From 7dca54f872004a71537500c5d5251ea80a63ae16 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 4 Feb 2013 15:23:17 +0100 Subject: xilinx: zynq: Enable DCC and create new zynq_dcc board Enable DCC driver for arm zynq platform to be compiled. Signed-off-by: Michal Simek diff --git a/boards.cfg b/boards.cfg index 98f7a14..1d30a18 100644 --- a/boards.cfg +++ b/boards.cfg @@ -296,6 +296,7 @@ snowball arm armv7 snowball st-e kzm9g arm armv7 kzm9g kmc rmobile armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile zynq arm armv7 zynq xilinx zynq +zynq_dcc arm armv7 zynq xilinx zynq zynq:ZYNQ_DCC socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 18fd76f..2989e72 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -58,6 +58,11 @@ #define CONFIG_ZYNQ_GEM #define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000 +#if defined(CONFIG_ZYNQ_DCC) +# define CONFIG_ARM_DCC +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#endif + #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY -- cgit v0.10.2 From 59c651f4e2b7614e97c2fda10eeabd00529dd740 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 4 Feb 2013 12:38:59 +0100 Subject: arm: zynq: Add SLCR support with system reset The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile index 499ace4..388085d 100644 --- a/arch/arm/cpu/armv7/zynq/Makefile +++ b/arch/arm/cpu/armv7/zynq/Makefile @@ -30,6 +30,7 @@ LIB = $(obj)lib$(SOC).o COBJS-y := timer.o COBJS-y += cpu.o +COBJS-y += slcr.o COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index ab615cc..91618d3 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -21,11 +21,13 @@ * MA 02111-1307 USA */ #include +#include inline void lowlevel_init(void) {} void reset_cpu(ulong addr) { + zynq_slcr_cpu_reset(); while (1) ; } diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c new file mode 100644 index 0000000..788a8fd --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define SLCR_LOCK_MAGIC 0x767B +#define SLCR_UNLOCK_MAGIC 0xDF0D + +static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ + +void zynq_slcr_lock(void) +{ + if (!slcr_lock) + writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); +} + +void zynq_slcr_unlock(void) +{ + if (slcr_lock) + writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); +} + +/* Reset the entire system */ +void zynq_slcr_cpu_reset(void) +{ + /* + * Unlock the SLCR then reset the system. + * Note that this seems to require raw i/o + * functions or there's a lockup? + */ + zynq_slcr_unlock(); + + /* + * Clear 0x0F000000 bits of reboot status register to workaround + * the FSBL not loading the bitstream after soft-reboot + * This is a temporary solution until we know more. + */ + clrbits_le32(&slcr_base->reboot_status, 0xF000000); + + writel(1, &slcr_base->pss_rst_ctrl); +} diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h new file mode 100644 index 0000000..ad17b27 --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define XPSS_SYS_CTRL_BASEADDR 0xF8000000 + +/* Reflect slcr offsets */ +struct slcr_regs { + u32 scl; /* 0x0 */ + u32 slcr_lock; /* 0x4 */ + u32 slcr_unlock; /* 0x8 */ + u32 reserved1[125]; + u32 pss_rst_ctrl; /* 0x200 */ + u32 reserved2[21]; + u32 reboot_status; /* 0x258 */ +}; + +#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR) + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h new file mode 100644 index 0000000..e788900 --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2013 Xilinx Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +extern void zynq_slcr_lock(void); +extern void zynq_slcr_unlock(void); +extern void zynq_slcr_cpu_reset(void); + +#endif /* _SYS_PROTO_H_ */ -- cgit v0.10.2 From 00ed34589880ca7092999ec5b92e061018d0fd0f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 4 Feb 2013 12:42:25 +0100 Subject: arm: zynq: Add lowlevel initialization to C Do lowlevel initialization directly in C. Zynq do not require to do it in asm. Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 91618d3..e8f4c19 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -21,9 +21,33 @@ * MA 02111-1307 USA */ #include +#include #include +#include -inline void lowlevel_init(void) {} +void lowlevel_init(void) +{ + zynq_slcr_unlock(); + /* remap DDR to zero, FILTERSTART */ + writel(0, &scu_base->filter_start); + + /* Device config APB, unlock the PCAP */ + writel(0x757BDF0D, &devcfg_base->unlock); + writel(0xFFFFFFFF, &devcfg_base->rom_shadow); + + /* OCM_CFG, Mask out the ROM, map ram into upper addresses */ + writel(0x1F, &slcr_base->ocm_cfg); + /* FPGA_RST_CTRL, clear resets on AXI fabric ports */ + writel(0x0, &slcr_base->fpga_rst_ctrl); + /* TZ_DDR_RAM, Set DDR trust zone non-secure */ + writel(0xFFFFFFFF, &slcr_base->trust_zone); + /* Set urgent bits with register */ + writel(0x0, &slcr_base->ddr_urgent_sel); + /* Urgent write, ports S2/S3 */ + writel(0xC, &slcr_base->ddr_urgent); + + zynq_slcr_lock(); +} void reset_cpu(ulong addr) { diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index ad17b27..d0c69da 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -24,6 +24,8 @@ #define _ASM_ARCH_HARDWARE_H #define XPSS_SYS_CTRL_BASEADDR 0xF8000000 +#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000 +#define XPSS_SCU_BASEADDR 0xF8F00000 /* Reflect slcr offsets */ struct slcr_regs { @@ -32,10 +34,52 @@ struct slcr_regs { u32 slcr_unlock; /* 0x8 */ u32 reserved1[125]; u32 pss_rst_ctrl; /* 0x200 */ - u32 reserved2[21]; + u32 reserved2[15]; + u32 fpga_rst_ctrl; /* 0x240 */ + u32 reserved3[5]; u32 reboot_status; /* 0x258 */ + u32 boot_mode; /* 0x25c */ + u32 reserved4[116]; + u32 trust_zone; /* 0x430 */ /* FIXME */ + u32 reserved5[115]; + u32 ddr_urgent; /* 0x600 */ + u32 reserved6[6]; + u32 ddr_urgent_sel; /* 0x61c */ + u32 reserved7[188]; + u32 ocm_cfg; /* 0x910 */ }; #define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR) +struct devcfg_regs { + u32 ctrl; /* 0x0 */ + u32 lock; /* 0x4 */ + u32 cfg; /* 0x8 */ + u32 int_sts; /* 0xc */ + u32 int_mask; /* 0x10 */ + u32 status; /* 0x14 */ + u32 dma_src_addr; /* 0x18 */ + u32 dma_dst_addr; /* 0x1c */ + u32 dma_src_len; /* 0x20 */ + u32 dma_dst_len; /* 0x24 */ + u32 rom_shadow; /* 0x28 */ + u32 reserved1[2]; + u32 unlock; /* 0x34 */ + u32 reserved2[18]; + u32 mctrl; /* 0x80 */ + u32 reserved3; + u32 write_count; /* 0x88 */ + u32 read_count; /* 0x8c */ +}; + +#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR) + +struct scu_regs { + u32 reserved1[16]; + u32 filter_start; /* 0x40 */ + u32 filter_end; /* 0x44 */ +}; + +#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ -- cgit v0.10.2 From 6904e377465db6c731adf4fb0eb67e55454606d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:13 +0000 Subject: imx: mx6q DDR3 init: Fix tMRD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3. For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns) Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5]. Signed-off-by: Benoît Thébaudeau Tested-by: Eric Nelson diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index c86cd40..9ac8027 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740 DATA 4 0x021b001c 0x00008000 DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 +DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -- cgit v0.10.2 From aa53149e1108ab9395ee8309ce6f90480bfdf34b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:14 +0000 Subject: imx: mx6q DDR3 init: Fix tXPR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR. For all DDR3 speed bins: tXPR(min) = max(5 nCK, tRFC(min) + 10 ns) tRFC(2 Gb) = 160 ns All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron MT41K128M16JT-125:K for i.MX6 SABRE SD). Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16]. Signed-off-by: Benoît Thébaudeau diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 9ac8027..1c24da8 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -DATA 4 0x021b0030 0x005B0E21 +DATA 4 0x021b0030 0x005A0E21 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027 -- cgit v0.10.2 From ada02b84636242f5142f74016dbedb50889e93d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:15 +0000 Subject: imx: mx6q DDR3 init: Fix SDE_to_RST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded as 0x10 for the bit-field MMDC1_MDOR[13:8]. Signed-off-by: Benoît Thébaudeau diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 1c24da8..73317b5 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -DATA 4 0x021b0030 0x005A0E21 +DATA 4 0x021b0030 0x005A1021 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027 -- cgit v0.10.2 From 1791b1f97f71bb4f110ca851ab10479640b7bc05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:16 +0000 Subject: imx: mx6q DDR3 init: Fix RST_to_CKE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0]. Signed-off-by: Benoît Thébaudeau diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 73317b5..51f8c35 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 -DATA 4 0x021b0030 0x005A1021 +DATA 4 0x021b0030 0x005A1023 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x00000027 -- cgit v0.10.2 From b42b5b7a243ab3923fd80ab03f950f036b6e1329 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:17 +0000 Subject: imx: mx6q DDR3 init: Fix MR0.PPD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28]. Signed-off-by: Benoît Thébaudeau diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 51f8c35..d50858d 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033 DATA 4 0x021b001c 0x0000803B DATA 4 0x021b001c 0x00428031 DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x09408030 -DATA 4 0x021b001c 0x09408038 +DATA 4 0x021b001c 0x19408030 +DATA 4 0x021b001c 0x19408038 DATA 4 0x021b001c 0x04008040 DATA 4 0x021b001c 0x04008048 -- cgit v0.10.2 From 7c92c540754a0c3756d467a9b0695f2a40d1fe86 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Wed, 30 Jan 2013 11:19:18 +0000 Subject: imx: mx6q DDR3 init: Benefit from available CL = 7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it. In these conditions: tRCD(min) = 13.125 ns tRP(min) = 13.125 ns tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min) tRAS(min, DDR3-1333H) = 36 ns tRAS(min, DDR3-1600K) = 35 ns MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG0[3:0]. MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18]. MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG1[2:0]. MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[31:29]. MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[28:26]. MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded as 0x1A in the bit-field MMDC1_MDCFG1[25:21]. Signed-off-by: Benoît Thébaudeau diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index d50858d..f4cae5e 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -109,8 +109,8 @@ DATA 4 0x021b4828 0x33333333 DATA 4 0x021b0018 0x00081740 DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538F64 +DATA 4 0x021b000c 0x555A7974 +DATA 4 0x021b0010 0xDB538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x000026D2 @@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033 DATA 4 0x021b001c 0x0000803B DATA 4 0x021b001c 0x00428031 DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x19408030 -DATA 4 0x021b001c 0x19408038 +DATA 4 0x021b001c 0x19308030 +DATA 4 0x021b001c 0x19308038 DATA 4 0x021b001c 0x04008040 DATA 4 0x021b001c 0x04008048 -- cgit v0.10.2 From 76c91e668a54a45fa06086d4044fcae0b6ce225a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 7 Feb 2013 06:45:23 +0000 Subject: mx6: Disable Power Down Bit of watchdog On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted and it is not able to reach the Linux prompt. Comparing the watchdog behaviour on a revB versus revC board: - On a mx6qsabresd revB: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: WDOG ... - On a mx6qsabresd revC: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR. Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and is also safe for all mx6 boards. Signed-off-by: Fabio Estevam Acked-by: Otavio Salvador Acked-by: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index a8aad5d..efe4136 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -30,6 +30,7 @@ #include #include #include +#include struct scu_regs { u32 ctrl; @@ -121,12 +122,23 @@ void set_vddsoc(u32 mv) writel(reg, &anatop->reg_core); } +static void imx_set_wdog_powerdown(bool enable) +{ + struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; + struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; + + /* Write to the PDE (Power Down Enable) bit */ + writew(enable, &wdog1->wmcr); + writew(enable, &wdog2->wmcr); +} + int arch_cpu_init(void) { init_aips(); set_vddsoc(1200); /* Set VDDSOC to 1.2V */ + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ return 0; } diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 3eb0081..eaa7439 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -601,5 +601,13 @@ struct iomuxc_base_regs { u32 daisy[104]; /* 0x7b0..94c */ }; +struct wdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Miscellaneous Control */ +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ -- cgit v0.10.2 From 291b3dcd496abab800078b1d3a105a24509b80d9 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 11 Feb 2013 04:33:51 +0000 Subject: build: imx: Fix 'u-boot.imx' build without full OBJTREE reference When calling 'make u-boot.imx' the build were failing as it were expecting the full path for the file; this regression has been included by commit 71a988a (imximage.cfg: run files through C preprocessor). The direct references for u-boot.imx were replaced by $(obj) as config.mk handles the proper setting of it making it set to $(OBJTREE) when required. The build has been test using: - ./MAKEALL -s mx5 -s mx6 - make u-boot.imx - make O=/tmp/build Signed-off-by: Otavio Salvador diff --git a/Makefile b/Makefile index f4a9b33..a8c7b7b 100644 --- a/Makefile +++ b/Makefile @@ -467,8 +467,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -d $< $@ -$(OBJTREE)/u-boot.imx : $(obj)u-boot.bin $(SUBDIR_TOOLS) depend - $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@ +$(obj)u-boot.imx: $(obj)u-boot.bin depend + $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx $(obj)u-boot.kwb: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 47f24f5..6a3a1bb 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -34,6 +34,6 @@ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) ifneq ($(CONFIG_IMX_CONFIG),) -ALL-y += $(OBJTREE)/u-boot.imx +ALL-y += $(obj)u-boot.imx endif diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 350e946..9c3e2f3 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -40,5 +40,5 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,) PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED) ifneq ($(CONFIG_IMX_CONFIG),) -ALL-y += $(OBJTREE)/u-boot.imx +ALL-y += $(obj)u-boot.imx endif -- cgit v0.10.2 From c4c25940b9bf61526862ec7f1d2e99141c3a4c0a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 28 Jan 2013 01:41:00 +0000 Subject: mx23evk: Remove CONFIG_SYS_BAUDRATE_TABLE The baudrate is already defined by CONFIG_BAUDRATE and there is no need to keep CONFIG_SYS_BAUDRATE_TABLE. Signed-off-by: Fabio Estevam Acked-by: Otavio Salvador diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index c44a8b8..31506ff 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -112,7 +112,6 @@ #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* DMA */ #define CONFIG_APBH_DMA -- cgit v0.10.2 From 2d7237c92f11242cc0c9d7aee84f2852c25c419b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 28 Jan 2013 01:41:01 +0000 Subject: mx23evk: Turn on caches It is safe to turn on data and instruction caches for mx23. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 31506ff..d206c95 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -33,8 +33,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_MISC_INIT -- cgit v0.10.2 From bec0160e9f5adab1d451ded3a95b0114b14e1970 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Fri, 1 Feb 2013 08:08:45 +0000 Subject: i.MX6Q: mx6qsabre*: Configure to allow CONFIG_SYS_ALT_MEMTEST In order to use the more thorough memory test, the macro CONFIG_SYS_MEMTEST_SCRATCH must be defined with a usable address. Signed-off-by: Eric Nelson diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h index d76357c..f7e8779 100644 --- a/include/configs/mx6qsabre_common.h +++ b/include/configs/mx6qsabre_common.h @@ -171,6 +171,7 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 752f098..c8c3ccc 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -241,6 +241,7 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 -- cgit v0.10.2 From 78ed94c8bc743b0a52060388fc9a1439606b71ac Mon Sep 17 00:00:00 2001 From: Tomas Novotny Date: Fri, 1 Feb 2013 06:44:06 +0000 Subject: da8xx: ea20: Add the configuration define for the exact SoC variant Signed-off-by: Tomas Novotny Cc: Tom Rini Cc: Stefano Babic Acked-by: Stefano Babic diff --git a/include/configs/ea20.h b/include/configs/ea20.h index d3eb596..03dfe0a 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -42,6 +42,7 @@ #define CONFIG_MACH_DAVINCI_DA850_EVM #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -- cgit v0.10.2 From b9f56698c7e9bf7ac773b5346c4f6886e214b69b Mon Sep 17 00:00:00 2001 From: Tomas Novotny Date: Fri, 1 Feb 2013 06:46:00 +0000 Subject: da8xx: Add the missing pinmux for da830 to the gpio driver The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of kernel version 3.7.5. If the driver is used for the da850, then SoC variant must be specified by CONFIG_SOC_DA850. Signed-off-by: Tomas Novotny Cc: Tom Rini diff --git a/arch/arm/include/asm/arch-davinci/gpio.h b/arch/arm/include/asm/arch-davinci/gpio.h index ef65ffb..fbbb1f3 100644 --- a/arch/arm/include/asm/arch-davinci/gpio.h +++ b/arch/arm/include/asm/arch-davinci/gpio.h @@ -67,7 +67,11 @@ struct davinci_gpio_bank { #define gpio_status() gpio_info() #define GPIO_NAME_SIZE 20 +#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) +#define MAX_NUM_GPIOS 128 +#else #define MAX_NUM_GPIOS 144 +#endif #define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5)) #define GPIO_BIT(gp) ((gp) & 0x1F) diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c index 84d2b77..271b8d9 100644 --- a/drivers/gpio/da8xx_gpio.c +++ b/drivers/gpio/da8xx_gpio.c @@ -33,6 +33,138 @@ static struct gpio_registry { #define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) +#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) +static const struct pinmux_config gpio_pinmux[] = { + { pinmux(13), 8, 6 }, /* GP0[0] */ + { pinmux(13), 8, 7 }, + { pinmux(14), 8, 0 }, + { pinmux(14), 8, 1 }, + { pinmux(14), 8, 2 }, + { pinmux(14), 8, 3 }, + { pinmux(14), 8, 4 }, + { pinmux(14), 8, 5 }, + { pinmux(14), 8, 6 }, + { pinmux(14), 8, 7 }, + { pinmux(15), 8, 0 }, + { pinmux(15), 8, 1 }, + { pinmux(15), 8, 2 }, + { pinmux(15), 8, 3 }, + { pinmux(15), 8, 4 }, + { pinmux(15), 8, 5 }, + { pinmux(15), 8, 6 }, /* GP1[0] */ + { pinmux(15), 8, 7 }, + { pinmux(16), 8, 0 }, + { pinmux(16), 8, 1 }, + { pinmux(16), 8, 2 }, + { pinmux(16), 8, 3 }, + { pinmux(16), 8, 4 }, + { pinmux(16), 8, 5 }, + { pinmux(16), 8, 6 }, + { pinmux(16), 8, 7 }, + { pinmux(17), 8, 0 }, + { pinmux(17), 8, 1 }, + { pinmux(17), 8, 2 }, + { pinmux(17), 8, 3 }, + { pinmux(17), 8, 4 }, + { pinmux(17), 8, 5 }, + { pinmux(17), 8, 6 }, /* GP2[0] */ + { pinmux(17), 8, 7 }, + { pinmux(18), 8, 0 }, + { pinmux(18), 8, 1 }, + { pinmux(18), 8, 2 }, + { pinmux(18), 8, 3 }, + { pinmux(18), 8, 4 }, + { pinmux(18), 8, 5 }, + { pinmux(18), 8, 6 }, + { pinmux(18), 8, 7 }, + { pinmux(19), 8, 0 }, + { pinmux(9), 8, 2 }, + { pinmux(9), 8, 3 }, + { pinmux(9), 8, 4 }, + { pinmux(9), 8, 5 }, + { pinmux(9), 8, 6 }, + { pinmux(10), 8, 1 }, /* GP3[0] */ + { pinmux(10), 8, 2 }, + { pinmux(10), 8, 3 }, + { pinmux(10), 8, 4 }, + { pinmux(10), 8, 5 }, + { pinmux(10), 8, 6 }, + { pinmux(10), 8, 7 }, + { pinmux(11), 8, 0 }, + { pinmux(11), 8, 1 }, + { pinmux(11), 8, 2 }, + { pinmux(11), 8, 3 }, + { pinmux(11), 8, 4 }, + { pinmux(9), 8, 7 }, + { pinmux(2), 8, 6 }, + { pinmux(11), 8, 5 }, + { pinmux(11), 8, 6 }, + { pinmux(12), 8, 4 }, /* GP4[0] */ + { pinmux(12), 8, 5 }, + { pinmux(12), 8, 6 }, + { pinmux(12), 8, 7 }, + { pinmux(13), 8, 0 }, + { pinmux(13), 8, 1 }, + { pinmux(13), 8, 2 }, + { pinmux(13), 8, 3 }, + { pinmux(13), 8, 4 }, + { pinmux(13), 8, 5 }, + { pinmux(11), 8, 7 }, + { pinmux(12), 8, 0 }, + { pinmux(12), 8, 1 }, + { pinmux(12), 8, 2 }, + { pinmux(12), 8, 3 }, + { pinmux(9), 8, 1 }, + { pinmux(7), 8, 3 }, /* GP5[0] */ + { pinmux(7), 8, 4 }, + { pinmux(7), 8, 5 }, + { pinmux(7), 8, 6 }, + { pinmux(7), 8, 7 }, + { pinmux(8), 8, 0 }, + { pinmux(8), 8, 1 }, + { pinmux(8), 8, 2 }, + { pinmux(8), 8, 3 }, + { pinmux(8), 8, 4 }, + { pinmux(8), 8, 5 }, + { pinmux(8), 8, 6 }, + { pinmux(8), 8, 7 }, + { pinmux(9), 8, 0 }, + { pinmux(7), 8, 1 }, + { pinmux(7), 8, 2 }, + { pinmux(5), 8, 1 }, /* GP6[0] */ + { pinmux(5), 8, 2 }, + { pinmux(5), 8, 3 }, + { pinmux(5), 8, 4 }, + { pinmux(5), 8, 5 }, + { pinmux(5), 8, 6 }, + { pinmux(5), 8, 7 }, + { pinmux(6), 8, 0 }, + { pinmux(6), 8, 1 }, + { pinmux(6), 8, 2 }, + { pinmux(6), 8, 3 }, + { pinmux(6), 8, 4 }, + { pinmux(6), 8, 5 }, + { pinmux(6), 8, 6 }, + { pinmux(6), 8, 7 }, + { pinmux(7), 8, 0 }, + { pinmux(1), 8, 0 }, /* GP7[0] */ + { pinmux(1), 8, 1 }, + { pinmux(1), 8, 2 }, + { pinmux(1), 8, 3 }, + { pinmux(1), 8, 4 }, + { pinmux(1), 8, 5 }, + { pinmux(1), 8, 6 }, + { pinmux(1), 8, 7 }, + { pinmux(2), 8, 0 }, + { pinmux(2), 8, 1 }, + { pinmux(2), 8, 2 }, + { pinmux(2), 8, 3 }, + { pinmux(2), 8, 4 }, + { pinmux(2), 8, 5 }, + { pinmux(0), 1, 0 }, + { pinmux(0), 1, 1 }, +}; +#else static const struct pinmux_config gpio_pinmux[] = { { pinmux(1), 8, 7 }, /* GP0[0] */ { pinmux(1), 8, 6 }, @@ -179,6 +311,7 @@ static const struct pinmux_config gpio_pinmux[] = { { pinmux(18), 8, 3 }, { pinmux(18), 8, 2 }, }; +#endif int gpio_request(unsigned gpio, const char *label) { -- cgit v0.10.2 From ff229ecf8b4e5379d32c74f0486c2285e2ee27d4 Mon Sep 17 00:00:00 2001 From: "robertcnelson@gmail.com" Date: Mon, 4 Feb 2013 06:03:10 +0000 Subject: beagle: expansion boards: retry i2c_read with 16bit addressing Some expansion boards now ship with at24 eeproms that need to communicate via 16bit addressing. Signed-off-by: Robert Nelson diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index b829a79..9493c6b 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -227,6 +227,14 @@ static unsigned int get_expansion_id(void) i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config, sizeof(expansion_config)); + /* retry reading configuration data with 16bit addressing */ + if ((expansion_config.device_vendor == 0xFFFFFF00) || + (expansion_config.device_vendor == 0xFFFFFFFF)) { + printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n"); + i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config, + sizeof(expansion_config)); + } + i2c_set_bus_num(TWL4030_I2C_BUS); return expansion_config.device_vendor; -- cgit v0.10.2 From 8a1f2dc0818771cfe5e5e6de97e6a0a8b0604062 Mon Sep 17 00:00:00 2001 From: "robertcnelson@gmail.com" Date: Mon, 4 Feb 2013 06:03:30 +0000 Subject: beagle: expansion boards: add LSR COM6L adapter http://www.lsr.com/wireless-products/com6l The eeprom on this expansion board requires 16bit addressing. Signed-off-by: Robert Nelson diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 9493c6b..58bd556 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -72,6 +72,7 @@ #define BBTOYS_LCD 0x03000B00 #define BCT_BRETTL3 0x01000F00 #define BCT_BRETTL4 0x02000F00 +#define LSR_COM6L_ADPT 0x01001300 #define BEAGLE_NO_EEPROM 0xffffffff DECLARE_GLOBAL_DATA_PTR; @@ -462,6 +463,11 @@ int misc_init_r(void) case BCT_BRETTL4: printf("Recognized bct electronic GmbH brettl4 board\n"); break; + case LSR_COM6L_ADPT: + printf("Recognized LSR COM6L Adapter Board\n"); + MUX_BBTOYS_WIFI() + setenv("buddy", "lsr-com6l-adpt"); + break; case BEAGLE_NO_EEPROM: printf("No EEPROM on expansion board\n"); setenv("buddy", "none"); -- cgit v0.10.2 From 9648865d5eba4478398051b59610992bd698fb5a Mon Sep 17 00:00:00 2001 From: Lars Poeschel Date: Mon, 4 Feb 2013 23:13:58 +0000 Subject: am33xx: pcm051: Remove wp pin mux for sd-card The pcm051 does not have the wp pin connected to the sd-card socket. Therefore remove the pinmux for the pin. The was a carry-over from the am335x evm code. Signed-off-by: Lars Poeschel diff --git a/board/phytec/pcm051/mux.c b/board/phytec/pcm051/mux.c index 4d3a1d5..6e9c3d2 100644 --- a/board/phytec/pcm051/mux.c +++ b/board/phytec/pcm051/mux.c @@ -35,7 +35,6 @@ static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ - {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ {-1}, }; -- cgit v0.10.2 From 62a814310e4794a1218d0057142cf57349924a1c Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Tue, 5 Feb 2013 11:36:24 +0000 Subject: spl: support for booting via usbeth In case of usbeth booting just call net_load_image("usb_ether"). This patch also adds CONFIG_SPL_USBETH_SUPPORT and CONFIG_SPL_MUSB_NEW_SUPPORT config options to enable linking of SPL against USB gagdet support and new MUSB driver resp. Signed-off-by: Ilya Yanok diff --git a/common/spl/spl.c b/common/spl/spl.c index ff9ba7b..6a5a136 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -221,6 +221,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) #endif break; #endif +#ifdef CONFIG_SPL_USBETH_SUPPORT + case BOOT_DEVICE_USBETH: + spl_net_load_image("usb_ether"); + break; +#endif default: debug("SPL: Un-supported Boot Device\n"); hang(); diff --git a/spl/Makefile b/spl/Makefile index 101d478..aac6146 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -81,6 +81,8 @@ LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o +LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o +LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o -- cgit v0.10.2 From da07c21b77aaa4633caffb804aad23a809c233b4 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Tue, 5 Feb 2013 11:36:25 +0000 Subject: am33xx: support for booting via usbeth This patch adds BOOT_DEVICE define for USB booting and fixes spl_board_init function to call arch_misc_init (this is the place there musb is initialized). Signed-off-by: Ilya Yanok diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 2b584e0..1c8b617 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -55,6 +55,9 @@ void spl_board_init(void) #ifdef CONFIG_SPL_NAND_SUPPORT gpmc_init(); #endif +#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) + arch_misc_init(); +#endif } int board_mmc_init(bd_t *bis) diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 644ff35..e961ce0 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -29,6 +29,7 @@ #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #define BOOT_DEVICE_SPI 11 #define BOOT_DEVICE_UART 65 +#define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF #endif -- cgit v0.10.2 From c0e66793c4af8f6a50fa236ab14ff4de7e31d01a Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Tue, 5 Feb 2013 11:36:26 +0000 Subject: am335x_evm: enable support for booting via USB This adds necessary config options and a new build target, am335x_evm_usbspl, to enable usb booting and fixes board_eth_init() function to take into account that we may have USB ether support in SPL now. This uses the same MAC for both cpsw and USB, in order to match ROM behavior. The usbspl build target does not contain UART SPL, CPSW SPL or extra environment settings, so that we may fit within our binary size constraint. Signed-off-by: Ilya Yanok Signed-off-by: Tom Rini diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 48e6896..441758f 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -389,7 +389,8 @@ int board_late_init(void) } #endif -#ifdef CONFIG_DRIVER_TI_CPSW +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) static void cpsw_control(int enabled) { /* VTP can be added here */ @@ -434,26 +435,26 @@ static struct cpsw_platform_data cpsw_data = { int board_eth_init(bd_t *bis) { int rv, n = 0; -#ifdef CONFIG_DRIVER_TI_CPSW uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; - if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { - printf(" not set. Reading from E-fuse\n"); - /* try reading mac address from efuse */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf(" not set. Validating first E-fuse MAC\n"); if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); - else - goto try_usbether; } if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { @@ -494,8 +495,11 @@ int board_eth_init(bd_t *bis) AR8051_RGMII_TX_CLK_DLY); } #endif -try_usbether: -#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_USB_ETHER) && \ + (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("usbnet_devaddr", mac_addr); + rv = usb_eth_initialize(bis); if (rv < 0) printf("Error %d registering USB_ETHER\n", rv); diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 33ee2c4..4549190 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -239,6 +239,7 @@ #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SPL_MUSB_NEW_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT @@ -312,8 +313,21 @@ #ifdef CONFIG_MUSB_GADGET #define CONFIG_USB_ETHER #define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" #endif /* CONFIG_MUSB_GADGET */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* + * Disable UART, CPSW ethernet support and extra environment settings so we + * will fit within 101KiB. + */ +#undef CONFIG_SPL_ETH_SUPPORT +#undef CONFIG_SPL_YMODEM_SUPPORT +#undef CONFIG_EXTRA_ENV_SETTINGS +#endif + /* Unsupported features */ #undef CONFIG_USE_IRQ -- cgit v0.10.2 From 4c21b4c4adc1f84a58d17448c95259649d08d905 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 7 Feb 2013 00:40:04 +0000 Subject: OMAP3: igep00x0: use official board names. This trivial patch only changes current boards names for the official names. Signed-off-by: Enric Balletbo i Serra diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index ea1e9ac..9fcaab5 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -34,10 +34,10 @@ const omap3_sysinfo sysinfo = { DDR_STACKED, #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) - "OMAP3 IGEP v2 board", + "IGEPv2", #endif #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) - "OMAP3 IGEP COM Module", + "IGEP COM MODULE/ELECTRON", #endif #if defined(CONFIG_ENV_IS_IN_ONENAND) "ONENAND", -- cgit v0.10.2 From aa127df60ecf5ab1450936902e3374d5a92bd0fb Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 7 Feb 2013 00:40:05 +0000 Subject: OMAP3: igep00x0: add missing include mach-types.h Current '#if' directives (used in igep00x0.h config file) comparing MACH_TYPE values in igep00x0.h doesn't work as expected. The comparision between CONFIG_MACH_TYPE and MACH_TYPE_IGEP0020 is always true independent of the IGEP machine configured. For example, following directive if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) define something endif Is always evaluated true although we configure u-boot for MACH_TYPE_IGEP0030. The build doesn't shows any error so looks that both defines had always the same value. Including the mach-types.h file sets properly the value of MACH_TYPE_IGEPxxxx. Signed-off-by: Enric Balletbo i Serra diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 0e7f924..0e539ef 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -36,6 +36,7 @@ #include #include +#include /* * Display CPU and Board information -- cgit v0.10.2 From d9aacf4190136225763407a4c1ce2dccd30edf5e Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 7 Feb 2013 00:40:06 +0000 Subject: OMAP3: igep00x0: Add new IGEP COM PROTON. The IGEP COM PROTON is a new ultra compact module design with an on-board ethernet controller. Signed-off-by: Enric Balletbo i Serra diff --git a/MAINTAINERS b/MAINTAINERS index 45e2dd4..175bbe2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -607,6 +607,7 @@ Enric Balletbo i Serra igep0020 ARM ARMV7 (OMAP3xx SoC) igep0030 ARM ARMV7 (OMAP3xx SoC) + igep0032 ARM ARMV7 (OMAP3xx SoC) Eric Benard diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index 9fcaab5..5ef22ae 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -39,6 +39,9 @@ const omap3_sysinfo sysinfo = { #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) "IGEP COM MODULE/ELECTRON", #endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) + "IGEP COM PROTON", +#endif #if defined(CONFIG_ENV_IS_IN_ONENAND) "ONENAND", #else diff --git a/boards.cfg b/boards.cfg index b1319aa..beefb53 100644 --- a/boards.cfg +++ b/boards.cfg @@ -262,6 +262,7 @@ igep0020 arm armv7 igep00x0 isee igep0020_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND +igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND am3517_evm arm armv7 am3517evm logicpd omap3 mt_ventoux arm armv7 mt_ventoux teejet omap3 omap3_zoom1 arm armv7 zoom1 logicpd omap3 diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 0e539ef..559e375 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -87,7 +87,10 @@ #define CONFIG_DOS_PARTITION 1 /* define to enable boot progress via leds */ +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ + (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) #define CONFIG_SHOW_BOOT_PROGRESS +#endif /* USB */ #define CONFIG_MUSB_UDC 1 @@ -119,7 +122,8 @@ #ifdef CONFIG_BOOT_NAND #define CONFIG_CMD_NAND #endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ + (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #endif #define CONFIG_CMD_DHCP -- cgit v0.10.2 From 661bb0f8f49303891b8460149943e32337544e03 Mon Sep 17 00:00:00 2001 From: Howard Gray Date: Thu, 7 Feb 2013 23:53:35 +0000 Subject: omap3: mvblx: change console to ttyO0 and make silent by default. Also, change bootdelay to 0 but allow pressing 'S' to stop at U-Boot prompt. Signed-off-by: Michael Jones Signed-off-by: Howard Gray Signed-off-by: Michael Jones diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 07de565..99f0d4b 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -90,9 +90,9 @@ /* * select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 /* UART3 */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ @@ -102,6 +102,10 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 +/* silent console by default */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 +#define CONFIG_SILENT_CONSOLE 1 + /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 @@ -152,12 +156,16 @@ /* Environment information */ #undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */ -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 0 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "S" #define CONFIG_EXTRA_ENV_SETTINGS \ + "silent=true\0" \ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ - "console=ttyO2,115200n8\0" \ + "console=ttyO0,115200n8\0" \ "mpurate=600\0" \ "vram=12M\0" \ "dvimode=1024x768-24@60\0" \ -- cgit v0.10.2 From 71c4ae3f6db39b888497923573bff215b64a36bd Mon Sep 17 00:00:00 2001 From: Michael Jones Date: Thu, 7 Feb 2013 23:53:36 +0000 Subject: omap3: mvblx: select fpgafilename according to orientation Rather than load the FPGA file from the FAT partition, look at entry in system EEPROM to decide which file to retrieve directly from the EXT3 partition. Signed-off-by: Michael Jones diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c index 945a36d..15269c6 100644 --- a/board/matrix_vision/mvblx/sys_eeprom.c +++ b/board/matrix_vision/mvblx/sys_eeprom.c @@ -326,10 +326,28 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +static inline int is_portrait(void) +{ + int i; + unsigned int orient_index = 0; /* idx of char which determines orientation */ + + for (i = sizeof(e.id)/sizeof(*e.id) - 1; i>=0; i--) { + if (e.id[i] == '-') { + orient_index = i+1; + break; + } + } + + return (orient_index && + (e.id[orient_index] >= '5') && (e.id[orient_index] <= '8')); +} + int mac_read_from_eeprom(void) { u32 crc, crc_offset = offsetof(struct eeprom, crc); u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ +#define FILENAME_LANDSCAPE "mvBlueLynx_X.rbf" +#define FILENAME_PORTRAIT "mvBlueLynx_X_sensor_cd.rbf" if (read_eeprom()) { printf("EEPROM Read failed.\n"); @@ -374,6 +392,12 @@ int mac_read_from_eeprom(void) setenv("serial#", serial_num); } + /* decide which fpga file to load depending on orientation */ + if (is_portrait()) + setenv("fpgafilename", FILENAME_PORTRAIT); + else + setenv("fpgafilename", FILENAME_LANDSCAPE); + /* TODO should I calculate CRC here? */ return 0; } diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 99f0d4b..7bb05ca 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -170,9 +170,9 @@ "vram=12M\0" \ "dvimode=1024x768-24@60\0" \ "defaultdisplay=dvi\0" \ - "fpgafilename=mvbluelynx_x.rbf\0" \ - "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \ - "fpga load 0 ${loadaddr} ${filesize}; " \ + "loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\ + "/lib/firmware/mvblx/${fpgafilename}; then " \ + "fpga load 0 ${loadaddr} ${filesize}; " \ "fi;\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ -- cgit v0.10.2 From bb4d46455c017e40e2c5d78ad78465a270565f9e Mon Sep 17 00:00:00 2001 From: Michael Jones Date: Thu, 7 Feb 2013 23:53:37 +0000 Subject: omap3: mvblx: pass FPGA version to the kernel Extract FPGA version from the .rbf and pass this info to the kernel. Signed-off-by: Michael Jones diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c index dacc138..3fcf968 100644 --- a/board/matrix_vision/mvblx/fpga.c +++ b/board/matrix_vision/mvblx/fpga.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "fpga.h" #ifdef FPGA_DEBUG @@ -209,9 +210,20 @@ int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) { unsigned char *data = (unsigned char *) buf; int i; + int headerlen = len - cyclone2.size; + + if (headerlen < 0) + return FPGA_FAIL; + else if (headerlen == sizeof(uint32_t)) { + const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */ + char fpgavers_str[fpgavers_len]; + snprintf(fpgavers_str, fpgavers_len, "0x%08x", + be32_to_cpup((uint32_t*)data)); + setenv("fpgavers", fpgavers_str); + } fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) + for (i = headerlen; i < len; i++) _write_fpga(data[i]); fpga_debug("-%s\n", __func__); diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 7bb05ca..376a3d0 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -185,6 +185,7 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype} " \ + "mvfw.fpgavers=${fpgavers} " \ "${cmdline_suffix}\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ "importbootenv=echo Importing environment from mmc ...; " \ -- cgit v0.10.2 From 73c1f4aff04dd468963457250e36048fb6ec2e14 Mon Sep 17 00:00:00 2001 From: Chase Maupin Date: Fri, 8 Feb 2013 11:20:11 +0000 Subject: am335x_evm: Add NAND environment variables * Added support to the default environment variables for NAND boot. * Add nandboot to the default bootcmd. Signed-off-by: Chase Maupin Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 4549190..77bd734 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -61,12 +61,20 @@ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandsrcaddr=0x280000\0" \ + "nandimgsize=0x500000\0" \ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ @@ -81,6 +89,10 @@ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ + "bootm ${loadaddr}\0" \ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ "bootm ${loadaddr}\0" \ @@ -106,6 +118,8 @@ "if run loaduimage; then " \ "run mmcboot;" \ "fi;" \ + "else " \ + "run nandboot;" \ "fi;" \ /* Clock Defines */ -- cgit v0.10.2 From 63ba7c66d9f56e6e9ab82dab9b8e819c3a1f6f22 Mon Sep 17 00:00:00 2001 From: Chase Maupin Date: Fri, 8 Feb 2013 11:20:12 +0000 Subject: am335x_evm: Add SPI environment variables * Added variables to support SPI booting * Note that the first 512KiB are reserved for 4 copies of SPL. Signed-off-by: Chase Maupin Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 77bd734..54707d4 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -75,6 +75,15 @@ "${optargs} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ + "spiroot=/dev/mtdblock4 rw\0" \ + "spirootfstype=jffs2\0" \ + "spisrcaddr=0xe0000\0" \ + "spiimgsize=0x362000\0" \ + "spibusno=0\0" \ + "spiargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${spiroot} " \ + "rootfstype=${spirootfstype}\0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ @@ -93,6 +102,11 @@ "run nandargs; " \ "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ "bootm ${loadaddr}\0" \ + "spiboot=echo Booting from spi ...; " \ + "run spiargs; " \ + "sf probe ${spibusno}:0; " \ + "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ + "bootm ${loadaddr}\0" \ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ "bootm ${loadaddr}\0" \ -- cgit v0.10.2 From abdd178dc348df193470e19b431affec9a457987 Mon Sep 17 00:00:00 2001 From: Chase Maupin Date: Fri, 8 Feb 2013 11:20:13 +0000 Subject: am335x_evm: Add NET environment variables * Add environment variables to support network booting Signed-off-by: Chase Maupin Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 54707d4..259d01e 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -65,6 +65,10 @@ "nandrootfstype=ubifs rootwait=1\0" \ "nandsrcaddr=0x280000\0" \ "nandimgsize=0x500000\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ @@ -84,6 +88,11 @@ "${optargs} " \ "root=${spiroot} " \ "rootfstype=${spirootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ @@ -107,6 +116,12 @@ "sf probe ${spibusno}:0; " \ "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ "bootm ${loadaddr}\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "run netargs; " \ + "bootm ${loadaddr}\0" \ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ "bootm ${loadaddr}\0" \ -- cgit v0.10.2 From 427ac8cca34516c9e3845fee40d7fbd6f3293aec Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Fri, 8 Feb 2013 11:20:14 +0000 Subject: doc/SPL/README.am335x-network: Document using ethernet (and USB) SPL Added README file with the description of required options and host configuration to use network SPL with am335x targets. Briefly discuss how to use this configuration to program empty boards. Signed-off-by: Ilya Yanok Signed-off-by: Tom Rini diff --git a/doc/SPL/README.am335x-network b/doc/SPL/README.am335x-network new file mode 100644 index 0000000..e5a198f --- /dev/null +++ b/doc/SPL/README.am335x-network @@ -0,0 +1,92 @@ +USING AM335x NETBOOT FEATURE + + Some boards (like TI AM335x based ones) have quite big on-chip RAM and +have support for booting via network in ROM. The following describes +how to setup network booting and then optionally use this support to flash +NAND and bricked (empty) board with only a network cable. + + I. Building the required images + 1. You have to enable generic SPL configuration options (see +docs/README.SPL) as well as CONFIG_SPL_NET_SUPPORT, +CONFIG_ETH_SUPPORT, CONFIG_SPL_LIBGENERIC_SUPPORT and +CONFIG_SPL_LIBCOMMON_SUPPORT in your board configuration file to build +SPL with support for booting over the network. Also you have to enable +the driver for the NIC used and CONFIG_SPL_BOARD_INIT option if your +board needs some board-specific initialization (TI AM335x EVM does). +If you want SPL to use some Vendor Class Identifier (VCI) you can set +one with CONFIG_SPL_NET_VCI_STRING option. am335x_evm configuration +comes with support for network booting preconfigured. + 2. Define CONFIG_BOOTCOMMAND for your board to load and run debrick +script after boot: +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "bootp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +(Or create additional board configuration with such option). + 3. Build U-Boot as usual + $ make + You will need u-boot.img and spl/u-boot.bin images to perform +network boot. Copy them to u-boot-restore.img and +u-boot-spl-restore.bin respectively to distinguish this version +(with automatic restore running) from the main one. + + II. Host configuration. + 1. Setup DHCP server (recommended server is ISC DHCPd). + - Install DHCP server and setup it to listen on the interface you +chose to connect to the board (usually configured in +/etc/default/dhcpd or /etc/default/isc-dhcp-server). Make sure there +are no other active DHCP servers in the same network segment. + - Edit your dhcpd.conf and subnet declaration matching the address +on the interface. Specify the range of assigned addresses and bootfile +to use. IMPORTANT! Both RBL and SPL use the image filename provided +in the BOOTP reply but obviously they need different images (RBL needs +raw SPL image -- u-boot-spl-restore.bin while SPL needs main U-Boot +image -- u-boot-restore.img). So you have to configure DHCP server to +provide different image filenames to RBL and SPL (and possibly another +one to main U-Boot). This can be done by checking Vendor Class +Identifier (VCI) set by BOOTP client (RBL sets VCI to "DM814x ROM v1.0" +and you can set VCI used by SPL with CONFIG_SPL_NET_VCI_STRING option, +see above). + - If you plan to use TFTP server on another machine you have to set +server-name option to point to it. + - Here is sample configuration for ISC DHCPd, assuming the interface +used to connect to the board is eth0, and it has address 192.168.8.1: + +subnet 192.168.8.0 netmask 255.255.255.0 { + range dynamic-bootp 192.168.8.100 192.168.8.199; + + if substring (option vendor-class-identifier, 0, 10) = "DM814x ROM" { + filename "u-boot-spl-restore.bin"; + } elsif substring (option vendor-class-identifier, 0, 17) = "AM335x U-Boot SPL" { + filename "u-boot-restore.img"; + } else { + filename "uImage"; + } +} + + 2. Setup TFTP server. + Install TFTP server and put image files to it's root directory +(likely /tftpboot or /var/lib/tftpboot or /srv/tftp). You will need +u-boot.img and spl/u-boot-spl-bin files from U-Boot build directory. + + III. Reflashing (debricking) the board. + 1. Write debrick script. You will need to write a script that will +be executed after network boot to perform actual rescue actions. You +can use usual U-Boot commands from this script: tftp to load additional +files, nand erase/nand write to erase/write the NAND flash. + + 2. Create script image from your script. From U-Boot build directory: + +$ ./tools/mkimage -A arm -O U-Boot -C none -T script -d debrick.scr + +This will create debrick.scr file with your script inside. + + 3. Copy debrick.scr to TFTP root directory. You also need to copy +there all the files your script tries to load via TFTP. Example script +loads u-boot.img and MLO. You have to create these files doing regular +(not restore_flash) build and copy them to tftpboot directory. + + 4. Boot the board from the network, U-Boot will load debrick script +and run it after boot. -- cgit v0.10.2 From 4adfcd68cc10449e2fda0f9fac8b09f2b5c09a02 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 8 Feb 2013 11:20:15 +0000 Subject: am335x evm: Add am335x_evm_spiboot target This target will move the environment into SPI flash and documents the expected layout. We correct the SPL define for where U-Boot is and remove an unused define. Signed-off-by: Tom Rini diff --git a/boards.cfg b/boards.cfg index beefb53..5766f86 100644 --- a/boards.cfg +++ b/boards.cfg @@ -233,6 +233,7 @@ integratorap_cm946es arm arm946es integrator armltd integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES ca9x4_ct_vxp arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 +am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 259d01e..0dc2a50 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -280,8 +280,7 @@ #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 #define CONFIG_SPL_MUSB_NEW_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" @@ -371,6 +370,26 @@ #undef CONFIG_EXTRA_ENV_SETTINGS #endif +/* + * Default to using SPI for environment, etc. We have multiple copies + * of SPL as the ROM will check these locations. + * 0x0 - 0x20000 : First copy of SPL + * 0x20000 - 0x40000 : Second copy of SPL + * 0x40000 - 0x60000 : Third copy of SPL + * 0x60000 - 0x80000 : Fourth copy of SPL + * 0x80000 - 0xDF000 : U-Boot + * 0xDF000 - 0xE0000 : U-Boot Environment + * 0xE0000 - 0x442000 : Linux Kernel + * 0x442000 - 0x800000 : Userland + */ +#if defined(CONFIG_SPI_BOOT) +# undef CONFIG_ENV_IS_NOWHERE +# define CONFIG_ENV_IS_IN_SPI_FLASH +# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ +# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#endif /* SPI support */ + /* Unsupported features */ #undef CONFIG_USE_IRQ @@ -403,10 +422,12 @@ /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#if !defined(CONFIG_SPI_BOOT) #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ #endif +#endif #endif /* ! __CONFIG_AM335X_EVM_H */ -- cgit v0.10.2 From 8495faf525be9a8c7c8d608200e8795c2f7b9290 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Tue, 29 Jan 2013 15:43:26 +0000 Subject: ARM: atmel: add at91sam9g20ek_2mmc nand boot support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add at91sam9g20_2mmc nand boot support. on this board, there is no dataflash, so disable it change one commet for at91sam9g20ek board Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 2555672..3aa394a 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -157,13 +157,18 @@ int board_early_init_f(void) int board_init(void) { +#ifdef CONFIG_AT91SAM9G20EK_2MMC + /* arch number of AT91SAM9G20EK_2MMC-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK_2MMC; +#else #ifdef CONFIG_AT91SAM9G20EK - /* arch number of AT91SAM9260EK-Board */ + /* arch number of AT91SAM9G20EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK; #else /* arch number of AT91SAM9260EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK; #endif +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/boards.cfg b/boards.cfg index b1319aa..32b0ccf 100644 --- a/boards.cfg +++ b/boards.cfg @@ -95,6 +95,7 @@ at91sam9g10ek_nandflash arm arm926ejs at91sam9261ek atmel at91sam9g20ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 at91sam9g20ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 at91sam9g20ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH +at91sam9g20ek_2mmc_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index f921fac..02696b3 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -126,6 +126,7 @@ #endif /* DataFlash */ +#ifndef CONFIG_AT91SAM9G20EK_2MMC #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) @@ -133,6 +134,7 @@ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ #define AT91_SPI_CLK 15000000 +#endif #ifdef CONFIG_AT91SAM9G20EK #define DATAFLASH_TCSS (0x22 << 16) -- cgit v0.10.2 From 85dafbb8bfe4144f346f4a76771fb690905a1e02 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Feb 2013 14:35:35 +0000 Subject: common: cmd_sata: Fix usage text for 'sata init' Currently sata usage text prints a double 'sata' for the init command. MX53LOCO U-Boot > sata sata - SATA sub system Usage: sata sata init - init SATA sub system sata info - show available SATA devices sata device [dev] - show or set current device sata part [dev] - print partition table sata read addr blk# cnt sata write addr blk# cnt Remove the extra 'sata' from the 'sata init' line. Signed-off-by: Fabio Estevam diff --git a/common/cmd_sata.c b/common/cmd_sata.c index b401bd1..8d57285 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -196,7 +196,7 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( sata, 5, 1, do_sata, "SATA sub system", - "sata init - init SATA sub system\n" + "init - init SATA sub system\n" "sata info - show available SATA devices\n" "sata device [dev] - show or set current device\n" "sata part [dev] - print partition table\n" -- cgit v0.10.2 From 11da5d821324991f1e6a79bde1a0908ffb9bcf36 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 29 Nov 2012 02:53:28 +0000 Subject: README.scrapyard: add missing commit IDs Now that the patches have made it into mainline, we can also add the commit IDs. Signed-off-by: Wolfgang Denk diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 2b868e6..185bd0e 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -9,83 +9,83 @@ maintain a list of such former fellows, so archeologists can check easily if here is something they might want to dig for... -Board Arch CPU removed Commit last known maintainer/contact -============================================================================= -AMX860 powerpc mpc860 - - Wolfgang Denk -c2mon powerpc mpc855 - - Wolfgang Denk -ETX094 powerpc mpc850 - - Wolfgang Denk -IAD210 powerpc mpc860 - - - -LANTEC powerpc mpc850 - - Wolfgang Denk -SCM powerpc mpc8260 - - Wolfgang Grandegger -SX1 arm arm925t - - -TQM85xx powerpc MPC85xx d923a5d5 2012-10-04 Stefan Roese -apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park -tb0229 mips mips32 3f3110d 2011-12-12 -rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk -OXC powerpc MPC8240 309a292 2011-12-07 -BAB7xx powerpc MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling -xm250 arm pxa c746cdd 2011-25-11 -pleb2 arm pxa b185a1c 2011-25-11 -cradle arm pxa 4e24f8a 2011-25-11 Kyle Harris -cerf250 arm pxa a3f1241 2011-25-11 Prakash Kumar -mpq101 powerpc mpc85xx e877fab 2011-10-23 Alex Dubov -ixdpg425 arm ixp 0ca8eb7 2011-09-22 Stefan Roese -ixdp425 arm ixp 0ca8eb7 2011-09-22 Kyle Harris -zylonite arm pxa b66521a 2011-09-05 -shannon arm sa1100 5df092d 2011-09-05 Rolf Offermanns -modnet50 arm arm720t 9c62815 2011-09-05 Thomas Elste -lpc2292sodimm arm arm720t d1a067a 2011-09-05 -lart arm sa1100 3d57573 2011-09-05 Alex Züpke -impa7 arm arm720t c1f8750 2011-09-05 Marius Gröger -gcplus arm sa1100 2c650e2 2011-09-05 George G. Davis -evb4510 arm arm720t 26e670e 2011-09-05 Curt Brune -ep7312 arm arm720t c8f63b4 2011-09-05 Marius Gröger -dnp1110 arm sa1100 fc5e5ce 2011-09-05 Alex Züpke -SMN42 arm arm720t 6aac646 2011-09-05 -at91rm9200dk arm arm920t 1c85752 2011-07-17 -m501sk arm arm920t b1a2bd4 2011-07-17 -kb9202 arm arm920t 5bd3814 2011-07-17 -csb637 arm arm920t d14af08 2011-07-17 -cmc_pu2 arm arm920t 37a9b4d 2011-07-17 -at91cap9adk arm arm926ejs b550834 2011-07-17 Stelian Pop -voiceblue arm arm925t 1b793a4 2011-07-17 -smdk2400 arm arm920t ad218a8 2011-07-17 Gary Jennejohn -sbc2410x arm arm920t 1f7f0ed 2011-07-17 -netstar arm arm925t 6ea2405 2011-07-17 -mx1fs2 arm arm920t 6962419 2011-07-17 -lpd7a404 arm lh7a40x 957731e 2011-07-17 -edb9301 arm arm920t 716f7ad 2011-07-17 -edb9302 arm arm920t 716f7ad 2011-07-17 -edb9302a arm arm920t 716f7ad 2011-07-17 -edb9307 arm arm920t 716f7ad 2011-07-17 -edb9307a arm arm920t 716f7ad 2011-07-17 -edb9312 arm arm920t 716f7ad 2011-07-17 -edb9315 arm arm920t 716f7ad 2011-07-17 -edb9315a arm arm920t 716f7ad 2011-07-17 -B2 arm s3c44b0 5dcf536 2011-07-16 Andrea Scian -armadillo arm arm720t be28857 2011-07-16 Rowel Atienza -assabet arm sa1100 c91e90d 2011-07-16 George G. Davis -trab arm S3C2400 566e5cf 2011-05-01 Gary Jennejohn -xsengine ARM PXA2xx 4262a7c 2010-10-20 -wepep250 ARM PXA2xx 7369478 2010-10-20 Peter Figuli -delta ARM PXA2xx 75e2035 2010-10-20 -mp2usb ARM AT91RM2900 ee986e2 2011-01-25 Eric Bénard -barco powerpc MPC8245 afaa27b 2010-11-23 Marc Leeman -ERIC powerpc 405GP d9ba451 2010-11-21 Swen Anderson -VoVPN-GW_100MHz powerpc MPC8260 26fe3d2 2010-10-24 Juergen Selent -NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk -CP850 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk -logodl ARM PXA2xx 059e778 2010-10-18 August Hoeraendl -CCM powerpc MPC860 dff07e1 2010-10-06 Wolfgang Grandegger -PCU_E powerpc MPC860T 544d97e 2010-10-06 Wolfgang Denk -spieval powerpc MPC5200 69434e4 2010-09-19 -smmaco4 powerpc MPC5200 9ddc3af 2010-09-19 -HMI10 powerpc MPC823 77efe35 2010-09-19 Wolfgang Denk -GTH powerpc MPC860 0fe247b 2010-07-17 Thomas Lange -AmigaOneG3SE 953b7e6 2010-06-23 -suzaku microblaze 4f18060 2009-10-03 Yasushi Shoji -XUPV2P microblaze 8fab49e 2008-12-10 Michal Simek -MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwarz -adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi -R5200 ColdFire 48ead7a 2008-03-31 Zachary P. Landau -CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs +Board Arch CPU Commit Removed Last known maintainer/contact +================================================================================================= +AMX860 powerpc mpc860 1b0757e 2012-10-28 Wolfgang Denk +c2mon powerpc mpc855 1b0757e 2012-10-28 Wolfgang Denk +ETX094 powerpc mpc850 1b0757e 2012-10-28 Wolfgang Denk +IAD210 powerpc mpc860 1b0757e 2012-10-28 - +LANTEC powerpc mpc850 1b0757e 2012-10-28 Wolfgang Denk +SCM powerpc mpc8260 1b0757e 2012-10-28 Wolfgang Grandegger +SX1 arm arm925t 53c4154 2012-10-26 +TQM85xx powerpc MPC85xx d923a5d 2012-10-04 Stefan Roese +apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park +tb0229 mips mips32 3f3110d 2011-12-12 +rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk +OXC powerpc MPC8240 309a292 2011-12-07 +BAB7xx powerpc MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling +xm250 arm pxa c746cdd 2011-25-11 +pleb2 arm pxa b185a1c 2011-25-11 +cradle arm pxa 4e24f8a 2011-25-11 Kyle Harris +cerf250 arm pxa a3f1241 2011-25-11 Prakash Kumar +mpq101 powerpc mpc85xx e877fab 2011-10-23 Alex Dubov +ixdpg425 arm ixp 0ca8eb7 2011-09-22 Stefan Roese +ixdp425 arm ixp 0ca8eb7 2011-09-22 Kyle Harris +zylonite arm pxa b66521a 2011-09-05 +shannon arm sa1100 5df092d 2011-09-05 Rolf Offermanns +modnet50 arm arm720t 9c62815 2011-09-05 Thomas Elste +lpc2292sodimm arm arm720t d1a067a 2011-09-05 +lart arm sa1100 3d57573 2011-09-05 Alex Züpke +impa7 arm arm720t c1f8750 2011-09-05 Marius Gröger +gcplus arm sa1100 2c650e2 2011-09-05 George G. Davis +evb4510 arm arm720t 26e670e 2011-09-05 Curt Brune +ep7312 arm arm720t c8f63b4 2011-09-05 Marius Gröger +dnp1110 arm sa1100 fc5e5ce 2011-09-05 Alex Züpke +SMN42 arm arm720t 6aac646 2011-09-05 +at91rm9200dk arm arm920t 1c85752 2011-07-17 +m501sk arm arm920t b1a2bd4 2011-07-17 +kb9202 arm arm920t 5bd3814 2011-07-17 +csb637 arm arm920t d14af08 2011-07-17 +cmc_pu2 arm arm920t 37a9b4d 2011-07-17 +at91cap9adk arm arm926ejs b550834 2011-07-17 Stelian Pop +voiceblue arm arm925t 1b793a4 2011-07-17 +smdk2400 arm arm920t ad218a8 2011-07-17 Gary Jennejohn +sbc2410x arm arm920t 1f7f0ed 2011-07-17 +netstar arm arm925t 6ea2405 2011-07-17 +mx1fs2 arm arm920t 6962419 2011-07-17 +lpd7a404 arm lh7a40x 957731e 2011-07-17 +edb9301 arm arm920t 716f7ad 2011-07-17 +edb9302 arm arm920t 716f7ad 2011-07-17 +edb9302a arm arm920t 716f7ad 2011-07-17 +edb9307 arm arm920t 716f7ad 2011-07-17 +edb9307a arm arm920t 716f7ad 2011-07-17 +edb9312 arm arm920t 716f7ad 2011-07-17 +edb9315 arm arm920t 716f7ad 2011-07-17 +edb9315a arm arm920t 716f7ad 2011-07-17 +B2 arm s3c44b0 5dcf536 2011-07-16 Andrea Scian +armadillo arm arm720t be28857 2011-07-16 Rowel Atienza +assabet arm sa1100 c91e90d 2011-07-16 George G. Davis +trab arm S3C2400 566e5cf 2011-05-01 Gary Jennejohn +xsengine ARM PXA2xx 4262a7c 2010-10-20 +wepep250 ARM PXA2xx 7369478 2010-10-20 Peter Figuli +delta ARM PXA2xx 75e2035 2010-10-20 +mp2usb ARM AT91RM2900 ee986e2 2011-01-25 Eric Bénard +barco powerpc MPC8245 afaa27b 2010-11-23 Marc Leeman +ERIC powerpc 405GP d9ba451 2010-11-21 Swen Anderson +VoVPN-GW_100MHz powerpc MPC8260 26fe3d2 2010-10-24 Juergen Selent +NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk +CP850 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk +logodl ARM PXA2xx 059e778 2010-10-18 August Hoeraendl +CCM powerpc MPC860 dff07e1 2010-10-06 Wolfgang Grandegger +PCU_E powerpc MPC860T 544d97e 2010-10-06 Wolfgang Denk +spieval powerpc MPC5200 69434e4 2010-09-19 +smmaco4 powerpc MPC5200 9ddc3af 2010-09-19 +HMI10 powerpc MPC823 77efe35 2010-09-19 Wolfgang Denk +GTH powerpc MPC860 0fe247b 2010-07-17 Thomas Lange +AmigaOneG3SE powerpc 74xx_7xx 953b7e6 2010-06-23 +suzaku microblaze - 4f18060 2009-10-03 Yasushi Shoji +XUPV2P microblaze - 8fab49e 2008-12-10 Michal Simek +MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwarz +adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi +R5200 ColdFire - 48ead7a 2008-03-31 Zachary P. Landau +CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs -- cgit v0.10.2 From 4cfc611b4a4ce009cfad46804bec2a1caad8e329 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 29 Nov 2012 02:53:29 +0000 Subject: ARM: ns9750dev: remove remainders of dead board Commit 8b710b1 started removing code for the unmaintained "ns9750dev" board; the board support is still broken, and not included anywhere in the Makefile or boards.cfg. Remove the remaining dead code. Signed-off-by: Wolfgang Denk diff --git a/board/ns9750dev/Makefile b/board/ns9750dev/Makefile deleted file mode 100644 index 0d082c5..0000000 --- a/board/ns9750dev/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := ns9750dev.o flash.o led.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ns9750dev/config.mk b/board/ns9750dev/config.mk deleted file mode 100644 index e5d8702..0000000 --- a/board/ns9750dev/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -####################################################################### -# -# Copyright (C) 2004 by FS Forth-Systeme GmbH. -# Markus Pietrek -# -# @TODO -# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000 -# optionally with a ramdisk at 0080'0000 -# -# we load ourself to 0078'0000 -# -# download area is 0060'0000 -# - - -CONFIG_SYS_TEXT_BASE = 0x00780000 diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c deleted file mode 100644 index 185bc2d..0000000 --- a/board/ns9750dev/flash.c +++ /dev/null @@ -1,474 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - OrgDef *pOrgDef; - - pOrgDef = OrgIntel_28F256L18T; - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - flash_unprotect_sectors (addr); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/ns9750dev/led.c b/board/ns9750dev/led.c deleted file mode 100644 index b85c869..0000000 --- a/board/ns9750dev/led.c +++ /dev/null @@ -1,46 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: led.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @Descr: Defines helper functions for toggeling LEDs - * @Usage: - * @References: [1] - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ***********************************************************************/ - -#ifdef CONFIG_STATUS_LED - -#include - -static inline void __led_init( led_id_t mask, int state ) -{ - XXXX; -} - -static inline void __led_toggle( led_id_t mask ) -{ -} - -static inline void __led_set( led_id_t mask, int state ) -{ -} - -#endif /* CONFIG_STATUS_LED */ diff --git a/board/ns9750dev/lowlevel_init.S b/board/ns9750dev/lowlevel_init.S deleted file mode 100644 index ba5ff81..0000000 --- a/board/ns9750dev/lowlevel_init.S +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Modified for the NS9750 DevBoard by - * (C) Copyright 2004 by FS Forth-Systeme GmbH. - * Markus Pietrek - * @References: [1] NS9750 Hardware Reference/December 2003 - * [2] ns9750_a.cmd from MAJIC configuration - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_NS9750DEV) -# ifndef CONFIG_SKIP_LOWLEVEL_INIT -# include <./ns9750_sys.h> -# include <./ns9750_mem.h> -# endif -#endif - -/*********************************************************************** - * @Function: write_register_block - * @Return: nothing - * @Descr: Copies the register block of register_offset:register value to - * the registers at base r0. The block is assumed to start in RAM at r1 - * and end at r2. The linked RAM base address of U-Boot is assumed to be - * in r5 while the ROM base address we are running from is r6 - * Uses r3 and r4 as tempory registers - ***********************************************************************/ - -.macro write_register_block - @@ map the addresses to high memory - sub r1, r1, r5 - add r1, r1, r6 - sub r2, r2, r5 - add r2, r2, r6 - - @@ copy all -1: - @@ Write register/value pair starting at [r1] to register base r0 - ldr r3, [r1], #4 - ldr r4, [r1], #4 - str r4, [r0,r3] - cmp r1, r2 - blt 1b -.endm - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config.mk -_PHYS_FLASH: - .word PHYS_FLASH_1 @ real flash address (without mirroring) -_CAS_LATENCY: - .word 0x00022000 @ for CAS2 latency - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -.globl lowlevel_init -lowlevel_init: - - /* U-Boot may be linked to RAM at 0x780000. But this code will run in - flash from 0x0. But in order to enable RAM we have to disable the - mirror bit, therefore we have to jump to our real flash address - beginning at PHYS_FLASH_1 (CS4 Base). Therefore, - _run_at_real_flash_address may be 0x500003b0 while be linked to - 0x7803b0. So we must modify our linked addresses */ - - @@ branch to high memory address, away from 0x0 - ldr r5, _TEXT_BASE - ldr r6, _PHYS_FLASH - ldr r0, =_run_at_real_flash_address - sub r0, r0, r5 - add r0, r0, r6 - mov pc, r0 - nop @ for pipelining - -_run_at_real_flash_address: - @@ now we are running > PHYS_FLASH_1, safe to enable memory controller - - @@ Write Memory Configuration Registers - - ldr r0, _NS9750_MEM_MODULE_BASE - ldr r1, =_MEM_CONFIG_START - ldr r2, =_MEM_CONFIG_END - - write_register_block - - @@ Give SDRAM some time to settle - @@ @TODO. According to [2] it should be 2 AHB cycles. Check - - ldr r1, =0x50 -_sdram_settle: - subs r1, r1, #1 - bne _sdram_settle - -_enable_mappings: - @@ Enable SDRAM Mode - - ldr r1, =_MEM_MODE_START - ldr r2, =_MEM_MODE_END - - write_register_block - - ldr r3, _CAS_LATENCY @ perform one read from SDRAM - ldr r3, [r3] - - @@ Enable SDRAM and memory mappings - - ldr r1, =_MEM_ENABLE_START - ldr r2, =_MEM_ENABLE_END - - write_register_block - - @@ Activate AHB monitor - - ldr r0, =NS9750_SYS_MODULE_BASE - ldr r1, =_AHB_MONITOR_START - ldr r2, =_AHB_MONITOR_END - - write_register_block -_relocate_lr: - /* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to - PHYS_FLASH. */ - mov r1, ip - add r1, r1, r6 - mov ip, r1 - - mov r1, lr - add r1, r1, r6 - mov lr, r1 - - @@ back to arch calling code - mov pc, lr - - .ltorg - -_NS9750_MEM_MODULE_BASE: - .word NS9750_MEM_MODULE_BASE - -_MEM_CONFIG_START: - /* Table of 2 32bit entries. First word is register address offset - relative to NS9750_MEM_MODULE_BASE, second one is value. They are - written in order of appearance */ - - @@ Register values taken from [2] - .word NS9750_MEM_CTRL - .word NS9750_MEM_CTRL_E - - .word NS9750_MEM_DYN_REFRESH - .word (0x6 & NS9750_MEM_DYN_REFRESH_MA) - - .word NS9750_MEM_DYN_READ_CFG - .word (0x1 & NS9750_MEM_DYN_READ_CFG_MA) - - .word NS9750_MEM_DYN_TRP - .word (0x1 & NS9750_MEM_DYN_TRP_MA) - - .word NS9750_MEM_DYN_TRAS - .word (0x4 & NS9750_MEM_DYN_TRAS_MA) - - .word NS9750_MEM_DYN_TAPR - .word (0x1 & NS9750_MEM_DYN_TRAS_MA) - - .word NS9750_MEM_DYN_TDAL - .word (0x5 & NS9750_MEM_DYN_TDAL_MA) - - .word NS9750_MEM_DYN_TWR - .word (0x1 & NS9750_MEM_DYN_TWR_MA) - - .word NS9750_MEM_DYN_TRC - .word (0x6 & NS9750_MEM_DYN_TRC_MA) - - .word NS9750_MEM_DYN_TRFC - .word (0x6 & NS9750_MEM_DYN_TRFC_MA) - - .word NS9750_MEM_DYN_TRRD - .word (0x1 & NS9750_MEM_DYN_TRRD_MA) - - .word NS9750_MEM_DYN_TMRD - .word (0x1 & NS9750_MEM_DYN_TMRD_MA) - - @@ CS 4 - .word NS9750_MEM_DYN_CFG(0) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(0) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - @@ CS 5 - .word NS9750_MEM_DYN_CFG(1) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(1) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - @@ CS 6 - .word NS9750_MEM_DYN_CFG(2) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(2) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - @@ CS 7 - .word NS9750_MEM_DYN_CFG(3) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(3) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - .word NS9750_MEM_DYN_CTRL - .word (NS9750_MEM_DYN_CTRL_I_PALL | \ - NS9750_MEM_DYN_CTRL_SR | \ - NS9750_MEM_DYN_CTRL_CE ) - - .word NS9750_MEM_DYN_REFRESH - .word (0x1 & NS9750_MEM_DYN_REFRESH_MA) - @@ No further register settings after refresh -_MEM_CONFIG_END: - -_MEM_MODE_START: - .word NS9750_MEM_DYN_REFRESH - .word (0x30 & NS9750_MEM_DYN_REFRESH_MA) - - .word NS9750_MEM_DYN_CTRL - .word (NS9750_MEM_DYN_CTRL_I_MODE | \ - NS9750_MEM_DYN_CTRL_SR | \ - NS9750_MEM_DYN_CTRL_CE ) -_MEM_MODE_END: - -_MEM_ENABLE_START: - .word NS9750_MEM_DYN_CTRL - .word (NS9750_MEM_DYN_CTRL_I_NORMAL | \ - NS9750_MEM_DYN_CTRL_SR | \ - NS9750_MEM_DYN_CTRL_CE ) - - @@ CS 4 - .word NS9750_MEM_DYN_CFG(0) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - @@ CS 5 - .word NS9750_MEM_DYN_CFG(1) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - @@ CS 6 - .word NS9750_MEM_DYN_CFG(2) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - @@ CS 7 - .word NS9750_MEM_DYN_CFG(3) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) -_MEM_ENABLE_END: - -_AHB_MONITOR_START: - .word NS9750_SYS_AHB_TIMEOUT - .word 0x01000100 @ @TODO not calculated yet - - .word NS9750_SYS_AHB_MON - .word (NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \ - NS9750_SYS_AHB_MON_BATC_GEN_IRQ) -_AHB_MONITOR_END: - -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c deleted file mode 100644 index fc46244..0000000 --- a/board/ns9750dev/ns9750dev.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * Markus Pietrek - * derived from omap1610innovator.c - * @References: [1] NS9750 Hardware Reference/December 2003 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_NS9750DEV) -# include <./configs/ns9750dev.h> -# include <./ns9750_bbus.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -void flash__init( void ); -void ether__init( void ); - -static inline void delay( unsigned long loops ) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - - -/*********************************************************************** - * @Function: board_init - * @Return: 0 - * @Descr: Enables BBUS modules and other devices - ***********************************************************************/ - -int board_init( void ) -{ - /* Active BBUS modules */ - *get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0; - -#warning Please register your machine at http://www.arm.linux.org.uk/developer/machines/?action=new - /* arch number of OMAP 1510-Board */ - /* to be changed for OMAP 1610 Board */ - gd->bd->bi_arch_number = 234; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - -/* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable(); - - flash__init(); - ether__init(); - return 0; -} - - -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - -#if CONFIG_NR_DRAM_BANKS > 1 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif - return 0; -} diff --git a/doc/README.ns9750dev b/doc/README.ns9750dev deleted file mode 100644 index 2991440..0000000 --- a/doc/README.ns9750dev +++ /dev/null @@ -1,36 +0,0 @@ -U-Boot Port to the NS9750 DevKit from NetSilicon - -1 Overview -2 Board Configuration -3 Installation - - -1 Overview ----------- - -This port supports these NS9750 features. - -o one UART - -2 Board Configuration ---------------------- - -Switches: -SW10: 4 -SW11: 6,7 -SW16: 6,7,8 -SW17-SW20: 1 -SW4: 3, 6 -SW 1: 1 -SW2: 4 -SW3: 3 -SW8: 3 (rotated by 180 degree!!!!) - -Serial Console is Port B (bottom right port) - -3 Installation --------------- - -Have fun, --- -Markus Pietrek diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 185bd0e..e9ca96c 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +ns9750dev arm arm926ejs - - Markus Pietrek AMX860 powerpc mpc860 1b0757e 2012-10-28 Wolfgang Denk c2mon powerpc mpc855 1b0757e 2012-10-28 Wolfgang Denk ETX094 powerpc mpc850 1b0757e 2012-10-28 Wolfgang Denk diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt index c6a8ab0..ef71fea 100644 --- a/doc/driver-model/UDM-serial.txt +++ b/doc/driver-model/UDM-serial.txt @@ -86,7 +86,7 @@ III) Analysis of in-tree drivers 7) ns9750_serial.c ------------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. + Unmaintained port. Code got removed. 8) opencores_yanu.c ------------------- diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 5e8b648..de3f471 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -33,7 +33,6 @@ COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o COBJS-$(CONFIG_MCFUART) += mcfuart.o -COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o diff --git a/drivers/serial/ns9750_serial.c b/drivers/serial/ns9750_serial.c deleted file mode 100644 index 85fc68a..0000000 --- a/drivers/serial/ns9750_serial.c +++ /dev/null @@ -1,218 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_serial.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @Descr: Serial driver for the NS9750. Only one UART is supported yet. - * @References: [1] NS9750 Hardware Reference/December 2003 - * @TODO: Implement Character GAP Timer when chip is fixed for PLL bypass - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ***********************************************************************/ - -#include - -#include "ns9750_bbus.h" /* for GPIOs */ -#include "ns9750_ser.h" /* for serial configuration */ - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_CONS_INDEX) -#error "No console index specified." -#endif - -#define CONSOLE CONFIG_CONS_INDEX - -static unsigned int calcBitrateRegister( void ); -static unsigned int calcRxCharGapRegister( void ); - -static char cCharsAvailable; /* Numbers of chars in unCharCache */ -static unsigned int unCharCache; /* unCharCache is only valid if - * cCharsAvailable > 0 */ - -/*********************************************************************** - * @Function: serial_init - * @Return: 0 - * @Descr: configures GPIOs and UART. Requires BBUS Master Reset turned off - ***********************************************************************/ - -static int ns9750_serial_init(void) -{ - unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 }; - unsigned int aunGPIORxD[] = { 1, 9, 41, 45 }; - - cCharsAvailable = 0; - - /* configure TxD and RxD pins for their special function */ - set_gpio_cfg_reg_val( aunGPIOTxD[ CONSOLE ], - NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_OUTPUT ); - set_gpio_cfg_reg_val( aunGPIORxD[ CONSOLE ], - NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_INPUT ); - - /* configure serial engine */ - *get_ser_reg_addr_channel( NS9750_SER_CTRL_A, CONSOLE ) = - NS9750_SER_CTRL_A_CE | - NS9750_SER_CTRL_A_STOP | - NS9750_SER_CTRL_A_WLS_8; - - serial_setbrg(); - - *get_ser_reg_addr_channel( NS9750_SER_CTRL_B, CONSOLE ) = - NS9750_SER_CTRL_B_RCGT; - - return 0; -} - -/*********************************************************************** - * @Function: serial_putc - * @Return: n/a - * @Descr: writes one character to the FIFO. Blocks until FIFO is not full - ***********************************************************************/ - -static void ns9750_serial_putc(const char c) -{ - if (c == '\n') - serial_putc( '\r' ); - - while (!(*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE) & - NS9750_SER_STAT_A_TRDY ) ) { - /* do nothing, wait for characters in FIFO sent */ - } - - *(volatile char*) get_ser_reg_addr_channel( NS9750_SER_FIFO, - CONSOLE) = c; -} - -/*********************************************************************** - * @Function: serial_getc - * @Return: the character read - * @Descr: performs only 8bit accesses to the FIFO. No error handling - ***********************************************************************/ - -static int ns9750_serial_getc(void) -{ - int i; - - while (!serial_tstc() ) { - /* do nothing, wait for incoming characters */ - } - - /* at least one character in unCharCache */ - i = (int) (unCharCache & 0xff); - - unCharCache >>= 8; - cCharsAvailable--; - - return i; -} - -/*********************************************************************** - * @Function: serial_tstc - * @Return: 0 if no input available, otherwise != 0 - * @Descr: checks for incoming FIFO not empty. Stores the incoming chars in - * unCharCache and the numbers of characters in cCharsAvailable - ***********************************************************************/ - -static int ns9750_serial_tstc(void) -{ - unsigned int unRegCache; - - if ( cCharsAvailable ) - return 1; - - unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,CONSOLE ); - if( unRegCache & NS9750_SER_STAT_A_RBC ) { - *get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE ) = - NS9750_SER_STAT_A_RBC; - unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A, - CONSOLE ); - } - - if ( unRegCache & NS9750_SER_STAT_A_RRDY ) { - cCharsAvailable = (unRegCache & NS9750_SER_STAT_A_RXFDB_MA)>>20; - if ( !cCharsAvailable ) - cCharsAvailable = 4; - - unCharCache = *get_ser_reg_addr_channel( NS9750_SER_FIFO, - CONSOLE ); - return 1; - } - - /* no chars available */ - return 0; -} - -static void ns9750_serial_setbrg(void) -{ - *get_ser_reg_addr_channel( NS9750_SER_BITRATE, CONSOLE ) = - calcBitrateRegister(); - *get_ser_reg_addr_channel( NS9750_SER_RX_CHAR_TIMER, CONSOLE ) = - calcRxCharGapRegister(); -} - -/*********************************************************************** - * @Function: calcBitrateRegister - * @Return: value for the serial bitrate register - * @Descr: register value depends on clock frequency and baudrate - ***********************************************************************/ - -static unsigned int calcBitrateRegister( void ) -{ - return ( NS9750_SER_BITRATE_EBIT | - NS9750_SER_BITRATE_CLKMUX_BCLK | - NS9750_SER_BITRATE_TMODE | - NS9750_SER_BITRATE_TCDR_16 | - NS9750_SER_BITRATE_RCDR_16 | - ( ( ( ( CONFIG_SYS_CLK_FREQ / 8 ) / /* BBUS clock,[1] Fig. 38 */ - ( gd->baudrate * 16 ) ) - 1 ) & - NS9750_SER_BITRATE_N_MA ) ); -} - -/*********************************************************************** - * @Function: calcRxCharGapRegister - * @Return: value for the character gap timer register - * @Descr: register value depends on clock frequency and baudrate. Currently 0 - * is used as there is a bug with the gap timer in PLL bypass mode. - ***********************************************************************/ - -static unsigned int calcRxCharGapRegister( void ) -{ - return NS9750_SER_RX_CHAR_TIMER_TRUN; -} - -static struct serial_device ns9750_serial_drv = { - .name = "ns9750_serial", - .start = ns9750_serial_init, - .stop = NULL, - .setbrg = ns9750_serial_setbrg, - .putc = ns9750_serial_putc, - .puts = default_serial_puts, - .getc = ns9750_serial_getc, - .tstc = ns9750_serial_tstc, -}; - -void ns9750_serial_initialize(void) -{ - serial_register(&ns9750_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &ns9750_serial_drv; -} diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 1f8955a..7922bf0 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -164,7 +164,6 @@ serial_initfunc(altera_serial_initialize); serial_initfunc(atmel_serial_initialize); serial_initfunc(lpc32xx_serial_initialize); serial_initfunc(mcf_serial_initialize); -serial_initfunc(ns9750_serial_initialize); serial_initfunc(oc_serial_initialize); serial_initfunc(s3c64xx_serial_initialize); serial_initfunc(sandbox_serial_initialize); @@ -259,7 +258,6 @@ void serial_initialize(void) atmel_serial_initialize(); lpc32xx_serial_initialize(); mcf_serial_initialize(); - ns9750_serial_initialize(); oc_serial_initialize(); s3c64xx_serial_initialize(); sandbox_serial_initialize(); diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h deleted file mode 100644 index 3f49c6f..0000000 --- a/include/configs/ns9750dev.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * Markus Pietrek - * - * Configuation settings for the NetSilicon NS9750 DevBoard - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */ -#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */ - -#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2) -#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4) -#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8) - -/*@TODO #define CONFIG_STATUS_LED*/ -#define CONFIG_USE_IRQ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_NS9750_UART 1 /* use on-chip UART */ - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 1 /* Port B */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 38400 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_PING - - -#define CONFIG_BOOTDELAY 3 -/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ - -#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.42.30 -#define CONFIG_SERVERIP 192.168.42.1 - -/*#define CONFIG_BOOTFILE "elinos-lart" */ -/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "NS9750DEV # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */ - -#define CONFIG_SYS_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */ - -#define CONFIG_SYS_HZ (CPU_CLK_FREQ/64) - -#define NS9750_ETH_PHY_ADDRESS (0x0000) - -/*----------------------------------------------------------------------- - * Stack sizes - */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -/* TODO */ -#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ -#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */ - -#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* @TODO*/ -#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ -#endif - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* @TODO */ -/*#define CONFIG_ENV_IS_IN_FLASH 1*/ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - -#ifdef CONFIG_STATUS_LED - -extern void __led_init(led_id_t mask, int state); -extern void __led_toggle(led_id_t mask); -extern void __led_set(led_id_t mask, int state); - -#endif /* CONFIG_STATUS_LED */ - -#endif /* __CONFIG_H */ diff --git a/include/ns9750_bbus.h b/include/ns9750_bbus.h deleted file mode 100644 index 9485338..0000000 --- a/include/ns9750_bbus.h +++ /dev/null @@ -1,125 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @Descr: Definitions for BBus usage - * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - ***********************************************************************/ - -#ifndef FS_NS9750_BBUS_H -#define FS_NS9750_BBUS_H - -#define NS9750_BBUS_MODULE_BASE (0x90600000) - -#define get_bbus_reg_addr(c) \ - ((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c))) - -/* We have support for 50 GPIO pins */ - -#define get_gpio_cfg_reg_addr(pin) \ - get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) ) - -/* To Read/Modify/Write a pin configuration register, use it like - set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT ); - They should be wrapped by cli()/sti() */ -#define set_gpio_cfg_reg_val(pin,cfg) \ - *get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \ - ~NS9750_GPIO_CFG_MASK((pin))) |\ - NS9750_GPIO_CFG_VAL((pin),(cfg)); - -#define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \ - NS9750_GPIO_CFG_MA)) -#define NS9750_GPIO_CFG_VAL(pin,cfg) ((cfg) << (((pin) % 8) * 4)) - -#define NS9750_GPIO_CFG_MA (0x0F) -#define NS9750_GPIO_CFG_INPUT (0x00) -#define NS9750_GPIO_CFG_OUTPUT (0x08) -#define NS9750_GPIO_CFG_FUNC_GPIO (0x03) -#define NS9750_GPIO_CFG_FUNC_2 (0x02) -#define NS9750_GPIO_CFG_FUNC_1 (0x01) -#define NS9750_GPIO_CFG_FUNC_0 (0x00) - -/* the register addresses */ - -#define NS9750_BBUS_MASTER_RESET (0x00) -#define NS9750_BBUS_GPIO_CFG_BASE (0x10) -#define NS9750_BBUS_GPIO_CTRL_BASE (0x30) -#define NS9750_BBUS_GPIO_STAT_BASE (0x40) -#define NS9750_BBUS_MONITOR (0x50) -#define NS9750_BBUS_DMA_INT_STAT (0x60) -#define NS9750_BBUS_DMA_INT_ENABLE (0x64) -#define NS9750_BBUS_USB_CFG (0x70) -#define NS9750_BBUS_ENDIAN_CFG (0x80) -#define NS9750_BBUS_ARM_WAKE_UP (0x90) - -/* register bit fields */ - -#define NS9750_BBUS_MASTER_RESET_UTIL (0x00000100) -#define NS9750_BBUS_MASTER_RESET_I2C (0x00000080) -#define NS9750_BBUS_MASTER_RESET_1284 (0x00000040) -#define NS9750_BBUS_MASTER_RESET_SER4 (0x00000020) -#define NS9750_BBUS_MASTER_RESET_SER3 (0x00000010) -#define NS9750_BBUS_MASTER_RESET_SER2 (0x00000008) -#define NS9750_BBUS_MASTER_RESET_SER1 (0x00000004) -#define NS9750_BBUS_MASTER_RESET_USB (0x00000002) -#define NS9750_BBUS_MASTER_RESET_DMA (0x00000001) - -/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */ - -#define NS9750_BBUS_DMA_INT_BINT16 (0x00010000) -#define NS9750_BBUS_DMA_INT_BINT15 (0x00008000) -#define NS9750_BBUS_DMA_INT_BINT14 (0x00004000) -#define NS9750_BBUS_DMA_INT_BINT13 (0x00002000) -#define NS9750_BBUS_DMA_INT_BINT12 (0x00001000) -#define NS9750_BBUS_DMA_INT_BINT11 (0x00000800) -#define NS9750_BBUS_DMA_INT_BINT10 (0x00000400) -#define NS9750_BBUS_DMA_INT_BINT9 (0x00000200) -#define NS9750_BBUS_DMA_INT_BINT8 (0x00000100) -#define NS9750_BBUS_DMA_INT_BINT7 (0x00000080) -#define NS9750_BBUS_DMA_INT_BINT6 (0x00000040) -#define NS9750_BBUS_DMA_INT_BINT5 (0x00000020) -#define NS9750_BBUS_DMA_INT_BINT4 (0x00000010) -#define NS9750_BBUS_DMA_INT_BINT3 (0x00000008) -#define NS9750_BBUS_DMA_INT_BINT2 (0x00000004) -#define NS9750_BBUS_DMA_INT_BINT1 (0x00000002) -#define NS9750_BBUS_DMA_INT_BINT0 (0x00000001) - -#define NS9750_BBUS_USB_CFG_OUTEN (0x00000008) -#define NS9750_BBUS_USB_CFG_SPEED (0x00000004) -#define NS9750_BBUS_USB_CFG_CFG_MA (0x00000003) -#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003) -#define NS9750_BBUS_USB_CFG_CFG_DEVICE (0x00000002) -#define NS9750_BBUS_USB_CFG_CFG_HOST (0x00000001) -#define NS9750_BBUS_USB_CFG_CFG_DIS (0x00000000) - -#define NS9750_BBUS_ENDIAN_CFG_AHBM (0x00001000) -#define NS9750_BBUS_ENDIAN_CFG_I2C (0x00000080) -#define NS9750_BBUS_ENDIAN_CFG_IEEE1284 (0x00000040) -#define NS9750_BBUS_ENDIAN_CFG_SER4 (0x00000020) -#define NS9750_BBUS_ENDIAN_CFG_SER3 (0x00000010) -#define NS9750_BBUS_ENDIAN_CFG_SER2 (0x00000008) -#define NS9750_BBUS_ENDIAN_CFG_SER1 (0x00000004) -#define NS9750_BBUS_ENDIAN_CFG_USB (0x00000002) -#define NS9750_BBUS_ENDIAN_CFG_DMA (0x00000001) - -#endif /* FS_NS9750_BBUS_H */ diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h deleted file mode 100644 index 666e412..0000000 --- a/include/ns9750_mem.h +++ /dev/null @@ -1,172 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @Descr: Definitions for Memory Control Module - * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ***********************************************************************/ - -#ifndef FS_NS9750_MEM_H -#define FS_NS9750_SYS_H - -#define NS9750_MEM_MODULE_BASE (0xA0700000) - -#define get_mem_reg_addr(c) \ - ((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c))) - -/* the register addresses */ - -#define NS9750_MEM_CTRL (0x0000) -#define NS9750_MEM_STATUS (0x0004) -#define NS9750_MEM_CFG (0x0008) -#define NS9750_MEM_DYN_CTRL (0x0020) -#define NS9750_MEM_DYN_REFRESH (0x0024) -#define NS9750_MEM_DYN_READ_CFG (0x0028) -#define NS9750_MEM_DYN_TRP (0x0030) -#define NS9750_MEM_DYN_TRAS (0x0034) -#define NS9750_MEM_DYN_TSREX (0x0038) -#define NS9750_MEM_DYN_TAPR (0x003C) -#define NS9750_MEM_DYN_TDAL (0x0040) -#define NS9750_MEM_DYN_TWR (0x0044) -#define NS9750_MEM_DYN_TRC (0x0048) -#define NS9750_MEM_DYN_TRFC (0x004C) -#define NS9750_MEM_DYN_TXSR (0x0050) -#define NS9750_MEM_DYN_TRRD (0x0054) -#define NS9750_MEM_DYN_TMRD (0x0058) -#define NS9750_MEM_STAT_EXT_WAIT (0x0080) -#define NS9750_MEM_DYN_CFG_BASE (0x0100) -#define NS9750_MEM_DYN_RAS_CAS_BASE (0x0104) -#define NS9750_MEM_STAT_CFG_BASE (0x0200) -#define NS9750_MEM_STAT_WAIT_WEN_BASE (0x0204) -#define NS9750_MEM_STAT_WAIT_OEN_BASE (0x0208) -#define NS9750_MEM_STAT_WAIT_RD_BASE (0x020C) -#define NS9750_MEM_STAT_WAIT_PAGE_BASE (0x0210) -#define NS9750_MEM_STAT_WAIR_WR_BASE (0x0214) -#define NS9750_MEM_STAT_WAIT_TURN_BASE (0x0218) - -/* the vectored register addresses */ - -#define NS9750_MEM_DYN_CFG(c) (NS9750_MEM_DYN_CFG_BASE + (c)*0x20) -#define NS9750_MEM_DYN_RAS_CAS(c) (NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20) -#define NS9750_MEM_STAT_CFG(c) (NS9750_MEM_STAT_CFG_BASE + (c)*0x20) -#define NS9750_MEM_STAT_WAIT_WEN(c) (NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20) -#define NS9750_MEM_STAT_WAIT_OEN(c) (NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20) -#define NS9750_MEM_STAT_RD(c) (NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20) -#define NS9750_MEM_STAT_PAGE(c) (NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20) -#define NS9750_MEM_STAT_WR(c) (NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20) -#define NS9750_MEM_STAT_TURN(c) (NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20) - -/* register bit fields */ - -#define NS9750_MEM_CTRL_L (0x00000004) -#define NS9750_MEM_CTRL_M (0x00000002) -#define NS9750_MEM_CTRL_E (0x00000001) - -#define NS9750_MEM_STAT_SA (0x00000004) -#define NS9750_MEM_STAT_S (0x00000002) -#define NS9750_MEM_STAT_B (0x00000001) - -#define NS9750_MEM_CFG_CLK (0x00000010) -#define NS9750_MEM_CFG_N (0x00000001) - -#define NS9750_MEM_DYN_CTRL_NRP (0x00004000) -#define NS9750_MEM_DYN_CTRL_DP (0x00002000) -#define NS9750_MEM_DYN_CTRL_I_MA (0x00000180) -#define NS9750_MEM_DYN_CTRL_I_NORMAL (0x00000000) -#define NS9750_MEM_DYN_CTRL_I_MODE (0x00000080) -#define NS9750_MEM_DYN_CTRL_I_PALL (0x00000100) -#define NS9750_MEM_DYN_CTRL_I_NOP (0x00000180) -#define NS9750_MEM_DYN_CTRL_SR (0x00000002) -#define NS9750_MEM_DYN_CTRL_CE (0x00000001) - - -#define NS9750_MEM_DYN_REFRESH_MA (0x000007FF) - -#define NS9750_MEM_DYN_READ_CFG_MA (0x00000003) -#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001) -#define NS9750_MEM_DYN_READ_CFG_DELAY1 (0x00000002) -#define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003) - -#define NS9750_MEM_DYN_TRP_MA (0x0000000F) - -#define NS9750_MEM_DYN_TRAS_MA (0x0000000F) - -#define NS9750_MEM_DYN_TSREX_MA (0x0000000F) - -#define NS9750_MEM_DYN_TAPR_MA (0x0000000F) - -#define NS9750_MEM_DYN_TDAL_MA (0x0000000F) - -#define NS9750_MEM_DYN_TWR_MA (0x0000000F) - -#define NS9750_MEM_DYN_TRC_MA (0x0000001F) - -#define NS9750_MEM_DYN_TRFC_MA (0x0000001F) - -#define NS9750_MEM_DYN_TXSR_MA (0x0000001F) - -#define NS9750_MEM_DYN_TRRD_MA (0x0000000F) - -#define NS9750_MEM_DYN_TMRD_MA (0x0000000F) - -#define NS9750_MEM_STAT_EXTW_WAIT_MA (0x0000003F) - -#define NS9750_MEM_DYN_CFG_P (0x00100000) -#define NS9750_MEM_DYN_CFG_BDMC (0x00080000) -#define NS9750_MEM_DYN_CFG_AM (0x00004000) -#define NS9750_MEM_DYN_CFG_AM_MA (0x00001F80) -#define NS9750_MEM_DYN_CFG_MD (0x00000018) - -#define NS9750_MEM_DYN_RAS_CAS_CAS_MA (0x00000300) -#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100) -#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200) -#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300) -#define NS9750_MEM_DYN_RAS_CAS_RAS_MA (0x00000003) -#define NS9750_MEM_DYN_RAS_CAS_RAS_1 (0x00000001) -#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002) -#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003) - -#define NS9750_MEM_STAT_CFG_PSMC (0x00100000) -#define NS9750_MEM_STAT_CFG_BSMC (0x00080000) -#define NS9750_MEM_STAT_CFG_EW (0x00000100) -#define NS9750_MEM_STAT_CFG_PB (0x00000080) -#define NS9750_MEM_STAT_CFG_PC (0x00000040) -#define NS9750_MEM_STAT_CFG_PM (0x00000008) -#define NS9750_MEM_STAT_CFG_MW_MA (0x00000003) -#define NS9750_MEM_STAT_CFG_MW_8 (0x00000000) -#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001) -#define NS9750_MEM_STAT_CFG_MW_32 (0x00000002) - -#define NS9750_MEM_STAT_WAIT_WEN_MA (0x0000000F) - -#define NS9750_MEM_STAT_WAIT_OEN_MA (0x0000000F) - -#define NS9750_MEM_STAT_WAIT_RD_MA (0x0000001F) - -#define NS9750_MEM_STAT_WAIT_PAGE_MA (0x0000001F) - -#define NS9750_MEM_STAT_WAIT_WR_MA (0x0000001F) - -#define NS9750_MEM_STAT_WAIT_TURN_MA (0x0000000F) - - -#endif /* FS_NS9750_MEM_H */ diff --git a/include/ns9750_ser.h b/include/ns9750_ser.h deleted file mode 100644 index b5c297e..0000000 --- a/include/ns9750_ser.h +++ /dev/null @@ -1,202 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @References: [1] NS9750 Hardware Reference, December 2003 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ***********************************************************************/ - -#ifndef FS_NS9750_SER_H -#define FS_NS9750_SER_H - -#define NS9750_SER_MODULE_BASE (0x90200000) - -#define get_ser_reg_addr(c) \ - ((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c))) - -#define get_ser_reg_addr_channel(reg,chan) \ - get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0)) - -/* the register addresses */ - -#define NS9750_SER_CTRL_A (0x00) -#define NS9750_SER_CTRL_B (0x04) -#define NS9750_SER_STAT_A (0x08) -#define NS9750_SER_BITRATE (0x0C) -#define NS9750_SER_FIFO (0x10) -#define NS9750_SER_RX_BUF_TIMER (0x14) -#define NS9750_SER_RX_CHAR_TIMER (0x18) -#define NS9750_SER_RX_MATCH (0x1C) -#define NS9750_SER_RX_MATCH_MASK (0x20) -#define NS9750_SER_FLOW_CTRL (0x34) -#define NS9750_SER_FLOW_CTRL_FORCE (0x38) - -/* register bit fields */ - -/* control A register */ - -#define NS9750_SER_CTRL_A_CE (0x80000000) -#define NS9750_SER_CTRL_A_BRK (0x40000000) -#define NS9750_SER_CTRL_A_STICKP (0x20000000) -#define NS9750_SER_CTRL_A_EPS (0x10000000) -#define NS9750_SER_CTRL_A_PE (0x08000000) -#define NS9750_SER_CTRL_A_STOP (0x04000000) -#define NS9750_SER_CTRL_A_WLS_MA (0x03000000) -#define NS9750_SER_CTRL_A_WLS_5 (0x00000000) -#define NS9750_SER_CTRL_A_WLS_6 (0x01000000) -#define NS9750_SER_CTRL_A_WLS_7 (0x02000000) -#define NS9750_SER_CTRL_A_WLS_8 (0x03000000) -#define NS9750_SER_CTRL_A_CTSTX (0x00800000) -#define NS9750_SER_CTRL_A_RTSRX (0x00400000) -#define NS9750_SER_CTRL_A_RL (0x00200000) -#define NS9750_SER_CTRL_A_LL (0x00100000) -#define NS9750_SER_CTRL_A_RES (0x000CF000) -#define NS9750_SER_CTRL_A_DTR (0x00020000) -#define NS9750_SER_CTRL_A_RTS (0x00010000) -#define NS9750_SER_CTRL_A_RIE_MA (0x00000E00) -#define NS9750_SER_CTRL_A_ERXDMA (0x00000100) -#define NS9750_SER_CTRL_A_RIC_MA (0x000000E0) -#define NS9750_SER_CTRL_A_TIC_MA (0x0000001E) -#define NS9750_SER_CTRL_A_ETXDMA (0x00000001) - -/* control B register */ - -#define NS9750_SER_CTRL_B_RDM1 (0x80000000) -#define NS9750_SER_CTRL_B_RDM2 (0x40000000) -#define NS9750_SER_CTRL_B_RDM3 (0x20000000) -#define NS9750_SER_CTRL_B_RDM4 (0x10000000) -#define NS9750_SER_CTRL_B_RBGT (0x08000000) -#define NS9750_SER_CTRL_B_RCGT (0x04000000) -#define NS9750_SER_CTRL_B_MODE_MA (0x00300000) -#define NS9750_SER_CTRL_B_MODE_UART (0x00000000) -#define NS9750_SER_CTRL_B_MODE_HDLC (0x00100000) -#define NS9750_SER_CTRL_B_MODE_SPI_M (0x00200000) -#define NS9750_SER_CTRL_B_MODE_SPI_S (0x00300000) -#define NS9750_SER_CTRL_B_BITORDR (0x00080000) -#define NS9750_SER_CTRL_B_RES (0x0007703F) -#define NS9750_SER_CTRL_B_RTSTX (0x00008000) -#define NS9750_SER_CTRL_B_ENDEC_MA (0x00000FC0) - -/* status A register */ - -#define NS9750_SER_STAT_A_MATCH1 (0x80000000) -#define NS9750_SER_STAT_A_MATCH2 (0x40000000) -#define NS9750_SER_STAT_A_MATCH3 (0x20000000) -#define NS9750_SER_STAT_A_MATCH4 (0x10000000) -#define NS9750_SER_STAT_A_BGAP (0x08000000) -#define NS9750_SER_STAT_A_CGAP (0x04000000) -#define NS9750_SER_STAT_A_RXFDB_MA (0x00300000) -#define NS9750_SER_STAT_A_RXFDB_FULL (0x00000000) -#define NS9750_SER_STAT_A_RXFDB_1 (0x00100000) -#define NS9750_SER_STAT_A_RXFDB_2 (0x00200000) -#define NS9750_SER_STAT_A_RXFDB_3 (0x00300000) -#define NS9750_SER_STAT_A_DCD (0x00080000) -#define NS9750_SER_STAT_A_RI (0x00040000) -#define NS9750_SER_STAT_A_DSR (0x00020000) -#define NS9750_SER_STAT_A_CTS (0x00010000) -#define NS9750_SER_STAT_A_RBRK (0x00008000) -#define NS9750_SER_STAT_A_RFE (0x00004000) -#define NS9750_SER_STAT_A_RPE (0x00002000) -#define NS9750_SER_STAT_A_ROVER (0x00001000) -#define NS9750_SER_STAT_A_RRDY (0x00000800) -#define NS9750_SER_STAT_A_RHALF (0x00000400) -#define NS9750_SER_STAT_A_RBC (0x00000200) -#define NS9750_SER_STAT_A_RFULL (0x00000100) -#define NS9750_SER_STAT_A_DCDI (0x00000080) -#define NS9750_SER_STAT_A_RII (0x00000040) -#define NS9750_SER_STAT_A_DSRI (0x00000020) -#define NS9750_SER_STAT_A_CTSI (0x00000010) -#define NS9750_SER_STAT_A_TRDY (0x00000008) -#define NS9750_SER_STAT_A_THALF (0x00000004) -#define NS9750_SER_STAT_A_TBC (0x00000002) -#define NS9750_SER_STAT_A_TEMPTY (0x00000001) - -#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \ - NS9750_SER_STAT_A_ROVER | \ - NS9750_SER_STAT_A_RPE ) -#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \ - NS9750_SER_STAT_A_RBRK | \ - NS9750_SER_STAT_A_RRDY | \ - NS9750_SER_STAT_A_RHALF | \ - NS9750_SER_STAT_A_RBC | \ - NS9750_SER_STAT_A_DCDI | \ - NS9750_SER_STAT_A_RII | \ - NS9750_SER_STAT_A_DSRI | \ - NS9750_SER_STAT_A_CTSI ) -#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \ - NS9750_SER_STAT_A_THALF | \ - NS9750_SER_STAT_A_TBC | \ - NS9750_SER_STAT_A_TEMPTY ) -/* bit rate register */ - -#define NS9750_SER_BITRATE_EBIT (0x80000000) -#define NS9750_SER_BITRATE_TMODE (0x40000000) -#define NS9750_SER_BITRATE_RXSRC (0x20000000) -#define NS9750_SER_BITRATE_TXSRC (0x10000000) -#define NS9750_SER_BITRATE_RXEXT (0x08000000) -#define NS9750_SER_BITRATE_TXEXT (0x04000000) -#define NS9750_SER_BITRATE_CLKMUX_MA (0x03000000) -#define NS9750_SER_BITRATE_CLKMUX_XTAL (0x00000000) -#define NS9750_SER_BITRATE_CLKMUX_BCLK (0x01000000) -#define NS9750_SER_BITRATE_CLKMUX_OUT1 (0x02000000) -#define NS9750_SER_BITRATE_CLKMUX_OUT2 (0x03000000) -#define NS9750_SER_BITRATE_TXCINV (0x00800000) -#define NS9750_SER_BITRATE_RXCINV (0x00400000) -#define NS9750_SER_BITRATE_TCDR_MA (0x00180000) -#define NS9750_SER_BITRATE_TCDR_1 (0x00000000) -#define NS9750_SER_BITRATE_TCDR_8 (0x00080000) -#define NS9750_SER_BITRATE_TCDR_16 (0x00100000) -#define NS9750_SER_BITRATE_TCDR_32 (0x00180000) -#define NS9750_SER_BITRATE_RCDR_MA (0x00070000) -#define NS9750_SER_BITRATE_RCDR_1 (0x00000000) -#define NS9750_SER_BITRATE_RCDR_8 (0x00020000) -#define NS9750_SER_BITRATE_RCDR_16 (0x00040000) -#define NS9750_SER_BITRATE_RCDR_32 (0x00060000) -#define NS9750_SER_BITRATE_TICS (0x00010000) -#define NS9750_SER_BITRATE_RICS (0x00008000) -#define NS9750_SER_BITRATE_N_MA (0x00007FFF) - -/* receive buffer gap timer */ - -#define NS9750_SER_RX_BUF_TIMER_TRUN (0x80000000) /* UART and SPI */ -#define NS9750_SER_RX_BUF_TIMER_BT_MA (0x0000FFFF) /* UART and SPI */ -#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */ - -/* receive character gap timer */ - -#define NS9750_SER_RX_CHAR_TIMER_TRUN (0x80000000) -#define NS9750_SER_RX_CHAR_TIMER_CT_MA (0x000FFFFF) - -/* receive match */ - -#define NS9750_SER_RX_MATCH_RDMB1_MA (0xFF000000) -#define NS9750_SER_RX_MATCH_RDMB2_MA (0x00FF0000) -#define NS9750_SER_RX_MATCH_RDMB3_MA (0x0000FF00) -#define NS9750_SER_RX_MATCH_RDMB4_MA (0x000000FF) - -/* receive match mask */ - -#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000) -#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000) -#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00) -#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF) - -#endif /* FS_NS9750_SER_H */ diff --git a/include/ns9750_sys.h b/include/ns9750_sys.h deleted file mode 100644 index f1dc2b2..0000000 --- a/include/ns9750_sys.h +++ /dev/null @@ -1,215 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @Descr: Definitions for SYS Control Module - * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ***********************************************************************/ - -#ifndef FS_NS9750_SYS_H -#define FS_NS9750_SYS_H - -#define NS9750_SYS_MODULE_BASE (0xA0900000) - -#define get_sys_reg_addr(c) \ - ((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c))) - -/* the register addresses */ - -#define NS9750_SYS_AHB_GEN (0x0000) -#define NS9750_SYS_BRC_BASE (0x0004) -#define NS9750_SYS_AHB_TIMEOUT (0x0014) -#define NS9750_SYS_AHB_ERROR1 (0x0018) -#define NS9750_SYS_AHB_ERROR2 (0x001C) -#define NS9750_SYS_AHB_MON (0x0020) -#define NS9750_SYS_TIMER_COUNT_BASE (0x0044) -#define NS9750_SYS_TIMER_READ_BASE (0x0084) -#define NS9750_SYS_INT_VEC_ADR_BASE (0x00C4) -#define NS9750_SYS_INT_CFG_BASE (0x0144) -#define NS9750_SYS_ISRADDR (0x0164) -#define NS9750_SYS_INT_STAT_ACTIVE (0x0168) -#define NS9750_SYS_INT_STAT_RAW (0x016C) -#define NS9750_SYS_TIMER_INT_STAT (0x0170) -#define NS9750_SYS_SW_WDOG_CFG (0x0174) -#define NS9750_SYS_SW_WDOG_TIMER (0x0178) -#define NS9750_SYS_CLOCK (0x017C) -#define NS9750_SYS_RESET (0x0180) -#define NS9750_SYS_MISC (0x0184) -#define NS9750_SYS_PLL (0x0188) -#define NS9750_SYS_ACT_INT_STAT (0x018C) -#define NS9750_SYS_TIMER_CTRL_BASE (0x0190) -#define NS9750_SYS_CS_DYN_BASE_BASE (0x01D0) -#define NS9750_SYS_CS_DYN_MASK_BASE (0x01D4) -#define NS9750_SYS_CS_STATIC_BASE_BASE (0x01F0) -#define NS9750_SYS_CS_STATIC_MASK_BASE (0x01F4) -#define NS9750_SYS_GEN_ID (0x0210) -#define NS9750_SYS_EXT_INT_CTRL_BASE (0x0214) - -/* the vectored register addresses */ - -#define NS9750_SYS_TIMER_COUNT(c) (NS9750_SYS_TIMER_COUNT_BASE + (c)) -#define NS9750_SYS_TIMER_READ(c) (NS9750_SYS_TIMER_READ_BASE + (c)) -#define NS9750_SYS_INT_VEC_ADR(c) (NS9750_SYS_INT_VEC_ADR_BASE + (c)) -#define NS9750_SYS_TIMER_CTRL(c) (NS9750_SYS_TIMER_CTRL_BASE + (c)) -/* CS_DYN start with 4 */ -#define NS9750_SYS_CS_DYN_BASE(c) (NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2) -#define NS9750_SYS_CS_DYN_MASK(c) (NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2) -/* CS_STATIC start with 0 */ -#define NS9750_SYS_CS_STATIC_BASE(c) (NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2) -#define NS9750_SYS_CS_STATIC_MASK(c) (NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2) -#define NS9750_SYS_EXT_INT_CTRL(c) (NS9750_SYS_EXT_INT_CTRL + (c)) - -/* register bit fields */ - -#define NS9750_SYS_AHB_GEN_EXMAM (0x00000001) - -/* need to be n*8bit to BRC channel */ -#define NS9750_SYS_BRC_CEB (0x00000080) -#define NS9750_SYS_BRC_BRF_MA (0x00000030) -#define NS9750_SYS_BRC_BRF_100 (0x00000000) -#define NS9750_SYS_BRC_BRF_75 (0x00000010) -#define NS9750_SYS_BRC_BRF_50 (0x00000020) -#define NS9750_SYS_BRC_BRF_25 (0x00000030) - -#define NS9750_SYS_AHB_TIMEOUT_BAT_MA (0xFFFF0000) -#define NS9750_SYS_AHB_TIMEOUT_BMT_MA (0x0000FFFF) - -#define NS9750_SYS_AHB_ERROR2_ABL (0x00040000) -#define NS9750_SYS_AHB_ERROR2_AER (0x00020000) -#define NS9750_SYS_AHB_ERROR2_ABM (0x00010000) -#define NS9750_SYS_AHB_ERROR2_ABA (0x00008000) -#define NS9750_SYS_AHB_ERROR2_HWRT (0x00004000) -#define NS9750_SYS_AHB_ERROR2_HMID_MA (0x00003C00) -#define NS9750_SYS_AHB_ERROR2_HTPC_MA (0x000003C0) -#define NS9750_SYS_AHB_ERROR2_HSZ_MA (0x00000038) -#define NS9750_SYS_AHB_ERROR2_RR_MA (0x00000007) - -#define NS9750_SYS_AHB_MON_EIC (0x00800000) -#define NS9750_SYS_AHB_MON_MBII (0x00400000) -#define NS9750_SYS_AHB_MON_MBL_MA (0x003FFFC0) -#define NS9750_SYS_AHB_MON_MBLDC (0x00000020) -#define NS9750_SYS_AHB_MON_SERDC (0x00000010) -#define NS9750_SYS_AHB_MON_BMTC_MA (0x0000000C) -#define NS9750_SYS_AHB_MON_BMTC_RECORD (0x00000000) -#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ (0x00000004) -#define NS9750_SYS_AHB_MON_BMTC_GEN_RES (0x00000008) -#define NS9750_SYS_AHB_MON_BATC_MA (0x00000003) -#define NS9750_SYS_AHB_MON_BATC_RECORD (0x00000000) -#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ (0x00000001) -#define NS9750_SYS_AHB_MON_BATC_GEN_RES (0x00000002) - -/* need to be n*8bit to Int Level */ - -#define NS9750_SYS_INT_CFG_IE (0x00000080) -#define NS9750_SYS_INT_CFG_IT (0x00000020) -#define NS9750_SYS_INT_CFG_IAD_MA (0x0000001F) - -#define NS9750_SYS_TIMER_INT_STAT_MA (0x0000FFFF) - -#define NS9750_SYS_SW_WDOG_CFG_SWWE (0x00000080) -#define NS9750_SYS_SW_WDOG_CFG_SWWI (0x00000020) -#define NS9750_SYS_SW_WDOG_CFG_SWWIC (0x00000010) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA (0x00000007) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 (0x00000000) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 (0x00000001) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 (0x00000002) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16 (0x00000003) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32 (0x00000004) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64 (0x00000005) - -#define NS9750_SYS_CLOCK_LPCS_MA (0x00000380) -#define NS9750_SYS_CLOCK_LPCS_1 (0x00000000) -#define NS9750_SYS_CLOCK_LPCS_2 (0x00000080) -#define NS9750_SYS_CLOCK_LPCS_4 (0x00000100) -#define NS9750_SYS_CLOCK_LPCS_8 (0x00000180) -#define NS9750_SYS_CLOCK_LPCS_EXT (0x00000200) -#define NS9750_SYS_CLOCK_BBC (0x00000040) -#define NS9750_SYS_CLOCK_LCC (0x00000020) -#define NS9750_SYS_CLOCK_MCC (0x00000010) -#define NS9750_SYS_CLOCK_PARBC (0x00000008) -#define NS9750_SYS_CLOCK_PC (0x00000004) -#define NS9750_SYS_CLOCK_MACC (0x00000001) - -#define NS9750_SYS_RESET_SR (0x80000000) -#define NS9750_SYS_RESET_I2CW (0x00100000) -#define NS9750_SYS_RESET_CSE (0x00080000) -#define NS9750_SYS_RESET_SMWE (0x00040000) -#define NS9750_SYS_RESET_EWE (0x00020000) -#define NS9750_SYS_RESET_PI3WE (0x00010000) -#define NS9750_SYS_RESET_BBT (0x00000040) -#define NS9750_SYS_RESET_LCDC (0x00000020) -#define NS9750_SYS_RESET_MEMC (0x00000010) -#define NS9750_SYS_RESET_PCIAR (0x00000008) -#define NS9750_SYS_RESET_PCIM (0x00000004) -#define NS9750_SYS_RESET_MACM (0x00000001) - -#define NS9750_SYS_MISC_REV_MA (0xFF000000) -#define NS9750_SYS_MISC_PCIA (0x00002000) -#define NS9750_SYS_MISC_VDIS (0x00001000) -#define NS9750_SYS_MISC_BMM (0x00000800) -#define NS9750_SYS_MISC_CS1DB (0x00000400) -#define NS9750_SYS_MISC_CS1DW_MA (0x00000300) -#define NS9750_SYS_MISC_MCCM (0x00000080) -#define NS9750_SYS_MISC_PMSS (0x00000040) -#define NS9750_SYS_MISC_CS1P (0x00000020) -#define NS9750_SYS_MISC_ENDM (0x00000008) -#define NS9750_SYS_MISC_MBAR (0x00000004) -#define NS9750_SYS_MISC_IRAM0 (0x00000001) - -#define NS9750_SYS_PLL_PLLBS (0x02000000) -#define NS9750_SYS_PLL_PLLFS_MA (0x01800000) -#define NS9750_SYS_PLL_PLLIS_MA (0x00600000) -#define NS9750_SYS_PLL_PLLND_MA (0x001F0000) -#define NS9750_SYS_PLL_PLLSW (0x00008000) -#define NS9750_SYS_PLL_PLLBSSW (0x00000200) -#define NS9750_SYS_PLL_FSEL_MA (0x00000180) -#define NS9750_SYS_PLL_CPCC_MA (0x00000060) -#define NS9750_SYS_PLL_NDSW_MA (0x0000001F) - -#define NS9750_SYS_ACT_INT_STAT_MA (0x0000FFFF) - -#define NS9750_SYS_TIMER_CTRL_TEN (0x00008000) -#define NS9750_SYS_TIMER_CTRL_INTC (0x00000200) -#define NS9750_SYS_TIMER_CTRL_TLCS_MA (0x000001C0) -#define NS9750_SYS_TIMER_CTRL_TLCS_1 (0x00000000) -#define NS9750_SYS_TIMER_CTRL_TLCS_2 (0x00000040) -#define NS9750_SYS_TIMER_CTRL_TLCS_4 (0x00000080) -#define NS9750_SYS_TIMER_CTRL_TLCS_8 (0x000000C0) -#define NS9750_SYS_TIMER_CTRL_TLCS_16 (0x00000100) -#define NS9750_SYS_TIMER_CTRL_TLCS_32 (0x00000140) -#define NS9750_SYS_TIMER_CTRL_TLCS_64 (0x00000180) -#define NS9750_SYS_TIMER_CTRL_TLCS_EXT (0x000001C0) -#define NS9750_SYS_TIMER_CTRL_TM_MA (0x00000030) -#define NS9750_SYS_TIMER_CTRL_TM_INT (0x00000000) -#define NS9750_SYS_TIMER_CTRL_TM_LOW (0x00000010) -#define NS9750_SYS_TIMER_CTRL_TM_HIGH (0x00000020) -#define NS9750_SYS_TIMER_CTRL_INTS (0x00000008) -#define NS9750_SYS_TIMER_CTRL_UDS (0x00000004) -#define NS9750_SYS_TIMER_CTRL_TSZ (0x00000002) -#define NS9750_SYS_TIMER_CTRL_REN (0x00000001) - -#define NS9750_SYS_EXT_INT_CTRL_STS (0x00000008) -#define NS9750_SYS_EXT_INT_CTRL_CLR (0x00000004) -#define NS9750_SYS_EXT_INT_CTRL_PLTY (0x00000002) -#define NS9750_SYS_EXT_INT_CTRL_LVEDG (0x00000001) - -#endif /* FS_NS9750_SYS_H */ -- cgit v0.10.2 From 74cf809972658eae18c33e078c05a7cc9c9460c9 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 19 Feb 2013 10:07:00 +0000 Subject: i.MX6: mx6qsabrelite: indent with tabs This patch has no functional changes and simply replaces leading spaces with tabs. Signed-off-by: Eric Nelson diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index f010d0c..c6c64c3 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -46,12 +46,12 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ @@ -72,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - return 0; + return 0; } iomux_v3_cfg_t const uart1_pads[] = { @@ -83,8 +83,8 @@ iomux_v3_cfg_t const uart1_pads[] = { }; iomux_v3_cfg_t const uart2_pads[] = { - MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -132,23 +132,23 @@ struct i2c_pads_info i2c_pad_info2 = { }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const enet_pads1[] = { @@ -227,7 +227,7 @@ iomux_v3_cfg_t const usb_pads[] = { static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } #ifdef CONFIG_USB_EHCI_MX6 @@ -246,55 +246,55 @@ int board_ehci_hcd_init(int port) #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { gpio_direction_input(IMX_GPIO_NR(7, 0)); ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); - } else { + } else { gpio_direction_input(IMX_GPIO_NR(2, 6)); ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); - } + } - return ret; + return ret; } int board_mmc_init(bd_t *bis) { - s32 status = 0; - u32 index = 0; + s32 status = 0; + u32 index = 0; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); break; default: - printf("Warning: you configured more USDHC controllers" + printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; - } + return status; + } - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - } + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } - return status; + return status; } #endif @@ -732,8 +732,8 @@ int overwrite_console(void) int board_init(void) { - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_MXC_SPI setup_spi(); @@ -746,14 +746,14 @@ int board_init(void) setup_sata(); #endif - return 0; + return 0; } int checkboard(void) { - puts("Board: MX6Q-Sabre Lite\n"); + puts("Board: MX6Q-Sabre Lite\n"); - return 0; + return 0; } struct button_key { -- cgit v0.10.2 From cfb8b9d3351ebb519f9c27e0aeba814e7c81ee85 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 19 Feb 2013 10:07:01 +0000 Subject: i.MX6: consolidate pad names for multi-CPU boards Rename all i.MX6 pad declarations to MX6_PAD_x, so a board may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo (MX6DL) by including the proper header. Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd only support MX6Q, so they include mx6q_pins.h. Signed-off-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h new file mode 100644 index 0000000..63f4856 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2013 Boundary Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_MX6_PINS_H__ +#define __ASM_ARCH_MX6_PINS_H__ + +#ifdef CONFIG_MX6Q +#include "mx6q_pins.h" +#else +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#include "mx6dl_pins.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX6DL or CONFIG_MX6S */ +#endif /* CONFIG_MX6Q */ + +#endif /*__ASM_ARCH_MX6_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 79e2c4f..0395357 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -50,100 +50,100 @@ #define NO_MUX_I 0 #define NO_PAD_I 0 enum { - MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0), - MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0), - MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0), - MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), - MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), - MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0), - MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0), - MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), - MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), - MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0), - MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), - MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0), - MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0), - MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), - MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0), - MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0), - MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0), - MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), - MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), - MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), - MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), - MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), - MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), - MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), - MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), - MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), - MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), - MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), - MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0), - MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), - MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6DL_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6DL_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), - MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), - MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), - MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), - MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), - MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0), + MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0), + MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0), + MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0), + MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), + MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0), + MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0), + MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0), + MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0), + MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), + MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), + MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), + MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), + MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), + MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0), + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), + MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), + MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), + MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h new file mode 100644 index 0000000..1c1c008 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -0,0 +1,1671 @@ +/* + * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Auto Generate file, please don't edit it + * + */ + +#ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__ +#define __ASM_ARCH_MX6_MX6Q_PINS_H__ + +#include + +/* Use to set PAD control */ +#define PAD_CTL_HYS (1 << 16) +#define PAD_CTL_PUS_100K_DOWN (0 << 14) +#define PAD_CTL_PUS_47K_UP (1 << 14) +#define PAD_CTL_PUS_100K_UP (2 << 14) +#define PAD_CTL_PUS_22K_UP (3 << 14) + +#define PAD_CTL_PUE (1 << 13) +#define PAD_CTL_PKE (1 << 12) +#define PAD_CTL_ODE (1 << 11) +#define PAD_CTL_SPEED_LOW (1 << 6) +#define PAD_CTL_SPEED_MED (2 << 6) +#define PAD_CTL_SPEED_HIGH (3 << 6) +#define PAD_CTL_DSE_DISABLE (0 << 3) +#define PAD_CTL_DSE_240ohm (1 << 3) +#define PAD_CTL_DSE_120ohm (2 << 3) +#define PAD_CTL_DSE_80ohm (3 << 3) +#define PAD_CTL_DSE_60ohm (4 << 3) +#define PAD_CTL_DSE_48ohm (5 << 3) +#define PAD_CTL_DSE_40ohm (6 << 3) +#define PAD_CTL_DSE_34ohm (7 << 3) +#define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_SLOW (0 << 0) + +#define NO_MUX_I 0 +#define NO_PAD_I 0 + +enum { + MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0), + MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), + MX6_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), + MX6_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0), + MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), + MX6_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), + MX6_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0), + MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), + MX6_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), + MX6_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), + MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0), + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), + MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), + MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), + MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), + MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), + MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), + MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0), + MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0), + MX6_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0), + MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0), + MX6_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), + MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0), + MX6_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0), + MX6_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0), + MX6_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), + MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0), + MX6_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0), + MX6_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0), + MX6_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0), + MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0), + MX6_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0), + MX6_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), + MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0), + MX6_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), + MX6_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), + MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), + MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0), + MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), + MX6_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), + MX6_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), + MX6_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), + MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0), + MX6_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), + MX6_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), + MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), + MX6_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0), + MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), + MX6_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0), + MX6_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), + MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0), + MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), + MX6_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), + MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0), + MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), + MX6_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), + MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), + MX6_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), + MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), + MX6_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0), + MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), + MX6_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), + MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0), + MX6_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), + MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0), + MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), + MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), + MX6_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), + MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), + MX6_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), + MX6_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), + MX6_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), + MX6_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), + MX6_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), + MX6_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), + MX6_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), + MX6_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0), + MX6_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0), + MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0), + MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), + MX6_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0), + MX6_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), + MX6_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), + MX6_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0), + MX6_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), + MX6_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), + MX6_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0), + MX6_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), + MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), + MX6_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), + MX6_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), + MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0), + MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0), + MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0), + MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), + MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), + MX6_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), + MX6_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), + MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), + MX6_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0), + MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), + MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), + MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0), + MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), + MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), + MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), + MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), + MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), + MX6_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0), + MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), + MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), + MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0), + MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), + MX6_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0), + MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), + MX6_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0), + MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), + MX6_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), + MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), + MX6_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0), + MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), + MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), + MX6_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), + MX6_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), + MX6_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0), + MX6_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), + MX6_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), + MX6_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), + MX6_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0), + MX6_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0), + MX6_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), + MX6_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), + MX6_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), + MX6_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), + MX6_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0), + MX6_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), + MX6_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), + MX6_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0), + MX6_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0), + MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), + MX6_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0), + MX6_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), + MX6_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), + MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), + MX6_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0), + MX6_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), + MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0), + MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), + MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0), + MX6_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0), + MX6_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0), + MX6_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), + MX6_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), + MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), + MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), + MX6_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0), + MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), + MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), + MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0), + MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0), + MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), + MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), + MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0), + MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), + MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), + MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0), + MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), + MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0), + MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), + MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0), + MX6_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0), + MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0), + MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0), + MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), + MX6_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), + MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0), + MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0), + MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), + MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), + MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), + MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), + MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), + MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), + MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), + MX6_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), + MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), + MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), + MX6_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), + MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), + MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), + MX6_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0), + MX6_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), + MX6_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), + MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), + MX6_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0), + MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), + MX6_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), + MX6_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), + MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), + MX6_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), + MX6_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), + MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), + MX6_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), + MX6_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0), + MX6_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0), + MX6_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0), + MX6_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0), + MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), + MX6_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), + MX6_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), + MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), + MX6_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), + MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0), + MX6_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0), + MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0), + MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), + MX6_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), + MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0), + MX6_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), + MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), + MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), + MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0), + MX6_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), + MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0), + MX6_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), + MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0), + MX6_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), + MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0), + MX6_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), + MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0), + MX6_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), + MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0), + MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0), + MX6_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), + MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0), + MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), + MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), + MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), + MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), + MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), + MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), + MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), + MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), + MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), + MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), + MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), + MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), + MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), + MX6_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), + MX6_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), + MX6_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), + MX6_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), + MX6_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), + MX6_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), + MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), + MX6_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), + MX6_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), + MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), + MX6_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), + MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), + MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), + MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), + MX6_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0), + MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0), + MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0), + MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), + MX6_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), + MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), + MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__IPU2_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), + MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), + MX6_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), + MX6_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), + MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), + MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), + MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), + MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0), + MX6_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0), + MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0), + MX6_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0), + MX6_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0), + MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0), + MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), + MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), + MX6_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0), + MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), + MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), + MX6_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), + MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), + MX6_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0), +}; + +#endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6x_pins.h b/arch/arm/include/asm/arch-mx6/mx6x_pins.h deleted file mode 100644 index 3ade8dc..0000000 --- a/arch/arm/include/asm/arch-mx6/mx6x_pins.h +++ /dev/null @@ -1,1671 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Auto Generate file, please don't edit it - * - */ - -#ifndef __ASM_ARCH_MX6_MX6X_PINS_H__ -#define __ASM_ARCH_MX6_MX6X_PINS_H__ - -#include - -/* Use to set PAD control */ -#define PAD_CTL_HYS (1 << 16) -#define PAD_CTL_PUS_100K_DOWN (0 << 14) -#define PAD_CTL_PUS_47K_UP (1 << 14) -#define PAD_CTL_PUS_100K_UP (2 << 14) -#define PAD_CTL_PUS_22K_UP (3 << 14) - -#define PAD_CTL_PUE (1 << 13) -#define PAD_CTL_PKE (1 << 12) -#define PAD_CTL_ODE (1 << 11) -#define PAD_CTL_SPEED_LOW (1 << 6) -#define PAD_CTL_SPEED_MED (2 << 6) -#define PAD_CTL_SPEED_HIGH (3 << 6) -#define PAD_CTL_DSE_DISABLE (0 << 3) -#define PAD_CTL_DSE_240ohm (1 << 3) -#define PAD_CTL_DSE_120ohm (2 << 3) -#define PAD_CTL_DSE_80ohm (3 << 3) -#define PAD_CTL_DSE_60ohm (4 << 3) -#define PAD_CTL_DSE_48ohm (5 << 3) -#define PAD_CTL_DSE_40ohm (6 << 3) -#define PAD_CTL_DSE_34ohm (7 << 3) -#define PAD_CTL_SRE_FAST (1 << 0) -#define PAD_CTL_SRE_SLOW (0 << 0) - -#define NO_MUX_I 0 -#define NO_PAD_I 0 - -enum { - MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0), - MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), - MX6Q_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), - MX6Q_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0), - MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), - MX6Q_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), - MX6Q_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0), - MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), - MX6Q_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), - MX6Q_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), - MX6Q_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0), - MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), - MX6Q_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), - MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), - MX6Q_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), - MX6Q_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), - MX6Q_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), - MX6Q_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0), - MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0), - MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0), - MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), - MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0), - MX6Q_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0), - MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0), - MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), - MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0), - MX6Q_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0), - MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0), - MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0), - MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0), - MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0), - MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), - MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0), - MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), - MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), - MX6Q_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), - MX6Q_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0), - MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), - MX6Q_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), - MX6Q_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), - MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), - MX6Q_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0), - MX6Q_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), - MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), - MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), - MX6Q_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0), - MX6Q_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), - MX6Q_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0), - MX6Q_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), - MX6Q_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0), - MX6Q_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), - MX6Q_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), - MX6Q_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0), - MX6Q_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), - MX6Q_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), - MX6Q_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), - MX6Q_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), - MX6Q_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), - MX6Q_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0), - MX6Q_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), - MX6Q_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), - MX6Q_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0), - MX6Q_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), - MX6Q_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0), - MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), - MX6Q_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), - MX6Q_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), - MX6Q_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), - MX6Q_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), - MX6Q_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), - MX6Q_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), - MX6Q_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), - MX6Q_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), - MX6Q_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), - MX6Q_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), - MX6Q_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0), - MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0), - MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0), - MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0), - MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0), - MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0), - MX6Q_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), - MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), - MX6Q_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), - MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), - MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0), - MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0), - MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0), - MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0), - MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), - MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), - MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), - MX6Q_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), - MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), - MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), - MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), - MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), - MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), - MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0), - MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), - MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), - MX6Q_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0), - MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), - MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), - MX6Q_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), - MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), - MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), - MX6Q_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0), - MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), - MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), - MX6Q_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0), - MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), - MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0), - MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), - MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0), - MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), - MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), - MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), - MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0), - MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0), - MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0), - MX6Q_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0), - MX6Q_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), - MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0), - MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), - MX6Q_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), - MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), - MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0), - MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), - MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0), - MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), - MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), - MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0), - MX6Q_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), - MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), - MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), - MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), - MX6Q_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), - MX6Q_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0), - MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0), - MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0), - MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), - MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), - MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), - MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), - MX6Q_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0), - MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0), - MX6Q_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), - MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), - MX6Q_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), - MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), - MX6Q_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), - MX6Q_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0), - MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0), - MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0), - MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), - MX6Q_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), - MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), - MX6Q_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), - MX6Q_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0), - MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0), - MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0), - MX6Q_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0), - MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), - MX6Q_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), - MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0), - MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0), - MX6Q_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), - MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), - MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), - MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0), - MX6Q_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), - MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0), - MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0), - MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0), - MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), - MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), - MX6Q_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), - MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0), - MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0), - MX6Q_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), - MX6Q_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0), - MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), - MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0), - MX6Q_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), - MX6Q_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0), - MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), - MX6Q_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), - MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), - MX6Q_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), - MX6Q_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0), - MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), - MX6Q_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), - MX6Q_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0), - MX6Q_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0), - MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), - MX6Q_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), - MX6Q_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0), - MX6Q_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), - MX6Q_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), - MX6Q_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0), - MX6Q_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), - MX6Q_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0), - MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), - MX6Q_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0), - MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0), - MX6Q_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0), - MX6Q_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0), - MX6Q_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), - MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), - MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0), - MX6Q_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0), - MX6Q_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), - MX6Q_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), - MX6Q_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0), - MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), - MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), - MX6Q_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), - MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), - MX6Q_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), - MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), - MX6Q_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), - MX6Q_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), - MX6Q_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), - MX6Q_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), - MX6Q_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), - MX6Q_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), - MX6Q_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), - MX6Q_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), - MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0), - MX6Q_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), - MX6Q_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), - MX6Q_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), - MX6Q_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), - MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0), - MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), - MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), - MX6Q_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), - MX6Q_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), - MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), - MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), - MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6Q_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), - MX6Q_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), - MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), - MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), - MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), - MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), - MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), - MX6Q_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), - MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0), - MX6Q_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0), - MX6Q_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0), - MX6Q_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6Q_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0), - MX6Q_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0), - MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0), - MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), - MX6Q_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), - MX6Q_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), - MX6Q_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), - MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), - MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), - MX6Q_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), - MX6Q_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), - MX6Q_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0), - MX6Q_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0), - MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0), - MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), - MX6Q_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), - MX6Q_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0), - MX6Q_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), - MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), - MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), - MX6Q_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), - MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0), - MX6Q_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), - MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0), - MX6Q_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), - MX6Q_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0), - MX6Q_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0), - MX6Q_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), - MX6Q_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0), - MX6Q_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), - MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0), - MX6Q_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), - MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0), - MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), - MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0), - MX6Q_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), - MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0), - MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), - MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0), - MX6Q_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), - MX6Q_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0), - MX6Q_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0), - MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), - MX6Q_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0), - MX6Q_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), - MX6Q_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), - MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), - MX6Q_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), - MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), - MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), - MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), - MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), - MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), - MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), - MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), - MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), - MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0), - MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0), - MX6Q_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), - MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), - MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), - MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), - MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0), - MX6Q_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), - MX6Q_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), - MX6Q_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), - MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0), - MX6Q_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), - MX6Q_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), - MX6Q_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), - MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), - MX6Q_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), - MX6Q_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), - MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), - MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), - MX6Q_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6Q_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6Q_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), - MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0), - MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0), - MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0), - MX6Q_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), - MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), - MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), - MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), - MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), - MX6Q_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), - MX6Q_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), - MX6Q_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), - MX6Q_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), - MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), - MX6Q_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), - MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0), - MX6Q_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), - MX6Q_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), - MX6Q_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), - MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), - MX6Q_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), - MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), - MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), - MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), - MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), - MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0), - MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0), - MX6Q_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0), - MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0), - MX6Q_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), - MX6Q_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0), - MX6Q_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), - MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), - MX6Q_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), - MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0), - MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), - MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0), - MX6Q_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), - MX6Q_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0), - MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), - MX6Q_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), - MX6Q_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), - MX6Q_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), - MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0), - MX6Q_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), - MX6Q_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0), - MX6Q_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), - MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), - MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), - MX6Q_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), - MX6Q_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), - MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0), - MX6Q_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), - MX6Q_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0), - MX6Q_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), - MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), - MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), - MX6Q_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), - MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), - MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), - MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0), -}; - -#endif /* __ASM_ARCH_MX6_MX6X_PINS_H__ */ diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index ee20d4f..ff7f5e8 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include @@ -55,53 +55,53 @@ int dram_init(void) } iomux_v3_cfg_t const uart4_pads[] = { - MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { - MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 9e3700e..91cc007 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include @@ -54,26 +54,26 @@ int dram_init(void) } iomux_v3_cfg_t const uart4_pads[] = { - MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { - MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -82,18 +82,18 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index c6c64c3..f7b7f07 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -78,13 +78,13 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const uart2_pads[] = { - MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -92,13 +92,13 @@ iomux_v3_cfg_t const uart2_pads[] = { /* I2C1, SGTL5000 */ struct i2c_pads_info i2c_pad_info0 = { .scl = { - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC, + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, .gp = IMX_GPIO_NR(3, 21) }, .sda = { - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC, + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, .gp = IMX_GPIO_NR(3, 28) } }; @@ -106,13 +106,13 @@ struct i2c_pads_info i2c_pad_info0 = { /* I2C2 Camera, MIPI */ struct i2c_pads_info i2c_pad_info1 = { .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC, + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, .gp = IMX_GPIO_NR(4, 12) }, .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC, + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; @@ -120,86 +120,86 @@ struct i2c_pads_info i2c_pad_info1 = { /* I2C3, J15 - RGB connector */ struct i2c_pads_info i2c_pad_info2 = { .scl = { - .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC, + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, .gp = IMX_GPIO_NR(1, 5) }, .sda = { - .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC, + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, .gp = IMX_GPIO_NR(7, 11) } }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const enet_pads1[] = { - MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), /* pin 35 - 1 (PHY_AD2) on reset */ - MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 32 - 1 - (MODE0) all */ - MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 31 - 1 - (MODE1) all */ - MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 28 - 1 - (MODE2) all */ - MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 27 - 1 - (MODE3) all */ - MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 42 PHY nRST */ - MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads2[] = { - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; /* Button assignments for J14 */ static iomux_v3_cfg_t const button_pads[] = { /* Menu */ - MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Back */ - MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Labelled Search (mapped to Power under Android) */ - MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Home */ - MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Down */ - MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Up */ - MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -221,7 +221,7 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usb_pads[] = { - MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) @@ -306,10 +306,10 @@ u32 get_board_rev(void) #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ - MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), }; void setup_spi(void) @@ -403,44 +403,44 @@ int setup_sata(void) static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight on RGB connector: J15 */ - MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) /* Backlight on LVDS connector: J6 */ - MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) }; static iomux_v3_cfg_t const rgb_pads[] = { - MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, - MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, - MX6Q_PAD_DI0_PIN4__GPIO_4_20, - MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, + MX6_PAD_DI0_PIN4__GPIO_4_20, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, }; struct display_info_t { diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c index 65c4a1a..2b3926a 100644 --- a/board/freescale/mx6qsabresd/mx6qsabresd.c +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include @@ -52,28 +52,28 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { - MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8031 PHY Reset */ - MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -87,44 +87,44 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usdhc2_pads[] = { - MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; static void setup_iomux_uart(void) -- cgit v0.10.2 From 4f60c49a70a1201c2365651dc5dcb76503b58cf3 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 19 Feb 2013 10:07:02 +0000 Subject: i.MX6: crm_regs: define CCM_CCGRx for use in board config files Signed-off-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index d670f30..7676457 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -20,6 +20,17 @@ #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ +#define CCM_CCGR0 0x020C4068 +#define CCM_CCGR1 0x020C406c +#define CCM_CCGR2 0x020C4070 +#define CCM_CCGR3 0x020C4074 +#define CCM_CCGR4 0x020C4078 +#define CCM_CCGR5 0x020C407c +#define CCM_CCGR6 0x020C4080 + +#define PMU_MISC2 0x020C8170 + +#ifndef __ASSEMBLY__ struct mxc_ccm_reg { u32 ccr; /* 0x0000 */ u32 ccdr; @@ -105,6 +116,7 @@ struct mxc_ccm_reg { u32 analog_pfd_528_clr; u32 analog_pfd_528_tog; }; +#endif /* Define the bits in register CCR */ #define MXC_CCM_CCR_RBC_EN (1 << 27) -- cgit v0.10.2 From 714afa64f3d81a660715b61785f1f3a3b986f852 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 19 Feb 2013 10:07:03 +0000 Subject: i.MX6: crm_regs: define IOMUXC_GPR4/6/7 Signed-off-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index d23abd7..d67f600 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -16,6 +16,11 @@ #ifndef __ASM_ARCH_IOMUX_H__ #define __ASM_ARCH_IOMUX_H__ + +#define MX6_IOMUXC_GPR4 0x020e0010 +#define MX6_IOMUXC_GPR6 0x020e0018 +#define MX6_IOMUXC_GPR7 0x020e001c + /* * IOMUXC_GPR13 bit fields */ -- cgit v0.10.2 From 828bd14c108975e956bf9b687005c1fc1b6e8ba1 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 19 Feb 2013 10:07:04 +0000 Subject: i.MX6DL: define IOMUX pads NANDF_CS1-3 for use as GPIO Signed-off-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 0395357..9494e41 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -105,6 +105,9 @@ enum { MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), -- cgit v0.10.2 From 690417236f8abe7c2f383559035c0398031b7fa5 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 19 Feb 2013 10:07:05 +0000 Subject: i.MX6: Add DDR controller registers Signed-off-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h new file mode 100644 index 0000000..1fdc1d4 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2013 Boundary Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_MX6_DDR_H__ +#define __ASM_ARCH_MX6_DDR_H__ + +#ifdef CONFIG_MX6Q +#include "mx6q-ddr.h" +#else +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#include "mx6dl-ddr.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX6DL or CONFIG_MX6S */ +#endif /* CONFIG_MX6Q */ + +#define MX6_MMDC_P0_MDCTL 0x021b0000 +#define MX6_MMDC_P0_MDPDC 0x021b0004 +#define MX6_MMDC_P0_MDOTC 0x021b0008 +#define MX6_MMDC_P0_MDCFG0 0x021b000c +#define MX6_MMDC_P0_MDCFG1 0x021b0010 +#define MX6_MMDC_P0_MDCFG2 0x021b0014 +#define MX6_MMDC_P0_MDMISC 0x021b0018 +#define MX6_MMDC_P0_MDSCR 0x021b001c +#define MX6_MMDC_P0_MDREF 0x021b0020 +#define MX6_MMDC_P0_MDRWD 0x021b002c +#define MX6_MMDC_P0_MDOR 0x021b0030 +#define MX6_MMDC_P0_MDASP 0x021b0040 +#define MX6_MMDC_P0_MAPSR 0x021b0404 +#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800 +#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c +#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810 +#define MX6_MMDC_P0_MPODTCTRL 0x021b0818 +#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c +#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820 +#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824 +#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828 +#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c +#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840 +#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848 +#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850 +#define MX6_MMDC_P0_MPMUR0 0x021b08b8 + +#define MX6_MMDC_P1_MDCTL 0x021b4000 +#define MX6_MMDC_P1_MDPDC 0x021b4004 +#define MX6_MMDC_P1_MDOTC 0x021b4008 +#define MX6_MMDC_P1_MDCFG0 0x021b400c +#define MX6_MMDC_P1_MDCFG1 0x021b4010 +#define MX6_MMDC_P1_MDCFG2 0x021b4014 +#define MX6_MMDC_P1_MDMISC 0x021b4018 +#define MX6_MMDC_P1_MDSCR 0x021b401c +#define MX6_MMDC_P1_MDREF 0x021b4020 +#define MX6_MMDC_P1_MDRWD 0x021b402c +#define MX6_MMDC_P1_MDOR 0x021b4030 +#define MX6_MMDC_P1_MDASP 0x021b4040 +#define MX6_MMDC_P1_MAPSR 0x021b4404 +#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800 +#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c +#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810 +#define MX6_MMDC_P1_MPODTCTRL 0x021b4818 +#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c +#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820 +#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824 +#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828 +#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c +#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840 +#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848 +#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850 +#define MX6_MMDC_P1_MPMUR0 0x021b48b8 + +#endif /*__ASM_ARCH_MX6_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h new file mode 100644 index 0000000..325da33 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2013 Boundary Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_MX6DLS_DDR_H__ +#define __ASM_ARCH_MX6DLS_DDR_H__ + +#ifndef CONFIG_MX6DL +#ifndef CONFIG_MX6S +#error "wrong CPU" +#endif +#endif + +#define MX6_IOM_DRAM_DQM0 0x020e0470 +#define MX6_IOM_DRAM_DQM1 0x020e0474 +#define MX6_IOM_DRAM_DQM2 0x020e0478 +#define MX6_IOM_DRAM_DQM3 0x020e047c +#define MX6_IOM_DRAM_DQM4 0x020e0480 +#define MX6_IOM_DRAM_DQM5 0x020e0484 +#define MX6_IOM_DRAM_DQM6 0x020e0488 +#define MX6_IOM_DRAM_DQM7 0x020e048c + +#define MX6_IOM_DRAM_CAS 0x020e0464 +#define MX6_IOM_DRAM_RAS 0x020e0490 +#define MX6_IOM_DRAM_RESET 0x020e0494 +#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac +#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0 +#define MX6_IOM_DRAM_SDBA2 0x020e04a0 +#define MX6_IOM_DRAM_SDCKE0 0x020e04a4 +#define MX6_IOM_DRAM_SDCKE1 0x020e04a8 +#define MX6_IOM_DRAM_SDODT0 0x020e04b4 +#define MX6_IOM_DRAM_SDODT1 0x020e04b8 + +#define MX6_IOM_DRAM_SDQS0 0x020e04bc +#define MX6_IOM_DRAM_SDQS1 0x020e04c0 +#define MX6_IOM_DRAM_SDQS2 0x020e04c4 +#define MX6_IOM_DRAM_SDQS3 0x020e04c8 +#define MX6_IOM_DRAM_SDQS4 0x020e04cc +#define MX6_IOM_DRAM_SDQS5 0x020e04d0 +#define MX6_IOM_DRAM_SDQS6 0x020e04d4 +#define MX6_IOM_DRAM_SDQS7 0x020e04d8 + +#define MX6_IOM_GRP_B0DS 0x020e0764 +#define MX6_IOM_GRP_B1DS 0x020e0770 +#define MX6_IOM_GRP_B2DS 0x020e0778 +#define MX6_IOM_GRP_B3DS 0x020e077c +#define MX6_IOM_GRP_B4DS 0x020e0780 +#define MX6_IOM_GRP_B5DS 0x020e0784 +#define MX6_IOM_GRP_B6DS 0x020e078c +#define MX6_IOM_GRP_B7DS 0x020e0748 +#define MX6_IOM_GRP_ADDDS 0x020e074c +#define MX6_IOM_DDRMODE_CTL 0x020e0750 +#define MX6_IOM_GRP_DDRPKE 0x020e0754 +#define MX6_IOM_GRP_DDRMODE 0x020e0760 +#define MX6_IOM_GRP_CTLDS 0x020e076c +#define MX6_IOM_GRP_DDR_TYPE 0x020e0774 + +#endif /*__ASM_ARCH_MX6S_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h new file mode 100644 index 0000000..e51727c --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2013 Boundary Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_MX6Q_DDR_H__ +#define __ASM_ARCH_MX6Q_DDR_H__ + +#ifndef CONFIG_MX6Q +#error "wrong CPU" +#endif + +#define MX6_IOM_DRAM_DQM0 0x020e05ac +#define MX6_IOM_DRAM_DQM1 0x020e05b4 +#define MX6_IOM_DRAM_DQM2 0x020e0528 +#define MX6_IOM_DRAM_DQM3 0x020e0520 +#define MX6_IOM_DRAM_DQM4 0x020e0514 +#define MX6_IOM_DRAM_DQM5 0x020e0510 +#define MX6_IOM_DRAM_DQM6 0x020e05bc +#define MX6_IOM_DRAM_DQM7 0x020e05c4 + +#define MX6_IOM_DRAM_CAS 0x020e056c +#define MX6_IOM_DRAM_RAS 0x020e0578 +#define MX6_IOM_DRAM_RESET 0x020e057c +#define MX6_IOM_DRAM_SDCLK_0 0x020e0588 +#define MX6_IOM_DRAM_SDCLK_1 0x020e0594 +#define MX6_IOM_DRAM_SDBA2 0x020e058c +#define MX6_IOM_DRAM_SDCKE0 0x020e0590 +#define MX6_IOM_DRAM_SDCKE1 0x020e0598 +#define MX6_IOM_DRAM_SDODT0 0x020e059c +#define MX6_IOM_DRAM_SDODT1 0x020e05a0 + +#define MX6_IOM_DRAM_SDQS0 0x020e05a8 +#define MX6_IOM_DRAM_SDQS1 0x020e05b0 +#define MX6_IOM_DRAM_SDQS2 0x020e0524 +#define MX6_IOM_DRAM_SDQS3 0x020e051c +#define MX6_IOM_DRAM_SDQS4 0x020e0518 +#define MX6_IOM_DRAM_SDQS5 0x020e050c +#define MX6_IOM_DRAM_SDQS6 0x020e05b8 +#define MX6_IOM_DRAM_SDQS7 0x020e05c0 + +#define MX6_IOM_GRP_B0DS 0x020e0784 +#define MX6_IOM_GRP_B1DS 0x020e0788 +#define MX6_IOM_GRP_B2DS 0x020e0794 +#define MX6_IOM_GRP_B3DS 0x020e079c +#define MX6_IOM_GRP_B4DS 0x020e07a0 +#define MX6_IOM_GRP_B5DS 0x020e07a4 +#define MX6_IOM_GRP_B6DS 0x020e07a8 +#define MX6_IOM_GRP_B7DS 0x020e0748 +#define MX6_IOM_GRP_ADDDS 0x020e074c +#define MX6_IOM_DDRMODE_CTL 0x020e0750 +#define MX6_IOM_GRP_DDRPKE 0x020e0758 +#define MX6_IOM_GRP_DDRMODE 0x020e0774 +#define MX6_IOM_GRP_CTLDS 0x020e078c +#define MX6_IOM_GRP_DDR_TYPE 0x020e0798 + +#endif /*__ASM_ARCH_MX6Q_DDR_H__ */ -- cgit v0.10.2 From 62db0b3d62366f1573d245a96d3ebbfa3bac118d Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sat, 23 Feb 2013 11:07:29 +0100 Subject: USB: drop unneeded header in ehci-mx6 Including header for pads is not needed and breaks board after renaming pin definitions. Series-to: u-boot Series-cc: marex@denx.de,fabio.estevam@freescale.com,eric.nelson@boundarydevices.com Signed-off-by: Stefano Babic diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 1b20e41..c1ae3d9 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include "ehci.h" -- cgit v0.10.2 From 5c2f444c9b061dcc4e7d9988c2cacf64bb4be4e8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 23 Feb 2013 02:42:57 +0000 Subject: mxs: Reset the EMI block on mx23 The real reason for memory instability was the fact that the EMI block was gated and not reset throughout the boards' operation. This patch resets the EMI block properly while also reverts the memory voltage bump. The memory stability issues were caused by the EMI not being reset properly and thus there is no longer need to run the memory at higher voltage than it ought to run at. This partly reverts 8303ed128a55519f19c5f11087032d4bc4e0537a . Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index f8392f6..4a0a5aa 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "mxs_init.h" @@ -229,7 +230,7 @@ static void mx23_mem_setup_vddmem(void) struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; - writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) | + writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) | POWER_VDDMEMCTRL_ENABLE_ILIMIT | POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_PULLDOWN_ACTIVE, @@ -237,13 +238,20 @@ static void mx23_mem_setup_vddmem(void) early_delay(10000); - writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) | + writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) | POWER_VDDMEMCTRL_ENABLE_LINREG, &power_regs->hw_power_vddmemctrl); } static void mx23_mem_init(void) { + /* + * Reset/ungate the EMI block. This is essential, otherwise the system + * suffers from memory instability. This thing is mx23 specific and is + * no longer present on mx28. + */ + mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE); + mx23_mem_setup_vddmem(); /* -- cgit v0.10.2 From 3430e0bd2aa5b94fdd5f7627172a5cb540776c9d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 23 Feb 2013 02:42:58 +0000 Subject: mxs: mmc: spi: dma: Better wrap the MXS differences This patch streamlines the differences between the MX23 and MX28 by implementing a few helper functions to handle different DMA channel mapping, different clock domain for SSP block and fixes a few minor bugs. First of all, the DMA channel mapping is now fixed in dma.h by defining the actual channel map for both MX23 and MX28. Thus, MX23 now does no longer use MX28 channel map which was wrong. Also, there is a fix for MX28 DMA channel map, where the last four channels were incorrect. Next, because correct DMA channel map is in place, the mxs_dma_init_channel() call now bases the channel ID starting from SSP port #0. This removes the need for DMA channel offset being added and cleans up the code. For the same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus no need to adjust dma channel number in the driver either. Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus() which handles the fact that MX23 has shared SSP clock for both ports, while MX28 has per-port SSP clock. Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the same functionality from MMC and SPI driver into common code. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 00b9aba..43e7663 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -289,7 +289,8 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp) void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq) { struct mxs_ssp_regs *ssp_regs; - const uint32_t sspclk = mxs_get_sspclk(bus); + const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus); + const uint32_t sspclk = mxs_get_sspclk(clk); uint32_t reg; uint32_t divide, rate, tgtclk; diff --git a/arch/arm/include/asm/arch-mxs/dma.h b/arch/arm/include/asm/arch-mxs/dma.h index a0a0ea5..1ac8696 100644 --- a/arch/arm/include/asm/arch-mxs/dma.h +++ b/arch/arm/include/asm/arch-mxs/dma.h @@ -40,6 +40,19 @@ /* * MXS DMA channels */ +#if defined(CONFIG_MX23) +enum { + MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP0, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_RESERVED0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_MAX_DMA_CHANNELS, +}; +#elif defined(CONFIG_MX28) enum { MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, MXS_DMA_CHANNEL_AHB_APBH_SSP1, @@ -53,9 +66,13 @@ enum { MXS_DMA_CHANNEL_AHB_APBH_GPMI5, MXS_DMA_CHANNEL_AHB_APBH_GPMI6, MXS_DMA_CHANNEL_AHB_APBH_GPMI7, - MXS_DMA_CHANNEL_AHB_APBH_SSP, + MXS_DMA_CHANNEL_AHB_APBH_HSADC, + MXS_DMA_CHANNEL_AHB_APBH_LCDIF, + MXS_DMA_CHANNEL_AHB_APBH_RESERVED0, + MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, MXS_MAX_DMA_CHANNELS, }; +#endif /* * MXS DMA hardware command. diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h index 9b30f56..5920f9b 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h @@ -74,6 +74,32 @@ struct mxs_ssp_regs { }; #endif +static inline int mxs_ssp_bus_id_valid(int bus) +{ +#if defined(CONFIG_MX23) + const unsigned int mxs_ssp_chan_count = 2; +#elif defined(CONFIG_MX28) + const unsigned int mxs_ssp_chan_count = 4; +#endif + + if (bus >= mxs_ssp_chan_count) + return 0; + + if (bus < 0) + return 0; + + return 1; +} + +static inline int mxs_ssp_clock_by_bus(unsigned int clock) +{ +#if defined(CONFIG_MX23) + return 0; +#elif defined(CONFIG_MX28) + return clock; +#endif +} + static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) { switch (port) { diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index a72f66c..b1537e2 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -53,12 +53,6 @@ struct mxsmmc_priv { struct mxs_dma_desc *desc; }; -#if defined(CONFIG_MX23) -static const unsigned int mxsmmc_id_offset = 1; -#elif defined(CONFIG_MX28) -static const unsigned int mxsmmc_id_offset = 0; -#endif - #define MXSMMC_MAX_TIMEOUT 10000 #define MXSMMC_SMALL_TRANSFER 512 @@ -137,7 +131,7 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | (data_count << MXS_DMA_DESC_BYTES_OFFSET); - dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id + mxsmmc_id_offset; + dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; mxs_dma_desc_append(dmach, priv->desc); if (mxs_dma_go(dmach)) { bounce_buffer_stop(&bbstate); @@ -390,15 +384,9 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) struct mmc *mmc = NULL; struct mxsmmc_priv *priv = NULL; int ret; -#if defined(CONFIG_MX23) - const unsigned int mxsmmc_max_id = 2; - const unsigned int mxsmmc_clk_id = 0; -#elif defined(CONFIG_MX28) - const unsigned int mxsmmc_max_id = 4; - const unsigned int mxsmmc_clk_id = id; -#endif + const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id); - if (id >= mxsmmc_max_id) + if (!mxs_ssp_bus_id_valid(id)) return -ENODEV; mmc = malloc(sizeof(struct mmc)); @@ -418,7 +406,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) return -ENOMEM; } - ret = mxs_dma_init_channel(id + mxsmmc_id_offset); + ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id); if (ret) return ret; diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index bb865b7..6acc95a 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -70,7 +70,7 @@ void spi_init(void) int spi_cs_is_valid(unsigned int bus, unsigned int cs) { /* MXS SPI: 4 ports and 3 chip selects maximum */ - if (bus > 3 || cs > 2) + if (!mxs_ssp_bus_id_valid(bus) || cs > 2) return 0; else return 1; @@ -92,7 +92,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!mxs_slave) return NULL; - if (mxs_dma_init_channel(bus)) + if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus)) goto err_init; mxs_slave->slave.bus = bus; -- cgit v0.10.2 From c96e78ccfe81394d87cbff855f40f5d7cd377811 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 23 Feb 2013 02:42:59 +0000 Subject: mxs: spi: Fix the MXS SPI for mx23 The MX23 has slightly different register layout. Adjust the SPI driver to match the layout, both the PIO and DMA part. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 6acc95a..b5b32dc 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -168,7 +168,12 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave, while (length--) { /* We transfer 1 byte */ +#if defined(CONFIG_MX23) + writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr); + writel(1, &ssp_regs->hw_ssp_ctrl0_set); +#elif defined(CONFIG_MX28) writel(1, &ssp_regs->hw_ssp_xfer_size); +#endif if ((flags & SPI_XFER_END) && !length) mxs_spi_end_xfer(ssp_regs); @@ -226,6 +231,12 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, int tl; int ret = 0; +#if defined(CONFIG_MX23) + const int mxs_spi_pio_words = 1; +#elif defined(CONFIG_MX28) + const int mxs_spi_pio_words = 4; +#endif + ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count); memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count); @@ -281,7 +292,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, dp->cmd.data |= ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) | - (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | + (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) | MXS_DMA_DESC_HALT_ON_TERMINATE | MXS_DMA_DESC_TERMINATE_FLUSH; @@ -298,15 +309,19 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, } /* - * Write CTRL0, CMD0, CMD1, XFER_SIZE registers. It is + * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in + * case of MX28, write only CTRL0 in case of MX23 due + * to the difference in register layout. It is utterly * essential that the XFER_SIZE register is written on * a per-descriptor basis with the same size as is the * descriptor! */ dp->cmd.pio_words[0] = ctrl0; +#ifdef CONFIG_MX28 dp->cmd.pio_words[1] = 0; dp->cmd.pio_words[2] = 0; dp->cmd.pio_words[3] = tl; +#endif mxs_dma_desc_append(dmach, dp); -- cgit v0.10.2 From d3f26a27003d55ce17ca54e84799fa18b965c3dc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 23 Feb 2013 02:43:00 +0000 Subject: mxs: spi: Remove CONFIG_MXS_SPI_DMA_ENABLE The CONFIG_MXS_SPI_DMA_ENABLE is no longer relevant as the SPI DMA has proven to work correctly. Remove this configuration option. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index b5b32dc..ffa3c1d 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -40,17 +40,6 @@ #define MXSSSP_SMALL_TRANSFER 512 -/* - * CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI - * host. Use with utmost caution! - * - * Enabling this is not yet recommended since this - * still doesn't support transfers to/from unaligned - * addresses. Therefore this driver will not work - * for example with saving environment. This is - * caused by DMA alignment constraints on MXS. - */ - struct mxs_spi_slave { struct spi_slave slave; uint32_t max_khz; @@ -347,12 +336,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, char dummy; int write = 0; char *data = NULL; - -#ifdef CONFIG_MXS_SPI_DMA_ENABLE int dma = 1; -#else - int dma = 0; -#endif if (bitlen == 0) { if (flags & SPI_XFER_END) { diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 1b51fe2..59a7be9 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -244,7 +244,6 @@ #ifdef CONFIG_CMD_SPI #define CONFIG_HARD_SPI #define CONFIG_MXS_SPI -#define CONFIG_MXS_SPI_DMA_ENABLE #define CONFIG_SPI_HALF_DUPLEX #define CONFIG_DEFAULT_SPI_BUS 2 #define CONFIG_DEFAULT_SPI_CS 0 diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 71447d9..6a46f3c 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -202,7 +202,6 @@ #ifdef CONFIG_CMD_SPI #define CONFIG_HARD_SPI #define CONFIG_MXS_SPI -#define CONFIG_MXS_SPI_DMA_ENABLE #define CONFIG_SPI_HALF_DUPLEX #define CONFIG_DEFAULT_SPI_BUS 2 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 -- cgit v0.10.2 From 47f13315061b4f931a9263924627b870ec083578 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 23 Feb 2013 02:43:01 +0000 Subject: mxs: Squash the header file usage in ehci-mxs The ehci-mxs driver included the register definitions directly. Use imx-regs.h instead since it contains proper handling of the differences between mx23 and mx28. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic Acked-by: Otavio Salvador diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h index 05eb63c..8f67497 100644 --- a/arch/arm/include/asm/arch-mxs/imx-regs.h +++ b/arch/arm/include/asm/arch-mxs/imx-regs.h @@ -36,6 +36,8 @@ #include #include #include +#include +#include #ifdef CONFIG_MX23 #include diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 5062af5..0ca7545 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -21,11 +21,7 @@ #include #include -#include -#include -#include -#include -#include +#include #include "ehci.h" -- cgit v0.10.2 From afa872109942b37fce291b592d6f2f02f55a4021 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 23 Feb 2013 02:43:02 +0000 Subject: mxs: Make ehci-mxs multiport capable Rework ehci-mxs so it supports both ports on MX28. It was necessary to wrap the per-port configuration into struct ehci_mxs_port and pull out the clock configuration function. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 0ca7545..f320d3e 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -22,86 +22,106 @@ #include #include #include +#include #include "ehci.h" -#if (CONFIG_EHCI_MXS_PORT != 0) && (CONFIG_EHCI_MXS_PORT != 1) -#error "MXS EHCI: Invalid port selected!" -#endif - -#ifndef CONFIG_EHCI_MXS_PORT -#error "MXS EHCI: Please define correct port using CONFIG_EHCI_MXS_PORT!" -#endif +/* This DIGCTL register ungates clock to USB */ +#define HW_DIGCTL_CTRL 0x8001c000 +#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2) +#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16) -static struct ehci_mxs { - struct mxs_usb_regs *usb_regs; +struct ehci_mxs_port { + uint32_t usb_regs; struct mxs_usbphy_regs *phy_regs; -} ehci_mxs; -int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port) + struct mxs_register_32 *pll; + uint32_t pll_en_bits; + uint32_t pll_dis_bits; + uint32_t gate_bits; +}; + +static const struct ehci_mxs_port mxs_port[] = { +#ifdef CONFIG_EHCI_MXS_PORT0 + { + MXS_USBCTRL0_BASE, + (struct mxs_usbphy_regs *)MXS_USBPHY0_BASE, + (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + + offsetof(struct mxs_clkctrl_regs, + hw_clkctrl_pll0ctrl0_reg)), + CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, + CLKCTRL_PLL0CTRL0_EN_USB_CLKS, + HW_DIGCTL_CTRL_USB0_CLKGATE, + }, +#endif +#ifdef CONFIG_EHCI_MXS_PORT1 + { + MXS_USBCTRL1_BASE, + (struct mxs_usbphy_regs *)MXS_USBPHY1_BASE, + (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + + offsetof(struct mxs_clkctrl_regs, + hw_clkctrl_pll1ctrl0_reg)), + CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER, + CLKCTRL_PLL1CTRL0_EN_USB_CLKS, + HW_DIGCTL_CTRL_USB1_CLKGATE, + }, +#endif +}; + +static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable) { - uint32_t usb_base, phy_base; - switch (port) { - case 0: - usb_base = MXS_USBCTRL0_BASE; - phy_base = MXS_USBPHY0_BASE; - break; - case 1: - usb_base = MXS_USBCTRL1_BASE; - phy_base = MXS_USBPHY1_BASE; - break; - default: - printf("CONFIG_EHCI_MXS_PORT (port = %d)\n", port); - return -1; + struct mxs_register_32 *digctl_ctrl = + (struct mxs_register_32 *)HW_DIGCTL_CTRL; + int pll_offset, dig_offset; + + if (enable) { + pll_offset = offsetof(struct mxs_register_32, reg_set); + dig_offset = offsetof(struct mxs_register_32, reg_clr); + writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset); + writel(port->pll_en_bits, (u32)port->pll + pll_offset); + } else { + pll_offset = offsetof(struct mxs_register_32, reg_clr); + dig_offset = offsetof(struct mxs_register_32, reg_set); + writel(port->pll_dis_bits, (u32)port->pll + pll_offset); + writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset); } - mxs_usb->usb_regs = (struct mxs_usb_regs *)usb_base; - mxs_usb->phy_regs = (struct mxs_usbphy_regs *)phy_base; return 0; } -/* This DIGCTL register ungates clock to USB */ -#define HW_DIGCTL_CTRL 0x8001c000 -#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2) -#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16) - int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { int ret; uint32_t usb_base, cap_base; - struct mxs_register_32 *digctl_ctrl = - (struct mxs_register_32 *)HW_DIGCTL_CTRL; - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + const struct ehci_mxs_port *port; - ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT); - if (ret) - return ret; + if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { + printf("Invalid port index (index = %d)!\n", index); + return -EINVAL; + } + + port = &mxs_port[index]; /* Reset the PHY block */ - writel(USBPHY_CTRL_SFTRST, &ehci_mxs.phy_regs->hw_usbphy_ctrl_set); + writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set); udelay(10); writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, - &ehci_mxs.phy_regs->hw_usbphy_ctrl_clr); + &port->phy_regs->hw_usbphy_ctrl_clr); /* Enable USB clock */ - writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); - writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll1ctrl0_set); - - writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE, - &digctl_ctrl->reg_clr); + ret = ehci_mxs_toggle_clock(port, 1); + if (ret) + return ret; /* Start USB PHY */ - writel(0, &ehci_mxs.phy_regs->hw_usbphy_pwd); + writel(0, &port->phy_regs->hw_usbphy_pwd); /* Enable UTMI+ Level 2 and Level 3 compatibility */ writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1, - &ehci_mxs.phy_regs->hw_usbphy_ctrl_set); + &port->phy_regs->hw_usbphy_ctrl_set); - usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100; + usb_base = port->usb_regs + 0x100; *hccr = (struct ehci_hccr *)usb_base; cap_base = ehci_readl(&(*hccr)->cr_capbase); @@ -114,19 +134,19 @@ int ehci_hcd_stop(int index) { int ret; uint32_t usb_base, cap_base, tmp; - struct mxs_register_32 *digctl_ctrl = - (struct mxs_register_32 *)HW_DIGCTL_CTRL; - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct ehci_hccr *hccr; struct ehci_hcor *hcor; + const struct ehci_mxs_port *port; - ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT); - if (ret) - return ret; + if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { + printf("Invalid port index (index = %d)!\n", index); + return -EINVAL; + } + + port = &mxs_port[index]; /* Stop the USB port */ - usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100; + usb_base = port->usb_regs + 0x100; hccr = (struct ehci_hccr *)usb_base; cap_base = ehci_readl(&hccr->cr_capbase); hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base)); @@ -140,17 +160,10 @@ int ehci_hcd_stop(int index) USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV | USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS | USBPHY_PWD_TXPWDFS; - writel(tmp, &ehci_mxs.phy_regs->hw_usbphy_pwd); + writel(tmp, &port->phy_regs->hw_usbphy_pwd); /* Disable USB clock */ - writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS, - &clkctrl_regs->hw_clkctrl_pll0ctrl0_clr); - writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS, - &clkctrl_regs->hw_clkctrl_pll1ctrl0_clr); + ret = ehci_mxs_toggle_clock(port, 0); - /* Gate off the USB clock */ - writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE, - &digctl_ctrl->reg_set); - - return 0; + return ret; } diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index 73c66af..18c4241 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -182,7 +182,8 @@ #ifdef CONFIG_CMD_USB #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MXS -#define CONFIG_EHCI_MXS_PORT 1 +#define CONFIG_EHCI_MXS_PORT1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 59a7be9..f2725cc 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -233,7 +233,9 @@ #ifdef CONFIG_CMD_USB #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MXS -#define CONFIG_EHCI_MXS_PORT 1 +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_EHCI_MXS_PORT1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 6a46f3c..0d918a1 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -181,7 +181,8 @@ #ifdef CONFIG_CMD_USB #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MXS -#define CONFIG_EHCI_MXS_PORT 1 +#define CONFIG_EHCI_MXS_PORT1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index decf8d9..349497f 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -170,7 +170,8 @@ #ifdef CONFIG_CMD_USB #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MXS -#define CONFIG_EHCI_MXS_PORT 0 +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif -- cgit v0.10.2 From f94669f30656cd05bbc75f6c799a1b06c493f3d2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 23 Feb 2013 02:43:03 +0000 Subject: mxs: m28: Enable power to USB port 0 The USB port 0 can now be used alongside the USB port 1, thus enable power to it. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Otavio Salvador Cc: Stefano Babic diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index d93efaf..aff7c1f 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -57,6 +57,10 @@ int board_early_init_f(void) mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 | MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0); + + mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 | + MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); + gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0); #endif return 0; -- cgit v0.10.2 From a74dbf2734e8c86220dea159c242149d9acc61e1 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 23 Feb 2013 02:43:04 +0000 Subject: mxs: Rename CONFIG_SPL_MX28_PSWITCH_WAIT to CONFIG_SPL_MXS_PSWITCH_WAIT The power switch option is compatible with i.MX23 and i.MX28 so the configration option needs to reflect it. We choose 'CONFIG_SPL_MXS_PSWITCH_WAIT' for the option name. Signed-off-by: Otavio Salvador Acked-by: Marek Vasut diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h index 2ddc5bc..084def5 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h +++ b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h @@ -30,7 +30,7 @@ void early_delay(int delay); void mxs_power_init(void); -#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT void mxs_power_wait_pswitch(void); #else static inline void mxs_power_wait_pswitch(void) { } diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index e9d6302..287c698 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -921,7 +921,7 @@ void mxs_power_init(void) early_delay(1000); } -#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT void mxs_power_wait_pswitch(void) { struct mxs_power_regs *power_regs = -- cgit v0.10.2 From 89075d3f4f5550638f0bf656046af5ca0306bdd7 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 23 Feb 2013 02:43:05 +0000 Subject: mx23: Document the tRAS lockout setting in memory initialization Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to enable the 'Fast Auto Pre-Charge' found in the memory chip. The setting is applied after memory initialization and it is worth document it. Signed-off-by: Otavio Salvador diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 4a0a5aa..fdac73c 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -120,6 +120,10 @@ static void initialize_dram_values(void) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); #ifdef CONFIG_MX23 + /* + * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last + * element to be set + */ writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); #endif } -- cgit v0.10.2 From 920178d38133e76da8b0394b0d3f088e7afbaee7 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 23 Feb 2013 02:43:06 +0000 Subject: mx23evk: Adjust DRAM control register to use full 128MB of RAM Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full 128MB of RAM. Signed-off-by: Otavio Salvador diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c index 6007433..b6f4e7e 100644 --- a/board/freescale/mx23evk/spl_boot.c +++ b/board/freescale/mx23evk/spl_boot.c @@ -98,6 +98,16 @@ const iomux_cfg_t iomux_setup[] = { (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), }; +#define HW_DRAM_CTL14 (0x38 >> 2) +#define CS_MAP 0x3 +#define INTAREF 0x2 +#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP) + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG; +} + void board_init_ll(void) { mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); -- cgit v0.10.2 From af73034c6ba131a93ed215098f43595637ef6ac3 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 23 Feb 2013 02:43:07 +0000 Subject: led: Use STATUS_LED_ON and STATUS_LED_OFF when calling __led_set This fixes the gpio_led driver which needs to compare againt a STATUS_LED_ON to enable a led. Signed-off-by: Otavio Salvador diff --git a/common/cmd_led.c b/common/cmd_led.c index 7f5ab43..84f79fa 100644 --- a/common/cmd_led.c +++ b/common/cmd_led.c @@ -110,13 +110,15 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (led_commands[i].on) led_commands[i].on(); else - __led_set(led_commands[i].mask, 1); + __led_set(led_commands[i].mask, + STATUS_LED_ON); break; case LED_OFF: if (led_commands[i].off) led_commands[i].off(); else - __led_set(led_commands[i].mask, 0); + __led_set(led_commands[i].mask, + STATUS_LED_OFF); break; case LED_TOGGLE: if (led_commands[i].toggle) -- cgit v0.10.2 From eb2996024b1592f77454302213d5bf0659684c7b Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 23 Feb 2013 02:43:08 +0000 Subject: mxs: Fix iomux.h to not break build during assembly stage This fixes the build failure when included in mx23_olinuxino.h board config; the addition of "asm/types.h" is due "u32" being otherwise undefined. Signed-off-by: Otavio Salvador diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h index 7abdf58..4288715 100644 --- a/arch/arm/include/asm/arch-mxs/iomux.h +++ b/arch/arm/include/asm/arch-mxs/iomux.h @@ -21,6 +21,10 @@ #ifndef __MACH_MXS_IOMUX_H__ #define __MACH_MXS_IOMUX_H__ +#ifndef __ASSEMBLY__ + +#include + /* * IOMUX/PAD Bit field definitions * @@ -165,4 +169,5 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad); */ int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); +#endif /* __ASSEMBLY__ */ #endif /* __MACH_MXS_IOMUX_H__*/ -- cgit v0.10.2 From 36c7c9250d7c4717808a637da74e59a29a235848 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 23 Feb 2013 02:43:09 +0000 Subject: mx23_olinuxino: Add support for status LED This allow user to know if the bootloader is running, even without a serial console. Signed-off-by: Otavio Salvador diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 6a6053b..2501417 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -28,6 +28,9 @@ #include #include #include +#ifdef CONFIG_STATUS_LED +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -67,5 +70,9 @@ int board_init(void) /* Adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_STATE); +#endif + return 0; } diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index 7def8bc..3bbf5ad 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -84,6 +84,10 @@ const iomux_cfg_t iomux_setup[] = { MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + /* Green LED */ + MX23_PAD_SSP1_DETECT__GPIO_2_1 | + (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL), + /* MMC 0 */ MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP, MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP, diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index 7983c5d..d019944 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -19,6 +19,8 @@ #ifndef __MX23_OLINUXINO_CONFIG_H__ #define __MX23_OLINUXINO_CONFIG_H__ +#include + /* * SoC configurations */ @@ -56,6 +58,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_GPIO +#define CONFIG_CMD_LED #define CONFIG_CMD_MMC /* @@ -112,6 +115,17 @@ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ /* + * Status LED + */ +#define CONFIG_STATUS_LED +#define CONFIG_GPIO_LED +#define CONFIG_BOARD_SPECIFIC_LED +#define STATUS_LED_BOOT 0 +#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1 +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) + +/* * MMC Driver */ #ifdef CONFIG_CMD_MMC -- cgit v0.10.2 From 6ecd05d2f5bec0a1a70367b1750f52dc2f1f4382 Mon Sep 17 00:00:00 2001 From: Fadil Berisha Date: Wed, 27 Feb 2013 17:00:07 +0000 Subject: mxs: timrot: Add support to i.MX23 This patch add timer support to i.MX23 and complete bit fields and values on regs-timrot.h. Testet on imx23-olinuxino board. Signed-off-by: Fadil Berisha Acked-by: Marek Vasut Cc: Marek Vasut Cc: Otavio Salvador Cc: Fabio Estevam Cc: Stefano Babic Acked-by: Otavio Salvador diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 3738411..2a95bcb 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -32,7 +32,11 @@ #include /* Maximum fixed count */ -#define TIMER_LOAD_VAL 0xffffffff +#if defined(CONFIG_MX23) +#define TIMER_LOAD_VAL 0xffff +#elif defined(CONFIG_MX28) +#define TIMER_LOAD_VAL 0xffffffff +#endif DECLARE_GLOBAL_DATA_PTR; @@ -69,7 +73,11 @@ int timer_init(void) mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); /* Set fixed_count to 0 */ +#if defined(CONFIG_MX23) + writel(0, &timrot_regs->hw_timrot_timcount0); +#elif defined(CONFIG_MX28) writel(0, &timrot_regs->hw_timrot_fixed_count0); +#endif /* Set UPDATE bit and 1Khz frequency */ writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD | @@ -77,7 +85,11 @@ int timer_init(void) &timrot_regs->hw_timrot_timctrl0); /* Set fixed_count to maximal value */ +#if defined(CONFIG_MX23) + writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0); +#elif defined(CONFIG_MX28) writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); +#endif return 0; } @@ -86,9 +98,16 @@ unsigned long long get_ticks(void) { struct mxs_timrot_regs *timrot_regs = (struct mxs_timrot_regs *)MXS_TIMROT_BASE; + uint32_t now; /* Current tick value */ - uint32_t now = readl(&timrot_regs->hw_timrot_running_count0); +#if defined(CONFIG_MX23) + /* Upper bits are the valid ones. */ + now = readl(&timrot_regs->hw_timrot_timcount0) >> + TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET; +#elif defined(CONFIG_MX28) + now = readl(&timrot_regs->hw_timrot_running_count0); +#endif if (lastdec >= now) { /* diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h index 529a3bc..f8537f1 100644 --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h @@ -31,6 +31,16 @@ struct mxs_timrot_regs { mxs_reg_32(hw_timrot_rotctrl) mxs_reg_32(hw_timrot_rotcount) +#if defined(CONFIG_MX23) + mxs_reg_32(hw_timrot_timctrl0) + mxs_reg_32(hw_timrot_timcount0) + mxs_reg_32(hw_timrot_timctrl1) + mxs_reg_32(hw_timrot_timcount1) + mxs_reg_32(hw_timrot_timctrl2) + mxs_reg_32(hw_timrot_timcount2) + mxs_reg_32(hw_timrot_timctrl3) + mxs_reg_32(hw_timrot_timcount3) +#elif defined(CONFIG_MX28) mxs_reg_32(hw_timrot_timctrl0) mxs_reg_32(hw_timrot_running_count0) mxs_reg_32(hw_timrot_fixed_count0) @@ -47,6 +57,7 @@ struct mxs_timrot_regs { mxs_reg_32(hw_timrot_running_count3) mxs_reg_32(hw_timrot_fixed_count3) mxs_reg_32(hw_timrot_match_count3) +#endif mxs_reg_32(hw_timrot_version) }; #endif @@ -71,7 +82,11 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) #define TIMROT_ROTCTRL_POLARITY_B (1 << 9) #define TIMROT_ROTCTRL_POLARITY_A (1 << 8) +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) +#elif defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) +#endif #define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 #define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) @@ -79,12 +94,21 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) +#elif defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) #define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) #define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) +#endif +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 +#elif defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_A_MASK 0xf +#endif #define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 #define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 #define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 @@ -92,18 +116,25 @@ struct mxs_timrot_regs { #define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 #define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 #define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 +#if defined(CONFIG_MX23) +#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 +#elif defined(CONFIG_MX28) #define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 #define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 #define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 #define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 #define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa +#endif #define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff #define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 #define TIMROT_TIMCTRLn_IRQ (1 << 15) #define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) +#if defined(CONFIG_MX28) #define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) +#endif #define TIMROT_TIMCTRLn_POLARITY (1 << 8) #define TIMROT_TIMCTRLn_UPDATE (1 << 7) #define TIMROT_TIMCTRLn_RELOAD (1 << 6) @@ -121,6 +152,15 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 #define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 #define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 +#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 +#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 +#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9 +#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa +#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb +#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc +#elif defined(CONFIG_MX28) #define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 #define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 #define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 @@ -131,15 +171,28 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd #define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe #define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf +#endif +#if defined(CONFIG_MX23) +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 +#elif defined(CONFIG_MX28) #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff #define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 +#endif +#if defined(CONFIG_MX23) +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 +#elif defined(CONFIG_MX28) #define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff #define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 +#endif +#if defined(CONFIG_MX28) #define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff #define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 +#endif #define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 @@ -149,6 +202,15 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) +#elif defined(CONFIG_MX28) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) @@ -159,7 +221,46 @@ struct mxs_timrot_regs { #define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) #define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) +#endif +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRL3_IRQ (1 << 15) +#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) +#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) +#endif #define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) +#if defined(CONFIG_MX23) +#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) +#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 +#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) +#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) +#define TIMROT_TIMCTRL3_UPDATE (1 << 7) +#define TIMROT_TIMCTRL3_RELOAD (1 << 6) +#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4) +#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4) +#define TIMROT_TIMCTRL3_SELECT_MASK 0xf +#define TIMROT_TIMCTRL3_SELECT_OFFSET 0 +#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0 +#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1 +#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2 +#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3 +#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4 +#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5 +#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6 +#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7 +#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8 +#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9 +#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa +#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb +#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc +#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16) +#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16 +#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff +#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0 +#endif #define TIMROT_VERSION_MAJOR_MASK (0xff << 24) #define TIMROT_VERSION_MAJOR_OFFSET 24 -- cgit v0.10.2 From e895aa45b93a2d27e6720c40f869c01854d3ca09 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 2 Mar 2013 05:17:28 +0000 Subject: mx23evk: Enable USB support This enabled USB support for the mx23evk board. Signed-off-by: Otavio Salvador diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index d206c95..e5a15a4 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -58,6 +58,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_GPIO #define CONFIG_CMD_MMC +#define CONFIG_CMD_USB #define CONFIG_CMD_BOOTZ /* Memory configurations */ @@ -122,6 +123,16 @@ #define CONFIG_MXS_MMC #endif +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MXS +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#endif + /* Boot Linux */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -- cgit v0.10.2 From ebe1d17006001adfa375335acdd56f326264aeb8 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 2 Mar 2013 05:17:29 +0000 Subject: mx23_olinuxino: Enable USB support This enabled USB support for the mx23_olinuxino board. Signed-off-by: Otavio Salvador diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 2501417..9252717 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -45,6 +45,11 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); +#ifdef CONFIG_CMD_USB + /* Enable LAN9512 */ + gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1); +#endif + return 0; } diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index 3bbf5ad..a96c293 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -95,6 +95,10 @@ const iomux_cfg_t iomux_setup[] = { MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP, MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP, MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP, + + /* Ethernet */ + MX23_PAD_GPMI_ALE__GPIO_0_17 | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), }; void board_init_ll(void) diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index d019944..90dda01 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -60,6 +60,7 @@ #define CONFIG_CMD_GPIO #define CONFIG_CMD_LED #define CONFIG_CMD_MMC +#define CONFIG_CMD_USB /* * Memory configurations @@ -140,6 +141,16 @@ */ #define CONFIG_APBH_DMA +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MXS +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#endif + /* * Boot Linux */ -- cgit v0.10.2 From b8bd75af77e125133f004a26cbc3b008f7feea52 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 2 Mar 2013 05:17:30 +0000 Subject: mx23_olinuxino: Add ethernet support This adds support to the LAN9512 chip included in the board and extend the environment to easy netboot use. Signed-off-by: Otavio Salvador diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index 90dda01..03893d7 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -55,11 +55,13 @@ #define CONFIG_DOS_PARTITION #define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_GPIO #define CONFIG_CMD_LED #define CONFIG_CMD_MMC +#define CONFIG_CMD_NET #define CONFIG_CMD_USB /* @@ -151,6 +153,12 @@ #define CONFIG_USB_STORAGE #endif +/* Ethernet */ +#ifdef CONFIG_CMD_NET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#endif + /* * Boot Linux */ @@ -192,6 +200,7 @@ "fdt_file=imx23-olinuxino.dtb\0" \ "fdt_addr=0x41000000\0" \ "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ "mmcdev=0\0" \ "mmcpart=2\0" \ "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ @@ -217,6 +226,31 @@ "fi; " \ "else " \ "bootm; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "usb start; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "if test ${boot_fdt} = yes; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi;" \ + "fi; " \ + "else " \ + "bootm; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -226,10 +260,9 @@ "else " \ "if run loaduimage; then " \ "run mmcboot; " \ - "else " \ - "echo ERR: Fail to boot from MMC; " \ + "else run netboot; " \ "fi; " \ "fi; " \ - "else exit; fi" + "else run netboot; fi" #endif /* __MX23_OLINUXINO_CONFIG_H__ */ -- cgit v0.10.2 From 3e9dc930514a4433b445cbf16f128a44c4775063 Mon Sep 17 00:00:00 2001 From: Fadil Berisha Date: Thu, 28 Feb 2013 10:03:26 -0500 Subject: mxs: timrot: Rename local macros Local macros apply to both iMX23 and iMX28. This patch renames local macros with attribute MX28 to MXS. Signed-off-by: Fadil Berisha Cc: Marek Vasut Cc: Otavio Salvador Cc: Fabio Estevam Cc: Stefano Babic diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 2a95bcb..2039106 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -46,22 +46,22 @@ DECLARE_GLOBAL_DATA_PTR; /* * This driver uses 1kHz clock source. */ -#define MX28_INCREMENTER_HZ 1000 +#define MXS_INCREMENTER_HZ 1000 static inline unsigned long tick_to_time(unsigned long tick) { - return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); + return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); } static inline unsigned long time_to_tick(unsigned long time) { - return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ); + return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); } /* Calculate how many ticks happen in "us" microseconds */ static inline unsigned long us_to_tick(unsigned long us) { - return (us * MX28_INCREMENTER_HZ) / 1000000; + return (us * MXS_INCREMENTER_HZ) / 1000000; } int timer_init(void) @@ -136,17 +136,17 @@ ulong get_timer(ulong base) } /* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ -#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0 +#define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0 void __udelay(unsigned long usec) { uint32_t old, new, incr; uint32_t counter = 0; - old = readl(MX28_HW_DIGCTL_MICROSECONDS); + old = readl(MXS_HW_DIGCTL_MICROSECONDS); while (counter < usec) { - new = readl(MX28_HW_DIGCTL_MICROSECONDS); + new = readl(MXS_HW_DIGCTL_MICROSECONDS); /* Check if the timer wrapped. */ if (new < old) { @@ -171,5 +171,5 @@ void __udelay(unsigned long usec) ulong get_tbclk(void) { - return MX28_INCREMENTER_HZ; + return MXS_INCREMENTER_HZ; } -- cgit v0.10.2 From 1b097cff51a6781ce3a0036b7f0a9e53864c9727 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 28 Feb 2013 14:35:02 +0000 Subject: mx6: Provide a structure for accessing HDMI registers Provide a structure for accessing HDMI registers, so that we can use proper read/write accessors. Signed-off-by: Fabio Estevam Tested-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h index 02a413f..9dccb3f 100644 --- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h +++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h @@ -24,542 +24,553 @@ /* * Hdmi controller registers */ - -/* Identification Registers */ -#define HDMI_DESIGN_ID 0x0000 -#define HDMI_REVISION_ID 0x0001 -#define HDMI_PRODUCT_ID0 0x0002 -#define HDMI_PRODUCT_ID1 0x0003 -#define HDMI_CONFIG0_ID 0x0004 -#define HDMI_CONFIG1_ID 0x0005 -#define HDMI_CONFIG2_ID 0x0006 -#define HDMI_CONFIG3_ID 0x0007 - -/* Interrupt Registers */ -#define HDMI_IH_FC_STAT0 0x0100 -#define HDMI_IH_FC_STAT1 0x0101 -#define HDMI_IH_FC_STAT2 0x0102 -#define HDMI_IH_AS_STAT0 0x0103 -#define HDMI_IH_PHY_STAT0 0x0104 -#define HDMI_IH_I2CM_STAT0 0x0105 -#define HDMI_IH_CEC_STAT0 0x0106 -#define HDMI_IH_VP_STAT0 0x0107 -#define HDMI_IH_I2CMPHY_STAT0 0x0108 -#define HDMI_IH_AHBDMAAUD_STAT0 0x0109 - -#define HDMI_IH_MUTE_FC_STAT0 0x0180 -#define HDMI_IH_MUTE_FC_STAT1 0x0181 -#define HDMI_IH_MUTE_FC_STAT2 0x0182 -#define HDMI_IH_MUTE_AS_STAT0 0x0183 -#define HDMI_IH_MUTE_PHY_STAT0 0x0184 -#define HDMI_IH_MUTE_I2CM_STAT0 0x0185 -#define HDMI_IH_MUTE_CEC_STAT0 0x0186 -#define HDMI_IH_MUTE_VP_STAT0 0x0187 -#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 -#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 -#define HDMI_IH_MUTE 0x01FF - -/* Video Sample Registers */ -#define HDMI_TX_INVID0 0x0200 -#define HDMI_TX_INSTUFFING 0x0201 -#define HDMI_TX_GYDATA0 0x0202 -#define HDMI_TX_GYDATA1 0x0203 -#define HDMI_TX_RCRDATA0 0x0204 -#define HDMI_TX_RCRDATA1 0x0205 -#define HDMI_TX_BCBDATA0 0x0206 -#define HDMI_TX_BCBDATA1 0x0207 - -/* Video Packetizer Registers */ -#define HDMI_VP_STATUS 0x0800 -#define HDMI_VP_PR_CD 0x0801 -#define HDMI_VP_STUFF 0x0802 -#define HDMI_VP_REMAP 0x0803 -#define HDMI_VP_CONF 0x0804 -#define HDMI_VP_STAT 0x0805 -#define HDMI_VP_INT 0x0806 -#define HDMI_VP_MASK 0x0807 -#define HDMI_VP_POL 0x0808 - -/* Frame Composer Registers */ -#define HDMI_FC_INVIDCONF 0x1000 -#define HDMI_FC_INHACTV0 0x1001 -#define HDMI_FC_INHACTV1 0x1002 -#define HDMI_FC_INHBLANK0 0x1003 -#define HDMI_FC_INHBLANK1 0x1004 -#define HDMI_FC_INVACTV0 0x1005 -#define HDMI_FC_INVACTV1 0x1006 -#define HDMI_FC_INVBLANK 0x1007 -#define HDMI_FC_HSYNCINDELAY0 0x1008 -#define HDMI_FC_HSYNCINDELAY1 0x1009 -#define HDMI_FC_HSYNCINWIDTH0 0x100A -#define HDMI_FC_HSYNCINWIDTH1 0x100B -#define HDMI_FC_VSYNCINDELAY 0x100C -#define HDMI_FC_VSYNCINWIDTH 0x100D -#define HDMI_FC_INFREQ0 0x100E -#define HDMI_FC_INFREQ1 0x100F -#define HDMI_FC_INFREQ2 0x1010 -#define HDMI_FC_CTRLDUR 0x1011 -#define HDMI_FC_EXCTRLDUR 0x1012 -#define HDMI_FC_EXCTRLSPAC 0x1013 -#define HDMI_FC_CH0PREAM 0x1014 -#define HDMI_FC_CH1PREAM 0x1015 -#define HDMI_FC_CH2PREAM 0x1016 -#define HDMI_FC_AVICONF3 0x1017 -#define HDMI_FC_GCP 0x1018 -#define HDMI_FC_AVICONF0 0x1019 -#define HDMI_FC_AVICONF1 0x101A -#define HDMI_FC_AVICONF2 0x101B -#define HDMI_FC_AVIVID 0x101C -#define HDMI_FC_AVIETB0 0x101D -#define HDMI_FC_AVIETB1 0x101E -#define HDMI_FC_AVISBB0 0x101F -#define HDMI_FC_AVISBB1 0x1020 -#define HDMI_FC_AVIELB0 0x1021 -#define HDMI_FC_AVIELB1 0x1022 -#define HDMI_FC_AVISRB0 0x1023 -#define HDMI_FC_AVISRB1 0x1024 -#define HDMI_FC_AUDICONF0 0x1025 -#define HDMI_FC_AUDICONF1 0x1026 -#define HDMI_FC_AUDICONF2 0x1027 -#define HDMI_FC_AUDICONF3 0x1028 -#define HDMI_FC_VSDIEEEID0 0x1029 -#define HDMI_FC_VSDSIZE 0x102A -#define HDMI_FC_VSDIEEEID1 0x1030 -#define HDMI_FC_VSDIEEEID2 0x1031 -#define HDMI_FC_VSDPAYLOAD0 0x1032 -#define HDMI_FC_VSDPAYLOAD1 0x1033 -#define HDMI_FC_VSDPAYLOAD2 0x1034 -#define HDMI_FC_VSDPAYLOAD3 0x1035 -#define HDMI_FC_VSDPAYLOAD4 0x1036 -#define HDMI_FC_VSDPAYLOAD5 0x1037 -#define HDMI_FC_VSDPAYLOAD6 0x1038 -#define HDMI_FC_VSDPAYLOAD7 0x1039 -#define HDMI_FC_VSDPAYLOAD8 0x103A -#define HDMI_FC_VSDPAYLOAD9 0x103B -#define HDMI_FC_VSDPAYLOAD10 0x103C -#define HDMI_FC_VSDPAYLOAD11 0x103D -#define HDMI_FC_VSDPAYLOAD12 0x103E -#define HDMI_FC_VSDPAYLOAD13 0x103F -#define HDMI_FC_VSDPAYLOAD14 0x1040 -#define HDMI_FC_VSDPAYLOAD15 0x1041 -#define HDMI_FC_VSDPAYLOAD16 0x1042 -#define HDMI_FC_VSDPAYLOAD17 0x1043 -#define HDMI_FC_VSDPAYLOAD18 0x1044 -#define HDMI_FC_VSDPAYLOAD19 0x1045 -#define HDMI_FC_VSDPAYLOAD20 0x1046 -#define HDMI_FC_VSDPAYLOAD21 0x1047 -#define HDMI_FC_VSDPAYLOAD22 0x1048 -#define HDMI_FC_VSDPAYLOAD23 0x1049 -#define HDMI_FC_SPDVENDORNAME0 0x104A -#define HDMI_FC_SPDVENDORNAME1 0x104B -#define HDMI_FC_SPDVENDORNAME2 0x104C -#define HDMI_FC_SPDVENDORNAME3 0x104D -#define HDMI_FC_SPDVENDORNAME4 0x104E -#define HDMI_FC_SPDVENDORNAME5 0x104F -#define HDMI_FC_SPDVENDORNAME6 0x1050 -#define HDMI_FC_SPDVENDORNAME7 0x1051 -#define HDMI_FC_SDPPRODUCTNAME0 0x1052 -#define HDMI_FC_SDPPRODUCTNAME1 0x1053 -#define HDMI_FC_SDPPRODUCTNAME2 0x1054 -#define HDMI_FC_SDPPRODUCTNAME3 0x1055 -#define HDMI_FC_SDPPRODUCTNAME4 0x1056 -#define HDMI_FC_SDPPRODUCTNAME5 0x1057 -#define HDMI_FC_SDPPRODUCTNAME6 0x1058 -#define HDMI_FC_SDPPRODUCTNAME7 0x1059 -#define HDMI_FC_SDPPRODUCTNAME8 0x105A -#define HDMI_FC_SDPPRODUCTNAME9 0x105B -#define HDMI_FC_SDPPRODUCTNAME10 0x105C -#define HDMI_FC_SDPPRODUCTNAME11 0x105D -#define HDMI_FC_SDPPRODUCTNAME12 0x105E -#define HDMI_FC_SDPPRODUCTNAME13 0x105F -#define HDMI_FC_SDPPRODUCTNAME14 0x1060 -#define HDMI_FC_SPDPRODUCTNAME15 0x1061 -#define HDMI_FC_SPDDEVICEINF 0x1062 -#define HDMI_FC_AUDSCONF 0x1063 -#define HDMI_FC_AUDSSTAT 0x1064 -#define HDMI_FC_DATACH0FILL 0x1070 -#define HDMI_FC_DATACH1FILL 0x1071 -#define HDMI_FC_DATACH2FILL 0x1072 -#define HDMI_FC_CTRLQHIGH 0x1073 -#define HDMI_FC_CTRLQLOW 0x1074 -#define HDMI_FC_ACP0 0x1075 -#define HDMI_FC_ACP28 0x1076 -#define HDMI_FC_ACP27 0x1077 -#define HDMI_FC_ACP26 0x1078 -#define HDMI_FC_ACP25 0x1079 -#define HDMI_FC_ACP24 0x107A -#define HDMI_FC_ACP23 0x107B -#define HDMI_FC_ACP22 0x107C -#define HDMI_FC_ACP21 0x107D -#define HDMI_FC_ACP20 0x107E -#define HDMI_FC_ACP19 0x107F -#define HDMI_FC_ACP18 0x1080 -#define HDMI_FC_ACP17 0x1081 -#define HDMI_FC_ACP16 0x1082 -#define HDMI_FC_ACP15 0x1083 -#define HDMI_FC_ACP14 0x1084 -#define HDMI_FC_ACP13 0x1085 -#define HDMI_FC_ACP12 0x1086 -#define HDMI_FC_ACP11 0x1087 -#define HDMI_FC_ACP10 0x1088 -#define HDMI_FC_ACP9 0x1089 -#define HDMI_FC_ACP8 0x108A -#define HDMI_FC_ACP7 0x108B -#define HDMI_FC_ACP6 0x108C -#define HDMI_FC_ACP5 0x108D -#define HDMI_FC_ACP4 0x108E -#define HDMI_FC_ACP3 0x108F -#define HDMI_FC_ACP2 0x1090 -#define HDMI_FC_ACP1 0x1091 -#define HDMI_FC_ISCR1_0 0x1092 -#define HDMI_FC_ISCR1_16 0x1093 -#define HDMI_FC_ISCR1_15 0x1094 -#define HDMI_FC_ISCR1_14 0x1095 -#define HDMI_FC_ISCR1_13 0x1096 -#define HDMI_FC_ISCR1_12 0x1097 -#define HDMI_FC_ISCR1_11 0x1098 -#define HDMI_FC_ISCR1_10 0x1099 -#define HDMI_FC_ISCR1_9 0x109A -#define HDMI_FC_ISCR1_8 0x109B -#define HDMI_FC_ISCR1_7 0x109C -#define HDMI_FC_ISCR1_6 0x109D -#define HDMI_FC_ISCR1_5 0x109E -#define HDMI_FC_ISCR1_4 0x109F -#define HDMI_FC_ISCR1_3 0x10A0 -#define HDMI_FC_ISCR1_2 0x10A1 -#define HDMI_FC_ISCR1_1 0x10A2 -#define HDMI_FC_ISCR2_15 0x10A3 -#define HDMI_FC_ISCR2_14 0x10A4 -#define HDMI_FC_ISCR2_13 0x10A5 -#define HDMI_FC_ISCR2_12 0x10A6 -#define HDMI_FC_ISCR2_11 0x10A7 -#define HDMI_FC_ISCR2_10 0x10A8 -#define HDMI_FC_ISCR2_9 0x10A9 -#define HDMI_FC_ISCR2_8 0x10AA -#define HDMI_FC_ISCR2_7 0x10AB -#define HDMI_FC_ISCR2_6 0x10AC -#define HDMI_FC_ISCR2_5 0x10AD -#define HDMI_FC_ISCR2_4 0x10AE -#define HDMI_FC_ISCR2_3 0x10AF -#define HDMI_FC_ISCR2_2 0x10B0 -#define HDMI_FC_ISCR2_1 0x10B1 -#define HDMI_FC_ISCR2_0 0x10B2 -#define HDMI_FC_DATAUTO0 0x10B3 -#define HDMI_FC_DATAUTO1 0x10B4 -#define HDMI_FC_DATAUTO2 0x10B5 -#define HDMI_FC_DATMAN 0x10B6 -#define HDMI_FC_DATAUTO3 0x10B7 -#define HDMI_FC_RDRB0 0x10B8 -#define HDMI_FC_RDRB1 0x10B9 -#define HDMI_FC_RDRB2 0x10BA -#define HDMI_FC_RDRB3 0x10BB -#define HDMI_FC_RDRB4 0x10BC -#define HDMI_FC_RDRB5 0x10BD -#define HDMI_FC_RDRB6 0x10BE -#define HDMI_FC_RDRB7 0x10BF -#define HDMI_FC_STAT0 0x10D0 -#define HDMI_FC_INT0 0x10D1 -#define HDMI_FC_MASK0 0x10D2 -#define HDMI_FC_POL0 0x10D3 -#define HDMI_FC_STAT1 0x10D4 -#define HDMI_FC_INT1 0x10D5 -#define HDMI_FC_MASK1 0x10D6 -#define HDMI_FC_POL1 0x10D7 -#define HDMI_FC_STAT2 0x10D8 -#define HDMI_FC_INT2 0x10D9 -#define HDMI_FC_MASK2 0x10DA -#define HDMI_FC_POL2 0x10DB -#define HDMI_FC_PRCONF 0x10E0 - -#define HDMI_FC_GMD_STAT 0x1100 -#define HDMI_FC_GMD_EN 0x1101 -#define HDMI_FC_GMD_UP 0x1102 -#define HDMI_FC_GMD_CONF 0x1103 -#define HDMI_FC_GMD_HB 0x1104 -#define HDMI_FC_GMD_PB0 0x1105 -#define HDMI_FC_GMD_PB1 0x1106 -#define HDMI_FC_GMD_PB2 0x1107 -#define HDMI_FC_GMD_PB3 0x1108 -#define HDMI_FC_GMD_PB4 0x1109 -#define HDMI_FC_GMD_PB5 0x110A -#define HDMI_FC_GMD_PB6 0x110B -#define HDMI_FC_GMD_PB7 0x110C -#define HDMI_FC_GMD_PB8 0x110D -#define HDMI_FC_GMD_PB9 0x110E -#define HDMI_FC_GMD_PB10 0x110F -#define HDMI_FC_GMD_PB11 0x1110 -#define HDMI_FC_GMD_PB12 0x1111 -#define HDMI_FC_GMD_PB13 0x1112 -#define HDMI_FC_GMD_PB14 0x1113 -#define HDMI_FC_GMD_PB15 0x1114 -#define HDMI_FC_GMD_PB16 0x1115 -#define HDMI_FC_GMD_PB17 0x1116 -#define HDMI_FC_GMD_PB18 0x1117 -#define HDMI_FC_GMD_PB19 0x1118 -#define HDMI_FC_GMD_PB20 0x1119 -#define HDMI_FC_GMD_PB21 0x111A -#define HDMI_FC_GMD_PB22 0x111B -#define HDMI_FC_GMD_PB23 0x111C -#define HDMI_FC_GMD_PB24 0x111D -#define HDMI_FC_GMD_PB25 0x111E -#define HDMI_FC_GMD_PB26 0x111F -#define HDMI_FC_GMD_PB27 0x1120 - -#define HDMI_FC_DBGFORCE 0x1200 -#define HDMI_FC_DBGAUD0CH0 0x1201 -#define HDMI_FC_DBGAUD1CH0 0x1202 -#define HDMI_FC_DBGAUD2CH0 0x1203 -#define HDMI_FC_DBGAUD0CH1 0x1204 -#define HDMI_FC_DBGAUD1CH1 0x1205 -#define HDMI_FC_DBGAUD2CH1 0x1206 -#define HDMI_FC_DBGAUD0CH2 0x1207 -#define HDMI_FC_DBGAUD1CH2 0x1208 -#define HDMI_FC_DBGAUD2CH2 0x1209 -#define HDMI_FC_DBGAUD0CH3 0x120A -#define HDMI_FC_DBGAUD1CH3 0x120B -#define HDMI_FC_DBGAUD2CH3 0x120C -#define HDMI_FC_DBGAUD0CH4 0x120D -#define HDMI_FC_DBGAUD1CH4 0x120E -#define HDMI_FC_DBGAUD2CH4 0x120F -#define HDMI_FC_DBGAUD0CH5 0x1210 -#define HDMI_FC_DBGAUD1CH5 0x1211 -#define HDMI_FC_DBGAUD2CH5 0x1212 -#define HDMI_FC_DBGAUD0CH6 0x1213 -#define HDMI_FC_DBGAUD1CH6 0x1214 -#define HDMI_FC_DBGAUD2CH6 0x1215 -#define HDMI_FC_DBGAUD0CH7 0x1216 -#define HDMI_FC_DBGAUD1CH7 0x1217 -#define HDMI_FC_DBGAUD2CH7 0x1218 -#define HDMI_FC_DBGTMDS0 0x1219 -#define HDMI_FC_DBGTMDS1 0x121A -#define HDMI_FC_DBGTMDS2 0x121B - -/* HDMI Source PHY Registers */ -#define HDMI_PHY_CONF0 0x3000 -#define HDMI_PHY_TST0 0x3001 -#define HDMI_PHY_TST1 0x3002 -#define HDMI_PHY_TST2 0x3003 -#define HDMI_PHY_STAT0 0x3004 -#define HDMI_PHY_INT0 0x3005 -#define HDMI_PHY_MASK0 0x3006 -#define HDMI_PHY_POL0 0x3007 - -/* HDMI Master PHY Registers */ -#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 -#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 -#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 -#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 -#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 -#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 -#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 -#define HDMI_PHY_I2CM_INT_ADDR 0x3027 -#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 -#define HDMI_PHY_I2CM_DIV_ADDR 0x3029 -#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a -#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b -#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c -#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d -#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e -#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f -#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 -#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 -#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 - -/* Audio Sampler Registers */ -#define HDMI_AUD_CONF0 0x3100 -#define HDMI_AUD_CONF1 0x3101 -#define HDMI_AUD_INT 0x3102 -#define HDMI_AUD_CONF2 0x3103 -#define HDMI_AUD_N1 0x3200 -#define HDMI_AUD_N2 0x3201 -#define HDMI_AUD_N3 0x3202 -#define HDMI_AUD_CTS1 0x3203 -#define HDMI_AUD_CTS2 0x3204 -#define HDMI_AUD_CTS3 0x3205 -#define HDMI_AUD_INPUTCLKFS 0x3206 -#define HDMI_AUD_SPDIFINT 0x3302 -#define HDMI_AUD_CONF0_HBR 0x3400 -#define HDMI_AUD_HBR_STATUS 0x3401 -#define HDMI_AUD_HBR_INT 0x3402 -#define HDMI_AUD_HBR_POL 0x3403 -#define HDMI_AUD_HBR_MASK 0x3404 - -/* Generic Parallel Audio Interface Registers */ -/* Not used as GPAUD interface is not enabled in hw */ -#define HDMI_GP_CONF0 0x3500 -#define HDMI_GP_CONF1 0x3501 -#define HDMI_GP_CONF2 0x3502 -#define HDMI_GP_STAT 0x3503 -#define HDMI_GP_INT 0x3504 -#define HDMI_GP_MASK 0x3505 -#define HDMI_GP_POL 0x3506 - -/* Audio DMA Registers */ -#define HDMI_AHB_DMA_CONF0 0x3600 -#define HDMI_AHB_DMA_START 0x3601 -#define HDMI_AHB_DMA_STOP 0x3602 -#define HDMI_AHB_DMA_THRSLD 0x3603 -#define HDMI_AHB_DMA_STRADDR0 0x3604 -#define HDMI_AHB_DMA_STRADDR1 0x3605 -#define HDMI_AHB_DMA_STRADDR2 0x3606 -#define HDMI_AHB_DMA_STRADDR3 0x3607 -#define HDMI_AHB_DMA_STPADDR0 0x3608 -#define HDMI_AHB_DMA_STPADDR1 0x3609 -#define HDMI_AHB_DMA_STPADDR2 0x360a -#define HDMI_AHB_DMA_STPADDR3 0x360b -#define HDMI_AHB_DMA_BSTADDR0 0x360c -#define HDMI_AHB_DMA_BSTADDR1 0x360d -#define HDMI_AHB_DMA_BSTADDR2 0x360e -#define HDMI_AHB_DMA_BSTADDR3 0x360f -#define HDMI_AHB_DMA_MBLENGTH0 0x3610 -#define HDMI_AHB_DMA_MBLENGTH1 0x3611 -#define HDMI_AHB_DMA_STAT 0x3612 -#define HDMI_AHB_DMA_INT 0x3613 -#define HDMI_AHB_DMA_MASK 0x3614 -#define HDMI_AHB_DMA_POL 0x3615 -#define HDMI_AHB_DMA_CONF1 0x3616 -#define HDMI_AHB_DMA_BUFFSTAT 0x3617 -#define HDMI_AHB_DMA_BUFFINT 0x3618 -#define HDMI_AHB_DMA_BUFFMASK 0x3619 -#define HDMI_AHB_DMA_BUFFPOL 0x361a - -/* Main Controller Registers */ -#define HDMI_MC_SFRDIV 0x4000 -#define HDMI_MC_CLKDIS 0x4001 -#define HDMI_MC_SWRSTZ 0x4002 -#define HDMI_MC_OPCTRL 0x4003 -#define HDMI_MC_FLOWCTRL 0x4004 -#define HDMI_MC_PHYRSTZ 0x4005 -#define HDMI_MC_LOCKONCLOCK 0x4006 -#define HDMI_MC_HEACPHY_RST 0x4007 - -/* Color Space Converter Registers */ -#define HDMI_CSC_CFG 0x4100 -#define HDMI_CSC_SCALE 0x4101 -#define HDMI_CSC_COEF_A1_MSB 0x4102 -#define HDMI_CSC_COEF_A1_LSB 0x4103 -#define HDMI_CSC_COEF_A2_MSB 0x4104 -#define HDMI_CSC_COEF_A2_LSB 0x4105 -#define HDMI_CSC_COEF_A3_MSB 0x4106 -#define HDMI_CSC_COEF_A3_LSB 0x4107 -#define HDMI_CSC_COEF_A4_MSB 0x4108 -#define HDMI_CSC_COEF_A4_LSB 0x4109 -#define HDMI_CSC_COEF_B1_MSB 0x410A -#define HDMI_CSC_COEF_B1_LSB 0x410B -#define HDMI_CSC_COEF_B2_MSB 0x410C -#define HDMI_CSC_COEF_B2_LSB 0x410D -#define HDMI_CSC_COEF_B3_MSB 0x410E -#define HDMI_CSC_COEF_B3_LSB 0x410F -#define HDMI_CSC_COEF_B4_MSB 0x4110 -#define HDMI_CSC_COEF_B4_LSB 0x4111 -#define HDMI_CSC_COEF_C1_MSB 0x4112 -#define HDMI_CSC_COEF_C1_LSB 0x4113 -#define HDMI_CSC_COEF_C2_MSB 0x4114 -#define HDMI_CSC_COEF_C2_LSB 0x4115 -#define HDMI_CSC_COEF_C3_MSB 0x4116 -#define HDMI_CSC_COEF_C3_LSB 0x4117 -#define HDMI_CSC_COEF_C4_MSB 0x4118 -#define HDMI_CSC_COEF_C4_LSB 0x4119 - -/* HDCP Encryption Engine Registers */ -#define HDMI_A_HDCPCFG0 0x5000 -#define HDMI_A_HDCPCFG1 0x5001 -#define HDMI_A_HDCPOBS0 0x5002 -#define HDMI_A_HDCPOBS1 0x5003 -#define HDMI_A_HDCPOBS2 0x5004 -#define HDMI_A_HDCPOBS3 0x5005 -#define HDMI_A_APIINTCLR 0x5006 -#define HDMI_A_APIINTSTAT 0x5007 -#define HDMI_A_APIINTMSK 0x5008 -#define HDMI_A_VIDPOLCFG 0x5009 -#define HDMI_A_OESSWCFG 0x500A -#define HDMI_A_TIMER1SETUP0 0x500B -#define HDMI_A_TIMER1SETUP1 0x500C -#define HDMI_A_TIMER2SETUP0 0x500D -#define HDMI_A_TIMER2SETUP1 0x500E -#define HDMI_A_100MSCFG 0x500F -#define HDMI_A_2SCFG0 0x5010 -#define HDMI_A_2SCFG1 0x5011 -#define HDMI_A_5SCFG0 0x5012 -#define HDMI_A_5SCFG1 0x5013 -#define HDMI_A_SRMVERLSB 0x5014 -#define HDMI_A_SRMVERMSB 0x5015 -#define HDMI_A_SRMCTRL 0x5016 -#define HDMI_A_SFRSETUP 0x5017 -#define HDMI_A_I2CHSETUP 0x5018 -#define HDMI_A_INTSETUP 0x5019 -#define HDMI_A_PRESETUP 0x501A -#define HDMI_A_SRM_BASE 0x5020 - -/* CEC Engine Registers */ -#define HDMI_CEC_CTRL 0x7D00 -#define HDMI_CEC_STAT 0x7D01 -#define HDMI_CEC_MASK 0x7D02 -#define HDMI_CEC_POLARITY 0x7D03 -#define HDMI_CEC_INT 0x7D04 -#define HDMI_CEC_ADDR_L 0x7D05 -#define HDMI_CEC_ADDR_H 0x7D06 -#define HDMI_CEC_TX_CNT 0x7D07 -#define HDMI_CEC_RX_CNT 0x7D08 -#define HDMI_CEC_TX_DATA0 0x7D10 -#define HDMI_CEC_TX_DATA1 0x7D11 -#define HDMI_CEC_TX_DATA2 0x7D12 -#define HDMI_CEC_TX_DATA3 0x7D13 -#define HDMI_CEC_TX_DATA4 0x7D14 -#define HDMI_CEC_TX_DATA5 0x7D15 -#define HDMI_CEC_TX_DATA6 0x7D16 -#define HDMI_CEC_TX_DATA7 0x7D17 -#define HDMI_CEC_TX_DATA8 0x7D18 -#define HDMI_CEC_TX_DATA9 0x7D19 -#define HDMI_CEC_TX_DATA10 0x7D1a -#define HDMI_CEC_TX_DATA11 0x7D1b -#define HDMI_CEC_TX_DATA12 0x7D1c -#define HDMI_CEC_TX_DATA13 0x7D1d -#define HDMI_CEC_TX_DATA14 0x7D1e -#define HDMI_CEC_TX_DATA15 0x7D1f -#define HDMI_CEC_RX_DATA0 0x7D20 -#define HDMI_CEC_RX_DATA1 0x7D21 -#define HDMI_CEC_RX_DATA2 0x7D22 -#define HDMI_CEC_RX_DATA3 0x7D23 -#define HDMI_CEC_RX_DATA4 0x7D24 -#define HDMI_CEC_RX_DATA5 0x7D25 -#define HDMI_CEC_RX_DATA6 0x7D26 -#define HDMI_CEC_RX_DATA7 0x7D27 -#define HDMI_CEC_RX_DATA8 0x7D28 -#define HDMI_CEC_RX_DATA9 0x7D29 -#define HDMI_CEC_RX_DATA10 0x7D2a -#define HDMI_CEC_RX_DATA11 0x7D2b -#define HDMI_CEC_RX_DATA12 0x7D2c -#define HDMI_CEC_RX_DATA13 0x7D2d -#define HDMI_CEC_RX_DATA14 0x7D2e -#define HDMI_CEC_RX_DATA15 0x7D2f -#define HDMI_CEC_LOCK 0x7D30 -#define HDMI_CEC_WKUPCTRL 0x7D31 - -/* I2C Master Registers (E-DDC) */ -#define HDMI_I2CM_SLAVE 0x7E00 -#define HDMI_I2CMESS 0x7E01 -#define HDMI_I2CM_DATAO 0x7E02 -#define HDMI_I2CM_DATAI 0x7E03 -#define HDMI_I2CM_OPERATION 0x7E04 -#define HDMI_I2CM_INT 0x7E05 -#define HDMI_I2CM_CTLINT 0x7E06 -#define HDMI_I2CM_DIV 0x7E07 -#define HDMI_I2CM_SEGADDR 0x7E08 -#define HDMI_I2CM_SOFTRSTZ 0x7E09 -#define HDMI_I2CM_SEGPTR 0x7E0A -#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B -#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C -#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D -#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E -#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F -#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 -#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 -#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 - -/* Random Number Generator Registers (RNG) */ -#define HDMI_RNG_BASE 0x8000 - +struct hdmi_regs { + /*Identification Registers */ + u8 design_id; /* 0x000 */ + u8 revision_id; /* 0x001 */ + u8 product_id0; /* 0x002 */ + u8 product_id1; /* 0x003 */ + u8 config0_id; /* 0x004 */ + u8 config1_id; /* 0x005 */ + u8 config2_id; /* 0x006 */ + u8 config3_id; /* 0x007 */ + u8 reserved1[0xf8]; + /* Interrupt Registers */ + u8 ih_fc_stat0; /* 0x100 */ + u8 ih_fc_stat1; /* 0x101 */ + u8 ih_fc_stat2; /* 0x102 */ + u8 ih_as_stat0; /* 0x103 */ + u8 ih_phy_stat0; /* 0x104 */ + u8 ih_i2cm_stat0; /* 0x105 */ + u8 ih_cec_stat0; /* 0x106 */ + u8 ih_vp_stat0; /* 0x107 */ + u8 ih_i2cmphy_stat0; /* 0x108 */ + u8 ih_ahbdmaaud_stat0; /* 0x109 */ + u8 reserved2[0x76]; + u8 ih_mute_fc_stat0; /* 0x180 */ + u8 ih_mute_fc_stat1; /* 0x181 */ + u8 ih_mute_fc_stat2; /* 0x182 */ + u8 ih_mute_as_stat0; /* 0x183 */ + u8 ih_mute_phy_stat0; /* 0x184 */ + u8 ih_mute_i2cm_stat0; /* 0x185 */ + u8 ih_mute_cec_stat0; /* 0x186 */ + u8 ih_mute_vp_stat0; /* 0x187 */ + u8 ih_mute_i2cmphy_stat0; /* 0x188 */ + u8 ih_mute_ahbdmaaud_stat0; /* 0x189 */ + u8 reserved3[0x75]; + u8 ih_mute; /* 0x1ff */ + /* Video Sample Registers */ + u8 tx_invid0; /* 0x200 */ + u8 tx_instuffing; /* 0x201 */ + u8 tx_gydata0; /* 0x202 */ + u8 tx_gydata1; /* 0x203 */ + u8 tx_rcrdata0; /* 0x204 */ + u8 tx_rcrdata1; /* 0x205 */ + u8 tx_bcbdata0; /* 0x206 */ + u8 tx_bcbdata1; /* 0x207 */ + u8 reserved4[0x5f8]; + /* Video Packetizer Registers */ + u8 vp_status; /* 0x800 */ + u8 vp_pr_cd; /* 0x801 */ + u8 vp_stuff; /* 0x802 */ + u8 vp_remap; /* 0x803 */ + u8 vp_conf; /* 0x804 */ + u8 vp_stat; /* 0x805 */ + u8 vp_int; /* 0x806 */ + u8 vp_mask; /* 0x807 */ + u8 vp_pol; /* 0x808 */ + u8 reserved5[0x7f7]; + /* Frame Composer Registers */ + u8 fc_invidconf; /* 0x1000 */ + u8 fc_inhactv0; /* 0x1001 */ + u8 fc_inhactv1; /* 0x1002 */ + u8 fc_inhblank0; /* 0x1003 */ + u8 fc_inhblank1; /* 0x1004 */ + u8 fc_invactv0; /* 0x1005 */ + u8 fc_invactv1; /* 0x1006 */ + u8 fc_invblank; /* 0x1007 */ + u8 fc_hsyncindelay0; /* 0x1008 */ + u8 fc_hsyncindelay1; /* 0x1009 */ + u8 fc_hsyncinwidth0; /* 0x100a */ + u8 fc_hsyncinwidth1; /* 0x100b */ + u8 fc_vsyncindelay; /* 0x100c */ + u8 fc_vsyncinwidth; /* 0x100d */ + u8 fc_infreq0; /* 0x100e */ + u8 fc_infreq1; /* 0x100f */ + u8 fc_infreq2; /* 0x1010 */ + u8 fc_ctrldur; /* 0x1011 */ + u8 fc_exctrldur; /* 0x1012 */ + u8 fc_exctrlspac; /* 0x1013 */ + u8 fc_ch0pream; /* 0x1014 */ + u8 fc_ch1pream; /* 0x1015 */ + u8 fc_ch2pream; /* 0x1016 */ + u8 fc_aviconf3; /* 0x1017 */ + u8 fc_gcp; /* 0x1018 */ + u8 fc_aviconf0; /* 0x1019 */ + u8 fc_aviconf1; /* 0x101a */ + u8 fc_aviconf2; /* 0x101b */ + u8 fc_avivid; /* 0x101c */ + u8 fc_avietb0; /* 0x101d */ + u8 fc_avietb1; /* 0x101e */ + u8 fc_avisbb0; /* 0x101f */ + u8 fc_avisbb1; /* 0x1020 */ + u8 fc_avielb0; /* 0x1021 */ + u8 fc_avielb1; /* 0x1022 */ + u8 fc_avisrb0; /* 0x1023 */ + u8 fc_avisrb1; /* 0x1024 */ + u8 fc_audiconf0; /* 0x1025 */ + u8 fc_audiconf1; /* 0x1026 */ + u8 fc_audiconf2; /* 0x1027 */ + u8 fc_audiconf3; /* 0x1028 */ + u8 fc_vsdieeeid0; /* 0x1029 */ + u8 fc_vsdsize; /* 0x102a */ + u8 reserved6[5]; + u8 fc_vsdieeeid1; /* 0x1030 */ + u8 fc_vsdieeeid2; /* 0x1031 */ + u8 fc_vsdpayload0; /* 0x1032 */ + u8 fc_vsdpayload1; /* 0x1033 */ + u8 fc_vsdpayload2; /* 0x1034 */ + u8 fc_vsdpayload3; /* 0x1035 */ + u8 fc_vsdpayload4; /* 0x1036 */ + u8 fc_vsdpayload5; /* 0x1037 */ + u8 fc_vsdpayload6; /* 0x1038 */ + u8 fc_vsdpayload7; /* 0x1039 */ + u8 fc_vsdpayload8; /* 0x103a */ + u8 fc_vsdpayload9; /* 0x103b */ + u8 fc_vsdpayload10; /* 0x103c */ + u8 fc_vsdpayload11; /* 0x103d */ + u8 fc_vsdpayload12; /* 0x103e */ + u8 fc_vsdpayload13; /* 0x103f */ + u8 fc_vsdpayload14; /* 0x1040 */ + u8 fc_vsdpayload15; /* 0x1041 */ + u8 fc_vsdpayload16; /* 0x1042 */ + u8 fc_vsdpayload17; /* 0x1043 */ + u8 fc_vsdpayload18; /* 0x1044 */ + u8 fc_vsdpayload19; /* 0x1045 */ + u8 fc_vsdpayload20; /* 0x1046 */ + u8 fc_vsdpayload21; /* 0x1047 */ + u8 fc_vsdpayload22; /* 0x1048 */ + u8 fc_vsdpayload23; /* 0x1049 */ + u8 fc_spdvendorname0; /* 0x104a */ + u8 fc_spdvendorname1; /* 0x104b */ + u8 fc_spdvendorname2; /* 0x104c */ + u8 fc_spdvendorname3; /* 0x104d */ + u8 fc_spdvendorname4; /* 0x104e */ + u8 fc_spdvendorname5; /* 0x104f */ + u8 fc_spdvendorname6; /* 0x1050 */ + u8 fc_spdvendorname7; /* 0x1051 */ + u8 fc_sdpproductname0; /* 0x1052 */ + u8 fc_sdpproductname1; /* 0x1053 */ + u8 fc_sdpproductname2; /* 0x1054 */ + u8 fc_sdpproductname3; /* 0x1055 */ + u8 fc_sdpproductname4; /* 0x1056 */ + u8 fc_sdpproductname5; /* 0x1057 */ + u8 fc_sdpproductname6; /* 0x1058 */ + u8 fc_sdpproductname7; /* 0x1059 */ + u8 fc_sdpproductname8; /* 0x105a */ + u8 fc_sdpproductname9; /* 0x105b */ + u8 fc_sdpproductname10; /* 0x105c */ + u8 fc_sdpproductname11; /* 0x105d */ + u8 fc_sdpproductname12; /* 0x105e */ + u8 fc_sdpproductname13; /* 0x105f */ + u8 fc_sdpproductname14; /* 0x1060 */ + u8 fc_spdproductname15; /* 0x1061 */ + u8 fc_spddeviceinf; /* 0x1062 */ + u8 fc_audsconf; /* 0x1063 */ + u8 fc_audsstat; /* 0x1064 */ + u8 reserved7[0xb]; + u8 fc_datach0fill; /* 0x1070 */ + u8 fc_datach1fill; /* 0x1071 */ + u8 fc_datach2fill; /* 0x1072 */ + u8 fc_ctrlqhigh; /* 0x1073 */ + u8 fc_ctrlqlow; /* 0x1074 */ + u8 fc_acp0; /* 0x1075 */ + u8 fc_acp28; /* 0x1076 */ + u8 fc_acp27; /* 0x1077 */ + u8 fc_acp26; /* 0x1078 */ + u8 fc_acp25; /* 0x1079 */ + u8 fc_acp24; /* 0x107a */ + u8 fc_acp23; /* 0x107b */ + u8 fc_acp22; /* 0x107c */ + u8 fc_acp21; /* 0x107d */ + u8 fc_acp20; /* 0x107e */ + u8 fc_acp19; /* 0x107f */ + u8 fc_acp18; /* 0x1080 */ + u8 fc_acp17; /* 0x1081 */ + u8 fc_acp16; /* 0x1082 */ + u8 fc_acp15; /* 0x1083 */ + u8 fc_acp14; /* 0x1084 */ + u8 fc_acp13; /* 0x1085 */ + u8 fc_acp12; /* 0x1086 */ + u8 fc_acp11; /* 0x1087 */ + u8 fc_acp10; /* 0x1088 */ + u8 fc_acp9; /* 0x1089 */ + u8 fc_acp8; /* 0x108a */ + u8 fc_acp7; /* 0x108b */ + u8 fc_acp6; /* 0x108c */ + u8 fc_acp5; /* 0x108d */ + u8 fc_acp4; /* 0x108e */ + u8 fc_acp3; /* 0x108f */ + u8 fc_acp2; /* 0x1090 */ + u8 fc_acp1; /* 0x1091 */ + u8 fc_iscr1_0; /* 0x1092 */ + u8 fc_iscr1_16; /* 0x1093 */ + u8 fc_iscr1_15; /* 0x1094 */ + u8 fc_iscr1_14; /* 0x1095 */ + u8 fc_iscr1_13; /* 0x1096 */ + u8 fc_iscr1_12; /* 0x1097 */ + u8 fc_iscr1_11; /* 0x1098 */ + u8 fc_iscr1_10; /* 0x1099 */ + u8 fc_iscr1_9; /* 0x109a */ + u8 fc_iscr1_8; /* 0x109b */ + u8 fc_iscr1_7; /* 0x109c */ + u8 fc_iscr1_6; /* 0x109d */ + u8 fc_iscr1_5; /* 0x109e */ + u8 fc_iscr1_4; /* 0x109f */ + u8 fc_iscr1_3; /* 0x10a0 */ + u8 fc_iscr1_2; /* 0x10a1 */ + u8 fc_iscr1_1; /* 0x10a2 */ + u8 fc_iscr2_15; /* 0x10a3 */ + u8 fc_iscr2_14; /* 0x10a4 */ + u8 fc_iscr2_13; /* 0x10a5 */ + u8 fc_iscr2_12; /* 0x10a6 */ + u8 fc_iscr2_11; /* 0x10a7 */ + u8 fc_iscr2_10; /* 0x10a8 */ + u8 fc_iscr2_9; /* 0x10a9 */ + u8 fc_iscr2_8; /* 0x10aa */ + u8 fc_iscr2_7; /* 0x10ab */ + u8 fc_iscr2_6; /* 0x10ac */ + u8 fc_iscr2_5; /* 0x10ad */ + u8 fc_iscr2_4; /* 0x10ae */ + u8 fc_iscr2_3; /* 0x10af */ + u8 fc_iscr2_2; /* 0x10b0 */ + u8 fc_iscr2_1; /* 0x10b1 */ + u8 fc_iscr2_0; /* 0x10b2 */ + u8 fc_datauto0; /* 0x10b3 */ + u8 fc_datauto1; /* 0x10b4 */ + u8 fc_datauto2; /* 0x10b5 */ + u8 fc_datman; /* 0x10b6 */ + u8 fc_datauto3; /* 0x10b7 */ + u8 fc_rdrb0; /* 0x10b8 */ + u8 fc_rdrb1; /* 0x10b9 */ + u8 fc_rdrb2; /* 0x10ba */ + u8 fc_rdrb3; /* 0x10bb */ + u8 fc_rdrb4; /* 0x10bc */ + u8 fc_rdrb5; /* 0x10bd */ + u8 fc_rdrb6; /* 0x10be */ + u8 fc_rdrb7; /* 0x10bf */ + u8 reserved8[0x10]; + u8 fc_stat0; /* 0x10d0 */ + u8 fc_int0; /* 0x10d1 */ + u8 fc_mask0; /* 0x10d2 */ + u8 fc_pol0; /* 0x10d3 */ + u8 fc_stat1; /* 0x10d4 */ + u8 fc_int1; /* 0x10d5 */ + u8 fc_mask1; /* 0x10d6 */ + u8 fc_pol1; /* 0x10d7 */ + u8 fc_stat2; /* 0x10d8 */ + u8 fc_int2; /* 0x10d9 */ + u8 fc_mask2; /* 0x10da */ + u8 fc_pol2; /* 0x10db */ + u8 reserved9[0x4]; + u8 fc_prconf; /* 0x10e0 */ + u8 reserved10[0x1f]; + u8 fc_gmd_stat; /* 0x1100 */ + u8 fc_gmd_en; /* 0x1101 */ + u8 fc_gmd_up; /* 0x1102 */ + u8 fc_gmd_conf; /* 0x1103 */ + u8 fc_gmd_hb; /* 0x1104 */ + u8 fc_gmd_pb0; /* 0x1105 */ + u8 fc_gmd_pb1; /* 0x1106 */ + u8 fc_gmd_pb2; /* 0x1107 */ + u8 fc_gmd_pb3; /* 0x1108 */ + u8 fc_gmd_pb4; /* 0x1109 */ + u8 fc_gmd_pb5; /* 0x110a */ + u8 fc_gmd_pb6; /* 0x110b */ + u8 fc_gmd_pb7; /* 0x110c */ + u8 fc_gmd_pb8; /* 0x110d */ + u8 fc_gmd_pb9; /* 0x110e */ + u8 fc_gmd_pb10; /* 0x110f */ + u8 fc_gmd_pb11; /* 0x1110 */ + u8 fc_gmd_pb12; /* 0x1111 */ + u8 fc_gmd_pb13; /* 0x1112 */ + u8 fc_gmd_pb14; /* 0x1113 */ + u8 fc_gmd_pb15; /* 0x1114 */ + u8 fc_gmd_pb16; /* 0x1115 */ + u8 fc_gmd_pb17; /* 0x1116 */ + u8 fc_gmd_pb18; /* 0x1117 */ + u8 fc_gmd_pb19; /* 0x1118 */ + u8 fc_gmd_pb20; /* 0x1119 */ + u8 fc_gmd_pb21; /* 0x111a */ + u8 fc_gmd_pb22; /* 0x111b */ + u8 fc_gmd_pb23; /* 0x111c */ + u8 fc_gmd_pb24; /* 0x111d */ + u8 fc_gmd_pb25; /* 0x111e */ + u8 fc_gmd_pb26; /* 0x111f */ + u8 fc_gmd_pb27; /* 0x1120 */ + u8 reserved11[0xdf]; + u8 fc_dbgforce; /* 0x1200 */ + u8 fc_dbgaud0ch0; /* 0x1201 */ + u8 fc_dbgaud1ch0; /* 0x1202 */ + u8 fc_dbgaud2ch0; /* 0x1203 */ + u8 fc_dbgaud0ch1; /* 0x1204 */ + u8 fc_dbgaud1ch1; /* 0x1205 */ + u8 fc_dbgaud2ch1; /* 0x1206 */ + u8 fc_dbgaud0ch2; /* 0x1207 */ + u8 fc_dbgaud1ch2; /* 0x1208 */ + u8 fc_dbgaud2ch2; /* 0x1209 */ + u8 fc_dbgaud0ch3; /* 0x120a */ + u8 fc_dbgaud1ch3; /* 0x120b */ + u8 fc_dbgaud2ch3; /* 0x120c */ + u8 fc_dbgaud0ch4; /* 0x120d */ + u8 fc_dbgaud1ch4; /* 0x120e */ + u8 fc_dbgaud2ch4; /* 0x120f */ + u8 fc_dbgaud0ch5; /* 0x1210 */ + u8 fc_dbgaud1ch5; /* 0x1211 */ + u8 fc_dbgaud2ch5; /* 0x1212 */ + u8 fc_dbgaud0ch6; /* 0x1213 */ + u8 fc_dbgaud1ch6; /* 0x1214 */ + u8 fc_dbgaud2ch6; /* 0x1215 */ + u8 fc_dbgaud0ch7; /* 0x1216 */ + u8 fc_dbgaud1ch7; /* 0x1217 */ + u8 fc_dbgaud2ch7; /* 0x1218 */ + u8 fc_dbgtmds0; /* 0x1219 */ + u8 fc_dbgtmds1; /* 0x121a */ + u8 fc_dbgtmds2; /* 0x121b */ + u8 reserved12[0x1de4]; + /* Hdmi Source Phy Registers */ + u8 phy_conf0; /* 0x3000 */ + u8 phy_tst0; /* 0x3001 */ + u8 phy_tst1; /* 0x3002 */ + u8 phy_tst2; /* 0x3003 */ + u8 phy_stat0; /* 0x3004 */ + u8 phy_int0; /* 0x3005 */ + u8 phy_mask0; /* 0x3006 */ + u8 phy_pol0; /* 0x3007 */ + u8 reserved13[0x18]; + /* Hdmi Master Phy Registers */ + u8 phy_i2cm_slave_addr; /* 0x3020 */ + u8 phy_i2cm_address_addr; /* 0x3021 */ + u8 phy_i2cm_datao_1_addr; /* 0x3022 */ + u8 phy_i2cm_datao_0_addr; /* 0x3023 */ + u8 phy_i2cm_datai_1_addr; /* 0x3024 */ + u8 phy_i2cm_datai_0_addr; /* 0x3025 */ + u8 phy_i2cm_operation_addr; /* 0x3026 */ + u8 phy_i2cm_int_addr; /* 0x3027 */ + u8 phy_i2cm_ctlint_addr; /* 0x3028 */ + u8 phy_i2cm_div_addr; /* 0x3029 */ + u8 phy_i2cm_softrstz_addr; /* 0x302a */ + u8 phy_i2cm_ss_scl_hcnt_1_addr; /* 0x302b */ + u8 phy_i2cm_ss_scl_hcnt_0_addr; /* 0x302c */ + u8 phy_i2cm_ss_scl_lcnt_1_addr; /* 0x302d */ + u8 phy_i2cm_ss_scl_lcnt_0_addr; /* 0x302e */ + u8 phy_i2cm_fs_scl_hcnt_1_addr; /* 0x302f */ + u8 phy_i2cm_fs_scl_hcnt_0_addr; /* 0x3030 */ + u8 phy_i2cm_fs_scl_lcnt_1_addr; /* 0x3031 */ + u8 phy_i2cm_fs_scl_lcnt_0_addr; /* 0x3032 */ + u8 reserved14[0xcd]; + /* Audio Sampler Registers */ + u8 aud_conf0; /* 0x3100 */ + u8 aud_conf1; /* 0x3101 */ + u8 aud_int; /* 0x3102 */ + u8 aud_conf2; /* 0x3103 */ + u8 reserved15[0xfc]; + u8 aud_n1; /* 0x3200 */ + u8 aud_n2; /* 0x3201 */ + u8 aud_n3; /* 0x3202 */ + u8 aud_cts1; /* 0x3203 */ + u8 aud_cts2; /* 0x3204 */ + u8 aud_cts3; /* 0x3205 */ + u8 aud_inputclkfs; /* 0x3206 */ + u8 reserved16[0xfb]; + u8 aud_spdifint; /* 0x3302 */ + u8 reserved17[0xfd]; + u8 aud_conf0_hbr; /* 0x3400 */ + u8 aud_hbr_status; /* 0x3401 */ + u8 aud_hbr_int; /* 0x3402 */ + u8 aud_hbr_pol; /* 0x3403 */ + u8 aud_hbr_mask; /* 0x3404 */ + u8 reserved18[0xfb]; + /* + * Generic Parallel Audio Interface Registers + * Not used as GPAUD interface is not enabled in hw + */ + u8 gp_conf0; /* 0x3500 */ + u8 gp_conf1; /* 0x3501 */ + u8 gp_conf2; /* 0x3502 */ + u8 gp_stat; /* 0x3503 */ + u8 gp_int; /* 0x3504 */ + u8 gp_mask; /* 0x3505 */ + u8 gp_pol; /* 0x3506 */ + u8 reserved19[0xf9]; + /* Audio DMA Registers */ + u8 ahb_dma_conf0; /* 0x3600 */ + u8 ahb_dma_start; /* 0x3601 */ + u8 ahb_dma_stop; /* 0x3602 */ + u8 ahb_dma_thrsld; /* 0x3603 */ + u8 ahb_dma_straddr0; /* 0x3604 */ + u8 ahb_dma_straddr1; /* 0x3605 */ + u8 ahb_dma_straddr2; /* 0x3606 */ + u8 ahb_dma_straddr3; /* 0x3607 */ + u8 ahb_dma_stpaddr0; /* 0x3608 */ + u8 ahb_dma_stpaddr1; /* 0x3609 */ + u8 ahb_dma_stpaddr2; /* 0x360a */ + u8 ahb_dma_stpaddr3; /* 0x360b */ + u8 ahb_dma_bstaddr0; /* 0x360c */ + u8 ahb_dma_bstaddr1; /* 0x360d */ + u8 ahb_dma_bstaddr2; /* 0x360e */ + u8 ahb_dma_bstaddr3; /* 0x360f */ + u8 ahb_dma_mblength0; /* 0x3610 */ + u8 ahb_dma_mblength1; /* 0x3611 */ + u8 ahb_dma_stat; /* 0x3612 */ + u8 ahb_dma_int; /* 0x3613 */ + u8 ahb_dma_mask; /* 0x3614 */ + u8 ahb_dma_pol; /* 0x3615 */ + u8 ahb_dma_conf1; /* 0x3616 */ + u8 ahb_dma_buffstat; /* 0x3617 */ + u8 ahb_dma_buffint; /* 0x3618 */ + u8 ahb_dma_buffmask; /* 0x3619 */ + u8 ahb_dma_buffpol; /* 0x361a */ + u8 reserved20[0x9e5]; + /* Main Controller Registers */ + u8 mc_sfrdiv; /* 0x4000 */ + u8 mc_clkdis; /* 0x4001 */ + u8 mc_swrstz; /* 0x4002 */ + u8 mc_opctrl; /* 0x4003 */ + u8 mc_flowctrl; /* 0x4004 */ + u8 mc_phyrstz; /* 0x4005 */ + u8 mc_lockonclock; /* 0x4006 */ + u8 mc_heacphy_rst; /* 0x4007 */ + u8 reserved21[0xf8]; + /* Colorspace Converter Registers */ + u8 csc_cfg; /* 0x4100 */ + u8 csc_scale; /* 0x4101 */ + u8 csc_coef_a1_msb; /* 0x4102 */ + u8 csc_coef_a1_lsb; /* 0x4103 */ + u8 csc_coef_a2_msb; /* 0x4104 */ + u8 csc_coef_a2_lsb; /* 0x4105 */ + u8 csc_coef_a3_msb; /* 0x4106 */ + u8 csc_coef_a3_lsb; /* 0x4107 */ + u8 csc_coef_a4_msb; /* 0x4108 */ + u8 csc_coef_a4_lsb; /* 0x4109 */ + u8 csc_coef_b1_msb; /* 0x410a */ + u8 csc_coef_b1_lsb; /* 0x410b */ + u8 csc_coef_b2_msb; /* 0x410c */ + u8 csc_coef_b2_lsb; /* 0x410d */ + u8 csc_coef_b3_msb; /* 0x410e */ + u8 csc_coef_b3_lsb; /* 0x410f */ + u8 csc_coef_b4_msb; /* 0x4110 */ + u8 csc_coef_b4_lsb; /* 0x4111 */ + u8 csc_coef_c1_msb; /* 0x4112 */ + u8 csc_coef_c1_lsb; /* 0x4113 */ + u8 csc_coef_c2_msb; /* 0x4114 */ + u8 csc_coef_c2_lsb; /* 0x4115 */ + u8 csc_coef_c3_msb; /* 0x4116 */ + u8 csc_coef_c3_lsb; /* 0x4117 */ + u8 csc_coef_c4_msb; /* 0x4118 */ + u8 csc_coef_c4_lsb; /* 0x4119 */ + u8 reserved22[0xee6]; + /* HDCP Encryption Engine Registers */ + u8 a_hdcpcfg0; /* 0x5000 */ + u8 a_hdcpcfg1; /* 0x5001 */ + u8 a_hdcpobs0; /* 0x5002 */ + u8 a_hdcpobs1; /* 0x5003 */ + u8 a_hdcpobs2; /* 0x5004 */ + u8 a_hdcpobs3; /* 0x5005 */ + u8 a_apiintclr; /* 0x5006 */ + u8 a_apiintstat; /* 0x5007 */ + u8 a_apiintmsk; /* 0x5008 */ + u8 a_vidpolcfg; /* 0x5009 */ + u8 a_oesswcfg; /* 0x500a */ + u8 a_timer1setup0; /* 0x500b */ + u8 a_timer1setup1; /* 0x500c */ + u8 a_timer2setup0; /* 0x500d */ + u8 a_timer2setup1; /* 0x500e */ + u8 a_100mscfg; /* 0x500f */ + u8 a_2scfg0; /* 0x5010 */ + u8 a_2scfg1; /* 0x5011 */ + u8 a_5scfg0; /* 0x5012 */ + u8 a_5scfg1; /* 0x5013 */ + u8 a_srmverlsb; /* 0x5014 */ + u8 a_srmvermsb; /* 0x5015 */ + u8 a_srmctrl; /* 0x5016 */ + u8 a_sfrsetup; /* 0x5017 */ + u8 a_i2chsetup; /* 0x5018 */ + u8 a_intsetup; /* 0x5019 */ + u8 a_presetup; /* 0x501a */ + u8 reserved23[0x5]; + u8 a_srm_base; /* 0x5020 */ + u8 reserved24[0x2cdf]; + /* CEC Engine Registers */ + u8 cec_ctrl; /* 0x7d00 */ + u8 cec_stat; /* 0x7d01 */ + u8 cec_mask; /* 0x7d02 */ + u8 cec_polarity; /* 0x7d03 */ + u8 cec_int; /* 0x7d04 */ + u8 cec_addr_l; /* 0x7d05 */ + u8 cec_addr_h; /* 0x7d06 */ + u8 cec_tx_cnt; /* 0x7d07 */ + u8 cec_rx_cnt; /* 0x7d08 */ + u8 reserved25[0x7]; + u8 cec_tx_data0; /* 0x7d10 */ + u8 cec_tx_data1; /* 0x7d11 */ + u8 cec_tx_data2; /* 0x7d12 */ + u8 cec_tx_data3; /* 0x7d13 */ + u8 cec_tx_data4; /* 0x7d14 */ + u8 cec_tx_data5; /* 0x7d15 */ + u8 cec_tx_data6; /* 0x7d16 */ + u8 cec_tx_data7; /* 0x7d17 */ + u8 cec_tx_data8; /* 0x7d18 */ + u8 cec_tx_data9; /* 0x7d19 */ + u8 cec_tx_data10; /* 0x7d1a */ + u8 cec_tx_data11; /* 0x7d1b */ + u8 cec_tx_data12; /* 0x7d1c */ + u8 cec_tx_data13; /* 0x7d1d */ + u8 cec_tx_data14; /* 0x7d1e */ + u8 cec_tx_data15; /* 0x7d1f */ + u8 cec_rx_data0; /* 0x7d20 */ + u8 cec_rx_data1; /* 0x7d21 */ + u8 cec_rx_data2; /* 0x7d22 */ + u8 cec_rx_data3; /* 0x7d23 */ + u8 cec_rx_data4; /* 0x7d24 */ + u8 cec_rx_data5; /* 0x7d25 */ + u8 cec_rx_data6; /* 0x7d26 */ + u8 cec_rx_data7; /* 0x7d27 */ + u8 cec_rx_data8; /* 0x7d28 */ + u8 cec_rx_data9; /* 0x7d29 */ + u8 cec_rx_data10; /* 0x7d2a */ + u8 cec_rx_data11; /* 0x7d2b */ + u8 cec_rx_data12; /* 0x7d2c */ + u8 cec_rx_data13; /* 0x7d2d */ + u8 cec_rx_data14; /* 0x7d2e */ + u8 cec_rx_data15; /* 0x7d2f */ + u8 cec_lock; /* 0x7d30 */ + u8 cec_wkupctrl; /* 0x7d31 */ + u8 reserved26[0xce]; + /* I2C Master Registers (E-DDC) */ + u8 i2cm_slave; /* 0x7e00 */ + u8 i2cmess; /* 0x7e01 */ + u8 i2cm_datao; /* 0x7e02 */ + u8 i2cm_datai; /* 0x7e03 */ + u8 i2cm_operation; /* 0x7e04 */ + u8 i2cm_int; /* 0x7e05 */ + u8 i2cm_ctlint; /* 0x7e06 */ + u8 i2cm_div; /* 0x7e07 */ + u8 i2cm_segaddr; /* 0x7e08 */ + u8 i2cm_softrstz; /* 0x7e09 */ + u8 i2cm_segptr; /* 0x7e0a */ + u8 i2cm_ss_scl_hcnt_1_addr; /* 0x7e0b */ + u8 i2cm_ss_scl_hcnt_0_addr; /* 0x7e0c */ + u8 i2cm_ss_scl_lcnt_1_addr; /* 0x7e0d */ + u8 i2cm_ss_scl_lcnt_0_addr; /* 0x7e0e */ + u8 i2cm_fs_scl_hcnt_1_addr; /* 0x7e0f */ + u8 i2cm_fs_scl_hcnt_0_addr; /* 0x7e10 */ + u8 i2cm_fs_scl_lcnt_1_addr; /* 0x7e11 */ + u8 i2cm_fs_scl_lcnt_0_addr; /* 0x7e12 */ + u8 reserved27[0x1ed]; + /* Random Number Generator Registers (RNG) */ + u8 rng_base; /* 0x8000 */ +}; /* * Register field definitions diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index f7b7f07..5b69a6d 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -455,32 +455,26 @@ struct display_info_t { static int detect_hdmi(struct display_info_t const *dev) { - return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; } static void enable_hdmi(struct display_info_t const *dev) { + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; u8 reg; printf("%s: setup HDMI monitor\n", __func__); - reg = __raw_readb( - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); + reg = readb(&hdmi->phy_conf0); reg |= HDMI_PHY_CONF0_PDZ_MASK; - __raw_writeb(reg, - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); + writeb(reg, &hdmi->phy_conf0); + udelay(3000); reg |= HDMI_PHY_CONF0_ENTMDS_MASK; - __raw_writeb(reg, - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); + writeb(reg, &hdmi->phy_conf0); udelay(3000); reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; - __raw_writeb(reg, - HDMI_ARB_BASE_ADDR - +HDMI_PHY_CONF0); - __raw_writeb(HDMI_MC_PHYRSTZ_ASSERT, - HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ); + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); } static int detect_i2c(struct display_info_t const *dev) @@ -638,6 +632,7 @@ static void setup_display(void) struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; int reg; @@ -654,8 +649,7 @@ static void setup_display(void) writel(reg, &mxc_ccm->CCGR2); /* clear HDMI PHY reset */ - __raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT, - HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ); + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); -- cgit v0.10.2 From 8f3937761bf260e71e7c199cf6547535ae7e90b9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 26 Feb 2013 12:28:29 +0000 Subject: ARM: mx6: use common CPU errata config options Now that U-Boot has common CONFIG_ options to work around some ARM CPU errata, enable the relevant options on MX6, and remove the custom lowlevel_init.S, since it's just duplicated code now. Signed-off-by: Stephen Warren Reviewed-by: Fabio Estevam Acked-by: Jason Liu diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index ee8c2b3..4668b3c 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -32,7 +32,7 @@ COBJS += cache_v7.o COBJS += cpu.o COBJS += syslib.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6),) SOBJS += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile index cbce411..4f9ca68 100644 --- a/arch/arm/cpu/armv7/mx6/Makefile +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -28,7 +28,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o COBJS = soc.o clock.o -SOBJS = lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/armv7/mx6/lowlevel_init.S b/arch/arm/cpu/armv7/mx6/lowlevel_init.S deleted file mode 100644 index 7b60ca7..0000000 --- a/arch/arm/cpu/armv7/mx6/lowlevel_init.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -.section ".text.init", "x" - -#include - -.macro init_arm_errata - /* ARM erratum ID #743622 */ - mrc p15, 0, r10, c15, c0, 1 /* read diagnostic register */ - orr r10, r10, #1 << 6 /* set bit #6 */ - /* ARM erratum ID #751472 */ - orr r10, r10, #1 << 11 /* set bit #11 */ - mcr p15, 0, r10, c15, c0, 1 /* write diagnostic register */ -.endm - -ENTRY(lowlevel_init) - init_arm_errata - mov pc, lr -ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index efe4136..193ba12 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -205,3 +205,7 @@ const struct boot_mode soc_boot_modes[] = { {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, {NULL, 0}, }; + +void s_init(void) +{ +} diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h new file mode 100644 index 0000000..b333937 --- /dev/null +++ b/include/configs/mx6_common.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __MX6_COMMON_H +#define __MX6_COMMON_H + +#define CONFIG_ARM_ERRATA_743622 +#define CONFIG_ARM_ERRATA_751472 + +#endif diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 138e460..bd52cde 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -24,6 +24,9 @@ #define CONFIG_MX6 #define CONFIG_MX6Q + +#include "mx6_common.h" + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h index f7e8779..9eda9ed 100644 --- a/include/configs/mx6qsabre_common.h +++ b/include/configs/mx6qsabre_common.h @@ -19,6 +19,9 @@ #define CONFIG_MX6 #define CONFIG_MX6Q + +#include "mx6_common.h" + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index c8c3ccc..5dc8255 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -24,6 +24,9 @@ #define CONFIG_MX6 #define CONFIG_MX6Q + +#include "mx6_common.h" + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- cgit v0.10.2 From 7315e3bf2cc95abf9ae53f43ccbd31c6f638aacd Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 7 Mar 2013 07:32:53 +0000 Subject: mx23_olinuxino: Fix warning for implicit declaration Fixes a build warning of implicit declaration of gpio_direction_output, as bellow: ,---- | mx23_olinuxino.c: In function 'board_early_init_f': | mx23_olinuxino.c:51:2: warning: implicit declaration | of function 'gpio_direction_output' | [-Wimplicit-function-declaration] `---- Signed-off-by: Otavio Salvador diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 9252717..9ed7718 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include -- cgit v0.10.2 From a32f42f65d30fc2ac15fb14e00779db5bc780153 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 26 Feb 2013 13:08:53 -0500 Subject: am335x_evm: Never set CONFIG_EXTRA_ENV_SETTINGS in SPL Because of our support for network-based SPL, we don't discard all of the environment related functions. We however never make use of the default CONFIG_EXTRA_ENV_SETTINGS items and as this variable grows, it brings us closer to (or with some toolchains, over) our SPL size limit. Never set this in the case of SPL. Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 0dc2a50..630cd48 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -49,6 +49,7 @@ #define CONFIG_BOOTDELAY 1 #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x80F80000\0" \ @@ -133,6 +134,8 @@ "if test $board_name = A335X_SK; then " \ "setenv fdtfile am335x-evmsk.dtb; fi\0" \ +#endif + #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ @@ -367,7 +370,6 @@ */ #undef CONFIG_SPL_ETH_SUPPORT #undef CONFIG_SPL_YMODEM_SUPPORT -#undef CONFIG_EXTRA_ENV_SETTINGS #endif /* -- cgit v0.10.2 From 98bc1228c800005e7addf95632e23079a236e5f5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 26 Feb 2013 15:43:22 -0500 Subject: am335x_evm: Add am335x_evm_usbspl build target We add USB (RNDIS gadget) SPL support as a separate target. We need to pull out YMODEM support in order to be a small enough target binary. Signed-off-by: Tom Rini diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 441758f..f4b972b 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -73,7 +73,7 @@ static inline int board_is_idk(void) return !strncmp(header.config, "SKU#02", 6); } -static int board_is_gp_evm(void) +static int __maybe_unused board_is_gp_evm(void) { return !strncmp("A33515BB", header.name, 8); } diff --git a/boards.cfg b/boards.cfg index 7a0b79d..c117368 100644 --- a/boards.cfg +++ b/boards.cfg @@ -239,6 +239,7 @@ am335x_evm_uart2 arm armv7 am335x ti am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4 am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5 am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 +am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT pcm051 arm armv7 pcm051 phytec am33xx pcm051 highbank arm armv7 highbank - highbank mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 630cd48..35a71ca 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -365,11 +365,9 @@ /* disable host part of MUSB in SPL */ #undef CONFIG_MUSB_HOST /* - * Disable UART, CPSW ethernet support and extra environment settings so we - * will fit within 101KiB. + * Disable CPSW SPL support so we fit within the 101KiB limit. */ #undef CONFIG_SPL_ETH_SUPPORT -#undef CONFIG_SPL_YMODEM_SUPPORT #endif /* -- cgit v0.10.2 From 1c382ead7a0081140e4961f2a03a20abd5e41f05 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 26 Feb 2013 16:35:33 -0500 Subject: am33xx: Update DDR3 EMIF configuration sequence Based on http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips we need to re-work our sequence in config_sdram slightly to match what the TRM describes as the correct sequence. In our current (incorrect) sequence some edge cases may fail to initalize correctly. Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index fd9fc4a..448cc40 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -45,13 +45,19 @@ static struct ddr_cmdtctrl *ioctrl_reg = { */ void config_sdram(const struct emif_regs *regs) { - writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); - writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); - if (regs->zq_config){ + if (regs->zq_config) { + /* + * A value of 0x2800 for the REF CTRL will give us + * about 570us for a delay, which will be long enough + * to configure things. + */ + writel(0x2800, &emif_reg->emif_sdram_ref_ctrl); writel(regs->zq_config, &emif_reg->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); } writel(regs->sdram_config, &emif_reg->emif_sdram_config); + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); } /** -- cgit v0.10.2 From fa3a69289f95efc01db0b15df326884973e80156 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Mon, 3 Dec 2012 02:19:41 +0000 Subject: omap: consolidate common mmc definitions The various mmc_host_def.h files are almost identical. Reduce code duplication by moving the similar definitions to a common header file. Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 1f597c0..33c9c83 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -16,148 +16,12 @@ #ifndef MMC_HOST_DEF_H #define MMC_HOST_DEF_H +#include + /* * OMAP HSMMC register definitions */ #define OMAP_HSMMC1_BASE 0x48060100 #define OMAP_HSMMC2_BASE 0x481D8100 -typedef struct hsmmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ -} hsmmc_t; - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define MSBS_MULTIBLK (0x1 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define CMDI_MASK (0x1 << 0) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) - -/* Clock Configurations and Macros */ -#define MMC_CLOCK_REFERENCE 96 /* MHz */ - -#define mmc_reg_out(addr, mask, val)\ - writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) - -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); - #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h index 3ce1f07..0ba621a 100644 --- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h @@ -25,6 +25,8 @@ #ifndef MMC_HOST_DEF_H #define MMC_HOST_DEF_H +#include + /* T2 Register definitions */ #define T2_BASE 0x48002000 @@ -59,142 +61,5 @@ typedef struct t2 { #define OMAP_HSMMC2_BASE 0x480B4000 #define OMAP_HSMMC3_BASE 0x480AD000 -struct hsmmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ -}; - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define MSBS_MULTIBLK (0x1 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define CMDI_MASK (0x1 << 0) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) - -/* Clock Configurations and Macros */ -#define MMC_CLOCK_REFERENCE 96 /* MHz */ - -#define mmc_reg_out(addr, mask, val)\ - writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) - -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h index 2114046..9c8ccb6 100644 --- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h @@ -25,6 +25,8 @@ #ifndef MMC_HOST_DEF_H #define MMC_HOST_DEF_H +#include + /* * OMAP HSMMC register definitions */ @@ -33,142 +35,4 @@ #define OMAP_HSMMC2_BASE 0x480B4100 #define OMAP_HSMMC3_BASE 0x480AD100 -struct hsmmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ -}; - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define MSBS_MULTIBLK (0x1 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define CMDI_MASK (0x1 << 0) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) - -/* Clock Configurations and Macros */ -#define MMC_CLOCK_REFERENCE 96 /* MHz */ - -#define mmc_reg_out(addr, mask, val)\ - writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) - -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); - #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h index 2114046..9c8ccb6 100644 --- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h @@ -25,6 +25,8 @@ #ifndef MMC_HOST_DEF_H #define MMC_HOST_DEF_H +#include + /* * OMAP HSMMC register definitions */ @@ -33,142 +35,4 @@ #define OMAP_HSMMC2_BASE 0x480B4100 #define OMAP_HSMMC3_BASE 0x480AD100 -struct hsmmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ -}; - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define MSBS_MULTIBLK (0x1 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define CMDI_MASK (0x1 << 0) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) - -/* Clock Configurations and Macros */ -#define MMC_CLOCK_REFERENCE 96 /* MHz */ - -#define mmc_reg_out(addr, mask, val)\ - writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) - -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); - #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h new file mode 100644 index 0000000..83726ee --- /dev/null +++ b/arch/arm/include/asm/omap_mmc.h @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef OMAP_MMC_H_ +#define OMAP_MMC_H_ + +struct hsmmc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int sysstatus; /* 0x14 */ + unsigned char res2[0x14]; + unsigned int con; /* 0x2C */ + unsigned char res3[0xD4]; + unsigned int blk; /* 0x104 */ + unsigned int arg; /* 0x108 */ + unsigned int cmd; /* 0x10C */ + unsigned int rsp10; /* 0x110 */ + unsigned int rsp32; /* 0x114 */ + unsigned int rsp54; /* 0x118 */ + unsigned int rsp76; /* 0x11C */ + unsigned int data; /* 0x120 */ + unsigned int pstate; /* 0x124 */ + unsigned int hctl; /* 0x128 */ + unsigned int sysctl; /* 0x12C */ + unsigned int stat; /* 0x130 */ + unsigned int ie; /* 0x134 */ + unsigned char res4[0x8]; + unsigned int capa; /* 0x140 */ +}; + +/* + * OMAP HS MMC Bit definitions + */ +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_DISABLE (0x0 << 0) +#define BCE_DISABLE (0x0 << 1) +#define BCE_ENABLE (0x1 << 1) +#define ACEN_DISABLE (0x0 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define MSBS_MULTIBLK (0x1 << 5) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define CMDI_MASK (0x1 << 0) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_DISABLE (0x0 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS30_3V0SUP (1 << 25) +#define VS18_1V8SUP (1 << 26) + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE 512 +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) + +/* Clock Configurations and Macros */ +#define MMC_CLOCK_REFERENCE 96 /* MHz */ + +#define mmc_reg_out(addr, mask, val)\ + writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) + +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); + + +#endif /* OMAP_MMC_H_ */ -- cgit v0.10.2 From 5964dadd0371238cbc91b1c2b6b24fd7d83833d8 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Mon, 3 Dec 2012 02:19:42 +0000 Subject: omap_hsmmc: fix out of bounds array access There are 3 MMC/SD/SDIO controllers in OMAP SoCs, but only 2 structs are defined for devices. This leads to data being written outside of array bounds on systems that use all 3 controllers. Update hsmmc_dev array to the correct size. Signed-off-by: Nikita Kiryanov diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index afd9b30..23dcebd 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -44,7 +44,7 @@ static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int siz); -static struct mmc hsmmc_dev[2]; +static struct mmc hsmmc_dev[3]; #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) static void omap4_vmmc_pbias_config(struct mmc *mmc) -- cgit v0.10.2 From cc22b0c0122cee0ab59dcc3c06c52835b38e8791 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Mon, 3 Dec 2012 02:19:43 +0000 Subject: omap_hsmmc: introduce omap_hsmmc_data struct Currently there's no appropriate place to store driver specific data because the pointer that is meant for that (priv) is being used to store the base address of mmc registers. Introduce a new struct for storing driver specific data. Signed-off-by: Nikita Kiryanov diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 23dcebd..0fdbac3 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -38,6 +38,10 @@ #define SYSCTL_SRC (1 << 25) #define SYSCTL_SRD (1 << 26) +struct omap_hsmmc_data { + struct hsmmc *base_addr; +}; + /* If we fail after 1 second wait, something is really bad */ #define MAX_RETRY_MS 1000 @@ -45,6 +49,7 @@ static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int siz); static struct mmc hsmmc_dev[3]; +static struct omap_hsmmc_data hsmmc_dev_data[3]; #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) static void omap4_vmmc_pbias_config(struct mmc *mmc) @@ -177,11 +182,12 @@ void mmc_init_stream(struct hsmmc *mmc_base) static int mmc_init_setup(struct mmc *mmc) { - struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; + struct hsmmc *mmc_base; unsigned int reg_val; unsigned int dsor; ulong start; + mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; mmc_board_init(mmc); writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, @@ -262,10 +268,11 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; + struct hsmmc *mmc_base; unsigned int flags, mmc_stat; ulong start; + mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; start = get_timer(0); while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { if (get_timer(0) - start > MAX_RETRY_MS) { @@ -489,10 +496,11 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, static void mmc_set_ios(struct mmc *mmc) { - struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; + struct hsmmc *mmc_base; unsigned int dsor = 0; ulong start; + mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; /* configue bus width */ switch (mmc->bus_width) { case 8: @@ -542,32 +550,32 @@ static void mmc_set_ios(struct mmc *mmc) int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max) { - struct mmc *mmc; - - mmc = &hsmmc_dev[dev_index]; + struct mmc *mmc = &hsmmc_dev[dev_index]; + struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index]; sprintf(mmc->name, "OMAP SD/MMC"); mmc->send_cmd = mmc_send_cmd; mmc->set_ios = mmc_set_ios; mmc->init = mmc_init_setup; mmc->getcd = NULL; + mmc->priv = priv_data; switch (dev_index) { case 0: - mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE; + priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; break; #ifdef OMAP_HSMMC2_BASE case 1: - mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE; + priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; break; #endif #ifdef OMAP_HSMMC3_BASE case 2: - mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE; + priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; break; #endif default: - mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE; + priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; return 1; } mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; -- cgit v0.10.2 From e874d5b001e9d7ea0fc7596ef0fe6dd520ed8ec6 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Mon, 3 Dec 2012 02:19:44 +0000 Subject: omap_hsmmc: implement driver check for card detection Implement driver check for card detection. Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index ab31326..7def17e 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -56,11 +56,11 @@ int cpu_mmc_init(bd_t *bis) { int ret; - ret = omap_mmc_init(0, 0, 0); + ret = omap_mmc_init(0, 0, 0, -1); if (ret) return ret; - return omap_mmc_init(1, 0, 0); + return omap_mmc_init(1, 0, 0, -1); } #endif diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 1c8b617..793e82e 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -64,11 +64,11 @@ int board_mmc_init(bd_t *bis) { switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0); + omap_mmc_init(0, 0, 0, -1); break; case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: - omap_mmc_init(1, 0, 0); + omap_mmc_init(1, 0, 0, -1); break; } return 0; diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 89c587e..f9f7aae 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -98,11 +98,11 @@ int board_mmc_init(bd_t *bis) { switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0); + omap_mmc_init(0, 0, 0, -1); break; case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: - omap_mmc_init(1, 0, 0); + omap_mmc_init(1, 0, 0, -1); break; } return 0; diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 83726ee..8d86de1 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -161,7 +161,7 @@ struct hsmmc { #define mmc_reg_out(addr, mask, val)\ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio); #endif /* OMAP_MMC_H_ */ diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index edbb941..89e0fd3 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -379,7 +379,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index c6c1071..2a55cb8 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -147,8 +147,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index 56fe495..23e15be 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -80,7 +80,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD)) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 9fe6408..5cf5bb6 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -114,7 +114,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 49fcf34..3a2a023 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -150,8 +150,7 @@ static inline void setup_net_chip(void) {} #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 0b3721e..26f0289 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -135,8 +135,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 12bcfcb..fc11812 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -140,7 +140,7 @@ int board_init(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 90b6b0f..e02dc34 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -92,8 +92,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c index 8e18019..a622b9a 100644 --- a/board/logicpd/zoom2/zoom2.c +++ b/board/logicpd/zoom2/zoom2.c @@ -183,8 +183,7 @@ void set_muxconf_regs (void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c index f68f312..cb1e0c8 100644 --- a/board/matrix_vision/mvblx/mvblx.c +++ b/board/matrix_vision/mvblx/mvblx.c @@ -106,8 +106,8 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - omap_mmc_init(1, 0, 0); + omap_mmc_init(0, 0, 0, -1); + omap_mmc_init(1, 0, 0, -1); return 0; } #endif diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index b2fe1c5..f303e1e 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -671,7 +671,7 @@ int rx51_kp_getc(void) */ int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - omap_mmc_init(1, 0, 0); + omap_mmc_init(0, 0, 0, -1); + omap_mmc_init(1, 0, 0, -1); return 0; } diff --git a/board/overo/overo.c b/board/overo/overo.c index fdf46a2..c5b4d5b 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -392,7 +392,6 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 3a62e9d..e2feff8 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -139,7 +139,6 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index c9eea9b..0d44bae 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -147,7 +147,7 @@ int board_eth_init(bd_t *bis) !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index c516c75..6f6c515 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -304,7 +304,7 @@ int board_eth_init(bd_t *bis) !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0); + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index 888398d..91b6822 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -78,7 +78,6 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 58bd556..51dbd5d 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -532,8 +532,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 8a3aa0c..42a98ff 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -277,7 +277,6 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c index c8dfdf8..45d4704 100644 --- a/board/ti/omap5_evm/evm.c +++ b/board/ti/omap5_evm/evm.c @@ -94,8 +94,8 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - omap_mmc_init(1, 0, 0); + omap_mmc_init(0, 0, 0, -1); + omap_mmc_init(1, 0, 0, -1); return 0; } #endif diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 4feef78..ebbb8b1 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -179,8 +179,7 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c index 9a1c012..e256815 100644 --- a/board/ti/sdp3430/sdp.c +++ b/board/ti/sdp3430/sdp.c @@ -209,7 +209,6 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 982c771..167f3cb 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -108,8 +108,8 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - omap_mmc_init(1, 0, 0); + omap_mmc_init(0, 0, 0, -1); + omap_mmc_init(1, 0, 0, -1); return 0; } #endif diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 85685ee..0fb8065 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -136,8 +136,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0); - return 0; + return omap_mmc_init(0, 0, 0, -1); } #endif diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 0fdbac3..cb1a7bd 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,7 @@ struct omap_hsmmc_data { struct hsmmc *base_addr; + int cd_gpio; }; /* If we fail after 1 second wait, something is really bad */ @@ -51,6 +53,36 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, static struct mmc hsmmc_dev[3]; static struct omap_hsmmc_data hsmmc_dev_data[3]; +#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) +static int omap_mmc_setup_gpio_in(int gpio, const char *label) +{ + if (!gpio_is_valid(gpio)) + return -1; + + if (gpio_request(gpio, label) < 0) + return -1; + + if (gpio_direction_input(gpio) < 0) + return -1; + + return gpio; +} + +static int omap_mmc_getcd(struct mmc *mmc) +{ + int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio; + return gpio_get_value(cd_gpio); +} +#else +static inline int omap_mmc_setup_gpio_in(int gpio, const char *label) +{ + return -1; +} + +#define omap_mmc_getcd NULL +#endif + #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) static void omap4_vmmc_pbias_config(struct mmc *mmc) { @@ -548,7 +580,7 @@ static void mmc_set_ios(struct mmc *mmc) writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); } -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max) +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio) { struct mmc *mmc = &hsmmc_dev[dev_index]; struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index]; @@ -557,7 +589,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max) mmc->send_cmd = mmc_send_cmd; mmc->set_ios = mmc_set_ios; mmc->init = mmc_init_setup; - mmc->getcd = NULL; + mmc->getcd = omap_mmc_getcd; mmc->priv = priv_data; switch (dev_index) { @@ -578,6 +610,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max) priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; return 1; } + priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC) & ~host_caps_mask; -- cgit v0.10.2 From 5c1214de8c7b8b3e807ec09508e653580872e599 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Mon, 3 Dec 2012 02:19:45 +0000 Subject: cm-t35: implement board specific card detect check Implement a card detection check for cm-t35. Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 89e0fd3..dfd91e7 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -377,6 +378,16 @@ void set_muxconf_regs(void) } #ifdef CONFIG_GENERIC_MMC +int board_mmc_getcd(struct mmc *mmc) +{ + u8 val; + + if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, TWL4030_BASEADD_GPIO)) + return -1; + + return !(val & 1); +} + int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1); -- cgit v0.10.2 From d23d8d7e069c3aca071b7f68d9c15d11f8d4c84d Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Mon, 3 Dec 2012 02:19:46 +0000 Subject: mmc: add support for write protection Add generic mmc write protection functionality. Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 7dacd51..8c53a10 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -282,6 +282,13 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) mmc_init(mmc); + if ((state == MMC_WRITE || state == MMC_ERASE)) { + if (mmc_getwp(mmc) == 1) { + printf("Error: card is write protected!\n"); + return 1; + } + } + switch (state) { case MMC_READ: n = mmc->block_dev.block_read(curr_device, blk, diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index af1380a..ab2e81e 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -377,6 +377,7 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host) dev->set_ios = host_set_ios; dev->init = mmc_host_reset; dev->getcd = NULL; + dev->getwp = NULL; dev->host_caps = host->caps; dev->voltages = host->voltages; dev->f_min = host->clock_min; diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 8d59d46..81d8e54 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -251,6 +251,7 @@ int bfin_mmc_init(bd_t *bis) mmc->set_ios = bfin_sdh_set_ios; mmc->init = bfin_sdh_init; mmc->getcd = NULL; + mmc->getwp = NULL; mmc->host_caps = MMC_MODE_4BIT; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index ee8f261..e2379e3 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -388,6 +388,7 @@ int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host) mmc->set_ios = dmmc_set_ios; mmc->init = dmmc_init; mmc->getcd = NULL; + mmc->getwp = NULL; mmc->f_min = 200000; mmc->f_max = 25000000; diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index b90f3e7..54b5363 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -552,6 +552,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) mmc->set_ios = esdhc_set_ios; mmc->init = esdhc_init; mmc->getcd = esdhc_getcd; + mmc->getwp = NULL; voltage_caps = 0; caps = regs->hostcapblt; diff --git a/drivers/mmc/ftsdc010_esdhc.c b/drivers/mmc/ftsdc010_esdhc.c index f1702fe..42f0e0c 100644 --- a/drivers/mmc/ftsdc010_esdhc.c +++ b/drivers/mmc/ftsdc010_esdhc.c @@ -666,6 +666,7 @@ int ftsdc010_mmc_init(int dev_index) mmc->set_ios = ftsdc010_set_ios; mmc->init = ftsdc010_core_init; mmc->getcd = NULL; + mmc->getwp = NULL; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 67b2dbe..70a9f91 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -349,6 +349,7 @@ int atmel_mci_init(void *regs) mmc->set_ios = mci_set_ios; mmc->init = mci_init; mmc->getcd = NULL; + mmc->getwp = NULL; /* need to be able to pass these in on a board by board basis */ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 72e8ce6..7b5fdd9 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -40,6 +40,23 @@ static struct list_head mmc_devices; static int cur_dev_num = -1; +int __weak board_mmc_getwp(struct mmc *mmc) +{ + return -1; +} + +int mmc_getwp(struct mmc *mmc) +{ + int wp; + + wp = board_mmc_getwp(mmc); + + if ((wp < 0) && mmc->getwp) + wp = mmc->getwp(mmc); + + return wp; +} + int __board_mmc_getcd(struct mmc *mmc) { return -1; } diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index 11ba532..fe6a5a1 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -273,6 +273,7 @@ struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode) mmc->set_ios = mmc_spi_set_ios; mmc->init = mmc_spi_init_p; mmc->getcd = NULL; + mmc->getwp = NULL; mmc->host_caps = MMC_MODE_SPI; mmc->voltages = MMC_SPI_VOLTAGE; diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c index d58c18b..4f99617 100644 --- a/drivers/mmc/mxcmmc.c +++ b/drivers/mmc/mxcmmc.c @@ -499,6 +499,7 @@ static int mxcmci_initialize(bd_t *bis) mmc->set_ios = mxcmci_set_ios; mmc->init = mxcmci_init; mmc->getcd = NULL; + mmc->getwp = NULL; mmc->host_caps = MMC_MODE_4BIT; host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE; diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index a72f66c..a87529d 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -432,6 +432,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) mmc->set_ios = mxsmmc_set_ios; mmc->init = mxsmmc_init; mmc->getcd = NULL; + mmc->getwp = NULL; mmc->priv = priv; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index cb1a7bd..fcbd133 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -590,6 +590,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio) mmc->set_ios = mmc_set_ios; mmc->init = mmc_init_setup; mmc->getcd = omap_mmc_getcd; + mmc->getwp = NULL; mmc->priv = priv_data; switch (dev_index) { diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index b9cbe34..daca0ea 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -438,6 +438,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) mmc->set_ios = sdhci_set_ios; mmc->init = sdhci_init; mmc->getcd = NULL; + mmc->getwp = NULL; caps = sdhci_readl(host, SDHCI_CAPABILITIES); #ifdef CONFIG_MMC_SDMA diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 4588568..011d4f3 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -599,6 +599,7 @@ int mmcif_mmc_init(void) mmc->set_ios = sh_mmcif_set_ios; mmc->init = sh_mmcif_init; mmc->getcd = NULL; + mmc->getwp = NULL; host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; host->clk = CONFIG_SH_MMCIF_CLK; mmc->priv = host; diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index d749ab0..7258619 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -563,6 +563,7 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) mmc->set_ios = mmc_set_ios; mmc->init = mmc_core_init; mmc->getcd = tegra_mmc_getcd; + mmc->getwp = NULL; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; mmc->host_caps = 0; diff --git a/include/mmc.h b/include/mmc.h index a13e2bd..de6d497 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -259,6 +259,7 @@ struct mmc { void (*set_ios)(struct mmc *mmc); int (*init)(struct mmc *mmc); int (*getcd)(struct mmc *mmc); + int (*getwp)(struct mmc *mmc); uint b_max; }; @@ -274,6 +275,7 @@ int get_mmc_num(void); int board_mmc_getcd(struct mmc *mmc); int mmc_switch_part(int dev_num, unsigned int part_num); int mmc_getcd(struct mmc *mmc); +int mmc_getwp(struct mmc *mmc); void spl_mmc_load(void) __noreturn; #ifdef CONFIG_GENERIC_MMC -- cgit v0.10.2 From e3913f56a26dbb49758370320dac477ab0324631 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Mon, 3 Dec 2012 02:19:47 +0000 Subject: omap_hsmmc: add driver check for write protection Add check for write protection in omap mmc driver. Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 7def17e..e35a3e3 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -56,11 +56,11 @@ int cpu_mmc_init(bd_t *bis) { int ret; - ret = omap_mmc_init(0, 0, 0, -1); + ret = omap_mmc_init(0, 0, 0, -1, -1); if (ret) return ret; - return omap_mmc_init(1, 0, 0, -1); + return omap_mmc_init(1, 0, 0, -1, -1); } #endif diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 793e82e..24cbe2d 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -64,11 +64,11 @@ int board_mmc_init(bd_t *bis) { switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0, -1); + omap_mmc_init(0, 0, 0, -1, -1); break; case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: - omap_mmc_init(1, 0, 0, -1); + omap_mmc_init(1, 0, 0, -1, -1); break; } return 0; diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index f9f7aae..23ccc59 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -98,11 +98,11 @@ int board_mmc_init(bd_t *bis) { switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0, -1); + omap_mmc_init(0, 0, 0, -1, -1); break; case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: - omap_mmc_init(1, 0, 0, -1); + omap_mmc_init(1, 0, 0, -1, -1); break; } return 0; diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 8d86de1..617e22f 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -161,7 +161,8 @@ struct hsmmc { #define mmc_reg_out(addr, mask, val)\ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio); +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, + int wp_gpio); #endif /* OMAP_MMC_H_ */ diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index dfd91e7..e470d96 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -390,7 +390,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, 59); } #endif diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index 2a55cb8..2dca275 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -147,7 +147,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index 23e15be..5c02eaf 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -80,7 +80,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD)) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 5cf5bb6..46fa7e4 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -114,7 +114,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 3a2a023..2bac916 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -150,7 +150,7 @@ static inline void setup_net_chip(void) {} #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 26f0289..65e1b78 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -135,7 +135,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index fc11812..6e83aa2 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -140,7 +140,7 @@ int board_init(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index e02dc34..c79a261 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -92,7 +92,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c index a622b9a..ad6ae36 100644 --- a/board/logicpd/zoom2/zoom2.c +++ b/board/logicpd/zoom2/zoom2.c @@ -183,7 +183,7 @@ void set_muxconf_regs (void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c index cb1e0c8..49af384 100644 --- a/board/matrix_vision/mvblx/mvblx.c +++ b/board/matrix_vision/mvblx/mvblx.c @@ -106,8 +106,8 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0, -1); - omap_mmc_init(1, 0, 0, -1); + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); return 0; } #endif diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index f303e1e..48eb65f 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -671,7 +671,7 @@ int rx51_kp_getc(void) */ int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0, -1); - omap_mmc_init(1, 0, 0, -1); + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); return 0; } diff --git a/board/overo/overo.c b/board/overo/overo.c index c5b4d5b..8690450 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -392,6 +392,6 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index e2feff8..9ff5dd7 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -139,6 +139,6 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index 0d44bae..5f197a7 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -147,7 +147,7 @@ int board_eth_init(bd_t *bis) !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index 6f6c515..2de0e81 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -304,7 +304,7 @@ int board_eth_init(bd_t *bis) !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index 91b6822..0b94245 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -78,6 +78,6 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 51dbd5d..3d9b6dd 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -532,7 +532,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 42a98ff..3c2dcab 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -277,6 +277,6 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c index 45d4704..55337c0 100644 --- a/board/ti/omap5_evm/evm.c +++ b/board/ti/omap5_evm/evm.c @@ -94,8 +94,8 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0, -1); - omap_mmc_init(1, 0, 0, -1); + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); return 0; } #endif diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index ebbb8b1..cab0598 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -179,7 +179,7 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c index e256815..052efc5 100644 --- a/board/ti/sdp3430/sdp.c +++ b/board/ti/sdp3430/sdp.c @@ -209,6 +209,6 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 167f3cb..4c1a4f7 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -108,8 +108,8 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0, 0, 0, -1); - omap_mmc_init(1, 0, 0, -1); + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); return 0; } #endif diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 0fb8065..22b3fac 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -136,7 +136,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0, 0, 0, -1); + return omap_mmc_init(0, 0, 0, -1, -1); } #endif diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index fcbd133..d0b2820 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -42,6 +42,7 @@ struct omap_hsmmc_data { struct hsmmc *base_addr; int cd_gpio; + int wp_gpio; }; /* If we fail after 1 second wait, something is really bad */ @@ -74,6 +75,12 @@ static int omap_mmc_getcd(struct mmc *mmc) int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio; return gpio_get_value(cd_gpio); } + +static int omap_mmc_getwp(struct mmc *mmc) +{ + int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio; + return gpio_get_value(wp_gpio); +} #else static inline int omap_mmc_setup_gpio_in(int gpio, const char *label) { @@ -81,6 +88,7 @@ static inline int omap_mmc_setup_gpio_in(int gpio, const char *label) } #define omap_mmc_getcd NULL +#define omap_mmc_getwp NULL #endif #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) @@ -580,7 +588,8 @@ static void mmc_set_ios(struct mmc *mmc) writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); } -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio) +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, + int wp_gpio) { struct mmc *mmc = &hsmmc_dev[dev_index]; struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index]; @@ -590,7 +599,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio) mmc->set_ios = mmc_set_ios; mmc->init = mmc_init_setup; mmc->getcd = omap_mmc_getcd; - mmc->getwp = NULL; + mmc->getwp = omap_mmc_getwp; mmc->priv = priv_data; switch (dev_index) { @@ -612,6 +621,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio) return 1; } priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); + priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC) & ~host_caps_mask; -- cgit v0.10.2 From bc84b18f7512b979c3ee2917a372bde56cc13aa5 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 30 Jan 2013 21:39:54 +0000 Subject: omap3: add useful dss defines Add useful omap3 dss defines for: polarity, TFT data lines, lcd display type, gfx burst size, and gfx format Cc: Anatolij Gustschin Cc: Jeroen Hofstee Cc: Tom Rini Cc: Wolfgang Denk Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index ffaffbb..0cbef84 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -167,6 +167,36 @@ struct venc_regs { #define VENC_OUT_SEL (1 << 6) #define DIG_LPP_SHIFT 16 +/* LCD display type */ +#define PASSIVE_DISPLAY 0 +#define ACTIVE_DISPLAY 1 + +/* TFTDATALINES */ +#define LCD_INTERFACE_12_BIT 0 +#define LCD_INTERFACE_16_BIT 1 +#define LCD_INTERFACE_18_BIT 2 +#define LCD_INTERFACE_24_BIT 3 + +/* Polarity */ +#define DSS_IVS (1 << 12) +#define DSS_IHS (1 << 13) +#define DSS_IPC (1 << 14) +#define DSS_IEO (1 << 15) + +/* GFX format */ +#define GFXFORMAT_BITMAP1 (0x0 << 1) +#define GFXFORMAT_BITMAP2 (0x1 << 1) +#define GFXFORMAT_BITMAP4 (0x2 << 1) +#define GFXFORMAT_BITMAP8 (0x3 << 1) +#define GFXFORMAT_RGB12 (0x4 << 1) +#define GFXFORMAT_ARGB16 (0x5 << 1) +#define GFXFORMAT_RGB16 (0x6 << 1) +#define GFXFORMAT_RGB24_UNPACKED (0x8 << 1) +#define GFXFORMAT_RGB24_PACKED (0x9 << 1) +#define GFXFORMAT_ARGB32 (0xC << 1) +#define GFXFORMAT_RGBA32 (0xD << 1) +#define GFXFORMAT_RGBx32 (0xE << 1) + /* Panel Configuration */ struct panel_config { u32 timing_h; -- cgit v0.10.2 From bcc6cc9b3777f0c7246ff441f1d275552109713e Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 30 Jan 2013 21:39:55 +0000 Subject: omap3: allow dynamic selection of gfx_format Currently, omap3_dss_panel_config() sets gfx_format to a value that is hardcoded in the code. This forces anyone who wants to use a different gfx_format to make adjustments after calling omap3_dss_panel_config(). This could be avoided if the value of gfx_format were parameterized as input for omap3_dss_panel_config(). Make gfx_format a field in struct panel_config, and update existing structs to set this field to the value that was originally hard coded. Cc: Wolfgang Denk Cc: Jeroen Hofstee Cc: Tom Rini Cc: Anatolij Gustschin Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index 0cbef84..ae0babf 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -208,6 +208,7 @@ struct panel_config { u32 data_lines; u32 load_mode; u32 panel_color; + u32 gfx_format; void *frame_buffer; }; diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 46fa7e4..923461a 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -130,6 +130,7 @@ static struct panel_config lcd_cfg = { .load_mode = 0x02, /* Frame Mode */ .panel_color = 0, .lcd_size = PANEL_LCD_SIZE(800, 480), + .gfx_format = GFXFORMAT_RGB24_UNPACKED, }; int board_video_init(void) diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index 2de0e81..d576786 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -81,6 +81,7 @@ static struct panel_config lcd_cfg[] = { .data_lines = 0x03, /* 24 Bit RGB */ .load_mode = 0x02, /* Frame Mode */ .panel_color = 0, + .gfx_format = GFXFORMAT_RGB24_UNPACKED, }, { .timing_h = PANEL_TIMING_H(20, 192, 4), @@ -91,6 +92,7 @@ static struct panel_config lcd_cfg[] = { .data_lines = 0x03, /* 24 Bit RGB */ .load_mode = 0x02, /* Frame Mode */ .panel_color = 0, + .gfx_format = GFXFORMAT_RGB24_UNPACKED, } }; #endif diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index c0a94a9..6d71bbc 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -544,7 +544,8 @@ static const struct panel_config dvid_cfg = { .panel_type = 0x01, /* TFT */ .data_lines = 0x03, /* 24 Bit RGB */ .load_mode = 0x02, /* Frame Mode */ - .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */ + .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */ + .gfx_format = GFXFORMAT_RGB24_UNPACKED, }; static const struct panel_config dvid_cfg_xm = { @@ -556,6 +557,7 @@ static const struct panel_config dvid_cfg_xm = { .panel_type = 0x01, /* TFT */ .data_lines = 0x03, /* 24 Bit RGB */ .load_mode = 0x02, /* Frame Mode */ - .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */ + .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */ + .gfx_format = GFXFORMAT_RGB24_UNPACKED, }; #endif diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c index b1424bf..6efba12 100644 --- a/drivers/video/omap3_dss.c +++ b/drivers/video/omap3_dss.c @@ -121,7 +121,7 @@ void omap3_dss_panel_config(const struct panel_config *panel_cfg) if (!panel_cfg->frame_buffer) return; - writel(8 << GFX_FORMAT_SHIFT | GFX_ENABLE, &dispc->gfx_attributes); + writel(panel_cfg->gfx_format | GFX_ENABLE, &dispc->gfx_attributes); writel(1, &dispc->gfx_row_inc); writel(1, &dispc->gfx_pixel_inc); writel(panel_cfg->lcd_size, &dispc->gfx_size); -- cgit v0.10.2 From 581bb41980a38c6ddac40f07ec1c8dcd37aca8f6 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 30 Jan 2013 21:39:57 +0000 Subject: lcd: add option for board specific splash screen preparation Currently there is no logical place to put the code that prepares the splash image data. The splash image data should be ready in memory before bmp_display() is called, and after the environment is ready (since lcd.c looks for the splash image in an address specified by the environment variable "splashimage"). Our window of opportunity in board_init_r() is therefore: between env_relocate() and bmp_display(), and from the available options only the lcd related functions in drv_lcd_init() seem appropriate for such lcd oriented code. Add the option to prepare the splash image data in lcd_logo() right before it is sent to be displayed. Cc: Anatolij Gustschin Cc: Jeroen Hofstee Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/README b/README index d8cb394..b8ed1f1 100644 --- a/README +++ b/README @@ -1550,6 +1550,14 @@ CBFS (Coreboot Filesystem) support => vertically centered image at x = dspWidth - bmpWidth - 9 + CONFIG_SPLASH_SCREEN_PREPARE + + If this option is set then the board_splash_screen_prepare() + function, which must be defined in your code, is called as part + of the splash screen display sequence. It gives the board an + opportunity to prepare the splash image data before it is + processed and sent to the frame buffer by U-Boot. + - Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP If this option is set, additionally to standard BMP diff --git a/common/lcd.c b/common/lcd.c index 66d4f94..ba6975b 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -1034,6 +1034,18 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } #endif +#ifdef CONFIG_SPLASH_SCREEN_PREPARE +static inline int splash_screen_prepare(void) +{ + return board_splash_screen_prepare(); +} +#else +static inline int splash_screen_prepare(void) +{ + return 0; +} +#endif + static void *lcd_logo(void) { #ifdef CONFIG_SPLASH_SCREEN @@ -1045,6 +1057,9 @@ static void *lcd_logo(void) int x = 0, y = 0; do_splash = 0; + if (splash_screen_prepare()) + return (void *)gd->fb_base; + addr = simple_strtoul (s, NULL, 16); #ifdef CONFIG_SPLASH_SCREEN_ALIGN s = getenv("splashpos"); diff --git a/include/lcd.h b/include/lcd.h index c24164a..4ac4ddd 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -47,6 +47,7 @@ extern struct vidinfo panel_info; extern void lcd_ctrl_init (void *lcdbase); extern void lcd_enable (void); +extern int board_splash_screen_prepare(void); /* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */ extern void lcd_setcolreg (ushort regno, -- cgit v0.10.2 From 7878ca51f2d6e2c131c96451e8727fda247d794e Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 30 Jan 2013 21:39:58 +0000 Subject: cm-t35: add support for dvi displays Add support for dvi displays with user selectable dvi presets. Cc: Wolfgang Denk Cc: Jeroen Hofstee Cc: Anatolij Gustschin Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/board/cm_t35/Makefile b/board/cm_t35/Makefile index 894fa09..bde56e6 100644 --- a/board/cm_t35/Makefile +++ b/board/cm_t35/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o +COBJS-$(CONFIG_LCD) += display.o COBJS := cm_t35.o leds.o $(COBJS-y) diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index e470d96..e0e8235 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -217,6 +217,9 @@ static void cm_t3x_set_common_muxconf(void) /* SB-T35 Ethernet */ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ + /* DVI enable */ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ + /* CM-T3x Ethernet */ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ diff --git a/board/cm_t35/display.c b/board/cm_t35/display.c new file mode 100644 index 0000000..43f0628 --- /dev/null +++ b/board/cm_t35/display.c @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2012 CompuLab, Ltd. + * + * Authors: Nikita Kiryanov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum display_type { + NONE, + DVI, +}; + +#define CMAP_ADDR 0x80100000 + +/* + * The frame buffer is allocated before we have the chance to parse user input. + * To make sure enough memory is allocated for all resolutions, we define + * vl_{col | row} to the maximal resolution supported by OMAP3. + */ +vidinfo_t panel_info = { + .vl_col = 1400, + .vl_row = 1050, + .vl_bpix = LCD_BPP, + .cmap = (ushort *)CMAP_ADDR, +}; + +static struct panel_config panel_cfg; +static enum display_type lcd_def; + +/* + * A note on DVI presets; + * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can + * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to + * support two BMP types with one setting. + */ +static const struct panel_config preset_dvi_640X480 = { + .lcd_size = PANEL_LCD_SIZE(640, 480), + .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96), + .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2), + .divisor = 12 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_800X600 = { + .lcd_size = PANEL_LCD_SIZE(800, 600), + .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128), + .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4), + .divisor = 8 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1024X768 = { + .lcd_size = PANEL_LCD_SIZE(1024, 768), + .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136), + .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6), + .divisor = 5 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1152X864 = { + .lcd_size = PANEL_LCD_SIZE(1152, 864), + .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128), + .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3), + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1280X960 = { + .lcd_size = PANEL_LCD_SIZE(1280, 960), + .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112), + .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3), + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1280X1024 = { + .lcd_size = PANEL_LCD_SIZE(1280, 1024), + .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112), + .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3), + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +/* + * set_resolution_params() + * + * Due to usage of multiple display related APIs resolution data is located in + * more than one place. This function updates them all. + */ +static void set_resolution_params(int x, int y) +{ + panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y); + panel_info.vl_col = x; + panel_info.vl_row = y; + lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; +} + +static void set_preset(const struct panel_config preset, int x_res, int y_res) +{ + panel_cfg = preset; + set_resolution_params(x_res, y_res); +} + +static enum display_type set_dvi_preset(const struct panel_config preset, + int x_res, int y_res) +{ + set_preset(preset, x_res, y_res); + return DVI; +} + +/* + * env_parse_displaytype() - parse display type. + * + * Parses the environment variable "displaytype", which contains the + * name of the display type or preset, in which case it applies its + * configurations. + * + * Returns the type of display that was specified. + */ +static enum display_type env_parse_displaytype(char *displaytype) +{ + if (!strncmp(displaytype, "dvi640x480", 10)) + return set_dvi_preset(preset_dvi_640X480, 640, 480); + else if (!strncmp(displaytype, "dvi800x600", 10)) + return set_dvi_preset(preset_dvi_800X600, 800, 600); + else if (!strncmp(displaytype, "dvi1024x768", 11)) + return set_dvi_preset(preset_dvi_1024X768, 1024, 768); + else if (!strncmp(displaytype, "dvi1152x864", 11)) + return set_dvi_preset(preset_dvi_1152X864, 1152, 864); + else if (!strncmp(displaytype, "dvi1280x960", 11)) + return set_dvi_preset(preset_dvi_1280X960, 1280, 960); + else if (!strncmp(displaytype, "dvi1280x1024", 12)) + return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024); + + return NONE; +} + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; +void *lcd_base; +short console_col; +short console_row; +void *lcd_console_address; + +void lcd_ctrl_init(void *lcdbase) +{ + struct prcm *prcm = (struct prcm *)PRCM_BASE; + char *displaytype = getenv("displaytype"); + + if (displaytype == NULL) + return; + + lcd_def = env_parse_displaytype(displaytype); + if (lcd_def == NONE) + return; + + panel_cfg.frame_buffer = lcdbase; + omap3_dss_panel_config(&panel_cfg); + /* + * Pixel clock is defined with many divisions and only few + * multiplications of the system clock. Since DSS FCLK divisor is set + * to 16 by default, we need to set it to a smaller value, like 3 + * (chosen via trial and error). + */ + clrsetbits_le32(&prcm->clksel_dss, 0xF, 3); +} + +void lcd_enable(void) +{ + if (lcd_def == DVI) { + gpio_direction_output(54, 0); /* Turn on DVI */ + omap3_dss_enable(); + } +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {} diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 943b658..e6aef7b 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -336,4 +336,11 @@ #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ #endif +/* Display Configuration */ +#define CONFIG_OMAP3_GPIO_2 +#define CONFIG_VIDEO_OMAP3 +#define LCD_BPP LCD_COLOR16 + +#define CONFIG_LCD + #endif /* __CONFIG_H */ -- cgit v0.10.2 From 4fc4afa9d1e259f89c774e9ec52f6257caa09425 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 30 Jan 2013 21:39:59 +0000 Subject: cm-t35: add support for user defined lcd parameters Add support for user defined lcd parameters for cm-t35 splash screen. Cc: Jeroen Hofstee Cc: Anatolij Gustschin Signed-off-by: Nikita Kiryanov Signed-off-by: Igor Grinberg diff --git a/board/cm_t35/display.c b/board/cm_t35/display.c index 43f0628..2f78bad 100644 --- a/board/cm_t35/display.c +++ b/board/cm_t35/display.c @@ -3,6 +3,8 @@ * * Authors: Nikita Kiryanov * + * Parsing code based on linux/drivers/video/pxafb.c + * * See file CREDITS for list of people who contributed to this * project. * @@ -33,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; enum display_type { NONE, DVI, + DVI_CUSTOM, }; #define CMAP_ADDR 0x80100000 @@ -152,6 +155,206 @@ static enum display_type set_dvi_preset(const struct panel_config preset, } /* + * parse_mode() - parse the mode parameter of custom lcd settings + * + * @mode: x + * + * Returns -1 on error, 0 on success. + */ +static int parse_mode(const char *mode) +{ + unsigned int modelen = strlen(mode); + int res_specified = 0; + unsigned int xres = 0, yres = 0; + int yres_specified = 0; + int i; + + for (i = modelen - 1; i >= 0; i--) { + switch (mode[i]) { + case 'x': + if (!yres_specified) { + yres = simple_strtoul(&mode[i + 1], NULL, 0); + yres_specified = 1; + } else { + goto done_parsing; + } + + break; + case '0' ... '9': + break; + default: + goto done_parsing; + } + } + + if (i < 0 && yres_specified) { + xres = simple_strtoul(mode, NULL, 0); + res_specified = 1; + } + +done_parsing: + if (res_specified) { + set_resolution_params(xres, yres); + } else { + printf("LCD: invalid mode: %s\n", mode); + return -1; + } + + return 0; +} + +#define PIXEL_CLK_NUMERATOR (26 * 432 / 39) +/* + * parse_pixclock() - Parse the pixclock parameter of custom lcd settings + * + * @pixclock: the desired pixel clock + * + * Returns -1 on error, 0 on success. + * + * Handling the pixel_clock: + * + * Pixel clock is defined in the OMAP35x TRM as follows: + * pixel_clock = + * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) / + * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] * + * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1)) + * + * In practice, this means that in order to set the + * divisor for the desired pixel clock one needs to + * solve the following equation: + * + * 26 * 432 / (39 * ) = DSS.DISPC_DIVISOR[6:0] + * + * NOTE: the explicit equation above is reduced. Do not + * try to infer anything from these numbers. + */ +static int parse_pixclock(char *pixclock) +{ + int divisor, pixclock_val; + char *pixclk_start = pixclock; + + pixclock_val = simple_strtoul(pixclock, &pixclock, 10); + divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val); + /* 0 and 1 are illegal values for PCD */ + if (divisor <= 1) + divisor = 2; + + panel_cfg.divisor = divisor | (1 << 16); + if (pixclock[0] != '\0') { + printf("LCD: invalid value for pixclock:%s\n", pixclk_start); + return -1; + } + + return 0; +} + +/* + * parse_setting() - parse a single setting of custom lcd parameters + * + * @setting: The custom lcd setting : + * + * Returns -1 on failure, 0 on success. + */ +static int parse_setting(char *setting) +{ + int num_val; + char *setting_start = setting; + + if (!strncmp(setting, "mode:", 5)) { + return parse_mode(setting + 5); + } else if (!strncmp(setting, "pixclock:", 9)) { + return parse_pixclock(setting + 9); + } else if (!strncmp(setting, "left:", 5)) { + num_val = simple_strtoul(setting + 5, &setting, 0); + panel_cfg.timing_h |= DSS_HBP(num_val); + } else if (!strncmp(setting, "right:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_h |= DSS_HFP(num_val); + } else if (!strncmp(setting, "upper:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_v |= DSS_VBP(num_val); + } else if (!strncmp(setting, "lower:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_v |= DSS_VFP(num_val); + } else if (!strncmp(setting, "hsynclen:", 9)) { + num_val = simple_strtoul(setting + 9, &setting, 0); + panel_cfg.timing_h |= DSS_HSW(num_val); + } else if (!strncmp(setting, "vsynclen:", 9)) { + num_val = simple_strtoul(setting + 9, &setting, 0); + panel_cfg.timing_v |= DSS_VSW(num_val); + } else if (!strncmp(setting, "hsync:", 6)) { + if (simple_strtoul(setting + 6, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IHS; + else + panel_cfg.pol_freq &= ~DSS_IHS; + } else if (!strncmp(setting, "vsync:", 6)) { + if (simple_strtoul(setting + 6, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IVS; + else + panel_cfg.pol_freq &= ~DSS_IVS; + } else if (!strncmp(setting, "outputen:", 9)) { + if (simple_strtoul(setting + 9, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IEO; + else + panel_cfg.pol_freq &= ~DSS_IEO; + } else if (!strncmp(setting, "pixclockpol:", 12)) { + if (simple_strtoul(setting + 12, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IPC; + else + panel_cfg.pol_freq &= ~DSS_IPC; + } else if (!strncmp(setting, "active", 6)) { + panel_cfg.panel_type = ACTIVE_DISPLAY; + return 0; /* Avoid sanity check below */ + } else if (!strncmp(setting, "passive", 7)) { + panel_cfg.panel_type = PASSIVE_DISPLAY; + return 0; /* Avoid sanity check below */ + } else if (!strncmp(setting, "display:", 8)) { + if (!strncmp(setting + 8, "dvi", 3)) { + lcd_def = DVI_CUSTOM; + return 0; /* Avoid sanity check below */ + } + } else { + printf("LCD: unknown option %s\n", setting_start); + return -1; + } + + if (setting[0] != '\0') { + printf("LCD: invalid value for %s\n", setting_start); + return -1; + } + + return 0; +} + +/* + * env_parse_customlcd() - parse custom lcd params from an environment variable. + * + * @custom_lcd_params: The environment variable containing the lcd params. + * + * Returns -1 on failure, 0 on success. + */ +static int parse_customlcd(char *custom_lcd_params) +{ + char params_cpy[160]; + char *setting; + + strncpy(params_cpy, custom_lcd_params, 160); + setting = strtok(params_cpy, ","); + while (setting) { + if (parse_setting(setting) < 0) + return -1; + + setting = strtok(NULL, ","); + } + + /* Currently we don't support changing this via custom lcd params */ + panel_cfg.data_lines = LCD_INTERFACE_24_BIT; + panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */ + + return 0; +} + +/* * env_parse_displaytype() - parse display type. * * Parses the environment variable "displaytype", which contains the @@ -189,14 +392,19 @@ void *lcd_console_address; void lcd_ctrl_init(void *lcdbase) { struct prcm *prcm = (struct prcm *)PRCM_BASE; + char *custom_lcd; char *displaytype = getenv("displaytype"); if (displaytype == NULL) return; lcd_def = env_parse_displaytype(displaytype); - if (lcd_def == NONE) - return; + /* If we did not recognize the preset, check if it's an env variable */ + if (lcd_def == NONE) { + custom_lcd = getenv(displaytype); + if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0) + return; + } panel_cfg.frame_buffer = lcdbase; omap3_dss_panel_config(&panel_cfg); @@ -211,7 +419,7 @@ void lcd_ctrl_init(void *lcdbase) void lcd_enable(void) { - if (lcd_def == DVI) { + if (lcd_def == DVI || lcd_def == DVI_CUSTOM) { gpio_direction_output(54, 0); /* Turn on DVI */ omap3_dss_enable(); } -- cgit v0.10.2 From 66c7f399239e6c0ff5db1ea87c3c2a9a8ae613a1 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 7 Feb 2013 23:14:46 +0000 Subject: SPL: ONENAND: Fix some ONENAND related defines. Some ONENAND related defines use the term ONE_NAND instead of ONENAND, as the technology name is ONENAND this patch replaces all these defines. Signed-off-by: Enric Balletbo i Serra diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index d11e6f6..46f4b64 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -519,7 +519,7 @@ u32 spl_boot_device(void) case RCSR_MEM_TYPE_NOR: return BOOT_DEVICE_NOR; case RCSR_MEM_TYPE_ONENAND: - return BOOT_DEVICE_ONE_NAND; + return BOOT_DEVICE_ONENAND; default: return BOOT_DEVICE_NONE; } diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h index 91d11ae..3ca4c94 100644 --- a/arch/arm/include/asm/arch-mx35/spl.h +++ b/arch/arm/include/asm/arch-mx35/spl.h @@ -27,7 +27,7 @@ #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 #define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_ONENAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h index 404e16a..dec4dac 100644 --- a/arch/arm/include/asm/arch-omap3/spl.h +++ b/arch/arm/include/asm/arch-omap3/spl.h @@ -26,7 +26,7 @@ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_NAND 2 -#define BOOT_DEVICE_ONE_NAND 3 +#define BOOT_DEVICE_ONENAND 3 #define BOOT_DEVICE_MMC2 5 /*emmc*/ #define BOOT_DEVICE_MMC1 6 #define BOOT_DEVICE_XIPWAIT 7 diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h index cec84dc..4e094f9 100644 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -27,7 +27,7 @@ #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 #define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_ONENAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 0xFF diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index d125c61..323cd63 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -27,7 +27,7 @@ #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 #define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_ONENAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 -- cgit v0.10.2 From f99613782a41dbf1b91c19684fe9556ed02ec6d1 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 7 Feb 2013 23:14:47 +0000 Subject: SPL: ONENAND: Fix onenand_spl_load_image implementation. Tested with an IGEPv2 board seems that current onenand_spl_load_image implementation doesn't work. This patch fixes this function changing the read loop and reading the onenand blocks from page to page. Tested with various IGEP based boards with a OneNAND from Numonyx. Signed-off-by: Enric Balletbo i Serra diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c index 50eaa71..4bec2c2 100644 --- a/drivers/mtd/onenand/onenand_spl.c +++ b/drivers/mtd/onenand/onenand_spl.c @@ -112,7 +112,7 @@ static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf, void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst) { uint32_t *addr = (uint32_t *)dst; - uint32_t total_pages; + uint32_t to_page; uint32_t block; uint32_t page, rpage; enum onenand_spl_pagesize pagesize; @@ -125,22 +125,20 @@ void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst) * pulling further unwanted functions into the SPL. */ if (pagesize == 2048) { - total_pages = DIV_ROUND_UP(size, 2048); page = offs / 2048; + to_page = page + DIV_ROUND_UP(size, 2048); } else { - total_pages = DIV_ROUND_UP(size, 4096); page = offs / 4096; + to_page = page + DIV_ROUND_UP(size, 4096); } - for (; page <= total_pages; page++) { + for (; page <= to_page; page++) { block = page / ONENAND_PAGES_PER_BLOCK; rpage = page & (ONENAND_PAGES_PER_BLOCK - 1); ret = onenand_spl_read_page(block, rpage, addr, pagesize); - if (ret) { - total_pages += ONENAND_PAGES_PER_BLOCK; + if (ret) page += ONENAND_PAGES_PER_BLOCK - 1; - } else { + else addr += pagesize / 4; - } } } -- cgit v0.10.2 From 6000992e265f507a18b0dcbcf2a89179822b42c4 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 7 Feb 2013 23:14:48 +0000 Subject: SPL: ONENAND: Support SPL to boot u-boot from OneNAND. This patch will allow use SPL to boot an u-boot from the OneNAND. Tested with IGEPv2 board with a OneNAND from Numonyx Signed-off-by: Enric Balletbo i Serra [trini: Add hunk to fix warning] Signed-off-by: Tom Rini diff --git a/common/spl/Makefile b/common/spl/Makefile index 5698a23..da2afc1 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -18,6 +18,7 @@ COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o COBJS-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o +COBJS-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o COBJS-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o endif diff --git a/common/spl/spl.c b/common/spl/spl.c index 6a5a136..6715e0d 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -197,6 +197,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) spl_nand_load_image(); break; #endif +#ifdef CONFIG_SPL_ONENAND_SUPPORT + case BOOT_DEVICE_ONENAND: + spl_onenand_load_image(); + break; +#endif #ifdef CONFIG_SPL_NOR_SUPPORT case BOOT_DEVICE_NOR: spl_nor_load_image(); diff --git a/common/spl/spl_onenand.c b/common/spl/spl_onenand.c new file mode 100644 index 0000000..4349303 --- /dev/null +++ b/common/spl/spl_onenand.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2013 + * ISEE 2007 SL - Enric Balletbo i Serra + * + * Based on common/spl/spl_nand.c + * Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include + +void spl_onenand_load_image(void) +{ + struct image_header *header; + + debug("spl: onenand\n"); + + /*use CONFIG_SYS_TEXT_BASE as temporary storage area */ + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); + /* Load u-boot */ + onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS, + CONFIG_SYS_ONENAND_PAGE_SIZE, (void *)header); + spl_parse_image_header(header); + onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS, + spl_image.size, (void *)spl_image.load_addr); +} diff --git a/include/spl.h b/include/spl.h index b02f36f..b40be80 100644 --- a/include/spl.h +++ b/include/spl.h @@ -59,6 +59,9 @@ void spl_display_print(void); /* NAND SPL functions */ void spl_nand_load_image(void); +/* OneNAND SPL functions */ +void spl_onenand_load_image(void); + /* NOR SPL functions */ void spl_nor_load_image(void); -- cgit v0.10.2 From b51a5e3a0a8f412e221165f92991bb59a5cad111 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 7 Feb 2013 23:14:49 +0000 Subject: OMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled. In order to use SPL boot from OneNAND we should initialize the gpmc. Signed-off-by: Enric Balletbo i Serra diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 23ccc59..c6d9a42 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -110,7 +110,7 @@ int board_mmc_init(bd_t *bis) void spl_board_init(void) { -#ifdef CONFIG_SPL_NAND_SUPPORT +#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) gpmc_init(); #endif #ifdef CONFIG_SPL_I2C_SUPPORT -- cgit v0.10.2 From 6b3dcc45c4af4cb927c5c2430884e506c95faa71 Mon Sep 17 00:00:00 2001 From: Mark Jackson Date: Mon, 18 Feb 2013 01:26:29 +0000 Subject: Allow AM33xx boards to setup GPMC chipselects. Expose the enable_gpmc_cs_config() function so AM33xx based boards can register GPMC chip selects. Changes in V4: - Fix checkpatch errors (TAB -> space mangling) Changes in V3: - Fix line wrapping Changes in V2: - Indicate this is for AM33xx (not OMAP2) Signed-off-by: Mark Jackson Acked-by: Peter Korsgaard diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 588d8de..97ab60d 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -35,5 +35,7 @@ void ddr_pll_config(unsigned int ddrpll_M); void sdelay(unsigned long); void gpmc_init(void); +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size); void omap_nand_switch_ecc(int); #endif -- cgit v0.10.2 From d446c9038396abec9d68cfda76924c3c3e260851 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 Feb 2013 11:18:15 +0000 Subject: am335x_evm: Enable CONFIG_CMD_BOOTZ With v3.9 and later of the Linux Kernel defaulting to multi-platform images with omap2plus_defconfig, uImage isn't builtable anymore by default. Add CONFIG_CMD_BOOTZ so that we can still boot something the kernel spits out. Signed-off-by: Tom Rini Acked-by: Peter Korsgaard diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 35a71ca..709c1f3 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -35,6 +35,7 @@ #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM #define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -- cgit v0.10.2 From fe8f1372cdf7b45becc01e5b1dbe09af4929fd95 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 Feb 2013 11:18:16 +0000 Subject: omap5_evm: Enable CONFIG_CMD_BOOTZ With v3.9 and later of the Linux Kernel defaulting to multi-platform images with omap2plus_defconfig, uImage isn't builtable anymore by default. Add CONFIG_CMD_BOOTZ so that we can still boot something the kernel spits out. Cc: Sricharan R Signed-off-by: Tom Rini Reviewed-by: R Sricharan diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 623da77..85ea88b 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -55,6 +55,7 @@ #define CONFIG_MISC_INIT_R #define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS -- cgit v0.10.2 From 03a2075a2154daf8fa0a058ee4b2b4fca89b631f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 Feb 2013 11:18:17 +0000 Subject: omap3_beagle: Enable CONFIG_CMD_BOOTZ With v3.9 and later of the Linux Kernel defaulting to multi-platform images with omap2plus_defconfig, uImage isn't builtable anymore by default. Add CONFIG_CMD_BOOTZ so that we can still boot something the kernel spits out. Signed-off-by: Tom Rini diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 59255c4..48ce4c0 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -53,7 +53,8 @@ #define CONFIG_MISC_INIT_R -#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 -- cgit v0.10.2 From f0617d4b52fef0d539e7d08045f30237fdf141f7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 Feb 2013 11:18:18 +0000 Subject: omap4_common: Enable CONFIG_CMD_BOOTZ With v3.9 and later of the Linux Kernel defaulting to multi-platform images with omap2plus_defconfig, uImage isn't builtable anymore by default. Add CONFIG_CMD_BOOTZ so that we can still boot something the kernel spits out. Cc: Sricharan R Signed-off-by: Tom Rini Reviewed-by: R Sricharan diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 180cb24..6ae6a0f 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -52,7 +52,7 @@ #define CONFIG_MISC_INIT_R #define CONFIG_OF_LIBFDT 1 - +#define CONFIG_CMD_BOOTZ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 -- cgit v0.10.2 From 48ec52910047e048a5857fdaf00679b85a952ec5 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Tue, 19 Feb 2013 21:34:44 +0000 Subject: am335x: cpsw: optimize cpsw_send to increase network performance Before submitting packets to cpdma, phy status is updated on every packet which leads to delay in packet send intern reduces the Ethernet performance. Checking mdio status for each packet will reduce timetaken to send a packet and there by increasing the Ethernet performance. With this the performance is increased from 208KiB/s to 375KiB/s on EVMsk Signed-off-by: Mugunthan V N diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index db04795..93f8417 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -227,6 +227,9 @@ struct cpsw_priv { struct cpsw_slave *slaves; struct phy_device *phydev; struct mii_dev *bus; + + u32 mdio_link; + u32 phy_mask; }; static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) @@ -598,10 +601,21 @@ static int cpsw_update_link(struct cpsw_priv *priv) for_each_slave(slave, priv) cpsw_slave_update_link(slave, priv, &link); - + priv->mdio_link = readl(&mdio_regs->link); return link; } +static int cpsw_check_link(struct cpsw_priv *priv) +{ + u32 link = 0; + + link = __raw_readl(&mdio_regs->link) & priv->phy_mask; + if ((link) && (link == priv->mdio_link)) + return 1; + + return cpsw_update_link(priv); +} + static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) { if (priv->host_port == 0) @@ -631,6 +645,8 @@ static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD); cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port); + + priv->phy_mask |= 1 << slave->data->phy_id; } static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) @@ -862,7 +878,7 @@ static int cpsw_send(struct eth_device *dev, void *packet, int length) int len; int timeout = CPDMA_TIMEOUT; - if (!cpsw_update_link(priv)) + if (!cpsw_check_link(priv)) return -EIO; flush_dcache_range((unsigned long)packet, -- cgit v0.10.2 From c08804853361bb7c6e2f9e0cdcdc0b327f71fe35 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Sun, 24 Feb 2013 21:28:43 +0000 Subject: lcd: implement a callback for splashimage On some architectures certain values of splashimage will lead to a data abort exception. Document the problem, and implement a callback for splashimage to reject such values. Cc: Anatolij Gustschin Cc: Wolfgang Denk Signed-off-by: Nikita Kiryanov Acked-by: Igor Grinberg diff --git a/README b/README index b8ed1f1..398d70d 100644 --- a/README +++ b/README @@ -1530,6 +1530,17 @@ CBFS (Coreboot Filesystem) support allows for a "silent" boot where a splash screen is loaded very quickly after power-on. + CONFIG_SPLASHIMAGE_GUARD + + If this option is set, then U-Boot will prevent the environment + variable "splashimage" from being set to a problematic address + (see README.displaying-bmps and README.arm-unaligned-accesses). + This option is useful for targets where, due to alignment + restrictions, an improperly aligned BMP image will cause a data + abort. If you think you will not have problems with unaligned + accesses (for example because your toolchain prevents them) + there is no need to set this option. + CONFIG_SPLASH_SCREEN_ALIGN If this option is set the splash image can be freely positioned diff --git a/common/lcd.c b/common/lcd.c index ba6975b..590bbb9 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include #include #include #if defined(CONFIG_POST) @@ -1099,6 +1101,30 @@ static void *lcd_logo(void) #endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */ } +#ifdef CONFIG_SPLASHIMAGE_GUARD +static int on_splashimage(const char *name, const char *value, enum env_op op, + int flags) +{ + ulong addr; + int aligned; + + if (op == env_op_delete) + return 0; + + addr = simple_strtoul(value, NULL, 16); + /* See README.displaying-bmps */ + aligned = (addr % 4 == 2); + if (!aligned) { + printf("Invalid splashimage value. Value must be 16 bit aligned, but not 32 bit aligned\n"); + return -1; + } + + return 0; +} + +U_BOOT_ENV_CALLBACK(splashimage, on_splashimage); +#endif + void lcd_position_cursor(unsigned col, unsigned row) { console_col = min(col, CONSOLE_COLS - 1); diff --git a/doc/README.displaying-bmps b/doc/README.displaying-bmps new file mode 100644 index 0000000..3311541 --- /dev/null +++ b/doc/README.displaying-bmps @@ -0,0 +1,27 @@ +If you are experiencing hangups/data-aborts when trying to display a BMP image, +the following might be relevant to your situation... + +Some architectures cannot handle unaligned memory accesses, and an attempt to +perform one will lead to a data abort. On such architectures it is necessary to +make sure all data is properly aligned, and in many situations simply choosing +a 32 bit aligned address is enough to ensure proper alignment. This is not +always the case when dealing with data that has an internal layout such as a +BMP image: + +BMP images have a header that starts with 2 byte-size fields followed by mostly +32 bit fields. The packed struct that represents this header can be seen below: + +typedef struct bmp_header { + /* Header */ + char signature[2]; + __u32 file_size; + __u32 reserved; + __u32 data_offset; + ... etc +} __attribute__ ((packed)) bmp_header_t; + +When placed in an aligned address such as 0x80a00000, char signature offsets +the __u32 fields into unaligned addresses (in our example 0x80a00002, +0x80a00006, and so on...). When these fields are accessed by U-Boot, a 32 bit +access is generated at a non-32-bit-aligned address, causing a data abort. +The proper alignment for BMP images is therefore: 32-bit-aligned-address + 2. diff --git a/include/env_callback.h b/include/env_callback.h index c583120..62428d1 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -41,6 +41,12 @@ #define SILENT_CALLBACK #endif +#ifdef CONFIG_SPLASHIMAGE_GUARD +#define SPLASHIMAGE_CALLBACK "splashimage:splashimage," +#else +#define SPLASHIMAGE_CALLBACK +#endif + /* * This list of callback bindings is static, but may be overridden by defining * a new association in the ".callbacks" environment variable. @@ -51,6 +57,7 @@ "bootfile:bootfile," \ "loadaddr:loadaddr," \ SILENT_CALLBACK \ + SPLASHIMAGE_CALLBACK \ "stdin:console,stdout:console,stderr:console," \ CONFIG_ENV_CALLBACK_LIST_STATIC -- cgit v0.10.2 From 60e6bdcc948f99e6b24d198c1b9136b0cb4e376b Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Sun, 24 Feb 2013 06:19:23 +0000 Subject: cm_t35: prevent splashimage from being set to a bad value Define CONFIG_SPLASHIMAGE_GUARD to prevent splashimage from being set to a value that will cause U-Boot to hang while displaying a splash screen. Signed-off-by: Nikita Kiryanov Acked-by: Igor Grinberg diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index e6aef7b..8d79ffd 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -331,6 +331,8 @@ #define STATUS_LED_BOOT STATUS_LED_BIT #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ +#define CONFIG_SPLASHIMAGE_GUARD + /* GPIO banks */ #ifdef CONFIG_STATUS_LED #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ -- cgit v0.10.2 From 9ca8bfea80f38e3b423e339499c861ddc24b830c Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 4 Feb 2013 04:21:59 +0000 Subject: ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register Now SDRAM initialization is done on the basis of omap revision. Instead this should be done on basis of SDRAM type read from EMIF_SDRAM_CONFIG register. This will be helpful to avoid unnessecary cpu checks for new boards Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index b1fd277..1f95fba 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -36,6 +36,7 @@ #include #include #include +#include #ifndef CONFIG_SPL_BUILD /* @@ -299,7 +300,7 @@ static void setup_dplls(void) * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ - if (omap_revision() != OMAP5432_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, "core"); else diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 88253cf..8864abc 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -66,6 +66,19 @@ inline u32 emif_num(u32 base) return 0; } +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +u32 emif_sdram_type() +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + return (readl(&emif->emif_sdram_config) & + EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; +} static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) { @@ -1079,7 +1092,7 @@ static void do_sdram_init(u32 base) * OPP to another) */ if (!(in_sdram || warm_reset())) { - if (omap_revision() != OMAP5432_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) lpddr2_init(base, regs); else ddr3_init(base, regs); @@ -1264,7 +1277,7 @@ void dmm_init(u32 base) void sdram_init(void) { u32 in_sdram, size_prog, size_detect; - u32 omap_rev = omap_revision(); + u32 sdram_type = emif_sdram_type(); debug(">>sdram_init()\n"); @@ -1275,7 +1288,7 @@ void sdram_init(void) debug("in_sdram = %d\n", in_sdram); if (!(in_sdram || warm_reset())) { - if (omap_rev != OMAP5432_ES1_0) + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) bypass_dpll(&prcm->cm_clkmode_dpll_core); else writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); @@ -1298,7 +1311,7 @@ void sdram_init(void) } /* for the shadow registers to take effect */ - if (omap_rev != OMAP5432_ES1_0) + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) freq_update_core(); /* Do some testing after the init */ diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index eecfbad..1f33692 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -36,6 +36,7 @@ #include #include #include +#include #ifndef CONFIG_SPL_BUILD /* @@ -279,7 +280,7 @@ void scale_vcores(void) do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu); do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm); - if (omap_revision() == OMAP5432_ES1_0) { + if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { /* Configure LDO SRAM "magic" bits */ writel(2, &prcm->prm_sldo_core_setup); writel(2, &prcm->prm_sldo_mpu_setup); diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index d0c3ff7..4def422 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -191,7 +191,7 @@ void do_io_settings(void) (sc_fast << 17) | (sc_fast << 14); writel(io_settings, &(ioregs_base->control_smart3io_padconf_1)); - if (omap_revision() <= OMAP5430_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) io_settings_lpddr2(); else io_settings_ddr3(); diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index ed251ec..0824a80 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1027,6 +1027,11 @@ extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; #define MR8_IO_WIDTH_SHIFT 0x6 #define MR8_IO_WIDTH_MASK (0x3 << 0x6) +/* SDRAM TYPE */ +#define EMIF_SDRAM_TYPE_DDR2 0x2 +#define EMIF_SDRAM_TYPE_DDR3 0x3 +#define EMIF_SDRAM_TYPE_LPDDR2 0x4 + struct lpddr2_addressing { u8 num_banks; u8 t_REFI_us_x10; @@ -1156,4 +1161,5 @@ extern u32 *const emif_sizes; #endif void config_data_eye_leveling_samples(u32 emif_base); +u32 emif_sdram_type(void); #endif -- cgit v0.10.2 From 01b753ff7badb5b8670794de3d5dd71e1c4c9baf Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Mon, 4 Feb 2013 04:22:00 +0000 Subject: ARM: OMAP4+: Change the PRCM structure prototype common for all Socs The current PRCM structure prototype directly matches the hardware register layout. So there is a need to change this for every new silicon revision which has register space changes. Avoiding this by making the prototye generic and populating the register addresses seperately for all Socs. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 1f95fba..d36fccc 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -61,7 +61,7 @@ static inline u32 __get_sys_clk_index(void) ind = OMAP_SYS_CLK_IND_38_4_MHZ; else { /* SYS_CLKSEL - 1 to match the dpll param array indices */ - ind = (readl(&prcm->cm_sys_clksel) & + ind = (readl((*prcm)->cm_sys_clksel) & CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; } return ind; @@ -76,7 +76,7 @@ u32 get_sys_clk_freq(void) return sys_clk_array[index]; } -static inline void do_bypass_dpll(u32 *const base) +static inline void do_bypass_dpll(u32 const base) { struct dpll_regs *dpll_regs = (struct dpll_regs *)base; @@ -86,17 +86,17 @@ static inline void do_bypass_dpll(u32 *const base) CM_CLKMODE_DPLL_EN_SHIFT); } -static inline void wait_for_bypass(u32 *const base) +static inline void wait_for_bypass(u32 const base) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, LDELAY)) { - printf("Bypassing DPLL failed %p\n", base); + printf("Bypassing DPLL failed %x\n", base); } } -static inline void do_lock_dpll(u32 *const base) +static inline void do_lock_dpll(u32 const base) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; @@ -105,18 +105,18 @@ static inline void do_lock_dpll(u32 *const base) DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); } -static inline void wait_for_lock(u32 *const base) +static inline void wait_for_lock(u32 const base) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, &dpll_regs->cm_idlest_dpll, LDELAY)) { - printf("DPLL locking failed for %p\n", base); + printf("DPLL locking failed for %x\n", base); hang(); } } -inline u32 check_for_lock(u32 *const base) +inline u32 check_for_lock(u32 const base) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK; @@ -124,7 +124,7 @@ inline u32 check_for_lock(u32 *const base) return lock; } -static void do_setup_dpll(u32 *const base, const struct dpll_params *params, +static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { u32 temp, M, N; @@ -236,24 +236,24 @@ void configure_mpu_dpll(void) */ if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) { mpu_dpll_regs = - (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu; - bypass_dpll(&prcm->cm_clkmode_dpll_mpu); - clrbits_le32(&prcm->cm_mpu_mpu_clkctrl, + (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu); + bypass_dpll((*prcm)->cm_clkmode_dpll_mpu); + clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); - setbits_le32(&prcm->cm_mpu_mpu_clkctrl, + setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, CM_CLKSEL_DCC_EN_MASK); } - setbits_le32(&prcm->cm_mpu_mpu_clkctrl, + setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); - setbits_le32(&prcm->cm_mpu_mpu_clkctrl, + setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); params = get_mpu_dpll_params(); - do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); + do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); debug("MPU DPLL locked\n"); } @@ -277,12 +277,12 @@ static void setup_usb_dpll(void) den = (params->n + 1) * 250 * 1000; num += den - 1; sd_div = num / den; - clrsetbits_le32(&prcm->cm_clksel_dpll_usb, + clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); /* Now setup the dpll with the regular function */ - do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); + do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); } #endif @@ -301,21 +301,21 @@ static void setup_dplls(void) * using the FREQ_UPDATE method(freq_update_core()) */ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) - do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, + do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, "core"); else - do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, + do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, DPLL_LOCK, "core"); /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); - writel(temp, &prcm->cm_clksel_core); + writel(temp, (*prcm)->cm_clksel_core); debug("Core DPLL configured\n"); /* lock PER dpll */ params = get_per_dpll_params(); - do_setup_dpll(&prcm->cm_clkmode_dpll_per, + do_setup_dpll((*prcm)->cm_clkmode_dpll_per, params, DPLL_LOCK, "per"); debug("PER DPLL locked\n"); @@ -334,11 +334,11 @@ static void setup_non_essential_dplls(void) const struct dpll_params *params; /* IVA */ - clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, + clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva, CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); params = get_iva_dpll_params(); - do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); + do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); /* Configure ABE dpll */ params = get_abe_dpll_params(); @@ -350,23 +350,23 @@ static void setup_non_essential_dplls(void) * We need to enable some additional options to achieve * 196.608MHz from 32768 Hz */ - setbits_le32(&prcm->cm_clkmode_dpll_abe, + setbits_le32((*prcm)->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| CM_CLKMODE_DPLL_LPMODE_EN_MASK| CM_CLKMODE_DPLL_REGM4XEN_MASK); /* Spend 4 REFCLK cycles at each stage */ - clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, + clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_RAMP_RATE_MASK, 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); #endif /* Select the right reference clk */ - clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, + clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel, CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); /* Lock the dpll */ - do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); + do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); } #endif @@ -417,14 +417,14 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv) printf("Scaling voltage failed for 0x%x\n", vcore_reg); } -static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) +static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) { clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); - debug("Enable clock domain - %p\n", clkctrl_reg); + debug("Enable clock domain - %x\n", clkctrl_reg); } -static inline void wait_for_clk_enable(u32 *clkctrl_addr) +static inline void wait_for_clk_enable(u32 clkctrl_addr) { u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; u32 bound = LDELAY; @@ -436,19 +436,19 @@ static inline void wait_for_clk_enable(u32 *clkctrl_addr) idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> MODULE_CLKCTRL_IDLEST_SHIFT; if (--bound == 0) { - printf("Clock enable failed for 0x%p idlest 0x%x\n", + printf("Clock enable failed for 0x%x idlest 0x%x\n", clkctrl_addr, clkctrl); return; } } } -static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, +static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode, u32 wait_for_enable) { clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); - debug("Enable clock module - %p\n", clkctrl_addr); + debug("Enable clock module - %x\n", clkctrl_addr); if (wait_for_enable) wait_for_clk_enable(clkctrl_addr); } @@ -461,10 +461,10 @@ void freq_update_core(void) core_dpll_params = get_core_dpll_params(); /* Put EMIF clock domain in sw wakeup mode */ - enable_clock_domain(&prcm->cm_memif_clkstctrl, + enable_clock_domain((*prcm)->cm_memif_clkstctrl, CD_CLKCTRL_CLKTRCTRL_SW_WKUP); - wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); - wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); + wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; @@ -476,9 +476,9 @@ void freq_update_core(void) SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & SHADOW_FREQ_CONFIG1_M2_DIV_MASK; - writel(freq_config1, &prcm->cm_shadow_freq_config1); + writel(freq_config1, (*prcm)->cm_shadow_freq_config1); if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, - &prcm->cm_shadow_freq_config1, LDELAY)) { + (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) { puts("FREQ UPDATE procedure failed!!"); hang(); } @@ -490,20 +490,20 @@ void freq_update_core(void) */ if (omap_rev != OMAP5430_ES1_0) { /* Put EMIF clock domain back in hw auto mode */ - enable_clock_domain(&prcm->cm_memif_clkstctrl, + enable_clock_domain((*prcm)->cm_memif_clkstctrl, CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); - wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); + wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); } } -void bypass_dpll(u32 *const base) +void bypass_dpll(u32 const base) { do_bypass_dpll(base); wait_for_bypass(base); } -void lock_dpll(u32 *const base) +void lock_dpll(u32 const base) { do_lock_dpll(base); wait_for_lock(base); @@ -512,39 +512,39 @@ void lock_dpll(u32 *const base) void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ - clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, CD_CLKCTRL_CLKTRCTRL_SW_WKUP << CD_CLKCTRL_CLKTRCTRL_SHIFT); /* Enable all UARTs - console will be on one of them */ - clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl, + clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl, MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl, + clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl, MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, + clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, + clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, CD_CLKCTRL_CLKTRCTRL_HW_AUTO << CD_CLKCTRL_CLKTRCTRL_SHIFT); } -void do_enable_clocks(u32 *const *clk_domains, - u32 *const *clk_modules_hw_auto, - u32 *const *clk_modules_explicit_en, +void do_enable_clocks(u32 const *clk_domains, + u32 const *clk_modules_hw_auto, + u32 const *clk_modules_explicit_en, u8 wait_for_enable) { u32 i, max = 100; diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 8864abc..bb37cf3 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1289,9 +1289,9 @@ void sdram_init(void) if (!(in_sdram || warm_reset())) { if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) - bypass_dpll(&prcm->cm_clkmode_dpll_core); + bypass_dpll((*prcm)->cm_clkmode_dpll_core); else - writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); + writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); } if (!in_sdram) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 9ef10bd..fff89da 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -32,6 +32,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -116,6 +117,8 @@ void spl_display_print(void) void s_init(void) { init_omap_revision(); + hw_data_init(); + #ifdef CONFIG_SPL_BUILD if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0)) force_emif_self_refresh(); diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c index a045b77..e6e5f78 100644 --- a/arch/arm/cpu/armv7/omap-common/vc.c +++ b/arch/arm/cpu/armv7/omap-common/vc.c @@ -81,13 +81,13 @@ void omap_vc_init(u16 speed_khz) cycles_low -= 7; val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); - writel(val, &prcm->prm_vc_cfg_i2c_clk); + writel(val, (*prcm)->prm_vc_cfg_i2c_clk); val = CONFIG_OMAP_VC_I2C_HS_MCODE << PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT; /* No HS mode for now */ val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT; - writel(val, &prcm->prm_vc_cfg_i2c_mode); + writel(val, (*prcm)->prm_vc_cfg_i2c_mode); } /** @@ -113,14 +113,15 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT | reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT | reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT; - writel(reg_val, &prcm->prm_vc_val_bypass); + writel(reg_val, (*prcm)->prm_vc_val_bypass); /* Signal VC to send data */ - writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, &prcm->prm_vc_val_bypass); + writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, + (*prcm)->prm_vc_val_bypass); /* Wait on VC to complete transmission */ do { - reg_val = readl(&prcm->prm_vc_val_bypass) & + reg_val = readl((*prcm)->prm_vc_val_bypass) & PRM_VC_VAL_BYPASS_VALID_BIT; if (!reg_val) break; diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index 83160a2..0365148 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -29,6 +29,8 @@ COBJS += sdram_elpida.o COBJS += hwinit.o COBJS += clocks.o COBJS += emif.o +COBJS += prcm-regs.o +COBJS += hw_data.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 12c5803..9acceb0 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -46,8 +46,6 @@ #define puts(s) #endif /* !CONFIG_SPL_BUILD */ -struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; - const u32 sys_clk_array[8] = { 12000000, /* 12 MHz */ 13000000, /* 13 MHz */ @@ -176,7 +174,7 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -void setup_post_dividers(u32 *const base, const struct dpll_params *params) +void setup_post_dividers(u32 const base, const struct dpll_params *params) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; @@ -345,54 +343,54 @@ u32 get_offset_code(u32 offset) */ void enable_basic_clocks(void) { - u32 *const clk_domains_essential[] = { - &prcm->cm_l4per_clkstctrl, - &prcm->cm_l3init_clkstctrl, - &prcm->cm_memif_clkstctrl, - &prcm->cm_l4cfg_clkstctrl, + u32 const clk_domains_essential[] = { + (*prcm)->cm_l4per_clkstctrl, + (*prcm)->cm_l3init_clkstctrl, + (*prcm)->cm_memif_clkstctrl, + (*prcm)->cm_l4cfg_clkstctrl, 0 }; - u32 *const clk_modules_hw_auto_essential[] = { - &prcm->cm_l3_2_gpmc_clkctrl, - &prcm->cm_memif_emif_1_clkctrl, - &prcm->cm_memif_emif_2_clkctrl, - &prcm->cm_l4cfg_l4_cfg_clkctrl, - &prcm->cm_wkup_gpio1_clkctrl, - &prcm->cm_l4per_gpio2_clkctrl, - &prcm->cm_l4per_gpio3_clkctrl, - &prcm->cm_l4per_gpio4_clkctrl, - &prcm->cm_l4per_gpio5_clkctrl, - &prcm->cm_l4per_gpio6_clkctrl, + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3_2_gpmc_clkctrl, + (*prcm)->cm_memif_emif_1_clkctrl, + (*prcm)->cm_memif_emif_2_clkctrl, + (*prcm)->cm_l4cfg_l4_cfg_clkctrl, + (*prcm)->cm_wkup_gpio1_clkctrl, + (*prcm)->cm_l4per_gpio2_clkctrl, + (*prcm)->cm_l4per_gpio3_clkctrl, + (*prcm)->cm_l4per_gpio4_clkctrl, + (*prcm)->cm_l4per_gpio5_clkctrl, + (*prcm)->cm_l4per_gpio6_clkctrl, 0 }; - u32 *const clk_modules_explicit_en_essential[] = { - &prcm->cm_wkup_gptimer1_clkctrl, - &prcm->cm_l3init_hsmmc1_clkctrl, - &prcm->cm_l3init_hsmmc2_clkctrl, - &prcm->cm_l4per_gptimer2_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_l4per_uart3_clkctrl, + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_wkup_gptimer1_clkctrl, + (*prcm)->cm_l3init_hsmmc1_clkctrl, + (*prcm)->cm_l3init_hsmmc2_clkctrl, + (*prcm)->cm_l4per_gptimer2_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart3_clkctrl, 0 }; /* Enable optional additional functional clock for GPIO4 */ - setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, + setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, GPIO4_CLKCTRL_OPTFCLKEN_MASK); /* Enable 96 MHz clock for MMC1 & MMC2 */ - setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); - setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); /* Select 32KHz clock as the source of GPTIMER1 */ - setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, + setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, GPTIMER1_CLKCTRL_CLKSEL_MASK); /* Enable optional 48M functional clock for USB PHY */ - setbits_le32(&prcm->cm_l3init_usbphy_clkctrl, + setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); do_enable_clocks(clk_domains_essential, @@ -403,26 +401,26 @@ void enable_basic_clocks(void) void enable_basic_uboot_clocks(void) { - u32 *const clk_domains_essential[] = { + u32 const clk_domains_essential[] = { 0 }; - u32 *const clk_modules_hw_auto_essential[] = { - &prcm->cm_l3init_hsusbotg_clkctrl, - &prcm->cm_l3init_usbphy_clkctrl, - &prcm->cm_l3init_usbphy_clkctrl, - &prcm->cm_clksel_usb_60mhz, - &prcm->cm_l3init_hsusbtll_clkctrl, + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3init_hsusbotg_clkctrl, + (*prcm)->cm_l3init_usbphy_clkctrl, + (*prcm)->cm_l3init_usbphy_clkctrl, + (*prcm)->cm_clksel_usb_60mhz, + (*prcm)->cm_l3init_hsusbtll_clkctrl, 0 }; - u32 *const clk_modules_explicit_en_essential[] = { - &prcm->cm_l4per_mcspi1_clkctrl, - &prcm->cm_l4per_i2c1_clkctrl, - &prcm->cm_l4per_i2c2_clkctrl, - &prcm->cm_l4per_i2c3_clkctrl, - &prcm->cm_l4per_i2c4_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_l4per_mcspi1_clkctrl, + (*prcm)->cm_l4per_i2c1_clkctrl, + (*prcm)->cm_l4per_i2c2_clkctrl, + (*prcm)->cm_l4per_i2c3_clkctrl, + (*prcm)->cm_l4per_i2c4_clkctrl, + (*prcm)->cm_l3init_hsusbhost_clkctrl, 0 }; @@ -438,72 +436,72 @@ void enable_basic_uboot_clocks(void) */ void enable_non_essential_clocks(void) { - u32 *const clk_domains_non_essential[] = { - &prcm->cm_mpu_m3_clkstctrl, - &prcm->cm_ivahd_clkstctrl, - &prcm->cm_dsp_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sgx_clkstctrl, - &prcm->cm1_abe_clkstctrl, - &prcm->cm_c2c_clkstctrl, - &prcm->cm_cam_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sdma_clkstctrl, + u32 const clk_domains_non_essential[] = { + (*prcm)->cm_mpu_m3_clkstctrl, + (*prcm)->cm_ivahd_clkstctrl, + (*prcm)->cm_dsp_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sgx_clkstctrl, + (*prcm)->cm1_abe_clkstctrl, + (*prcm)->cm_c2c_clkstctrl, + (*prcm)->cm_cam_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sdma_clkstctrl, 0 }; - u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_l3instr_l3_3_clkctrl, - &prcm->cm_l3instr_l3_instr_clkctrl, - &prcm->cm_l3instr_intrconn_wp1_clkctrl, - &prcm->cm_l3init_hsi_clkctrl, + u32 const clk_modules_hw_auto_non_essential[] = { + (*prcm)->cm_l3instr_l3_3_clkctrl, + (*prcm)->cm_l3instr_l3_instr_clkctrl, + (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, + (*prcm)->cm_l3init_hsi_clkctrl, 0 }; - u32 *const clk_modules_explicit_en_non_essential[] = { - &prcm->cm1_abe_aess_clkctrl, - &prcm->cm1_abe_pdm_clkctrl, - &prcm->cm1_abe_dmic_clkctrl, - &prcm->cm1_abe_mcasp_clkctrl, - &prcm->cm1_abe_mcbsp1_clkctrl, - &prcm->cm1_abe_mcbsp2_clkctrl, - &prcm->cm1_abe_mcbsp3_clkctrl, - &prcm->cm1_abe_slimbus_clkctrl, - &prcm->cm1_abe_timer5_clkctrl, - &prcm->cm1_abe_timer6_clkctrl, - &prcm->cm1_abe_timer7_clkctrl, - &prcm->cm1_abe_timer8_clkctrl, - &prcm->cm1_abe_wdt3_clkctrl, - &prcm->cm_l4per_gptimer9_clkctrl, - &prcm->cm_l4per_gptimer10_clkctrl, - &prcm->cm_l4per_gptimer11_clkctrl, - &prcm->cm_l4per_gptimer3_clkctrl, - &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, - &prcm->cm_l4per_mcbsp4_clkctrl, - &prcm->cm_l4per_mcspi2_clkctrl, - &prcm->cm_l4per_mcspi3_clkctrl, - &prcm->cm_l4per_mcspi4_clkctrl, - &prcm->cm_l4per_mmcsd3_clkctrl, - &prcm->cm_l4per_mmcsd4_clkctrl, - &prcm->cm_l4per_mmcsd5_clkctrl, - &prcm->cm_l4per_uart1_clkctrl, - &prcm->cm_l4per_uart2_clkctrl, - &prcm->cm_l4per_uart4_clkctrl, - &prcm->cm_wkup_keyboard_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_cam_iss_clkctrl, - &prcm->cm_cam_fdif_clkctrl, - &prcm->cm_dss_dss_clkctrl, - &prcm->cm_sgx_sgx_clkctrl, + u32 const clk_modules_explicit_en_non_essential[] = { + (*prcm)->cm1_abe_aess_clkctrl, + (*prcm)->cm1_abe_pdm_clkctrl, + (*prcm)->cm1_abe_dmic_clkctrl, + (*prcm)->cm1_abe_mcasp_clkctrl, + (*prcm)->cm1_abe_mcbsp1_clkctrl, + (*prcm)->cm1_abe_mcbsp2_clkctrl, + (*prcm)->cm1_abe_mcbsp3_clkctrl, + (*prcm)->cm1_abe_slimbus_clkctrl, + (*prcm)->cm1_abe_timer5_clkctrl, + (*prcm)->cm1_abe_timer6_clkctrl, + (*prcm)->cm1_abe_timer7_clkctrl, + (*prcm)->cm1_abe_timer8_clkctrl, + (*prcm)->cm1_abe_wdt3_clkctrl, + (*prcm)->cm_l4per_gptimer9_clkctrl, + (*prcm)->cm_l4per_gptimer10_clkctrl, + (*prcm)->cm_l4per_gptimer11_clkctrl, + (*prcm)->cm_l4per_gptimer3_clkctrl, + (*prcm)->cm_l4per_gptimer4_clkctrl, + (*prcm)->cm_l4per_hdq1w_clkctrl, + (*prcm)->cm_l4per_mcbsp4_clkctrl, + (*prcm)->cm_l4per_mcspi2_clkctrl, + (*prcm)->cm_l4per_mcspi3_clkctrl, + (*prcm)->cm_l4per_mcspi4_clkctrl, + (*prcm)->cm_l4per_mmcsd3_clkctrl, + (*prcm)->cm_l4per_mmcsd4_clkctrl, + (*prcm)->cm_l4per_mmcsd5_clkctrl, + (*prcm)->cm_l4per_uart1_clkctrl, + (*prcm)->cm_l4per_uart2_clkctrl, + (*prcm)->cm_l4per_uart4_clkctrl, + (*prcm)->cm_wkup_keyboard_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_cam_iss_clkctrl, + (*prcm)->cm_cam_fdif_clkctrl, + (*prcm)->cm_dss_dss_clkctrl, + (*prcm)->cm_sgx_sgx_clkctrl, 0 }; /* Enable optional functional clock for ISS */ - setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); + setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); /* Enable all optional functional clocks of DSS */ - setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); + setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); do_enable_clocks(clk_domains_non_essential, clk_modules_hw_auto_non_essential, @@ -511,7 +509,8 @@ void enable_non_essential_clocks(void) 0); /* Put camera module in no sleep mode */ - clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, + clrsetbits_le32((*prcm)->cm_cam_clkstctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << MODULE_CLKCTRL_MODULEMODE_SHIFT); } diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c new file mode 100644 index 0000000..3174cc3 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -0,0 +1,38 @@ +/* + * + * HW data initialization for OMAP4 + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include + +struct prcm_regs const **prcm = + (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; + +void hw_data_init(void) +{ + *prcm = &omap4_prcm; +} diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c new file mode 100644 index 0000000..815b9d2 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -0,0 +1,295 @@ +/* + * + * HW regs data for OMAP4 + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +struct prcm_regs const omap4_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_m4_dpll_core = 0x4a004138, + .cm_div_m5_dpll_core = 0x4a00413c, + .cm_div_m6_dpll_core = 0x4a004140, + .cm_div_m7_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_emu_override_dpll_core = 0x4a004150, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_m4_dpll_iva = 0x4a0041b8, + .cm_div_m5_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_m4_dpll_ddrphy = 0x4a004238, + .cm_div_m5_dpll_ddrphy = 0x4a00423c, + .cm_div_m6_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_m4_dpll_per = 0x4a008158, + .cm_div_m5_dpll_per = 0x4a00815c, + .cm_div_m6_dpll_per = 0x4a008160, + .cm_div_m7_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_2_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkct = 0x4a008e40, + .cm_ivahd_clkstctrl = 0x4a008f00, + + /* cm2.ivahd */ + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_iss_clkctrl = 0x4a009020, + .cm_cam_fdif_clkctrl = 0x4a009028, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsi_clkctrl = 0x4a009338, + .cm_l3init_hsusbhost_clkctrl = 0x4a009358, + .cm_l3init_hsusbotg_clkctrl = 0x4a009360, + .cm_l3init_hsusbtll_clkctrl = 0x4a009368, + .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_fsusb_clkctrl = 0x4a0093d0, + .cm_l3init_usbphy_clkctrl = 0x4a0093e0, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009400, + .cm_l4per_dynamicdep = 0x4a009408, + .cm_l4per_adc_clkctrl = 0x4a009420, + .cm_l4per_gptimer10_clkctrl = 0x4a009428, + .cm_l4per_gptimer11_clkctrl = 0x4a009430, + .cm_l4per_gptimer2_clkctrl = 0x4a009438, + .cm_l4per_gptimer3_clkctrl = 0x4a009440, + .cm_l4per_gptimer4_clkctrl = 0x4a009448, + .cm_l4per_gptimer9_clkctrl = 0x4a009450, + .cm_l4per_elm_clkctrl = 0x4a009458, + .cm_l4per_gpio2_clkctrl = 0x4a009460, + .cm_l4per_gpio3_clkctrl = 0x4a009468, + .cm_l4per_gpio4_clkctrl = 0x4a009470, + .cm_l4per_gpio5_clkctrl = 0x4a009478, + .cm_l4per_gpio6_clkctrl = 0x4a009480, + .cm_l4per_hdq1w_clkctrl = 0x4a009488, + .cm_l4per_hecc1_clkctrl = 0x4a009490, + .cm_l4per_hecc2_clkctrl = 0x4a009498, + .cm_l4per_i2c1_clkctrl = 0x4a0094a0, + .cm_l4per_i2c2_clkctrl = 0x4a0094a8, + .cm_l4per_i2c3_clkctrl = 0x4a0094b0, + .cm_l4per_i2c4_clkctrl = 0x4a0094b8, + .cm_l4per_l4per_clkctrl = 0x4a0094c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, + .cm_l4per_mcbsp4_clkctrl = 0x4a0094e0, + .cm_l4per_mgate_clkctrl = 0x4a0094e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009500, + .cm_l4per_mcspi4_clkctrl = 0x4a009508, + .cm_l4per_mmcsd3_clkctrl = 0x4a009520, + .cm_l4per_mmcsd4_clkctrl = 0x4a009528, + .cm_l4per_msprohg_clkctrl = 0x4a009530, + .cm_l4per_slimbus2_clkctrl = 0x4a009538, + .cm_l4per_uart1_clkctrl = 0x4a009540, + .cm_l4per_uart2_clkctrl = 0x4a009548, + .cm_l4per_uart3_clkctrl = 0x4a009550, + .cm_l4per_uart4_clkctrl = 0x4a009558, + .cm_l4per_mmcsd5_clkctrl = 0x4a009560, + .cm_l4per_i2c5_clkctrl = 0x4a009568, + .cm_l4sec_clkstctrl = 0x4a009580, + .cm_l4sec_staticdep = 0x4a009584, + .cm_l4sec_dynamicdep = 0x4a009588, + .cm_l4sec_aes1_clkctrl = 0x4a0095a0, + .cm_l4sec_aes2_clkctrl = 0x4a0095a8, + .cm_l4sec_des3des_clkctrl = 0x4a0095b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, + .cm_l4sec_rng_clkctrl = 0x4a0095c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4a30610c, + .cm_sys_clksel = 0x4a306110, + .cm_wkup_clkstctrl = 0x4a307800, + .cm_wkup_l4wkup_clkctrl = 0x4a307820, + .cm_wkup_wdtimer1_clkctrl = 0x4a307828, + .cm_wkup_wdtimer2_clkctrl = 0x4a307830, + .cm_wkup_gpio1_clkctrl = 0x4a307838, + .cm_wkup_gptimer1_clkctrl = 0x4a307840, + .cm_wkup_gptimer12_clkctrl = 0x4a307848, + .cm_wkup_synctimer_clkctrl = 0x4a307850, + .cm_wkup_usim_clkctrl = 0x4a307858, + .cm_wkup_sarram_clkctrl = 0x4a307860, + .cm_wkup_keyboard_clkctrl = 0x4a307878, + .cm_wkup_rtc_clkctrl = 0x4a307880, + .cm_wkup_bandgap_clkctrl = 0x4a307888, + .prm_vc_val_bypass = 0x4a307ba0, + .prm_vc_cfg_channel = 0x4a307ba4, + .prm_vc_cfg_i2c_mode = 0x4a307ba8, + .prm_vc_cfg_i2c_clk = 0x4a307bac, +}; diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index 9b261c4..81625f6 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -29,6 +29,8 @@ COBJS += hwinit.o COBJS += clocks.o COBJS += emif.o COBJS += sdram.o +COBJS += prcm-regs.o +COBJS += hw_data.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index 1f33692..a90f922 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -47,8 +47,6 @@ #define puts(s) #endif -struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100; - const u32 sys_clk_array[8] = { 12000000, /* 12 MHz */ 0, /* NA */ @@ -188,7 +186,7 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -void setup_post_dividers(u32 *const base, const struct dpll_params *params) +void setup_post_dividers(u32 const base, const struct dpll_params *params) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; @@ -282,9 +280,9 @@ void scale_vcores(void) if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { /* Configure LDO SRAM "magic" bits */ - writel(2, &prcm->prm_sldo_core_setup); - writel(2, &prcm->prm_sldo_mpu_setup); - writel(2, &prcm->prm_sldo_mm_setup); + writel(2, (*prcm)->prm_sldo_core_setup); + writel(2, (*prcm)->prm_sldo_mpu_setup); + writel(2, (*prcm)->prm_sldo_mm_setup); } } @@ -309,57 +307,57 @@ u32 get_offset_code(u32 volt_offset) */ void enable_basic_clocks(void) { - u32 *const clk_domains_essential[] = { - &prcm->cm_l4per_clkstctrl, - &prcm->cm_l3init_clkstctrl, - &prcm->cm_memif_clkstctrl, - &prcm->cm_l4cfg_clkstctrl, + u32 const clk_domains_essential[] = { + (*prcm)->cm_l4per_clkstctrl, + (*prcm)->cm_l3init_clkstctrl, + (*prcm)->cm_memif_clkstctrl, + (*prcm)->cm_l4cfg_clkstctrl, 0 }; - u32 *const clk_modules_hw_auto_essential[] = { - &prcm->cm_l3_2_gpmc_clkctrl, - &prcm->cm_memif_emif_1_clkctrl, - &prcm->cm_memif_emif_2_clkctrl, - &prcm->cm_l4cfg_l4_cfg_clkctrl, - &prcm->cm_wkup_gpio1_clkctrl, - &prcm->cm_l4per_gpio2_clkctrl, - &prcm->cm_l4per_gpio3_clkctrl, - &prcm->cm_l4per_gpio4_clkctrl, - &prcm->cm_l4per_gpio5_clkctrl, - &prcm->cm_l4per_gpio6_clkctrl, + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3_2_gpmc_clkctrl, + (*prcm)->cm_memif_emif_1_clkctrl, + (*prcm)->cm_memif_emif_2_clkctrl, + (*prcm)->cm_l4cfg_l4_cfg_clkctrl, + (*prcm)->cm_wkup_gpio1_clkctrl, + (*prcm)->cm_l4per_gpio2_clkctrl, + (*prcm)->cm_l4per_gpio3_clkctrl, + (*prcm)->cm_l4per_gpio4_clkctrl, + (*prcm)->cm_l4per_gpio5_clkctrl, + (*prcm)->cm_l4per_gpio6_clkctrl, 0 }; - u32 *const clk_modules_explicit_en_essential[] = { - &prcm->cm_wkup_gptimer1_clkctrl, - &prcm->cm_l3init_hsmmc1_clkctrl, - &prcm->cm_l3init_hsmmc2_clkctrl, - &prcm->cm_l4per_gptimer2_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_l4per_uart3_clkctrl, - &prcm->cm_l4per_i2c1_clkctrl, + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_wkup_gptimer1_clkctrl, + (*prcm)->cm_l3init_hsmmc1_clkctrl, + (*prcm)->cm_l3init_hsmmc2_clkctrl, + (*prcm)->cm_l4per_gptimer2_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart3_clkctrl, + (*prcm)->cm_l4per_i2c1_clkctrl, 0 }; /* Enable optional additional functional clock for GPIO4 */ - setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, + setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, GPIO4_CLKCTRL_OPTFCLKEN_MASK); /* Enable 96 MHz clock for MMC1 & MMC2 */ - setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); - setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); /* Set the correct clock dividers for mmc */ - setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_DIV_MASK); /* Select 32KHz clock as the source of GPTIMER1 */ - setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, + setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, GPTIMER1_CLKCTRL_CLKSEL_MASK); do_enable_clocks(clk_domains_essential, @@ -368,36 +366,36 @@ void enable_basic_clocks(void) 1); /* Select 384Mhz for GPU as its the POR for ES1.0 */ - setbits_le32(&prcm->cm_sgx_sgx_clkctrl, + setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, CLKSEL_GPU_HYD_GCLK_MASK); - setbits_le32(&prcm->cm_sgx_sgx_clkctrl, + setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, CLKSEL_GPU_CORE_GCLK_MASK); /* Enable SCRM OPT clocks for PER and CORE dpll */ - setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl, + setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); - setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl, + setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_CORE_MASK); } void enable_basic_uboot_clocks(void) { - u32 *const clk_domains_essential[] = { + u32 const clk_domains_essential[] = { 0 }; - u32 *const clk_modules_hw_auto_essential[] = { + u32 const clk_modules_hw_auto_essential[] = { 0 }; - u32 *const clk_modules_explicit_en_essential[] = { - &prcm->cm_l4per_mcspi1_clkctrl, - &prcm->cm_l4per_i2c2_clkctrl, - &prcm->cm_l4per_i2c3_clkctrl, - &prcm->cm_l4per_i2c4_clkctrl, - &prcm->cm_l3init_hsusbtll_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, - &prcm->cm_l3init_fsusb_clkctrl, + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_l4per_mcspi1_clkctrl, + (*prcm)->cm_l4per_i2c2_clkctrl, + (*prcm)->cm_l4per_i2c3_clkctrl, + (*prcm)->cm_l4per_i2c4_clkctrl, + (*prcm)->cm_l3init_hsusbtll_clkctrl, + (*prcm)->cm_l3init_hsusbhost_clkctrl, + (*prcm)->cm_l3init_fsusb_clkctrl, 0 }; @@ -413,75 +411,75 @@ void enable_basic_uboot_clocks(void) */ void enable_non_essential_clocks(void) { - u32 *const clk_domains_non_essential[] = { - &prcm->cm_mpu_m3_clkstctrl, - &prcm->cm_ivahd_clkstctrl, - &prcm->cm_dsp_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sgx_clkstctrl, - &prcm->cm1_abe_clkstctrl, - &prcm->cm_c2c_clkstctrl, - &prcm->cm_cam_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sdma_clkstctrl, + u32 const clk_domains_non_essential[] = { + (*prcm)->cm_mpu_m3_clkstctrl, + (*prcm)->cm_ivahd_clkstctrl, + (*prcm)->cm_dsp_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sgx_clkstctrl, + (*prcm)->cm1_abe_clkstctrl, + (*prcm)->cm_c2c_clkstctrl, + (*prcm)->cm_cam_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sdma_clkstctrl, 0 }; - u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_mpu_m3_mpu_m3_clkctrl, - &prcm->cm_ivahd_ivahd_clkctrl, - &prcm->cm_ivahd_sl2_clkctrl, - &prcm->cm_dsp_dsp_clkctrl, - &prcm->cm_l3instr_l3_3_clkctrl, - &prcm->cm_l3instr_l3_instr_clkctrl, - &prcm->cm_l3instr_intrconn_wp1_clkctrl, - &prcm->cm_l3init_hsi_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, + u32 const clk_modules_hw_auto_non_essential[] = { + (*prcm)->cm_mpu_m3_mpu_m3_clkctrl, + (*prcm)->cm_ivahd_ivahd_clkctrl, + (*prcm)->cm_ivahd_sl2_clkctrl, + (*prcm)->cm_dsp_dsp_clkctrl, + (*prcm)->cm_l3instr_l3_3_clkctrl, + (*prcm)->cm_l3instr_l3_instr_clkctrl, + (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, + (*prcm)->cm_l3init_hsi_clkctrl, + (*prcm)->cm_l4per_hdq1w_clkctrl, 0 }; - u32 *const clk_modules_explicit_en_non_essential[] = { - &prcm->cm1_abe_aess_clkctrl, - &prcm->cm1_abe_pdm_clkctrl, - &prcm->cm1_abe_dmic_clkctrl, - &prcm->cm1_abe_mcasp_clkctrl, - &prcm->cm1_abe_mcbsp1_clkctrl, - &prcm->cm1_abe_mcbsp2_clkctrl, - &prcm->cm1_abe_mcbsp3_clkctrl, - &prcm->cm1_abe_slimbus_clkctrl, - &prcm->cm1_abe_timer5_clkctrl, - &prcm->cm1_abe_timer6_clkctrl, - &prcm->cm1_abe_timer7_clkctrl, - &prcm->cm1_abe_timer8_clkctrl, - &prcm->cm1_abe_wdt3_clkctrl, - &prcm->cm_l4per_gptimer9_clkctrl, - &prcm->cm_l4per_gptimer10_clkctrl, - &prcm->cm_l4per_gptimer11_clkctrl, - &prcm->cm_l4per_gptimer3_clkctrl, - &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_mcspi2_clkctrl, - &prcm->cm_l4per_mcspi3_clkctrl, - &prcm->cm_l4per_mcspi4_clkctrl, - &prcm->cm_l4per_mmcsd3_clkctrl, - &prcm->cm_l4per_mmcsd4_clkctrl, - &prcm->cm_l4per_mmcsd5_clkctrl, - &prcm->cm_l4per_uart1_clkctrl, - &prcm->cm_l4per_uart2_clkctrl, - &prcm->cm_l4per_uart4_clkctrl, - &prcm->cm_wkup_keyboard_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_cam_iss_clkctrl, - &prcm->cm_cam_fdif_clkctrl, - &prcm->cm_dss_dss_clkctrl, - &prcm->cm_sgx_sgx_clkctrl, + u32 const clk_modules_explicit_en_non_essential[] = { + (*prcm)->cm1_abe_aess_clkctrl, + (*prcm)->cm1_abe_pdm_clkctrl, + (*prcm)->cm1_abe_dmic_clkctrl, + (*prcm)->cm1_abe_mcasp_clkctrl, + (*prcm)->cm1_abe_mcbsp1_clkctrl, + (*prcm)->cm1_abe_mcbsp2_clkctrl, + (*prcm)->cm1_abe_mcbsp3_clkctrl, + (*prcm)->cm1_abe_slimbus_clkctrl, + (*prcm)->cm1_abe_timer5_clkctrl, + (*prcm)->cm1_abe_timer6_clkctrl, + (*prcm)->cm1_abe_timer7_clkctrl, + (*prcm)->cm1_abe_timer8_clkctrl, + (*prcm)->cm1_abe_wdt3_clkctrl, + (*prcm)->cm_l4per_gptimer9_clkctrl, + (*prcm)->cm_l4per_gptimer10_clkctrl, + (*prcm)->cm_l4per_gptimer11_clkctrl, + (*prcm)->cm_l4per_gptimer3_clkctrl, + (*prcm)->cm_l4per_gptimer4_clkctrl, + (*prcm)->cm_l4per_mcspi2_clkctrl, + (*prcm)->cm_l4per_mcspi3_clkctrl, + (*prcm)->cm_l4per_mcspi4_clkctrl, + (*prcm)->cm_l4per_mmcsd3_clkctrl, + (*prcm)->cm_l4per_mmcsd4_clkctrl, + (*prcm)->cm_l4per_mmcsd5_clkctrl, + (*prcm)->cm_l4per_uart1_clkctrl, + (*prcm)->cm_l4per_uart2_clkctrl, + (*prcm)->cm_l4per_uart4_clkctrl, + (*prcm)->cm_wkup_keyboard_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_cam_iss_clkctrl, + (*prcm)->cm_cam_fdif_clkctrl, + (*prcm)->cm_dss_dss_clkctrl, + (*prcm)->cm_sgx_sgx_clkctrl, 0 }; /* Enable optional functional clock for ISS */ - setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); + setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); /* Enable all optional functional clocks of DSS */ - setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); + setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); do_enable_clocks(clk_domains_non_essential, clk_modules_hw_auto_non_essential, @@ -489,7 +487,8 @@ void enable_non_essential_clocks(void) 0); /* Put camera module in no sleep mode */ - clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, + clrsetbits_le32((*prcm)->cm_cam_clkstctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << MODULE_CLKCTRL_MODULEMODE_SHIFT); } diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c new file mode 100644 index 0000000..0f1234c --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -0,0 +1,38 @@ +/* + * + * HW data initialization for OMAP5 + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include + +struct prcm_regs const **prcm = + (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; + +void hw_data_init(void) +{ + *prcm = &omap5_es1_prcm; +} diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c new file mode 100644 index 0000000..cdc4864 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -0,0 +1,306 @@ +/* + * + * HW regs data for OMAP5 Soc + * + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +struct prcm_regs const omap5_es1_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_h11_dpll_core = 0x4a004138, + .cm_div_h12_dpll_core = 0x4a00413c, + .cm_div_h13_dpll_core = 0x4a004140, + .cm_div_h14_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_emu_override_dpll_core = 0x4a004150, + .cm_div_h22_dpllcore = 0x4a004154, + .cm_div_h23_dpll_core = 0x4a004158, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_h11_dpll_iva = 0x4a0041b8, + .cm_div_h12_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_h11_dpll_ddrphy = 0x4a004238, + .cm_div_h12_dpll_ddrphy = 0x4a00423c, + .cm_div_h13_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_h11_dpll_per = 0x4a008158, + .cm_div_h12_dpll_per = 0x4a00815c, + .cm_div_h14_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + + /* cm2.core */ + .cm_coreaon_bandgap_clkctrl = 0x4a008648, + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_2_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, + + /* cm2.ivahd */ + .cm_ivahd_clkstctrl = 0x4a008f00, + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_iss_clkctrl = 0x4a009020, + .cm_cam_fdif_clkctrl = 0x4a009028, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsi_clkctrl = 0x4a009338, + .cm_l3init_hsusbhost_clkctrl = 0x4a009358, + .cm_l3init_hsusbotg_clkctrl = 0x4a009360, + .cm_l3init_hsusbtll_clkctrl = 0x4a009368, + .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_fsusb_clkctrl = 0x4a0093d0, + .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009400, + .cm_l4per_dynamicdep = 0x4a009408, + .cm_l4per_adc_clkctrl = 0x4a009420, + .cm_l4per_gptimer10_clkctrl = 0x4a009428, + .cm_l4per_gptimer11_clkctrl = 0x4a009430, + .cm_l4per_gptimer2_clkctrl = 0x4a009438, + .cm_l4per_gptimer3_clkctrl = 0x4a009440, + .cm_l4per_gptimer4_clkctrl = 0x4a009448, + .cm_l4per_gptimer9_clkctrl = 0x4a009450, + .cm_l4per_elm_clkctrl = 0x4a009458, + .cm_l4per_gpio2_clkctrl = 0x4a009460, + .cm_l4per_gpio3_clkctrl = 0x4a009468, + .cm_l4per_gpio4_clkctrl = 0x4a009470, + .cm_l4per_gpio5_clkctrl = 0x4a009478, + .cm_l4per_gpio6_clkctrl = 0x4a009480, + .cm_l4per_hdq1w_clkctrl = 0x4a009488, + .cm_l4per_hecc1_clkctrl = 0x4a009490, + .cm_l4per_hecc2_clkctrl = 0x4a009498, + .cm_l4per_i2c1_clkctrl = 0x4a0094a0, + .cm_l4per_i2c2_clkctrl = 0x4a0094a8, + .cm_l4per_i2c3_clkctrl = 0x4a0094b0, + .cm_l4per_i2c4_clkctrl = 0x4a0094b8, + .cm_l4per_l4per_clkctrl = 0x4a0094c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, + .cm_l4per_mgate_clkctrl = 0x4a0094e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009500, + .cm_l4per_mcspi4_clkctrl = 0x4a009508, + .cm_l4per_gpio7_clkctrl = 0x4a009510, + .cm_l4per_gpio8_clkctrl = 0x4a009518, + .cm_l4per_mmcsd3_clkctrl = 0x4a009520, + .cm_l4per_mmcsd4_clkctrl = 0x4a009528, + .cm_l4per_msprohg_clkctrl = 0x4a009530, + .cm_l4per_slimbus2_clkctrl = 0x4a009538, + .cm_l4per_uart1_clkctrl = 0x4a009540, + .cm_l4per_uart2_clkctrl = 0x4a009548, + .cm_l4per_uart3_clkctrl = 0x4a009550, + .cm_l4per_uart4_clkctrl = 0x4a009558, + .cm_l4per_mmcsd5_clkctrl = 0x4a009560, + .cm_l4per_i2c5_clkctrl = 0x4a009568, + .cm_l4per_uart5_clkctrl = 0x4a009570, + .cm_l4per_uart6_clkctrl = 0x4a009578, + .cm_l4sec_clkstctrl = 0x4a009580, + .cm_l4sec_staticdep = 0x4a009584, + .cm_l4sec_dynamicdep = 0x4a009588, + .cm_l4sec_aes1_clkctrl = 0x4a0095a0, + .cm_l4sec_aes2_clkctrl = 0x4a0095a8, + .cm_l4sec_des3des_clkctrl = 0x4a0095b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, + .cm_l4sec_rng_clkctrl = 0x4a0095c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4ae0610c, + .cm_sys_clksel = 0x4ae06110, + .cm_wkup_clkstctrl = 0x4ae07800, + .cm_wkup_l4wkup_clkctrl = 0x4ae07820, + .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, + .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, + .cm_wkup_gpio1_clkctrl = 0x4ae07838, + .cm_wkup_gptimer1_clkctrl = 0x4ae07840, + .cm_wkup_gptimer12_clkctrl = 0x4ae07848, + .cm_wkup_synctimer_clkctrl = 0x4ae07850, + .cm_wkup_usim_clkctrl = 0x4ae07858, + .cm_wkup_sarram_clkctrl = 0x4ae07860, + .cm_wkup_keyboard_clkctrl = 0x4ae07878, + .cm_wkup_rtc_clkctrl = 0x4ae07880, + .cm_wkup_bandgap_clkctrl = 0x4ae07888, + .cm_wkupaon_scrm_clkctrl = 0x4ae07890, + .prm_vc_val_bypass = 0x4ae07ba0, + .prm_vc_cfg_i2c_mode = 0x4ae07bb4, + .prm_vc_cfg_i2c_clk = 0x4ae07bb8, + .prm_sldo_core_setup = 0x4ae07bc4, + .prm_sldo_core_ctrl = 0x4ae07bc8, + .prm_sldo_mpu_setup = 0x4ae07bcc, + .prm_sldo_mpu_ctrl = 0x4ae07bd0, + .prm_sldo_mm_setup = 0x4ae07bd4, + .prm_sldo_mm_ctrl = 0x4ae07bd8, +}; diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index be20fc0..4710d88 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -25,6 +25,7 @@ #ifndef _CLOCKS_OMAP4_H_ #define _CLOCKS_OMAP4_H_ #include +#include /* * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per @@ -38,479 +39,6 @@ #define CM_CLKMODE_DPLL_MPU 0x4A004160 #define CM_CLKSEL_CORE 0x4A004100 -struct omap4_prcm_regs { - /* cm1.ckgen */ - u32 cm_clksel_core; - u32 pad001[1]; - u32 cm_clksel_abe; - u32 pad002[1]; - u32 cm_dll_ctrl; - u32 pad003[3]; - u32 cm_clkmode_dpll_core; - u32 cm_idlest_dpll_core; - u32 cm_autoidle_dpll_core; - u32 cm_clksel_dpll_core; - u32 cm_div_m2_dpll_core; - u32 cm_div_m3_dpll_core; - u32 cm_div_m4_dpll_core; - u32 cm_div_m5_dpll_core; - u32 cm_div_m6_dpll_core; - u32 cm_div_m7_dpll_core; - u32 cm_ssc_deltamstep_dpll_core; - u32 cm_ssc_modfreqdiv_dpll_core; - u32 cm_emu_override_dpll_core; - u32 pad004[3]; - u32 cm_clkmode_dpll_mpu; - u32 cm_idlest_dpll_mpu; - u32 cm_autoidle_dpll_mpu; - u32 cm_clksel_dpll_mpu; - u32 cm_div_m2_dpll_mpu; - u32 pad005[5]; - u32 cm_ssc_deltamstep_dpll_mpu; - u32 cm_ssc_modfreqdiv_dpll_mpu; - u32 pad006[3]; - u32 cm_bypclk_dpll_mpu; - u32 cm_clkmode_dpll_iva; - u32 cm_idlest_dpll_iva; - u32 cm_autoidle_dpll_iva; - u32 cm_clksel_dpll_iva; - u32 pad007[2]; - u32 cm_div_m4_dpll_iva; - u32 cm_div_m5_dpll_iva; - u32 pad008[2]; - u32 cm_ssc_deltamstep_dpll_iva; - u32 cm_ssc_modfreqdiv_dpll_iva; - u32 pad009[3]; - u32 cm_bypclk_dpll_iva; - u32 cm_clkmode_dpll_abe; - u32 cm_idlest_dpll_abe; - u32 cm_autoidle_dpll_abe; - u32 cm_clksel_dpll_abe; - u32 cm_div_m2_dpll_abe; - u32 cm_div_m3_dpll_abe; - u32 pad010[4]; - u32 cm_ssc_deltamstep_dpll_abe; - u32 cm_ssc_modfreqdiv_dpll_abe; - u32 pad011[4]; - u32 cm_clkmode_dpll_ddrphy; - u32 cm_idlest_dpll_ddrphy; - u32 cm_autoidle_dpll_ddrphy; - u32 cm_clksel_dpll_ddrphy; - u32 cm_div_m2_dpll_ddrphy; - u32 pad012[1]; - u32 cm_div_m4_dpll_ddrphy; - u32 cm_div_m5_dpll_ddrphy; - u32 cm_div_m6_dpll_ddrphy; - u32 pad013[1]; - u32 cm_ssc_deltamstep_dpll_ddrphy; - u32 pad014[5]; - u32 cm_shadow_freq_config1; - u32 pad0141[47]; - u32 cm_mpu_mpu_clkctrl; - - /* cm1.dsp */ - u32 pad015[55]; - u32 cm_dsp_clkstctrl; - u32 pad016[7]; - u32 cm_dsp_dsp_clkctrl; - - /* cm1.abe */ - u32 pad017[55]; - u32 cm1_abe_clkstctrl; - u32 pad018[7]; - u32 cm1_abe_l4abe_clkctrl; - u32 pad019[1]; - u32 cm1_abe_aess_clkctrl; - u32 pad020[1]; - u32 cm1_abe_pdm_clkctrl; - u32 pad021[1]; - u32 cm1_abe_dmic_clkctrl; - u32 pad022[1]; - u32 cm1_abe_mcasp_clkctrl; - u32 pad023[1]; - u32 cm1_abe_mcbsp1_clkctrl; - u32 pad024[1]; - u32 cm1_abe_mcbsp2_clkctrl; - u32 pad025[1]; - u32 cm1_abe_mcbsp3_clkctrl; - u32 pad026[1]; - u32 cm1_abe_slimbus_clkctrl; - u32 pad027[1]; - u32 cm1_abe_timer5_clkctrl; - u32 pad028[1]; - u32 cm1_abe_timer6_clkctrl; - u32 pad029[1]; - u32 cm1_abe_timer7_clkctrl; - u32 pad030[1]; - u32 cm1_abe_timer8_clkctrl; - u32 pad031[1]; - u32 cm1_abe_wdt3_clkctrl; - - /* cm2.ckgen */ - u32 pad032[3805]; - u32 cm_clksel_mpu_m3_iss_root; - u32 cm_clksel_usb_60mhz; - u32 cm_scale_fclk; - u32 pad033[1]; - u32 cm_core_dvfs_perf1; - u32 cm_core_dvfs_perf2; - u32 cm_core_dvfs_perf3; - u32 cm_core_dvfs_perf4; - u32 pad034[1]; - u32 cm_core_dvfs_current; - u32 cm_iva_dvfs_perf_tesla; - u32 cm_iva_dvfs_perf_ivahd; - u32 cm_iva_dvfs_perf_abe; - u32 pad035[1]; - u32 cm_iva_dvfs_current; - u32 pad036[1]; - u32 cm_clkmode_dpll_per; - u32 cm_idlest_dpll_per; - u32 cm_autoidle_dpll_per; - u32 cm_clksel_dpll_per; - u32 cm_div_m2_dpll_per; - u32 cm_div_m3_dpll_per; - u32 cm_div_m4_dpll_per; - u32 cm_div_m5_dpll_per; - u32 cm_div_m6_dpll_per; - u32 cm_div_m7_dpll_per; - u32 cm_ssc_deltamstep_dpll_per; - u32 cm_ssc_modfreqdiv_dpll_per; - u32 cm_emu_override_dpll_per; - u32 pad037[3]; - u32 cm_clkmode_dpll_usb; - u32 cm_idlest_dpll_usb; - u32 cm_autoidle_dpll_usb; - u32 cm_clksel_dpll_usb; - u32 cm_div_m2_dpll_usb; - u32 pad038[5]; - u32 cm_ssc_deltamstep_dpll_usb; - u32 cm_ssc_modfreqdiv_dpll_usb; - u32 pad039[1]; - u32 cm_clkdcoldo_dpll_usb; - u32 pad040[2]; - u32 cm_clkmode_dpll_unipro; - u32 cm_idlest_dpll_unipro; - u32 cm_autoidle_dpll_unipro; - u32 cm_clksel_dpll_unipro; - u32 cm_div_m2_dpll_unipro; - u32 pad041[5]; - u32 cm_ssc_deltamstep_dpll_unipro; - u32 cm_ssc_modfreqdiv_dpll_unipro; - - /* cm2.core */ - u32 pad0411[324]; - u32 cm_l3_1_clkstctrl; - u32 pad042[1]; - u32 cm_l3_1_dynamicdep; - u32 pad043[5]; - u32 cm_l3_1_l3_1_clkctrl; - u32 pad044[55]; - u32 cm_l3_2_clkstctrl; - u32 pad045[1]; - u32 cm_l3_2_dynamicdep; - u32 pad046[5]; - u32 cm_l3_2_l3_2_clkctrl; - u32 pad047[1]; - u32 cm_l3_2_gpmc_clkctrl; - u32 pad048[1]; - u32 cm_l3_2_ocmc_ram_clkctrl; - u32 pad049[51]; - u32 cm_mpu_m3_clkstctrl; - u32 cm_mpu_m3_staticdep; - u32 cm_mpu_m3_dynamicdep; - u32 pad050[5]; - u32 cm_mpu_m3_mpu_m3_clkctrl; - u32 pad051[55]; - u32 cm_sdma_clkstctrl; - u32 cm_sdma_staticdep; - u32 cm_sdma_dynamicdep; - u32 pad052[5]; - u32 cm_sdma_sdma_clkctrl; - u32 pad053[55]; - u32 cm_memif_clkstctrl; - u32 pad054[7]; - u32 cm_memif_dmm_clkctrl; - u32 pad055[1]; - u32 cm_memif_emif_fw_clkctrl; - u32 pad056[1]; - u32 cm_memif_emif_1_clkctrl; - u32 pad057[1]; - u32 cm_memif_emif_2_clkctrl; - u32 pad058[1]; - u32 cm_memif_dll_clkctrl; - u32 pad059[3]; - u32 cm_memif_emif_h1_clkctrl; - u32 pad060[1]; - u32 cm_memif_emif_h2_clkctrl; - u32 pad061[1]; - u32 cm_memif_dll_h_clkctrl; - u32 pad062[39]; - u32 cm_c2c_clkstctrl; - u32 cm_c2c_staticdep; - u32 cm_c2c_dynamicdep; - u32 pad063[5]; - u32 cm_c2c_sad2d_clkctrl; - u32 pad064[1]; - u32 cm_c2c_modem_icr_clkctrl; - u32 pad065[1]; - u32 cm_c2c_sad2d_fw_clkctrl; - u32 pad066[51]; - u32 cm_l4cfg_clkstctrl; - u32 pad067[1]; - u32 cm_l4cfg_dynamicdep; - u32 pad068[5]; - u32 cm_l4cfg_l4_cfg_clkctrl; - u32 pad069[1]; - u32 cm_l4cfg_hw_sem_clkctrl; - u32 pad070[1]; - u32 cm_l4cfg_mailbox_clkctrl; - u32 pad071[1]; - u32 cm_l4cfg_sar_rom_clkctrl; - u32 pad072[49]; - u32 cm_l3instr_clkstctrl; - u32 pad073[7]; - u32 cm_l3instr_l3_3_clkctrl; - u32 pad074[1]; - u32 cm_l3instr_l3_instr_clkctrl; - u32 pad075[5]; - u32 cm_l3instr_intrconn_wp1_clkctrl; - - - /* cm2.ivahd */ - u32 pad076[47]; - u32 cm_ivahd_clkstctrl; - u32 pad077[7]; - u32 cm_ivahd_ivahd_clkctrl; - u32 pad078[1]; - u32 cm_ivahd_sl2_clkctrl; - - /* cm2.cam */ - u32 pad079[53]; - u32 cm_cam_clkstctrl; - u32 pad080[7]; - u32 cm_cam_iss_clkctrl; - u32 pad081[1]; - u32 cm_cam_fdif_clkctrl; - - /* cm2.dss */ - u32 pad082[53]; - u32 cm_dss_clkstctrl; - u32 pad083[7]; - u32 cm_dss_dss_clkctrl; - - /* cm2.sgx */ - u32 pad084[55]; - u32 cm_sgx_clkstctrl; - u32 pad085[7]; - u32 cm_sgx_sgx_clkctrl; - - /* cm2.l3init */ - u32 pad086[55]; - u32 cm_l3init_clkstctrl; - - /* cm2.l3init */ - u32 pad087[9]; - u32 cm_l3init_hsmmc1_clkctrl; - u32 pad088[1]; - u32 cm_l3init_hsmmc2_clkctrl; - u32 pad089[1]; - u32 cm_l3init_hsi_clkctrl; - u32 pad090[7]; - u32 cm_l3init_hsusbhost_clkctrl; - u32 pad091[1]; - u32 cm_l3init_hsusbotg_clkctrl; - u32 pad092[1]; - u32 cm_l3init_hsusbtll_clkctrl; - u32 pad093[3]; - u32 cm_l3init_p1500_clkctrl; - u32 pad094[21]; - u32 cm_l3init_fsusb_clkctrl; - u32 pad095[3]; - u32 cm_l3init_usbphy_clkctrl; - - /* cm2.l4per */ - u32 pad096[7]; - u32 cm_l4per_clkstctrl; - u32 pad097[1]; - u32 cm_l4per_dynamicdep; - u32 pad098[5]; - u32 cm_l4per_adc_clkctrl; - u32 pad100[1]; - u32 cm_l4per_gptimer10_clkctrl; - u32 pad101[1]; - u32 cm_l4per_gptimer11_clkctrl; - u32 pad102[1]; - u32 cm_l4per_gptimer2_clkctrl; - u32 pad103[1]; - u32 cm_l4per_gptimer3_clkctrl; - u32 pad104[1]; - u32 cm_l4per_gptimer4_clkctrl; - u32 pad105[1]; - u32 cm_l4per_gptimer9_clkctrl; - u32 pad106[1]; - u32 cm_l4per_elm_clkctrl; - u32 pad107[1]; - u32 cm_l4per_gpio2_clkctrl; - u32 pad108[1]; - u32 cm_l4per_gpio3_clkctrl; - u32 pad109[1]; - u32 cm_l4per_gpio4_clkctrl; - u32 pad110[1]; - u32 cm_l4per_gpio5_clkctrl; - u32 pad111[1]; - u32 cm_l4per_gpio6_clkctrl; - u32 pad112[1]; - u32 cm_l4per_hdq1w_clkctrl; - u32 pad113[1]; - u32 cm_l4per_hecc1_clkctrl; - u32 pad114[1]; - u32 cm_l4per_hecc2_clkctrl; - u32 pad115[1]; - u32 cm_l4per_i2c1_clkctrl; - u32 pad116[1]; - u32 cm_l4per_i2c2_clkctrl; - u32 pad117[1]; - u32 cm_l4per_i2c3_clkctrl; - u32 pad118[1]; - u32 cm_l4per_i2c4_clkctrl; - u32 pad119[1]; - u32 cm_l4per_l4per_clkctrl; - u32 pad1191[3]; - u32 cm_l4per_mcasp2_clkctrl; - u32 pad120[1]; - u32 cm_l4per_mcasp3_clkctrl; - u32 pad121[1]; - u32 cm_l4per_mcbsp4_clkctrl; - u32 pad122[1]; - u32 cm_l4per_mgate_clkctrl; - u32 pad123[1]; - u32 cm_l4per_mcspi1_clkctrl; - u32 pad124[1]; - u32 cm_l4per_mcspi2_clkctrl; - u32 pad125[1]; - u32 cm_l4per_mcspi3_clkctrl; - u32 pad126[1]; - u32 cm_l4per_mcspi4_clkctrl; - u32 pad127[5]; - u32 cm_l4per_mmcsd3_clkctrl; - u32 pad128[1]; - u32 cm_l4per_mmcsd4_clkctrl; - u32 pad129[1]; - u32 cm_l4per_msprohg_clkctrl; - u32 pad130[1]; - u32 cm_l4per_slimbus2_clkctrl; - u32 pad131[1]; - u32 cm_l4per_uart1_clkctrl; - u32 pad132[1]; - u32 cm_l4per_uart2_clkctrl; - u32 pad133[1]; - u32 cm_l4per_uart3_clkctrl; - u32 pad134[1]; - u32 cm_l4per_uart4_clkctrl; - u32 pad135[1]; - u32 cm_l4per_mmcsd5_clkctrl; - u32 pad136[1]; - u32 cm_l4per_i2c5_clkctrl; - u32 pad137[5]; - u32 cm_l4sec_clkstctrl; - u32 cm_l4sec_staticdep; - u32 cm_l4sec_dynamicdep; - u32 pad138[5]; - u32 cm_l4sec_aes1_clkctrl; - u32 pad139[1]; - u32 cm_l4sec_aes2_clkctrl; - u32 pad140[1]; - u32 cm_l4sec_des3des_clkctrl; - u32 pad141[1]; - u32 cm_l4sec_pkaeip29_clkctrl; - u32 pad142[1]; - u32 cm_l4sec_rng_clkctrl; - u32 pad143[1]; - u32 cm_l4sec_sha2md51_clkctrl; - u32 pad144[3]; - u32 cm_l4sec_cryptodma_clkctrl; - u32 pad145[776841]; - - /* l4 wkup regs */ - u32 pad201[6211]; - u32 cm_abe_pll_ref_clksel; - u32 cm_sys_clksel; - u32 pad202[1467]; - u32 cm_wkup_clkstctrl; - u32 pad203[7]; - u32 cm_wkup_l4wkup_clkctrl; - u32 pad204; - u32 cm_wkup_wdtimer1_clkctrl; - u32 pad205; - u32 cm_wkup_wdtimer2_clkctrl; - u32 pad206; - u32 cm_wkup_gpio1_clkctrl; - u32 pad207; - u32 cm_wkup_gptimer1_clkctrl; - u32 pad208; - u32 cm_wkup_gptimer12_clkctrl; - u32 pad209; - u32 cm_wkup_synctimer_clkctrl; - u32 pad210; - u32 cm_wkup_usim_clkctrl; - u32 pad211; - u32 cm_wkup_sarram_clkctrl; - u32 pad212[5]; - u32 cm_wkup_keyboard_clkctrl; - u32 pad213; - u32 cm_wkup_rtc_clkctrl; - u32 pad214; - u32 cm_wkup_bandgap_clkctrl; - u32 pad215[197]; - u32 prm_vc_val_bypass; - u32 prm_vc_cfg_channel; - u32 prm_vc_cfg_i2c_mode; - u32 prm_vc_cfg_i2c_clk; - -}; - -struct omap4_scrm_regs { - u32 revision; /* 0x0000 */ - u32 pad00[63]; - u32 clksetuptime; /* 0x0100 */ - u32 pmicsetuptime; /* 0x0104 */ - u32 pad01[2]; - u32 altclksrc; /* 0x0110 */ - u32 pad02[2]; - u32 c2cclkm; /* 0x011c */ - u32 pad03[56]; - u32 extclkreq; /* 0x0200 */ - u32 accclkreq; /* 0x0204 */ - u32 pwrreq; /* 0x0208 */ - u32 pad04[1]; - u32 auxclkreq0; /* 0x0210 */ - u32 auxclkreq1; /* 0x0214 */ - u32 auxclkreq2; /* 0x0218 */ - u32 auxclkreq3; /* 0x021c */ - u32 auxclkreq4; /* 0x0220 */ - u32 auxclkreq5; /* 0x0224 */ - u32 pad05[3]; - u32 c2cclkreq; /* 0x0234 */ - u32 pad06[54]; - u32 auxclk0; /* 0x0310 */ - u32 auxclk1; /* 0x0314 */ - u32 auxclk2; /* 0x0318 */ - u32 auxclk3; /* 0x031c */ - u32 auxclk4; /* 0x0320 */ - u32 auxclk5; /* 0x0324 */ - u32 pad07[54]; - u32 rsttime_reg; /* 0x0400 */ - u32 pad08[6]; - u32 c2crstctrl; /* 0x041c */ - u32 extpwronrstctrl; /* 0x0420 */ - u32 pad09[59]; - u32 extwarmrstst_reg; /* 0x0510 */ - u32 apewarmrstst_reg; /* 0x0514 */ - u32 pad10[1]; - u32 c2cwarmrstst_reg; /* 0x051C */ -}; - /* DPLL register offsets */ #define CM_CLKMODE_DPLL 0 #define CM_IDLEST_DPLL 0x4 @@ -741,7 +269,6 @@ struct dpll_params { s8 m7; }; -extern struct omap4_prcm_regs *const prcm; extern const u32 sys_clk_array[8]; void scale_vcores(void); @@ -749,14 +276,14 @@ void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); u32 get_offset_code(u32 offset); u32 omap_ddr_clk(void); void do_scale_vcore(u32 vcore_reg, u32 volt_mv); -void setup_post_dividers(u32 *const base, const struct dpll_params *params); +void setup_post_dividers(u32 const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); void enable_non_essential_clocks(void); -void do_enable_clocks(u32 *const *clk_domains, - u32 *const *clk_modules_hw_auto, - u32 *const *clk_modules_explicit_en, +void do_enable_clocks(u32 const *clk_domains, + u32 const *clk_modules_hw_auto, + u32 const *clk_modules_explicit_en, u8 wait_for_enable); const struct dpll_params *get_mpu_dpll_params(void); const struct dpll_params *get_core_dpll_params(void); @@ -764,4 +291,45 @@ const struct dpll_params *get_per_dpll_params(void); const struct dpll_params *get_iva_dpll_params(void); const struct dpll_params *get_usb_dpll_params(void); const struct dpll_params *get_abe_dpll_params(void); + +struct omap4_scrm_regs { + u32 revision; /* 0x0000 */ + u32 pad00[63]; + u32 clksetuptime; /* 0x0100 */ + u32 pmicsetuptime; /* 0x0104 */ + u32 pad01[2]; + u32 altclksrc; /* 0x0110 */ + u32 pad02[2]; + u32 c2cclkm; /* 0x011c */ + u32 pad03[56]; + u32 extclkreq; /* 0x0200 */ + u32 accclkreq; /* 0x0204 */ + u32 pwrreq; /* 0x0208 */ + u32 pad04[1]; + u32 auxclkreq0; /* 0x0210 */ + u32 auxclkreq1; /* 0x0214 */ + u32 auxclkreq2; /* 0x0218 */ + u32 auxclkreq3; /* 0x021c */ + u32 auxclkreq4; /* 0x0220 */ + u32 auxclkreq5; /* 0x0224 */ + u32 pad05[3]; + u32 c2cclkreq; /* 0x0234 */ + u32 pad06[54]; + u32 auxclk0; /* 0x0310 */ + u32 auxclk1; /* 0x0314 */ + u32 auxclk2; /* 0x0318 */ + u32 auxclk3; /* 0x031c */ + u32 auxclk4; /* 0x0320 */ + u32 auxclk5; /* 0x0324 */ + u32 pad07[54]; + u32 rsttime_reg; /* 0x0400 */ + u32 pad08[6]; + u32 c2crstctrl; /* 0x041c */ + u32 extpwronrstctrl; /* 0x0420 */ + u32 pad09[59]; + u32 extwarmrstst_reg; /* 0x0510 */ + u32 apewarmrstst_reg; /* 0x0514 */ + u32 pad10[1]; + u32 c2cwarmrstst_reg; /* 0x051C */ +}; #endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index d4b5076..86ba335 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -178,7 +178,8 @@ struct control_lpddr2io_regs { #define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) -#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) +#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) +#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x18) /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index b48f81d..d5f1868 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -44,7 +44,7 @@ void sdelay(unsigned long); void set_pl310_ctrl_reg(u32 val); void setup_clocks_for_console(void); void prcm_init(void); -void bypass_dpll(u32 *const base); +void bypass_dpll(u32 const base); void freq_update_core(void); u32 get_sys_clk_freq(void); u32 omap4_ddr_clk(void); diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 5f1a7aa..67e74ca 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -26,6 +26,7 @@ #ifndef _CLOCKS_OMAP5_H_ #define _CLOCKS_OMAP5_H_ #include +#include /* * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per @@ -39,456 +40,6 @@ #define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160) #define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100) -struct omap5_prcm_regs { - /* cm1.ckgen */ - u32 cm_clksel_core; /* 4a004100 */ - u32 pad001[1]; /* 4a004104 */ - u32 cm_clksel_abe; /* 4a004108 */ - u32 pad002[1]; /* 4a00410c */ - u32 cm_dll_ctrl; /* 4a004110 */ - u32 pad003[3]; /* 4a004114 */ - u32 cm_clkmode_dpll_core; /* 4a004120 */ - u32 cm_idlest_dpll_core; /* 4a004124 */ - u32 cm_autoidle_dpll_core; /* 4a004128 */ - u32 cm_clksel_dpll_core; /* 4a00412c */ - u32 cm_div_m2_dpll_core; /* 4a004130 */ - u32 cm_div_m3_dpll_core; /* 4a004134 */ - u32 cm_div_h11_dpll_core; /* 4a004138 */ - u32 cm_div_h12_dpll_core; /* 4a00413c */ - u32 cm_div_h13_dpll_core; /* 4a004140 */ - u32 cm_div_h14_dpll_core; /* 4a004144 */ - u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */ - u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */ - u32 cm_emu_override_dpll_core; /* 4a004150 */ - - u32 cm_div_h22_dpllcore; /* 4a004154 */ - u32 cm_div_h23_dpll_core; /* 4a004158 */ - u32 pad0041[1]; /* 4a00415c */ - u32 cm_clkmode_dpll_mpu; /* 4a004160 */ - u32 cm_idlest_dpll_mpu; /* 4a004164 */ - u32 cm_autoidle_dpll_mpu; /* 4a004168 */ - u32 cm_clksel_dpll_mpu; /* 4a00416c */ - u32 cm_div_m2_dpll_mpu; /* 4a004170 */ - u32 pad005[5]; /* 4a004174 */ - u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */ - u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */ - u32 pad006[3]; /* 4a004190 */ - u32 cm_bypclk_dpll_mpu; /* 4a00419c */ - u32 cm_clkmode_dpll_iva; /* 4a0041a0 */ - u32 cm_idlest_dpll_iva; /* 4a0041a4 */ - u32 cm_autoidle_dpll_iva; /* 4a0041a8 */ - u32 cm_clksel_dpll_iva; /* 4a0041ac */ - u32 pad007[2]; /* 4a0041b0 */ - u32 cm_div_h11_dpll_iva; /* 4a0041b8 */ - u32 cm_div_h12_dpll_iva; /* 4a0041bc */ - u32 pad008[2]; /* 4a0041c0 */ - u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */ - u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */ - u32 pad009[3]; /* 4a0041d0 */ - u32 cm_bypclk_dpll_iva; /* 4a0041dc */ - u32 cm_clkmode_dpll_abe; /* 4a0041e0 */ - u32 cm_idlest_dpll_abe; /* 4a0041e4 */ - u32 cm_autoidle_dpll_abe; /* 4a0041e8 */ - u32 cm_clksel_dpll_abe; /* 4a0041ec */ - u32 cm_div_m2_dpll_abe; /* 4a0041f0 */ - u32 cm_div_m3_dpll_abe; /* 4a0041f4 */ - u32 pad010[4]; /* 4a0041f8 */ - u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */ - u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */ - u32 pad011[4]; /* 4a004210 */ - u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */ - u32 cm_idlest_dpll_ddrphy; /* 4a004224 */ - u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */ - u32 cm_clksel_dpll_ddrphy; /* 4a00422c */ - u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */ - u32 pad012[1]; /* 4a004234 */ - u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */ - u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */ - u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */ - u32 pad013[1]; /* 4a004244 */ - u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */ - u32 pad014[5]; /* 4a00424c */ - u32 cm_shadow_freq_config1; /* 4a004260 */ - u32 pad0141[47]; /* 4a004264 */ - u32 cm_mpu_mpu_clkctrl; /* 4a004320 */ - - - /* cm1.dsp */ - u32 pad015[55]; /* 4a004324 */ - u32 cm_dsp_clkstctrl; /* 4a004400 */ - u32 pad016[7]; /* 4a004404 */ - u32 cm_dsp_dsp_clkctrl; /* 4a004420 */ - - /* cm1.abe */ - u32 pad017[55]; /* 4a004424 */ - u32 cm1_abe_clkstctrl; /* 4a004500 */ - u32 pad018[7]; /* 4a004504 */ - u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */ - u32 pad019[1]; /* 4a004524 */ - u32 cm1_abe_aess_clkctrl; /* 4a004528 */ - u32 pad020[1]; /* 4a00452c */ - u32 cm1_abe_pdm_clkctrl; /* 4a004530 */ - u32 pad021[1]; /* 4a004534 */ - u32 cm1_abe_dmic_clkctrl; /* 4a004538 */ - u32 pad022[1]; /* 4a00453c */ - u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */ - u32 pad023[1]; /* 4a004544 */ - u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */ - u32 pad024[1]; /* 4a00454c */ - u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */ - u32 pad025[1]; /* 4a004554 */ - u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */ - u32 pad026[1]; /* 4a00455c */ - u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */ - u32 pad027[1]; /* 4a004564 */ - u32 cm1_abe_timer5_clkctrl; /* 4a004568 */ - u32 pad028[1]; /* 4a00456c */ - u32 cm1_abe_timer6_clkctrl; /* 4a004570 */ - u32 pad029[1]; /* 4a004574 */ - u32 cm1_abe_timer7_clkctrl; /* 4a004578 */ - u32 pad030[1]; /* 4a00457c */ - u32 cm1_abe_timer8_clkctrl; /* 4a004580 */ - u32 pad031[1]; /* 4a004584 */ - u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */ - - /* cm2.ckgen */ - u32 pad032[3805]; /* 4a00458c */ - u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */ - u32 cm_clksel_usb_60mhz; /* 4a008104 */ - u32 cm_scale_fclk; /* 4a008108 */ - u32 pad033[1]; /* 4a00810c */ - u32 cm_core_dvfs_perf1; /* 4a008110 */ - u32 cm_core_dvfs_perf2; /* 4a008114 */ - u32 cm_core_dvfs_perf3; /* 4a008118 */ - u32 cm_core_dvfs_perf4; /* 4a00811c */ - u32 pad034[1]; /* 4a008120 */ - u32 cm_core_dvfs_current; /* 4a008124 */ - u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */ - u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */ - u32 cm_iva_dvfs_perf_abe; /* 4a008130 */ - u32 pad035[1]; /* 4a008134 */ - u32 cm_iva_dvfs_current; /* 4a008138 */ - u32 pad036[1]; /* 4a00813c */ - u32 cm_clkmode_dpll_per; /* 4a008140 */ - u32 cm_idlest_dpll_per; /* 4a008144 */ - u32 cm_autoidle_dpll_per; /* 4a008148 */ - u32 cm_clksel_dpll_per; /* 4a00814c */ - u32 cm_div_m2_dpll_per; /* 4a008150 */ - u32 cm_div_m3_dpll_per; /* 4a008154 */ - u32 cm_div_h11_dpll_per; /* 4a008158 */ - u32 cm_div_h12_dpll_per; /* 4a00815c */ - u32 pad0361[1]; /* 4a008160 */ - u32 cm_div_h14_dpll_per; /* 4a008164 */ - u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */ - u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */ - u32 cm_emu_override_dpll_per; /* 4a008170 */ - u32 pad037[3]; /* 4a008174 */ - u32 cm_clkmode_dpll_usb; /* 4a008180 */ - u32 cm_idlest_dpll_usb; /* 4a008184 */ - u32 cm_autoidle_dpll_usb; /* 4a008188 */ - u32 cm_clksel_dpll_usb; /* 4a00818c */ - u32 cm_div_m2_dpll_usb; /* 4a008190 */ - u32 pad038[5]; /* 4a008194 */ - u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */ - u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */ - u32 pad039[1]; /* 4a0081b0 */ - u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */ - u32 pad040[2]; /* 4a0081b8 */ - u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */ - u32 cm_idlest_dpll_unipro; /* 4a0081c4 */ - u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */ - u32 cm_clksel_dpll_unipro; /* 4a0081cc */ - u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */ - u32 pad041[5]; /* 4a0081d4 */ - u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */ - u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */ - - /* cm2.core */ - u32 pad0411[324]; /* 4a0081f0 */ - u32 cm_l3_1_clkstctrl; /* 4a008700 */ - u32 pad042[1]; /* 4a008704 */ - u32 cm_l3_1_dynamicdep; /* 4a008708 */ - u32 pad043[5]; /* 4a00870c */ - u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */ - u32 pad044[55]; /* 4a008724 */ - u32 cm_l3_2_clkstctrl; /* 4a008800 */ - u32 pad045[1]; /* 4a008804 */ - u32 cm_l3_2_dynamicdep; /* 4a008808 */ - u32 pad046[5]; /* 4a00880c */ - u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */ - u32 pad047[1]; /* 4a008824 */ - u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */ - u32 pad048[1]; /* 4a00882c */ - u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */ - u32 pad049[51]; /* 4a008834 */ - u32 cm_mpu_m3_clkstctrl; /* 4a008900 */ - u32 cm_mpu_m3_staticdep; /* 4a008904 */ - u32 cm_mpu_m3_dynamicdep; /* 4a008908 */ - u32 pad050[5]; /* 4a00890c */ - u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */ - u32 pad051[55]; /* 4a008924 */ - u32 cm_sdma_clkstctrl; /* 4a008a00 */ - u32 cm_sdma_staticdep; /* 4a008a04 */ - u32 cm_sdma_dynamicdep; /* 4a008a08 */ - u32 pad052[5]; /* 4a008a0c */ - u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */ - u32 pad053[55]; /* 4a008a24 */ - u32 cm_memif_clkstctrl; /* 4a008b00 */ - u32 pad054[7]; /* 4a008b04 */ - u32 cm_memif_dmm_clkctrl; /* 4a008b20 */ - u32 pad055[1]; /* 4a008b24 */ - u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */ - u32 pad056[1]; /* 4a008b2c */ - u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */ - u32 pad057[1]; /* 4a008b34 */ - u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */ - u32 pad058[1]; /* 4a008b3c */ - u32 cm_memif_dll_clkctrl; /* 4a008b40 */ - u32 pad059[3]; /* 4a008b44 */ - u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */ - u32 pad060[1]; /* 4a008b54 */ - u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */ - u32 pad061[1]; /* 4a008b5c */ - u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */ - u32 pad062[39]; /* 4a008b64 */ - u32 cm_c2c_clkstctrl; /* 4a008c00 */ - u32 cm_c2c_staticdep; /* 4a008c04 */ - u32 cm_c2c_dynamicdep; /* 4a008c08 */ - u32 pad063[5]; /* 4a008c0c */ - u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */ - u32 pad064[1]; /* 4a008c24 */ - u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */ - u32 pad065[1]; /* 4a008c2c */ - u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */ - u32 pad066[51]; /* 4a008c34 */ - u32 cm_l4cfg_clkstctrl; /* 4a008d00 */ - u32 pad067[1]; /* 4a008d04 */ - u32 cm_l4cfg_dynamicdep; /* 4a008d08 */ - u32 pad068[5]; /* 4a008d0c */ - u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */ - u32 pad069[1]; /* 4a008d24 */ - u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */ - u32 pad070[1]; /* 4a008d2c */ - u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */ - u32 pad071[1]; /* 4a008d34 */ - u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */ - u32 pad072[49]; /* 4a008d3c */ - u32 cm_l3instr_clkstctrl; /* 4a008e00 */ - u32 pad073[7]; /* 4a008e04 */ - u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */ - u32 pad074[1]; /* 4a008e24 */ - u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */ - u32 pad075[5]; /* 4a008e2c */ - u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */ - - - /* cm2.ivahd */ - u32 pad076[47]; /* 4a008e44 */ - u32 cm_ivahd_clkstctrl; /* 4a008f00 */ - u32 pad077[7]; /* 4a008f04 */ - u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */ - u32 pad078[1]; /* 4a008f24 */ - u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */ - - /* cm2.cam */ - u32 pad079[53]; /* 4a008f2c */ - u32 cm_cam_clkstctrl; /* 4a009000 */ - u32 pad080[7]; /* 4a009004 */ - u32 cm_cam_iss_clkctrl; /* 4a009020 */ - u32 pad081[1]; /* 4a009024 */ - u32 cm_cam_fdif_clkctrl; /* 4a009028 */ - - /* cm2.dss */ - u32 pad082[53]; /* 4a00902c */ - u32 cm_dss_clkstctrl; /* 4a009100 */ - u32 pad083[7]; /* 4a009104 */ - u32 cm_dss_dss_clkctrl; /* 4a009120 */ - - /* cm2.sgx */ - u32 pad084[55]; /* 4a009124 */ - u32 cm_sgx_clkstctrl; /* 4a009200 */ - u32 pad085[7]; /* 4a009204 */ - u32 cm_sgx_sgx_clkctrl; /* 4a009220 */ - - /* cm2.l3init */ - u32 pad086[55]; /* 4a009224 */ - u32 cm_l3init_clkstctrl; /* 4a009300 */ - - /* cm2.l3init */ - u32 pad087[9]; /* 4a009304 */ - u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */ - u32 pad088[1]; /* 4a00932c */ - u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */ - u32 pad089[1]; /* 4a009334 */ - u32 cm_l3init_hsi_clkctrl; /* 4a009338 */ - u32 pad090[7]; /* 4a00933c */ - u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */ - u32 pad091[1]; /* 4a00935c */ - u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */ - u32 pad092[1]; /* 4a009364 */ - u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */ - u32 pad093[3]; /* 4a00936c */ - u32 cm_l3init_p1500_clkctrl; /* 4a009378 */ - u32 pad094[21]; /* 4a00937c */ - u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */ - u32 pad095[3]; /* 4a0093d4 */ - u32 cm_l3init_ocp2scp1_clkctrl; - - /* cm2.l4per */ - u32 pad096[7]; /* 4a0093e4 */ - u32 cm_l4per_clkstctrl; /* 4a009400 */ - u32 pad097[1]; /* 4a009404 */ - u32 cm_l4per_dynamicdep; /* 4a009408 */ - u32 pad098[5]; /* 4a00940c */ - u32 cm_l4per_adc_clkctrl; /* 4a009420 */ - u32 pad100[1]; /* 4a009424 */ - u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */ - u32 pad101[1]; /* 4a00942c */ - u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */ - u32 pad102[1]; /* 4a009434 */ - u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */ - u32 pad103[1]; /* 4a00943c */ - u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */ - u32 pad104[1]; /* 4a009444 */ - u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */ - u32 pad105[1]; /* 4a00944c */ - u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */ - u32 pad106[1]; /* 4a009454 */ - u32 cm_l4per_elm_clkctrl; /* 4a009458 */ - u32 pad107[1]; /* 4a00945c */ - u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */ - u32 pad108[1]; /* 4a009464 */ - u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */ - u32 pad109[1]; /* 4a00946c */ - u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */ - u32 pad110[1]; /* 4a009474 */ - u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */ - u32 pad111[1]; /* 4a00947c */ - u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */ - u32 pad112[1]; /* 4a009484 */ - u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */ - u32 pad113[1]; /* 4a00948c */ - u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */ - u32 pad114[1]; /* 4a009494 */ - u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */ - u32 pad115[1]; /* 4a00949c */ - u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */ - u32 pad116[1]; /* 4a0094a4 */ - u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */ - u32 pad117[1]; /* 4a0094ac */ - u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */ - u32 pad118[1]; /* 4a0094b4 */ - u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */ - u32 pad119[1]; /* 4a0094bc */ - u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */ - u32 pad1191[3]; /* 4a0094c4 */ - u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */ - u32 pad120[1]; /* 4a0094d4 */ - u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */ - u32 pad121[3]; /* 4a0094dc */ - u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */ - u32 pad123[1]; /* 4a0094ec */ - u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */ - u32 pad124[1]; /* 4a0094f4 */ - u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */ - u32 pad125[1]; /* 4a0094fc */ - u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */ - u32 pad126[1]; /* 4a009504 */ - u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */ - u32 pad127[1]; /* 4a00950c */ - u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */ - u32 pad1271[1]; /* 4a009514 */ - u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */ - u32 pad1272[1]; /* 4a00951c */ - u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */ - u32 pad128[1]; /* 4a009524 */ - u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */ - u32 pad129[1]; /* 4a00952c */ - u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */ - u32 pad130[1]; /* 4a009534 */ - u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */ - u32 pad131[1]; /* 4a00953c */ - u32 cm_l4per_uart1_clkctrl; /* 4a009540 */ - u32 pad132[1]; /* 4a009544 */ - u32 cm_l4per_uart2_clkctrl; /* 4a009548 */ - u32 pad133[1]; /* 4a00954c */ - u32 cm_l4per_uart3_clkctrl; /* 4a009550 */ - u32 pad134[1]; /* 4a009554 */ - u32 cm_l4per_uart4_clkctrl; /* 4a009558 */ - u32 pad135[1]; /* 4a00955c */ - u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */ - u32 pad136[1]; /* 4a009564 */ - u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */ - u32 pad1371[1]; /* 4a00956c */ - u32 cm_l4per_uart5_clkctrl; /* 4a009570 */ - u32 pad1372[1]; /* 4a009574 */ - u32 cm_l4per_uart6_clkctrl; /* 4a009578 */ - u32 pad1374[1]; /* 4a00957c */ - u32 cm_l4sec_clkstctrl; /* 4a009580 */ - u32 cm_l4sec_staticdep; /* 4a009584 */ - u32 cm_l4sec_dynamicdep; /* 4a009588 */ - u32 pad138[5]; /* 4a00958c */ - u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */ - u32 pad139[1]; /* 4a0095a4 */ - u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */ - u32 pad140[1]; /* 4a0095ac */ - u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */ - u32 pad141[1]; /* 4a0095b4 */ - u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */ - u32 pad142[1]; /* 4a0095bc */ - u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */ - u32 pad143[1]; /* 4a0095c4 */ - u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */ - u32 pad144[3]; /* 4a0095cc */ - u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */ - u32 pad145[3660425]; /* 4a0095dc */ - - /* l4 wkup regs */ - u32 pad201[6211]; /* 4ae00000 */ - u32 cm_abe_pll_ref_clksel; /* 4ae0610c */ - u32 cm_sys_clksel; /* 4ae06110 */ - u32 pad202[1467]; /* 4ae06114 */ - u32 cm_wkup_clkstctrl; /* 4ae07800 */ - u32 pad203[7]; /* 4ae07804 */ - u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */ - u32 pad204; /* 4ae07824 */ - u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */ - u32 pad205; /* 4ae0782c */ - u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */ - u32 pad206; /* 4ae07834 */ - u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */ - u32 pad207; /* 4ae0783c */ - u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */ - u32 pad208; /* 4ae07844 */ - u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */ - u32 pad209; /* 4ae0784c */ - u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */ - u32 pad210; /* 4ae07854 */ - u32 cm_wkup_usim_clkctrl; /* 4ae07858 */ - u32 pad211; /* 4ae0785c */ - u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */ - u32 pad212[5]; /* 4ae07864 */ - u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */ - u32 pad213; /* 4ae0787c */ - u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */ - u32 pad214; /* 4ae07884 */ - u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */ - u32 pad215[1]; /* 4ae0788c */ - u32 cm_wkupaon_scrm_clkctrl; /* 4ae07890 */ - u32 pad216[195]; - u32 prm_vc_val_bypass; /* 4ae07ba0 */ - u32 pad217[4]; - u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ - u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ - u32 pad218[2]; - u32 prm_sldo_core_setup; /* 4ae07bc4 */ - u32 prm_sldo_core_ctrl; /* 4ae07bc8 */ - u32 prm_sldo_mpu_setup; /* 4ae07bcc */ - u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */ - u32 prm_sldo_mm_setup; /* 4ae07bd4 */ - u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */ -}; - /* DPLL register offsets */ #define CM_CLKMODE_DPLL 0 #define CM_IDLEST_DPLL 0x4 @@ -715,7 +266,6 @@ struct dpll_params { s8 h23; }; -extern struct omap5_prcm_regs *const prcm; extern const u32 sys_clk_array[8]; void scale_vcores(void); @@ -723,14 +273,14 @@ void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); u32 get_offset_code(u32 offset); u32 omap_ddr_clk(void); void do_scale_vcore(u32 vcore_reg, u32 volt_mv); -void setup_post_dividers(u32 *const base, const struct dpll_params *params); +void setup_post_dividers(u32 const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_non_essential_clocks(void); void enable_basic_uboot_clocks(void); -void do_enable_clocks(u32 *const *clk_domains, - u32 *const *clk_modules_hw_auto, - u32 *const *clk_modules_explicit_en, +void do_enable_clocks(u32 const *clk_domains, + u32 const *clk_modules_hw_auto, + u32 const *clk_modules_explicit_en, u8 wait_for_enable); const struct dpll_params *get_mpu_dpll_params(void); const struct dpll_params *get_core_dpll_params(void); diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 9dce49a..50e055e 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -271,7 +271,8 @@ struct omap_sys_ctrl_regs { #define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) +#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x18) /* Silicon revisions */ #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 72e9df7..2b3a071 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -44,7 +44,7 @@ u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void setup_clocks_for_console(void); void prcm_init(void); -void bypass_dpll(u32 *const base); +void bypass_dpll(u32 const base); void freq_update_core(void); u32 get_sys_clk_freq(void); u32 omap5_ddr_clk(void); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2a40b89..fcf9ce5 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -25,6 +25,310 @@ #ifndef _OMAP_COMMON_H_ #define _OMAP_COMMON_H_ +#include + +struct prcm_regs { + /* cm1.ckgen */ + u32 cm_clksel_core; + u32 cm_clksel_abe; + u32 cm_dll_ctrl; + u32 cm_clkmode_dpll_core; + u32 cm_idlest_dpll_core; + u32 cm_autoidle_dpll_core; + u32 cm_clksel_dpll_core; + u32 cm_div_m2_dpll_core; + u32 cm_div_m3_dpll_core; + u32 cm_div_h11_dpll_core; + u32 cm_div_h12_dpll_core; + u32 cm_div_h13_dpll_core; + u32 cm_div_h14_dpll_core; + u32 cm_ssc_deltamstep_dpll_core; + u32 cm_ssc_modfreqdiv_dpll_core; + u32 cm_emu_override_dpll_core; + u32 cm_div_h22_dpllcore; + u32 cm_div_h23_dpll_core; + u32 cm_clkmode_dpll_mpu; + u32 cm_idlest_dpll_mpu; + u32 cm_autoidle_dpll_mpu; + u32 cm_clksel_dpll_mpu; + u32 cm_div_m2_dpll_mpu; + u32 cm_ssc_deltamstep_dpll_mpu; + u32 cm_ssc_modfreqdiv_dpll_mpu; + u32 cm_bypclk_dpll_mpu; + u32 cm_clkmode_dpll_iva; + u32 cm_idlest_dpll_iva; + u32 cm_autoidle_dpll_iva; + u32 cm_clksel_dpll_iva; + u32 cm_div_h11_dpll_iva; + u32 cm_div_h12_dpll_iva; + u32 cm_ssc_deltamstep_dpll_iva; + u32 cm_ssc_modfreqdiv_dpll_iva; + u32 cm_bypclk_dpll_iva; + u32 cm_clkmode_dpll_abe; + u32 cm_idlest_dpll_abe; + u32 cm_autoidle_dpll_abe; + u32 cm_clksel_dpll_abe; + u32 cm_div_m2_dpll_abe; + u32 cm_div_m3_dpll_abe; + u32 cm_ssc_deltamstep_dpll_abe; + u32 cm_ssc_modfreqdiv_dpll_abe; + u32 cm_clkmode_dpll_ddrphy; + u32 cm_idlest_dpll_ddrphy; + u32 cm_autoidle_dpll_ddrphy; + u32 cm_clksel_dpll_ddrphy; + u32 cm_div_m2_dpll_ddrphy; + u32 cm_div_h11_dpll_ddrphy; + u32 cm_div_h12_dpll_ddrphy; + u32 cm_div_h13_dpll_ddrphy; + u32 cm_ssc_deltamstep_dpll_ddrphy; + u32 cm_shadow_freq_config1; + u32 cm_mpu_mpu_clkctrl; + + /* cm1.dsp */ + u32 cm_dsp_clkstctrl; + u32 cm_dsp_dsp_clkctrl; + + /* cm1.abe */ + u32 cm1_abe_clkstctrl; + u32 cm1_abe_l4abe_clkctrl; + u32 cm1_abe_aess_clkctrl; + u32 cm1_abe_pdm_clkctrl; + u32 cm1_abe_dmic_clkctrl; + u32 cm1_abe_mcasp_clkctrl; + u32 cm1_abe_mcbsp1_clkctrl; + u32 cm1_abe_mcbsp2_clkctrl; + u32 cm1_abe_mcbsp3_clkctrl; + u32 cm1_abe_slimbus_clkctrl; + u32 cm1_abe_timer5_clkctrl; + u32 cm1_abe_timer6_clkctrl; + u32 cm1_abe_timer7_clkctrl; + u32 cm1_abe_timer8_clkctrl; + u32 cm1_abe_wdt3_clkctrl; + + /* cm2.ckgen */ + u32 cm_clksel_mpu_m3_iss_root; + u32 cm_clksel_usb_60mhz; + u32 cm_scale_fclk; + u32 cm_core_dvfs_perf1; + u32 cm_core_dvfs_perf2; + u32 cm_core_dvfs_perf3; + u32 cm_core_dvfs_perf4; + u32 cm_core_dvfs_current; + u32 cm_iva_dvfs_perf_tesla; + u32 cm_iva_dvfs_perf_ivahd; + u32 cm_iva_dvfs_perf_abe; + u32 cm_iva_dvfs_current; + u32 cm_clkmode_dpll_per; + u32 cm_idlest_dpll_per; + u32 cm_autoidle_dpll_per; + u32 cm_clksel_dpll_per; + u32 cm_div_m2_dpll_per; + u32 cm_div_m3_dpll_per; + u32 cm_div_h11_dpll_per; + u32 cm_div_h12_dpll_per; + u32 cm_div_h14_dpll_per; + u32 cm_ssc_deltamstep_dpll_per; + u32 cm_ssc_modfreqdiv_dpll_per; + u32 cm_emu_override_dpll_per; + u32 cm_clkmode_dpll_usb; + u32 cm_idlest_dpll_usb; + u32 cm_autoidle_dpll_usb; + u32 cm_clksel_dpll_usb; + u32 cm_div_m2_dpll_usb; + u32 cm_ssc_deltamstep_dpll_usb; + u32 cm_ssc_modfreqdiv_dpll_usb; + u32 cm_clkdcoldo_dpll_usb; + u32 cm_clkmode_dpll_unipro; + u32 cm_idlest_dpll_unipro; + u32 cm_autoidle_dpll_unipro; + u32 cm_clksel_dpll_unipro; + u32 cm_div_m2_dpll_unipro; + u32 cm_ssc_deltamstep_dpll_unipro; + u32 cm_ssc_modfreqdiv_dpll_unipro; + + /* cm2.core */ + u32 cm_coreaon_bandgap_clkctrl; + u32 cm_l3_1_clkstctrl; + u32 cm_l3_1_dynamicdep; + u32 cm_l3_1_l3_1_clkctrl; + u32 cm_l3_2_clkstctrl; + u32 cm_l3_2_dynamicdep; + u32 cm_l3_2_l3_2_clkctrl; + u32 cm_l3_2_gpmc_clkctrl; + u32 cm_l3_2_ocmc_ram_clkctrl; + u32 cm_mpu_m3_clkstctrl; + u32 cm_mpu_m3_staticdep; + u32 cm_mpu_m3_dynamicdep; + u32 cm_mpu_m3_mpu_m3_clkctrl; + u32 cm_sdma_clkstctrl; + u32 cm_sdma_staticdep; + u32 cm_sdma_dynamicdep; + u32 cm_sdma_sdma_clkctrl; + u32 cm_memif_clkstctrl; + u32 cm_memif_dmm_clkctrl; + u32 cm_memif_emif_fw_clkctrl; + u32 cm_memif_emif_1_clkctrl; + u32 cm_memif_emif_2_clkctrl; + u32 cm_memif_dll_clkctrl; + u32 cm_memif_emif_h1_clkctrl; + u32 cm_memif_emif_h2_clkctrl; + u32 cm_memif_dll_h_clkctrl; + u32 cm_c2c_clkstctrl; + u32 cm_c2c_staticdep; + u32 cm_c2c_dynamicdep; + u32 cm_c2c_sad2d_clkctrl; + u32 cm_c2c_modem_icr_clkctrl; + u32 cm_c2c_sad2d_fw_clkctrl; + u32 cm_l4cfg_clkstctrl; + u32 cm_l4cfg_dynamicdep; + u32 cm_l4cfg_l4_cfg_clkctrl; + u32 cm_l4cfg_hw_sem_clkctrl; + u32 cm_l4cfg_mailbox_clkctrl; + u32 cm_l4cfg_sar_rom_clkctrl; + u32 cm_l3instr_clkstctrl; + u32 cm_l3instr_l3_3_clkctrl; + u32 cm_l3instr_l3_instr_clkctrl; + u32 cm_l3instr_intrconn_wp1_clkctrl; + + /* cm2.ivahd */ + u32 cm_ivahd_clkstctrl; + u32 cm_ivahd_ivahd_clkctrl; + u32 cm_ivahd_sl2_clkctrl; + + /* cm2.cam */ + u32 cm_cam_clkstctrl; + u32 cm_cam_iss_clkctrl; + u32 cm_cam_fdif_clkctrl; + + /* cm2.dss */ + u32 cm_dss_clkstctrl; + u32 cm_dss_dss_clkctrl; + + /* cm2.sgx */ + u32 cm_sgx_clkstctrl; + u32 cm_sgx_sgx_clkctrl; + + /* cm2.l3init */ + u32 cm_l3init_clkstctrl; + + /* cm2.l3init */ + u32 cm_l3init_hsmmc1_clkctrl; + u32 cm_l3init_hsmmc2_clkctrl; + u32 cm_l3init_hsi_clkctrl; + u32 cm_l3init_hsusbhost_clkctrl; + u32 cm_l3init_hsusbotg_clkctrl; + u32 cm_l3init_hsusbtll_clkctrl; + u32 cm_l3init_p1500_clkctrl; + u32 cm_l3init_fsusb_clkctrl; + u32 cm_l3init_ocp2scp1_clkctrl; + + /* cm2.l4per */ + u32 cm_l4per_clkstctrl; + u32 cm_l4per_dynamicdep; + u32 cm_l4per_adc_clkctrl; + u32 cm_l4per_gptimer10_clkctrl; + u32 cm_l4per_gptimer11_clkctrl; + u32 cm_l4per_gptimer2_clkctrl; + u32 cm_l4per_gptimer3_clkctrl; + u32 cm_l4per_gptimer4_clkctrl; + u32 cm_l4per_gptimer9_clkctrl; + u32 cm_l4per_elm_clkctrl; + u32 cm_l4per_gpio2_clkctrl; + u32 cm_l4per_gpio3_clkctrl; + u32 cm_l4per_gpio4_clkctrl; + u32 cm_l4per_gpio5_clkctrl; + u32 cm_l4per_gpio6_clkctrl; + u32 cm_l4per_hdq1w_clkctrl; + u32 cm_l4per_hecc1_clkctrl; + u32 cm_l4per_hecc2_clkctrl; + u32 cm_l4per_i2c1_clkctrl; + u32 cm_l4per_i2c2_clkctrl; + u32 cm_l4per_i2c3_clkctrl; + u32 cm_l4per_i2c4_clkctrl; + u32 cm_l4per_l4per_clkctrl; + u32 cm_l4per_mcasp2_clkctrl; + u32 cm_l4per_mcasp3_clkctrl; + u32 cm_l4per_mgate_clkctrl; + u32 cm_l4per_mcspi1_clkctrl; + u32 cm_l4per_mcspi2_clkctrl; + u32 cm_l4per_mcspi3_clkctrl; + u32 cm_l4per_mcspi4_clkctrl; + u32 cm_l4per_gpio7_clkctrl; + u32 cm_l4per_gpio8_clkctrl; + u32 cm_l4per_mmcsd3_clkctrl; + u32 cm_l4per_mmcsd4_clkctrl; + u32 cm_l4per_msprohg_clkctrl; + u32 cm_l4per_slimbus2_clkctrl; + u32 cm_l4per_uart1_clkctrl; + u32 cm_l4per_uart2_clkctrl; + u32 cm_l4per_uart3_clkctrl; + u32 cm_l4per_uart4_clkctrl; + u32 cm_l4per_mmcsd5_clkctrl; + u32 cm_l4per_i2c5_clkctrl; + u32 cm_l4per_uart5_clkctrl; + u32 cm_l4per_uart6_clkctrl; + u32 cm_l4sec_clkstctrl; + u32 cm_l4sec_staticdep; + u32 cm_l4sec_dynamicdep; + u32 cm_l4sec_aes1_clkctrl; + u32 cm_l4sec_aes2_clkctrl; + u32 cm_l4sec_des3des_clkctrl; + u32 cm_l4sec_pkaeip29_clkctrl; + u32 cm_l4sec_rng_clkctrl; + u32 cm_l4sec_sha2md51_clkctrl; + u32 cm_l4sec_cryptodma_clkctrl; + + /* l4 wkup regs */ + u32 cm_abe_pll_ref_clksel; + u32 cm_sys_clksel; + u32 cm_wkup_clkstctrl; + u32 cm_wkup_l4wkup_clkctrl; + u32 cm_wkup_wdtimer1_clkctrl; + u32 cm_wkup_wdtimer2_clkctrl; + u32 cm_wkup_gpio1_clkctrl; + u32 cm_wkup_gptimer1_clkctrl; + u32 cm_wkup_gptimer12_clkctrl; + u32 cm_wkup_synctimer_clkctrl; + u32 cm_wkup_usim_clkctrl; + u32 cm_wkup_sarram_clkctrl; + u32 cm_wkup_keyboard_clkctrl; + u32 cm_wkup_rtc_clkctrl; + u32 cm_wkup_bandgap_clkctrl; + u32 cm_wkupaon_scrm_clkctrl; + u32 prm_vc_val_bypass; + u32 prm_vc_cfg_i2c_mode; + u32 prm_vc_cfg_i2c_clk; + u32 prm_sldo_core_setup; + u32 prm_sldo_core_ctrl; + u32 prm_sldo_mpu_setup; + u32 prm_sldo_mpu_ctrl; + u32 prm_sldo_mm_setup; + u32 prm_sldo_mm_ctrl; + + u32 cm_div_m4_dpll_core; + u32 cm_div_m5_dpll_core; + u32 cm_div_m6_dpll_core; + u32 cm_div_m7_dpll_core; + u32 cm_div_m4_dpll_iva; + u32 cm_div_m5_dpll_iva; + u32 cm_div_m4_dpll_ddrphy; + u32 cm_div_m5_dpll_ddrphy; + u32 cm_div_m6_dpll_ddrphy; + u32 cm_div_m4_dpll_per; + u32 cm_div_m5_dpll_per; + u32 cm_div_m6_dpll_per; + u32 cm_div_m7_dpll_per; + u32 cm_l3instr_intrconn_wp1_clkct; + u32 cm_l3init_usbphy_clkctrl; + u32 cm_l4per_mcbsp4_clkctrl; + u32 prm_vc_cfg_channel; +}; + +extern struct prcm_regs const **prcm; +extern struct prcm_regs const omap5_es1_prcm; +extern struct prcm_regs const omap4_prcm; + +void hw_data_init(void); /* Max value for DPLL multiplier M */ #define OMAP_DPLL_MAX_N 127 -- cgit v0.10.2 From ee9447bfe37a646a8dce182e6f625f27c10512a0 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Mon, 4 Feb 2013 04:22:01 +0000 Subject: ARM: OMAP4+: Cleanup the clocks layer Currently there is quite a lot of code which is duplicated in the clocks code for OMAP 4 and 5 Socs. Avoiding this here by moving the clocks data to a SOC specific place and the sharing the common code. This helps in addition of a new Soc with minimal changes. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index d36fccc..2becc4a 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -47,6 +47,16 @@ #define puts(s) #endif +const u32 sys_clk_array[8] = { + 12000000, /* 12 MHz */ + 13000000, /* 13 MHz */ + 16800000, /* 16.8 MHz */ + 19200000, /* 19.2 MHz */ + 26000000, /* 26 MHz */ + 27000000, /* 27 MHz */ + 38400000, /* 38.4 MHz */ +}; + static inline u32 __get_sys_clk_index(void) { u32 ind; @@ -76,6 +86,29 @@ u32 get_sys_clk_freq(void) return sys_clk_array[index]; } +void setup_post_dividers(u32 const base, const struct dpll_params *params) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, &dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, &dpll_regs->cm_div_m3_dpll); + if (params->m4_h11 >= 0) + writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll); + if (params->m5_h12 >= 0) + writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll); + if (params->m6_h13 >= 0) + writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); + if (params->m7_h14 >= 0) + writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll); + if (params->h22 >= 0) + writel(params->h22, &dpll_regs->cm_div_h22_dpll); + if (params->h23 >= 0) + writel(params->h23, &dpll_regs->cm_div_h23_dpll); +} + static inline void do_bypass_dpll(u32 const base) { struct dpll_regs *dpll_regs = (struct dpll_regs *)base; @@ -124,6 +157,46 @@ inline u32 check_for_lock(u32 const base) return lock; } +const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->mpu[sysclk_ind]; +} + +const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->core[sysclk_ind]; +} + +const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->per[sysclk_ind]; +} + +const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->iva[sysclk_ind]; +} + +const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->usb[sysclk_ind]; +} + +const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data) +{ +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->abe[sysclk_ind]; +#else + return dpll_data->abe; +#endif +} + static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { @@ -184,7 +257,7 @@ u32 omap_ddr_clk(void) omap_rev = omap_revision(); sys_clk_khz = get_sys_clk_freq() / 1000; - core_dpll_params = get_core_dpll_params(); + core_dpll_params = get_core_dpll_params(*dplls_data); debug("sys_clk %d\n ", sys_clk_khz * 1000); @@ -251,7 +324,7 @@ void configure_mpu_dpll(void) setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); - params = get_mpu_dpll_params(); + params = get_mpu_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); debug("MPU DPLL locked\n"); @@ -272,7 +345,7 @@ static void setup_usb_dpll(void) * Use CLKINP in KHz and adjust the denominator accordingly so * that we have enough accuracy and at the same time no overflow */ - params = get_usb_dpll_params(); + params = get_usb_dpll_params(*dplls_data); num = params->m * sys_clk_khz; den = (params->n + 1) * 250 * 1000; num += den - 1; @@ -294,7 +367,7 @@ static void setup_dplls(void) debug("setup_dplls\n"); /* CORE dpll */ - params = get_core_dpll_params(); /* default - safest */ + params = get_core_dpll_params(*dplls_data); /* default - safest */ /* * Do not lock the core DPLL now. Just set it up. * Core DPLL will be locked after setting up EMIF @@ -314,7 +387,7 @@ static void setup_dplls(void) debug("Core DPLL configured\n"); /* lock PER dpll */ - params = get_per_dpll_params(); + params = get_per_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_per, params, DPLL_LOCK, "per"); debug("PER DPLL locked\n"); @@ -337,11 +410,11 @@ static void setup_non_essential_dplls(void) clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva, CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); - params = get_iva_dpll_params(); + params = get_iva_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); /* Configure ABE dpll */ - params = get_abe_dpll_params(); + params = get_abe_dpll_params(*dplls_data); #ifdef CONFIG_SYS_OMAP_ABE_SYSCK abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; #else @@ -459,7 +532,7 @@ void freq_update_core(void) const struct dpll_params *core_dpll_params; u32 omap_rev = omap_revision(); - core_dpll_params = get_core_dpll_params(); + core_dpll_params = get_core_dpll_params(*dplls_data); /* Put EMIF clock domain in sw wakeup mode */ enable_clock_domain((*prcm)->cm_memif_clkstctrl, CD_CLKCTRL_CLKTRCTRL_SW_WKUP); diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 9acceb0..4772743 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -46,221 +46,6 @@ #define puts(s) #endif /* !CONFIG_SPL_BUILD */ -const u32 sys_clk_array[8] = { - 12000000, /* 12 MHz */ - 13000000, /* 13 MHz */ - 16800000, /* 16.8 MHz */ - 19200000, /* 19.2 MHz */ - 26000000, /* 26 MHz */ - 27000000, /* 27 MHz */ - 38400000, /* 38.4 MHz */ -}; - -/* - * The M & N values in the following tables are created using the - * following tool: - * tools/omap/clocks_get_m_n.c - * Please use this tool for creating the table for any new frequency. - */ - -/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */ -static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { - {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */ -static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* dpll locked at 1200 MHz - MPU clk at 600 MHz */ -static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { - {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ - {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ - {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ - {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ - {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ -}; - -static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { - {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ - {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ - {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ - {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ - {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { - {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */ - {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */ - {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */ - {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */ - {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */ -}; - -static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { - {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */ - {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */ - {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */ - {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */ - {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */ - {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */ - {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */ -}; - -static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { - {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ - {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ - {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ - {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ - {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ - {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ - {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with sys_clk as source */ -static const struct dpll_params - abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ - {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ - {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with 32K clock as source */ -static const struct dpll_params abe_dpll_params_32k_196608khz = { - 750, 0, 1, 1, -1, -1, -1, -1 -}; - -static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ - {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ - {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ - {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -void setup_post_dividers(u32 const base, const struct dpll_params *params) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - /* Setup post-dividers */ - if (params->m2 >= 0) - writel(params->m2, &dpll_regs->cm_div_m2_dpll); - if (params->m3 >= 0) - writel(params->m3, &dpll_regs->cm_div_m3_dpll); - if (params->m4 >= 0) - writel(params->m4, &dpll_regs->cm_div_m4_dpll); - if (params->m5 >= 0) - writel(params->m5, &dpll_regs->cm_div_m5_dpll); - if (params->m6 >= 0) - writel(params->m6, &dpll_regs->cm_div_m6_dpll); - if (params->m7 >= 0) - writel(params->m7, &dpll_regs->cm_div_m7_dpll); -} - -/* - * Lock MPU dpll - * - * Resulting MPU frequencies: - * 4430 ES1.0 : 600 MHz - * 4430 ES2.x : 792 MHz (OPP Turbo) - * 4460 : 920 MHz (OPP Turbo) - DCC disabled - */ -const struct dpll_params *get_mpu_dpll_params(void) -{ - u32 omap_rev, sysclk_ind; - - omap_rev = omap_revision(); - sysclk_ind = get_sys_clk_index(); - - if (omap_rev == OMAP4430_ES1_0) - return &mpu_dpll_params_1200mhz[sysclk_ind]; - else if (omap_rev < OMAP4460_ES1_0) - return &mpu_dpll_params_1600mhz[sysclk_ind]; - else - return &mpu_dpll_params_1400mhz[sysclk_ind]; -} - -const struct dpll_params *get_core_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - - switch (omap_revision()) { - case OMAP4430_ES1_0: - return &core_dpll_params_es1_1524mhz[sysclk_ind]; - case OMAP4430_ES2_0: - case OMAP4430_SILICON_ID_INVALID: - /* safest */ - return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind]; - default: - return &core_dpll_params_1600mhz[sysclk_ind]; - } -} - - -const struct dpll_params *get_per_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &per_dpll_params_1536mhz[sysclk_ind]; -} - -const struct dpll_params *get_iva_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &iva_dpll_params_1862mhz[sysclk_ind]; -} - -const struct dpll_params *get_usb_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &usb_dpll_params_1920mhz[sysclk_ind]; -} - -const struct dpll_params *get_abe_dpll_params(void) -{ -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - u32 sysclk_ind = get_sys_clk_index(); - return &abe_dpll_params_sysclk_196608khz[sysclk_ind]; -#else - return &abe_dpll_params_32k_196608khz; -#endif -} - /* * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva * We set the maximum voltages allowed here because Smart-Reflex is not @@ -336,181 +121,3 @@ u32 get_offset_code(u32 offset) /* The code starts at 1 not 0 */ return ++offset_code; } - -/* - * Enable essential clock domains, modules and - * do some additional special settings needed - */ -void enable_basic_clocks(void) -{ - u32 const clk_domains_essential[] = { - (*prcm)->cm_l4per_clkstctrl, - (*prcm)->cm_l3init_clkstctrl, - (*prcm)->cm_memif_clkstctrl, - (*prcm)->cm_l4cfg_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_essential[] = { - (*prcm)->cm_l3_2_gpmc_clkctrl, - (*prcm)->cm_memif_emif_1_clkctrl, - (*prcm)->cm_memif_emif_2_clkctrl, - (*prcm)->cm_l4cfg_l4_cfg_clkctrl, - (*prcm)->cm_wkup_gpio1_clkctrl, - (*prcm)->cm_l4per_gpio2_clkctrl, - (*prcm)->cm_l4per_gpio3_clkctrl, - (*prcm)->cm_l4per_gpio4_clkctrl, - (*prcm)->cm_l4per_gpio5_clkctrl, - (*prcm)->cm_l4per_gpio6_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_essential[] = { - (*prcm)->cm_wkup_gptimer1_clkctrl, - (*prcm)->cm_l3init_hsmmc1_clkctrl, - (*prcm)->cm_l3init_hsmmc2_clkctrl, - (*prcm)->cm_l4per_gptimer2_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_l4per_uart3_clkctrl, - 0 - }; - - /* Enable optional additional functional clock for GPIO4 */ - setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, - GPIO4_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable 96 MHz clock for MMC1 & MMC2 */ - setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - - /* Select 32KHz clock as the source of GPTIMER1 */ - setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, - GPTIMER1_CLKCTRL_CLKSEL_MASK); - - /* Enable optional 48M functional clock for USB PHY */ - setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, - USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); -} - -void enable_basic_uboot_clocks(void) -{ - u32 const clk_domains_essential[] = { - 0 - }; - - u32 const clk_modules_hw_auto_essential[] = { - (*prcm)->cm_l3init_hsusbotg_clkctrl, - (*prcm)->cm_l3init_usbphy_clkctrl, - (*prcm)->cm_l3init_usbphy_clkctrl, - (*prcm)->cm_clksel_usb_60mhz, - (*prcm)->cm_l3init_hsusbtll_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_essential[] = { - (*prcm)->cm_l4per_mcspi1_clkctrl, - (*prcm)->cm_l4per_i2c1_clkctrl, - (*prcm)->cm_l4per_i2c2_clkctrl, - (*prcm)->cm_l4per_i2c3_clkctrl, - (*prcm)->cm_l4per_i2c4_clkctrl, - (*prcm)->cm_l3init_hsusbhost_clkctrl, - 0 - }; - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); -} - -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 const clk_domains_non_essential[] = { - (*prcm)->cm_mpu_m3_clkstctrl, - (*prcm)->cm_ivahd_clkstctrl, - (*prcm)->cm_dsp_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sgx_clkstctrl, - (*prcm)->cm1_abe_clkstctrl, - (*prcm)->cm_c2c_clkstctrl, - (*prcm)->cm_cam_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sdma_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_non_essential[] = { - (*prcm)->cm_l3instr_l3_3_clkctrl, - (*prcm)->cm_l3instr_l3_instr_clkctrl, - (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, - (*prcm)->cm_l3init_hsi_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_non_essential[] = { - (*prcm)->cm1_abe_aess_clkctrl, - (*prcm)->cm1_abe_pdm_clkctrl, - (*prcm)->cm1_abe_dmic_clkctrl, - (*prcm)->cm1_abe_mcasp_clkctrl, - (*prcm)->cm1_abe_mcbsp1_clkctrl, - (*prcm)->cm1_abe_mcbsp2_clkctrl, - (*prcm)->cm1_abe_mcbsp3_clkctrl, - (*prcm)->cm1_abe_slimbus_clkctrl, - (*prcm)->cm1_abe_timer5_clkctrl, - (*prcm)->cm1_abe_timer6_clkctrl, - (*prcm)->cm1_abe_timer7_clkctrl, - (*prcm)->cm1_abe_timer8_clkctrl, - (*prcm)->cm1_abe_wdt3_clkctrl, - (*prcm)->cm_l4per_gptimer9_clkctrl, - (*prcm)->cm_l4per_gptimer10_clkctrl, - (*prcm)->cm_l4per_gptimer11_clkctrl, - (*prcm)->cm_l4per_gptimer3_clkctrl, - (*prcm)->cm_l4per_gptimer4_clkctrl, - (*prcm)->cm_l4per_hdq1w_clkctrl, - (*prcm)->cm_l4per_mcbsp4_clkctrl, - (*prcm)->cm_l4per_mcspi2_clkctrl, - (*prcm)->cm_l4per_mcspi3_clkctrl, - (*prcm)->cm_l4per_mcspi4_clkctrl, - (*prcm)->cm_l4per_mmcsd3_clkctrl, - (*prcm)->cm_l4per_mmcsd4_clkctrl, - (*prcm)->cm_l4per_mmcsd5_clkctrl, - (*prcm)->cm_l4per_uart1_clkctrl, - (*prcm)->cm_l4per_uart2_clkctrl, - (*prcm)->cm_l4per_uart4_clkctrl, - (*prcm)->cm_wkup_keyboard_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_cam_iss_clkctrl, - (*prcm)->cm_cam_fdif_clkctrl, - (*prcm)->cm_dss_dss_clkctrl, - (*prcm)->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32((*prcm)->cm_cam_clkstctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 3174cc3..6ae3986 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -27,12 +27,377 @@ */ #include #include +#include #include +#include +#include struct prcm_regs const **prcm = (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; +struct dplls const **dplls_data = + (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; + +/* + * The M & N values in the following tables are created using the + * following tool: + * tools/omap/clocks_get_m_n.c + * Please use this tool for creating the table for any new frequency. + */ + +/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */ +static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { + {175, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {638, 34, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */ +static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* dpll locked at 1200 MHz - MPU clk at 600 MHz */ +static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { + {50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {250, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 3, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {200, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { + {127, 1, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { + {200, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { + {64, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 12 MHz */ + {768, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 13 MHz */ + {320, 6, 8, 6, 12, 9, 4, 5, -1, -1}, /* 16.8 MHz */ + {40, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 19.2 MHz */ + {384, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 26 MHz */ + {256, 8, 8, 6, 12, 9, 4, 5, -1, -1}, /* 27 MHz */ + {20, 0, 8, 6, 12, 9, 4, 5, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { + {931, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1, -1, -1}, /* 27 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with sys_clk as source */ +static const struct dpll_params + abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { + {49, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {68, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {29, 7, 1, 1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1 +}; + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {80, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +struct dplls omap4430_dplls_es1 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es1_1524mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz +}; + +struct dplls omap4430_dplls = { + .mpu = mpu_dpll_params_1600mhz, + .core = core_dpll_params_es2_1600mhz_ddr200mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz +}; + +struct dplls omap4460_dplls = { + .mpu = mpu_dpll_params_1400mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz +}; + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +void enable_basic_clocks(void) +{ + u32 const clk_domains_essential[] = { + (*prcm)->cm_l4per_clkstctrl, + (*prcm)->cm_l3init_clkstctrl, + (*prcm)->cm_memif_clkstctrl, + (*prcm)->cm_l4cfg_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3_2_gpmc_clkctrl, + (*prcm)->cm_memif_emif_1_clkctrl, + (*prcm)->cm_memif_emif_2_clkctrl, + (*prcm)->cm_l4cfg_l4_cfg_clkctrl, + (*prcm)->cm_wkup_gpio1_clkctrl, + (*prcm)->cm_l4per_gpio2_clkctrl, + (*prcm)->cm_l4per_gpio3_clkctrl, + (*prcm)->cm_l4per_gpio4_clkctrl, + (*prcm)->cm_l4per_gpio5_clkctrl, + (*prcm)->cm_l4per_gpio6_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_wkup_gptimer1_clkctrl, + (*prcm)->cm_l3init_hsmmc1_clkctrl, + (*prcm)->cm_l3init_hsmmc2_clkctrl, + (*prcm)->cm_l4per_gptimer2_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart3_clkctrl, + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, + GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, + GPTIMER1_CLKCTRL_CLKSEL_MASK); + + /* Enable optional 48M functional clock for USB PHY */ + setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, + USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +void enable_basic_uboot_clocks(void) +{ + u32 const clk_domains_essential[] = { + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3init_hsusbotg_clkctrl, + (*prcm)->cm_l3init_usbphy_clkctrl, + (*prcm)->cm_l3init_usbphy_clkctrl, + (*prcm)->cm_clksel_usb_60mhz, + (*prcm)->cm_l3init_hsusbtll_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_l4per_mcspi1_clkctrl, + (*prcm)->cm_l4per_i2c1_clkctrl, + (*prcm)->cm_l4per_i2c2_clkctrl, + (*prcm)->cm_l4per_i2c3_clkctrl, + (*prcm)->cm_l4per_i2c4_clkctrl, + (*prcm)->cm_l3init_hsusbhost_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +/* + * Enable non-essential clock domains, modules and + * do some additional special settings needed + */ +void enable_non_essential_clocks(void) +{ + u32 const clk_domains_non_essential[] = { + (*prcm)->cm_mpu_m3_clkstctrl, + (*prcm)->cm_ivahd_clkstctrl, + (*prcm)->cm_dsp_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sgx_clkstctrl, + (*prcm)->cm1_abe_clkstctrl, + (*prcm)->cm_c2c_clkstctrl, + (*prcm)->cm_cam_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sdma_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_non_essential[] = { + (*prcm)->cm_l3instr_l3_3_clkctrl, + (*prcm)->cm_l3instr_l3_instr_clkctrl, + (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, + (*prcm)->cm_l3init_hsi_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_non_essential[] = { + (*prcm)->cm1_abe_aess_clkctrl, + (*prcm)->cm1_abe_pdm_clkctrl, + (*prcm)->cm1_abe_dmic_clkctrl, + (*prcm)->cm1_abe_mcasp_clkctrl, + (*prcm)->cm1_abe_mcbsp1_clkctrl, + (*prcm)->cm1_abe_mcbsp2_clkctrl, + (*prcm)->cm1_abe_mcbsp3_clkctrl, + (*prcm)->cm1_abe_slimbus_clkctrl, + (*prcm)->cm1_abe_timer5_clkctrl, + (*prcm)->cm1_abe_timer6_clkctrl, + (*prcm)->cm1_abe_timer7_clkctrl, + (*prcm)->cm1_abe_timer8_clkctrl, + (*prcm)->cm1_abe_wdt3_clkctrl, + (*prcm)->cm_l4per_gptimer9_clkctrl, + (*prcm)->cm_l4per_gptimer10_clkctrl, + (*prcm)->cm_l4per_gptimer11_clkctrl, + (*prcm)->cm_l4per_gptimer3_clkctrl, + (*prcm)->cm_l4per_gptimer4_clkctrl, + (*prcm)->cm_l4per_hdq1w_clkctrl, + (*prcm)->cm_l4per_mcbsp4_clkctrl, + (*prcm)->cm_l4per_mcspi2_clkctrl, + (*prcm)->cm_l4per_mcspi3_clkctrl, + (*prcm)->cm_l4per_mcspi4_clkctrl, + (*prcm)->cm_l4per_mmcsd3_clkctrl, + (*prcm)->cm_l4per_mmcsd4_clkctrl, + (*prcm)->cm_l4per_mmcsd5_clkctrl, + (*prcm)->cm_l4per_uart1_clkctrl, + (*prcm)->cm_l4per_uart2_clkctrl, + (*prcm)->cm_l4per_uart4_clkctrl, + (*prcm)->cm_wkup_keyboard_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_cam_iss_clkctrl, + (*prcm)->cm_cam_fdif_clkctrl, + (*prcm)->cm_dss_dss_clkctrl, + (*prcm)->cm_sgx_sgx_clkctrl, + 0 + }; + + /* Enable optional functional clock for ISS */ + setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable all optional functional clocks of DSS */ + setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); + + do_enable_clocks(clk_domains_non_essential, + clk_modules_hw_auto_non_essential, + clk_modules_explicit_en_non_essential, + 0); + + /* Put camera module in no sleep mode */ + clrsetbits_le32((*prcm)->cm_cam_clkstctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} void hw_data_init(void) { - *prcm = &omap4_prcm; + u32 omap_rev = omap_revision(); + + (*prcm) = &omap4_prcm; + + switch (omap_rev) { + + case OMAP4430_ES1_0: + *dplls_data = &omap4430_dplls_es1; + break; + + case OMAP4430_ES2_0: + case OMAP4430_ES2_1: + case OMAP4430_ES2_2: + case OMAP4430_ES2_3: + *dplls_data = &omap4430_dplls; + break; + + case OMAP4460_ES1_0: + case OMAP4460_ES1_1: + *dplls_data = &omap4460_dplls; + break; + + default: + printf("\n INVALID OMAP REVISION "); + } + } diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index a90f922..da5b3ac 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -47,210 +47,6 @@ #define puts(s) #endif -const u32 sys_clk_array[8] = { - 12000000, /* 12 MHz */ - 0, /* NA */ - 16800000, /* 16.8 MHz */ - 19200000, /* 19.2 MHz */ - 26000000, /* 26 MHz */ - 0, /* NA */ - 38400000, /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { - {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = { - {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { - {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { - {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { - {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = { - {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { - {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ - {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ - {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { - {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */ - {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */ - {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */ -}; - -static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { - {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { - {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */ - {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */ - {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with sys_clk as source */ -static const struct dpll_params - abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with 32K clock as source */ -static const struct dpll_params abe_dpll_params_32k_196608khz = { - 750, 0, 1, 1, -1, -1, -1, -1, -1, -1 -}; - -static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -void setup_post_dividers(u32 const base, const struct dpll_params *params) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - /* Setup post-dividers */ - if (params->m2 >= 0) - writel(params->m2, &dpll_regs->cm_div_m2_dpll); - if (params->m3 >= 0) - writel(params->m3, &dpll_regs->cm_div_m3_dpll); - if (params->h11 >= 0) - writel(params->h11, &dpll_regs->cm_div_h11_dpll); - if (params->h12 >= 0) - writel(params->h12, &dpll_regs->cm_div_h12_dpll); - if (params->h13 >= 0) - writel(params->h13, &dpll_regs->cm_div_h13_dpll); - if (params->h14 >= 0) - writel(params->h14, &dpll_regs->cm_div_h14_dpll); - if (params->h22 >= 0) - writel(params->h22, &dpll_regs->cm_div_h22_dpll); - if (params->h23 >= 0) - writel(params->h23, &dpll_regs->cm_div_h23_dpll); -} - -const struct dpll_params *get_mpu_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &mpu_dpll_params_800mhz[sysclk_ind]; -} - -const struct dpll_params *get_core_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - - /* Configuring the DDR to be at 532mhz */ - return &core_dpll_params_2128mhz_ddr532[sysclk_ind]; -} - -const struct dpll_params *get_per_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &per_dpll_params_768mhz[sysclk_ind]; -} - -const struct dpll_params *get_iva_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &iva_dpll_params_2330mhz[sysclk_ind]; -} - -const struct dpll_params *get_usb_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &usb_dpll_params_1920mhz[sysclk_ind]; -} - -const struct dpll_params *get_abe_dpll_params(void) -{ -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - u32 sysclk_ind = get_sys_clk_index(); - return &abe_dpll_params_sysclk_196608khz[sysclk_ind]; -#else - return &abe_dpll_params_32k_196608khz; -#endif -} - /* * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva * We set the maximum voltages allowed here because Smart-Reflex is not @@ -300,195 +96,3 @@ u32 get_offset_code(u32 volt_offset) */ return offset_code + 6; } - -/* - * Enable essential clock domains, modules and - * do some additional special settings needed - */ -void enable_basic_clocks(void) -{ - u32 const clk_domains_essential[] = { - (*prcm)->cm_l4per_clkstctrl, - (*prcm)->cm_l3init_clkstctrl, - (*prcm)->cm_memif_clkstctrl, - (*prcm)->cm_l4cfg_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_essential[] = { - (*prcm)->cm_l3_2_gpmc_clkctrl, - (*prcm)->cm_memif_emif_1_clkctrl, - (*prcm)->cm_memif_emif_2_clkctrl, - (*prcm)->cm_l4cfg_l4_cfg_clkctrl, - (*prcm)->cm_wkup_gpio1_clkctrl, - (*prcm)->cm_l4per_gpio2_clkctrl, - (*prcm)->cm_l4per_gpio3_clkctrl, - (*prcm)->cm_l4per_gpio4_clkctrl, - (*prcm)->cm_l4per_gpio5_clkctrl, - (*prcm)->cm_l4per_gpio6_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_essential[] = { - (*prcm)->cm_wkup_gptimer1_clkctrl, - (*prcm)->cm_l3init_hsmmc1_clkctrl, - (*prcm)->cm_l3init_hsmmc2_clkctrl, - (*prcm)->cm_l4per_gptimer2_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_l4per_uart3_clkctrl, - (*prcm)->cm_l4per_i2c1_clkctrl, - 0 - }; - - /* Enable optional additional functional clock for GPIO4 */ - setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, - GPIO4_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable 96 MHz clock for MMC1 & MMC2 */ - setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - - /* Set the correct clock dividers for mmc */ - setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - - /* Select 32KHz clock as the source of GPTIMER1 */ - setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, - GPTIMER1_CLKCTRL_CLKSEL_MASK); - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); - - /* Select 384Mhz for GPU as its the POR for ES1.0 */ - setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, - CLKSEL_GPU_HYD_GCLK_MASK); - setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, - CLKSEL_GPU_CORE_GCLK_MASK); - - /* Enable SCRM OPT clocks for PER and CORE dpll */ - setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, - OPTFCLKEN_SCRM_PER_MASK); - setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, - OPTFCLKEN_SCRM_CORE_MASK); -} - -void enable_basic_uboot_clocks(void) -{ - u32 const clk_domains_essential[] = { - 0 - }; - - u32 const clk_modules_hw_auto_essential[] = { - 0 - }; - - u32 const clk_modules_explicit_en_essential[] = { - (*prcm)->cm_l4per_mcspi1_clkctrl, - (*prcm)->cm_l4per_i2c2_clkctrl, - (*prcm)->cm_l4per_i2c3_clkctrl, - (*prcm)->cm_l4per_i2c4_clkctrl, - (*prcm)->cm_l3init_hsusbtll_clkctrl, - (*prcm)->cm_l3init_hsusbhost_clkctrl, - (*prcm)->cm_l3init_fsusb_clkctrl, - 0 - }; - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); -} - -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 const clk_domains_non_essential[] = { - (*prcm)->cm_mpu_m3_clkstctrl, - (*prcm)->cm_ivahd_clkstctrl, - (*prcm)->cm_dsp_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sgx_clkstctrl, - (*prcm)->cm1_abe_clkstctrl, - (*prcm)->cm_c2c_clkstctrl, - (*prcm)->cm_cam_clkstctrl, - (*prcm)->cm_dss_clkstctrl, - (*prcm)->cm_sdma_clkstctrl, - 0 - }; - - u32 const clk_modules_hw_auto_non_essential[] = { - (*prcm)->cm_mpu_m3_mpu_m3_clkctrl, - (*prcm)->cm_ivahd_ivahd_clkctrl, - (*prcm)->cm_ivahd_sl2_clkctrl, - (*prcm)->cm_dsp_dsp_clkctrl, - (*prcm)->cm_l3instr_l3_3_clkctrl, - (*prcm)->cm_l3instr_l3_instr_clkctrl, - (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, - (*prcm)->cm_l3init_hsi_clkctrl, - (*prcm)->cm_l4per_hdq1w_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_non_essential[] = { - (*prcm)->cm1_abe_aess_clkctrl, - (*prcm)->cm1_abe_pdm_clkctrl, - (*prcm)->cm1_abe_dmic_clkctrl, - (*prcm)->cm1_abe_mcasp_clkctrl, - (*prcm)->cm1_abe_mcbsp1_clkctrl, - (*prcm)->cm1_abe_mcbsp2_clkctrl, - (*prcm)->cm1_abe_mcbsp3_clkctrl, - (*prcm)->cm1_abe_slimbus_clkctrl, - (*prcm)->cm1_abe_timer5_clkctrl, - (*prcm)->cm1_abe_timer6_clkctrl, - (*prcm)->cm1_abe_timer7_clkctrl, - (*prcm)->cm1_abe_timer8_clkctrl, - (*prcm)->cm1_abe_wdt3_clkctrl, - (*prcm)->cm_l4per_gptimer9_clkctrl, - (*prcm)->cm_l4per_gptimer10_clkctrl, - (*prcm)->cm_l4per_gptimer11_clkctrl, - (*prcm)->cm_l4per_gptimer3_clkctrl, - (*prcm)->cm_l4per_gptimer4_clkctrl, - (*prcm)->cm_l4per_mcspi2_clkctrl, - (*prcm)->cm_l4per_mcspi3_clkctrl, - (*prcm)->cm_l4per_mcspi4_clkctrl, - (*prcm)->cm_l4per_mmcsd3_clkctrl, - (*prcm)->cm_l4per_mmcsd4_clkctrl, - (*prcm)->cm_l4per_mmcsd5_clkctrl, - (*prcm)->cm_l4per_uart1_clkctrl, - (*prcm)->cm_l4per_uart2_clkctrl, - (*prcm)->cm_l4per_uart4_clkctrl, - (*prcm)->cm_wkup_keyboard_clkctrl, - (*prcm)->cm_wkup_wdtimer2_clkctrl, - (*prcm)->cm_cam_iss_clkctrl, - (*prcm)->cm_cam_fdif_clkctrl, - (*prcm)->cm_dss_dss_clkctrl, - (*prcm)->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32((*prcm)->cm_cam_clkstctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 0f1234c..df375f9 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -27,12 +27,367 @@ */ #include #include +#include #include +#include +#include struct prcm_regs const **prcm = (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; +struct dplls const **dplls_data = + (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; + +static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { + {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = { + {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { + {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { + {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = { + {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { + {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ + {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ + {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { + {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */ + {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */ + {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { + {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { + {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */ + {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */ + {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with sys_clk as source */ +static const struct dpll_params + abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { + {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1 +}; + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +struct dplls omap5_dplls_es1 = { + .mpu = mpu_dpll_params_800mhz, + .core = core_dpll_params_2128mhz_ddr532, + .per = per_dpll_params_768mhz, + .iva = iva_dpll_params_2330mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz +}; + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +void enable_basic_clocks(void) +{ + u32 const clk_domains_essential[] = { + (*prcm)->cm_l4per_clkstctrl, + (*prcm)->cm_l3init_clkstctrl, + (*prcm)->cm_memif_clkstctrl, + (*prcm)->cm_l4cfg_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3_2_gpmc_clkctrl, + (*prcm)->cm_memif_emif_1_clkctrl, + (*prcm)->cm_memif_emif_2_clkctrl, + (*prcm)->cm_l4cfg_l4_cfg_clkctrl, + (*prcm)->cm_wkup_gpio1_clkctrl, + (*prcm)->cm_l4per_gpio2_clkctrl, + (*prcm)->cm_l4per_gpio3_clkctrl, + (*prcm)->cm_l4per_gpio4_clkctrl, + (*prcm)->cm_l4per_gpio5_clkctrl, + (*prcm)->cm_l4per_gpio6_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_wkup_gptimer1_clkctrl, + (*prcm)->cm_l3init_hsmmc1_clkctrl, + (*prcm)->cm_l3init_hsmmc2_clkctrl, + (*prcm)->cm_l4per_gptimer2_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart3_clkctrl, + (*prcm)->cm_l4per_i2c1_clkctrl, + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, + GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Set the correct clock dividers for mmc */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, + GPTIMER1_CLKCTRL_CLKSEL_MASK); + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); + + /* Select 384Mhz for GPU as its the POR for ES1.0 */ + setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, + CLKSEL_GPU_HYD_GCLK_MASK); + setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, + CLKSEL_GPU_CORE_GCLK_MASK); + + /* Enable SCRM OPT clocks for PER and CORE dpll */ + setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, + OPTFCLKEN_SCRM_PER_MASK); + setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, + OPTFCLKEN_SCRM_CORE_MASK); +} + +void enable_basic_uboot_clocks(void) +{ + u32 const clk_domains_essential[] = { + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_l4per_mcspi1_clkctrl, + (*prcm)->cm_l4per_i2c2_clkctrl, + (*prcm)->cm_l4per_i2c3_clkctrl, + (*prcm)->cm_l4per_i2c4_clkctrl, + (*prcm)->cm_l3init_hsusbtll_clkctrl, + (*prcm)->cm_l3init_hsusbhost_clkctrl, + (*prcm)->cm_l3init_fsusb_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +/* + * Enable non-essential clock domains, modules and + * do some additional special settings needed + */ +void enable_non_essential_clocks(void) +{ + u32 const clk_domains_non_essential[] = { + (*prcm)->cm_mpu_m3_clkstctrl, + (*prcm)->cm_ivahd_clkstctrl, + (*prcm)->cm_dsp_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sgx_clkstctrl, + (*prcm)->cm1_abe_clkstctrl, + (*prcm)->cm_c2c_clkstctrl, + (*prcm)->cm_cam_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sdma_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_non_essential[] = { + (*prcm)->cm_mpu_m3_mpu_m3_clkctrl, + (*prcm)->cm_ivahd_ivahd_clkctrl, + (*prcm)->cm_ivahd_sl2_clkctrl, + (*prcm)->cm_dsp_dsp_clkctrl, + (*prcm)->cm_l3instr_l3_3_clkctrl, + (*prcm)->cm_l3instr_l3_instr_clkctrl, + (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, + (*prcm)->cm_l3init_hsi_clkctrl, + (*prcm)->cm_l4per_hdq1w_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_non_essential[] = { + (*prcm)->cm1_abe_aess_clkctrl, + (*prcm)->cm1_abe_pdm_clkctrl, + (*prcm)->cm1_abe_dmic_clkctrl, + (*prcm)->cm1_abe_mcasp_clkctrl, + (*prcm)->cm1_abe_mcbsp1_clkctrl, + (*prcm)->cm1_abe_mcbsp2_clkctrl, + (*prcm)->cm1_abe_mcbsp3_clkctrl, + (*prcm)->cm1_abe_slimbus_clkctrl, + (*prcm)->cm1_abe_timer5_clkctrl, + (*prcm)->cm1_abe_timer6_clkctrl, + (*prcm)->cm1_abe_timer7_clkctrl, + (*prcm)->cm1_abe_timer8_clkctrl, + (*prcm)->cm1_abe_wdt3_clkctrl, + (*prcm)->cm_l4per_gptimer9_clkctrl, + (*prcm)->cm_l4per_gptimer10_clkctrl, + (*prcm)->cm_l4per_gptimer11_clkctrl, + (*prcm)->cm_l4per_gptimer3_clkctrl, + (*prcm)->cm_l4per_gptimer4_clkctrl, + (*prcm)->cm_l4per_mcspi2_clkctrl, + (*prcm)->cm_l4per_mcspi3_clkctrl, + (*prcm)->cm_l4per_mcspi4_clkctrl, + (*prcm)->cm_l4per_mmcsd3_clkctrl, + (*prcm)->cm_l4per_mmcsd4_clkctrl, + (*prcm)->cm_l4per_mmcsd5_clkctrl, + (*prcm)->cm_l4per_uart1_clkctrl, + (*prcm)->cm_l4per_uart2_clkctrl, + (*prcm)->cm_l4per_uart4_clkctrl, + (*prcm)->cm_wkup_keyboard_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_cam_iss_clkctrl, + (*prcm)->cm_cam_fdif_clkctrl, + (*prcm)->cm_dss_dss_clkctrl, + (*prcm)->cm_sgx_sgx_clkctrl, + 0 + }; + + /* Enable optional functional clock for ISS */ + setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable all optional functional clocks of DSS */ + setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); + + do_enable_clocks(clk_domains_non_essential, + clk_modules_hw_auto_non_essential, + clk_modules_explicit_en_non_essential, + 0); + + /* Put camera module in no sleep mode */ + clrsetbits_le32((*prcm)->cm_cam_clkstctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} void hw_data_init(void) { + u32 omap_rev = omap_revision(); + + switch (omap_rev) { + + case OMAP5430_ES1_0: *prcm = &omap5_es1_prcm; + *dplls_data = &omap5_dplls_es1; + break; + + case OMAP5432_ES1_0: + *prcm = &omap5_es1_prcm; + *dplls_data = &omap5_dplls_es1; + break; + + default: + printf("\n INVALID OMAP REVISION "); + } } diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 4710d88..ceb3367 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -242,55 +242,10 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 -#define NUM_SYS_CLKS 7 - -struct dpll_regs { - u32 cm_clkmode_dpll; - u32 cm_idlest_dpll; - u32 cm_autoidle_dpll; - u32 cm_clksel_dpll; - u32 cm_div_m2_dpll; - u32 cm_div_m3_dpll; - u32 cm_div_m4_dpll; - u32 cm_div_m5_dpll; - u32 cm_div_m6_dpll; - u32 cm_div_m7_dpll; -}; - -/* DPLL parameter table */ -struct dpll_params { - u32 m; - u32 n; - s8 m2; - s8 m3; - s8 m4; - s8 m5; - s8 m6; - s8 m7; -}; - -extern const u32 sys_clk_array[8]; - void scale_vcores(void); void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); u32 get_offset_code(u32 offset); -u32 omap_ddr_clk(void); void do_scale_vcore(u32 vcore_reg, u32 volt_mv); -void setup_post_dividers(u32 const base, const struct dpll_params *params); -u32 get_sys_clk_index(void); -void enable_basic_clocks(void); -void enable_basic_uboot_clocks(void); -void enable_non_essential_clocks(void); -void do_enable_clocks(u32 const *clk_domains, - u32 const *clk_modules_hw_auto, - u32 const *clk_modules_explicit_en, - u8 wait_for_enable); -const struct dpll_params *get_mpu_dpll_params(void); -const struct dpll_params *get_core_dpll_params(void); -const struct dpll_params *get_per_dpll_params(void); -const struct dpll_params *get_iva_dpll_params(void); -const struct dpll_params *get_usb_dpll_params(void); -const struct dpll_params *get_abe_dpll_params(void); struct omap4_scrm_regs { u32 revision; /* 0x0000 */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 86ba335..1c0ce9b 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -179,7 +179,8 @@ struct control_lpddr2io_regs { #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) -#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C) /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 67e74ca..063347f 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -234,58 +234,8 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 -#define NUM_SYS_CLKS 7 - -struct dpll_regs { - u32 cm_clkmode_dpll; - u32 cm_idlest_dpll; - u32 cm_autoidle_dpll; - u32 cm_clksel_dpll; - u32 cm_div_m2_dpll; - u32 cm_div_m3_dpll; - u32 cm_div_h11_dpll; - u32 cm_div_h12_dpll; - u32 cm_div_h13_dpll; - u32 cm_div_h14_dpll; - u32 reserved[3]; - u32 cm_div_h22_dpll; - u32 cm_div_h23_dpll; -}; - -/* DPLL parameter table */ -struct dpll_params { - u32 m; - u32 n; - s8 m2; - s8 m3; - s8 h11; - s8 h12; - s8 h13; - s8 h14; - s8 h22; - s8 h23; -}; - -extern const u32 sys_clk_array[8]; - void scale_vcores(void); void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); u32 get_offset_code(u32 offset); -u32 omap_ddr_clk(void); void do_scale_vcore(u32 vcore_reg, u32 volt_mv); -void setup_post_dividers(u32 const base, const struct dpll_params *params); -u32 get_sys_clk_index(void); -void enable_basic_clocks(void); -void enable_non_essential_clocks(void); -void enable_basic_uboot_clocks(void); -void do_enable_clocks(u32 const *clk_domains, - u32 const *clk_modules_hw_auto, - u32 const *clk_modules_explicit_en, - u8 wait_for_enable); -const struct dpll_params *get_mpu_dpll_params(void); -const struct dpll_params *get_core_dpll_params(void); -const struct dpll_params *get_per_dpll_params(void); -const struct dpll_params *get_iva_dpll_params(void); -const struct dpll_params *get_usb_dpll_params(void); -const struct dpll_params *get_abe_dpll_params(void); #endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 50e055e..7123694 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -272,7 +272,8 @@ struct omap_sys_ctrl_regs { #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C) /* Silicon revisions */ #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index fcf9ce5..c2d8388 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -27,6 +27,8 @@ #include +#define NUM_SYS_CLKS 7 + struct prcm_regs { /* cm1.ckgen */ u32 cm_clksel_core; @@ -324,11 +326,72 @@ struct prcm_regs { u32 prm_vc_cfg_channel; }; +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 m4_h11; + s8 m5_h12; + s8 m6_h13; + s8 m7_h14; + s8 h22; + s8 h23; +}; + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_h11_dpll; + u32 cm_div_m5_h12_dpll; + u32 cm_div_m6_h13_dpll; + u32 cm_div_m7_h14_dpll; + u32 reserved[3]; + u32 cm_div_h22_dpll; + u32 cm_div_h23_dpll; +}; + +struct dplls { + const struct dpll_params *mpu; + const struct dpll_params *core; + const struct dpll_params *per; + const struct dpll_params *abe; + const struct dpll_params *iva; + const struct dpll_params *usb; +}; + extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; extern struct prcm_regs const omap4_prcm; +extern struct dplls const **dplls_data; +extern const u32 sys_clk_array[8]; void hw_data_init(void); + +const struct dpll_params *get_mpu_dpll_params(struct dplls const *); +const struct dpll_params *get_core_dpll_params(struct dplls const *); +const struct dpll_params *get_per_dpll_params(struct dplls const *); +const struct dpll_params *get_iva_dpll_params(struct dplls const *); +const struct dpll_params *get_usb_dpll_params(struct dplls const *); +const struct dpll_params *get_abe_dpll_params(struct dplls const *); + +void do_enable_clocks(u32 const *clk_domains, + u32 const *clk_modules_hw_auto, + u32 const *clk_modules_explicit_en, + u8 wait_for_enable); + +void setup_post_dividers(u32 const base, + const struct dpll_params *params); +u32 omap_ddr_clk(void); +u32 get_sys_clk_index(void); +void enable_basic_clocks(void); +void enable_basic_uboot_clocks(void); +void enable_non_essential_clocks(void); + /* Max value for DPLL multiplier M */ #define OMAP_DPLL_MAX_N 127 -- cgit v0.10.2 From 3fcdd4a5f8ba0e0fac4b2afdb5e90efac9f7f301 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Mon, 4 Feb 2013 04:22:02 +0000 Subject: ARM: OMAP4+: Clean up the pmic code The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 2becc4a..88e5336 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -443,44 +443,45 @@ static void setup_non_essential_dplls(void) } #endif -void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv) +u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic) { - u32 step; - int ret = 0; - - /* See if we can first get the GPIO if needed */ - if (gpio >= 0) - ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO"); - if (ret < 0) { - printf("%s: gpio %d request failed %d\n", __func__, gpio, ret); - gpio = -1; - } - - /* Pull the GPIO low to select SET0 register, while we program SET1 */ - if (gpio >= 0) - gpio_direction_output(gpio, 0); + u32 offset_code; - step = volt_mv - TPS62361_BASE_VOLT_MV; - step /= 10; + volt_offset -= pmic->base_offset; - debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step); - if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step)) - puts("Scaling voltage failed for vdd_mpu from TPS\n"); + offset_code = (volt_offset + pmic->step - 1) / pmic->step; - /* Pull the GPIO high to select SET1 register */ - if (gpio >= 0) - gpio_direction_output(gpio, 1); + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + return offset_code + pmic->start_code; } -void do_scale_vcore(u32 vcore_reg, u32 volt_mv) +void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) { u32 offset_code; u32 offset = volt_mv; + int ret = 0; + + /* See if we can first get the GPIO if needed */ + if (pmic->gpio_en) + ret = gpio_request(pmic->gpio, "PMIC_GPIO"); + + if (ret < 0) { + printf("%s: gpio %d request failed %d\n", __func__, + pmic->gpio, ret); + return; + } + + /* Pull the GPIO low to select SET0 register, while we program SET1 */ + if (pmic->gpio_en) + gpio_direction_output(pmic->gpio, 0); /* convert to uV for better accuracy in the calculations */ offset *= 1000; - offset_code = get_offset_code(offset); + offset_code = get_offset_code(offset, pmic); debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, offset_code); @@ -488,6 +489,36 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv) if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR, vcore_reg, offset_code)) printf("Scaling voltage failed for 0x%x\n", vcore_reg); + + if (pmic->gpio_en) + gpio_direction_output(pmic->gpio, 1); +} + +/* + * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva + * We set the maximum voltages allowed here because Smart-Reflex is not + * enabled in bootloader. Voltage initialization in the kernel will set + * these to the nominal values after enabling Smart-Reflex + */ +void scale_vcores(struct vcores_data const *vcores) +{ + omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); + + do_scale_vcore(vcores->core.addr, vcores->core.value, + vcores->core.pmic); + + do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, + vcores->mpu.pmic); + + do_scale_vcore(vcores->mm.addr, vcores->mm.value, + vcores->mm.pmic); + + if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { + /* Configure LDO SRAM "magic" bits */ + writel(2, (*prcm)->prm_sldo_core_setup); + writel(2, (*prcm)->prm_sldo_mpu_setup); + writel(2, (*prcm)->prm_sldo_mm_setup); + } } static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) @@ -656,7 +687,7 @@ void prcm_init(void) case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: enable_basic_clocks(); - scale_vcores(); + scale_vcores(*omap_vcores); setup_dplls(); #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL setup_non_essential_dplls(); diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index 0365148..40808d1 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -27,7 +27,6 @@ LIB = $(obj)lib$(SOC).o COBJS += sdram_elpida.o COBJS += hwinit.o -COBJS += clocks.o COBJS += emif.o COBJS += prcm-regs.o COBJS += hw_data.o diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c deleted file mode 100644 index 4772743..0000000 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * - * Clock initialization for OMAP4 - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V - * - * Based on previous work by: - * Santosh Shilimkar - * Rajendra Nayak - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONFIG_SPL_BUILD -/* - * printing to console doesn't work unless - * this code is executed from SPL - */ -#define printf(fmt, args...) -#define puts(s) -#endif /* !CONFIG_SPL_BUILD */ - -/* - * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva - * We set the maximum voltages allowed here because Smart-Reflex is not - * enabled in bootloader. Voltage initialization in the kernel will set - * these to the nominal values after enabling Smart-Reflex - */ -void scale_vcores(void) -{ - u32 volt, omap_rev; - - omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); - - omap_rev = omap_revision(); - - /* - * Scale Voltage rails: - * 1. VDD_CORE - * 3. VDD_MPU - * 3. VDD_IVA - */ - if (omap_rev < OMAP4460_ES1_0) { - /* - * OMAP4430: - * VDD_CORE = TWL6030 VCORE3 - * VDD_MPU = TWL6030 VCORE1 - * VDD_IVA = TWL6030 VCORE2 - */ - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); - - /* - * note on VDD_MPU: - * Setting a high voltage for Nitro mode as smart reflex is not - * enabled. We use the maximum possible value in the AVS range - * because the next higher voltage in the discrete range - * (code >= 0b111010) is way too high. - */ - volt = 1325; - do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); - - } else { - /* - * OMAP4460: - * VDD_CORE = TWL6030 VCORE1 - * VDD_MPU = TPS62361 - * VDD_IVA = TWL6030 VCORE2 - */ - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); - /* TPS62361 */ - volt = 1203; - do_scale_tps62361(TPS62361_VSEL0_GPIO, - TPS62361_REG_ADDR_SET1, volt); - /* VCORE 2 - supplies vdd_iva */ - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); - } -} - -u32 get_offset_code(u32 offset) -{ - u32 offset_code, step = 12660; /* 12.66 mV represented in uV */ - - if (omap_revision() == OMAP4430_ES1_0) - offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; - else - offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; - - offset_code = (offset + step - 1) / step; - - /* The code starts at 1 not 0 */ - return ++offset_code; -} diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 6ae3986..18efa6c 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -30,12 +30,15 @@ #include #include #include +#include #include struct prcm_regs const **prcm = (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; struct dplls const **dplls_data = (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct vcores_data const **omap_vcores = + (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; /* * The M & N values in the following tables are created using the @@ -194,6 +197,70 @@ struct dplls omap4460_dplls = { .usb = usb_dpll_params_1920mhz }; +struct pmic_data twl6030_4430es1 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, + .step = 12660, /* 10 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, +}; + +struct pmic_data twl6030 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, + .step = 12660, /* 10 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, +}; + +struct pmic_data tps62361 = { + .base_offset = TPS62361_BASE_VOLT_MV, + .step = 10000, /* 10 mV represented in uV */ + .start_code = 0, + .gpio = TPS62361_VSEL0_GPIO, + .gpio_en = 1 +}; + +struct vcores_data omap4430_volts_es1 = { + .mpu.value = 1325, + .mpu.addr = SMPS_REG_ADDR_VCORE1, + .mpu.pmic = &twl6030_4430es1, + + .core.value = 1200, + .core.addr = SMPS_REG_ADDR_VCORE3, + .core.pmic = &twl6030_4430es1, + + .mm.value = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030_4430es1, +}; + +struct vcores_data omap4430_volts = { + .mpu.value = 1325, + .mpu.addr = SMPS_REG_ADDR_VCORE1, + .mpu.pmic = &twl6030, + + .core.value = 1200, + .core.addr = SMPS_REG_ADDR_VCORE3, + .core.pmic = &twl6030, + + .mm.value = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030, +}; + +struct vcores_data omap4460_volts = { + .mpu.value = 1203, + .mpu.addr = TPS62361_REG_ADDR_SET1, + .mpu.pmic = &tps62361, + + .core.value = 1200, + .core.addr = SMPS_REG_ADDR_VCORE1, + .core.pmic = &tps62361, + + .mm.value = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &tps62361, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -382,6 +449,7 @@ void hw_data_init(void) case OMAP4430_ES1_0: *dplls_data = &omap4430_dplls_es1; + *omap_vcores = &omap4430_volts_es1; break; case OMAP4430_ES2_0: @@ -389,11 +457,13 @@ void hw_data_init(void) case OMAP4430_ES2_2: case OMAP4430_ES2_3: *dplls_data = &omap4430_dplls; + *omap_vcores = &omap4430_volts; break; case OMAP4460_ES1_0: case OMAP4460_ES1_1: *dplls_data = &omap4460_dplls; + *omap_vcores = &omap4460_volts; break; default: diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index 81625f6..ce00e2c 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o COBJS += hwinit.o -COBJS += clocks.o COBJS += emif.o COBJS += sdram.o COBJS += prcm-regs.o diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c deleted file mode 100644 index da5b3ac..0000000 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * - * Clock initialization for OMAP5 - * - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V - * Sricharan R - * - * Based on previous work by: - * Santosh Shilimkar - * Rajendra Nayak - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONFIG_SPL_BUILD -/* - * printing to console doesn't work unless - * this code is executed from SPL - */ -#define printf(fmt, args...) -#define puts(s) -#endif - -/* - * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva - * We set the maximum voltages allowed here because Smart-Reflex is not - * enabled in bootloader. Voltage initialization in the kernel will set - * these to the nominal values after enabling Smart-Reflex - */ -void scale_vcores(void) -{ - u32 volt_core, volt_mpu, volt_mm; - - omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); - - /* Palmas settings */ - if (omap_revision() != OMAP5432_ES1_0) { - volt_core = VDD_CORE; - volt_mpu = VDD_MPU; - volt_mm = VDD_MM; - } else { - volt_core = VDD_CORE_5432; - volt_mpu = VDD_MPU_5432; - volt_mm = VDD_MM_5432; - } - - do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core); - do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu); - do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm); - - if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { - /* Configure LDO SRAM "magic" bits */ - writel(2, (*prcm)->prm_sldo_core_setup); - writel(2, (*prcm)->prm_sldo_mpu_setup); - writel(2, (*prcm)->prm_sldo_mm_setup); - } -} - -u32 get_offset_code(u32 volt_offset) -{ - u32 offset_code, step = 10000; /* 10 mV represented in uV */ - - volt_offset -= PALMAS_SMPS_BASE_VOLT_UV; - - offset_code = (volt_offset + step - 1) / step; - - /* - * Offset codes 1-6 all give the base voltage in Palmas - * Offset code 0 switches OFF the SMPS - */ - return offset_code + 6; -} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index df375f9..13e618d 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -30,12 +30,15 @@ #include #include #include +#include #include struct prcm_regs const **prcm = (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; struct dplls const **dplls_data = (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct vcores_data const **omap_vcores = + (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -179,6 +182,44 @@ struct dplls omap5_dplls_es1 = { .usb = usb_dpll_params_1920mhz }; +struct pmic_data palmas = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, +}; + +struct vcores_data omap5430_volts = { + .mpu.value = VDD_MPU, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + + .core.value = VDD_CORE, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, +}; + +struct vcores_data omap5432_volts = { + .mpu.value = VDD_MPU_5432, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + + .core.value = VDD_CORE_5432, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM_5432, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -380,11 +421,13 @@ void hw_data_init(void) case OMAP5430_ES1_0: *prcm = &omap5_es1_prcm; *dplls_data = &omap5_dplls_es1; + *omap_vcores = &omap5430_volts; break; case OMAP5432_ES1_0: *prcm = &omap5_es1_prcm; *dplls_data = &omap5_dplls_es1; + *omap_vcores = &omap5432_volts; break; default: diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index ceb3367..ed7a1c8 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -242,11 +242,6 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 -void scale_vcores(void); -void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); -u32 get_offset_code(u32 offset); -void do_scale_vcore(u32 vcore_reg, u32 volt_mv); - struct omap4_scrm_regs { u32 revision; /* 0x0000 */ u32 pad00[63]; diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 1c0ce9b..73edd9d 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -180,7 +180,8 @@ struct control_lpddr2io_regs { #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) -#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20) /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 063347f..15362ae 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -234,8 +234,4 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 -void scale_vcores(void); -void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); -u32 get_offset_code(u32 offset); -void do_scale_vcore(u32 vcore_reg, u32 volt_mv); #endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 7123694..4bf555a 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -273,7 +273,8 @@ struct omap_sys_ctrl_regs { #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20) /* Silicon revisions */ #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index c2d8388..eee6893 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -364,10 +364,31 @@ struct dplls { const struct dpll_params *usb; }; +struct pmic_data { + u32 base_offset; + u32 step; + u32 start_code; + unsigned gpio; + int gpio_en; +}; + +struct volts { + u32 value; + u32 addr; + struct pmic_data *pmic; +}; + +struct vcores_data { + struct volts mpu; + struct volts core; + struct volts mm; +}; + extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; extern struct prcm_regs const omap4_prcm; extern struct dplls const **dplls_data; +extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; void hw_data_init(void); @@ -391,6 +412,9 @@ u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); void enable_non_essential_clocks(void); +void scale_vcores(struct vcores_data const *); +u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); +void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); /* Max value for DPLL multiplier M */ #define OMAP_DPLL_MAX_N 127 diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 85ea88b..0f11d34 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -265,5 +265,6 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ #define CONFIG_SYS_SPL_MALLOC_START 0x84100000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SPL_GPIO_SUPPORT #endif /* __CONFIG_H */ -- cgit v0.10.2 From e05a4f1f54f2b5a0c46de978672199e375ba0c00 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 4 Feb 2013 04:22:03 +0000 Subject: ARM: OMAP4+: Cleanup emif specific files Removing the duplicated code in ddr3 initialization. Also creating structure for lpddr2 mode registers to avoid unnessecary revision checks. These change reduces code addition for future Socs. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index bb37cf3..0683b9f 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -123,11 +123,13 @@ void emif_reset_phy(u32 base) static void do_lpddr2_init(u32 base, u32 cs) { u32 mr_addr; + const struct lpddr2_mr_regs *mr_regs; + get_lpddr2_mr_regs(&mr_regs); /* Wait till device auto initialization is complete */ while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) ; - set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT); + set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10); /* * tZQINIT = 1 us * Enough loops assuming a maximum of 2GHz @@ -135,22 +137,18 @@ static void do_lpddr2_init(u32 base, u32 cs) sdelay(2000); - if (omap_revision() >= OMAP5430_ES1_0) - set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8); - else - set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); - - set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY); + set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); + set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16); /* * Enable refresh along with writing MR2 * Encoding of RL in MR2 is (RL - 2) */ mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; - set_mr(base, cs, mr_addr, RL_FINAL - 2); + set_mr(base, cs, mr_addr, mr_regs->mr2); - if (omap_revision() >= OMAP5430_ES1_0) - set_mr(base, cs, LPDDR2_MR3, 0x1); + if (mr_regs->mr3 > 0) + set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); } static void lpddr2_init(u32 base, const struct emif_regs *regs) @@ -268,9 +266,6 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs) static void ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 *ext_phy_ctrl_base = 0; - u32 *emif_ext_phy_ctrl_base = 0; - u32 i = 0; /* * Set SDRAM_CONFIG and PHY control registers to locked frequency @@ -290,27 +285,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); - ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); - emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); - - /* Configure external phy control timing registers */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { - writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); - } - - /* - * external phy 6-24 registers do not change with - * ddr frequency - */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { - writel(ddr3_ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(ddr3_ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); - } + do_ext_phy_settings(base, regs); /* enable leveling */ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); @@ -1109,9 +1084,6 @@ void emif_post_init_config(u32 base) struct emif_reg_struct *emif = (struct emif_reg_struct *)base; u32 omap_rev = omap_revision(); - if (omap_rev == OMAP5430_ES1_0) - return; - /* reset phy on ES2.0 */ if (omap_rev == OMAP4430_ES2_0) emif_reset_phy(base); diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index b9128fa..01da790 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -90,9 +90,6 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .emif_ddr_phy_ctlr_1 = 0x049ff418 }; -/* Dummy registers for OMAP44xx */ -const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; - const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, @@ -284,3 +281,16 @@ void emif_get_device_timings(u32 emif_nr, __attribute__((weak, alias("emif_get_device_timings_sdp"))); #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ + +const struct lpddr2_mr_regs mr_regs = { + .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3, + .mr2 = 0x4, + .mr3 = -1, + .mr10 = MR10_ZQ_ZQINIT, + .mr16 = MR16_REF_FULL_ARRAY +}; + +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) +{ + *regs = &mr_regs; +} diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 6ebdf5f..687800f 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -116,6 +116,56 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_3 = 0xFF020100 }; +static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) +{ + switch (omap_revision()) { + case OMAP5430_ES1_0: + *regs = &emif_regs_532_mhz_2cs; + break; + case OMAP5432_ES1_0: + *regs = &emif_regs_ddr3_532_mhz_1cs; + break; + default: + *regs = &emif_regs_ddr3_532_mhz_1cs; + } +} + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) + __attribute__((weak, alias("emif_get_reg_dump_sdp"))); + +static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs + **dmm_lisa_regs) +{ + *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) + __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); +#else + +static const struct lpddr2_device_details dev_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG +}; + +static void emif_get_device_details_sdp(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) +{ + /* EMIF1 & EMIF2 have identical configuration */ + *cs0_device_details = dev_4G_S4_details; + *cs1_device_details = dev_4G_S4_details; +} + +void emif_get_device_details(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) + __attribute__((weak, alias("emif_get_device_details_sdp"))); + +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x01004010, 0x00001004, @@ -138,7 +188,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000077 }; -const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x01004010, 0x00001004, 0x04010040, @@ -160,54 +210,38 @@ const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000057 }; -static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) -{ - if (omap_revision() == OMAP5432_ES1_0) - *regs = &emif_regs_ddr3_532_mhz_1cs; - else - *regs = &emif_regs_532_mhz_2cs; -} -void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) - __attribute__((weak, alias("emif_get_reg_dump_sdp"))); +const struct lpddr2_mr_regs mr_regs = { + .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8, + .mr2 = 0x6, + .mr3 = 0x1, + .mr10 = MR10_ZQ_ZQINIT, + .mr16 = MR16_REF_FULL_ARRAY +}; -static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs - **dmm_lisa_regs) +static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) { - *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; + switch (omap_revision()) { + case OMAP5430_ES1_0: + *regs = ext_phy_ctrl_const_base; + break; + case OMAP5432_ES1_0: + *regs = ddr3_ext_phy_ctrl_const_base_es1; + break; + default: + *regs = ddr3_ext_phy_ctrl_const_base_es1; + } } -void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) - __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); - -#else - -static const struct lpddr2_device_details dev_4G_S4_details = { - .type = LPDDR2_TYPE_S4, - .density = LPDDR2_DENSITY_4Gb, - .io_width = LPDDR2_IO_WIDTH_32, - .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG -}; - -static void emif_get_device_details_sdp(u32 emif_nr, - struct lpddr2_device_details *cs0_device_details, - struct lpddr2_device_details *cs1_device_details) +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) { - /* EMIF1 & EMIF2 have identical configuration */ - *cs0_device_details = dev_4G_S4_details; - *cs1_device_details = dev_4G_S4_details; + *regs = &mr_regs; } -void emif_get_device_details(u32 emif_nr, - struct lpddr2_device_details *cs0_device_details, - struct lpddr2_device_details *cs1_device_details) - __attribute__((weak, alias("emif_get_device_details_sdp"))); - -#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ - void do_ext_phy_settings(u32 base, const struct emif_regs *regs) { u32 *ext_phy_ctrl_base = 0; u32 *emif_ext_phy_ctrl_base = 0; + const u32 *ext_phy_ctrl_const_regs; u32 i = 0; struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -226,12 +260,13 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) * external phy 6-24 registers do not change with * ddr frequency */ + emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs); for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { - writel(ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); + writel(ext_phy_ctrl_const_regs[i], + emif_ext_phy_ctrl_base++); /* Update shadow registers */ - writel(ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); + writel(ext_phy_ctrl_const_regs[i], + emif_ext_phy_ctrl_base++); } } diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 0824a80..fd530bb 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -698,9 +698,6 @@ struct dmm_lisa_map_regs { u32 dmm_lisa_map_3; }; -extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; -extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; - #define CS0 0 #define CS1 1 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ @@ -1134,6 +1131,14 @@ struct emif_regs { u32 emif_rd_wr_exec_thresh; }; +struct lpddr2_mr_regs { + s8 mr1; + s8 mr2; + s8 mr3; + s8 mr10; + s8 mr16; +}; + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) for (;;); }) @@ -1153,6 +1158,7 @@ void emif_get_device_timings(u32 emif_nr, #endif void do_ext_phy_settings(u32 base, const struct emif_regs *regs); +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs); #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS extern u32 *const T_num; -- cgit v0.10.2 From c43c8339fedc86c6c23990eaabff6feaf6742e7b Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 4 Feb 2013 04:22:04 +0000 Subject: ARM: OMAP4+: Make control module register structure generic A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index fff89da..e5a5eb6 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -238,10 +238,7 @@ int checkboard(void) */ u32 get_device_type(void) { - struct omap_sys_ctrl_regs *ctrl = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - - return (readl(&ctrl->control_status) & + return (readl((*ctrl)->control_status) & (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; } diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 18efa6c..892d016 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -39,6 +39,8 @@ struct dplls const **dplls_data = (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; struct vcores_data const **omap_vcores = (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL; /* * The M & N values in the following tables are created using the @@ -470,4 +472,5 @@ void hw_data_init(void) printf("\n INVALID OMAP REVISION "); } + *ctrl = &omap4_ctrl; } diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index f4123aa..2db517b 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -57,10 +57,6 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; void do_io_settings(void) { u32 lpddr2io; - struct control_lpddr2io_regs *lpddr2io_regs = - (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; - struct omap_sys_ctrl_regs *const ctrl = - (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; u32 omap4_rev = omap_revision(); @@ -72,20 +68,20 @@ void do_io_settings(void) lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; /* EMIF1 */ - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0); - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); /* No pull for GR10 as per hw team's recommendation */ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - &lpddr2io_regs->control_lpddr2io1_2); - writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3); + (*ctrl)->control_lpddr2io1_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); /* EMIF2 */ - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0); - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); /* No pull for GR10 as per hw team's recommendation */ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - &lpddr2io_regs->control_lpddr2io2_2); - writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3); + (*ctrl)->control_lpddr2io2_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); /* * Some of these settings (TRIM values) come from eFuse and are @@ -93,16 +89,16 @@ void do_io_settings(void) * calibration of the device. Do the software over-ride only if * the device is not correctly trimmed */ - if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) { + if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_iva_voltage_ctrl); + (*ctrl)->control_ldosram_iva_voltage_ctrl); writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_mpu_voltage_ctrl); + (*ctrl)->control_ldosram_mpu_voltage_ctrl); writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_core_voltage_ctrl); + (*ctrl)->control_ldosram_core_voltage_ctrl); } /* @@ -110,11 +106,11 @@ void do_io_settings(void) * i. unconditionally for all 4430 * ii. only if un-trimmed for 4460 */ - if (!readl(&ctrl->control_efuse_1)) - writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1); + if (!readl((*ctrl)->control_efuse_1)) + writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1); - if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2)) - writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2); + if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2)) + writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2); } #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c index 815b9d2..c58ce8d 100644 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -293,3 +293,23 @@ struct prcm_regs const omap4_prcm = { .prm_vc_cfg_i2c_mode = 0x4a307ba8, .prm_vc_cfg_i2c_clk = 0x4a307bac, }; + +struct omap_sys_ctrl_regs const omap4_ctrl = { + .control_id_code = 0x4A002204, + .control_std_fuse_opp_bgap = 0x4a002260, + .control_status = 0x4a0022c4, + .control_ldosram_iva_voltage_ctrl = 0x4A002320, + .control_ldosram_mpu_voltage_ctrl = 0x4A002324, + .control_ldosram_core_voltage_ctrl = 0x4A002328, + .control_pbiaslite = 0x4A100600, + .control_lpddr2io1_0 = 0x4A100638, + .control_lpddr2io1_1 = 0x4A10063C, + .control_lpddr2io1_2 = 0x4A100640, + .control_lpddr2io1_3 = 0x4A100644, + .control_lpddr2io2_0 = 0x4A100648, + .control_lpddr2io2_1 = 0x4A10064C, + .control_lpddr2io2_2 = 0x4A100650, + .control_lpddr2io2_3 = 0x4A100654, + .control_efuse_1 = 0x4A100700, + .control_efuse_2 = 0x4A100704, +}; diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 13e618d..320d5bb 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -39,6 +39,8 @@ struct dplls const **dplls_data = (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; struct vcores_data const **omap_vcores = (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL; static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -433,4 +435,6 @@ void hw_data_init(void) default: printf("\n INVALID OMAP REVISION "); } + + *ctrl = &omap5_ctrl; } diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 4def422..1863c69 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -56,76 +56,71 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; /* LPDDR2 specific IO settings */ static void io_settings_lpddr2(void) { - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_0)); + (*ctrl)->control_ddrch1_0); writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_1)); + (*ctrl)->control_ddrch1_1); writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_0)); + (*ctrl)->control_ddrch2_0); writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_1)); + (*ctrl)->control_ddrch2_1); writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_0)); + (*ctrl)->control_lpddr2ch1_0); writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_1)); + (*ctrl)->control_lpddr2ch1_1); writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, - &(ioregs_base->control_ddrio_0)); + (*ctrl)->control_ddrio_0); writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, - &(ioregs_base->control_ddrio_1)); + (*ctrl)->control_ddrio_1); writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, - &(ioregs_base->control_ddrio_2)); + (*ctrl)->control_ddrio_2); } /* DDR3 specific IO settings */ static void io_settings_ddr3(void) { u32 io_settings = 0; - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddr3ch1_0)); + (*ctrl)->control_ddr3ch1_0); writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch1_0)); + (*ctrl)->control_ddrch1_0); writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch1_1)); + (*ctrl)->control_ddrch1_1); writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddr3ch2_0)); + (*ctrl)->control_ddr3ch2_0); writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch2_0)); + (*ctrl)->control_ddrch2_0); writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch2_1)); + (*ctrl)->control_ddrch2_1); writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE, - &(ioregs_base->control_ddrio_0)); + (*ctrl)->control_ddrio_0); writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE, - &(ioregs_base->control_ddrio_1)); + (*ctrl)->control_ddrio_1); writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE, - &(ioregs_base->control_ddrio_2)); + (*ctrl)->control_ddrio_2); /* omap5432 does not use lpddr2 */ - writel(0x0, &(ioregs_base->control_lpddr2ch1_0)); - writel(0x0, &(ioregs_base->control_lpddr2ch1_1)); + writel(0x0, (*ctrl)->control_lpddr2ch1_0); + writel(0x0, (*ctrl)->control_lpddr2ch1_1); writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - &(ioregs_base->control_emif1_sdram_config_ext)); + (*ctrl)->control_emif1_sdram_config_ext); writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - &(ioregs_base->control_emif2_sdram_config_ext)); + (*ctrl)->control_emif2_sdram_config_ext); /* Disable DLL select */ - io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config)) + io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) & 0xFFEFFFFF); writel(io_settings, - &(ioregs_base->control_port_emif1_sdram_config)); + (*ctrl)->control_port_emif1_sdram_config); - io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config)) + io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) & 0xFFEFFFFF); writel(io_settings, - &(ioregs_base->control_port_emif2_sdram_config)); + (*ctrl)->control_port_emif2_sdram_config); } /* @@ -134,62 +129,60 @@ static void io_settings_ddr3(void) void do_io_settings(void) { u32 io_settings = 0, mask = 0; - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; /* Impedance settings EMMC, C2C 1,2, hsi2 */ mask = (ds_mask << 2) | (ds_mask << 8) | (ds_mask << 16) | (ds_mask << 18); - io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) & + io_settings = readl((*ctrl)->control_smart1io_padconf_0) & (~mask); io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) | (ds_45_ohm << 18) | (ds_60_ohm << 2); - writel(io_settings, &(ioregs_base->control_smart1io_padconf_0)); + writel(io_settings, (*ctrl)->control_smart1io_padconf_0); /* Impedance settings Mcspi2 */ mask = (ds_mask << 30); - io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) & + io_settings = readl((*ctrl)->control_smart1io_padconf_1) & (~mask); io_settings |= (ds_60_ohm << 30); - writel(io_settings, &(ioregs_base->control_smart1io_padconf_1)); + writel(io_settings, (*ctrl)->control_smart1io_padconf_1); /* Impedance settings C2C 3,4 */ mask = (ds_mask << 14) | (ds_mask << 16); - io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) & + io_settings = readl((*ctrl)->control_smart1io_padconf_2) & (~mask); io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16); - writel(io_settings, &(ioregs_base->control_smart1io_padconf_2)); + writel(io_settings, (*ctrl)->control_smart1io_padconf_2); /* Slew rate settings EMMC, C2C 1,2 */ mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18); - io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) & + io_settings = readl((*ctrl)->control_smart2io_padconf_0) & (~mask); io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18); - writel(io_settings, &(ioregs_base->control_smart2io_padconf_0)); + writel(io_settings, (*ctrl)->control_smart2io_padconf_0); /* Slew rate settings hsi2, Mcspi2 */ mask = (sc_mask << 24) | (sc_mask << 28); - io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) & + io_settings = readl((*ctrl)->control_smart2io_padconf_1) & (~mask); io_settings |= (sc_fast << 28) | (sc_fast << 24); - writel(io_settings, &(ioregs_base->control_smart2io_padconf_1)); + writel(io_settings, (*ctrl)->control_smart2io_padconf_1); /* Slew rate settings C2C 3,4 */ mask = (sc_mask << 16) | (sc_mask << 18); - io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) & + io_settings = readl((*ctrl)->control_smart2io_padconf_2) & (~mask); io_settings |= (sc_na << 16) | (sc_na << 18); - writel(io_settings, &(ioregs_base->control_smart2io_padconf_2)); + writel(io_settings, (*ctrl)->control_smart2io_padconf_2); /* impedance and slew rate settings for usb */ mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) | (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14); - io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) & + io_settings = readl((*ctrl)->control_smart3io_padconf_1) & (~mask); io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) | (ds_60_ohm << 23) | (sc_fast << 20) | (sc_fast << 17) | (sc_fast << 14); - writel(io_settings, &(ioregs_base->control_smart3io_padconf_1)); + writel(io_settings, (*ctrl)->control_smart3io_padconf_1); if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) io_settings_lpddr2(); @@ -197,25 +190,22 @@ void do_io_settings(void) io_settings_ddr3(); /* Efuse settings */ - writel(EFUSE_1, &(ioregs_base->control_efuse_1)); - writel(EFUSE_2, &(ioregs_base->control_efuse_2)); - writel(EFUSE_3, &(ioregs_base->control_efuse_3)); - writel(EFUSE_4, &(ioregs_base->control_efuse_4)); + writel(EFUSE_1, (*ctrl)->control_efuse_1); + writel(EFUSE_2, (*ctrl)->control_efuse_2); + writel(EFUSE_3, (*ctrl)->control_efuse_3); + writel(EFUSE_4, (*ctrl)->control_efuse_4); } #endif void config_data_eye_leveling_samples(u32 emif_base) { - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ if (emif_base == EMIF1_BASE) writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - &(ioregs_base->control_emif1_sdram_config_ext)); + (*ctrl)->control_emif1_sdram_config_ext); else if (emif_base == EMIF2_BASE) writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - &(ioregs_base->control_emif2_sdram_config_ext)); + (*ctrl)->control_emif2_sdram_config_ext); } void init_omap_revision(void) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index cdc4864..0f58b2f 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -304,3 +304,77 @@ struct prcm_regs const omap5_es1_prcm = { .prm_sldo_mm_setup = 0x4ae07bd4, .prm_sldo_mm_ctrl = 0x4ae07bd8, }; + +struct omap_sys_ctrl_regs const omap5_ctrl = { + .control_status = 0x4A002134, + .control_paconf_global = 0x4A002DA0, + .control_paconf_mode = 0x4A002DA4, + .control_smart1io_padconf_0 = 0x4A002DA8, + .control_smart1io_padconf_1 = 0x4A002DAC, + .control_smart1io_padconf_2 = 0x4A002DB0, + .control_smart2io_padconf_0 = 0x4A002DB4, + .control_smart2io_padconf_1 = 0x4A002DB8, + .control_smart2io_padconf_2 = 0x4A002DBC, + .control_smart3io_padconf_0 = 0x4A002DC0, + .control_smart3io_padconf_1 = 0x4A002DC4, + .control_pbias = 0x4A002E00, + .control_i2c_0 = 0x4A002E04, + .control_camera_rx = 0x4A002E08, + .control_hdmi_tx_phy = 0x4A002E0C, + .control_uniportm = 0x4A002E10, + .control_dsiphy = 0x4A002E14, + .control_mcbsplp = 0x4A002E18, + .control_usb2phycore = 0x4A002E1C, + .control_hdmi_1 = 0x4A002E20, + .control_hsi = 0x4A002E24, + .control_ddr3ch1_0 = 0x4A002E30, + .control_ddr3ch2_0 = 0x4A002E34, + .control_ddrch1_0 = 0x4A002E38, + .control_ddrch1_1 = 0x4A002E3C, + .control_ddrch2_0 = 0x4A002E40, + .control_ddrch2_1 = 0x4A002E44, + .control_lpddr2ch1_0 = 0x4A002E48, + .control_lpddr2ch1_1 = 0x4A002E4C, + .control_ddrio_0 = 0x4A002E50, + .control_ddrio_1 = 0x4A002E54, + .control_ddrio_2 = 0x4A002E58, + .control_hyst_1 = 0x4A002E5C, + .control_usbb_hsic_control = 0x4A002E60, + .control_c2c = 0x4A002E64, + .control_core_control_spare_rw = 0x4A002E68, + .control_core_control_spare_r = 0x4A002E6C, + .control_core_control_spare_r_c0 = 0x4A002E70, + .control_srcomp_north_side = 0x4A002E74, + .control_srcomp_south_side = 0x4A002E78, + .control_srcomp_east_side = 0x4A002E7C, + .control_srcomp_west_side = 0x4A002E80, + .control_srcomp_code_latch = 0x4A002E84, + .control_port_emif1_sdram_config = 0x4AE0C110, + .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, + .control_port_emif2_sdram_config = 0x4AE0C118, + .control_emif1_sdram_config_ext = 0x4AE0C144, + .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, + .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, + .control_padconf_mode = 0x4AE0CDA8, + .control_xtal_oscillator = 0x4AE0CDAC, + .control_i2c_2 = 0x4AE0CDB0, + .control_ckobuffer = 0x4AE0CDB4, + .control_wkup_control_spare_rw = 0x4AE0CDB8, + .control_wkup_control_spare_r = 0x4AE0CDBC, + .control_wkup_control_spare_r_c0 = 0x4AE0CDC0, + .control_srcomp_east_side_wkup = 0x4AE0CDC4, + .control_efuse_1 = 0x4AE0CDC8, + .control_efuse_2 = 0x4AE0CDCC, + .control_efuse_3 = 0x4AE0CDD0, + .control_efuse_4 = 0x4AE0CDD4, + .control_efuse_5 = 0x4AE0CDD8, + .control_efuse_6 = 0x4AE0CDDC, + .control_efuse_7 = 0x4AE0CDE0, + .control_efuse_8 = 0x4AE0CDE4, + .control_efuse_9 = 0x4AE0CDE8, + .control_efuse_10 = 0x4AE0CDEC, + .control_efuse_11 = 0x4AE0CDF0, + .control_efuse_12 = 0x4AE0CDF4, + .control_efuse_13 = 0x4AE0CDF8, +}; diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 73edd9d..5f321fe 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -132,34 +132,6 @@ struct s32ktimer { #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) #define DEVICE_GP 0x3 -struct omap_sys_ctrl_regs { - unsigned int pad1[129]; - unsigned int control_id_code; /* 0x4A002204 */ - unsigned int pad11[22]; - unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */ - unsigned int pad2[24]; /* 0x4a002264 */ - unsigned int control_status; /* 0x4a0022c4 */ - unsigned int pad3[22]; /* 0x4a0022c8 */ - unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */ - unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ - unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ - unsigned int pad4[260277]; - unsigned int control_pbiaslite; /* 0x4A100600 */ - unsigned int pad5[63]; - unsigned int control_efuse_1; /* 0x4A100700 */ - unsigned int control_efuse_2; /* 0x4A100704 */ -}; - -struct control_lpddr2io_regs { - unsigned int control_lpddr2io1_0; - unsigned int control_lpddr2io1_1; - unsigned int control_lpddr2io1_2; - unsigned int control_lpddr2io1_3; - unsigned int control_lpddr2io2_0; - unsigned int control_lpddr2io2_1; - unsigned int control_lpddr2io2_2; - unsigned int control_lpddr2io2_3; -}; #endif /* __ASSEMBLY__ */ /* @@ -181,7 +153,8 @@ struct control_lpddr2io_regs { #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) -#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20) +#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) +#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 4bf555a..a91da7d 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -131,87 +131,6 @@ struct s32ktimer { #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) #define DEVICE_GP 0x3 -struct omap_sys_ctrl_regs { - u32 pad0[77]; /* 0x4A002000 */ - u32 control_status; /* 0x4A002134 */ - u32 pad1[794]; /* 0x4A002138 */ - u32 control_paconf_global; /* 0x4A002DA0 */ - u32 control_paconf_mode; /* 0x4A002DA4 */ - u32 control_smart1io_padconf_0; /* 0x4A002DA8 */ - u32 control_smart1io_padconf_1; /* 0x4A002DAC */ - u32 control_smart1io_padconf_2; /* 0x4A002DB0 */ - u32 control_smart2io_padconf_0; /* 0x4A002DB4 */ - u32 control_smart2io_padconf_1; /* 0x4A002DB8 */ - u32 control_smart2io_padconf_2; /* 0x4A002DBC */ - u32 control_smart3io_padconf_0; /* 0x4A002DC0 */ - u32 control_smart3io_padconf_1; /* 0x4A002DC4 */ - u32 pad2[14]; - u32 control_pbias; /* 0x4A002E00 */ - u32 control_i2c_0; /* 0x4A002E04 */ - u32 control_camera_rx; /* 0x4A002E08 */ - u32 control_hdmi_tx_phy; /* 0x4A002E0C */ - u32 control_uniportm; /* 0x4A002E10 */ - u32 control_dsiphy; /* 0x4A002E14 */ - u32 control_mcbsplp; /* 0x4A002E18 */ - u32 control_usb2phycore; /* 0x4A002E1C */ - u32 control_hdmi_1; /*0x4A002E20*/ - u32 control_hsi; /*0x4A002E24*/ - u32 pad3[2]; - u32 control_ddr3ch1_0; /*0x4A002E30*/ - u32 control_ddr3ch2_0; /*0x4A002E34*/ - u32 control_ddrch1_0; /*0x4A002E38*/ - u32 control_ddrch1_1; /*0x4A002E3C*/ - u32 control_ddrch2_0; /*0x4A002E40*/ - u32 control_ddrch2_1; /*0x4A002E44*/ - u32 control_lpddr2ch1_0; /*0x4A002E48*/ - u32 control_lpddr2ch1_1; /*0x4A002E4C*/ - u32 control_ddrio_0; /*0x4A002E50*/ - u32 control_ddrio_1; /*0x4A002E54*/ - u32 control_ddrio_2; /*0x4A002E58*/ - u32 control_hyst_1; /*0x4A002E5C*/ - u32 control_usbb_hsic_control; /*0x4A002E60*/ - u32 control_c2c; /*0x4A002E64*/ - u32 control_core_control_spare_rw; /*0x4A002E68*/ - u32 control_core_control_spare_r; /*0x4A002E6C*/ - u32 control_core_control_spare_r_c0; /*0x4A002E70*/ - u32 control_srcomp_north_side; /*0x4A002E74*/ - u32 control_srcomp_south_side; /*0x4A002E78*/ - u32 control_srcomp_east_side; /*0x4A002E7C*/ - u32 control_srcomp_west_side; /*0x4A002E80*/ - u32 control_srcomp_code_latch; /*0x4A002E84*/ - u32 pad4[3679394]; - u32 control_port_emif1_sdram_config; /*0x4AE0C110*/ - u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/ - u32 control_port_emif2_sdram_config; /*0x4AE0C118*/ - u32 pad5[10]; - u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */ - u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */ - u32 pad6[789]; - u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */ - u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */ - u32 control_padconf_mode; /* 0x4AE0CDA8 */ - u32 control_xtal_oscillator; /* 0x4AE0CDAC */ - u32 control_i2c_2; /* 0x4AE0CDB0 */ - u32 control_ckobuffer; /* 0x4AE0CDB4 */ - u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */ - u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */ - u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */ - u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */ - u32 control_efuse_1; /* 0x4AE0CDC8 */ - u32 control_efuse_2; /* 0x4AE0CDCC */ - u32 control_efuse_3; /* 0x4AE0CDD0 */ - u32 control_efuse_4; /* 0x4AE0CDD4 */ - u32 control_efuse_5; /* 0x4AE0CDD8 */ - u32 control_efuse_6; /* 0x4AE0CDDC */ - u32 control_efuse_7; /* 0x4AE0CDE0 */ - u32 control_efuse_8; /* 0x4AE0CDE4 */ - u32 control_efuse_9; /* 0x4AE0CDE8 */ - u32 control_efuse_10; /* 0x4AE0CDEC */ - u32 control_efuse_11; /* 0x4AE0CDF0 */ - u32 control_efuse_12; /* 0x4AE0CDF4 */ - u32 control_efuse_13; /* 0x4AE0CDF8 */ -}; - /* Output impedance control */ #define ds_120_ohm 0x0 #define ds_60_ohm 0x1 @@ -274,7 +193,8 @@ struct omap_sys_ctrl_regs { #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20) +#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) /* Silicon revisions */ #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index eee6893..2115687 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -326,6 +326,94 @@ struct prcm_regs { u32 prm_vc_cfg_channel; }; +struct omap_sys_ctrl_regs { + u32 control_status; + u32 control_id_code; + u32 control_std_fuse_opp_bgap; + u32 control_ldosram_iva_voltage_ctrl; + u32 control_ldosram_mpu_voltage_ctrl; + u32 control_ldosram_core_voltage_ctrl; + u32 control_paconf_global; + u32 control_paconf_mode; + u32 control_smart1io_padconf_0; + u32 control_smart1io_padconf_1; + u32 control_smart1io_padconf_2; + u32 control_smart2io_padconf_0; + u32 control_smart2io_padconf_1; + u32 control_smart2io_padconf_2; + u32 control_smart3io_padconf_0; + u32 control_smart3io_padconf_1; + u32 control_pbias; + u32 control_i2c_0; + u32 control_camera_rx; + u32 control_hdmi_tx_phy; + u32 control_uniportm; + u32 control_dsiphy; + u32 control_mcbsplp; + u32 control_usb2phycore; + u32 control_hdmi_1; + u32 control_hsi; + u32 control_ddr3ch1_0; + u32 control_ddr3ch2_0; + u32 control_ddrch1_0; + u32 control_ddrch1_1; + u32 control_ddrch2_0; + u32 control_ddrch2_1; + u32 control_lpddr2ch1_0; + u32 control_lpddr2ch1_1; + u32 control_ddrio_0; + u32 control_ddrio_1; + u32 control_ddrio_2; + u32 control_lpddr2io1_0; + u32 control_lpddr2io1_1; + u32 control_lpddr2io1_2; + u32 control_lpddr2io1_3; + u32 control_lpddr2io2_0; + u32 control_lpddr2io2_1; + u32 control_lpddr2io2_2; + u32 control_lpddr2io2_3; + u32 control_hyst_1; + u32 control_usbb_hsic_control; + u32 control_c2c; + u32 control_core_control_spare_rw; + u32 control_core_control_spare_r; + u32 control_core_control_spare_r_c0; + u32 control_srcomp_north_side; + u32 control_srcomp_south_side; + u32 control_srcomp_east_side; + u32 control_srcomp_west_side; + u32 control_srcomp_code_latch; + u32 control_pbiaslite; + u32 control_port_emif1_sdram_config; + u32 control_port_emif1_lpddr2_nvm_config; + u32 control_port_emif2_sdram_config; + u32 control_emif1_sdram_config_ext; + u32 control_emif2_sdram_config_ext; + u32 control_smart1nopmio_padconf_0; + u32 control_smart1nopmio_padconf_1; + u32 control_padconf_mode; + u32 control_xtal_oscillator; + u32 control_i2c_2; + u32 control_ckobuffer; + u32 control_wkup_control_spare_rw; + u32 control_wkup_control_spare_r; + u32 control_wkup_control_spare_r_c0; + u32 control_srcomp_east_side_wkup; + u32 control_efuse_1; + u32 control_efuse_2; + u32 control_efuse_3; + u32 control_efuse_4; + u32 control_efuse_5; + u32 control_efuse_6; + u32 control_efuse_7; + u32 control_efuse_8; + u32 control_efuse_9; + u32 control_efuse_10; + u32 control_efuse_11; + u32 control_efuse_12; + u32 control_efuse_13; +}; + struct dpll_params { u32 m; u32 n; @@ -390,6 +478,9 @@ extern struct prcm_regs const omap4_prcm; extern struct dplls const **dplls_data; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; +extern struct omap_sys_ctrl_regs const **ctrl; +extern struct omap_sys_ctrl_regs const omap4_ctrl; +extern struct omap_sys_ctrl_regs const omap5_ctrl; void hw_data_init(void); diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index d0b2820..67cfcc2 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -95,18 +95,15 @@ static inline int omap_mmc_setup_gpio_in(int gpio, const char *label) static void omap4_vmmc_pbias_config(struct mmc *mmc) { u32 value = 0; - struct omap_sys_ctrl_regs *const ctrl = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - - value = readl(&ctrl->control_pbiaslite); + value = readl((*ctrl)->control_pbiaslite); value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); - writel(value, &ctrl->control_pbiaslite); + writel(value, (*ctrl)->control_pbiaslite); /* set VMMC to 3V */ twl6030_power_mmc_init(); - value = readl(&ctrl->control_pbiaslite); + value = readl((*ctrl)->control_pbiaslite); value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; - writel(value, &ctrl->control_pbiaslite); + writel(value, (*ctrl)->control_pbiaslite); } #endif @@ -114,26 +111,24 @@ static void omap4_vmmc_pbias_config(struct mmc *mmc) static void omap5_pbias_config(struct mmc *mmc) { u32 value = 0; - struct omap_sys_ctrl_regs *const ctrl = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - value = readl(&ctrl->control_pbias); + value = readl((*ctrl)->control_pbias); value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); value |= SDCARD_BIAS_HIZ_MODE; - writel(value, &ctrl->control_pbias); + writel(value, (*ctrl)->control_pbias); twl6035_mmc1_poweron_ldo(); - value = readl(&ctrl->control_pbias); + value = readl((*ctrl)->control_pbias); value &= ~SDCARD_BIAS_HIZ_MODE; value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ; - writel(value, &ctrl->control_pbias); + writel(value, (*ctrl)->control_pbias); - value = readl(&ctrl->control_pbias); + value = readl((*ctrl)->control_pbias); if (value & (1 << 23)) { value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); value |= SDCARD_BIAS_HIZ_MODE; - writel(value, &ctrl->control_pbias); + writel(value, (*ctrl)->control_pbias); } } #endif -- cgit v0.10.2 From ef1697e99f482b0e6a64df465ffff77251719abb Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 4 Feb 2013 04:22:05 +0000 Subject: ARM: OMAP5: Clean up iosettings code There is some code duplication in the ddr io settings code. This is avoided by moving the data to a Soc specific place and letting the code generic. This avoids unnessecary code addition for future socs. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 320d5bb..7ca6709 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -32,6 +32,7 @@ #include #include #include +#include struct prcm_regs const **prcm = (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; @@ -414,6 +415,24 @@ void enable_non_essential_clocks(void) MODULE_CLKCTRL_MODULEMODE_SHIFT); } +const struct ctrl_ioregs ioregs_omap5430 = { + .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, + .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, + .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, +}; + +const struct ctrl_ioregs ioregs_omap5432_es1 = { + .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + .ctrl_lpddr2ch = 0x0, + .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, + .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, + .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, + .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, + .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, +}; + void hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -438,3 +457,20 @@ void hw_data_init(void) *ctrl = &omap5_ctrl; } + +void get_ioregs(const struct ctrl_ioregs **regs) +{ + u32 omap_rev = omap_revision(); + + switch (omap_rev) { + case OMAP5430_ES1_0: + *regs = &ioregs_omap5430; + break; + case OMAP5432_ES1_0: + *regs = &ioregs_omap5432_es1; + break; + + default: + printf("\n INVALID OMAP REVISION "); + } +} diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 1863c69..dfc0e44 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -56,60 +56,47 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; /* LPDDR2 specific IO settings */ static void io_settings_lpddr2(void) { - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - (*ctrl)->control_ddrch1_0); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - (*ctrl)->control_ddrch1_1); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - (*ctrl)->control_ddrch2_0); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - (*ctrl)->control_ddrch2_1); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - (*ctrl)->control_lpddr2ch1_0); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - (*ctrl)->control_lpddr2ch1_1); - writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, - (*ctrl)->control_ddrio_0); - writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, - (*ctrl)->control_ddrio_1); - writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, - (*ctrl)->control_ddrio_2); + const struct ctrl_ioregs *ioregs; + + get_ioregs(&ioregs); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); + writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); + writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); + writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); } /* DDR3 specific IO settings */ static void io_settings_ddr3(void) { u32 io_settings = 0; + const struct ctrl_ioregs *ioregs; - writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, - (*ctrl)->control_ddr3ch1_0); - writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - (*ctrl)->control_ddrch1_0); - writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - (*ctrl)->control_ddrch1_1); - - writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, - (*ctrl)->control_ddr3ch2_0); - writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - (*ctrl)->control_ddrch2_0); - writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - (*ctrl)->control_ddrch2_1); - - writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE, - (*ctrl)->control_ddrio_0); - writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE, - (*ctrl)->control_ddrio_1); - writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE, - (*ctrl)->control_ddrio_2); + get_ioregs(&ioregs); + writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); + + writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); + + writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); + writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); + writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); /* omap5432 does not use lpddr2 */ - writel(0x0, (*ctrl)->control_lpddr2ch1_0); - writel(0x0, (*ctrl)->control_lpddr2ch1_1); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); - writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - (*ctrl)->control_emif1_sdram_config_ext); - writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - (*ctrl)->control_emif2_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext, + (*ctrl)->control_emif1_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext, + (*ctrl)->control_emif2_sdram_config_ext); /* Disable DLL select */ io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index a91da7d..873ccd7 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -229,5 +229,15 @@ struct omap_boot_parameters { unsigned char reset_reason; unsigned char ch_flags; }; + +struct ctrl_ioregs { + u32 ctrl_ddrch; + u32 ctrl_lpddr2ch; + u32 ctrl_ddr3ch; + u32 ctrl_ddrio_0; + u32 ctrl_ddrio_1; + u32 ctrl_ddrio_2; + u32 ctrl_emif_sdram_config_ext; +}; #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 2b3a071..201ed6f 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -58,6 +58,7 @@ void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); +void get_ioregs(const struct ctrl_ioregs **regs); /* * This is used to verify if the configuration header -- cgit v0.10.2 From eed7c0f727cf8255b193dfefd21d66dfd6dbae94 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Feb 2013 01:33:41 +0000 Subject: ARM: OMAP5: Add silicon id support for ES2.0 revision. Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs. Signed-off-by: R Sricharan Cc: Tom Rini Cc: Nishanth Menon diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index dfc0e44..8e66a96 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -204,17 +204,22 @@ void init_omap_revision(void) */ unsigned int rev = cortex_rev(); - switch (rev) { - case MIDR_CORTEX_A15_R0P0: - switch (readl(CONTROL_ID_CODE)) { - case OMAP5430_CONTROL_ID_CODE_ES1_0: - *omap_si_rev = OMAP5430_ES1_0; - break; - case OMAP5432_CONTROL_ID_CODE_ES1_0: - default: - *omap_si_rev = OMAP5432_ES1_0; - break; - } + switch (readl(CONTROL_ID_CODE)) { + case OMAP5430_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5430_ES1_0; + if (rev == MIDR_CORTEX_A15_R2P2) + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5432_ES1_0; + if (rev == MIDR_CORTEX_A15_R2P2) + *omap_si_rev = OMAP5432_ES2_0; + break; + case OMAP5430_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5432_ES2_0; break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 873ccd7..71935d8 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -57,7 +57,9 @@ /* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F +#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F /* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index ad9a875..a73630b 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -33,6 +33,7 @@ /* Cortex-A15 revisions */ #define MIDR_CORTEX_A15_R0P0 0x410FC0F0 +#define MIDR_CORTEX_A15_R2P2 0x412FC0F2 /* CCSIDR */ #define CCSIDR_LINE_SIZE_OFFSET 0 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2115687..4599167 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -542,4 +542,6 @@ static inline u32 omap_revision(void) #define OMAP5430_SILICON_ID_INVALID 0 #define OMAP5430_ES1_0 0x54300100 #define OMAP5432_ES1_0 0x54320100 +#define OMAP5430_ES2_0 0x54300200 +#define OMAP5432_ES2_0 0x54320200 #endif /* _OMAP_COMMON_H_ */ -- cgit v0.10.2 From afc2f9dcf1a4a478e51a84b1a162bca19c7b7715 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Feb 2013 01:33:42 +0000 Subject: ARM: OMAP5: clock: Add the prcm register changes required for ES2.0 PRCM register addresses are changed from ES1.0 to ES2.0 due to PER power domain getting moved to CORE power domain. So adding the nessecary register changes for the same. Signed-off-by: R Sricharan Reviewed-by: Tom Rini Cc: Tom Rini diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 7ca6709..baf1808 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -451,6 +451,11 @@ void hw_data_init(void) *omap_vcores = &omap5432_volts; break; + case OMAP5430_ES2_0: + case OMAP5432_ES2_0: + *prcm = &omap5_es2_prcm; + break; + default: printf("\n INVALID OMAP REVISION "); } diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 0f58b2f..58c9d50 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -378,3 +378,286 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_efuse_12 = 0x4AE0CDF4, .control_efuse_13 = 0x4AE0CDF8, }; + +struct prcm_regs const omap5_es2_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_h11_dpll_core = 0x4a004138, + .cm_div_h12_dpll_core = 0x4a00413c, + .cm_div_h13_dpll_core = 0x4a004140, + .cm_div_h14_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_div_h21_dpll_core = 0x4a004150, + .cm_div_h22_dpllcore = 0x4a004154, + .cm_div_h23_dpll_core = 0x4a004158, + .cm_div_h24_dpll_core = 0x4a00415c, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_h11_dpll_iva = 0x4a0041b8, + .cm_div_h12_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_h11_dpll_ddrphy = 0x4a004238, + .cm_div_h12_dpll_ddrphy = 0x4a00423c, + .cm_div_h13_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_h11_dpll_per = 0x4a008158, + .cm_div_h12_dpll_per = 0x4a00815c, + .cm_div_h13_dpll_per = 0x4a008160, + .cm_div_h14_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_bandgap_clkctrl = 0x4a008648, + + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_2_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, + .cm_l4per_clkstctrl = 0x4a009000, + .cm_l4per_dynamicdep = 0x4a009008, + .cm_l4per_adc_clkctrl = 0x4a009020, + .cm_l4per_gptimer10_clkctrl = 0x4a009028, + .cm_l4per_gptimer11_clkctrl = 0x4a009030, + .cm_l4per_gptimer2_clkctrl = 0x4a009038, + .cm_l4per_gptimer3_clkctrl = 0x4a009040, + .cm_l4per_gptimer4_clkctrl = 0x4a009048, + .cm_l4per_gptimer9_clkctrl = 0x4a009050, + .cm_l4per_elm_clkctrl = 0x4a009058, + .cm_l4per_gpio2_clkctrl = 0x4a009060, + .cm_l4per_gpio3_clkctrl = 0x4a009068, + .cm_l4per_gpio4_clkctrl = 0x4a009070, + .cm_l4per_gpio5_clkctrl = 0x4a009078, + .cm_l4per_gpio6_clkctrl = 0x4a009080, + .cm_l4per_hdq1w_clkctrl = 0x4a009088, + .cm_l4per_hecc1_clkctrl = 0x4a009090, + .cm_l4per_hecc2_clkctrl = 0x4a009098, + .cm_l4per_i2c1_clkctrl = 0x4a0090a0, + .cm_l4per_i2c2_clkctrl = 0x4a0090a8, + .cm_l4per_i2c3_clkctrl = 0x4a0090b0, + .cm_l4per_i2c4_clkctrl = 0x4a0090b8, + .cm_l4per_l4per_clkctrl = 0x4a0090c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0090d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0090d8, + .cm_l4per_mgate_clkctrl = 0x4a0090e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0090f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0090f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009100, + .cm_l4per_mcspi4_clkctrl = 0x4a009108, + .cm_l4per_gpio7_clkctrl = 0x4a009110, + .cm_l4per_gpio8_clkctrl = 0x4a009118, + .cm_l4per_mmcsd3_clkctrl = 0x4a009120, + .cm_l4per_mmcsd4_clkctrl = 0x4a009128, + .cm_l4per_msprohg_clkctrl = 0x4a009130, + .cm_l4per_slimbus2_clkctrl = 0x4a009138, + .cm_l4per_uart1_clkctrl = 0x4a009140, + .cm_l4per_uart2_clkctrl = 0x4a009148, + .cm_l4per_uart3_clkctrl = 0x4a009150, + .cm_l4per_uart4_clkctrl = 0x4a009158, + .cm_l4per_mmcsd5_clkctrl = 0x4a009160, + .cm_l4per_i2c5_clkctrl = 0x4a009168, + .cm_l4per_uart5_clkctrl = 0x4a009170, + .cm_l4per_uart6_clkctrl = 0x4a009178, + .cm_l4sec_clkstctrl = 0x4a009180, + .cm_l4sec_staticdep = 0x4a009184, + .cm_l4sec_dynamicdep = 0x4a009188, + .cm_l4sec_aes1_clkctrl = 0x4a0091a0, + .cm_l4sec_aes2_clkctrl = 0x4a0091a8, + .cm_l4sec_des3des_clkctrl = 0x4a0091b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8, + .cm_l4sec_rng_clkctrl = 0x4a0091c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8, + + /* cm2.ivahd */ + .cm_ivahd_clkstctrl = 0x4a009200, + .cm_ivahd_ivahd_clkctrl = 0x4a009220, + .cm_ivahd_sl2_clkctrl = 0x4a009228, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009300, + .cm_cam_iss_clkctrl = 0x4a009320, + .cm_cam_fdif_clkctrl = 0x4a009328, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009400, + .cm_dss_dss_clkctrl = 0x4a009420, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009500, + .cm_sgx_sgx_clkctrl = 0x4a009520, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009600, + + /* cm2.l3init */ + .cm_l3init_hsmmc1_clkctrl = 0x4a009628, + .cm_l3init_hsmmc2_clkctrl = 0x4a009630, + .cm_l3init_hsi_clkctrl = 0x4a009638, + .cm_l3init_hsusbhost_clkctrl = 0x4a009658, + .cm_l3init_hsusbotg_clkctrl = 0x4a009660, + .cm_l3init_hsusbtll_clkctrl = 0x4a009668, + .cm_l3init_p1500_clkctrl = 0x4a009678, + .cm_l3init_fsusb_clkctrl = 0x4a0096d0, + .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4ae0610c, + .cm_sys_clksel = 0x4ae06110, + .cm_wkup_clkstctrl = 0x4ae07900, + .cm_wkup_l4wkup_clkctrl = 0x4ae07920, + .cm_wkup_wdtimer1_clkctrl = 0x4ae07928, + .cm_wkup_wdtimer2_clkctrl = 0x4ae07930, + .cm_wkup_gpio1_clkctrl = 0x4ae07938, + .cm_wkup_gptimer1_clkctrl = 0x4ae07940, + .cm_wkup_gptimer12_clkctrl = 0x4ae07948, + .cm_wkup_synctimer_clkctrl = 0x4ae07950, + .cm_wkup_usim_clkctrl = 0x4ae07958, + .cm_wkup_sarram_clkctrl = 0x4ae07960, + .cm_wkup_keyboard_clkctrl = 0x4ae07978, + .cm_wkup_rtc_clkctrl = 0x4ae07980, + .cm_wkup_bandgap_clkctrl = 0x4ae07988, + .cm_wkupaon_scrm_clkctrl = 0x4ae07990, + .prm_vc_val_bypass = 0x4ae07ca0, + .prm_vc_cfg_i2c_mode = 0x4ae07cb4, + .prm_vc_cfg_i2c_clk = 0x4ae07cb8, + + .prm_sldo_core_setup = 0x4ae07cc4, + .prm_sldo_core_ctrl = 0x4ae07cc8, + .prm_sldo_mpu_setup = 0x4ae07ccc, + .prm_sldo_mpu_ctrl = 0x4ae07cd0, + .prm_sldo_mm_setup = 0x4ae07cd4, + .prm_sldo_mm_ctrl = 0x4ae07cd8, +}; diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 4599167..08395ca 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -44,6 +44,8 @@ struct prcm_regs { u32 cm_div_h12_dpll_core; u32 cm_div_h13_dpll_core; u32 cm_div_h14_dpll_core; + u32 cm_div_h21_dpll_core; + u32 cm_div_h24_dpll_core; u32 cm_ssc_deltamstep_dpll_core; u32 cm_ssc_modfreqdiv_dpll_core; u32 cm_emu_override_dpll_core; @@ -128,6 +130,7 @@ struct prcm_regs { u32 cm_div_m3_dpll_per; u32 cm_div_h11_dpll_per; u32 cm_div_h12_dpll_per; + u32 cm_div_h13_dpll_per; u32 cm_div_h14_dpll_per; u32 cm_ssc_deltamstep_dpll_per; u32 cm_ssc_modfreqdiv_dpll_per; @@ -474,6 +477,7 @@ struct vcores_data { extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; +extern struct prcm_regs const omap5_es2_prcm; extern struct prcm_regs const omap4_prcm; extern struct dplls const **dplls_data; extern struct vcores_data const **omap_vcores; -- cgit v0.10.2 From 47abc3df701d8bc26f311350aa523fc1d0f8ad4e Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Feb 2013 01:33:43 +0000 Subject: ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum Change OPP settings as per the latest 0.5 version of addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched here to add dummy dividers. While here correcting OPP_NOM mpu, core frequency for OMAP4430 ES2.x Note that OMAP5430 ES1.0 support is still kept alive and would be removed in a cleanup later. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Cc: Tom Rini Cc: Nishanth Menon diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 88e5336..818a963 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -103,10 +103,14 @@ void setup_post_dividers(u32 const base, const struct dpll_params *params) writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); if (params->m7_h14 >= 0) writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll); + if (params->h21 >= 0) + writel(params->h21, &dpll_regs->cm_div_h21_dpll); if (params->h22 >= 0) writel(params->h22, &dpll_regs->cm_div_h22_dpll); if (params->h23 >= 0) writel(params->h23, &dpll_regs->cm_div_h23_dpll); + if (params->h24 >= 0) + writel(params->h24, &dpll_regs->cm_div_h24_dpll); } static inline void do_bypass_dpll(u32 const base) @@ -319,11 +323,6 @@ void configure_mpu_dpll(void) CM_CLKSEL_DCC_EN_MASK); } - setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); - setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); - params = get_mpu_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 892d016..8d31d6d 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -49,115 +49,127 @@ struct omap_sys_ctrl_regs const **ctrl = * Please use this tool for creating the table for any new frequency. */ -/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */ +/* + * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF + * OMAP4460 OPP_NOM frequency + */ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { - {175, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {638, 34, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */ +/* + * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) + * OMAP4430 OPP_TURBO frequency + */ static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {125, 5, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -/* dpll locked at 1200 MHz - MPU clk at 600 MHz */ +/* + * dpll locked at 1200 MHz - MPU clk at 600 MHz + * OMAP4430 OPP_NOM frequency + */ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { - {50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {250, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 3, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {200, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +/* OMAP4460 OPP_NOM frequency */ static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */ - {800, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */ - {619, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */ - {125, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */ - {800, 26, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */ - {125, 5, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */ + {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ }; +/* OMAP4430 ES1 OPP_NOM frequency */ static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { - {127, 1, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */ - {762, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */ - {635, 13, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */ - {635, 15, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */ - {381, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */ - {254, 8, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */ - {496, 24, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */ + {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ }; +/* OMAP4430 ES2.X OPP_NOM frequency */ static const struct dpll_params core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { - {200, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */ - {800, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */ - {619, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */ - {125, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */ - {400, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */ - {800, 26, 2, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */ - {125, 5, 2, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */ + {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ }; static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { - {64, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 12 MHz */ - {768, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 13 MHz */ - {320, 6, 8, 6, 12, 9, 4, 5, -1, -1}, /* 16.8 MHz */ - {40, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 19.2 MHz */ - {384, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 26 MHz */ - {256, 8, 8, 6, 12, 9, 4, 5, -1, -1}, /* 27 MHz */ - {20, 0, 8, 6, 12, 9, 4, 5, -1, -1} /* 38.4 MHz */ + {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */ + {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */ + {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */ + {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */ + {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */ }; static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { - {931, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 12 MHz */ - {931, 12, -1, -1, 4, 7, -1, -1, -1, -1}, /* 13 MHz */ - {665, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 16.8 MHz */ - {727, 14, -1, -1, 4, 7, -1, -1, -1, -1}, /* 19.2 MHz */ - {931, 25, -1, -1, 4, 7, -1, -1, -1, -1}, /* 26 MHz */ - {931, 26, -1, -1, 4, 7, -1, -1, -1, -1}, /* 27 MHz */ - {291, 11, -1, -1, 4, 7, -1, -1, -1, -1} /* 38.4 MHz */ + {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {68, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {29, 7, 1, 1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = { - 750, 0, 1, 1, -1, -1, -1, -1, -1, -1 + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 }; static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {80, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {960, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {50, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {320, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {25, 0, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; struct dplls omap4430_dplls_es1 = { @@ -174,8 +186,8 @@ struct dplls omap4430_dplls_es1 = { }; struct dplls omap4430_dplls = { - .mpu = mpu_dpll_params_1600mhz, - .core = core_dpll_params_es2_1600mhz_ddr200mhz, + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_1600mhz, .per = per_dpll_params_1536mhz, .iva = iva_dpll_params_1862mhz, #ifdef CONFIG_SYS_OMAP_ABE_SYSCK diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index baf1808..7992b3f 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -43,133 +43,160 @@ struct vcores_data const **omap_vcores = struct omap_sys_ctrl_regs const **ctrl = (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL; +/* OPP HIGH FREQUENCY for ES2.0 */ static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { - {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = { - {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */ static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { - {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +/* OPP NOM FREQUENCY for ES1.0 */ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { - {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +/* OPP LOW FREQUENCY for ES1.0 */ static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { - {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = { - {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +/* OPP LOW FREQUENCY for ES2.0 */ +static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { + {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; static const struct dpll_params core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { - {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ - {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ - {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ + {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ + {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ + {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { + {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ + {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ + {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ }; static const struct dpll_params core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { - {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */ - {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */ - {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */ + {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */ + {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */ + {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = { + {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */ + {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */ + {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */ }; static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { - {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */ + {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { + {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ }; static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { - {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */ - {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */ - {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */ + {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = { - 750, 0, 1, 1, -1, -1, -1, -1, -1, -1 + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 }; static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; struct dplls omap5_dplls_es1 = { @@ -185,6 +212,19 @@ struct dplls omap5_dplls_es1 = { .usb = usb_dpll_params_1920mhz }; +struct dplls omap5_dplls_es2 = { + .mpu = mpu_dpll_params_1100mhz, + .core = core_dpll_params_2128mhz_ddr532_es2, + .per = per_dpll_params_768mhz_es2, + .iva = iva_dpll_params_2330mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz +}; + struct pmic_data palmas = { .base_offset = PALMAS_SMPS_BASE_VOLT_UV, .step = 10000, /* 10 mV represented in uV */ @@ -209,16 +249,16 @@ struct vcores_data omap5430_volts = { .mm.pmic = &palmas, }; -struct vcores_data omap5432_volts = { - .mpu.value = VDD_MPU_5432, +struct vcores_data omap5430_volts_es2 = { + .mpu.value = VDD_MPU_ES2, .mpu.addr = SMPS_REG_ADDR_12_MPU, .mpu.pmic = &palmas, - .core.value = VDD_CORE_5432, + .core.value = VDD_CORE_ES2, .core.addr = SMPS_REG_ADDR_8_CORE, .core.pmic = &palmas, - .mm.value = VDD_MM_5432, + .mm.value = VDD_MM_ES2, .mm.addr = SMPS_REG_ADDR_45_IVA, .mm.pmic = &palmas, }; @@ -440,20 +480,17 @@ void hw_data_init(void) switch (omap_rev) { case OMAP5430_ES1_0: - *prcm = &omap5_es1_prcm; - *dplls_data = &omap5_dplls_es1; - *omap_vcores = &omap5430_volts; - break; - case OMAP5432_ES1_0: *prcm = &omap5_es1_prcm; *dplls_data = &omap5_dplls_es1; - *omap_vcores = &omap5432_volts; + *omap_vcores = &omap5430_volts; break; case OMAP5430_ES2_0: case OMAP5432_ES2_0: *prcm = &omap5_es2_prcm; + *dplls_data = &omap5_dplls_es2; + *omap_vcores = &omap5430_volts_es2; break; default: diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 15362ae..6ee40be 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -176,9 +176,9 @@ /* CM_MPU_MPU_CLKCTRL */ #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) /* CM_WKUPAON_SCRM_CLKCTRL */ #define OPTFCLKEN_SCRM_PER_SHIFT 9 @@ -201,12 +201,25 @@ #define SMPS_REG_ADDR_8_CORE 0x37 /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ -#define VDD_MPU 1000 -#define VDD_MM 1000 +/* ES1.0 settings */ +#define VDD_MPU 1040 +#define VDD_MM 1040 #define VDD_CORE 1040 -#define VDD_MPU_5432 1150 -#define VDD_MM_5432 1150 -#define VDD_CORE_5432 1150 + +#define VDD_MPU_LOW 890 +#define VDD_MM_LOW 890 +#define VDD_CORE_LOW 890 + +/* ES2.0 settings */ +#define VDD_MPU_ES2 1060 +#define VDD_MM_ES2 1025 +#define VDD_CORE_ES2 1040 + +#define VDD_MPU_ES2_HIGH 1250 +#define VDD_MM_ES2_OD 1120 + +#define VDD_MPU_ES2_LOW 880 +#define VDD_MM_ES2_LOW 880 /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 08395ca..8a886ec 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -426,8 +426,10 @@ struct dpll_params { s8 m5_h12; s8 m6_h13; s8 m7_h14; + s8 h21; s8 h22; s8 h23; + s8 h24; }; struct dpll_regs { @@ -441,9 +443,11 @@ struct dpll_regs { u32 cm_div_m5_h12_dpll; u32 cm_div_m6_h13_dpll; u32 cm_div_m7_h14_dpll; - u32 reserved[3]; + u32 reserved[2]; + u32 cm_div_h21_dpll; u32 cm_div_h22_dpll; u32 cm_div_h23_dpll; + u32 cm_div_h24_dpll; }; struct dplls { -- cgit v0.10.2 From 9100edecf8379c357037c34044757202f85480b2 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 01:33:44 +0000 Subject: ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs Add pre calculated timing settings of LPDDR2 and DDR3 memories present in OMAP5430 and OMAP5432 ES2.0 versions. Also adding the DDR pad io settings required for OMAP543X SOCs here. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini Cc: Tom Rini diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 7992b3f..faf5eff 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -473,6 +473,16 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = { .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, }; +const struct ctrl_ioregs ioregs_omap5432_es2 = { + .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, + .ctrl_lpddr2ch = 0x0, + .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, + .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, +}; + void hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -506,11 +516,15 @@ void get_ioregs(const struct ctrl_ioregs **regs) switch (omap_rev) { case OMAP5430_ES1_0: + case OMAP5430_ES2_0: *regs = &ioregs_omap5430; break; case OMAP5432_ES1_0: *regs = &ioregs_omap5432_es1; break; + case OMAP5432_ES2_0: + *regs = &ioregs_omap5432_es2; + break; default: printf("\n INVALID OMAP REVISION "); diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 687800f..2ef7fcd 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -67,6 +67,25 @@ const struct emif_regs emif_regs_532_mhz_2cs = { .emif_ddr_ext_phy_ctrl_5 = 0x04010040 }; +const struct emif_regs emif_regs_532_mhz_2cs_es2 = { + .sdram_config_init = 0x80800EBA, + .sdram_config = 0x808022BA, + .ref_ctrl = 0x0000081A, + .sdram_tim1 = 0x772F6873, + .sdram_tim2 = 0x304a129a, + .sdram_tim3 = 0x02f7e45f, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x100b3215, + .temp_alert_config = 0x08000a05, + .emif_ddr_phy_ctlr_1_init = 0x0E30400d, + .emif_ddr_phy_ctlr_1 = 0x0E30400d, + .emif_ddr_ext_phy_ctrl_1 = 0x04020080, + .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3, + .emif_ddr_ext_phy_ctrl_3 = 0x518A3146, + .emif_ddr_ext_phy_ctrl_4 = 0x0014628C, + .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33, +}; + const struct emif_regs emif_regs_266_mhz_2cs = { .sdram_config_init = 0x80800EBA, .sdram_config = 0x808022BA, @@ -109,6 +128,29 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { .emif_rd_wr_exec_thresh = 0x00000305 }; +const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x1007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0030400A, + .emif_ddr_phy_ctlr_1 = 0x0034400A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00000000, + .emif_ddr_ext_phy_ctrl_3 = 0x00000000, + .emif_ddr_ext_phy_ctrl_4 = 0x00000000, + .emif_ddr_ext_phy_ctrl_5 = 0x4350D435, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x40000305 +}; + const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, @@ -125,8 +167,12 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) case OMAP5432_ES1_0: *regs = &emif_regs_ddr3_532_mhz_1cs; break; + case OMAP5430_ES2_0: + *regs = &emif_regs_532_mhz_2cs_es2; + break; + case OMAP5432_ES2_0: default: - *regs = &emif_regs_ddr3_532_mhz_1cs; + *regs = &emif_regs_ddr3_532_mhz_1cs_es2; } } @@ -210,6 +256,28 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000057 }; +const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x50D4350D, + 0x00000D43, + 0x04010040, + 0x01004010, + 0x00001004, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80080080, + 0x00800800, + 0x08102040, + 0x00000002, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000057 +}; + const struct lpddr2_mr_regs mr_regs = { .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8, .mr2 = 0x6, @@ -222,13 +290,16 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) { switch (omap_revision()) { case OMAP5430_ES1_0: + case OMAP5430_ES2_0: *regs = ext_phy_ctrl_const_base; break; case OMAP5432_ES1_0: *regs = ddr3_ext_phy_ctrl_const_base_es1; break; + case OMAP5432_ES2_0: default: - *regs = ddr3_ext_phy_ctrl_const_base_es1; + *regs = ddr3_ext_phy_ctrl_const_base_es2; + } } diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 71935d8..ba2775b 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -168,6 +168,12 @@ struct s32ktimer { #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 +#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 +#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 +#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 + #define EFUSE_1 0x45145100 #define EFUSE_2 0x45145100 #define EFUSE_3 0x45145100 diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index fd530bb..9d72fe3 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -519,6 +519,7 @@ #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7 /* DMM */ #define DMM_BASE 0x4E000040 -- cgit v0.10.2 From d4d986ee27fe6a78e50d4789d5b08b87a5e64892 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 01:33:45 +0000 Subject: ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini Cc: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index e5a5eb6..60af7eb 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -33,6 +33,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -100,6 +101,10 @@ void spl_display_print(void) } #endif +void __weak srcomp_enable(void) +{ +} + /* * Routine: s_init * Description: Does early system init of watchdog, muxing, andclocks @@ -126,6 +131,7 @@ void s_init(void) watchdog_init(); set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD + srcomp_enable(); setup_clocks_for_console(); gd = &gdata; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 8e66a96..f083198 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -182,6 +183,121 @@ void do_io_settings(void) writel(EFUSE_3, (*ctrl)->control_efuse_3); writel(EFUSE_4, (*ctrl)->control_efuse_4); } + +static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { + {0x45, 0x1}, /* 12 MHz */ + {-1, -1}, /* 13 MHz */ + {0x63, 0x2}, /* 16.8 MHz */ + {0x57, 0x2}, /* 19.2 MHz */ + {0x20, 0x1}, /* 26 MHz */ + {-1, -1}, /* 27 MHz */ + {0x41, 0x3} /* 38.4 MHz */ +}; + +void srcomp_enable(void) +{ + u32 srcomp_value, mul_factor, div_factor, clk_val, i; + u32 sysclk_ind = get_sys_clk_index(); + u32 omap_rev = omap_revision(); + + mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; + div_factor = srcomp_parameters[sysclk_ind].divide_factor; + + for (i = 0; i < 4; i++) { + srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= + ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK); + srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | + (div_factor << DIVIDE_FACTOR_XS_SHIFT); + writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4); + } + + if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) { + clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); + + for (i = 0; i < 4; i++) { + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~PWRDWN_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + + while (((readl((*ctrl)->control_srcomp_north_side + i*4) + & SRCODE_READ_XS_MASK) >> + SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + } else { + srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK | + DIVIDE_FACTOR_XS_MASK); + srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | + (div_factor << DIVIDE_FACTOR_XS_SHIFT); + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + for (i = 0; i < 4; i++) { + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); + + clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl); + + for (i = 0; i < 4; i++) { + while (((readl((*ctrl)->control_srcomp_north_side + i*4) + & SRCODE_READ_XS_MASK) >> + SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + + while (((readl((*ctrl)->control_srcomp_east_side_wkup) & + SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + } +} #endif void config_data_eye_leveling_samples(u32 emif_base) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 58c9d50..5e5abcc 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -149,6 +149,7 @@ struct prcm_regs const omap5_es1_prcm = { /* cm2.core */ .cm_coreaon_bandgap_clkctrl = 0x4a008648, + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, .cm_l3_1_clkstctrl = 0x4a008700, .cm_l3_1_dynamicdep = 0x4a008708, .cm_l3_1_l3_1_clkctrl = 0x4a008720, @@ -294,6 +295,7 @@ struct prcm_regs const omap5_es1_prcm = { .cm_wkup_rtc_clkctrl = 0x4ae07880, .cm_wkup_bandgap_clkctrl = 0x4ae07888, .cm_wkupaon_scrm_clkctrl = 0x4ae07890, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, @@ -502,7 +504,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, .cm_coreaon_bandgap_clkctrl = 0x4a008648, - + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, /* cm2.core */ .cm_l3_1_clkstctrl = 0x4a008700, @@ -650,6 +652,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_wkup_rtc_clkctrl = 0x4ae07980, .cm_wkup_bandgap_clkctrl = 0x4ae07988, .cm_wkupaon_scrm_clkctrl = 0x4ae07990, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, .prm_vc_val_bypass = 0x4ae07ca0, .prm_vc_cfg_i2c_mode = 0x4ae07cb4, .prm_vc_cfg_i2c_clk = 0x4ae07cb8, diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 6ee40be..cfde374 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -186,6 +186,10 @@ #define OPTFCLKEN_SCRM_CORE_SHIFT 8 #define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) +/* CM_COREAON_IO_SRCOMP_CLKCTRL */ +#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 +#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) + /* Clock frequencies */ #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index ba2775b..d29be93 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -229,7 +229,26 @@ struct s32ktimer { #define CH_FLAGS_CHFLASH (0x1 << 2) #define CH_FLAGS_CHMMCSD (0x1 << 3) +/* CONTROL_SRCOMP_XXX_SIDE */ +#define OVERRIDE_XS_SHIFT 30 +#define OVERRIDE_XS_MASK (1 << 30) +#define SRCODE_READ_XS_SHIFT 12 +#define SRCODE_READ_XS_MASK (0xff << 12) +#define PWRDWN_XS_SHIFT 11 +#define PWRDWN_XS_MASK (1 << 11) +#define DIVIDE_FACTOR_XS_SHIFT 4 +#define DIVIDE_FACTOR_XS_MASK (0x7f << 4) +#define MULTIPLY_FACTOR_XS_SHIFT 1 +#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) +#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 +#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) + #ifndef __ASSEMBLY__ +struct srcomp_params { + s8 divide_factor; + s8 multiply_factor; +}; + struct omap_boot_parameters { char *boot_message; unsigned int mem_boot_descriptor; diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 201ed6f..b8d841d 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -59,6 +59,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void get_ioregs(const struct ctrl_ioregs **regs); +void srcomp_enable(void); /* * This is used to verify if the configuration header diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8a886ec..0af0c33 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -153,6 +153,7 @@ struct prcm_regs { /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; + u32 cm_coreaon_io_srcomp_clkctrl; u32 cm_l3_1_clkstctrl; u32 cm_l3_1_dynamicdep; u32 cm_l3_1_l3_1_clkctrl; @@ -300,6 +301,7 @@ struct prcm_regs { u32 cm_wkup_rtc_clkctrl; u32 cm_wkup_bandgap_clkctrl; u32 cm_wkupaon_scrm_clkctrl; + u32 cm_wkupaon_io_srcomp_clkctrl; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; -- cgit v0.10.2 From d4e4129c31cf571824a1b34aa0b9210c876be718 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sun, 17 Feb 2013 23:33:37 +0000 Subject: arm: dra7xx: clock: Add the prcm changes PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX. So adding the necessary register changes for DRA7XX socs. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 8d31d6d..3b27bc1 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -290,7 +290,7 @@ void enable_basic_clocks(void) }; u32 const clk_modules_hw_auto_essential[] = { - (*prcm)->cm_l3_2_gpmc_clkctrl, + (*prcm)->cm_l3_gpmc_clkctrl, (*prcm)->cm_memif_emif_1_clkctrl, (*prcm)->cm_memif_emif_2_clkctrl, (*prcm)->cm_l4cfg_l4_cfg_clkctrl, diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c index c58ce8d..7225a30 100644 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -153,7 +153,7 @@ struct prcm_regs const omap4_prcm = { .cm_l3_2_clkstctrl = 0x4a008800, .cm_l3_2_dynamicdep = 0x4a008808, .cm_l3_2_l3_2_clkctrl = 0x4a008820, - .cm_l3_2_gpmc_clkctrl = 0x4a008828, + .cm_l3_gpmc_clkctrl = 0x4a008828, .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, .cm_mpu_m3_clkstctrl = 0x4a008900, .cm_mpu_m3_staticdep = 0x4a008904, diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index faf5eff..9b6b2db 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -278,7 +278,7 @@ void enable_basic_clocks(void) }; u32 const clk_modules_hw_auto_essential[] = { - (*prcm)->cm_l3_2_gpmc_clkctrl, + (*prcm)->cm_l3_gpmc_clkctrl, (*prcm)->cm_memif_emif_1_clkctrl, (*prcm)->cm_memif_emif_2_clkctrl, (*prcm)->cm_l4cfg_l4_cfg_clkctrl, @@ -503,6 +503,10 @@ void hw_data_init(void) *omap_vcores = &omap5430_volts_es2; break; + case DRA752_ES1_0: + *prcm = &dra7xx_prcm; + break; + default: printf("\n INVALID OMAP REVISION "); } diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index f083198..d291da9 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -351,7 +351,12 @@ void reset_cpu(ulong ignored) * So use cold reset in case instead. */ if (omap_rev == OMAP5430_ES1_0) - writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL); + writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl); else - writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); + writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl); +} + +u32 warm_reset(void) +{ + return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK; } diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 5e5abcc..ade9875 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -156,7 +156,7 @@ struct prcm_regs const omap5_es1_prcm = { .cm_l3_2_clkstctrl = 0x4a008800, .cm_l3_2_dynamicdep = 0x4a008808, .cm_l3_2_l3_2_clkctrl = 0x4a008820, - .cm_l3_2_gpmc_clkctrl = 0x4a008828, + .cm_l3_gpmc_clkctrl = 0x4a008828, .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, .cm_mpu_m3_clkstctrl = 0x4a008900, .cm_mpu_m3_staticdep = 0x4a008904, @@ -296,6 +296,8 @@ struct prcm_regs const omap5_es1_prcm = { .cm_wkup_bandgap_clkctrl = 0x4ae07888, .cm_wkupaon_scrm_clkctrl = 0x4ae07890, .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, + .prm_rstctrl = 0x4ae07b00, + .prm_rstst = 0x4ae07b04, .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, @@ -513,7 +515,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3_2_clkstctrl = 0x4a008800, .cm_l3_2_dynamicdep = 0x4a008808, .cm_l3_2_l3_2_clkctrl = 0x4a008820, - .cm_l3_2_gpmc_clkctrl = 0x4a008828, + .cm_l3_gpmc_clkctrl = 0x4a008828, .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, .cm_mpu_m3_clkstctrl = 0x4a008900, .cm_mpu_m3_staticdep = 0x4a008904, @@ -653,6 +655,8 @@ struct prcm_regs const omap5_es2_prcm = { .cm_wkup_bandgap_clkctrl = 0x4ae07988, .cm_wkupaon_scrm_clkctrl = 0x4ae07990, .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, + .prm_rstctrl = 0x4ae07c00, + .prm_rstst = 0x4ae07c04, .prm_vc_val_bypass = 0x4ae07ca0, .prm_vc_cfg_i2c_mode = 0x4ae07cb4, .prm_vc_cfg_i2c_clk = 0x4ae07cb8, @@ -664,3 +668,219 @@ struct prcm_regs const omap5_es2_prcm = { .prm_sldo_mm_setup = 0x4ae07cd4, .prm_sldo_mm_ctrl = 0x4ae07cd8, }; + +struct prcm_regs const dra7xx_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a005100, + .cm_clksel_abe = 0x4a005108, + .cm_dll_ctrl = 0x4a005110, + .cm_clkmode_dpll_core = 0x4a005120, + .cm_idlest_dpll_core = 0x4a005124, + .cm_autoidle_dpll_core = 0x4a005128, + .cm_clksel_dpll_core = 0x4a00512c, + .cm_div_m2_dpll_core = 0x4a005130, + .cm_div_m3_dpll_core = 0x4a005134, + .cm_div_h11_dpll_core = 0x4a005138, + .cm_div_h12_dpll_core = 0x4a00513c, + .cm_div_h13_dpll_core = 0x4a005140, + .cm_div_h14_dpll_core = 0x4a005144, + .cm_ssc_deltamstep_dpll_core = 0x4a005148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c, + .cm_div_h21_dpll_core = 0x4a005150, + .cm_div_h22_dpllcore = 0x4a005154, + .cm_div_h23_dpll_core = 0x4a005158, + .cm_div_h24_dpll_core = 0x4a00515c, + .cm_clkmode_dpll_mpu = 0x4a005160, + .cm_idlest_dpll_mpu = 0x4a005164, + .cm_autoidle_dpll_mpu = 0x4a005168, + .cm_clksel_dpll_mpu = 0x4a00516c, + .cm_div_m2_dpll_mpu = 0x4a005170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a005188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c, + .cm_bypclk_dpll_mpu = 0x4a00519c, + .cm_clkmode_dpll_iva = 0x4a0051a0, + .cm_idlest_dpll_iva = 0x4a0051a4, + .cm_autoidle_dpll_iva = 0x4a0051a8, + .cm_clksel_dpll_iva = 0x4a0051ac, + .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc, + .cm_bypclk_dpll_iva = 0x4a0051dc, + .cm_clkmode_dpll_abe = 0x4a0051e0, + .cm_idlest_dpll_abe = 0x4a0051e4, + .cm_autoidle_dpll_abe = 0x4a0051e8, + .cm_clksel_dpll_abe = 0x4a0051ec, + .cm_div_m2_dpll_abe = 0x4a0051f0, + .cm_div_m3_dpll_abe = 0x4a0051f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a005208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c, + .cm_clkmode_dpll_ddrphy = 0x4a005210, + .cm_idlest_dpll_ddrphy = 0x4a005214, + .cm_autoidle_dpll_ddrphy = 0x4a005218, + .cm_clksel_dpll_ddrphy = 0x4a00521c, + .cm_div_m2_dpll_ddrphy = 0x4a005220, + .cm_div_h11_dpll_ddrphy = 0x4a005228, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, + .cm_clkmode_dpll_dsp = 0x4a005234, + .cm_shadow_freq_config1 = 0x4a005260, + + /* cm1.mpu */ + .cm_mpu_mpu_clkctrl = 0x4a005320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a005400, + .cm_dsp_dsp_clkctrl = 0x4a005420, + + /* cm2.ckgen */ + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_h11_dpll_per = 0x4a008158, + .cm_div_h12_dpll_per = 0x4a00815c, + .cm_div_h13_dpll_per = 0x4a008160, + .cm_div_h14_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_pcie_ref = 0x4a008200, + .cm_clkmode_apll_pcie = 0x4a00821c, + .cm_idlest_apll_pcie = 0x4a008220, + .cm_div_m2_apll_pcie = 0x4a008224, + .cm_clkvcoldo_apll_pcie = 0x4a008228, + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_gpmc_clkctrl = 0x4a008728, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, + + /* cm2.ivahd */ + .cm_ivahd_clkstctrl = 0x4a008f00, + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_vip1_clkctrl = 0x4a009020, + .cm_cam_vip2_clkctrl = 0x4a009028, + .cm_cam_vip3_clkctrl = 0x4a009030, + .cm_cam_lvdsrx_clkctrl = 0x4a009038, + .cm_cam_csi1_clkctrl = 0x4a009040, + .cm_cam_csi2_clkctrl = 0x4a009048, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + + /* cm2.l3init */ + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsusbhost_clkctrl = 0x4a009340, + .cm_l3init_hsusbotg_clkctrl = 0x4a009348, + .cm_l3init_hsusbtll_clkctrl = 0x4a009350, + .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009700, + .cm_l4per_dynamicdep = 0x4a009708, + .cm_l4per_gptimer10_clkctrl = 0x4a009728, + .cm_l4per_gptimer11_clkctrl = 0x4a009730, + .cm_l4per_gptimer2_clkctrl = 0x4a009738, + .cm_l4per_gptimer3_clkctrl = 0x4a009740, + .cm_l4per_gptimer4_clkctrl = 0x4a009748, + .cm_l4per_gptimer9_clkctrl = 0x4a009750, + .cm_l4per_elm_clkctrl = 0x4a009758, + .cm_l4per_gpio2_clkctrl = 0x4a009760, + .cm_l4per_gpio3_clkctrl = 0x4a009768, + .cm_l4per_gpio4_clkctrl = 0x4a009770, + .cm_l4per_gpio5_clkctrl = 0x4a009778, + .cm_l4per_gpio6_clkctrl = 0x4a009780, + .cm_l4per_hdq1w_clkctrl = 0x4a009788, + .cm_l4per_i2c1_clkctrl = 0x4a0097a0, + .cm_l4per_i2c2_clkctrl = 0x4a0097a8, + .cm_l4per_i2c3_clkctrl = 0x4a0097b0, + .cm_l4per_i2c4_clkctrl = 0x4a0097b8, + .cm_l4per_l4per_clkctrl = 0x4a0097c0, + .cm_l4per_mcspi1_clkctrl = 0x4a0097f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0097f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009800, + .cm_l4per_mcspi4_clkctrl = 0x4a009808, + .cm_l4per_gpio7_clkctrl = 0x4a009810, + .cm_l4per_gpio8_clkctrl = 0x4a009818, + .cm_l4per_mmcsd3_clkctrl = 0x4a009820, + .cm_l4per_mmcsd4_clkctrl = 0x4a009828, + .cm_l4per_uart1_clkctrl = 0x4a009840, + .cm_l4per_uart2_clkctrl = 0x4a009848, + .cm_l4per_uart3_clkctrl = 0x4a009850, + .cm_l4per_uart4_clkctrl = 0x4a009858, + .cm_l4per_uart5_clkctrl = 0x4a009870, + .cm_l4sec_clkstctrl = 0x4a009880, + .cm_l4sec_staticdep = 0x4a009884, + .cm_l4sec_dynamicdep = 0x4a009888, + .cm_l4sec_aes1_clkctrl = 0x4a0098a0, + .cm_l4sec_aes2_clkctrl = 0x4a0098a8, + .cm_l4sec_des3des_clkctrl = 0x4a0098b0, + .cm_l4sec_rng_clkctrl = 0x4a0098c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4ae0610c, + .cm_sys_clksel = 0x4ae06110, + .cm_wkup_clkstctrl = 0x4ae07800, + .cm_wkup_l4wkup_clkctrl = 0x4ae07820, + .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, + .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, + .cm_wkup_gpio1_clkctrl = 0x4ae07838, + .cm_wkup_gptimer1_clkctrl = 0x4ae07840, + .cm_wkup_gptimer12_clkctrl = 0x4ae07848, + .cm_wkup_sarram_clkctrl = 0x4ae07860, + .cm_wkup_keyboard_clkctrl = 0x4ae07878, + .cm_wkupaon_scrm_clkctrl = 0x4ae07890, + .prm_rstctrl = 0x4ae07d00, + .prm_rstst = 0x4ae07d04, + .prm_vc_val_bypass = 0x4ae07da0, + .prm_vc_cfg_i2c_mode = 0x4ae07db4, + .prm_vc_cfg_i2c_clk = 0x4ae07db8, +}; diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 0af0c33..54700f7 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -85,6 +85,7 @@ struct prcm_regs { u32 cm_div_h12_dpll_ddrphy; u32 cm_div_h13_dpll_ddrphy; u32 cm_ssc_deltamstep_dpll_ddrphy; + u32 cm_clkmode_dpll_dsp; u32 cm_shadow_freq_config1; u32 cm_mpu_mpu_clkctrl; @@ -143,6 +144,11 @@ struct prcm_regs { u32 cm_ssc_deltamstep_dpll_usb; u32 cm_ssc_modfreqdiv_dpll_usb; u32 cm_clkdcoldo_dpll_usb; + u32 cm_clkmode_dpll_pcie_ref; + u32 cm_clkmode_apll_pcie; + u32 cm_idlest_apll_pcie; + u32 cm_div_m2_apll_pcie; + u32 cm_clkvcoldo_apll_pcie; u32 cm_clkmode_dpll_unipro; u32 cm_idlest_dpll_unipro; u32 cm_autoidle_dpll_unipro; @@ -160,7 +166,7 @@ struct prcm_regs { u32 cm_l3_2_clkstctrl; u32 cm_l3_2_dynamicdep; u32 cm_l3_2_l3_2_clkctrl; - u32 cm_l3_2_gpmc_clkctrl; + u32 cm_l3_gpmc_clkctrl; u32 cm_l3_2_ocmc_ram_clkctrl; u32 cm_mpu_m3_clkstctrl; u32 cm_mpu_m3_staticdep; @@ -205,6 +211,12 @@ struct prcm_regs { u32 cm_cam_clkstctrl; u32 cm_cam_iss_clkctrl; u32 cm_cam_fdif_clkctrl; + u32 cm_cam_vip1_clkctrl; + u32 cm_cam_vip2_clkctrl; + u32 cm_cam_vip3_clkctrl; + u32 cm_cam_lvdsrx_clkctrl; + u32 cm_cam_csi1_clkctrl; + u32 cm_cam_csi2_clkctrl; /* cm2.dss */ u32 cm_dss_clkstctrl; @@ -302,6 +314,8 @@ struct prcm_regs { u32 cm_wkup_bandgap_clkctrl; u32 cm_wkupaon_scrm_clkctrl; u32 cm_wkupaon_io_srcomp_clkctrl; + u32 prm_rstctrl; + u32 prm_rstst; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; @@ -485,6 +499,7 @@ extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; extern struct prcm_regs const omap5_es2_prcm; extern struct prcm_regs const omap4_prcm; +extern struct prcm_regs const dra7xx_prcm; extern struct dplls const **dplls_data; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; -- cgit v0.10.2 From ea8eff1fe080bef7c5cdfea734d8ac4cdd957c4c Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 21:29:05 +0000 Subject: arm: dra7xx: clock: Add the dplls data A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 818a963..9ed1899 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -55,11 +55,12 @@ const u32 sys_clk_array[8] = { 26000000, /* 26 MHz */ 27000000, /* 27 MHz */ 38400000, /* 38.4 MHz */ + 20000000, /* 20 MHz */ }; static inline u32 __get_sys_clk_index(void) { - u32 ind; + s8 ind; /* * For ES1 the ROM code calibration of sys clock is not reliable * due to hw issue. So, use hard-coded value. If this value is not @@ -73,6 +74,13 @@ static inline u32 __get_sys_clk_index(void) /* SYS_CLKSEL - 1 to match the dpll param array indices */ ind = (readl((*prcm)->cm_sys_clksel) & CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; + /* + * SYS_CLKSEL value for 20MHz is 0. This is introduced newly + * in DRA7XX socs. SYS_CLKSEL -1 will be greater than + * NUM_SYS_CLK. So considering the last 3 bits as the index + * for the dpll param array. + */ + ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK; } return ind; } @@ -201,12 +209,25 @@ const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data) #endif } +static const struct dpll_params *get_ddr_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->ddr) + return NULL; + return &dpll_data->ddr[sysclk_ind]; +} + static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { u32 temp, M, N; struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + if (!params) + return; + temp = readl(&dpll_regs->cm_clksel_dpll); if (check_for_lock(base)) { @@ -397,6 +418,9 @@ static void setup_dplls(void) #ifdef CONFIG_USB_EHCI_OMAP setup_usb_dpll(); #endif + params = get_ddr_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, + params, DPLL_LOCK, "ddr"); } #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 3b27bc1..7551b98 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -182,7 +182,8 @@ struct dplls omap4430_dplls_es1 = { #else .abe = &abe_dpll_params_32k_196608khz, #endif - .usb = usb_dpll_params_1920mhz + .usb = usb_dpll_params_1920mhz, + .ddr = NULL }; struct dplls omap4430_dplls = { @@ -195,7 +196,8 @@ struct dplls omap4430_dplls = { #else .abe = &abe_dpll_params_32k_196608khz, #endif - .usb = usb_dpll_params_1920mhz + .usb = usb_dpll_params_1920mhz, + .ddr = NULL }; struct dplls omap4460_dplls = { @@ -208,7 +210,8 @@ struct dplls omap4460_dplls = { #else .abe = &abe_dpll_params_32k_196608khz, #endif - .usb = usb_dpll_params_1920mhz + .usb = usb_dpll_params_1920mhz, + .ddr = NULL }; struct pmic_data twl6030_4430es1 = { diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 9b6b2db..b82205a 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -98,6 +98,17 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { + {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ + {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ +}; + static const struct dpll_params core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ @@ -121,6 +132,18 @@ static const struct dpll_params }; static const struct dpll_params + core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = { + {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */ + {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */ + {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */ + {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */ +}; + +static const struct dpll_params core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -162,6 +185,17 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ }; +static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { + {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ + {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */ +}; + static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -196,7 +230,19 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ + {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ +}; + +static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = { + {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ + {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ }; struct dplls omap5_dplls_es1 = { @@ -209,7 +255,8 @@ struct dplls omap5_dplls_es1 = { #else .abe = &abe_dpll_params_32k_196608khz, #endif - .usb = usb_dpll_params_1920mhz + .usb = usb_dpll_params_1920mhz, + .ddr = NULL }; struct dplls omap5_dplls_es2 = { @@ -222,7 +269,16 @@ struct dplls omap5_dplls_es2 = { #else .abe = &abe_dpll_params_32k_196608khz, #endif - .usb = usb_dpll_params_1920mhz + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls dra7xx_dplls = { + .mpu = mpu_dpll_params_1ghz, + .core = core_dpll_params_2128mhz_ddr532_dra7xx, + .per = per_dpll_params_768mhz_dra7xx, + .usb = usb_dpll_params_1920mhz, + .ddr = ddr_dpll_params_1066mhz, }; struct pmic_data palmas = { @@ -505,6 +561,8 @@ void hw_data_init(void) case DRA752_ES1_0: *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &omap5430_volts_es2; break; default: diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 54700f7..59bfabc 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -27,7 +27,7 @@ #include -#define NUM_SYS_CLKS 7 +#define NUM_SYS_CLKS 8 struct prcm_regs { /* cm1.ckgen */ @@ -473,6 +473,7 @@ struct dplls { const struct dpll_params *abe; const struct dpll_params *iva; const struct dpll_params *usb; + const struct dpll_params *ddr; }; struct pmic_data { -- cgit v0.10.2 From 8b12f1779e339e375151883b3d0aadbd4fdce894 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 21:29:06 +0000 Subject: arm: dra7xx: Add control module changes Control module register addresses are changed from OMAP5 to DRA7XX socs. So adding the necessary changes for the same. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index b82205a..7f1808c 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -550,6 +550,7 @@ void hw_data_init(void) *prcm = &omap5_es1_prcm; *dplls_data = &omap5_dplls_es1; *omap_vcores = &omap5430_volts; + *ctrl = &omap5_ctrl; break; case OMAP5430_ES2_0: @@ -557,19 +558,19 @@ void hw_data_init(void) *prcm = &omap5_es2_prcm; *dplls_data = &omap5_dplls_es2; *omap_vcores = &omap5430_volts_es2; + *ctrl = &omap5_ctrl; break; case DRA752_ES1_0: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; *omap_vcores = &omap5430_volts_es2; + *ctrl = &dra7xx_ctrl; break; default: printf("\n INVALID OMAP REVISION "); } - - *ctrl = &omap5_ctrl; } void get_ioregs(const struct ctrl_ioregs **regs) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index ade9875..b8a61fe 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -383,6 +383,78 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_efuse_13 = 0x4AE0CDF8, }; +struct omap_sys_ctrl_regs const dra7xx_ctrl = { + .control_status = 0x4A002134, + .control_core_mmr_lock1 = 0x4A002540, + .control_core_mmr_lock2 = 0x4A002544, + .control_core_mmr_lock3 = 0x4A002548, + .control_core_mmr_lock4 = 0x4A00254C, + .control_core_mmr_lock5 = 0x4A002550, + .control_core_control_io1 = 0x4A002554, + .control_core_control_io2 = 0x4A002558, + .control_paconf_global = 0x4A002DA0, + .control_paconf_mode = 0x4A002DA4, + .control_smart1io_padconf_0 = 0x4A002DA8, + .control_smart1io_padconf_1 = 0x4A002DAC, + .control_smart1io_padconf_2 = 0x4A002DB0, + .control_smart2io_padconf_0 = 0x4A002DB4, + .control_smart2io_padconf_1 = 0x4A002DB8, + .control_smart2io_padconf_2 = 0x4A002DBC, + .control_smart3io_padconf_0 = 0x4A002DC0, + .control_smart3io_padconf_1 = 0x4A002DC4, + .control_pbias = 0x4A002E00, + .control_i2c_0 = 0x4A002E04, + .control_camera_rx = 0x4A002E08, + .control_hdmi_tx_phy = 0x4A002E0C, + .control_uniportm = 0x4A002E10, + .control_dsiphy = 0x4A002E14, + .control_mcbsplp = 0x4A002E18, + .control_usb2phycore = 0x4A002E1C, + .control_hdmi_1 = 0x4A002E20, + .control_hsi = 0x4A002E24, + .control_ddr3ch1_0 = 0x4A002E30, + .control_ddr3ch2_0 = 0x4A002E34, + .control_ddrch1_0 = 0x4A002E38, + .control_ddrch1_1 = 0x4A002E3C, + .control_ddrch2_0 = 0x4A002E40, + .control_ddrch2_1 = 0x4A002E44, + .control_lpddr2ch1_0 = 0x4A002E48, + .control_lpddr2ch1_1 = 0x4A002E4C, + .control_ddrio_0 = 0x4A002E50, + .control_ddrio_1 = 0x4A002E54, + .control_ddrio_2 = 0x4A002E58, + .control_hyst_1 = 0x4A002E5C, + .control_usbb_hsic_control = 0x4A002E60, + .control_c2c = 0x4A002E64, + .control_core_control_spare_rw = 0x4A002E68, + .control_core_control_spare_r = 0x4A002E6C, + .control_core_control_spare_r_c0 = 0x4A002E70, + .control_srcomp_north_side = 0x4A002E74, + .control_srcomp_south_side = 0x4A002E78, + .control_srcomp_east_side = 0x4A002E7C, + .control_srcomp_west_side = 0x4A002E80, + .control_srcomp_code_latch = 0x4A002E84, + .control_padconf_core_base = 0x4A003400, + .control_port_emif1_sdram_config = 0x4AE0C110, + .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, + .control_port_emif2_sdram_config = 0x4AE0C118, + .control_emif1_sdram_config_ext = 0x4AE0C144, + .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_padconf_mode = 0x4AE0C5A0, + .control_xtal_oscillator = 0x4AE0C5A4, + .control_i2c_2 = 0x4AE0C5A8, + .control_ckobuffer = 0x4AE0C5AC, + .control_wkup_control_spare_rw = 0x4AE0C5B0, + .control_wkup_control_spare_r = 0x4AE0C5B4, + .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, + .control_srcomp_east_side_wkup = 0x4AE0C5BC, + .control_efuse_1 = 0x4AE0C5C0, + .control_efuse_2 = 0x4AE0C5C4, + .control_efuse_3 = 0x4AE0C5C8, + .control_efuse_4 = 0x4AE0C5CC, + .control_efuse_13 = 0x4AE0C5F0, +}; + struct prcm_regs const omap5_es2_prcm = { /* cm1.ckgen */ .cm_clksel_core = 0x4a004100, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 59bfabc..eeed163 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -347,11 +347,19 @@ struct prcm_regs { struct omap_sys_ctrl_regs { u32 control_status; + u32 control_core_mmr_lock1; + u32 control_core_mmr_lock2; + u32 control_core_mmr_lock3; + u32 control_core_mmr_lock4; + u32 control_core_mmr_lock5; + u32 control_core_control_io1; + u32 control_core_control_io2; u32 control_id_code; u32 control_std_fuse_opp_bgap; u32 control_ldosram_iva_voltage_ctrl; u32 control_ldosram_mpu_voltage_ctrl; u32 control_ldosram_core_voltage_ctrl; + u32 control_padconf_core_base; u32 control_paconf_global; u32 control_paconf_mode; u32 control_smart1io_padconf_0; @@ -431,6 +439,7 @@ struct omap_sys_ctrl_regs { u32 control_efuse_11; u32 control_efuse_12; u32 control_efuse_13; + u32 control_padconf_wkup_base; }; struct dpll_params { @@ -507,6 +516,7 @@ extern const u32 sys_clk_array[8]; extern struct omap_sys_ctrl_regs const **ctrl; extern struct omap_sys_ctrl_regs const omap4_ctrl; extern struct omap_sys_ctrl_regs const omap5_ctrl; +extern struct omap_sys_ctrl_regs const dra7xx_ctrl; void hw_data_init(void); -- cgit v0.10.2 From 7831419d7bd9cf61a53ad6f7f23dae107812fdf5 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 21:29:07 +0000 Subject: arm: dra7xx: Add DDR related data for DRA752 ES1.0 DRA752 uses DDR3. Populating the corresponding structures with DDR3 data. Writing into MA registers if only MA is present in that soc. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 0683b9f..9eb1279 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1191,7 +1191,7 @@ void dmm_init(u32 base) writel(lisa_map_regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); - if (omap_revision() >= OMAP4460_ES1_0) { + if (lisa_map_regs->is_ma_present) { hw_lisa_map_regs = (struct dmm_lisa_map_regs *)MA_BASE; diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index 01da790..20fc552 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -94,14 +94,24 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80540300 + .dmm_lisa_map_3 = 0x80540300, + .is_ma_present = 0x0 }; const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80640300 + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x0 +}; + +const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x1 }; static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) @@ -126,8 +136,10 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs if (omap_rev == OMAP4430_ES1_0) *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; - else + else if (omap_rev < OMAP4460_ES1_0) *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; + else + *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; } void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 7f1808c..ced274e 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -586,6 +586,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) *regs = &ioregs_omap5432_es1; break; case OMAP5432_ES2_0: + case DRA752_ES1_0: *regs = &ioregs_omap5432_es2; break; diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 2ef7fcd..6b461e4 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -155,7 +155,16 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, .dmm_lisa_map_2 = 0x80740300, - .dmm_lisa_map_3 = 0xFF020100 + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +const struct dmm_lisa_map_regs lisa_map_512M_x_1 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x0, + .dmm_lisa_map_3 = 0x80500100, + .is_ma_present = 0x1 }; static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) @@ -171,6 +180,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_532_mhz_2cs_es2; break; case OMAP5432_ES2_0: + case DRA752_ES1_0: default: *regs = &emif_regs_ddr3_532_mhz_1cs_es2; } @@ -182,7 +192,18 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs) { - *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + case OMAP5432_ES1_0: + case OMAP5432_ES2_0: + *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; + break; + case DRA752_ES1_0: + default: + *dmm_lisa_regs = &lisa_map_512M_x_1; + } + } void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) @@ -297,6 +318,7 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) *regs = ddr3_ext_phy_ctrl_const_base_es1; break; case OMAP5432_ES2_0: + case DRA752_ES1_0: default: *regs = ddr3_ext_phy_ctrl_const_base_es2; diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 9d72fe3..c5d1e6c 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -697,6 +697,7 @@ struct dmm_lisa_map_regs { u32 dmm_lisa_map_1; u32 dmm_lisa_map_2; u32 dmm_lisa_map_3; + u8 is_ma_present; }; #define CS0 0 -- cgit v0.10.2 From 687054a7e0f064db3161ea9c74a2909016ced9df Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 21:29:08 +0000 Subject: arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla Signed-off-by: Nishant Kamat Signed-off-by: R Sricharan Reviewed-by: Tom Rini [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h new file mode 100644 index 0000000..55e9de6 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -0,0 +1,344 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated + * + * Nishant Kamat + * Lokesh Vutla + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_DRA7XX_H_ +#define _MUX_DRA7XX_H_ + +#include + +#define IEN (1 << 18) +#define IDIS (0 << 18) + +#define PTU (3 << 16) +#define PTD (1 << 16) +#define PEN (1 << 16) +#define PDIS (0 << 16) + +#define WKEN (1 << 24) +#define WKDIS (0 << 24) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 +#define M8 8 +#define M9 9 +#define M10 10 +#define M11 11 +#define M12 12 +#define M13 13 +#define M14 14 +#define M15 15 + +#define SAFE_MODE M15 + +#define GPMC_AD0 0x000 +#define GPMC_AD1 0x004 +#define GPMC_AD2 0x008 +#define GPMC_AD3 0x00C +#define GPMC_AD4 0x010 +#define GPMC_AD5 0x014 +#define GPMC_AD6 0x018 +#define GPMC_AD7 0x01C +#define GPMC_AD8 0x020 +#define GPMC_AD9 0x024 +#define GPMC_AD10 0x028 +#define GPMC_AD11 0x02C +#define GPMC_AD12 0x030 +#define GPMC_AD13 0x034 +#define GPMC_AD14 0x038 +#define GPMC_AD15 0x03C +#define GPMC_A0 0x040 +#define GPMC_A1 0x044 +#define GPMC_A2 0x048 +#define GPMC_A3 0x04C +#define GPMC_A4 0x050 +#define GPMC_A5 0x054 +#define GPMC_A6 0x058 +#define GPMC_A7 0x05C +#define GPMC_A8 0x060 +#define GPMC_A9 0x064 +#define GPMC_A10 0x068 +#define GPMC_A11 0x06C +#define GPMC_A12 0x070 +#define GPMC_A13 0x074 +#define GPMC_A14 0x078 +#define GPMC_A15 0x07C +#define GPMC_A16 0x080 +#define GPMC_A17 0x084 +#define GPMC_A18 0x088 +#define GPMC_A19 0x08C +#define GPMC_A20 0x090 +#define GPMC_A21 0x094 +#define GPMC_A22 0x098 +#define GPMC_A23 0x09C +#define GPMC_A24 0x0A0 +#define GPMC_A25 0x0A4 +#define GPMC_A26 0x0A8 +#define GPMC_A27 0x0AC +#define GPMC_CS1 0x0B0 +#define GPMC_CS0 0x0B4 +#define GPMC_CS2 0x0B8 +#define GPMC_CS3 0x0BC +#define GPMC_CLK 0x0C0 +#define GPMC_ADVN_ALE 0x0C4 +#define GPMC_OEN_REN 0x0C8 +#define GPMC_WEN 0x0CC +#define GPMC_BEN0 0x0D0 +#define GPMC_BEN1 0x0D4 +#define GPMC_WAIT0 0x0D8 +#define VIN1A_CLK0 0x0DC +#define VIN1B_CLK1 0x0E0 +#define VIN1A_DE0 0x0E4 +#define VIN1A_FLD0 0x0E8 +#define VIN1A_HSYNC0 0x0EC +#define VIN1A_VSYNC0 0x0F0 +#define VIN1A_D0 0x0F4 +#define VIN1A_D1 0x0F8 +#define VIN1A_D2 0x0FC +#define VIN1A_D3 0x100 +#define VIN1A_D4 0x104 +#define VIN1A_D5 0x108 +#define VIN1A_D6 0x10C +#define VIN1A_D7 0x110 +#define VIN1A_D8 0x114 +#define VIN1A_D9 0x118 +#define VIN1A_D10 0x11C +#define VIN1A_D11 0x120 +#define VIN1A_D12 0x124 +#define VIN1A_D13 0x128 +#define VIN1A_D14 0x12C +#define VIN1A_D15 0x130 +#define VIN1A_D16 0x134 +#define VIN1A_D17 0x138 +#define VIN1A_D18 0x13C +#define VIN1A_D19 0x140 +#define VIN1A_D20 0x144 +#define VIN1A_D21 0x148 +#define VIN1A_D22 0x14C +#define VIN1A_D23 0x150 +#define VIN2A_CLK0 0x154 +#define VIN2A_DE0 0x158 +#define VIN2A_FLD0 0x15C +#define VIN2A_HSYNC0 0x160 +#define VIN2A_VSYNC0 0x164 +#define VIN2A_D0 0x168 +#define VIN2A_D1 0x16C +#define VIN2A_D2 0x170 +#define VIN2A_D3 0x174 +#define VIN2A_D4 0x178 +#define VIN2A_D5 0x17C +#define VIN2A_D6 0x180 +#define VIN2A_D7 0x184 +#define VIN2A_D8 0x188 +#define VIN2A_D9 0x18C +#define VIN2A_D10 0x190 +#define VIN2A_D11 0x194 +#define VIN2A_D12 0x198 +#define VIN2A_D13 0x19C +#define VIN2A_D14 0x1A0 +#define VIN2A_D15 0x1A4 +#define VIN2A_D16 0x1A8 +#define VIN2A_D17 0x1AC +#define VIN2A_D18 0x1B0 +#define VIN2A_D19 0x1B4 +#define VIN2A_D20 0x1B8 +#define VIN2A_D21 0x1BC +#define VIN2A_D22 0x1C0 +#define VIN2A_D23 0x1C4 +#define VOUT1_CLK 0x1C8 +#define VOUT1_DE 0x1CC +#define VOUT1_FLD 0x1D0 +#define VOUT1_HSYNC 0x1D4 +#define VOUT1_VSYNC 0x1D8 +#define VOUT1_D0 0x1DC +#define VOUT1_D1 0x1E0 +#define VOUT1_D2 0x1E4 +#define VOUT1_D3 0x1E8 +#define VOUT1_D4 0x1EC +#define VOUT1_D5 0x1F0 +#define VOUT1_D6 0x1F4 +#define VOUT1_D7 0x1F8 +#define VOUT1_D8 0x1FC +#define VOUT1_D9 0x200 +#define VOUT1_D10 0x204 +#define VOUT1_D11 0x208 +#define VOUT1_D12 0x20C +#define VOUT1_D13 0x210 +#define VOUT1_D14 0x214 +#define VOUT1_D15 0x218 +#define VOUT1_D16 0x21C +#define VOUT1_D17 0x220 +#define VOUT1_D18 0x224 +#define VOUT1_D19 0x228 +#define VOUT1_D20 0x22C +#define VOUT1_D21 0x230 +#define VOUT1_D22 0x234 +#define VOUT1_D23 0x238 +#define MDIO_MCLK 0x23C +#define MDIO_D 0x240 +#define RMII_MHZ_50_CLK 0x244 +#define UART3_RXD 0x248 +#define UART3_TXD 0x24C +#define RGMII0_TXC 0x250 +#define RGMII0_TXCTL 0x254 +#define RGMII0_TXD3 0x258 +#define RGMII0_TXD2 0x25C +#define RGMII0_TXD1 0x260 +#define RGMII0_TXD0 0x264 +#define RGMII0_RXC 0x268 +#define RGMII0_RXCTL 0x26C +#define RGMII0_RXD3 0x270 +#define RGMII0_RXD2 0x274 +#define RGMII0_RXD1 0x278 +#define RGMII0_RXD0 0x27C +#define USB1_DRVVBUS 0x280 +#define USB2_DRVVBUS 0x284 +#define GPIO6_14 0x288 +#define GPIO6_15 0x28C +#define GPIO6_16 0x290 +#define XREF_CLK0 0x294 +#define XREF_CLK1 0x298 +#define XREF_CLK2 0x29C +#define XREF_CLK3 0x2A0 +#define MCASP1_ACLKX 0x2A4 +#define MCASP1_FSX 0x2A8 +#define MCASP1_ACLKR 0x2AC +#define MCASP1_FSR 0x2B0 +#define MCASP1_AXR0 0x2B4 +#define MCASP1_AXR1 0x2B8 +#define MCASP1_AXR2 0x2BC +#define MCASP1_AXR3 0x2C0 +#define MCASP1_AXR4 0x2C4 +#define MCASP1_AXR5 0x2C8 +#define MCASP1_AXR6 0x2CC +#define MCASP1_AXR7 0x2D0 +#define MCASP1_AXR8 0x2D4 +#define MCASP1_AXR9 0x2D8 +#define MCASP1_AXR10 0x2DC +#define MCASP1_AXR11 0x2E0 +#define MCASP1_AXR12 0x2E4 +#define MCASP1_AXR13 0x2E8 +#define MCASP1_AXR14 0x2EC +#define MCASP1_AXR15 0x2F0 +#define MCASP2_ACLKX 0x2F4 +#define MCASP2_FSX 0x2F8 +#define MCASP2_ACLKR 0x2FC +#define MCASP2_FSR 0x300 +#define MCASP2_AXR0 0x304 +#define MCASP2_AXR1 0x308 +#define MCASP2_AXR2 0x30C +#define MCASP2_AXR3 0x310 +#define MCASP2_AXR4 0x314 +#define MCASP2_AXR5 0x318 +#define MCASP2_AXR6 0x31C +#define MCASP2_AXR7 0x320 +#define MCASP3_ACLKX 0x324 +#define MCASP3_FSX 0x328 +#define MCASP3_AXR0 0x32C +#define MCASP3_AXR1 0x330 +#define MCASP4_ACLKX 0x334 +#define MCASP4_FSX 0x338 +#define MCASP4_AXR0 0x33C +#define MCASP4_AXR1 0x340 +#define MCASP5_ACLKX 0x344 +#define MCASP5_FSX 0x348 +#define MCASP5_AXR0 0x34C +#define MCASP5_AXR1 0x350 +#define MMC1_CLK 0x354 +#define MMC1_CMD 0x358 +#define MMC1_DAT0 0x35C +#define MMC1_DAT1 0x360 +#define MMC1_DAT2 0x364 +#define MMC1_DAT3 0x368 +#define MMC1_SDCD 0x36C +#define MMC1_SDWP 0x370 +#define GPIO6_10 0x374 +#define GPIO6_11 0x378 +#define MMC3_CLK 0x37C +#define MMC3_CMD 0x380 +#define MMC3_DAT0 0x384 +#define MMC3_DAT1 0x388 +#define MMC3_DAT2 0x38C +#define MMC3_DAT3 0x390 +#define MMC3_DAT4 0x394 +#define MMC3_DAT5 0x398 +#define MMC3_DAT6 0x39C +#define MMC3_DAT7 0x3A0 +#define SPI1_SCLK 0x3A4 +#define SPI1_D1 0x3A8 +#define SPI1_D0 0x3AC +#define SPI1_CS0 0x3B0 +#define SPI1_CS1 0x3B4 +#define SPI1_CS2 0x3B8 +#define SPI1_CS3 0x3BC +#define SPI2_SCLK 0x3C0 +#define SPI2_D1 0x3C4 +#define SPI2_D0 0x3C8 +#define SPI2_CS0 0x3CC +#define DCAN1_TX 0x3D0 +#define DCAN1_RX 0x3D4 +#define DCAN2_TX 0x3D8 +#define DCAN2_RX 0x3DC +#define UART1_RXD 0x3E0 +#define UART1_TXD 0x3E4 +#define UART1_CTSN 0x3E8 +#define UART1_RTSN 0x3EC +#define UART2_RXD 0x3F0 +#define UART2_TXD 0x3F4 +#define UART2_CTSN 0x3F8 +#define UART2_RTSN 0x3FC +#define I2C1_SDA 0x400 +#define I2C1_SCL 0x404 +#define I2C2_SDA 0x408 +#define I2C2_SCL 0x40C +#define I2C3_SDA 0x410 +#define I2C3_SCL 0x414 +#define WAKEUP0 0x418 +#define WAKEUP1 0x41C +#define WAKEUP2 0x420 +#define WAKEUP3 0x424 +#define ON_OFF 0x428 +#define RTC_PORZ 0x42C +#define TMS 0x430 +#define TDI 0x434 +#define TDO 0x438 +#define TCLK 0x43C +#define TRSTN 0x440 +#define RTCK 0x444 +#define EMU0 0x448 +#define EMU1 0x44C +#define EMU2 0x450 +#define EMU3 0x454 +#define EMU4 0x458 +#define RESETN 0x45C +#define NMIN 0x460 +#define RSTOUTN 0x464 + +#endif /* _MUX_DRA7XX_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h index 4a6ed8b..34b0dbd 100644 --- a/arch/arm/include/asm/arch-omap5/mux_omap5.h +++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h @@ -28,14 +28,6 @@ #include -struct pad_conf_entry { - - u16 offset; - - u16 val; - -}; - #ifdef CONFIG_OFF_PADCONF #define OFF_PD (1 << 12) #define OFF_PU (3 << 12) diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index b8d841d..e66ab44 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -25,9 +25,13 @@ #include #include #include -#include #include +struct pad_conf_entry { + u32 offset; + u32 val; +}; + struct omap_sysinfo { char *board_string; }; diff --git a/board/ti/dra7xx/Makefile b/board/ti/dra7xx/Makefile new file mode 100644 index 0000000..db6da5b --- /dev/null +++ b/board/ti/dra7xx/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2013 +# Texas Instruments, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := evm.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c new file mode 100644 index 0000000..7bbb549 --- /dev/null +++ b/board/ti/dra7xx/evm.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated, + * + * Lokesh Vutla + * + * Based on previous work by: + * Aneesh V + * Steve Sakoman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include + +#include "mux_data.h" + +#ifdef CONFIG_USB_EHCI +#include +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: DRA7xx\n" +}; + +/** + * @brief board_init + * + * @return 0 + */ +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +/** + * @brief misc_init_r - Configure EVM board specific configurations + * such as power configurations, ethernet initialization as phase2 of + * boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ + return 0; +} + +static void do_set_mux32(u32 base, + struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *)array; + + for (i = 0; i < size; i++, pad++) + writel(pad->val, base + pad->offset); +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux32((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h new file mode 100644 index 0000000..04c95fd --- /dev/null +++ b/board/ti/dra7xx/mux_data.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated, + * + * Sricharan R + * Nishant Kamat + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_DATA_DRA7XX_H_ +#define _MUX_DATA_DRA7XX_H_ + +#include + +const struct pad_conf_entry core_padconf_array_essential[] = { + {MMC1_CLK, (PTU | IEN | M0)}, /* MMC1_CLK */ + {MMC1_CMD, (PTU | IEN | M0)}, /* MMC1_CMD */ + {MMC1_DAT0, (PTU | IEN | M0)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (PTU | IEN | M0)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (PTU | IEN | M0)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (PTU | IEN | M0)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (PTU | IEN | M0)}, /* MMC1_SDCD */ + {MMC1_SDWP, (PTU | IEN | M0)}, /* MMC1_SDWP */ + {UART1_RXD, (PTU | IEN | M0)}, /* UART1_RXD */ + {UART1_TXD, (M0)}, /* UART1_TXD */ + {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */ + {UART1_RTSN, (M0)}, /* UART1_RTSN */ + {I2C1_SDA, (PTU | IEN | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (PTU | IEN | M0)}, /* I2C1_SCL */ +}; +#endif /* _MUX_DATA_DRA7XX_H_ */ -- cgit v0.10.2 From 3ef5ebeb86d1ef76277ab738fa663dfca1ce9599 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Sun, 17 Feb 2013 23:34:35 +0000 Subject: arm: dra7xx: Add dra7xx_evm build support Adding the build support for dra7xx_evm. Reusing omap5_evm.h config by moving it to omap5_common.h Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan diff --git a/boards.cfg b/boards.cfg index c117368..efe137d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -285,6 +285,7 @@ nokia_rx51 arm armv7 rx51 nokia omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 omap5_evm arm armv7 omap5_evm ti omap5 +dra7xx_evm arm armv7 dra7xx ti omap5 s5p_goni arm armv7 goni samsung s5pc1xx smdkc100 arm armv7 smdkc100 samsung s5pc1xx origen arm armv7 origen samsung exynos diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h new file mode 100644 index 0000000..10a4939 --- /dev/null +++ b/include/configs/dra7xx_evm.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated. + * Lokesh Vutla + * + * Configuration settings for the TI DRA7XX board. + * See omap5_common.h for omap5 common settings. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DRA7XX_EVM_H +#define __CONFIG_DRA7XX_EVM_H + +#include + +#define CONFIG_DRA7XX /* in a TI DRA7XX core */ +#define CONFIG_SYS_PROMPT "DRA752 EVM # " + +#endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h new file mode 100644 index 0000000..af97564 --- /dev/null +++ b/include/configs/omap5_common.h @@ -0,0 +1,262 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated. + * Sricharan R + * + * Derived from OMAP4 done by: + * Aneesh V + * + * TI OMAP5 AND DRA7XX common configuration settings + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_OMAP5_COMMON_H +#define __CONFIG_OMAP5_COMMON_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP54XX /* which is a 54XX */ +#define CONFIG_OMAP_GPIO + +/* Get CPU defs */ +#include +#include + +/* Display CPU and Board Info */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 19200000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + +#define CONFIG_MISC_INIT_R + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + * Total Size Environment - 128k + * Malloc - add 256k + */ +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) +/* Vector Base */ +#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE + +/* + * Hardware drivers + */ + +/* + * serial port - NS16550 compatible + */ +#define V_NS16550_CLK 48000000 + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 UART3_BASE + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_I2C_MULTI_BUS + + +/* MMC */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* MMC ENV related defines */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_CMD_SAVEENV + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* Flash */ +#define CONFIG_SYS_NO_FLASH + +/* Cache */ +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CACHELINE_SHIFT 6 + +/* commands to include */ +#include + +/* Enabled commands */ +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_SAVEENV + +/* Disabled commands */ +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +/* + * Environment setup + */ + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "usbtty=cdc_acm\0" \ + "vram=16M\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "vram=${vram} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + +#define CONFIG_AUTO_COMPLETE 1 + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +/* + * memtest setup + */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20)) + +/* Default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x80000000 + +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * SDRAM Memory Map + * Even though we use two CS all the memory + * is mapped to one contiguous block + */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + +/* Defines for SDRAM init */ +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40300350 +#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_DISPLAY_PRINT + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 80E7FFC0--0x80E80000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80E80000 + +/* + * BSS and malloc area 64MB into memory to allow enough + * space for the kernel at the beginning of memory + */ +#define CONFIG_SPL_BSS_START_ADDR 0x84000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SPL_GPIO_SUPPORT + +#endif /* __CONFIG_OMAP5_COMMON_H */ diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 0f11d34..22a8e13 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -1,12 +1,10 @@ /* - * (C) Copyright 2010 + * (C) Copyright 2013 * Texas Instruments Incorporated. * Sricharan R * - * Derived from OMAP4 done by: - * Aneesh V - * * Configuration settings for the TI EVM5430 board. + * See omap5_common.h for omap5 common settings. * * See file CREDITS for list of people who contributed to this * project. @@ -27,244 +25,16 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP54XX /* which is a 54XX */ -#define CONFIG_OMAP5430 /* which is in a 5430 */ -#define CONFIG_5430EVM /* working with EVM */ -#define CONFIG_OMAP_GPIO - -/* Get CPU defs */ -#include -#include - -/* Display CPU and Board Info */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* Clock Defines */ -#define V_OSCK 19200000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - -#define CONFIG_MISC_INIT_R - -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - * Total Size Environment - 128k - * Malloc - add 256k - */ -#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) -/* Vector Base */ -#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE - -/* - * Hardware drivers - */ - -/* - * serial port - NS16550 compatible - */ -#define V_NS16550_CLK 48000000 - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#ifndef __CONFIG_OMAP5_EVM_H +#define __CONFIG_OMAP5_EVM_H -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -/* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C -#define CONFIG_I2C_MULTI_BUS +#include /* TWL6035 */ #ifndef CONFIG_SPL_BUILD #define CONFIG_TWL6035_POWER #endif -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION - -/* MMC ENV related defines */ -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ -#define CONFIG_ENV_OFFSET 0xE0000 -#define CONFIG_CMD_SAVEENV - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* Flash */ -#define CONFIG_SYS_NO_FLASH - -/* Cache */ -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_CACHELINE_SHIFT 6 - -/* commands to include */ -#include - -/* Enabled commands */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_SAVEENV - -/* Disabled commands */ -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMLS /* List all found images */ - -/* - * Environment setup - */ - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ - "usbtty=cdc_acm\0" \ - "vram=16M\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "vram=${vram} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi" - -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "OMAP5430 EVM # " -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -/* - * memtest setup - */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20)) - -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 - -/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* - * SDRAM Memory Map - * Even though we use two CS all the memory - * is mapped to one contiguous block - */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -/* Defines for SDRAM init */ -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x40300350 -#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SPL_DISPLAY_PRINT - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - -/* - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 80E7FFC0--0x80E80000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80E80000 - -/* - * BSS and malloc area 64MB into memory to allow enough - * space for the kernel at the beginning of memory - */ -#define CONFIG_SPL_BSS_START_ADDR 0x84000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SPL_GPIO_SUPPORT -#endif /* __CONFIG_H */ +#endif /* __CONFIG_OMAP5_EVM_H */ -- cgit v0.10.2 From de62688bb61c499ecc2d70a3aa8ccf90bb7a8ef6 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 12 Feb 2013 21:29:03 +0000 Subject: arm: dra7xx: Add silicon id support for DRA752 soc Adding CPU detection support for the DRA752 ES1.0 soc. Signed-off-by: Lokesh Vutla Signed-off-by: R Sricharan Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 60af7eb..05ff2e8 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -81,12 +81,17 @@ u32 cortex_rev(void) void omap_rev_string(void) { u32 omap_rev = omap_revision(); + u32 soc_variant = (omap_rev & 0xF0000000) >> 28; u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; u32 major_rev = (omap_rev & 0x00000F00) >> 8; u32 minor_rev = (omap_rev & 0x000000F0) >> 4; - printf("OMAP%x ES%x.%x\n", omap_variant, major_rev, - minor_rev); + if (soc_variant) + printf("OMAP"); + else + printf("DRA"); + printf("%x ES%x.%x\n", omap_variant, major_rev, + minor_rev); } #ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index d291da9..2f4b247 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -337,6 +337,9 @@ void init_omap_revision(void) case OMAP5432_CONTROL_ID_CODE_ES2_0: *omap_si_rev = OMAP5432_ES2_0; break; + case DRA752_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = DRA752_ES1_0; + break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index d29be93..b632635 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -60,6 +60,7 @@ #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F +#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F /* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index eeed163..091ddb5 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -580,4 +580,7 @@ static inline u32 omap_revision(void) #define OMAP5432_ES1_0 0x54320100 #define OMAP5430_ES2_0 0x54300200 #define OMAP5432_ES2_0 0x54320200 + +/* DRA7XX */ +#define DRA752_ES1_0 0x07520100 #endif /* _OMAP_COMMON_H_ */ -- cgit v0.10.2 From 36873e7d96f05ba53ff1d21e2fabf45e131856a7 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 20 Feb 2013 00:16:23 +0000 Subject: arm: at91/configs: add libfdt to configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit support to boot device tree Linux kernel Signed-off-by: Nicolas Ferre [Add libftd for at91rm9200, at91sam9263, at91sam9rl] Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index bf20065..4b526c2 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -75,6 +75,8 @@ #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_OF_LIBFDT + /* * Memory Configuration */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 02696b3..3db6cc8 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -62,6 +62,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_OF_LIBFDT + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 3503822..005d1af 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -62,6 +62,8 @@ #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_OF_LIBFDT + /* * Hardware drivers */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 8178b32..be084b2 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -48,6 +48,8 @@ #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_OF_LIBFDT + #define CONFIG_ATMEL_LEGACY #define CONFIG_AT91_GPIO 1 #define CONFIG_AT91_GPIO_PULLUP 1 -- cgit v0.10.2 From f9129fe33852ce98c15704aff954045606582b40 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 20 Feb 2013 00:16:24 +0000 Subject: arm: at91/configs: add bootz to configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Support to boot zImage Signed-off-by: Nicolas Ferre [Add bootz for at91rm9200, at91sam9263, at91sam9rl] Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 4b526c2..7352113 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -75,6 +75,7 @@ #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 3db6cc8..392a818 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -62,6 +62,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* general purpose I/O */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 005d1af..da2a931 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -62,6 +62,7 @@ #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index e988d81..f1a4db3 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -47,6 +47,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* general purpose I/O */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index be084b2..aa359b1 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -48,6 +48,7 @@ #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT #define CONFIG_ATMEL_LEGACY diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 6fac5ac..1bc56a5 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -42,6 +42,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* general purpose I/O */ -- cgit v0.10.2 From 0c58cfa9dd84176a26a64be258a554a38ce654e2 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 20 Feb 2013 00:16:25 +0000 Subject: ARM: at91: change nand flash table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change nand flash partition table according to www.at91.com/linux4sam more information: http://www.at91.com/linux4sam/bin/view/Linux4SAM/GettingStarted#Linux4SAM_NandFlash_demo_Memory Signed-off-by: Bo Shen [minor commit message changes] Signed-off-by: Andreas Bießmann diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 392a818..ebcc69a 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -215,16 +215,16 @@ /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock5 " \ - "mtdparts=atmel_nand:128k(bootstrap)ro," \ - "256k(uboot)ro,128k(env1)ro," \ - "128k(env2)ro,2M(linux),-(root) " \ - "rw rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256k(env),256k(env_redundant),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "root=/dev/mtdblock7 rw rootfstype=jffs2" #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 611e3e2..cabff9a 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -212,17 +212,16 @@ /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock5 " \ - "mtdparts=atmel_nand:128k(bootstrap)ro," \ - "256k(uboot)ro,128k(env1)ro," \ - "128k(env2)ro,2M(linux),-(root) " \ - "rw rootfstype=jffs2" - +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256k(env),256k(env_redundant),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "root=/dev/mtdblock7 rw rootfstype=jffs2" #endif #define CONFIG_SYS_PROMPT "U-Boot> " diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index da2a931..1ab9c30 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -327,15 +327,16 @@ /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock5 " \ - "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ - "rw rootfstype=jffs2" - +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256k(env),256k(env_redundant),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "root=/dev/mtdblock7 rw rootfstype=jffs2" #endif #define CONFIG_SYS_PROMPT "U-Boot> " diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index f1a4db3..07e1c9f 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -150,19 +150,19 @@ /* bootstrap + u-boot + env in nandflash */ #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 #define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_BOOTCOMMAND "nand read 0x70000000 0x100000 0x200000;" \ +#define CONFIG_BOOTCOMMAND \ + "nand read 0x70000000 0x200000 0x300000;" \ "bootm 0x70000000" #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk " \ - "root=/dev/mtdblock5 " \ - "mtdparts=atmel_nand:128k(bootstrap)ro," \ - "256k(uboot)ro,128k(env1)ro,128k(env2)ro," \ - "2M@1M(linux),-(root) " \ - "rw rootfstype=jffs2" + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256k(env),256k(env_redundant),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "root=/dev/mtdblock7 rw rootfstype=jffs2" #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 1bc56a5..ee6e3fc 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -232,11 +232,12 @@ "root=/dev/mmcblk0p2 " \ "rw rootfstype=ext4 rootwait" #else -#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \ - "mtdparts=atmel_nand:" \ - "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \ - "root=/dev/mtdblock1 rw " \ - "rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256k(env),256k(env_redundant),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw" #endif #define CONFIG_BAUDRATE 115200 -- cgit v0.10.2 From fc14fbace4b295ffb22aa90d2791365f1dd6bb15 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Thu, 7 Mar 2013 21:23:22 +0000 Subject: ARM: at91sam9x5: Using CPU string directly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As the CPU name is not configurable, using CPU string directly Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c index 0448c0b..29e8aa4 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -61,20 +61,20 @@ char *get_cpu_name() if (cpu_is_at91sam9x5()) { switch (extension_id) { case ARCH_EXID_AT91SAM9G15: - return CONFIG_SYS_AT91_G15_CPU_NAME; + return "AT91SAM9G15"; case ARCH_EXID_AT91SAM9G25: - return CONFIG_SYS_AT91_G25_CPU_NAME; + return "AT91SAM9G25"; case ARCH_EXID_AT91SAM9G35: - return CONFIG_SYS_AT91_G35_CPU_NAME; + return "AT91SAM9G35"; case ARCH_EXID_AT91SAM9X25: - return CONFIG_SYS_AT91_X25_CPU_NAME; + return "AT91SAM9X25"; case ARCH_EXID_AT91SAM9X35: - return CONFIG_SYS_AT91_X35_CPU_NAME; + return "AT91SAM9X35"; default: - return CONFIG_SYS_AT91_UNKNOWN_CPU; + return "Unknown CPU type"; } } else { - return CONFIG_SYS_AT91_UNKNOWN_CPU; + return "Unknown CPU type"; } } diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index de0f1b1..b7d1932 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -140,12 +140,6 @@ /* * Cpu Name */ -#define CONFIG_SYS_AT91_G15_CPU_NAME "AT91SAM9G15" -#define CONFIG_SYS_AT91_G25_CPU_NAME "AT91SAM9G25" -#define CONFIG_SYS_AT91_G35_CPU_NAME "AT91SAM9G35" -#define CONFIG_SYS_AT91_X25_CPU_NAME "AT91SAM9X25" -#define CONFIG_SYS_AT91_X35_CPU_NAME "AT91SAM9X35" -#define CONFIG_SYS_AT91_UNKNOWN_CPU "Unknown CPU type" #define ATMEL_CPU_NAME get_cpu_name() /* -- cgit v0.10.2 From 08f0533a147ca37546a6539b43fce3916e82811a Mon Sep 17 00:00:00 2001 From: Jesse Gilles Date: Wed, 27 Feb 2013 23:42:49 +0000 Subject: ARM: sam9x5: fix ethernet pins in MII mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix pin setting in MII mode Signed-off-by: Jesse Gilles Signed-off-by: Andreas Bießmann diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c index 29e8aa4..9218546 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -246,14 +246,14 @@ void at91_macb_hw_init(void) #ifndef CONFIG_RMII /* Only emac0 support MII */ if (has_emac0()) { - at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ - at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ - at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ - at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ - at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ - at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ - at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ - at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ } #endif } -- cgit v0.10.2 From 2fd34f2636e2547dcc2a6085de1039928f989ba4 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 25 Feb 2013 00:58:57 +0000 Subject: arm: omap: map u_boot_lists section to .sram Output section .u_boot_list was left unmapped in u-boot-spl.lds for omap-common, causing the location counter to roll back to bteween .rodata and .data, making __image_copy_end and _end symbols wrong. Mapping output section .u_boot_list to memory .sram fixes these symbols' mapping. This modifies the SPL binary but has no functional impact, as __image_copy_end and _end are never used in SPLs and u_boot_list is empty for all 29 boards affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3 omap3_beagle am3517_crane igep0032 mt_ventoux pcm051 am3517_evm omap3_evm_quick_mmc am335x_evm_uart2 am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand omap3_overo igep0020 am335x_evm omap4_panda omap5_evm am335x_evm_uart4 devkit8000 tricorder mcx twister omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand). Signed-off-by: Albert ARIBAUD diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 9979c30..6755628 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -50,7 +50,7 @@ SECTIONS .u_boot_list : { #include - } + } > .sram . = ALIGN(4); __image_copy_end = .; -- cgit v0.10.2 From 65cdd6430ed026484bfb9dc67fcc587b85212eb4 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 25 Feb 2013 00:58:58 +0000 Subject: Remove linker lists (LGAs) from SPL linker scripts Many SPL linker scripts needlessly include linker lists (aka LGAs). Remove them whenever possible; keep it only in the seven am335x_evm variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot), where there is actual content in output section .u_boot_list. This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets byte-identical. Signed-off-by: Albert ARIBAUD diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 6dc681a..0f3222c 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -51,12 +51,6 @@ SECTIONS . = ALIGN(4); - .u_boot_list : { - #include - } - - . = ALIGN(4); - .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index f3bd5e7..0af3e0a 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -51,12 +51,6 @@ SECTIONS . = ALIGN(4); - .u_boot_list : { - #include - } - - . = ALIGN(4); - .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds new file mode 100644 index 0000000..1c3deef --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + .u_boot_list : { + #include + } >.sram + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sdram +} diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 6755628..88f4069 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -48,10 +48,6 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - .u_boot_list : { - #include - } > .sram - . = ALIGN(4); __image_copy_end = .; _end = .; diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds new file mode 100644 index 0000000..8321afb --- /dev/null +++ b/arch/arm/cpu/u-boot-spl.lds @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __image_copy_start = .; + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} + +#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE) +ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big"); +#endif diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index 656b2fb..52c986e 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -48,10 +48,6 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { - #include - } >.sram - . = ALIGN(4); .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index c5fd93c..dd5f266 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -49,11 +49,6 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .u_boot_list : { - #include - } >.sram - - . = ALIGN(4); .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index 86dc172..b3a41af 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -58,11 +58,6 @@ SECTIONS } . = ALIGN(4); - .u_boot_list : { - #include - } - - . = ALIGN(4); __rel_dyn_start = .; __rel_dyn_end = .; __dynsym_start = .; diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 20161a4..1958c2f 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -57,10 +57,6 @@ SECTIONS *(.data) } - .u_boot_list : { - #include - } - . = ALIGN(4); .rel.dyn : { diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 709c1f3..9eada95 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -286,7 +286,7 @@ #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 #define CONFIG_SPL_MUSB_NEW_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_AM33XX_BCH diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index aa90ba9..63ab123 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -234,7 +234,7 @@ #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM diff --git a/spl/Makefile b/spl/Makefile index aac6146..14095c8 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -119,7 +119,7 @@ ifeq ($(wildcard $(LDSCRIPT)),) LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-spl.lds endif ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds + LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot-spl.lds endif ifeq ($(wildcard $(LDSCRIPT)),) $(error could not find linker script) @@ -177,11 +177,7 @@ $(START): depend $(LIBS): depend $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) -# The following line expands into whole rule which generates u-boot.lst, -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(obj)u-boot.lst, $(LIBS))) -$(obj)u-boot-spl.lds: $(LDSCRIPT) $(obj)u-boot.lst depend +$(obj)u-boot-spl.lds: $(LDSCRIPT) depend $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@ depend: $(obj).depend -- cgit v0.10.2 From 3ebd1cbc49f0005092d69cf0d9a6e64d7a1c300b Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 25 Feb 2013 00:58:59 +0000 Subject: arm: make __bss_start and __bss_end__ compiler-generated Turn __bss_start and __bss_end__ from linker-generated to compiler-generated symbols, causing relocations for these symbols to change type, from R_ARM_ABS32 to R_ARM_RELATIVE. This should have no functional impact, as it affects references to __bss_start and __bss_end__ only before relocation, and no such references are done. Signed-off-by: Albert ARIBAUD diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index 81d954f..bba91d5 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -67,11 +67,17 @@ SECTIONS _end = .; - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - __bss_end__ = .; + ___bssend___ = .; + } + .bss_end ___bssend___ (OVERLAY) : { + KEEP(*(.__bss_end__)); } /DISCARD/ : { *(.dynstr*) } diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index e6b202b..e1bc8e7 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -81,11 +81,17 @@ SECTIONS *(.mmutable) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - __bss_end__ = .; + ___bssend___ = .; + } + .bss_end ___bssend___ (OVERLAY) : { + KEEP(*(.__bss_end__)); } /DISCARD/ : { *(.dynstr*) } diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 57111af..11c2674 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -39,6 +39,7 @@ GLCOBJS += div0.o SOBJS-y += crt0.o ifndef CONFIG_SPL_BUILD +COBJS-y += bss.o COBJS-y += board.o COBJS-y += bootm.o COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o diff --git a/arch/arm/lib/bss.c b/arch/arm/lib/bss.c new file mode 100644 index 0000000..7c0b154 --- /dev/null +++ b/arch/arm/lib/bss.c @@ -0,0 +1,39 @@ +/* + * Copyright 2013 Albert ARIBAUD + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * These two symbols are declared in a C file so that the linker + * uses R_ARM_RELATIVE relocation, rather than the R_ARM_ABS32 one + * it would use if the symbols were defined in the linker file. + * Using only R_ARM_RELATIVE relocation ensures that references to + * the symbols are correct after as well as before relocation. + * + * We need a 0-byte-size type for these symbols, and the compiler + * does not allow defining objects of C type 'void'. Using an empty + * struct is allowed by the compiler, but causes gcc versions 4.4 and + * below to complain about aliasing. Therefore we use the next best + * thing: zero-sized arrays, which are both 0-byte-size and exempt from + * aliasing warnings. + */ + +char __bss_start[0] __attribute__((used, section(".__bss_start"))); +char __bss_end__[0] __attribute__((used, section(".__bss_end__"))); diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index c41eed0..572bcea 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -41,15 +41,15 @@ SECTIONS *(.text*) } - . = ALIGN (4); + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - . = ALIGN (4); + . = ALIGN(4); .data : { *(.data*) } - . = ALIGN (4); + . = ALIGN(4); .got : { *(.got) } @@ -72,13 +72,21 @@ SECTIONS *(.dynsym) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + _end = .; + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - _end = .; + ___bssend___ = .; } - __bss_end__ =.; + .bss_end ___bssend___ (OVERLAY) : { + KEEP(*(.__bss_end__)); + } + /DISCARD/ : { *(.dynstr*) } /DISCARD/ : { *(.dynamic*) } /DISCARD/ : { *(.plt*) } diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 8409984..6272a10 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -41,15 +41,15 @@ SECTIONS *(.text*) } - . = ALIGN (4); + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - . = ALIGN (4); + . = ALIGN(4); .data : { *(.data*) } - . = ALIGN (4); + . = ALIGN(4); .got : { *(.got) } @@ -72,13 +72,21 @@ SECTIONS *(.dynsym) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + _end = .; + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - _end = .; + ___bssend___ = .; } - __bss_end__ =.; + .bss_end ___bssend___ (OVERLAY) : { + KEEP(*(.__bss_end__)); + } + /DISCARD/ : { *(.dynstr*) } /DISCARD/ : { *(.dynamic*) } /DISCARD/ : { *(.plt*) } diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index a3bd02b..488e1e7 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -72,13 +72,21 @@ SECTIONS *(.dynsym) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + _end = .; + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - _end = .; + ___bssend___ = .; } - __bss_end__ =.; + .bss_end ___bssend___ (OVERLAY) : { + KEEP(*(.__bss_end__)); + } + /DISCARD/ : { *(.dynstr*) } /DISCARD/ : { *(.dynamic*) } /DISCARD/ : { *(.plt*) } diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index 1bd1700..6dc26c8 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -72,13 +72,21 @@ SECTIONS *(.dynsym) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + _end = .; + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - _end = .; + ___bssend___ = .; } - __bss_end__ =.; + .bss_end ___bssend___ (OVERLAY) : { + KEEP(*(.__bss_end__)); + } + /DISCARD/ : { *(.dynstr*) } /DISCARD/ : { *(.dynamic*) } /DISCARD/ : { *(.plt*) } diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 5267729..12d7c12 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -80,11 +80,17 @@ SECTIONS _end = .; - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { + *(.bss*) . = ALIGN(4); - __bss_end__ = .; + ___bssend___ = .; + } + .bss_end ___bssend___ (OVERLAY) : { + KEEP(*(.__bss_end__)); } /DISCARD/ : { *(.bss*) } -- cgit v0.10.2 From ef123c525370463254a6f8e67563fdb0b0b46412 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 25 Feb 2013 00:59:00 +0000 Subject: Refactor linker-generated arrays Refactor linker-generated array code so that symbols which were previously linker-generated are now compiler- generated. This causes relocation records of type R_ARM_ABS32 to become R_ARM_RELATIVE, which makes code which uses LGA able to run before relocation as well as after. Note: this affects more than ARM targets, as linker- lists span possibly all target architectures, notably PowerPC. Conflicts: arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds arch/arm/cpu/armv7/omap-common/u-boot-spl.lds board/ait/cam_enc_4xx/u-boot-spl.lds board/davinci/da8xxevm/u-boot-spl-da850evm.lds board/davinci/da8xxevm/u-boot-spl-hawk.lds board/vpac270/u-boot-spl.lds Signed-off-by: Albert ARIBAUD diff --git a/.gitignore b/.gitignore index e40eb7b..be09894 100644 --- a/.gitignore +++ b/.gitignore @@ -44,7 +44,6 @@ /u-boot.dtb /u-boot.sb /u-boot.geany -/include/u-boot.lst # # Generated files diff --git a/Makefile b/Makefile index 55bd55c..6a4e364 100644 --- a/Makefile +++ b/Makefile @@ -556,10 +556,8 @@ GEN_UBOOT = \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot else GEN_UBOOT = \ - UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \ - sed -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\ cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ - $$UNDEF_LST $(__OBJS) \ + $(__OBJS) \ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ -Map u-boot.map -o u-boot endif @@ -592,11 +590,7 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot $(LDSCRIPT): depend $(MAKE) -C $(dir $@) $(notdir $@) -# The following line expands into whole rule which generates u-boot.lst, -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS))) -$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst +$(obj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@ nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend @@ -832,7 +826,6 @@ clean: $(obj)board/matrix_vision/*/bootscript.img \ $(obj)board/voiceblue/eeprom \ $(obj)u-boot.lds \ - $(obj)include/u-boot.lst \ $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \ $(obj)arch/blackfin/cpu/init.{lds,elf} @rm -f $(obj)include/bmp_logo.h @@ -870,7 +863,7 @@ clobber: tidy @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map} @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map} @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map} - @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst} + @rm -f $(obj)spl/u-boot-spl.lds @rm -f $(obj)MLO MLO.byteswap @rm -f $(obj)SPL @rm -f $(obj)tools/xway-swap-bytes diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds index 008ae89..c19285d 100644 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -51,7 +51,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds index 1c3deef..69f6d48 100644 --- a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds @@ -49,7 +49,7 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } >.sram . = ALIGN(4); diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index bba91d5..5e66dd1 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -49,7 +49,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index e1bc8e7..d4ad352 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds index 0b16d2a..4a3fc2a 100644 --- a/arch/avr32/cpu/u-boot.lds +++ b/arch/avr32/cpu/u-boot.lds @@ -50,7 +50,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); diff --git a/arch/blackfin/cpu/u-boot.lds b/arch/blackfin/cpu/u-boot.lds index 58db838..77f48c1 100644 --- a/arch/blackfin/cpu/u-boot.lds +++ b/arch/blackfin/cpu/u-boot.lds @@ -114,7 +114,7 @@ SECTIONS .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } >ram_data .text_l1 : diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index fe3d97d..1ae4184 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -54,7 +54,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } .bss ALIGN(0x4): diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds index 10513ab..ca18d46 100644 --- a/arch/mips/cpu/u-boot.lds +++ b/arch/mips/cpu/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds index cef19c5..5790948 100644 --- a/arch/nds32/cpu/n1213/u-boot.lds +++ b/arch/nds32/cpu/n1213/u-boot.lds @@ -55,7 +55,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); diff --git a/arch/nios2/cpu/u-boot.lds b/arch/nios2/cpu/u-boot.lds index d0eb80d..f937396 100644 --- a/arch/nios2/cpu/u-boot.lds +++ b/arch/nios2/cpu/u-boot.lds @@ -48,7 +48,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } /* INIT DATA sections - "Small" data (see the gcc -G option) diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds index ecee439..c58d979 100644 --- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds +++ b/arch/powerpc/cpu/74xx_7xx/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds index 7faefba..a34501b 100644 --- a/arch/powerpc/cpu/mpc512x/u-boot.lds +++ b/arch/powerpc/cpu/mpc512x/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds index c91e146..0d87c8c 100644 --- a/arch/powerpc/cpu/mpc5xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds @@ -68,7 +68,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds index ac7844d..cdb36c0 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds @@ -68,7 +68,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds index 1f46ead..6bd646b 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/arch/powerpc/cpu/mpc8220/u-boot.lds b/arch/powerpc/cpu/mpc8220/u-boot.lds index c147954..6e9967c 100644 --- a/arch/powerpc/cpu/mpc8220/u-boot.lds +++ b/arch/powerpc/cpu/mpc8220/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds index a713012..699fb85 100644 --- a/arch/powerpc/cpu/mpc824x/u-boot.lds +++ b/arch/powerpc/cpu/mpc824x/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds index 42385fc..2709f37 100644 --- a/arch/powerpc/cpu/mpc8260/u-boot.lds +++ b/arch/powerpc/cpu/mpc8260/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index d699def..905823c 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index f7c4a22..3bb7572 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -72,7 +72,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index 46dbaed..87522b8 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -54,7 +54,7 @@ SECTIONS _edata = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(8); diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 4a40a1f..8c6e66e 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -80,7 +80,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds index 8bfadf2..81804e3 100644 --- a/arch/powerpc/cpu/mpc86xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds @@ -67,7 +67,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index a96ddd5..2cadcc9 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -81,7 +81,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds index 1b781eb..94c26f1 100644 --- a/arch/sandbox/cpu/u-boot.lds +++ b/arch/sandbox/cpu/u-boot.lds @@ -27,7 +27,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } __u_boot_sandbox_option_start = .; diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds index 17f8091..9bf1d85 100644 --- a/arch/sh/cpu/sh2/u-boot.lds +++ b/arch/sh/cpu/sh2/u-boot.lds @@ -74,7 +74,7 @@ SECTIONS .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } PROVIDE (reloc_dst_end = .); diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/sh3/u-boot.lds index c831961..29352ad 100644 --- a/arch/sh/cpu/sh3/u-boot.lds +++ b/arch/sh/cpu/sh3/u-boot.lds @@ -80,7 +80,7 @@ SECTIONS .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } PROVIDE (reloc_dst_end = .); diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds index 0ecafcf..cf3da0d 100644 --- a/arch/sh/cpu/sh4/u-boot.lds +++ b/arch/sh/cpu/sh4/u-boot.lds @@ -77,7 +77,7 @@ SECTIONS .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } PROVIDE (reloc_dst_end = .); diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index 54f2fb7..ef5aa95 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -36,7 +36,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); diff --git a/board/BuS/eb_cpu5282/u-boot.lds b/board/BuS/eb_cpu5282/u-boot.lds index 0c92d31..43bd9b7 100644 --- a/board/BuS/eb_cpu5282/u-boot.lds +++ b/board/BuS/eb_cpu5282/u-boot.lds @@ -68,7 +68,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index 2bb876d..3ff3871 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -89,7 +89,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index 18f962c..c2ec827 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index dc8c4e9..e88bd97 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds index 18f962c..c2ec827 100644 --- a/board/RPXlite/u-boot.lds +++ b/board/RPXlite/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug index dc8c4e9..e88bd97 100644 --- a/board/RPXlite/u-boot.lds.debug +++ b/board/RPXlite/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds index 18f962c..c2ec827 100644 --- a/board/RPXlite_dw/u-boot.lds +++ b/board/RPXlite_dw/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug index b43a1e4..88c410c 100644 --- a/board/RPXlite_dw/u-boot.lds.debug +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds index 748e511..f9d2ec2 100644 --- a/board/RRvision/u-boot.lds +++ b/board/RRvision/u-boot.lds @@ -74,7 +74,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index 572bcea..7cf5b46 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -57,7 +57,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN (4); diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 6272a10..e9b5547 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -57,7 +57,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN (4); diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index 488e1e7..b79ea3c 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -57,7 +57,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN (4); diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds index 73e2f3f..5e0ed00 100644 --- a/board/adder/u-boot.lds +++ b/board/adder/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds index 289386b..900fe65 100644 --- a/board/altera/nios2-generic/u-boot.lds +++ b/board/altera/nios2-generic/u-boot.lds @@ -49,7 +49,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } /* INIT DATA sections - "Small" data (see the gcc -G option) diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds index beba978..3861b67 100644 --- a/board/amcc/acadia/u-boot-nand.lds +++ b/board/amcc/acadia/u-boot-nand.lds @@ -74,7 +74,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds index 2dd00d7..6308d49 100644 --- a/board/amcc/bamboo/u-boot-nand.lds +++ b/board/amcc/bamboo/u-boot-nand.lds @@ -75,7 +75,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds index 8ac5116..5fc9062 100644 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -75,7 +75,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds index beba978..3861b67 100644 --- a/board/amcc/kilauea/u-boot-nand.lds +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -74,7 +74,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index 18266ef..b4600de 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -75,7 +75,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds index 6b02784..521d12a 100644 --- a/board/amcc/sequoia/u-boot-ram.lds +++ b/board/amcc/sequoia/u-boot-ram.lds @@ -66,7 +66,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds index bc40fd6..5ee8fcc 100644 --- a/board/astro/mcf5373l/u-boot.lds +++ b/board/astro/mcf5373l/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds index d054f20..7421eec 100644 --- a/board/cobra5272/u-boot.lds +++ b/board/cobra5272/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index 2a6027f..357f59d 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -73,7 +73,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug index dc8c4e9..e88bd97 100644 --- a/board/cogent/u-boot.lds.debug +++ b/board/cogent/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug index d7a2e56..99cbed4 100644 --- a/board/cray/L1/u-boot.lds.debug +++ b/board/cray/L1/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index 8a306d6..987b52d 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -77,7 +77,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index 6dc26c8..eb83b6f 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -57,7 +57,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN (4); diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds index c8d3894..bd74d74 100644 --- a/board/eltec/mhpc/u-boot.lds +++ b/board/eltec/mhpc/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug index 92796e6..614bbb2 100644 --- a/board/eltec/mhpc/u-boot.lds.debug +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds index 22626d3..ea04eca 100644 --- a/board/emk/top860/u-boot.lds +++ b/board/emk/top860/u-boot.lds @@ -70,7 +70,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds index 1dcc22a..e5fa63e 100644 --- a/board/ep88x/u-boot.lds +++ b/board/ep88x/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index 7eca183..cca527f 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -76,7 +76,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds index ca7df45..4469b80 100644 --- a/board/esd/pmc440/u-boot-nand.lds +++ b/board/esd/pmc440/u-boot-nand.lds @@ -104,7 +104,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds index 0d6a0f3..7642bba 100644 --- a/board/esd/tasreg/u-boot.lds +++ b/board/esd/tasreg/u-boot.lds @@ -68,7 +68,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index fe5cf09..357a794 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -77,7 +77,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds index eac9c07..e2cfcfe 100644 --- a/board/evb64260/u-boot.lds +++ b/board/evb64260/u-boot.lds @@ -73,7 +73,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds index 6022dbc..450103d 100644 --- a/board/fads/u-boot.lds +++ b/board/fads/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds index c8d3894..bd74d74 100644 --- a/board/flagadm/u-boot.lds +++ b/board/flagadm/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug index 92796e6..614bbb2 100644 --- a/board/flagadm/u-boot.lds.debug +++ b/board/flagadm/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds index 2c151f2..f3c9ed8 100644 --- a/board/freescale/m5208evbe/u-boot.lds +++ b/board/freescale/m5208evbe/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds index dbd6f6a..ae0a48d 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds index 00932ae..603858b 100644 --- a/board/freescale/m5235evb/u-boot.lds +++ b/board/freescale/m5235evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds index d054f20..7421eec 100644 --- a/board/freescale/m5249evb/u-boot.lds +++ b/board/freescale/m5249evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds index f8116f6..6838247 100644 --- a/board/freescale/m5253demo/u-boot.lds +++ b/board/freescale/m5253demo/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds index d054f20..7421eec 100644 --- a/board/freescale/m5253evbe/u-boot.lds +++ b/board/freescale/m5253evbe/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds index 133ec01..e222e80 100644 --- a/board/freescale/m5271evb/u-boot.lds +++ b/board/freescale/m5271evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds index d054f20..7421eec 100644 --- a/board/freescale/m5272c3/u-boot.lds +++ b/board/freescale/m5272c3/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds index fc68de1..c18758a 100644 --- a/board/freescale/m5275evb/u-boot.lds +++ b/board/freescale/m5275evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds index ad49874..20f6c47 100644 --- a/board/freescale/m5282evb/u-boot.lds +++ b/board/freescale/m5282evb/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index d25a36f..15dfa7d 100644 --- a/board/freescale/m53017evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -74,7 +74,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds index 6616594..5013ff4 100644 --- a/board/freescale/m5329evb/u-boot.lds +++ b/board/freescale/m5329evb/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds index bc40fd6..5ee8fcc 100644 --- a/board/freescale/m5373evb/u-boot.lds +++ b/board/freescale/m5373evb/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m54418twr/u-boot.lds b/board/freescale/m54418twr/u-boot.lds index 36a4c26..2df386b 100644 --- a/board/freescale/m54418twr/u-boot.lds +++ b/board/freescale/m54418twr/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m54451evb/u-boot.lds b/board/freescale/m54451evb/u-boot.lds index 91328a4..4440d61 100644 --- a/board/freescale/m54451evb/u-boot.lds +++ b/board/freescale/m54451evb/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds index 36a4c26..2df386b 100644 --- a/board/freescale/m54455evb/u-boot.lds +++ b/board/freescale/m54455evb/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds index de4d0eb..269bf8a 100644 --- a/board/freescale/m547xevb/u-boot.lds +++ b/board/freescale/m547xevb/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds index fbbe0c5..68bdad4 100644 --- a/board/freescale/m548xevb/u-boot.lds +++ b/board/freescale/m548xevb/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 12d7c12..2d08fea 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds index 774c494..dac87db 100644 --- a/board/gaisler/gr_cpci_ax2000/u-boot.lds +++ b/board/gaisler/gr_cpci_ax2000/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } .data : diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds index f6d1301..78e0e2d 100644 --- a/board/gaisler/gr_ep2s60/u-boot.lds +++ b/board/gaisler/gr_ep2s60/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } .data : diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds index 7df6e83..87ea473 100644 --- a/board/gaisler/gr_xc3s_1500/u-boot.lds +++ b/board/gaisler/gr_xc3s_1500/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } .data : diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds index b241cbc..e854a16 100644 --- a/board/gaisler/grsim/u-boot.lds +++ b/board/gaisler/grsim/u-boot.lds @@ -87,7 +87,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } .data : diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds index 63c15b9..f247e56 100644 --- a/board/gaisler/grsim_leon2/u-boot.lds +++ b/board/gaisler/grsim_leon2/u-boot.lds @@ -87,7 +87,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } .data : diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds index 1cbe7e3..b061441 100644 --- a/board/gen860t/u-boot-flashenv.lds +++ b/board/gen860t/u-boot-flashenv.lds @@ -73,7 +73,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index dd89c70..9e9449d 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -74,7 +74,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index 124b183..958dd84 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -83,7 +83,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug index e1cf249..a3aeb60 100644 --- a/board/genietv/u-boot.lds.debug +++ b/board/genietv/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index f02eb1c..b2bb50d 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -75,7 +75,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug index e84cc79..4383c49 100644 --- a/board/hermes/u-boot.lds.debug +++ b/board/hermes/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index 7afae0a..3133c55 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -113,7 +113,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug index dc8c4e9..e88bd97 100644 --- a/board/hymod/u-boot.lds.debug +++ b/board/hymod/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index 6778eb1..40f4a38 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug index 3e075a8..9995288 100644 --- a/board/icu862/u-boot.lds.debug +++ b/board/icu862/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds index 0d6a0f3..6d13831 100644 --- a/board/idmr/u-boot.lds +++ b/board/idmr/u-boot.lds @@ -68,7 +68,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds index 18f962c..c2ec827 100644 --- a/board/ip860/u-boot.lds +++ b/board/ip860/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug index e47aff0..0b34177 100644 --- a/board/ip860/u-boot.lds.debug +++ b/board/ip860/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds index 4cca652..dcd53ec 100644 --- a/board/ivm/u-boot.lds +++ b/board/ivm/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug index 53a19b2..bae9fb2 100644 --- a/board/ivm/u-boot.lds.debug +++ b/board/ivm/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds index 033cff4..b6fa79f 100644 --- a/board/korat/u-boot-F7FC.lds +++ b/board/korat/u-boot-F7FC.lds @@ -110,7 +110,7 @@ SECTIONS . = .; .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index 18f962c..c2ec827 100644 --- a/board/kup/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index b43a1e4..88c410c 100644 --- a/board/kup/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds index 18f962c..c2ec827 100644 --- a/board/kup/kup4x/u-boot.lds +++ b/board/kup/kup4x/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug index b43a1e4..88c410c 100644 --- a/board/kup/kup4x/u-boot.lds.debug +++ b/board/kup/kup4x/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds index bc71b0d..30523dc 100644 --- a/board/lwmon/u-boot.lds +++ b/board/lwmon/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug index 0a3e646..1d1b76a 100644 --- a/board/lwmon/u-boot.lds.debug +++ b/board/lwmon/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/manroland/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds index e32ae37..8c75dea 100644 --- a/board/manroland/uc100/u-boot.lds +++ b/board/manroland/uc100/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds index 5a3a9ea..5707770 100644 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -77,7 +77,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds index 18f962c..c2ec827 100644 --- a/board/mbx8xx/u-boot.lds +++ b/board/mbx8xx/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug index 4155b60..063f2cc 100644 --- a/board/mbx8xx/u-boot.lds.debug +++ b/board/mbx8xx/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index 43f91f1..080829b 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index d7a2e56..99cbed4 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds index c378564..e186ee6 100644 --- a/board/mvblue/u-boot.lds +++ b/board/mvblue/u-boot.lds @@ -73,7 +73,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds index cdc1fda..ddb5a72 100644 --- a/board/netphone/u-boot.lds +++ b/board/netphone/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug index 900da64..e1fe052 100644 --- a/board/netphone/u-boot.lds.debug +++ b/board/netphone/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds index cdc1fda..ddb5a72 100644 --- a/board/netta/u-boot.lds +++ b/board/netta/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug index 900da64..e1fe052 100644 --- a/board/netta/u-boot.lds.debug +++ b/board/netta/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds index cdc1fda..ddb5a72 100644 --- a/board/netta2/u-boot.lds +++ b/board/netta2/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug index 900da64..e1fe052 100644 --- a/board/netta2/u-boot.lds.debug +++ b/board/netta2/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index cdc1fda..ddb5a72 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug index 6cbf4dc..3243fc0 100644 --- a/board/netvia/u-boot.lds.debug +++ b/board/netvia/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds index c8d3894..bd74d74 100644 --- a/board/nx823/u-boot.lds +++ b/board/nx823/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug index 92796e6..614bbb2 100644 --- a/board/nx823/u-boot.lds.debug +++ b/board/nx823/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/openrisc/openrisc-generic/u-boot.lds b/board/openrisc/openrisc-generic/u-boot.lds index 4cffacb..9024f30 100644 --- a/board/openrisc/openrisc-generic/u-boot.lds +++ b/board/openrisc/openrisc-generic/u-boot.lds @@ -29,7 +29,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } .rodata : { diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds index 18f962c..c2ec827 100644 --- a/board/quantum/u-boot.lds +++ b/board/quantum/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds index 3ef0d9e..9262aa5 100644 --- a/board/r360mpi/u-boot.lds +++ b/board/r360mpi/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index a86b568..c6560c6 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -80,7 +80,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = .; diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds index 28449b6..5bbb63f 100644 --- a/board/renesas/sh7752evb/u-boot.lds +++ b/board/renesas/sh7752evb/u-boot.lds @@ -78,7 +78,7 @@ SECTIONS PROVIDE (_egot = .); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } PROVIDE (reloc_dst_end = .); diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds index cf406ce..0717d04 100644 --- a/board/renesas/sh7757lcr/u-boot.lds +++ b/board/renesas/sh7757lcr/u-boot.lds @@ -79,7 +79,7 @@ SECTIONS .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } PROVIDE (reloc_dst_end = .); diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index ff95029..4662546 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -100,7 +100,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds b/board/samsung/smdk5250/smdk5250-uboot-spl.lds index 951d8ce..4ef6a51 100644 --- a/board/samsung/smdk5250/smdk5250-uboot-spl.lds +++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds @@ -49,7 +49,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } >.sram . = ALIGN(4); diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds index fbb442a..ae32b16 100644 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ b/board/samsung/smdk6400/u-boot-nand.lds @@ -50,7 +50,7 @@ SECTIONS . = align(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } . = align(4); diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index 7a0757f..6b99f13 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -118,7 +118,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index 07bd6fe..0b4192e 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -118,7 +118,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds index ae3afa1..ca13619 100644 --- a/board/sandpoint/u-boot.lds +++ b/board/sandpoint/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds index 6cf7a01..fa4de9d 100644 --- a/board/sixnet/u-boot.lds +++ b/board/sixnet/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds index f57f8a0..5929335 100644 --- a/board/snmc/qs850/u-boot.lds +++ b/board/snmc/qs850/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds index 18f962c..c2ec827 100644 --- a/board/snmc/qs860t/u-boot.lds +++ b/board/snmc/qs860t/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds index 18f962c..c2ec827 100644 --- a/board/spc1920/u-boot.lds +++ b/board/spc1920/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index f69e39d..b2ad343 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -78,7 +78,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug index 4155b60..063f2cc 100644 --- a/board/spd8xx/u-boot.lds.debug +++ b/board/spd8xx/u-boot.lds.debug @@ -110,7 +110,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds index cdc1fda..ddb5a72 100644 --- a/board/stx/stxxtc/u-boot.lds +++ b/board/stx/stxxtc/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug index 900da64..e1fe052 100644 --- a/board/stx/stxxtc/u-boot.lds.debug +++ b/board/stx/stxxtc/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index 1635875..ebfa890 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -86,7 +86,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index e1e1ccd..bab452c 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -82,7 +82,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds index fd2d72e..9504fcd 100644 --- a/board/v37/u-boot.lds +++ b/board/v37/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug index 2ce5a9a..18b7752 100644 --- a/board/w7o/u-boot.lds.debug +++ b/board/w7o/u-boot.lds.debug @@ -109,7 +109,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug index c4e5706..c02581d 100644 --- a/board/xes/xpedite1000/u-boot.lds.debug +++ b/board/xes/xpedite1000/u-boot.lds.debug @@ -114,7 +114,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + KEEP(*(SORT(.u_boot_list*))); } diff --git a/common/cmd_help.c b/common/cmd_help.c index f832a96..d9bdc4d 100644 --- a/common/cmd_help.c +++ b/common/cmd_help.c @@ -41,7 +41,7 @@ U_BOOT_CMD( ); /* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */ -ll_entry_declare(cmd_tbl_t, question_mark, cmd, cmd) = { +ll_entry_declare(cmd_tbl_t, question_mark, cmd) = { "?", CONFIG_SYS_MAXARGS, 1, do_help, "alias for 'help'", #ifdef CONFIG_SYS_LONGHELP diff --git a/config.mk b/config.mk index b7cd481..bb5c69a 100644 --- a/config.mk +++ b/config.mk @@ -23,8 +23,6 @@ ######################################################################### -include $(TOPDIR)/helper.mk - ifeq ($(CURDIR),$(SRCTREE)) dir := else diff --git a/doc/README.commands b/doc/README.commands index 923418b..9eb3671 100644 --- a/doc/README.commands +++ b/doc/README.commands @@ -15,24 +15,22 @@ help: Long description. This is a string **** Behind the scene ****** -The structure created is named with a special prefix (__u_boot_list_cmd_) -and placed by the linker in a special section. +The structure created is named with a special prefix and placed by +the linker in a special section using the linker lists mechanism +(see include/linker_lists.h) This makes it possible for the final link to extract all commands compiled into any object code and construct a static array so the -command can be found in an array starting at _u_boot_list_cmd__start. +command array can be iterated over using the linker lists macros. -To ensure that the linker does not discard these symbols when linking -full U-Boot we generate a list of all the commands we have built (based -on the sections mentioned above) and use that to force the linker to -first enter the symbol as undefined in the output object so that there -is then a need for the symbol to be kept (this is the UNDEF_SYM logic in -the Makefile). +The linker lists feature ensures that the linker does not discard +these symbols when linking full U-Boot even though they are not +referenced in the source code as such. If a new board is defined do not forget to define the command section by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these 3 lines: .u_boot_list : { - #include "u-boot.lst"; + KEEP(*(SORT(.u_boot_list*))); } diff --git a/helper.mk b/helper.mk deleted file mode 100644 index 79a1da0..0000000 --- a/helper.mk +++ /dev/null @@ -1,64 +0,0 @@ -# -# Copyright (C) 2012 Marek Vasut -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -######################################################################### - -## -# make_u_boot_list - Generate contents of u_boot_list section -# 1: The name of the resulting file (usually u-boot.lst) -# 2: Files to analyze for possible u_boot_list entries -# -# This function generates the contents of the u_boot_list section, -# including all the border symbols for it's subsections. The operation -# of this function is as follows, numbering goes per lines: -# -# 1) Dump the ELF header sections from all files supplied via $(2) -# 2) Filter out all other stuff that does not belong into .u_boot_list -# section. -# 3) Fix up the lines so that the resulting output is is in format -# ".u_boot_list.*". -# 4) Remove the last .something$, since that only contains the name -# of the variable to be put into a subsection. This name is irelevant -# for generation of border symbols, thus of no interest, remove it. -# 5) Take each line and for every dot "." in that line, print the whole -# line until that dot "." . This is important so that we have all -# parent border symbols generated as well. -# 6) Load every line and firstly append "\a" at the end and print the -# line. Next, append "@" at the end and print the line. Finally, -# append "~" at the end of line. This will make sense in conjunction -# with 6) and 7). -# 7) Sort the lines. It is imperative to use LC_COLLATE=C here because -# with this, the "\a" symbol is first and "~" symbol is last. Any -# other symbols fall inbetween. Symbols like "@", which marks the -# end of current line (representing current section) and ".", which -# means the line continues and thus represents subsection. -# 8) With such ordering, all lines ending with "\a" will float at the -# begining of all lines with the same prefix. Thus it is easy to -# replace "\a" with __start and make it the __start border symbol. -# Very similarly for "~", which will be always at the bottom and so -# can be replaced by "__end" and made into the __end border symbol. -# Finally, every line ending with "@" symbol will be transformed -# into " *(SORT(${line}*)); " format, which in the linker parlance -# will allow it to trap all symbols relevant to the subsection. -# -define make_u_boot_list -$(1): $(2) - $(OBJDUMP) -h $(2) | \ - sed -n -e '/.*\.u_boot_list[^ ]\+/ ! {d;n}' \ - -e 's/.*\(\.u_boot_list[^ ]\+\).*$$$$/\1/' \ - -e 's/\.[^\.]\+$$$$//' \ - -e ':s /^.\+$$$$/ { p;s/^\(.*\)\.[^\.]*$$$$/\1/;b s }' | \ - sed -n -e 'h;s/$$$$/\a/p;g;s/$$$$/@/p;g;s/$$$$/~/p;' | \ - LC_COLLATE=C sort -u | \ - sed -n -e '/\a$$$$/ { s/\./_/g;s/\a$$$$/__start = .;/p; }'\ - -e '/~$$$$/ { s/\./_/g;s/~$$$$/__end = .;/p; }'\ - -e '/@$$$$/ { s/\(.*\)@$$$$/*(SORT(\1.*));/p }' > $(1) -endef diff --git a/include/command.h b/include/command.h index 3785eb9..65692fd 100644 --- a/include/command.h +++ b/include/command.h @@ -175,7 +175,7 @@ int cmd_process(int flag, int argc, char * const argv[], _usage, _help, NULL) #define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \ - ll_entry_declare(cmd_tbl_t, _name, cmd, cmd) = \ + ll_entry_declare(cmd_tbl_t, _name, cmd) = \ U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ _usage, _help, _comp); diff --git a/include/env_callback.h b/include/env_callback.h index 62428d1..e89b6da 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -83,7 +83,7 @@ void env_callback_init(ENTRY *var_entry); } #else #define U_BOOT_ENV_CALLBACK(name, callback) \ - ll_entry_declare(struct env_clbk_tbl, name, env_clbk, env_clbk) = \ + ll_entry_declare(struct env_clbk_tbl, name, env_clbk) = \ {#name, callback} #endif diff --git a/include/linker_lists.h b/include/linker_lists.h index 0b405d7..6c28bf9 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -13,6 +13,96 @@ * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ + +/* + * There is no use in including this from ASM files, but that happens + * anyway, e.g. PPC kgdb.S includes command.h which incluse us. + * So just don't define anything when included from ASM. + */ + +#if !defined(__ASSEMBLY__) + +/** + * A linker list is constructed by grouping together linker input + * sections, each containning one entry of the list. Each input section + * contains a constant initialized variable which holds the entry's + * content. Linker list input sections are constructed from the list + * and entry names, plus a prefix which allows grouping all lists + * together. Assuming _list and _entry are the list and entry names, + * then the corresponding input section name is + * + * _u_boot_list + _2_ + @_list + _2_ + @_entry + * + * and the C variable name is + * + * .u_boot_list_ + 2_ + @_list + _2_ + @_entry + * + * This ensures uniqueness for both input section and C variable name. + * + * Note that the names differ only in the first character, "." for the + * setion and "_" for the variable, so that the linker cannot confuse + * section and symbol names. From now on, both names will be referred + * to as + * + * %u_boot_list_ + 2_ + @_list + _2_ + @_entry + * + * Entry variables need never be referred to directly. + * + * The naming scheme for input sections allows grouping all linker lists + * into a single linker output section and grouping all entries for a + * single list. + * + * Note the two '_2_' constant components in the names: their presence + * allows putting a start and end symbols around a list, by mapping + * these symbols to sections names with components "1" (before) and + * "3" (after) instead of "2" (within). + * Start and end symbols for a list can generally be defined as + * + * %u_boot_list_2_ + @_list + _1_... + * %u_boot_list_2_ + @_list + _3_... + * + * Start and end symbols for the whole of the linker lists area can be + * defined as + * + * %u_boot_list_1_... + * %u_boot_list_3_... + * + * Here is an example of the sorted sections which result from a list + * "array" made up of three entries : "first", "second" and "third", + * iterated at least once. + * + * .u_boot_list_2_array_1 + * .u_boot_list_2_array_2_first + * .u_boot_list_2_array_2_second + * .u_boot_list_2_array_2_third + * .u_boot_list_2_array_3 + * + * If lists must be divided into sublists (e.g. for iterating only on + * part of a list), one can simply give the list a name of the form + * 'outer_2_inner', where 'outer' is the global list name and 'inner' + * is the sub-list name. Iterators for the whole list should use the + * global list name ("outer"); iterators for only a sub-list should use + * the full sub-list name ("outer_2_inner"). + * + * Here is an example of the sections generated from a global list + * named "drivers", two sub-lists named "i2c" and "pci", and iterators + * defined for the whole list and each sub-list: + * + * %u_boot_list_2_drivers_1 + * %u_boot_list_2_drivers_2_i2c_1 + * %u_boot_list_2_drivers_2_i2c_2_first + * %u_boot_list_2_drivers_2_i2c_2_first + * %u_boot_list_2_drivers_2_i2c_2_second + * %u_boot_list_2_drivers_2_i2c_2_third + * %u_boot_list_2_drivers_2_i2c_3 + * %u_boot_list_2_drivers_2_pci_1 + * %u_boot_list_2_drivers_2_pci_2_first + * %u_boot_list_2_drivers_2_pci_2_second + * %u_boot_list_2_drivers_2_pci_2_third + * %u_boot_list_2_drivers_2_pci_3 + * %u_boot_list_2_drivers_3 + */ + #ifndef __LINKER_LISTS_H__ #define __LINKER_LISTS_H__ @@ -20,43 +110,28 @@ * ll_entry_declare() - Declare linker-generated array entry * @_type: Data type of the entry * @_name: Name of the entry - * @_section_u: Subsection of u_boot_list in which this entry is placed - * (with underscores instead of dots, for name concatenation) - * @_section_d: Subsection of u_boot_list in which this entry is placed - * (with dots, for section concatenation) + * @_list: name of the list. Should contain only characters allowed + * in a C variable name! * * This macro declares a variable that is placed into a linker-generated * array. This is a basic building block for more advanced use of linker- * generated arrays. The user is expected to build their own macro wrapper * around this one. * - * A variable declared using this macro must be compile-time initialized - * and is as such placed into subsection of special section, .u_boot_list. - * The subsection is specified by the _section_[u,d] parameter, see below. - * The base name of the variable is _name, yet the actual variable is - * declared as concatenation of - * - * %_u_boot_list_ + @_section_u + _ + @_name - * - * which ensures name uniqueness. This variable shall never be refered - * directly though. + * A variable declared using this macro must be compile-time initialized. * * Special precaution must be made when using this macro: - * 1) The _type must not contain the "static" keyword, otherwise the entry - * is not generated. * - * 2) The @_section_u and @_section_d variables must match, the only difference - * is that in @_section_u is every dot "." character present in @_section_d - * replaced by a single underscore "_" character in @_section_u. The actual - * purpose of these parameters is to select proper subsection in the global - * .u_boot_list section. + * 1) The _type must not contain the "static" keyword, otherwise the + * entry is generated and can be iterated but is listed in the map + * file and cannot be retrieved by name. * - * 3) In case a section is declared that contains some array elements AND a - * subsection of this section is declared and contains some elements, it is - * imperative that the elements are of the same type. + * 2) In case a section is declared that contains some array elements AND + * a subsection of this section is declared and contains some elements, + * it is imperative that the elements are of the same type. * * 4) In case an outer section is declared that contains some array elements - * AND am inner subsection of this section is declared and contains some + * AND an inner subsection of this section is declared and contains some * elements, then when traversing the outer section, even the elements of * the inner sections are present in the array. * @@ -66,39 +141,71 @@ * .y = 4, * }; */ -#define ll_entry_declare(_type, _name, _section_u, _section_d) \ - _type _u_boot_list_##_section_u##_##_name __attribute__(( \ - unused, aligned(4), \ - section(".u_boot_list."#_section_d"."#_name))) +#define ll_entry_declare(_type, _name, _list) \ + _type _u_boot_list_2_##_list##_2_##_name __aligned(4) \ + __attribute__((unused, \ + section(".u_boot_list_2_"#_list"_2_"#_name))) + +/** + * We need a 0-byte-size type for iterator symbols, and the compiler + * does not allow defining objects of C type 'void'. Using an empty + * struct is allowed by the compiler, but causes gcc versions 4.4 and + * below to complain about aliasing. Therefore we use the next best + * thing: zero-sized arrays, which are both 0-byte-size and exempt from + * aliasing warnings. + */ /** * ll_entry_start() - Point to first entry of linker-generated array * @_type: Data type of the entry - * @_section_u: Subsection of u_boot_list in which this entry is placed - * (with underscores instead of dots) + * @_list: Name of the list in which this entry is placed * * This function returns (_type *) pointer to the very first entry of a * linker-generated array placed into subsection of .u_boot_list section - * specified by _section_u argument. + * specified by _list argument. + * + * Since this macro defines an array start symbol, its leftmost index + * must be 2 and its rightmost index must be 1. * * Example: * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub); */ -#define ll_entry_start(_type, _section_u) \ - ({ \ - extern _type _u_boot_list_##_section_u##__start; \ - _type *_ll_result = &_u_boot_list_##_section_u##__start;\ - _ll_result; \ - }) +#define ll_entry_start(_type, _list) \ +({ \ + static char start[0] __aligned(4) __attribute__((unused, \ + section(".u_boot_list_2_"#_list"_1"))); \ + (_type *)&start; \ +}) /** - * ll_entry_count() - Return the number of elements in linker-generated array + * ll_entry_end() - Point after last entry of linker-generated array * @_type: Data type of the entry - * @_section_u: Subsection of u_boot_list in which this entry is placed + * @_list: Name of the list in which this entry is placed * (with underscores instead of dots) * + * This function returns (_type *) pointer after the very last entry of + * a linker-generated array placed into subsection of .u_boot_list + * section specified by _list argument. + * + * Since this macro defines an array end symbol, its leftmost index + * must be 2 and its rightmost index must be 3. + * + * Example: + * struct my_sub_cmd *msc = ll_entry_end(struct my_sub_cmd, cmd_sub); + */ +#define ll_entry_end(_type, _list) \ +({ \ + static char end[0] __aligned(4) __attribute__((unused, \ + section(".u_boot_list_2_"#_list"_3"))); \ + (_type *)&end; \ +}) +/** + * ll_entry_count() - Return the number of elements in linker-generated array + * @_type: Data type of the entry + * @_list: Name of the list of which the number of elements is computed + * * This function returns the number of elements of a linker-generated array - * placed into subsection of .u_boot_list section specified by _section_u + * placed into subsection of .u_boot_list section specified by _list * argument. The result is of an unsigned int type. * * Example: @@ -108,23 +215,19 @@ * for (i = 0; i < count; i++, msc++) * printf("Entry %i, x=%i y=%i\n", i, msc->x, msc->y); */ -#define ll_entry_count(_type, _section_u) \ +#define ll_entry_count(_type, _list) \ ({ \ - extern _type _u_boot_list_##_section_u##__start; \ - extern _type _u_boot_list_##_section_u##__end; \ - unsigned int _ll_result = \ - &_u_boot_list_##_section_u##__end - \ - &_u_boot_list_##_section_u##__start; \ + _type *start = ll_entry_start(_type, _list); \ + _type *end = ll_entry_end(_type, _list); \ + unsigned int _ll_result = end - start; \ _ll_result; \ }) - /** * ll_entry_get() - Retrieve entry from linker-generated array by name * @_type: Data type of the entry * @_name: Name of the entry - * @_section_u: Subsection of u_boot_list in which this entry is placed - * (with underscores instead of dots) + * @_list: Name of the list in which this entry is placed * * This function returns a pointer to a particular entry in LG-array * identified by the subsection of u_boot_list where the entry resides @@ -138,11 +241,54 @@ * ... * struct my_sub_cmd *c = ll_entry_get(struct my_sub_cmd, my_sub_cmd, cmd_sub); */ -#define ll_entry_get(_type, _name, _section_u) \ +#define ll_entry_get(_type, _name, _list) \ ({ \ - extern _type _u_boot_list_##_section_u##_##_name; \ - _type *_ll_result = &_u_boot_list_##_section_u##_##_name;\ + extern _type _u_boot_list_2_##_list##_2_##_name; \ + _type *_ll_result = \ + &_u_boot_list_2_##_list##_2_##_name; \ _ll_result; \ }) +/** + * ll_start() - Point to first entry of first linker-generated array + * @_type: Data type of the entry + * + * This function returns (_type *) pointer to the very first entry of + * the very first linker-generated array. + * + * Since this macro defines the start of the linker-generated arrays, + * its leftmost index must be 1. + * + * Example: + * struct my_sub_cmd *msc = ll_start(struct my_sub_cmd); + */ +#define ll_start(_type) \ +({ \ + static char start[0] __aligned(4) __attribute__((unused, \ + section(".u_boot_list_1"))); \ + (_type *)&start; \ +}) + +/** + * ll_entry_end() - Point after last entry of last linker-generated array + * @_type: Data type of the entry + * + * This function returns (_type *) pointer after the very last entry of + * the very last linker-generated array. + * + * Since this macro defines the end of the linker-generated arrays, + * its leftmost index must be 3. + * + * Example: + * struct my_sub_cmd *msc = ll_end(struct my_sub_cmd); + */ +#define ll_end(_type) \ +({ \ + static char end[0] __aligned(4) __attribute__((unused, \ + section(".u_boot_list_3"))); \ + (_type *)&end; \ +}) + +#endif /* __ASSEMBLY__ */ + #endif /* __LINKER_LISTS_H__ */ diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile index 9c77826..3a2a2d4 100644 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -32,7 +32,6 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -62,11 +61,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile index 9c77826..3a2a2d4 100644 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -32,7 +32,6 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -62,11 +61,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile index 9c77826..3a2a2d4 100644 --- a/nand_spl/board/freescale/mpc8572ds/Makefile +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -32,7 +32,6 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -62,11 +61,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile index fd0dfc1..3d57059 100644 --- a/nand_spl/board/freescale/mx31pdk/Makefile +++ b/nand_spl/board/freescale/mx31pdk/Makefile @@ -6,7 +6,6 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL @@ -38,11 +37,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds -Map $(nandobj)u-boot-spl.map \ -o $@ -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT) +$(nandobj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ diff --git a/nand_spl/board/freescale/mx31pdk/u-boot.lds b/nand_spl/board/freescale/mx31pdk/u-boot.lds index a26110f..0656176 100644 --- a/nand_spl/board/freescale/mx31pdk/u-boot.lds +++ b/nand_spl/board/freescale/mx31pdk/u-boot.lds @@ -49,7 +49,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + *(SORT(.u_boot_list*)); } . = ALIGN(4); diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index c3495ec..f7bdf92 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -32,7 +32,6 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \ $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -62,11 +61,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index 9b2c0d7..fb7d561 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -27,7 +27,6 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -57,11 +56,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile index 9c77826..3a2a2d4 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -32,7 +32,6 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -62,11 +61,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ diff --git a/nand_spl/board/karo/tx25/Makefile b/nand_spl/board/karo/tx25/Makefile index 82489d2..9f9c589 100644 --- a/nand_spl/board/karo/tx25/Makefile +++ b/nand_spl/board/karo/tx25/Makefile @@ -27,7 +27,6 @@ include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL @@ -59,11 +58,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds -Map $(nandobj)u-boot-spl.map \ -o $@ -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT) +$(nandobj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/nand_spl/board/karo/tx25/u-boot.lds index ee36131..ea84d64 100644 --- a/nand_spl/board/karo/tx25/u-boot.lds +++ b/nand_spl/board/karo/tx25/u-boot.lds @@ -49,7 +49,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + *(SORT(.u_boot_list*)); } . = ALIGN(4); diff --git a/nand_spl/board/samsung/smdk6400/u-boot.lds b/nand_spl/board/samsung/smdk6400/u-boot.lds index 2ed6466..66b412e 100644 --- a/nand_spl/board/samsung/smdk6400/u-boot.lds +++ b/nand_spl/board/samsung/smdk6400/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include + *(SORT(.u_boot_list*)); } . = ALIGN(4); diff --git a/spl/.gitignore b/spl/.gitignore index 8cf487e..7c88147 100644 --- a/spl/.gitignore +++ b/spl/.gitignore @@ -2,4 +2,3 @@ u-boot-spl u-boot-spl.bin u-boot-spl.lds u-boot-spl.map -u-boot.lst -- cgit v0.10.2 From d67b0d97b156f9ec2fc4c838d84b1e510d6e49b4 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 11 Mar 2013 08:44:53 +0000 Subject: Add Boundary Devices Nitrogen6X boards Signed-off-by: Eric Nelson diff --git a/MAINTAINERS b/MAINTAINERS index 175bbe2..f490d62 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1037,6 +1037,14 @@ Pali Rohár nokia_rx51 ARM ARMV7 (OMAP34xx SoC) +Eric Nelson + nitrogen6dl i.MX6DL 1GB + nitrogen6dl2g i.MX6DL 2GB + nitrogen6q i.MX6Q/6D 1GB + nitrogen6q2g i.MX6Q/6D 2GB + nitrogen6s i.MX6S 512MB + nitrogen6s1g i.MX6S 1GB + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg new file mode 100644 index 0000000..16a37d0 --- /dev/null +++ b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7974 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg new file mode 100644 index 0000000..0607703 --- /dev/null +++ b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43040319 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03040279 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43040321 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03030251 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4d434248 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c4d +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34424543 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x49324933 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001a0017 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00170027 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000a001f +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/6x_bootscript.txt b/board/boundary/nitrogen6x/6x_bootscript.txt new file mode 100644 index 0000000..061b3a4 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript.txt @@ -0,0 +1,63 @@ +setenv bootargs enable_wait_mode=off +setenv nextcon 0; + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + setenv fbmem "fbmem=28M"; + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +i2c dev 2 +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs $fbmem +setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait" + +if test "sata" = "${dtype}" ; then + setenv bootargs "$bootargs root=/dev/sda1" ; +else + setenv "bootargs $bootargs root=/dev/mmcblk0p1" ; +fi +${fs}load ${dtype} ${disk}:1 10800000 /boot/uImage && bootm 10800000 ; +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_bootscript_android.txt b/board/boundary/nitrogen6x/6x_bootscript_android.txt new file mode 100644 index 0000000..0982cf8 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript_android.txt @@ -0,0 +1,64 @@ +${dtype} dev ${disk} + +setenv bootargs enable_wait_mode=off +setenv nextcon 0; +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ; + +i2c dev 2 + +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=28M"; + else + setenv fbcon ${fbcon},28M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs fbcon=$fbcon +${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000 +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt new file mode 100644 index 0000000..0982cf8 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt @@ -0,0 +1,64 @@ +${dtype} dev ${disk} + +setenv bootargs enable_wait_mode=off +setenv nextcon 0; +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ; + +i2c dev 2 + +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=28M"; + else + setenv fbcon ${fbcon},28M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs fbcon=$fbcon +${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000 +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt new file mode 100644 index 0000000..0d8e8e5 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_upgrade.txt @@ -0,0 +1,45 @@ +setenv stdout serial,vga +echo "check U-Boot" ; +setenv offset 0x400 +if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then + echo "read $filesize bytes from SD card" ; + if sf probe || sf probe || \ + sf probe 1 27000000 || sf probe 1 27000000 ; then + echo "probed SPI ROM" ; + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + echo "------- U-Boot versions match" ; + else + echo "Need U-Boot upgrade" ; + echo "Program in 5 seconds" ; + for n in 5 4 3 2 1 ; do + echo $n ; + sleep 1 ; + done + echo "erasing" ; + sf erase 0 0x50000 ; + # two steps to prevent bricking + echo "programming" ; + sf write 0x12000000 $offset $filesize ; + echo "verifying" ; + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + while echo "---- U-Boot upgraded. reset" ; do + sleep 120 + done + else + echo "Read verification error" ; + fi + else + echo "Error re-reading EEPROM" ; + fi + fi + else + echo "Error reading boot loader from EEPROM" ; + fi + else + echo "Error initializing EEPROM" ; + fi ; +else + echo "No U-Boot image found on SD card" ; +fi diff --git a/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg new file mode 100644 index 0000000..de33e65 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg new file mode 100644 index 0000000..19707cf --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg new file mode 100644 index 0000000..dd6a423 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg new file mode 100644 index 0000000..d5d06e2 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile new file mode 100644 index 0000000..fe1e5e0 --- /dev/null +++ b/board/boundary/nitrogen6x/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Boundary Devices +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := nitrogen6x.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README new file mode 100644 index 0000000..5049093 --- /dev/null +++ b/board/boundary/nitrogen6x/README @@ -0,0 +1,92 @@ +U-Boot for the Boundary Devices Nitrogen6X and +Freescale i.MX6Q SabreLite boards + +This file contains information for the port of +U-Boot to the Boundary Devices Nitrogen6X and +Freescale i.MX6Q SabreLite boards. + +1. Boot source, boot from SPI NOR +--------------------------------- +The configuration in this directory supports both the +Nitrogen6X and Freescale SabreLite board, but in a +different fashion from Freescale's implementation in +board/freescale/mx6qsabrelite. + +In particular, this image supports booting from SPI NOR +and saving the environment to SPI NOR. + +It does not support 'boot from SD' at offset 0x400 +except through the 'bmode' command. + http://lists.denx.de/pipermail/u-boot/2012-August/131151.html + +2. Boots using 6x_bootscript on SATA or SD card +----------------------------------------------- +The default bootcmd for these boards is configured +to look for and source a boot script named '6x_bootscript' +in the root of the first partition of the following +devices: + + sata 0 + mmc 0 + mmc 1 + +They're searched in the order listed above, trying both the +ext2 and fat filesystems. + +2. Maintaining the SPI NOR +-------------------------- +A couple of convenience commands + + clearenv - clear environment to factory default + upgradeu - look and source a boot script named + '6x_upgrade' to upgrade the U-Boot version + in SPI NOR. The search is the same as for + 6x_bootscript described above. + +3. Display support +------------------ +U-Boot support for the following displays is configured by +default: + + HDMI - 1024 x 768 for maximum compatibility + Hannstar-XGA - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1) + wsvga-lvds - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600) + wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480) + +Since the ipuv3_fb display driver currently supports only a single display, +this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect +or the I2C touch controller of the LVDS and RGB displays in the priority +listed above. + +Setting 'panel' environment variable to one of the names above will +override auto-detection and force activation of the specified panel. + +4. Building +------------ + +To build U-Boot for one of the Nitrogen6x or SabreLite board: + + make nitrogen6x_config + make u-boot.imx + +Note that 'nitrogen6x' is a placeholder. The complete list of supported +board configurations is shown in tha MAINTAINERS file: + nitrogen6q i.MX6Q/6D 1GB + nitrogen6dl i.MX6DL 1GB + nitrogen6s i.MX6S 512MB + nitrogen6q2g i.MX6Q/6D 2GB + nitrogen6dl2g i.MX6DL 2GB + nitrogen6s1g i.MX6S 1GB + +The -6q variants support either the i.MX6Quad or i.MX6Dual processors +and are configured for a 64-bit memory bus at 1066 MHz. + +The -6dl variants also use a 64-bit memory bus, operated at 800MHz. + +The -6s variants use a 32-bit memory bus at 800MHz. + +If you place the u-boot.imx into a single-partition SD card +along with a binary version of the boot script 6x_upgrade.txt, +you can program it using 'upgradeu': + + U-Boot> run upgradeu diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg new file mode 100644 index 0000000..e7d1f86 --- /dev/null +++ b/board/boundary/nitrogen6x/clocks.cfg @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg new file mode 100644 index 0000000..c315812 --- /dev/null +++ b/board/boundary/nitrogen6x/ddr-setup.cfg @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +/* + * MDSCR con_req + */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg new file mode 100644 index 0000000..d6da96c --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_4x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg new file mode 100644 index 0000000..0b1c35c --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg new file mode 100644 index 0000000..680a853 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6q.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg new file mode 100644 index 0000000..f57ab0e --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg new file mode 100644 index 0000000..b5af5cc --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6s.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_2x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg new file mode 100644 index 0000000..5aeefc8 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_2x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c new file mode 100644 index 0000000..0dbb6d2 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -0,0 +1,895 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013, Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +int dram_init(void) +{ + gd->ram_size = CONFIG_DDR_MB * 1024 * 1024; + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C1, SGTL5000 */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2 Camera, MIPI */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3, J15 - RGB connector */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +/* wl1271 pads on nitrogen6x */ +iomux_v3_cfg_t const wl12xx_pads[] = { + (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(WEAK_PULLDOWN), + (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(OUTPUT_40OHM), + (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(OUTPUT_40OHM), +}; +#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) +#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15) +#define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16) + +/* Button assignments for J14 */ +static iomux_v3_cfg_t const button_pads[] = { + /* Menu */ + MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Back */ + MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Labelled Search (mapped to Power under Android) */ + MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Home */ + MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Down */ + MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Up */ + MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */ + gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */ + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + udelay(1000 * 10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */ + gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +iomux_v3_cfg_t const usb_pads[] = { + MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + /* Reset USB hub */ + gpio_direction_output(IMX_GPIO_NR(7, 12), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(7, 12), 1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(IMX_GPIO_NR(7, 0)); + ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); + } else { + gpio_direction_input(IMX_GPIO_NR(2, 6)); + ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +} +#endif + +u32 get_board_rev(void) +{ + return 0x63000; +} + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + /* SS1 */ + MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +void setup_spi(void) +{ + gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + +static void setup_buttons(void) +{ + imx_iomux_v3_setup_multiple_pads(button_pads, + ARRAY_SIZE(button_pads)); +} + +#ifdef CONFIG_CMD_SATA + +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3<phy_stat0) & HDMI_PHY_HPD; +} + +static void enable_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + u8 reg; + printf("%s: setup HDMI monitor\n", __func__); + reg = readb(&hdmi->phy_conf0); + reg |= HDMI_PHY_CONF0_PDZ_MASK; + writeb(reg, &hdmi->phy_conf0); + + udelay(3000); + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return ((0 == i2c_set_bus_num(dev->bus)) + && + (0 == i2c_probe(dev->addr))); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + gpio_direction_output(LVDS_BACKLIGHT_GP, 1); +} + +static void enable_rgb(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + rgb_pads, + ARRAY_SIZE(rgb_pads)); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); +} + +static struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x4, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x38, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "wsvga-lvds", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x48, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_i2c, + .enable = enable_rgb, + .mode = { + .name = "wvga-rgb", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 37037, + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + } + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + ret = -EINVAL; + } + return (0 != ret); +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + + int reg; + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET + |MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* Turn on HDMI PHY clock */ + reg = __raw_readl(&mxc_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK + |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; + writel(reg, &mxc_ccm->CCGR2); + + /* clear HDMI PHY reset */ + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + + /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ + writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); + writel(0x13<pfd_480_set); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <gpr[3]); + + /* backlights off until needed */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + gpio_direction_input(LVDS_BACKLIGHT_GP); + gpio_direction_input(RGB_BACKLIGHT_GP); +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + /* Disable wl1271 For Nitrogen6w */ + gpio_direction_input(WL12XX_WL_IRQ_GP); + gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); + gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); + + imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); + setup_buttons(); + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + return 0; +} + +int checkboard(void) +{ + if (gpio_get_value(WL12XX_WL_IRQ_GP)) + puts("Board: Nitrogen6X\n"); + else + puts("Board: SABRE Lite\n"); + + return 0; +} + +struct button_key { + char const *name; + unsigned gpnum; + char ident; +}; + +static struct button_key const buttons[] = { + {"back", IMX_GPIO_NR(2, 2), 'B'}, + {"home", IMX_GPIO_NR(2, 4), 'H'}, + {"menu", IMX_GPIO_NR(2, 1), 'M'}, + {"search", IMX_GPIO_NR(2, 3), 'S'}, + {"volup", IMX_GPIO_NR(7, 13), 'V'}, + {"voldown", IMX_GPIO_NR(4, 5), 'v'}, +}; + +/* + * generate a null-terminated string containing the buttons pressed + * returns number of keys pressed + */ +static int read_keys(char *buf) +{ + int i, numpressed = 0; + for (i = 0; i < ARRAY_SIZE(buttons); i++) { + if (!gpio_get_value(buttons[i].gpnum)) + buf[numpressed++] = buttons[i].ident; + } + buf[numpressed] = '\0'; + return numpressed; +} + +static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char envvalue[ARRAY_SIZE(buttons)+1]; + int numpressed = read_keys(envvalue); + setenv("keybd", envvalue); + return numpressed == 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "Tests for keypresses, sets 'keybd' environment variable", + "Returns 0 (true) to shell if key is pressed." +); + +#ifdef CONFIG_PREBOOT +static char const kbd_magic_prefix[] = "key_magic"; +static char const kbd_command_prefix[] = "key_cmd"; + +static void preboot_keys(void) +{ + int numpressed; + char keypress[ARRAY_SIZE(buttons)+1]; + numpressed = read_keys(keypress); + if (numpressed) { + char *kbd_magic_keys = getenv("magic_keys"); + char *suffix; + /* + * loop over all magic keys + */ + for (suffix = kbd_magic_keys; *suffix; ++suffix) { + char *keys; + char magic[sizeof(kbd_magic_prefix) + 1]; + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); + keys = getenv(magic); + if (keys) { + if (!strcmp(keys, keypress)) + break; + } + } + if (*suffix) { + char cmd_name[sizeof(kbd_command_prefix) + 1]; + char *cmd; + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv(cmd_name); + if (cmd) { + setenv("preboot", cmd); + return; + } + } + } +} +#endif + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_PREBOOT + preboot_keys(); +#endif + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} diff --git a/boards.cfg b/boards.cfg index 7a0b79d..fb3b197 100644 --- a/boards.cfg +++ b/boards.cfg @@ -255,6 +255,12 @@ mx6qsabreauto arm armv7 mx6qsabreauto freesca mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg eco5pk arm armv7 eco5pk 8dtech omap3 +nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 +nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 +nitrogen6q arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 +nitrogen6q2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 +nitrogen6s arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 +nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,SDRAM_MB=1024 cm_t35 arm armv7 cm_t35 - omap3 omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h new file mode 100644 index 0000000..93e7fe4 --- /dev/null +++ b/include/configs/nitrogen6x.h @@ -0,0 +1,285 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * Configuration settings for the Boundary Devices Nitrogen6X + * and Freescale i.MX6Q Sabre Lite boards. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_MACH_TYPE 3769 + +#include +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* OCOTP Configs */ +#define CONFIG_CMD_IMXOTP +#ifdef CONFIG_CMD_IMXOTP +#define CONFIG_IMX_OTP +#define IMX_OTP_BASE OCOTP_BASE_ADDR +#define IMX_OTP_ADDR_MAX 0x7F +#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA +#define IMX_OTPWRITE_ENABLED +#endif + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#ifdef CONFIG_MX6Q +#define CONFIG_CMD_SATA +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Miscellaneous commands */ +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR + +/* Framebuffer and LCD */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_PREBOOT "" + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#ifdef CONFIG_CMD_SATA +#define CONFIG_DRIVE_SATA "sata " +#else +#define CONFIG_DRIVE_SATA +#endif + +#ifdef CONFIG_CMD_MMC +#define CONFIG_DRIVE_MMC "mmc " +#else +#define CONFIG_DRIVE_MMC +#endif + +#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc1\0" \ + "clearenv=if sf probe || sf probe || sf probe 1 ; then " \ + "sf erase 0xc0000 0x2000 && " \ + "echo restored environment to factory default ; fi\0" \ + "bootcmd=for dtype in " CONFIG_DRIVE_TYPES \ + "; do " \ + "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ + "for fs in fat ext2 ; do " \ + "${fs}load " \ + "${dtype} ${disk}:1 " \ + "10008000 " \ + "/6x_bootscript" \ + "&& source 10008000 ; " \ + "done ; " \ + "done ; " \ + "done; " \ + "setenv stdout serial,vga ; " \ + "echo ; echo 6x_bootscript not found ; " \ + "echo ; echo serial console at 115200, 8N1 ; echo ; " \ + "echo details at http://boundarydevices.com/6q_bootscript ; " \ + "setenv stdout serial\0" \ + "upgradeu=for dtype in " CONFIG_DRIVE_TYPES \ + "; do " \ + "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ + "for fs in fat ext2 ; do " \ + "${fs}load ${dtype} ${disk}:1 10008000 " \ + "/6x_upgrade " \ + "&& source 10008000 ; " \ + "done ; " \ + "done ; " \ + "done\0" \ + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +/* #define CONFIG_ENV_IS_IN_MMC */ +#define CONFIG_ENV_IS_IN_SPI_FLASH + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#define CONFIG_SYS_DCACHE_OFF + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#define CONFIG_CMD_BMP + +#define CONFIG_CMD_TIME +#define CONFIG_SYS_ALT_MEMTEST + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 0678587fb6f517d40c461f1d43fe7a6ff430f168 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 26 Feb 2013 12:28:27 +0000 Subject: ARM: implement some Cortex-A9 errata workarounds Various errata exist in the Cortex-A9 CPU, and may be worked around by setting some bits in a CP15 diagnostic register. Add code to implement the workarounds, enabled by new CONFIG_ options. This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S, and modified to remove the logic to conditionally apply the WAR (since we know exactly which CPU we're running on given the U-Boot configuration), and use r0 instead of r10 for consistency with the rest of U-Boot's cpu_init_cp15(). Signed-off-by: Stephen Warren Acked-by: Simon Glass diff --git a/README b/README index d51ece9..e45ae4a 100644 --- a/README +++ b/README @@ -485,6 +485,16 @@ The following options need to be configured: Thumb2 this flag will result in Thumb2 code generated by GCC. + CONFIG_ARM_ERRATA_742230 + CONFIG_ARM_ERRATA_743622 + CONFIG_ARM_ERRATA_751472 + + If set, the workarounds for these ARM errata are applied early + during U-Boot startup. Note that these options force the + workarounds to be applied; no CPU-type/version detection + exists, unlike the similar options in the Linux kernel. Do not + set these options unless they apply! + - Linux Kernel Interface: CONFIG_CLOCKS_IN_MHZ diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 6b59529d..30f02d3 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -309,6 +309,25 @@ ENTRY(cpu_init_cp15) orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache #endif mcr p15, 0, r0, c1, c0, 0 + +#ifdef CONFIG_ARM_ERRATA_742230 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 4 @ set bit #4 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_743622 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 6 @ set bit #6 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_751472 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 11 @ set bit #11 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15) -- cgit v0.10.2 From c44bb3a30f5a1332176edce1a91c0e2cf666ee8f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 26 Feb 2013 12:28:28 +0000 Subject: ARM: tegra: enable some CPU errata workarounds Tegra20 has a Cortex A9 r1p1, and Tegra30 has a Cortex A9 r2p9. As such, some CPU errata exist, and must be worked around. These must be worked around in the bootloader, since in general, the kernel (especially a multi-platform kernel) needs to support being launched in non-secure mode (normal world), and hence may not be able to write to the CP15 register to enable these workarounds. Signed-off-by: Stephen Warren diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 33e5f52..186e023 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -26,6 +26,12 @@ #include "tegra-common.h" /* + * Errata configuration + */ +#define CONFIG_ARM_ERRATA_742230 +#define CONFIG_ARM_ERRATA_751472 + +/* * NS16550 Configuration */ #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 04517e1..f6c07c6 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -26,6 +26,12 @@ #include "tegra-common.h" /* + * Errata configuration + */ +#define CONFIG_ARM_ERRATA_743622 +#define CONFIG_ARM_ERRATA_751472 + +/* * NS16550 Configuration */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -- cgit v0.10.2 From 2f3ec3402714d2ad20475b016487c7559ccba383 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 7 Feb 2013 07:16:24 +0000 Subject: tegra: usb: set USB_PORTS_MAX to correct value Both Tegra20 and Tegra30 have a max of 3 USB controllers. Signed-off-by: Lucas Stach Acked-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c index 1bccf2b..f151fb2 100644 --- a/arch/arm/cpu/armv7/tegra20/usb.c +++ b/arch/arm/cpu/armv7/tegra20/usb.c @@ -44,7 +44,7 @@ #endif enum { - USB_PORTS_MAX = 4, /* Maximum ports we allow */ + USB_PORTS_MAX = 3, /* Maximum ports we allow */ }; /* Parameters we need for USB */ -- cgit v0.10.2 From b0bbab8a149ad4c3f764fa7ecff79788769cab99 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 7 Feb 2013 07:16:25 +0000 Subject: tegra: usb: make controller init functions more self contained There is no need to pass around all those parameters. The init functions are able to easily extract all the needed setup info on their own. This allows to move out the controller init into ehci_hcd_init later on, without having to save away global state for later use and thus bloating the file global state. Signed-off-by: Lucas Stach Acked-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c index f151fb2..07c1ade 100644 --- a/arch/arm/cpu/armv7/tegra20/usb.c +++ b/arch/arm/cpu/armv7/tegra20/usb.c @@ -198,11 +198,12 @@ void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) } /* set up the UTMI USB controller with the parameters provided */ -static int init_utmi_usb_controller(struct fdt_usb *config, - struct usb_ctlr *usbctlr, const u32 timing[]) +static int init_utmi_usb_controller(struct fdt_usb *config) { u32 val; int loop_count; + const unsigned *timing; + struct usb_ctlr *usbctlr = config->reg; clock_enable(config->periph_id); @@ -229,6 +230,8 @@ static int init_utmi_usb_controller(struct fdt_usb *config, * PLL Delay CONFIGURATION settings. The following parameters control * the bring up of the plls. */ + timing = usb_pll[clock_get_osc_freq()]; + val = readl(&usbctlr->utmip_misc_cfg1); clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); @@ -331,12 +334,12 @@ static int init_utmi_usb_controller(struct fdt_usb *config, #endif /* set up the ULPI USB controller with the parameters provided */ -static int init_ulpi_usb_controller(struct fdt_usb *config, - struct usb_ctlr *usbctlr) +static int init_ulpi_usb_controller(struct fdt_usb *config) { u32 val; int loop_count; struct ulpi_viewport ulpi_vp; + struct usb_ctlr *usbctlr = config->reg; /* set up ULPI reference clock on pllp_out4 */ clock_enable(PERIPH_ID_DEV2_OUT); @@ -408,8 +411,7 @@ static int init_ulpi_usb_controller(struct fdt_usb *config, return 0; } #else -static int init_ulpi_usb_controller(struct fdt_usb *config, - struct usb_ctlr *usbctlr) +static int init_ulpi_usb_controller(struct fdt_usb *config) { printf("No code to set up ULPI controller, please enable" "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); @@ -430,22 +432,20 @@ static void config_clock(const u32 timing[]) * @param config USB port configuration * @return 0 if ok, -1 if error (too many ports) */ -static int add_port(struct fdt_usb *config, const u32 timing[]) +static int add_port(struct fdt_usb *config) { - struct usb_ctlr *usbctlr = config->reg; - if (port_count == USB_PORTS_MAX) { printf("tegrausb: Cannot register more than %d ports\n", USB_PORTS_MAX); return -1; } - if (config->utmi && init_utmi_usb_controller(config, usbctlr, timing)) { + if (config->utmi && init_utmi_usb_controller(config)) { printf("tegrausb: Cannot init port\n"); return -1; } - if (config->ulpi && init_ulpi_usb_controller(config, usbctlr)) { + if (config->ulpi && init_ulpi_usb_controller(config)) { printf("tegrausb: Cannot init port\n"); return -1; } @@ -558,7 +558,7 @@ int board_usb_init(const void *blob) return -1; } - if (add_port(&config, usb_pll[freq])) + if (add_port(&config)) return -1; set_host_mode(&config); } -- cgit v0.10.2 From a4bdcc38c94f5d693b3ad65a70fd1aeac9436d64 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 7 Feb 2013 07:16:26 +0000 Subject: tegra: usb: remove unneeded function parameter Just a dead parameter, never actually used. Signed-off-by: Lucas Stach Acked-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c index 07c1ade..2007483 100644 --- a/arch/arm/cpu/armv7/tegra20/usb.c +++ b/arch/arm/cpu/armv7/tegra20/usb.c @@ -486,8 +486,7 @@ int tegrausb_stop_port(int portnum) return 0; } -int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz, - struct fdt_usb *config) +int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) { const char *phy, *mode; @@ -535,7 +534,6 @@ int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz, int board_usb_init(const void *blob) { struct fdt_usb config; - unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC); enum clock_osc_freq freq; int node_list[USB_PORTS_MAX]; int node, count, i; @@ -552,7 +550,7 @@ int board_usb_init(const void *blob) node = node_list[i]; if (!node) continue; - if (fdt_decode_usb(blob, node, osc_freq, &config)) { + if (fdt_decode_usb(blob, node, &config)) { debug("Cannot decode USB node %s\n", fdt_get_name(blob, node, NULL)); return -1; -- cgit v0.10.2 From fdb4b9a71c93d5bd9e04df52be4587516ade6fb1 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 7 Feb 2013 07:16:27 +0000 Subject: tegra: usb: move controller init into start_port There is no need to init a USB controller before the upper layers indicate that they are actually going to use it. board_usb_init now only parses the device tree and sets up the common pll. Signed-off-by: Lucas Stach Acked-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c index 2007483..e4165e0 100644 --- a/arch/arm/cpu/armv7/tegra20/usb.c +++ b/arch/arm/cpu/armv7/tegra20/usb.c @@ -79,6 +79,7 @@ struct fdt_usb { unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ unsigned enabled:1; /* 1 to enable, 0 to disable */ unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ + unsigned initialized:1; /* has this port already been initialized? */ enum dr_mode dr_mode; /* dual role mode */ enum periph_id periph_id;/* peripheral id */ struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ @@ -426,44 +427,36 @@ static void config_clock(const u32 timing[]) timing[PARAM_CPCON], timing[PARAM_LFCON]); } -/** - * Add a new USB port to the list of available ports. - * - * @param config USB port configuration - * @return 0 if ok, -1 if error (too many ports) - */ -static int add_port(struct fdt_usb *config) +int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor) { - if (port_count == USB_PORTS_MAX) { - printf("tegrausb: Cannot register more than %d ports\n", - USB_PORTS_MAX); + struct fdt_usb *config; + struct usb_ctlr *usbctlr; + + if (portnum >= port_count) return -1; - } + + config = &port[portnum]; + + /* skip init, if the port is already initialized */ + if (config->initialized) + goto success; if (config->utmi && init_utmi_usb_controller(config)) { - printf("tegrausb: Cannot init port\n"); + printf("tegrausb: Cannot init port %d\n", portnum); return -1; } if (config->ulpi && init_ulpi_usb_controller(config)) { - printf("tegrausb: Cannot init port\n"); + printf("tegrausb: Cannot init port %d\n", portnum); return -1; } - port[port_count++] = *config; - - return 0; -} - -int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor) -{ - struct usb_ctlr *usbctlr; + set_host_mode(config); - if (portnum >= port_count) - return -1; - set_host_mode(&port[portnum]); + config->initialized = 1; - usbctlr = port[portnum].reg; +success: + usbctlr = config->reg; *hccr = (u32)&usbctlr->cap_length; *hcor = (u32)&usbctlr->usb_cmd; return 0; @@ -483,6 +476,8 @@ int tegrausb_stop_port(int portnum) writel(2, &usbctlr->usb_cmd); udelay(1000); + port[portnum].initialized = 0; + return 0; } @@ -546,6 +541,12 @@ int board_usb_init(const void *blob) count = fdtdec_find_aliases_for_id(blob, "usb", COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); for (i = 0; i < count; i++) { + if (port_count == USB_PORTS_MAX) { + printf("tegrausb: Cannot register more than %d ports\n", + USB_PORTS_MAX); + return -1; + } + debug("USB %d: ", i); node = node_list[i]; if (!node) @@ -555,10 +556,10 @@ int board_usb_init(const void *blob) fdt_get_name(blob, node, NULL)); return -1; } + config.initialized = 0; - if (add_port(&config)) - return -1; - set_host_mode(&config); + /* add new USB port to the list of available ports */ + port[port_count++] = config; } return 0; -- cgit v0.10.2 From a63eb6bbcc73c6bde716b23383139b8079f02144 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 7 Feb 2013 07:16:28 +0000 Subject: tegra: usb: various small cleanups Remove unneeded headers, function prototype and stale comment, that doesn't match the actual codebase anymore. Signed-off-by: Lucas Stach Acked-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c index e4165e0..3fdd5df 100644 --- a/arch/arm/cpu/armv7/tegra20/usb.c +++ b/arch/arm/cpu/armv7/tegra20/usb.c @@ -25,21 +25,15 @@ #include #include #include -#include -#include -#include #include #include -#include -#include -#include #include #include #ifdef CONFIG_USB_ULPI #ifndef CONFIG_USB_ULPI_VIEWPORT #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ - define CONFIG_USB_ULPI_VIEWPORT" + define CONFIG_USB_ULPI_VIEWPORT" #endif #endif @@ -191,11 +185,6 @@ void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) /* Enable the UTMIP PHY */ if (config->utmi) setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); - - /* - * TODO: where do we take the USB1 out of reset? The old code would - * take USB3 out of reset, but not USB1. This code doesn't do either. - */ } /* set up the UTMI USB controller with the parameters provided */ diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h index fdbd127..b18c850 100644 --- a/arch/arm/include/asm/arch-tegra20/usb.h +++ b/arch/arm/include/asm/arch-tegra20/usb.h @@ -243,9 +243,6 @@ struct usb_ctlr { #define VBUS_VLD_STS (1 << 26) -/* Change the USB host port into host mode */ -void usb_set_host_mode(void); - /* Setup USB on the board */ int board_usb_init(const void *blob); -- cgit v0.10.2 From 7ae18f3725fe3e2033888cf431f71ac08aaa8e1c Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 7 Feb 2013 07:16:29 +0000 Subject: tegra: usb: move implementation into right directory This moves the Tegra USB implementation into the drivers/usb/host directory. Note that this merges the old /arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code changes, just moving stuff around. v2: While at it also move some defines and the usb.h header file to make usb driver usable for Tegra30. NOTE: A lot more work is required to properly init the PHYs and PLL_U on Tegra30, this is just to make porting easier and it does no harm here. Signed-off-by: Lucas Stach Acked-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile index 54ed8c4..c8a8504 100644 --- a/arch/arm/cpu/armv7/tegra20/Makefile +++ b/arch/arm/cpu/armv7/tegra20/Makefile @@ -27,7 +27,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o COBJS-$(CONFIG_PWM_TEGRA) += pwm.o COBJS-$(CONFIG_VIDEO_TEGRA) += display.o diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c deleted file mode 100644 index 3fdd5df..0000000 --- a/arch/arm/cpu/armv7/tegra20/usb.c +++ /dev/null @@ -1,555 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010,2011 NVIDIA Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_USB_ULPI - #ifndef CONFIG_USB_ULPI_VIEWPORT - #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ - define CONFIG_USB_ULPI_VIEWPORT" - #endif -#endif - -enum { - USB_PORTS_MAX = 3, /* Maximum ports we allow */ -}; - -/* Parameters we need for USB */ -enum { - PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ - PARAM_DIVM, /* PLL INPUT DIVIDER */ - PARAM_DIVP, /* POST DIVIDER (2^N) */ - PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ - PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ - PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ - PARAM_STABLE_COUNT, /* PLL-U STABLE count */ - PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ - PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ - PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ - PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ - - PARAM_COUNT -}; - -/* Possible port types (dual role mode) */ -enum dr_mode { - DR_MODE_NONE = 0, - DR_MODE_HOST, /* supports host operation */ - DR_MODE_DEVICE, /* supports device operation */ - DR_MODE_OTG, /* supports both */ -}; - -/* Information about a USB port */ -struct fdt_usb { - struct usb_ctlr *reg; /* address of registers in physical memory */ - unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ - unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ - unsigned enabled:1; /* 1 to enable, 0 to disable */ - unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ - unsigned initialized:1; /* has this port already been initialized? */ - enum dr_mode dr_mode; /* dual role mode */ - enum periph_id periph_id;/* peripheral id */ - struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ - struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */ -}; - -static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ -static unsigned port_count; /* Number of available ports */ - -/* - * This table has USB timing parameters for each Oscillator frequency we - * support. There are four sets of values: - * - * 1. PLLU configuration information (reference clock is osc/clk_m and - * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). - * - * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz - * ---------------------------------------------------------------------- - * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) - * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) - * Filter frequency (MHz) 1 4.8 6 2 - * CPCON 1100b 0011b 1100b 1100b - * LFCON0 0 0 0 0 - * - * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: - * - * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz - * --------------------------------------------------------------------------- - * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) - * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) - * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) - * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) - * - * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and - * SessEnd. Each of these signals have their own debouncer and for each of - * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or - * BIAS_DEBOUNCE_B). - * - * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: - * 0xffff -> No debouncing at all - * ms = *1000 / (1/19.2MHz) / 4 - * - * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: - * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 - * - * We need to use only DebounceA for BOOTROM. We don't need the DebounceB - * values, so we can keep those to default. - * - * 4. The 20 microsecond delay after bias cell operation. - */ -static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { - /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ - { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, - { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, - { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, - { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } -}; - -/* UTMIP Idle Wait Delay */ -static const u8 utmip_idle_wait_delay = 17; - -/* UTMIP Elastic limit */ -static const u8 utmip_elastic_limit = 16; - -/* UTMIP High Speed Sync Start Delay */ -static const u8 utmip_hs_sync_start_delay = 9; - -/* Put the port into host mode */ -static void set_host_mode(struct fdt_usb *config) -{ - /* - * If we are an OTG port, check if remote host is driving VBus and - * bail out in this case. - */ - if (config->dr_mode == DR_MODE_OTG && - (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) - return; - - /* - * If not driving, we set the GPIO to enable VBUS. We assume - * that the pinmux is set up correctly for this. - */ - if (fdt_gpio_isvalid(&config->vbus_gpio)) { - fdtdec_setup_gpio(&config->vbus_gpio); - gpio_direction_output(config->vbus_gpio.gpio, - (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? - 0 : 1); - debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, - (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? - "low" : "high"); - } -} - -void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) -{ - /* Reset the USB controller with 2us delay */ - reset_periph(config->periph_id, 2); - - /* - * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under - * base address - */ - if (config->has_legacy_mode) - setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); - - /* Put UTMIP1/3 in reset */ - setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); - - /* Enable the UTMIP PHY */ - if (config->utmi) - setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); -} - -/* set up the UTMI USB controller with the parameters provided */ -static int init_utmi_usb_controller(struct fdt_usb *config) -{ - u32 val; - int loop_count; - const unsigned *timing; - struct usb_ctlr *usbctlr = config->reg; - - clock_enable(config->periph_id); - - /* Reset the usb controller */ - usbf_reset_controller(config, usbctlr); - - /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ - clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); - - /* Follow the crystal clock disable by >100ns delay */ - udelay(1); - - /* - * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP - * mux must be switched to actually use a_sess_vld threshold. - */ - if (fdt_gpio_isvalid(&config->vbus_gpio)) { - clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, - VBUS_SENSE_CTL_MASK, - VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); - } - - /* - * PLL Delay CONFIGURATION settings. The following parameters control - * the bring up of the plls. - */ - timing = usb_pll[clock_get_osc_freq()]; - - val = readl(&usbctlr->utmip_misc_cfg1); - clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, - timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); - clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, - timing[PARAM_ACTIVE_DELAY_COUNT] << - UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); - writel(val, &usbctlr->utmip_misc_cfg1); - - /* Set PLL enable delay count and crystal frequency count */ - val = readl(&usbctlr->utmip_pll_cfg1); - clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, - timing[PARAM_ENABLE_DELAY_COUNT] << - UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); - clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, - timing[PARAM_XTAL_FREQ_COUNT] << - UTMIP_XTAL_FREQ_COUNT_SHIFT); - writel(val, &usbctlr->utmip_pll_cfg1); - - /* Setting the tracking length time */ - clrsetbits_le32(&usbctlr->utmip_bias_cfg1, - UTMIP_BIAS_PDTRK_COUNT_MASK, - timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); - - /* Program debounce time for VBUS to become valid */ - clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, - UTMIP_DEBOUNCE_CFG0_MASK, - timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); - - setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); - - /* Disable battery charge enabling bit */ - setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); - - clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); - setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); - - /* - * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT - * Setting these fields, together with default values of the - * other fields, results in programming the registers below as - * follows: - * UTMIP_HSRX_CFG0 = 0x9168c000 - * UTMIP_HSRX_CFG1 = 0x13 - */ - - /* Set PLL enable delay count and Crystal frequency count */ - val = readl(&usbctlr->utmip_hsrx_cfg0); - clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, - utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); - clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, - utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); - writel(val, &usbctlr->utmip_hsrx_cfg0); - - /* Configure the UTMIP_HS_SYNC_START_DLY */ - clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, - UTMIP_HS_SYNC_START_DLY_MASK, - utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); - - /* Preceed the crystal clock disable by >100ns delay. */ - udelay(1); - - /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ - setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); - - /* Finished the per-controller init. */ - - /* De-assert UTMIP_RESET to bring out of reset. */ - clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); - - /* Wait for the phy clock to become valid in 100 ms */ - for (loop_count = 100000; loop_count != 0; loop_count--) { - if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) - break; - udelay(1); - } - if (!loop_count) - return -1; - - /* Disable ICUSB FS/LS transceiver */ - clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); - - /* Select UTMI parallel interface */ - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, - PTS_UTMI << PTS_SHIFT); - clrbits_le32(&usbctlr->port_sc1, STS); - - /* Deassert power down state */ - clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | - UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); - clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | - UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); - - return 0; -} - -#ifdef CONFIG_USB_ULPI -/* if board file does not set a ULPI reference frequency we default to 24MHz */ -#ifndef CONFIG_ULPI_REF_CLK -#define CONFIG_ULPI_REF_CLK 24000000 -#endif - -/* set up the ULPI USB controller with the parameters provided */ -static int init_ulpi_usb_controller(struct fdt_usb *config) -{ - u32 val; - int loop_count; - struct ulpi_viewport ulpi_vp; - struct usb_ctlr *usbctlr = config->reg; - - /* set up ULPI reference clock on pllp_out4 */ - clock_enable(PERIPH_ID_DEV2_OUT); - clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); - - /* reset ULPI phy */ - if (fdt_gpio_isvalid(&config->phy_reset_gpio)) { - fdtdec_setup_gpio(&config->phy_reset_gpio); - gpio_direction_output(config->phy_reset_gpio.gpio, 0); - mdelay(5); - gpio_set_value(config->phy_reset_gpio.gpio, 1); - } - - /* Reset the usb controller */ - clock_enable(config->periph_id); - usbf_reset_controller(config, usbctlr); - - /* enable pinmux bypass */ - setbits_le32(&usbctlr->ulpi_timing_ctrl_0, - ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); - - /* Select ULPI parallel interface */ - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT); - - /* enable ULPI transceiver */ - setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); - - /* configure ULPI transceiver timings */ - val = 0; - writel(val, &usbctlr->ulpi_timing_ctrl_1); - - val |= ULPI_DATA_TRIMMER_SEL(4); - val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); - val |= ULPI_DIR_TRIMMER_SEL(4); - writel(val, &usbctlr->ulpi_timing_ctrl_1); - udelay(10); - - val |= ULPI_DATA_TRIMMER_LOAD; - val |= ULPI_STPDIRNXT_TRIMMER_LOAD; - val |= ULPI_DIR_TRIMMER_LOAD; - writel(val, &usbctlr->ulpi_timing_ctrl_1); - - /* set up phy for host operation with external vbus supply */ - ulpi_vp.port_num = 0; - ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; - - if (ulpi_init(&ulpi_vp)) { - printf("Tegra ULPI viewport init failed\n"); - return -1; - } - - ulpi_set_vbus(&ulpi_vp, 1, 1); - ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); - - /* enable wakeup events */ - setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); - - /* Enable and wait for the phy clock to become valid in 100 ms */ - setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); - for (loop_count = 100000; loop_count != 0; loop_count--) { - if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) - break; - udelay(1); - } - if (!loop_count) - return -1; - clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); - - return 0; -} -#else -static int init_ulpi_usb_controller(struct fdt_usb *config) -{ - printf("No code to set up ULPI controller, please enable" - "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); - return -1; -} -#endif - -static void config_clock(const u32 timing[]) -{ - clock_start_pll(CLOCK_ID_USB, - timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], - timing[PARAM_CPCON], timing[PARAM_LFCON]); -} - -int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor) -{ - struct fdt_usb *config; - struct usb_ctlr *usbctlr; - - if (portnum >= port_count) - return -1; - - config = &port[portnum]; - - /* skip init, if the port is already initialized */ - if (config->initialized) - goto success; - - if (config->utmi && init_utmi_usb_controller(config)) { - printf("tegrausb: Cannot init port %d\n", portnum); - return -1; - } - - if (config->ulpi && init_ulpi_usb_controller(config)) { - printf("tegrausb: Cannot init port %d\n", portnum); - return -1; - } - - set_host_mode(config); - - config->initialized = 1; - -success: - usbctlr = config->reg; - *hccr = (u32)&usbctlr->cap_length; - *hcor = (u32)&usbctlr->usb_cmd; - return 0; -} - -int tegrausb_stop_port(int portnum) -{ - struct usb_ctlr *usbctlr; - - usbctlr = port[portnum].reg; - - /* Stop controller */ - writel(0, &usbctlr->usb_cmd); - udelay(1000); - - /* Initiate controller reset */ - writel(2, &usbctlr->usb_cmd); - udelay(1000); - - port[portnum].initialized = 0; - - return 0; -} - -int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) -{ - const char *phy, *mode; - - config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode) { - if (0 == strcmp(mode, "host")) - config->dr_mode = DR_MODE_HOST; - else if (0 == strcmp(mode, "peripheral")) - config->dr_mode = DR_MODE_DEVICE; - else if (0 == strcmp(mode, "otg")) - config->dr_mode = DR_MODE_OTG; - else { - debug("%s: Cannot decode dr_mode '%s'\n", __func__, - mode); - return -FDT_ERR_NOTFOUND; - } - } else { - config->dr_mode = DR_MODE_HOST; - } - - phy = fdt_getprop(blob, node, "phy_type", NULL); - config->utmi = phy && 0 == strcmp("utmi", phy); - config->ulpi = phy && 0 == strcmp("ulpi", phy); - config->enabled = fdtdec_get_is_enabled(blob, node); - config->has_legacy_mode = fdtdec_get_bool(blob, node, - "nvidia,has-legacy-mode"); - config->periph_id = clock_decode_periph_id(blob, node); - if (config->periph_id == PERIPH_ID_NONE) { - debug("%s: Missing/invalid peripheral ID\n", __func__); - return -FDT_ERR_NOTFOUND; - } - fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); - fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio", - &config->phy_reset_gpio); - debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " - "vbus=%d, phy_reset=%d, dr_mode=%d\n", - config->enabled, config->has_legacy_mode, config->utmi, - config->ulpi, config->periph_id, config->vbus_gpio.gpio, - config->phy_reset_gpio.gpio, config->dr_mode); - - return 0; -} - -int board_usb_init(const void *blob) -{ - struct fdt_usb config; - enum clock_osc_freq freq; - int node_list[USB_PORTS_MAX]; - int node, count, i; - - /* Set up the USB clocks correctly based on our oscillator frequency */ - freq = clock_get_osc_freq(); - config_clock(usb_pll[freq]); - - /* count may return <0 on error */ - count = fdtdec_find_aliases_for_id(blob, "usb", - COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); - for (i = 0; i < count; i++) { - if (port_count == USB_PORTS_MAX) { - printf("tegrausb: Cannot register more than %d ports\n", - USB_PORTS_MAX); - return -1; - } - - debug("USB %d: ", i); - node = node_list[i]; - if (!node) - continue; - if (fdt_decode_usb(blob, node, &config)) { - debug("Cannot decode USB node %s\n", - fdt_get_name(blob, node, NULL)); - return -1; - } - config.initialized = 0; - - /* add new USB port to the list of available ports */ - port[port_count++] = config; - } - - return 0; -} diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h new file mode 100644 index 0000000..b18c850 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_USB_H_ +#define _TEGRA_USB_H_ + + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[6]; + + /* 0x140 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x150 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint async_tt_sts; + + /* 0x160 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; /* is this port_sc1 on some controllers? */ + uint icusb_ctrl; + + /* 0x170 */ + uint ulpi_viewport; + uint reserved7; + uint endpt_nak; + uint endpt_nak_enable; + + /* 0x180 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x1a0 */ + uint reserved9; + uint otgsc; + uint usb_mode; + uint endpt_setup_stat; + + /* 0x1b0 */ + uint reserved10[20]; + + /* 0x200 */ + uint reserved11[0x80]; + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[4]; + + /* 0x424 */ + uint ulpi_timing_ctrl_0; + uint ulpi_timing_ctrl_1; + uint reserved13[53]; + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + + +/* USB1_LEGACY_CTRL */ +#define USB1_NO_LEGACY_MODE 1 + +#define VBUS_SENSE_CTL_SHIFT 1 +#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) +#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 +#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 +#define VBUS_SENSE_CTL_AB_SESS_VLD 2 +#define VBUS_SENSE_CTL_A_SESS_VLD 3 + +/* USB2_IF_ULPI_TIMING_CTRL_0 */ +#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) +#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) + +/* USB2_IF_ULPI_TIMING_CTRL_1 */ +#define ULPI_DATA_TRIMMER_LOAD (1 << 0) +#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) +#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) +#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) +#define ULPI_DIR_TRIMMER_LOAD (1 << 24) +#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) + +/* USBx_IF_USB_SUSP_CTRL_0 */ +#define ULPI_PHY_ENB (1 << 13) +#define UTMIP_PHY_ENB (1 << 12) +#define UTMIP_RESET (1 << 11) +#define USB_PHY_CLK_VALID (1 << 7) +#define USB_SUSP_CLR (1 << 5) + +/* USBx_UTMIP_MISC_CFG1 */ +#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 +#define UTMIP_PLLU_STABLE_COUNT_MASK \ + (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) +#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 +#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) +#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) + +/* USBx_UTMIP_PLL_CFG1_0 */ +#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 +#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ + (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) +#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 +#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff + +/* USBx_UTMIP_BIAS_CFG1_0 */ +#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 +#define UTMIP_BIAS_PDTRK_COUNT_MASK \ + (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) + +#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 +#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff + +/* USBx_UTMIP_TX_CFG0_0 */ +#define UTMIP_FS_PREAMBLE_J (1 << 19) + +/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ +#define UTMIP_PD_CHRG 1 + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_XCVR_LSBIAS_SE (1 << 21) + +/* USBx_UTMIP_SPARE_CFG0_0 */ +#define FUSE_SETUP_SEL (1 << 3) + +/* USBx_UTMIP_HSRX_CFG0_0 */ +#define UTMIP_IDLE_WAIT_SHIFT 15 +#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) +#define UTMIP_ELASTIC_LIMIT_SHIFT 10 +#define UTMIP_ELASTIC_LIMIT_MASK \ + (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) + +/* USBx_UTMIP_HSRX_CFG0_1 */ +#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 +#define UTMIP_HS_SYNC_START_DLY_MASK \ + (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT) + +/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ +#define IC_ENB1 (1 << 3) + +/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ +#define PTS_SHIFT 30 +#define PTS_MASK (3U << PTS_SHIFT) +#define PTS_UTMI 0 +#define PTS_RESERVED 1 +#define PTS_ULPI 2 +#define PTS_ICUSB_SER 3 + +#define STS (1 << 29) +#define WKOC (1 << 22) +#define WKDS (1 << 21) +#define WKCN (1 << 20) + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) +#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) +#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) + +/* USBx_UTMIP_XCVR_CFG1_0 */ +#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) + +/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ +#define VBUS_VLD_STS (1 << 26) + + +/* Setup USB on the board */ +int board_usb_init(const void *blob); + +/** + * Start up the given port number (ports are numbered from 0 on each board). + * This returns values for the appropriate hccr and hcor addresses to use for + * USB EHCI operations. + * + * @param portnum port number to start + * @param hccr returns start address of EHCI HCCR registers + * @param hcor returns start address of EHCI HCOR registers + * @return 0 if ok, -1 on error (generally invalid port number) + */ +int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor); + +/** + * Stop the current port + * + * @return 0 if ok, -1 if no port was active + */ +int tegrausb_stop_port(int portnum); + +#endif /* _TEGRA_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h index e1de044..ad5c01d 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra.h +++ b/arch/arm/include/asm/arch-tegra20/tegra.h @@ -29,7 +29,6 @@ #include #define TEGRA_USB1_BASE 0xC5000000 -#define TEGRA_USB3_BASE 0xC5008000 #define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h deleted file mode 100644 index b18c850..0000000 --- a/arch/arm/include/asm/arch-tegra20/usb.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA_USB_H_ -#define _TEGRA_USB_H_ - - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[6]; - - /* 0x140 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x150 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint async_tt_sts; - - /* 0x160 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; /* is this port_sc1 on some controllers? */ - uint icusb_ctrl; - - /* 0x170 */ - uint ulpi_viewport; - uint reserved7; - uint endpt_nak; - uint endpt_nak_enable; - - /* 0x180 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x1a0 */ - uint reserved9; - uint otgsc; - uint usb_mode; - uint endpt_setup_stat; - - /* 0x1b0 */ - uint reserved10[20]; - - /* 0x200 */ - uint reserved11[0x80]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[4]; - - /* 0x424 */ - uint ulpi_timing_ctrl_0; - uint ulpi_timing_ctrl_1; - uint reserved13[53]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - - -/* USB1_LEGACY_CTRL */ -#define USB1_NO_LEGACY_MODE 1 - -#define VBUS_SENSE_CTL_SHIFT 1 -#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) -#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 -#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 -#define VBUS_SENSE_CTL_AB_SESS_VLD 2 -#define VBUS_SENSE_CTL_A_SESS_VLD 3 - -/* USB2_IF_ULPI_TIMING_CTRL_0 */ -#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) -#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) - -/* USB2_IF_ULPI_TIMING_CTRL_1 */ -#define ULPI_DATA_TRIMMER_LOAD (1 << 0) -#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) -#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) -#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) -#define ULPI_DIR_TRIMMER_LOAD (1 << 24) -#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) - -/* USBx_IF_USB_SUSP_CTRL_0 */ -#define ULPI_PHY_ENB (1 << 13) -#define UTMIP_PHY_ENB (1 << 12) -#define UTMIP_RESET (1 << 11) -#define USB_PHY_CLK_VALID (1 << 7) -#define USB_SUSP_CLR (1 << 5) - -/* USBx_UTMIP_MISC_CFG1 */ -#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 -#define UTMIP_PLLU_STABLE_COUNT_MASK \ - (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) -#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 -#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ - (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) -#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) - -/* USBx_UTMIP_PLL_CFG1_0 */ -#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 -#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ - (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) -#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 -#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff - -/* USBx_UTMIP_BIAS_CFG1_0 */ -#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 -#define UTMIP_BIAS_PDTRK_COUNT_MASK \ - (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) - -#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 -#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff - -/* USBx_UTMIP_TX_CFG0_0 */ -#define UTMIP_FS_PREAMBLE_J (1 << 19) - -/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ -#define UTMIP_PD_CHRG 1 - -/* USBx_UTMIP_XCVR_CFG0_0 */ -#define UTMIP_XCVR_LSBIAS_SE (1 << 21) - -/* USBx_UTMIP_SPARE_CFG0_0 */ -#define FUSE_SETUP_SEL (1 << 3) - -/* USBx_UTMIP_HSRX_CFG0_0 */ -#define UTMIP_IDLE_WAIT_SHIFT 15 -#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) -#define UTMIP_ELASTIC_LIMIT_SHIFT 10 -#define UTMIP_ELASTIC_LIMIT_MASK \ - (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) - -/* USBx_UTMIP_HSRX_CFG0_1 */ -#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 -#define UTMIP_HS_SYNC_START_DLY_MASK \ - (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT) - -/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ -#define IC_ENB1 (1 << 3) - -/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ -#define PTS_SHIFT 30 -#define PTS_MASK (3U << PTS_SHIFT) -#define PTS_UTMI 0 -#define PTS_RESERVED 1 -#define PTS_ULPI 2 -#define PTS_ICUSB_SER 3 - -#define STS (1 << 29) -#define WKOC (1 << 22) -#define WKDS (1 << 21) -#define WKCN (1 << 20) - -/* USBx_UTMIP_XCVR_CFG0_0 */ -#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) -#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) -#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) - -/* USBx_UTMIP_XCVR_CFG1_0 */ -#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) -#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) - -/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ -#define VBUS_VLD_STS (1 << 26) - - -/* Setup USB on the board */ -int board_usb_init(const void *blob); - -/** - * Start up the given port number (ports are numbered from 0 on each board). - * This returns values for the appropriate hccr and hcor addresses to use for - * USB EHCI operations. - * - * @param portnum port number to start - * @param hccr returns start address of EHCI HCCR registers - * @param hcor returns start address of EHCI HCOR registers - * @return 0 if ok, -1 on error (generally invalid port number) - */ -int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor); - -/** - * Stop the current port - * - * @return 0 if ok, -1 if no port was active - */ -int tegrausb_stop_port(int portnum); - -#endif /* _TEGRA_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h index decf564..c02c5d8 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ b/arch/arm/include/asm/arch-tegra30/tegra.h @@ -21,6 +21,8 @@ #include +#define TEGRA_USB1_BASE 0x7D000000 + #define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ #define MAX_NUM_CPU 4 diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index d1d8a29..665fa1c 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -46,7 +46,7 @@ #include #endif #ifdef CONFIG_USB_EHCI_TEGRA -#include +#include #endif #include #include diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index a1c43f8..b77806f 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -1,5 +1,7 @@ /* + * Copyright (c) 2011 The Chromium OS Authors. * Copyright (c) 2009-2012 NVIDIA Corporation + * Copyright (c) 2013 Lucas Stach * * See file CREDITS for list of people who contributed to this * project. @@ -21,12 +23,128 @@ */ #include +#include +#include +#include +#include +#include #include +#include +#include +#include #include "ehci.h" -#include -#include +#ifdef CONFIG_USB_ULPI + #ifndef CONFIG_USB_ULPI_VIEWPORT + #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ + define CONFIG_USB_ULPI_VIEWPORT" + #endif +#endif + +enum { + USB_PORTS_MAX = 3, /* Maximum ports we allow */ +}; + +/* Parameters we need for USB */ +enum { + PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ + PARAM_DIVM, /* PLL INPUT DIVIDER */ + PARAM_DIVP, /* POST DIVIDER (2^N) */ + PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ + PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ + PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ + PARAM_STABLE_COUNT, /* PLL-U STABLE count */ + PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ + PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ + PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ + PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ + + PARAM_COUNT +}; + +/* Possible port types (dual role mode) */ +enum dr_mode { + DR_MODE_NONE = 0, + DR_MODE_HOST, /* supports host operation */ + DR_MODE_DEVICE, /* supports device operation */ + DR_MODE_OTG, /* supports both */ +}; + +/* Information about a USB port */ +struct fdt_usb { + struct usb_ctlr *reg; /* address of registers in physical memory */ + unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ + unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ + unsigned enabled:1; /* 1 to enable, 0 to disable */ + unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ + unsigned initialized:1; /* has this port already been initialized? */ + enum dr_mode dr_mode; /* dual role mode */ + enum periph_id periph_id;/* peripheral id */ + struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ + struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */ +}; + +static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ +static unsigned port_count; /* Number of available ports */ + +/* + * This table has USB timing parameters for each Oscillator frequency we + * support. There are four sets of values: + * + * 1. PLLU configuration information (reference clock is osc/clk_m and + * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). + * + * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz + * ---------------------------------------------------------------------- + * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) + * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) + * Filter frequency (MHz) 1 4.8 6 2 + * CPCON 1100b 0011b 1100b 1100b + * LFCON0 0 0 0 0 + * + * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: + * + * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz + * --------------------------------------------------------------------------- + * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) + * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) + * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) + * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) + * + * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and + * SessEnd. Each of these signals have their own debouncer and for each of + * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or + * BIAS_DEBOUNCE_B). + * + * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: + * 0xffff -> No debouncing at all + * ms = *1000 / (1/19.2MHz) / 4 + * + * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: + * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 + * + * We need to use only DebounceA for BOOTROM. We don't need the DebounceB + * values, so we can keep those to default. + * + * 4. The 20 microsecond delay after bias cell operation. + */ +static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { + /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ + { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, + { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, + { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, + { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } +}; + +/* UTMIP Idle Wait Delay */ +static const u8 utmip_idle_wait_delay = 17; + +/* UTMIP Elastic limit */ +static const u8 utmip_elastic_limit = 16; + +/* UTMIP High Speed Sync Start Delay */ +static const u8 utmip_hs_sync_start_delay = 9; /* * A known hardware issue where Connect Status Change bit of PORTSC register @@ -45,6 +163,419 @@ void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) *reg |= EHCI_PS_CSC; } +/* Put the port into host mode */ +static void set_host_mode(struct fdt_usb *config) +{ + /* + * If we are an OTG port, check if remote host is driving VBus and + * bail out in this case. + */ + if (config->dr_mode == DR_MODE_OTG && + (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) + return; + + /* + * If not driving, we set the GPIO to enable VBUS. We assume + * that the pinmux is set up correctly for this. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + fdtdec_setup_gpio(&config->vbus_gpio); + gpio_direction_output(config->vbus_gpio.gpio, + (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? + 0 : 1); + debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, + (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? + "low" : "high"); + } +} + +void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) +{ + /* Reset the USB controller with 2us delay */ + reset_periph(config->periph_id, 2); + + /* + * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under + * base address + */ + if (config->has_legacy_mode) + setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); + + /* Put UTMIP1/3 in reset */ + setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); + + /* Enable the UTMIP PHY */ + if (config->utmi) + setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); +} + +/* set up the UTMI USB controller with the parameters provided */ +static int init_utmi_usb_controller(struct fdt_usb *config) +{ + u32 val; + int loop_count; + const unsigned *timing; + struct usb_ctlr *usbctlr = config->reg; + + clock_enable(config->periph_id); + + /* Reset the usb controller */ + usbf_reset_controller(config, usbctlr); + + /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ + clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); + + /* Follow the crystal clock disable by >100ns delay */ + udelay(1); + + /* + * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP + * mux must be switched to actually use a_sess_vld threshold. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, + VBUS_SENSE_CTL_MASK, + VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); + } + + /* + * PLL Delay CONFIGURATION settings. The following parameters control + * the bring up of the plls. + */ + timing = usb_pll[clock_get_osc_freq()]; + + val = readl(&usbctlr->utmip_misc_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, + timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, + timing[PARAM_ACTIVE_DELAY_COUNT] << + UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); + writel(val, &usbctlr->utmip_misc_cfg1); + + /* Set PLL enable delay count and crystal frequency count */ + val = readl(&usbctlr->utmip_pll_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, + timing[PARAM_ENABLE_DELAY_COUNT] << + UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, + timing[PARAM_XTAL_FREQ_COUNT] << + UTMIP_XTAL_FREQ_COUNT_SHIFT); + writel(val, &usbctlr->utmip_pll_cfg1); + + /* Setting the tracking length time */ + clrsetbits_le32(&usbctlr->utmip_bias_cfg1, + UTMIP_BIAS_PDTRK_COUNT_MASK, + timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); + + /* Program debounce time for VBUS to become valid */ + clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, + UTMIP_DEBOUNCE_CFG0_MASK, + timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); + + setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); + + /* Disable battery charge enabling bit */ + setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); + + clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); + setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); + + /* + * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT + * Setting these fields, together with default values of the + * other fields, results in programming the registers below as + * follows: + * UTMIP_HSRX_CFG0 = 0x9168c000 + * UTMIP_HSRX_CFG1 = 0x13 + */ + + /* Set PLL enable delay count and Crystal frequency count */ + val = readl(&usbctlr->utmip_hsrx_cfg0); + clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, + utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); + clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, + utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); + writel(val, &usbctlr->utmip_hsrx_cfg0); + + /* Configure the UTMIP_HS_SYNC_START_DLY */ + clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, + UTMIP_HS_SYNC_START_DLY_MASK, + utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); + + /* Preceed the crystal clock disable by >100ns delay. */ + udelay(1); + + /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ + setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); + + /* Finished the per-controller init. */ + + /* De-assert UTMIP_RESET to bring out of reset. */ + clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); + + /* Wait for the phy clock to become valid in 100 ms */ + for (loop_count = 100000; loop_count != 0; loop_count--) { + if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) + break; + udelay(1); + } + if (!loop_count) + return -1; + + /* Disable ICUSB FS/LS transceiver */ + clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); + + /* Select UTMI parallel interface */ + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, + PTS_UTMI << PTS_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS); + + /* Deassert power down state */ + clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | + UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); + clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | + UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); + + return 0; +} + +#ifdef CONFIG_USB_ULPI +/* if board file does not set a ULPI reference frequency we default to 24MHz */ +#ifndef CONFIG_ULPI_REF_CLK +#define CONFIG_ULPI_REF_CLK 24000000 +#endif + +/* set up the ULPI USB controller with the parameters provided */ +static int init_ulpi_usb_controller(struct fdt_usb *config) +{ + u32 val; + int loop_count; + struct ulpi_viewport ulpi_vp; + struct usb_ctlr *usbctlr = config->reg; + + /* set up ULPI reference clock on pllp_out4 */ + clock_enable(PERIPH_ID_DEV2_OUT); + clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); + + /* reset ULPI phy */ + if (fdt_gpio_isvalid(&config->phy_reset_gpio)) { + fdtdec_setup_gpio(&config->phy_reset_gpio); + gpio_direction_output(config->phy_reset_gpio.gpio, 0); + mdelay(5); + gpio_set_value(config->phy_reset_gpio.gpio, 1); + } + + /* Reset the usb controller */ + clock_enable(config->periph_id); + usbf_reset_controller(config, usbctlr); + + /* enable pinmux bypass */ + setbits_le32(&usbctlr->ulpi_timing_ctrl_0, + ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); + + /* Select ULPI parallel interface */ + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT); + + /* enable ULPI transceiver */ + setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); + + /* configure ULPI transceiver timings */ + val = 0; + writel(val, &usbctlr->ulpi_timing_ctrl_1); + + val |= ULPI_DATA_TRIMMER_SEL(4); + val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); + val |= ULPI_DIR_TRIMMER_SEL(4); + writel(val, &usbctlr->ulpi_timing_ctrl_1); + udelay(10); + + val |= ULPI_DATA_TRIMMER_LOAD; + val |= ULPI_STPDIRNXT_TRIMMER_LOAD; + val |= ULPI_DIR_TRIMMER_LOAD; + writel(val, &usbctlr->ulpi_timing_ctrl_1); + + /* set up phy for host operation with external vbus supply */ + ulpi_vp.port_num = 0; + ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; + + if (ulpi_init(&ulpi_vp)) { + printf("Tegra ULPI viewport init failed\n"); + return -1; + } + + ulpi_set_vbus(&ulpi_vp, 1, 1); + ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); + + /* enable wakeup events */ + setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); + + /* Enable and wait for the phy clock to become valid in 100 ms */ + setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); + for (loop_count = 100000; loop_count != 0; loop_count--) { + if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) + break; + udelay(1); + } + if (!loop_count) + return -1; + clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); + + return 0; +} +#else +static int init_ulpi_usb_controller(struct fdt_usb *config) +{ + printf("No code to set up ULPI controller, please enable" + "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); + return -1; +} +#endif + +static void config_clock(const u32 timing[]) +{ + clock_start_pll(CLOCK_ID_USB, + timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], + timing[PARAM_CPCON], timing[PARAM_LFCON]); +} + +int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor) +{ + struct fdt_usb *config; + struct usb_ctlr *usbctlr; + + if (portnum >= port_count) + return -1; + + config = &port[portnum]; + + /* skip init, if the port is already initialized */ + if (config->initialized) + goto success; + + if (config->utmi && init_utmi_usb_controller(config)) { + printf("tegrausb: Cannot init port %d\n", portnum); + return -1; + } + + if (config->ulpi && init_ulpi_usb_controller(config)) { + printf("tegrausb: Cannot init port %d\n", portnum); + return -1; + } + + set_host_mode(config); + + config->initialized = 1; + +success: + usbctlr = config->reg; + *hccr = (u32)&usbctlr->cap_length; + *hcor = (u32)&usbctlr->usb_cmd; + return 0; +} + +int tegrausb_stop_port(int portnum) +{ + struct usb_ctlr *usbctlr; + + usbctlr = port[portnum].reg; + + /* Stop controller */ + writel(0, &usbctlr->usb_cmd); + udelay(1000); + + /* Initiate controller reset */ + writel(2, &usbctlr->usb_cmd); + udelay(1000); + + port[portnum].initialized = 0; + + return 0; +} + +int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) +{ + const char *phy, *mode; + + config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode) { + if (0 == strcmp(mode, "host")) + config->dr_mode = DR_MODE_HOST; + else if (0 == strcmp(mode, "peripheral")) + config->dr_mode = DR_MODE_DEVICE; + else if (0 == strcmp(mode, "otg")) + config->dr_mode = DR_MODE_OTG; + else { + debug("%s: Cannot decode dr_mode '%s'\n", __func__, + mode); + return -FDT_ERR_NOTFOUND; + } + } else { + config->dr_mode = DR_MODE_HOST; + } + + phy = fdt_getprop(blob, node, "phy_type", NULL); + config->utmi = phy && 0 == strcmp("utmi", phy); + config->ulpi = phy && 0 == strcmp("ulpi", phy); + config->enabled = fdtdec_get_is_enabled(blob, node); + config->has_legacy_mode = fdtdec_get_bool(blob, node, + "nvidia,has-legacy-mode"); + config->periph_id = clock_decode_periph_id(blob, node); + if (config->periph_id == PERIPH_ID_NONE) { + debug("%s: Missing/invalid peripheral ID\n", __func__); + return -FDT_ERR_NOTFOUND; + } + fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); + fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio", + &config->phy_reset_gpio); + debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " + "vbus=%d, phy_reset=%d, dr_mode=%d\n", + config->enabled, config->has_legacy_mode, config->utmi, + config->ulpi, config->periph_id, config->vbus_gpio.gpio, + config->phy_reset_gpio.gpio, config->dr_mode); + + return 0; +} + +int board_usb_init(const void *blob) +{ + struct fdt_usb config; + enum clock_osc_freq freq; + int node_list[USB_PORTS_MAX]; + int node, count, i; + + /* Set up the USB clocks correctly based on our oscillator frequency */ + freq = clock_get_osc_freq(); + config_clock(usb_pll[freq]); + + /* count may return <0 on error */ + count = fdtdec_find_aliases_for_id(blob, "usb", + COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); + for (i = 0; i < count; i++) { + if (port_count == USB_PORTS_MAX) { + printf("tegrausb: Cannot register more than %d ports\n", + USB_PORTS_MAX); + return -1; + } + + debug("USB %d: ", i); + node = node_list[i]; + if (!node) + continue; + if (fdt_decode_usb(blob, node, &config)) { + debug("Cannot decode USB node %s\n", + fdt_get_name(blob, node, NULL)); + return -1; + } + config.initialized = 0; + + /* add new USB port to the list of available ports */ + port[port_count++] = config; + } + + return 0; +} + /* * Create the appropriate control structures to manage * a new EHCI host controller. -- cgit v0.10.2 From d7a55e1a4b702bffae3e8ed43a5be125a30ba8ab Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 7 Feb 2013 07:16:30 +0000 Subject: tegra: usb: move [start|stop]_port into ehci_hcd_[init|stop] The ehci_hcd entry points were just calling into the Tegra USB functions. Now that they are in the same file we can just move over the implementation. Signed-off-by: Lucas Stach Acked-by: Simon Glass Signed-off-by: Tom Warren diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index b18c850..ef6c089 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -246,23 +246,4 @@ struct usb_ctlr { /* Setup USB on the board */ int board_usb_init(const void *blob); -/** - * Start up the given port number (ports are numbered from 0 on each board). - * This returns values for the appropriate hccr and hcor addresses to use for - * USB EHCI operations. - * - * @param portnum port number to start - * @param hccr returns start address of EHCI HCCR registers - * @param hcor returns start address of EHCI HCOR registers - * @return 0 if ok, -1 on error (generally invalid port number) - */ -int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor); - -/** - * Stop the current port - * - * @return 0 if ok, -1 if no port was active - */ -int tegrausb_stop_port(int portnum); - #endif /* _TEGRA_USB_H_ */ diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index b77806f..554145a 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -438,60 +438,6 @@ static void config_clock(const u32 timing[]) timing[PARAM_CPCON], timing[PARAM_LFCON]); } -int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor) -{ - struct fdt_usb *config; - struct usb_ctlr *usbctlr; - - if (portnum >= port_count) - return -1; - - config = &port[portnum]; - - /* skip init, if the port is already initialized */ - if (config->initialized) - goto success; - - if (config->utmi && init_utmi_usb_controller(config)) { - printf("tegrausb: Cannot init port %d\n", portnum); - return -1; - } - - if (config->ulpi && init_ulpi_usb_controller(config)) { - printf("tegrausb: Cannot init port %d\n", portnum); - return -1; - } - - set_host_mode(config); - - config->initialized = 1; - -success: - usbctlr = config->reg; - *hccr = (u32)&usbctlr->cap_length; - *hcor = (u32)&usbctlr->usb_cmd; - return 0; -} - -int tegrausb_stop_port(int portnum) -{ - struct usb_ctlr *usbctlr; - - usbctlr = port[portnum].reg; - - /* Stop controller */ - writel(0, &usbctlr->usb_cmd); - udelay(1000); - - /* Initiate controller reset */ - writel(2, &usbctlr->usb_cmd); - udelay(1000); - - port[portnum].initialized = 0; - - return 0; -} - int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) { const char *phy, *mode; @@ -576,32 +522,69 @@ int board_usb_init(const void *blob) return 0; } -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. +/** + * Start up the given port number (ports are numbered from 0 on each board). + * This returns values for the appropriate hccr and hcor addresses to use for + * USB EHCI operations. + * + * @param index port number to start + * @param hccr returns start address of EHCI HCCR registers + * @param hcor returns start address of EHCI HCOR registers + * @return 0 if ok, -1 on error (generally invalid port number) */ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - u32 our_hccr, our_hcor; + struct fdt_usb *config; + struct usb_ctlr *usbctlr; - /* - * Select the first port, as we don't have a way of selecting others - * yet - */ - if (tegrausb_start_port(index, &our_hccr, &our_hcor)) + if (index >= port_count) + return -1; + + config = &port[index]; + + /* skip init, if the port is already initialized */ + if (config->initialized) + goto success; + + if (config->utmi && init_utmi_usb_controller(config)) { + printf("tegrausb: Cannot init port %d\n", index); + return -1; + } + + if (config->ulpi && init_ulpi_usb_controller(config)) { + printf("tegrausb: Cannot init port %d\n", index); return -1; + } - *hccr = (struct ehci_hccr *)our_hccr; - *hcor = (struct ehci_hcor *)our_hcor; + set_host_mode(config); + + config->initialized = 1; +success: + usbctlr = config->reg; + *hccr = (struct ehci_hccr *)&usbctlr->cap_length; + *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; return 0; } /* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. + * Bring down the specified USB controller */ int ehci_hcd_stop(int index) { - return tegrausb_stop_port(index); + struct usb_ctlr *usbctlr; + + usbctlr = port[index].reg; + + /* Stop controller */ + writel(0, &usbctlr->usb_cmd); + udelay(1000); + + /* Initiate controller reset */ + writel(2, &usbctlr->usb_cmd); + udelay(1000); + + port[index].initialized = 0; + + return 0; } -- cgit v0.10.2 From 702b87289438cfc3165408f0eaf999b0b67c1e7e Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Wed, 27 Feb 2013 11:10:01 +0000 Subject: Tegra114: I2C: Take DVFS out of reset to allow I2C5 (PWR_I2C) to work I2C driver can now probe dev 0 (PWR_I2C, where the PMU, etc. lives). This is needed so that the SDIO slot power can be brought up for the MMC driver, so it has to precede those commits. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 5962e15..0b2157a 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -201,6 +201,7 @@ void t114_init_clocks(void) reset_set_enable(PERIPH_ID_MSELECT, 0); reset_set_enable(PERIPH_ID_EMC1, 0); reset_set_enable(PERIPH_ID_MC1, 0); + reset_set_enable(PERIPH_ID_DVFS, 0); debug("t114_init_clocks exit\n"); } -- cgit v0.10.2 From e32624ef820f821b94333402788e79979681eb29 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Fri, 8 Feb 2013 07:25:30 +0000 Subject: Tegra: I2C: Add T114 clock support to tegra_i2c driver T114 has a slightly different I2C clock, with a new (extra) divisor in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C clock is 100KHz +/- 3Hz on my Saleae Logic analyzer. Added a new entry in compat_names for T114 I2C since it differs from the previous Tegra SoCs. A flag is set when T114 I2C HW is found so new features like the extra clock divisor can be used. Signed-off-by: Tom Warren Acked-by: Laxman Dewangan diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index 2650744..853e59b 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -105,6 +105,7 @@ struct i2c_ctlr { u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ u32 reserved_2[4]; /* 40: */ struct i2c_control control; /* 50 ~ 68 */ + u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */ }; /* bit fields definitions for IO Packet Header 1 format */ @@ -154,6 +155,11 @@ struct i2c_ctlr { #define I2C_INT_ARBITRATION_LOST_SHIFT 2 #define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) +/* I2C_CLK_DIVISOR_REGISTER */ +#define CLK_DIV_STD_FAST_MODE 0x19 +#define CLK_DIV_HS_MODE 1 +#define CLK_MULT_STD_FAST_MODE 8 + /** * Returns the bus number of the DVC controller * diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index efc77fa..ca71cd3 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -46,6 +46,7 @@ struct i2c_bus { struct i2c_control *control; struct i2c_ctlr *regs; int is_dvc; /* DVC type, rather than I2C */ + int is_scs; /* single clock source (T114+) */ int inited; /* bus is inited */ }; @@ -88,7 +89,28 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) * 16 to get the right frequency. */ clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, - i2c_bus->speed * 2 * 8); + i2c_bus->speed * 2 * 8); + + if (i2c_bus->is_scs) { + /* + * T114 I2C went to a single clock source for standard/fast and + * HS clock speeds. The new clock rate setting calculation is: + * SCL = CLK_SOURCE.I2C / + * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) * + * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1). + * + * NOTE: We do this here, after the initial clock/pll start, + * because if we read the clk_div reg before the controller + * is running, we hang, and we need it for the new calc. + */ + int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; + debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, + clk_div_stdfst_mode); + + clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, + CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) * + i2c_bus->speed * 2); + } /* Reset I2C controller. */ i2c_reset_controller(i2c_bus); @@ -352,10 +374,11 @@ static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus) * @param node_list list of nodes to process (any <=0 are ignored) * @param count number of nodes to process * @param is_dvc 1 if these are DVC ports, 0 if standard I2C + * @param is_scs 1 if this HW uses a single clock source (T114+) * @return 0 if ok, -1 on error */ static int process_nodes(const void *blob, int node_list[], int count, - int is_dvc) + int is_dvc, int is_scs) { struct i2c_bus *i2c_bus; int i; @@ -375,6 +398,8 @@ static int process_nodes(const void *blob, int node_list[], int count, return -1; } + i2c_bus->is_scs = is_scs; + i2c_bus->is_dvc = is_dvc; if (is_dvc) { i2c_bus->control = @@ -403,18 +428,25 @@ void i2c_init_board(void) const void *blob = gd->fdt_blob; int count; - /* First get the normal i2c ports */ + /* First check for newer (T114+) I2C ports */ + count = fdtdec_find_aliases_for_id(blob, "i2c", + COMPAT_NVIDIA_TEGRA114_I2C, node_list, + TEGRA_I2C_NUM_CONTROLLERS); + if (process_nodes(blob, node_list, count, 0, 1)) + return; + + /* Now get the older (T20/T30) normal I2C ports */ count = fdtdec_find_aliases_for_id(blob, "i2c", COMPAT_NVIDIA_TEGRA20_I2C, node_list, TEGRA_I2C_NUM_CONTROLLERS); - if (process_nodes(blob, node_list, count, 0)) + if (process_nodes(blob, node_list, count, 0, 0)) return; /* Now look for dvc ports */ count = fdtdec_add_aliases_for_id(blob, "i2c", COMPAT_NVIDIA_TEGRA20_DVC, node_list, TEGRA_I2C_NUM_CONTROLLERS); - if (process_nodes(blob, node_list, count, 1)) + if (process_nodes(blob, node_list, count, 1, 0)) return; } diff --git a/include/fdtdec.h b/include/fdtdec.h index 77f244f..c7a92d5 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -62,6 +62,7 @@ struct fdt_memory { enum fdt_compat_id { COMPAT_UNKNOWN, COMPAT_NVIDIA_TEGRA20_USB, /* Tegra20 USB port */ + COMPAT_NVIDIA_TEGRA114_I2C, /* Tegra114 I2C w/single clock source */ COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra20 i2c */ COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra20 dvc (really just i2c) */ COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 3ae348d..7c7fc83 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -37,6 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; static const char * const compat_names[COMPAT_COUNT] = { COMPAT(UNKNOWN, ""), COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"), + COMPAT(NVIDIA_TEGRA114_I2C, "nvidia,tegra114-i2c"), COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"), COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"), COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"), -- cgit v0.10.2 From b77c3547e867f7876b3f970125c45d556588d9cb Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Fri, 8 Feb 2013 07:25:31 +0000 Subject: Tegra114: fdt: Update DT files with I2C info for T114/Dalmore T114, like T30, does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but I2C5 is used to designate the controller intended for power control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz. Signed-off-by: Tom Warren Acked-by: Laxman Dewangan Reviewed-by: Stephen Warren diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index d06cd12..0655b4d 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -2,4 +2,68 @@ / { compatible = "nvidia,tegra114"; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + }; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra114-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + i2c@7000c000 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 12>; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c400 0x100>; + interrupts = <0 84 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 54>; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c500 0x100>; + interrupts = <0 92 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 67>; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c700 0x100>; + interrupts = <0 120 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 103>; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000d000 0x100>; + interrupts = <0 53 0x04>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 47>; + status = "disabled"; + }; }; diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts index 7315577..ed3c2fd 100644 --- a/board/nvidia/dts/tegra114-dalmore.dts +++ b/board/nvidia/dts/tegra114-dalmore.dts @@ -10,4 +10,29 @@ device_type = "memory"; reg = <0x80000000 0x80000000>; }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; }; -- cgit v0.10.2 From a7f8b5e616e49a2bb819eeb96b5438039307e7b6 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Fri, 8 Feb 2013 07:25:32 +0000 Subject: Tegra114: I2C: Enable I2C driver on Dalmore E1611 eval board Tested all 5 'buses', i2c probe enumerates device addresses on bus 0, 1 and 2. Signed-off-by: Tom Warren Acked-by: Laxman Dewangan diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index ce32c80..b1a6e34 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -41,6 +41,15 @@ #define CONFIG_MACH_TYPE MACH_TYPE_DALMORE #define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_TEGRA_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + #define CONFIG_ENV_IS_NOWHERE #define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 0033530..c2986d8 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -76,4 +76,7 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra114/u-boot-spl.lds" +/* Total I2C ports on Tegra114 */ +#define TEGRA_I2C_NUM_CONTROLLERS 5 + #endif /* _TEGRA114_COMMON_H_ */ -- cgit v0.10.2 From 6c5be646b47e0dfea3df5a08948f50d1c5d37f68 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 21 Feb 2013 12:31:27 +0000 Subject: Tegra: fdt: Change /include/ to #include for C preprocessor dts Makefile has the arch & board include paths added to DTS_CPPFLAGS. This allows the use of '#include "xyz"' in the dts/dtsi file which helps the C preprocessor find common dtsi include files. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 0655b4d..f0f82de 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -1,4 +1,4 @@ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "nvidia,tegra114"; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 9a89685..d163ff8 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -1,4 +1,4 @@ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "nvidia,tegra20"; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 7b8126f..561c617 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -1,4 +1,4 @@ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "nvidia,tegra30"; diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts index e46afbe..4afe5c2 100644 --- a/board/avionic-design/dts/tegra20-medcom-wide.dts +++ b/board/avionic-design/dts/tegra20-medcom-wide.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "Avionic Design Medcom-Wide"; diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts index 3e6cce0..ef83f29 100644 --- a/board/avionic-design/dts/tegra20-plutux.dts +++ b/board/avionic-design/dts/tegra20-plutux.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "Avionic Design Plutux"; diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index bf3ff1d..cf2fadc 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "Avionic Design Tamonten Evaluation Carrier"; diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts index 31b064d..e521c80 100644 --- a/board/compal/dts/tegra20-paz00.dts +++ b/board/compal/dts/tegra20-paz00.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "Toshiba AC100 / Dynabook AZ"; diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts index 7aeed67..eefd199 100644 --- a/board/compulab/dts/tegra20-trimslice.dts +++ b/board/compulab/dts/tegra20-trimslice.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "Compulab TrimSlice board"; diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts index ed3c2fd..27a4a07 100644 --- a/board/nvidia/dts/tegra114-dalmore.dts +++ b/board/nvidia/dts/tegra114-dalmore.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { model = "NVIDIA Dalmore"; diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts index aeda3a1..9fc7c0d 100644 --- a/board/nvidia/dts/tegra20-harmony.dts +++ b/board/nvidia/dts/tegra20-harmony.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Harmony evaluation board"; diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts index 527a296..a73db36 100644 --- a/board/nvidia/dts/tegra20-seaboard.dts +++ b/board/nvidia/dts/tegra20-seaboard.dts @@ -1,7 +1,7 @@ /dts-v1/; /memreserve/ 0x1c000000 0x04000000; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "NVIDIA Seaboard"; diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts index 3e5e39d..ffc71b2 100644 --- a/board/nvidia/dts/tegra20-ventana.dts +++ b/board/nvidia/dts/tegra20-ventana.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Ventana evaluation board"; diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts index 4579557..1f09e5e 100644 --- a/board/nvidia/dts/tegra20-whistler.dts +++ b/board/nvidia/dts/tegra20-whistler.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "NVIDIA Tegra20 Whistler evaluation board"; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index f9f80c5..f7ea07a 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -1,7 +1,7 @@ /dts-v1/; /memreserve/ 0x1c000000 0x04000000; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { model = "NVIDIA Cardhu"; diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/board/toradex/dts/tegra20-colibri_t20_iris.dts index c29b43a..53c0cdc 100644 --- a/board/toradex/dts/tegra20-colibri_t20_iris.dts +++ b/board/toradex/dts/tegra20-colibri_t20_iris.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20.dtsi" / { model = "Toradex Colibri T20"; diff --git a/dts/Makefile b/dts/Makefile index 922c78c..6f36153 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -38,7 +38,8 @@ Please define CONFIG_ARCH_DEVICE_TREE)) # We preprocess the device tree file provide a useful define DTS_CPPFLAGS := -x assembler-with-cpp \ -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" \ - -DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\" + -DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\" \ + -I$(SRCTREE)/board/$(VENDOR)/dts -I$(SRCTREE)/arch/$(ARCH)/dts all: $(obj).depend $(LIB) -- cgit v0.10.2 From 90b079c8f989c0e949e2a275e77434aa4e16b8e0 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 21 Feb 2013 12:31:28 +0000 Subject: Tegra: fdt: tamonten: Add common tamonten.dtsi file from linux Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren Acked-by: Thierry Reding Reviewed-by: Stephen Warren diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts index 4afe5c2..2acfbc1 100644 --- a/board/avionic-design/dts/tegra20-medcom-wide.dts +++ b/board/avionic-design/dts/tegra20-medcom-wide.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "tegra20.dtsi" +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Medcom-Wide"; diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts index ef83f29..dba200d 100644 --- a/board/avionic-design/dts/tegra20-plutux.dts +++ b/board/avionic-design/dts/tegra20-plutux.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "tegra20.dtsi" +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Plutux"; diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/board/avionic-design/dts/tegra20-tamonten.dtsi new file mode 100644 index 0000000..86c7bab --- /dev/null +++ b/board/avionic-design/dts/tegra20-tamonten.dtsi @@ -0,0 +1,489 @@ +#include "tegra20.dtsi" + +/ { + model = "Avionic Design Tamonten SOM"; + compatible = "ad,tamonten", "nvidia,tegra20"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + host1x { + hdmi { + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ + }; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", + "spia", "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtd"; + nvidia,function = "sdio2"; + }; + dtb { + nvidia,pins = "dtb", "dtc", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dtb", "gma", + "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "pta", "rm", "slxa", + "slxk", "spia", "spib", "uac"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <0>; + }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; + conf_crtp { + nvidia,pins = "crtp", "dap2", "dap3", "dap4", + "dtc", "dte", "dtf", "gpu", "sdio1", + "slxc", "slxd", "spdi", "spdo", "spig", + "uda"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + conf_ddc { + nvidia,pins = "ddc", "dta", "dtd", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "sdc"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "owc", "sdb"; + nvidia,tristate = <1>; + }; + conf_irrx { + nvidia,pins = "irrx", "irtx", "sdd", "spic", + "spie", "spih", "uaa", "uab", "uad", + "uca", "ucb"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <2>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc"; + nvidia,tristate = <0>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <1>; + }; + }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006300 { + status = "okay"; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + }; + + i2c@7000c400 { + clock-frequency = <100000>; + status = "okay"; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + status = "okay"; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + sm0 { + regulator-name = "vdd_sys_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "vdd_sys_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sys_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + ldo0 { + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + }; + }; + + pmc { + nvidia,invert-interrupt; + }; + + usb@c5008000 { + status = "okay"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 58 1>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + bus-width = <4>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index cf2fadc..04e6730 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "tegra20.dtsi" +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Tamonten Evaluation Carrier"; -- cgit v0.10.2 From 126685ad44ad39895567884458b3a4581acf8902 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 21 Feb 2013 12:31:29 +0000 Subject: Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files Linux dts files were used for those boards that didn't already have sdhci info populated. Tamonten has their own dtsi file with common sdhci nodes (sourced from Linux). Signed-off-by: Tom Warren Tested-by: Thierry Reding Reviewed-by: Stephen Warren diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index d163ff8..3805750 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -318,24 +318,32 @@ sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; - interrupts = < 46 >; + interrupts = <0 14 0x04>; + clocks = <&tegra_car 14>; + status = "disabled"; }; sdhci@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; - interrupts = < 47 >; + interrupts = <0 15 0x04>; + clocks = <&tegra_car 9>; + status = "disabled"; }; sdhci@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; - interrupts = < 51 >; + interrupts = <0 19 0x04>; + clocks = <&tegra_car 69>; + status = "disabled"; }; sdhci@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; - interrupts = < 63 >; + interrupts = <0 31 0x04>; + clocks = <&tegra_car 15>; + status = "disabled"; }; }; diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts index 2acfbc1..a9a07f9 100644 --- a/board/avionic-design/dts/tegra20-medcom-wide.dts +++ b/board/avionic-design/dts/tegra20-medcom-wide.dts @@ -8,6 +8,7 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; }; memory { diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts index dba200d..20016f2 100644 --- a/board/avionic-design/dts/tegra20-plutux.dts +++ b/board/avionic-design/dts/tegra20-plutux.dts @@ -8,6 +8,7 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; }; memory { diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index 04e6730..1d7cf89 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -8,6 +8,7 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; }; memory { diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts index e521c80..780203c 100644 --- a/board/compal/dts/tegra20-paz00.dts +++ b/board/compal/dts/tegra20-paz00.dts @@ -3,11 +3,13 @@ #include "tegra20.dtsi" / { - model = "Toshiba AC100 / Dynabook AZ"; - compatible = "compal,paz00", "nvidia,tegra20"; + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000000"; }; memory { @@ -53,6 +55,19 @@ status = "disabled"; }; + sdhci@c8000000 { + status = "okay"; + cd-gpios = <&gpio 173 1>; /* gpio PV5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 169 0>; /* gpio PV1 */ + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; + lcd_panel: panel { /* PAZ00 has 1024x600 */ clock = <54030000>; diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts index eefd199..ee31476 100644 --- a/board/compulab/dts/tegra20-trimslice.dts +++ b/board/compulab/dts/tegra20-trimslice.dts @@ -9,6 +9,8 @@ aliases { usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000000"; }; memory { @@ -47,4 +49,16 @@ usb@c5004000 { status = "disabled"; }; + + sdhci@c8000000 { + status = "okay"; + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio 121 1>; /* gpio PP1 */ + wp-gpios = <&gpio 122 0>; /* gpio PP2 */ + bus-width = <4>; + }; }; diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts index 27a4a07..3e1e1ea 100644 --- a/board/nvidia/dts/tegra114-dalmore.dts +++ b/board/nvidia/dts/tegra114-dalmore.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include ARCH_CPU_DTS +#include "tegra114.dtsi" / { model = "NVIDIA Dalmore"; diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts index 9fc7c0d..7934e4a 100644 --- a/board/nvidia/dts/tegra20-harmony.dts +++ b/board/nvidia/dts/tegra20-harmony.dts @@ -9,6 +9,8 @@ aliases { usb0 = "/usb@c5008000"; usb1 = "/usb@c5004000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000200"; }; memory { @@ -52,4 +54,20 @@ usb@c5004000 { nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ }; + + sdhci@c8000200 { + status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio 58 1>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + bus-width = <8>; + }; }; diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts index a73db36..12cb0bc 100644 --- a/board/nvidia/dts/tegra20-seaboard.dts +++ b/board/nvidia/dts/tegra20-seaboard.dts @@ -12,14 +12,15 @@ }; aliases { - /* This defines the order of our USB ports */ + /* This defines the order of our ports */ usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; - i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000400"; }; memory { @@ -156,13 +157,16 @@ }; sdhci@c8000400 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ + bus-width = <4>; }; sdhci@c8000600 { - support-8bit; + status = "okay"; + bus-width = <8>; }; lcd_panel: panel { diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts index ffc71b2..e1a3d1e 100644 --- a/board/nvidia/dts/tegra20-ventana.dts +++ b/board/nvidia/dts/tegra20-ventana.dts @@ -8,6 +8,8 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000400"; }; memory { @@ -41,4 +43,17 @@ usb@c5004000 { status = "disabled"; }; + + sdhci@c8000400 { + status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; }; diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts index 1f09e5e..eb92264 100644 --- a/board/nvidia/dts/tegra20-whistler.dts +++ b/board/nvidia/dts/tegra20-whistler.dts @@ -9,6 +9,8 @@ aliases { i2c0 = "/i2c@7000d000"; usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000400"; }; memory { @@ -57,4 +59,15 @@ usb@c5004000 { status = "disabled"; }; + + sdhci@c8000400 { + status = "okay"; + wp-gpios = <&gpio 173 0>; /* gpio PV5 */ + bus-width = <8>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; }; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index f7ea07a..8ad1fb7 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -1,7 +1,7 @@ /dts-v1/; /memreserve/ 0x1c000000 0x04000000; -#include ARCH_CPU_DTS +#include "tegra30.dtsi" / { model = "NVIDIA Cardhu"; diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/board/toradex/dts/tegra20-colibri_t20_iris.dts index 53c0cdc..c0e54af 100644 --- a/board/toradex/dts/tegra20-colibri_t20_iris.dts +++ b/board/toradex/dts/tegra20-colibri_t20_iris.dts @@ -10,6 +10,7 @@ usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; usb2 = "/usb@c5004000"; + sdhci0 = "/sdhci@c8000600"; }; usb@c5000000 { @@ -35,4 +36,10 @@ compatible = "nand-flash"; }; }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio 23 1>; /* gpio PC7 */ + bus-width = <4>; + }; }; -- cgit v0.10.2 From c9aa831ee26f629fbd2df67cab8bb357777e2256 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 21 Feb 2013 12:31:30 +0000 Subject: Tegra: MMC: Add DT support to MMC driver for all T20 boards tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc. Tested on Seaboard, fully functional. Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren Signed-off-by: Thierry Reding Reviewed-by: Stephen Warren diff --git a/arch/arm/include/asm/arch-tegra/mmc.h b/arch/arm/include/asm/arch-tegra/mmc.h index 5c95047..71ad407 100644 --- a/arch/arm/include/asm/arch-tegra/mmc.h +++ b/arch/arm/include/asm/arch-tegra/mmc.h @@ -22,6 +22,6 @@ #ifndef _TEGRA_MMC_H_ #define _TEGRA_MMC_H_ -int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); +void tegra_mmc_init(void); #endif /* _TEGRA_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index dd746ca..bd18f5f 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -27,6 +27,8 @@ #define TEGRA_SDMMC3_BASE 0xC8000400 #define TEGRA_SDMMC4_BASE 0xC8000600 +#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */ + #ifndef __ASSEMBLY__ struct tegra_mmc { unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ @@ -119,12 +121,15 @@ struct tegra_mmc { struct mmc_host { struct tegra_mmc *reg; + int id; /* device id/number, 0-3 */ + int enabled; /* 1 to enable, 0 to disable */ + int width; /* Bus Width, 1, 4 or 8 */ + enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ + struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */ + struct fdt_gpio_state pwr_gpio; /* Power GPIO */ + struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */ unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ - unsigned int base; /* Base address, SDMMC1/2/3/4 */ - enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ - int pwr_gpio; /* Power GPIO */ - int cd_gpio; /* Change Detect GPIO */ }; #endif /* __ASSEMBLY__ */ diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index e6a932e..ea95e43 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -33,13 +33,8 @@ #include #include #include -#include #include #include -#ifdef CONFIG_TEGRA_MMC -#include -#endif - #ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) @@ -54,7 +49,7 @@ void gpio_early_init(void) * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); /* for write-protect GPIO PI6 */ @@ -62,16 +57,4 @@ static void pin_mux_mmc(void) /* for CD GPIO PH2 */ pinmux_tristate_disable(PINGRP_ATD); } - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - /* init dev 0, SD slot, with 4-bit bus */ - tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); - - return 0; -} #endif diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 1447f47..d6e5c37 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -18,19 +18,14 @@ #include #include #include -#include #include -#ifdef CONFIG_TEGRA_MMC -#include -#endif - #ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { /* SDMMC4: config 3, x8 on 2nd set of pins */ pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); @@ -51,25 +46,6 @@ static void pin_mux_mmc(void) /* For CD GPIO PV5 */ pinmux_tristate_disable(PINGRP_GPV); } - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("board_mmc_init called\n"); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - debug("board_mmc_init: init eMMC\n"); - /* init dev 0, eMMC chip, with 8-bit bus */ - tegra_mmc_init(0, 8, -1, -1); - - debug("board_mmc_init: init SD slot\n"); - /* init dev 3, SD slot, with 4-bit bus */ - tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); - - return 0; -} #endif #ifdef CONFIG_LCD diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 8f4dd09..8401100 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -27,12 +27,8 @@ #include #include #include -#include #include #include -#ifdef CONFIG_TEGRA_MMC -#include -#endif void pin_mux_usb(void) { @@ -52,7 +48,7 @@ void pin_mux_spi(void) * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT); funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); @@ -60,20 +56,3 @@ static void pin_mux_mmc(void) /* For CD GPIO PP1 */ pinmux_tristate_disable(PINGRP_DAP3); } - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("board_mmc_init called\n"); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */ - tegra_mmc_init(0, 4, -1, GPIO_PP1); - - /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */ - tegra_mmc_init(3, 4, -1, -1); - - return 0; -} diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 665fa1c..babbe08 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -48,6 +48,9 @@ #ifdef CONFIG_USB_EHCI_TEGRA #include #endif +#ifdef CONFIG_TEGRA_MMC +#include +#endif #include #include #include "emc.h" @@ -221,3 +224,25 @@ int board_late_init(void) #endif return 0; } + +#if defined(CONFIG_TEGRA_MMC) +void __pin_mux_mmc(void) +{ +} + +void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc"))); + +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("%s called\n", __func__); + + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + + debug("%s: init MMC\n", __func__); + tegra_mmc_init(); + + return 0; +} +#endif diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 93430ed..3122441 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -27,19 +27,14 @@ #include #include #include -#include #include -#ifdef CONFIG_TEGRA_MMC -#include -#endif - #ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT); @@ -54,25 +49,6 @@ static void pin_mux_mmc(void) /* For CD GPIO PI5 */ pinmux_tristate_disable(PINGRP_ATC); } - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("board_mmc_init called\n"); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - debug("board_mmc_init: init SD slot J26\n"); - /* init dev 0, SD slot J26, with 8-bit bus */ - tegra_mmc_init(0, 8, GPIO_PI6, GPIO_PH2); - - debug("board_mmc_init: init SD slot J5\n"); - /* init dev 2, SD slot J5, with 4-bit bus */ - tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5); - - return 0; -} #endif void pin_mux_usb(void) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 3e33da0..e581fdd 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -28,11 +28,7 @@ #include #include #include -#include #include -#ifdef CONFIG_TEGRA_MMC -#include -#endif /* TODO: Remove this code when the SPI switch is working */ #if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) @@ -51,7 +47,7 @@ void gpio_early_init_uart(void) * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) +void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT); @@ -61,25 +57,6 @@ static void pin_mux_mmc(void) /* For CD GPIO PI5 */ pinmux_tristate_disable(PINGRP_ATC); } - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("board_mmc_init called\n"); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - debug("board_mmc_init: init eMMC\n"); - /* init dev 0, eMMC chip, with 8-bit bus */ - tegra_mmc_init(0, 8, -1, -1); - - debug("board_mmc_init: init SD slot\n"); - /* init dev 1, SD slot, with 4-bit bus */ - tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5); - - return 0; -} #endif void pin_mux_usb(void) diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 592cd6b..f18aa27 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -27,32 +27,19 @@ #include #include #include -#include #include #include -#ifdef CONFIG_TEGRA_MMC -#include -#endif - +#ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -static void pin_mux_mmc(void) -{ - funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); -} - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) +void pin_mux_mmc(void) { uchar val; int ret; - debug("board_mmc_init called\n"); - /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ ret = i2c_set_bus_num(0); if (ret) @@ -70,17 +57,10 @@ int board_mmc_init(bd_t *bd) if (ret) printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - /* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */ - tegra_mmc_init(0, 8, -1, -1); - - /* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */ - tegra_mmc_init(1, 8, -1, -1); - - return 0; + funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); } +#endif /* this is a weak define that we are overriding */ void pin_mux_usb(void) diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c index e40a986..aa76f65 100644 --- a/board/toradex/colibri_t20_iris/colibri_t20_iris.c +++ b/board/toradex/colibri_t20_iris/colibri_t20_iris.c @@ -19,7 +19,6 @@ #include #include #include -#include #include "../colibri_t20-common/colibri_t20-common.h" @@ -34,13 +33,13 @@ void pin_mux_usb(void) #endif #ifdef CONFIG_TEGRA_MMC -int board_mmc_init(bd_t *bd) +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +void pin_mux_mmc(void) { funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); pinmux_tristate_disable(PINGRP_GMB); - - tegra_mmc_init(0, 4, -1, GPIO_PC7); - - return 0; } #endif diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 7258619..455a690 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -2,7 +2,7 @@ * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang * Jaehoon Chung - * Portions Copyright 2011-2012 NVIDIA Corporation + * Portions Copyright 2011-2013 NVIDIA Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -28,44 +29,14 @@ #include #include -/* support 4 mmc hosts */ -struct mmc mmc_dev[4]; -struct mmc_host mmc_host[4]; +DECLARE_GLOBAL_DATA_PTR; +struct mmc mmc_dev[MAX_HOSTS]; +struct mmc_host mmc_host[MAX_HOSTS]; -/** - * Get the host address and peripheral ID for a device. Devices are numbered - * from 0 to 3. - * - * @param host Structure to fill in (base, reg, mmc_id) - * @param dev_index Device index (0-3) - */ -static void tegra_get_setup(struct mmc_host *host, int dev_index) -{ - debug("tegra_get_setup: dev_index = %d\n", dev_index); - - switch (dev_index) { - case 1: - host->base = TEGRA_SDMMC3_BASE; - host->mmc_id = PERIPH_ID_SDMMC3; - break; - case 2: - host->base = TEGRA_SDMMC2_BASE; - host->mmc_id = PERIPH_ID_SDMMC2; - break; - case 3: - host->base = TEGRA_SDMMC1_BASE; - host->mmc_id = PERIPH_ID_SDMMC1; - break; - case 0: - default: - host->base = TEGRA_SDMMC4_BASE; - host->mmc_id = PERIPH_ID_SDMMC4; - break; - } - - host->reg = (struct tegra_mmc *)host->base; -} +#ifndef CONFIG_OF_CONTROL +#error "Please enable device tree support to use this driver" +#endif static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data, struct bounce_buffer *bbstate) @@ -518,41 +489,43 @@ int tegra_mmc_getcd(struct mmc *mmc) debug("tegra_mmc_getcd called\n"); - if (host->cd_gpio >= 0) - return !gpio_get_value(host->cd_gpio); + if (fdt_gpio_isvalid(&host->cd_gpio)) + return fdtdec_get_gpio(&host->cd_gpio); return 1; } -int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) +static int do_mmc_init(int dev_index) { struct mmc_host *host; char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */ struct mmc *mmc; - debug(" tegra_mmc_init: index %d, bus width %d " - "pwr_gpio %d cd_gpio %d\n", - dev_index, bus_width, pwr_gpio, cd_gpio); - + /* DT should have been read & host config filled in */ host = &mmc_host[dev_index]; + if (!host->enabled) + return -1; - host->clock = 0; - host->pwr_gpio = pwr_gpio; - host->cd_gpio = cd_gpio; - tegra_get_setup(host, dev_index); + debug(" do_mmc_init: index %d, bus width %d " + "pwr_gpio %d cd_gpio %d\n", + dev_index, host->width, + host->pwr_gpio.gpio, host->cd_gpio.gpio); + host->clock = 0; clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); - if (host->pwr_gpio >= 0) { + if (fdt_gpio_isvalid(&host->pwr_gpio)) { sprintf(gpusage, "SD/MMC%d PWR", dev_index); - gpio_request(host->pwr_gpio, gpusage); - gpio_direction_output(host->pwr_gpio, 1); + gpio_request(host->pwr_gpio.gpio, gpusage); + gpio_direction_output(host->pwr_gpio.gpio, 1); + debug(" Power GPIO name = %s\n", host->pwr_gpio.name); } - if (host->cd_gpio >= 0) { + if (fdt_gpio_isvalid(&host->cd_gpio)) { sprintf(gpusage, "SD/MMC%d CD", dev_index); - gpio_request(host->cd_gpio, gpusage); - gpio_direction_input(host->cd_gpio); + gpio_request(host->cd_gpio.gpio, gpusage); + gpio_direction_input(host->cd_gpio.gpio); + debug(" CD GPIO name = %s\n", host->cd_gpio.name); } mmc = &mmc_dev[dev_index]; @@ -567,9 +540,9 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; mmc->host_caps = 0; - if (bus_width == 8) + if (host->width == 8) mmc->host_caps |= MMC_MODE_8BIT; - if (bus_width >= 4) + if (host->width >= 4) mmc->host_caps |= MMC_MODE_4BIT; mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; @@ -578,8 +551,6 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) * low-speed SDIO card frequency (actually 400KHz) * max freq is highest HS eMMC clock as per the SD/MMC spec * (actually 52MHz) - * Both of these are the closest equivalents w/216MHz source - * clock and Tegra SDMMC divisors. */ mmc->f_min = 375000; mmc->f_max = 48000000; @@ -588,3 +559,95 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) return 0; } + +/** + * Get the host address and peripheral ID for a node. + * + * @param blob fdt blob + * @param node Device index (0-3) + * @param host Structure to fill in (reg, width, mmc_id) + */ +static int mmc_get_config(const void *blob, int node, struct mmc_host *host) +{ + debug("%s: node = %d\n", __func__, node); + + host->enabled = fdtdec_get_is_enabled(blob, node); + + host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg"); + if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) { + debug("%s: no sdmmc base reg info found\n", __func__); + return -FDT_ERR_NOTFOUND; + } + + host->mmc_id = clock_decode_periph_id(blob, node); + if (host->mmc_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id\n", __func__); + return -FDT_ERR_NOTFOUND; + } + + /* + * NOTE: mmc->bus_width is determined by mmc.c dynamically. + * TBD: Override it with this value? + */ + host->width = fdtdec_get_int(blob, node, "bus-width", 0); + if (!host->width) + debug("%s: no sdmmc width found\n", __func__); + + /* These GPIOs are optional */ + fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio); + fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio); + fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio); + + debug("%s: found controller at %p, width = %d, periph_id = %d\n", + __func__, host->reg, host->width, host->mmc_id); + return 0; +} + +/* + * Process a list of nodes, adding them to our list of SDMMC ports. + * + * @param blob fdt blob + * @param node_list list of nodes to process (any <=0 are ignored) + * @param count number of nodes to process + * @return 0 if ok, -1 on error + */ +static int process_nodes(const void *blob, int node_list[], int count) +{ + struct mmc_host *host; + int i, node; + + debug("%s: count = %d\n", __func__, count); + + /* build mmc_host[] for each controller */ + for (i = 0; i < count; i++) { + node = node_list[i]; + if (node <= 0) + continue; + + host = &mmc_host[i]; + host->id = i; + + if (mmc_get_config(blob, node, host)) { + printf("%s: failed to decode dev %d\n", __func__, i); + return -1; + } + do_mmc_init(i); + } + return 0; +} + +void tegra_mmc_init(void) +{ + int node_list[MAX_HOSTS], count; + const void *blob = gd->fdt_blob; + debug("%s entry\n", __func__); + + count = fdtdec_find_aliases_for_id(blob, "sdhci", + COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS); + debug("%s: count of sdhci nodes is %d\n", __func__, count); + + if (process_nodes(blob, node_list, count)) { + printf("%s: Error processing mmc node(s)!\n", __func__); + return; + } +} diff --git a/include/fdtdec.h b/include/fdtdec.h index c7a92d5..32730d2 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -71,6 +71,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ + COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */ COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 7c7fc83..000130f 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -46,6 +46,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"), COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), + COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"), COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"), COMPAT(SMSC_LAN9215, "smsc,lan9215"), -- cgit v0.10.2 From 73bb24439441d4a52e031c81f32a460ceab15421 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 21 Feb 2013 12:40:29 +0000 Subject: Tegra: fdt: Remove memreserve line from Cardhu/Seaboard DT files Not used, and wrong in Cardhu's case Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts index 12cb0bc..c0e2e1e 100644 --- a/board/nvidia/dts/tegra20-seaboard.dts +++ b/board/nvidia/dts/tegra20-seaboard.dts @@ -1,6 +1,5 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; #include "tegra20.dtsi" / { diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index 8ad1fb7..778e513 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -1,6 +1,5 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; #include "tegra30.dtsi" / { -- cgit v0.10.2 From 527519ae69cdde6386754015f986f99604f2c9a7 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 21 Feb 2013 13:33:23 +0000 Subject: Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock) Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 561c617..9483e80 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -3,8 +3,8 @@ / { compatible = "nvidia,tegra30"; - tegra_car: clock@60006000 { - compatible = "nvidia,tegra30-car", "nvidia,tegra20-car"; + tegra_car: clock { + compatible = "nvidia,tegra30-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; }; @@ -44,51 +44,79 @@ 0 141 0x04 0 142 0x04 0 143 0x04>; + clocks = <&tegra_car 34>; + }; + + gpio: gpio { + compatible = "nvidia,tegra30-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = <0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 + 0 125 0x04>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; }; i2c@7000c000 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C000 0x100>; - /* PERIPH_ID_I2C1, CLK_M */ - clocks = <&tegra_car 12>; + clocks = <&tegra_car 12>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; }; i2c@7000c400 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c400 0x100>; + interrupts = <0 84 0x04>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C400 0x100>; - /* PERIPH_ID_I2C2, CLK_M */ - clocks = <&tegra_car 54>; + clocks = <&tegra_car 54>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; }; i2c@7000c500 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c500 0x100>; + interrupts = <0 92 0x04>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C500 0x100>; - /* PERIPH_ID_I2C3, CLK_M */ - clocks = <&tegra_car 67>; + clocks = <&tegra_car 67>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; }; i2c@7000c700 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c700 0x100>; + interrupts = <0 120 0x04>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000C700 0x100>; - /* PERIPH_ID_I2C4, CLK_M */ - clocks = <&tegra_car 103>; + clocks = <&tegra_car 103>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; }; i2c@7000d000 { + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000d000 0x100>; + interrupts = <0 53 0x04>; #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; - reg = <0x7000D000 0x100>; - /* PERIPH_ID_I2C_DVC, CLK_M */ - clocks = <&tegra_car 47>; + clocks = <&tegra_car 47>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; + status = "disabled"; }; spi@7000d400 { @@ -98,9 +126,8 @@ nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC1, PLLP_OUT0 */ clocks = <&tegra_car 41>; + status = "disabled"; }; spi@7000d600 { @@ -110,9 +137,8 @@ nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC2, PLLP_OUT0 */ clocks = <&tegra_car 44>; + status = "disabled"; }; spi@7000d800 { @@ -122,9 +148,8 @@ nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC3, PLLP_OUT0 */ clocks = <&tegra_car 46>; + status = "disabled"; }; spi@7000da00 { @@ -134,9 +159,8 @@ nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC4, PLLP_OUT0 */ clocks = <&tegra_car 68>; + status = "disabled"; }; spi@7000dc00 { @@ -146,9 +170,8 @@ nvidia,dma-request-selector = <&apbdma 27>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC5, PLLP_OUT0 */ clocks = <&tegra_car 104>; + status = "disabled"; }; spi@7000de00 { @@ -158,8 +181,7 @@ nvidia,dma-request-selector = <&apbdma 28>; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; - /* PERIPH_ID_SBC6, PLLP_OUT0 */ clocks = <&tegra_car 105>; + status = "disabled"; }; }; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index 778e513..48039c9 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -20,22 +20,27 @@ }; i2c@7000c000 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c400 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c500 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000c700 { + status = "okay"; clock-frequency = <100000>; }; i2c@7000d000 { + status = "okay"; clock-frequency = <100000>; }; -- cgit v0.10.2 From 16bb08d19a5ecb9c3e90ab2394d7c5c40955ee60 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 28 Feb 2013 12:40:09 +0000 Subject: ARM: tegra: implement WAR for Tegra114 CPU reset vector A Tegra114 HW bug prevents the main CPU vector from being modified under certain circumstances. Tegra114 A01P and later with a patched boot ROM set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing an arbitrary jump instruction at that location, in order to redirect to the desired reset vector location. Modify Tegra114's start_cpu() to make use of this feature. This allows CPUs with the patched boot ROM to boot. Based-on-work-by: Jimmy Zhang . Signed-off-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 0b2157a..6a94179 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -270,6 +270,8 @@ void powerup_cpus(void) void start_cpu(u32 reset_vector) { + u32 imme, inst; + debug("start_cpu entry, reset_vector = %x\n", reset_vector); t114_init_clocks(); @@ -286,12 +288,38 @@ void start_cpu(u32 reset_vector) /* Take CPU(s) out of reset */ remove_cpu_resets(); + /* Set the entry point for CPU execution from reset */ + /* - * Set the entry point for CPU execution from reset, - * if it's a non-zero value. + * A01P with patched boot ROM; vector hard-coded to 0x4003fffc. + * See nvbug 1193357 for details. */ - if (reset_vector) - writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); + + /* mov r0, #lsb(reset_vector) */ + imme = reset_vector & 0xffff; + inst = imme & 0xfff; + inst |= ((imme >> 12) << 16); + inst |= 0xe3000000; + writel(inst, 0x4003fff0); + + /* movt r0, #msb(reset_vector) */ + imme = (reset_vector >> 16) & 0xffff; + inst = imme & 0xfff; + inst |= ((imme >> 12) << 16); + inst |= 0xe3400000; + writel(inst, 0x4003fff4); + + /* bx r0 */ + writel(0xe12fff10, 0x4003fff8); + + /* b -12 */ + imme = (u32)-20; + inst = (imme >> 2) & 0xffffff; + inst |= 0xea000000; + writel(inst, 0x4003fffc); + + /* Write to orignal location for compatibility */ + writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); /* If the CPU(s) don't already have power, power 'em up */ powerup_cpus(); -- cgit v0.10.2 From 7ea9c506d9390c03c61b21b222a18ede44b16f0a Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 26 Feb 2013 07:59:30 +0000 Subject: Tegra: Add twarren as maintainer for Tegra30 and Tegra114 SoCs Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/MAINTAINERS b/MAINTAINERS index e792a8b..059b487 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -976,6 +976,8 @@ Tom Warren harmony Tegra20 (ARM7 & A9 Dual Core) seaboard Tegra20 (ARM7 & A9 Dual Core) + cardhu Tegra30 (ARM7 & A9 Quad Core) + dalmore Tegra114 (ARM7 & A15 Quad Core) Tom Warren Stephen Warren -- cgit v0.10.2 From bfcf46db6340f202ecfd200252f9e3295a392696 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 26 Feb 2013 12:18:48 +0000 Subject: Tegra: Remove unused CONFIG_SYS_CPU_OSC_FREQUENCY define This wasn't used anywhere in any Tegra build. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 4a656bb..80c846c 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef __TEGRA_COMMON_H -#define __TEGRA_COMMON_H +#ifndef _TEGRA_COMMON_H_ +#define _TEGRA_COMMON_H_ #include #include @@ -56,10 +56,8 @@ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ /* - * PllX Configuration + * NS16550 Configuration */ -#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */ - #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -- cgit v0.10.2 From 19a970af28b7835ebabd61f1e09d623690b6feef Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Wed, 27 Feb 2013 05:52:52 +0000 Subject: Tegra114: fdt: Sync DT nodes with kernel DT files (GPIO, tegra_car) Minor edit to tegra_car node, add gpio node. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index f0f82de..dfeac53 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -11,12 +11,29 @@ i2c4 = "/i2c@7000c700"; }; - tegra_car: clock@60006000 { + tegra_car: clock { compatible = "nvidia,tegra114-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; }; + gpio: gpio { + compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = <0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 + 0 125 0x04>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + i2c@7000c000 { compatible = "nvidia,tegra114-i2c"; reg = <0x7000c000 0x100>; -- cgit v0.10.2 From bb638bb756b91a781d056d3b89cbd6dd562eabca Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Thu, 28 Feb 2013 06:30:03 +0000 Subject: Tegra30: Cardhu: Remove unneeded cardhu.c.mmc file This was an older debug/developmental file that got added accidentally. Not needed/used in any Cardhu build. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/board/nvidia/cardhu/cardhu.c.mmc b/board/nvidia/cardhu/cardhu.c.mmc deleted file mode 100644 index 9e83b6f..0000000 --- a/board/nvidia/cardhu/cardhu.c.mmc +++ /dev/null @@ -1,151 +0,0 @@ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "pinmux-config-cardhu.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_config_table(tegra3_pinmux_common, - ARRAY_SIZE(tegra3_pinmux_common)); - - pinmux_config_table(unused_pins_lowpower, - ARRAY_SIZE(unused_pins_lowpower)); -} - -#if defined(CONFIG_MMC) -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -static void pin_mux_mmc(void) -{ -} - -/* Do I2C/PMU writes to bring up SD card bus power */ -static void board_sdmmc_voltage_init(void) -{ - uchar reg, data_buffer[1]; - int i; - - i2c_set_bus_num(0); /* PMU is on bus 0 */ - - data_buffer[0] = 0x65; - reg = 0x32; - - for (i = 0; i < MAX_I2C_RETRY; ++i) { - if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) - udelay(100); - } - - data_buffer[0] = 0x09; - reg = 0x67; - - for (i = 0; i < MAX_I2C_RETRY; ++i) { - if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) - udelay(100); - } -} - -static void pad_init_mmc(struct tegra_mmc *reg) -{ - struct apb_misc_gp_ctlr *const gpc = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - struct sdmmc_ctlr *const sdmmc = (struct sdmmc_ctlr *)reg; - u32 val, offset = (unsigned int)reg; - u32 padcfg, padmask; - - debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)sdmmc); - - /* Set the pad drive strength for SDMMC1 or 3 only */ - if (offset != TEGRA_SDMMC1_BASE && offset != TEGRA_SDMMC3_BASE) { - debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", - __func__); - return; - } - - /* Set pads as per T30 TRM, section 24.6.1.2 */ - padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \ - GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN); - padmask = 0x00000FFF; - if (offset == TEGRA_SDMMC1_BASE) { - val = readl(&gpc->sdio1cfg); - val &= padmask; - val |= padcfg; - writel(val, &gpc->sdio1cfg); - } else { /* SDMMC3 */ - val = readl(&gpc->sdio3cfg); - val &= padmask; - val |= padcfg; - writel(val, &gpc->sdio3cfg); - } - - val = readl(&sdmmc->sdmmc_sdmemcomp_pad_ctrl); - val &= 0xFFFFFFF0; - val |= MEMCOMP_PADCTRL_VREF; - writel(val, &sdmmc->sdmmc_sdmemcomp_pad_ctrl); - - val = readl(&sdmmc->sdmmc_auto_cal_config); - val &= 0xFFFF0000; - val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; - writel(val, &sdmmc->sdmmc_auto_cal_config); -} - -/* this is a weak define that we are overriding */ -int board_mmc_init(bd_t *bd) -{ - debug("board_mmc_init called\n"); - - /* Turn on SD-card bus power */ - board_sdmmc_voltage_init(); - - /* Set up the SDMMC pads as per the TRM */ - pad_init_mmc((struct tegra_mmc *)TEGRA_SDMMC1_BASE); - - /* Enable muxes, etc. for SDMMC controllers */ - pin_mux_mmc(); - - /* init dev 0 (SDMMC4), ("HSMMC") with 8-bit bus */ - tegra_mmc_init(0, 8, -1, -1); - - /* init dev 1 (SDMMC0), ("SDIO") with 8-bit bus */ - tegra_mmc_init(1, 8, -1, -1); - - return 0; -} -#endif /* MMC */ -- cgit v0.10.2 From 8b7776b9f95d542d0e81357c4f8aa32f7bf466e5 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Fri, 1 Mar 2013 14:38:20 -0700 Subject: Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 init Use the latest tables & code from our internal U-Boot repo. The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup table were off by a few indices, causing the pinmux init code to write bad data to the PINMUX_AUX_ regs. This also enabled the lock bit, which made it impossible to reconfig the pads correctly for SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N, USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c index 52b3ec4..27b5f69 100644 --- a/arch/arm/cpu/tegra114-common/pinmux.c +++ b/arch/arm/cpu/tegra114-common/pinmux.c @@ -37,6 +37,7 @@ struct tegra_pingroup_desc { #define PMUX_OD_SHIFT 6 #define PMUX_LOCK_SHIFT 7 #define PMUX_IO_RESET_SHIFT 8 +#define PMUX_RCV_SEL_SHIFT 9 /* Convenient macro for defining pin group properties */ #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ @@ -58,6 +59,10 @@ struct tegra_pingroup_desc { #define PINO(pg_name, vdd, f0, f1, f2, f3) \ PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT) +/* A pin group number which is not used */ +#define PIN_RESERVED \ + PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE) + const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { /* NAME VDD f0 f1 f2 f3 */ PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI), @@ -84,71 +89,71 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA), PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA), PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA), - PINI(GPIO_PV2, BB, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(GPIO_PV3, BB, RSVD1, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */ + PIN_RESERVED, PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4), PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4), - PINO(LCD_PWR1, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_PWR2, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_SDIN, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_SDOUT, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_WR_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_CS0_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_DC0, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_SCK, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_PWR0, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_PCLK, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_DE, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_HSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_VSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D0, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D1, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D2, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D3, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D4, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D5, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D6, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D7, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D8, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D9, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D10, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D11, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D12, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D13, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D14, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D15, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D16, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D17, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D18, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D19, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D20, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D21, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D22, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_D23, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_CS1_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_M1, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINO(LCD_DC1, LCD, RSVD1, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */ + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4), PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4), PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4), - PINI(CRT_HSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(CRT_VSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D0, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D1, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D2, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D3, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D4, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D5, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D6, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D7, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D8, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D9, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D10, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_D11, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_PCLK, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_MCLK, VI, RSVD1, RSVD3, RSVD3, RSVD4), - PINI(VI_VSYNC, VI, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(VI_HSYNC, VI, RSVD1, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */ + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4), PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4), PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4), @@ -220,7 +225,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4), - PINI(SDMMC4_RST_N, SDMMC4, RSVD1, RSVD2, RSVD3, SDMMC4), + PIN_RESERVED, /* Reserved by t114: 0x3280 */ PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT2, RSVD4), PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4), PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3), @@ -246,11 +251,11 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA), PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA), PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA), - PINI(KB_ROW11, SYS, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(KB_ROW12, SYS, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(KB_ROW13, SYS, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(KB_ROW14, SYS, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(KB_ROW15, SYS, RSVD1, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */ + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL), PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL), PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4), @@ -278,36 +283,46 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4), PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4), PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4), - PINI(SPI2_MOSI, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4), - PINI(SPI2_MISO, AUDIO, SPI6, RSVD2, RSVD3, RSVD4), - PINI(SPI2_CS0_N, AUDIO, SPI6, SPI1, RSVD3, RSVD4), - PINI(SPI2_SCK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4), - PINI(SPI1_MOSI, AUDIO, RSVD1, SPI1, SPI2, DAP2), - PINI(SPI1_SCK, AUDIO, RSVD1, SPI1, SPI2, RSVD4), - PINI(SPI1_CS0_N, AUDIO, SPI6, SPI1, SPI2, RSVD4), - PINI(SPI1_MISO, AUDIO, RSVD1, SPI1, SPI2, RSVD4), - PINI(SPI2_CS1_N, AUDIO, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(SPI2_CS2_N, AUDIO, RSVD1, RSVD2, RSVD3, RSVD4), + PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4), + PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4), + PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4), + PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4), + PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2), + PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4), + PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4), + PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4), + PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */ + PIN_RESERVED, PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3), PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3), PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3), PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3), PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3), PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3), - PINI(SDMMC3_DAT4, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(SDMMC3_DAT5, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(SDMMC3_DAT6, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4), - PINI(SDMMC3_DAT7, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */ + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, + PIN_RESERVED, PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC), PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA), - PINI(SDMMC3_CD_N, SDMMC3, SDMMC3, OWR, RSVD3, RSVD4), - PINI(SPI1_CS1_N, AUDIO, SPI6, RSVD2, SPI2, I2C1), - PINI(SPI1_CS2_N, AUDIO, SPI6, SPI1, SPI2, I2C1), - PINI(USB_VBUS_EN0, SYS, USB, RSVD2, RSVD3, RSVD4), - PINI(USB_VBUS_EN1, SYS, USB, RSVD2, RSVD3, RSVD4), + PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4), + PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1), + PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1), + PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4), + PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4), PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4), - PINO(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4), - PINO(NAND_GMI_CLK_LB, GMI, SDMMC2, NAND, GMI, RSVD4), + PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4), + PIN_RESERVED, /* Reserved by t114: 0x3404 */ PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N), }; @@ -484,6 +499,30 @@ static int pinmux_set_ioreset(enum pmux_pingrp pin, return 0; } +static int pinmux_set_rcv_sel(enum pmux_pingrp pin, + enum pmux_pin_rcv_sel rcv_sel) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pin_rcv_sel = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and rcv_sel */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_rcv_sel_isvalid(rcv_sel)); + + if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT) + return 0; + + reg = readl(pin_rcv_sel); + reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT); + if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH) + reg |= (0x1 << PMUX_RCV_SEL_SHIFT); + writel(reg, pin_rcv_sel); + + return 0; +} + void pinmux_config_pingroup(struct pingroup_config *config) { enum pmux_pingrp pin = config->pingroup; @@ -495,6 +534,7 @@ void pinmux_config_pingroup(struct pingroup_config *config) pinmux_set_lock(pin, config->lock); pinmux_set_od(pin, config->od); pinmux_set_ioreset(pin, config->ioreset); + pinmux_set_rcv_sel(pin, config->rcv_sel); } void pinmux_config_table(struct pingroup_config *config, int len) diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index fd22930..53905cb 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -50,72 +50,12 @@ enum pmux_pingrp { PINGRP_SDMMC1_DAT2, PINGRP_SDMMC1_DAT1, PINGRP_SDMMC1_DAT0, - PINGRP_GPIO_PV2, - PINGRP_GPIO_PV3, - PINGRP_CLK2_OUT, + PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3, PINGRP_CLK2_REQ, - PINGRP_LCD_PWR1, - PINGRP_LCD_PWR2, - PINGRP_LCD_SDIN, - PINGRP_LCD_SDOUT, - PINGRP_LCD_WR_N, - PINGRP_LCD_CS0_N, - PINGRP_LCD_DC0, - PINGRP_LCD_SCK, - PINGRP_LCD_PWR0, - PINGRP_LCD_PCLK, - PINGRP_LCD_DE, - PINGRP_LCD_HSYNC, - PINGRP_LCD_VSYNC, - PINGRP_LCD_D0, - PINGRP_LCD_D1, - PINGRP_LCD_D2, - PINGRP_LCD_D3, - PINGRP_LCD_D4, - PINGRP_LCD_D5, - PINGRP_LCD_D6, - PINGRP_LCD_D7, - PINGRP_LCD_D8, - PINGRP_LCD_D9, - PINGRP_LCD_D10, - PINGRP_LCD_D11, - PINGRP_LCD_D12, - PINGRP_LCD_D13, - PINGRP_LCD_D14, - PINGRP_LCD_D15, - PINGRP_LCD_D16, - PINGRP_LCD_D17, - PINGRP_LCD_D18, - PINGRP_LCD_D19, - PINGRP_LCD_D20, - PINGRP_LCD_D21, - PINGRP_LCD_D22, - PINGRP_LCD_D23, - PINGRP_LCD_CS1_N, - PINGRP_LCD_M1, - PINGRP_LCD_DC1, - PINGRP_HDMI_INT, + PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41, PINGRP_DDC_SCL, PINGRP_DDC_SDA, - PINGRP_CRT_HSYNC, - PINGRP_CRT_VSYNC, - PINGRP_VI_D0, - PINGRP_VI_D1, - PINGRP_VI_D2, - PINGRP_VI_D3, - PINGRP_VI_D4, - PINGRP_VI_D5, - PINGRP_VI_D6, - PINGRP_VI_D7, - PINGRP_VI_D8, - PINGRP_VI_D9, - PINGRP_VI_D10, - PINGRP_VI_D11, - PINGRP_VI_PCLK, - PINGRP_VI_MCLK, - PINGRP_VI_VSYNC, - PINGRP_VI_HSYNC, - PINGRP_UART2_RXD, + PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19, PINGRP_UART2_TXD, PINGRP_UART2_RTS_N, PINGRP_UART2_CTS_N, @@ -186,8 +126,7 @@ enum pmux_pingrp { PINGRP_SDMMC4_DAT5, PINGRP_SDMMC4_DAT6, PINGRP_SDMMC4_DAT7, - PINGRP_SDMMC4_RST_N, - PINGRP_CAM_MCLK, + PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2, PINGRP_GPIO_PCC1, PINGRP_GPIO_PBB0, PINGRP_CAM_I2C_SCL, @@ -212,12 +151,7 @@ enum pmux_pingrp { PINGRP_KB_ROW8, PINGRP_KB_ROW9, PINGRP_KB_ROW10, - PINGRP_KB_ROW11, - PINGRP_KB_ROW12, - PINGRP_KB_ROW13, - PINGRP_KB_ROW14, - PINGRP_KB_ROW15, - PINGRP_KB_COL0, + PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6, PINGRP_KB_COL1, PINGRP_KB_COL2, PINGRP_KB_COL3, @@ -244,47 +178,30 @@ enum pmux_pingrp { PINGRP_DAP2_DIN, PINGRP_DAP2_DOUT, PINGRP_DAP2_SCLK, - PINGRP_SPI2_MOSI, - PINGRP_SPI2_MISO, - PINGRP_SPI2_CS0_N, - PINGRP_SPI2_SCK, - PINGRP_SPI1_MOSI, - PINGRP_SPI1_SCK, - PINGRP_SPI1_CS0_N, - PINGRP_SPI1_MISO, - PINGRP_SPI2_CS1_N, - PINGRP_SPI2_CS2_N, - PINGRP_SDMMC3_CLK, + PINGRP_DVFS_PWM, + PINGRP_GPIO_X1_AUD, + PINGRP_GPIO_X3_AUD, + PINGRP_DVFS_CLK, + PINGRP_GPIO_X4_AUD, + PINGRP_GPIO_X5_AUD, + PINGRP_GPIO_X6_AUD, + PINGRP_GPIO_X7_AUD, + PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3, PINGRP_SDMMC3_CMD, PINGRP_SDMMC3_DAT0, PINGRP_SDMMC3_DAT1, PINGRP_SDMMC3_DAT2, PINGRP_SDMMC3_DAT3, - PINGRP_SDMMC3_DAT4, - PINGRP_SDMMC3_DAT5, - PINGRP_SDMMC3_DAT6, - PINGRP_SDMMC3_DAT7, - PINGRP_PEX_L0_PRSNT_N, - PINGRP_PEX_L0_RST_N, - PINGRP_PEX_L0_CLKREQ_N, - PINGRP_PEX_WAKE_N, - PINGRP_PEX_L1_PRSNT_N, - PINGRP_PEX_L1_RST_N, - PINGRP_PEX_L1_CLKREQ_N, - PINGRP_PEX_L2_PRSNT_N, - PINGRP_PEX_L2_RST_N, - PINGRP_PEX_L2_CLKREQ_N, - PINGRP_HDMI_CEC, /* offset 0x33e0 */ + PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */ PINGRP_SDMMC1_WP_N, PINGRP_SDMMC3_CD_N, - PINGRP_SPI1_CS1_N, - PINGRP_SPI1_CS2_N, - PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */ + PINGRP_GPIO_W2_AUD, + PINGRP_GPIO_W3_AUD, + PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */ PINGRP_USB_VBUS_EN1, PINGRP_SDMMC3_CLK_LB_IN, PINGRP_SDMMC3_CLK_LB_OUT, - PINGRP_NAND_GMI_CLK_LB, - PINGRP_RESET_OUT_N, + PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2, PINGRP_COUNT, }; @@ -304,23 +221,16 @@ enum pdrive_pingrp { PDRIVE_PINGROUP_DAP3, PDRIVE_PINGROUP_DAP4, PDRIVE_PINGROUP_DBG, - PDRIVE_PINGROUP_LCD1, - PDRIVE_PINGROUP_LCD2, - PDRIVE_PINGROUP_SDIO2, PDRIVE_PINGROUP_SDIO3, PDRIVE_PINGROUP_SPI, PDRIVE_PINGROUP_UAA, PDRIVE_PINGROUP_UAB, PDRIVE_PINGROUP_UART2, PDRIVE_PINGROUP_UART3, - PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */ PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */ PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */ PDRIVE_PINGROUP_DDC, PDRIVE_PINGROUP_GMA, - PDRIVE_PINGROUP_GMB, - PDRIVE_PINGROUP_GMC, - PDRIVE_PINGROUP_GMD, PDRIVE_PINGROUP_GME, PDRIVE_PINGROUP_GMF, PDRIVE_PINGROUP_GMG, @@ -401,6 +311,7 @@ enum pmux_func { PMUX_FUNC_VI, PMUX_FUNC_VI_SENSOR_CLK, PMUX_FUNC_XIO, + /* End of Tegra2 MUX selectors */ PMUX_FUNC_BLINK, PMUX_FUNC_CEC, PMUX_FUNC_CLK12, @@ -444,7 +355,7 @@ enum pmux_func { PMUX_FUNC_VGP4, PMUX_FUNC_VGP5, PMUX_FUNC_VGP6, - + /* End of Tegra3 MUX selectors */ PMUX_FUNC_USB, PMUX_FUNC_SOC, PMUX_FUNC_CPU, @@ -453,10 +364,12 @@ enum pmux_func { PMUX_FUNC_PMI, PMUX_FUNC_CLDVFS, PMUX_FUNC_RESET_OUT_N, + /* End of Tegra114 MUX selectors */ PMUX_FUNC_SAFE, PMUX_FUNC_MAX, + PMUX_FUNC_INVALID = 0x4000, PMUX_FUNC_RSVD1 = 0x8000, PMUX_FUNC_RSVD2 = 0x8001, PMUX_FUNC_RSVD3 = 0x8002, @@ -492,6 +405,7 @@ enum pmux_tristate { enum pmux_pin_io { PMUX_PIN_OUTPUT = 0, PMUX_PIN_INPUT = 1, + PMUX_PIN_NONE, }; /* return 1 if a pin_io_is in range */ #define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \ @@ -525,6 +439,16 @@ enum pmux_pin_ioreset { (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \ ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) +enum pmux_pin_rcv_sel { + PMUX_PIN_RCV_SEL_DEFAULT = 0, + PMUX_PIN_RCV_SEL_NORMAL, + PMUX_PIN_RCV_SEL_HIGH, +}; +/* return 1 if a pin_rcv_sel_is in range */ +#define pmux_pin_rcv_sel_isvalid(rcv_sel) \ + (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \ + ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) + /* Available power domains used by pin groups */ enum pmux_vddio { PMUX_VDDIO_BB = 0, @@ -581,6 +505,8 @@ struct pingroup_config { enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ enum pmux_pin_od od; /* open-drain or push-pull driver */ enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ + enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ + /* VIL/VIH receivers */ }; /* Set a pin group to tristate */ diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index aca3c7d..2020a5f 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -24,6 +24,9 @@ */ void pinmux_init(void) { + pinmux_config_table(tegra114_pinmux_set_nontristate, + ARRAY_SIZE(tegra114_pinmux_set_nontristate)); + pinmux_config_table(tegra114_pinmux_common, ARRAY_SIZE(tegra114_pinmux_common)); diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index 3dd47da..d258819 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -17,7 +17,7 @@ #ifndef _PINMUX_CONFIG_DALMORE_H_ #define _PINMUX_CONFIG_DALMORE_H_ -#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ +#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ { \ .pingroup = PINGRP_##_pingroup, \ .func = PMUX_FUNC_##_mux, \ @@ -41,7 +41,19 @@ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ } -#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ +#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ { \ .pingroup = PINGRP_##_pingroup, \ .func = PMUX_FUNC_##_mux, \ @@ -50,200 +62,291 @@ .io = PMUX_PIN_##_io, \ .lock = PMUX_PIN_LOCK_##_lock, \ .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ } +#define USB_PINMUX CEC_PINMUX + static struct pingroup_config tegra114_pinmux_common[] = { + /* EXTPERIPH1 pinmux */ + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + + /* I2S0 pinmux */ + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + + /* I2S1 pinmux */ + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + + /* I2S3 pinmux */ + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + + /* CLDVFS pinmux */ + DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* VI pinmux */ + VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + + /* VI_ALT1 pinmux */ + VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + + /* VGP4 pinmux */ + VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* UARTD pinmux */ + DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), + + /* SPI4 pinmux */ + DEFAULT_PINMUX(GMI_AD5, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD7, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS6_N, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N, SPI4, NORMAL, NORMAL, INPUT), + + /* PWM1 pinmux */ + DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT), + + /* SOC pinmux */ + DEFAULT_PINMUX(GMI_CS1_N, SOC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_OE_N, SOC, NORMAL, TRISTATE, INPUT), + + /* EXTPERIPH2 pinmux */ + DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, OUTPUT), + /* SDMMC1 pinmux */ - DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_WP_N, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, NORMAL, NORMAL, OUTPUT), - - DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT), /* SDMMC4 pinmux */ - LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT), + + /* BLINK pinmux */ + DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), + + /* KBC pinmux */ + DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT), + + /*Audio Codec*/ + DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT), + + /* UARTA pinmux */ + DEFAULT_PINMUX(KB_ROW10, UARTA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT), + + /* I2CPWR pinmux (I2C5) */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* SYSCLK pinmux */ + DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), + + /* RTCK pinmux */ + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), + + /* CLK pinmux */ + DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT), + + /* PWRON pinmux */ + DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT), + + /* CPU pinmux */ + DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT), + + /* PMI pinmux */ + DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT), + + /* RESET_OUT_N pinmux */ + DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT), + + /* EXTPERIPH3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + /* UARTB pinmux */ + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), - /* I2C3 pinmux */ - I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + /* IRDA pinmux */ + DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), + + /* UARTC pinmux */ + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + + /* OWR pinmux */ + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + + /* CEC pinmux */ + CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), /* I2C4 pinmux */ - I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - /* Power I2C pinmux */ - I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DATA1, UARTA, UP, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), - - /* KBC keys */ - DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PV1, RSVD1, UP, NORMAL, INPUT), - - DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS1_N, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS2_N, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT), - - /* GPIOs */ - /* SDMMC1 CD gpio */ - DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT), - - /* Touch RESET */ - DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT), - - /* Power rails GPIO */ - DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), + DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + + /* USB pinmux */ + USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* nct */ + DEFAULT_PINMUX(GPIO_X6_AUD, SPI6, UP, TRISTATE, INPUT), }; static struct pingroup_config unused_pins_lowpower[] = { - DEFAULT_PINMUX(GMI_CS0_N, NAND, UP, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS3_N, NAND, UP, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS4_N, NAND, UP, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(USB_VBUS_EN1, RSVD3, DOWN, TRISTATE, OUTPUT), }; -#endif /* _PINMUX_CONFIG_DALMORE_H_ */ +/* Initially setting all used GPIO's to non-TRISTATE */ +static struct pingroup_config tegra114_pinmux_set_nontristate[] = { + DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_X5_AUD, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X6_AUD, RSVD3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_W3_AUD, SPI6, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X1_AUD, RSVD3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(DAP3_FS, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(GPIO_PBB3, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB5, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB6, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB7, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PCC1, RSVD3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, RSVD3, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD10, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD12, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD8, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CLK, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS0_N, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS3_N, GMI, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS4_N, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS7_N, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_DQS, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WP_N, GMI, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(SDMMC1_WP_N, SPI4, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW3, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK3_REQ, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), +}; +#endif /* PINMUX_CONFIG_COMMON_H */ -- cgit v0.10.2 From 8ca79b2ff467bda3bc1cfe7fe566f0c1189881dc Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Wed, 6 Mar 2013 16:16:22 -0700 Subject: Tegra30: Cardhu: Add pad config tables/code based on pinmux code Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, only SDIO1CFG is changed as per the TRM to work with the SD-card slot on Cardhu. Thanks to StephenW for the suggestion/original idea. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c index 122665f..eecf058 100644 --- a/arch/arm/cpu/tegra30-common/pinmux.c +++ b/arch/arm/cpu/tegra30-common/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -38,6 +38,19 @@ struct tegra_pingroup_desc { #define PMUX_LOCK_SHIFT 7 #define PMUX_IO_RESET_SHIFT 8 +#define PGRP_HSM_SHIFT 2 +#define PGRP_SCHMT_SHIFT 3 +#define PGRP_LPMD_SHIFT 4 +#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT) +#define PGRP_DRVDN_SHIFT 12 +#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT) +#define PGRP_DRVUP_SHIFT 20 +#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT) +#define PGRP_SLWR_SHIFT 28 +#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT) +#define PGRP_SLWF_SHIFT 30 +#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT) + /* Convenient macro for defining pin group properties */ #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ { \ @@ -504,3 +517,178 @@ void pinmux_config_table(struct pingroup_config *config, int len) for (i = 0; i < len; i++) pinmux_config_pingroup(&config[i]); } + +static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, + int slwf) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_slwf = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and slwf */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_slw_isvalid(slwf)); + + /* NONE means unspecified/do not change/use POR value */ + if (slwf == PGRP_SLWF_NONE) + return 0; + + reg = readl(pad_slwf); + reg &= ~PGRP_SLWF_MASK; + reg |= (slwf << PGRP_SLWF_SHIFT); + writel(reg, pad_slwf); + + return 0; +} + +static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_slwr = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and slwr */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_slw_isvalid(slwr)); + + /* NONE means unspecified/do not change/use POR value */ + if (slwr == PGRP_SLWR_NONE) + return 0; + + reg = readl(pad_slwr); + reg &= ~PGRP_SLWR_MASK; + reg |= (slwr << PGRP_SLWR_SHIFT); + writel(reg, pad_slwr); + + return 0; +} + +static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_drvup = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and drvup */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_drv_isvalid(drvup)); + + /* NONE means unspecified/do not change/use POR value */ + if (drvup == PGRP_DRVUP_NONE) + return 0; + + reg = readl(pad_drvup); + reg &= ~PGRP_DRVUP_MASK; + reg |= (drvup << PGRP_DRVUP_SHIFT); + writel(reg, pad_drvup); + + return 0; +} + +static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_drvdn = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and drvdn */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_drv_isvalid(drvdn)); + + /* NONE means unspecified/do not change/use POR value */ + if (drvdn == PGRP_DRVDN_NONE) + return 0; + + reg = readl(pad_drvdn); + reg &= ~PGRP_DRVDN_MASK; + reg |= (drvdn << PGRP_DRVDN_SHIFT); + writel(reg, pad_drvdn); + + return 0; +} + +static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_lpmd = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad and lpmd value */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_lpmd_isvalid(lpmd)); + + /* NONE means unspecified/do not change/use POR value */ + if (lpmd == PGRP_LPMD_NONE) + return 0; + + reg = readl(pad_lpmd); + reg &= ~PGRP_LPMD_MASK; + reg |= (lpmd << PGRP_LPMD_SHIFT); + writel(reg, pad_lpmd); + + return 0; +} + +static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_schmt = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad */ + assert(pmux_padgrp_isvalid(pad)); + + reg = readl(pad_schmt); + reg &= ~(1 << PGRP_SCHMT_SHIFT); + if (schmt == PGRP_SCHMT_ENABLE) + reg |= (0x1 << PGRP_SCHMT_SHIFT); + writel(reg, pad_schmt); + + return 0; +} +static int padgrp_set_hsm(enum pdrive_pingrp pad, + enum pgrp_hsm hsm) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_hsm = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad */ + assert(pmux_padgrp_isvalid(pad)); + + reg = readl(pad_hsm); + reg &= ~(1 << PGRP_HSM_SHIFT); + if (hsm == PGRP_HSM_ENABLE) + reg |= (0x1 << PGRP_HSM_SHIFT); + writel(reg, pad_hsm); + + return 0; +} + +void padctrl_config_pingroup(struct padctrl_config *config) +{ + enum pdrive_pingrp pad = config->padgrp; + + padgrp_set_drvup_slwf(pad, config->slwf); + padgrp_set_drvdn_slwr(pad, config->slwr); + padgrp_set_drvup(pad, config->drvup); + padgrp_set_drvdn(pad, config->drvdn); + padgrp_set_lpmd(pad, config->lpmd); + padgrp_set_schmt(pad, config->schmt); + padgrp_set_hsm(pad, config->hsm); +} + +void padgrp_config_table(struct padctrl_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + padctrl_config_pingroup(&config[i]); +} diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h index 9b383d0..23d184f 100644 --- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h @@ -56,4 +56,10 @@ struct apb_misc_gp_ctlr { u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ }; +/* SDMMC1/3 settings from section 24.6 of T30 TRM */ +#define SDIOCFG_DRVUP_SLWF 1 +#define SDIOCFG_DRVDN_SLWR 1 +#define SDIOCFG_DRVUP 0x2E +#define SDIOCFG_DRVDN 0x2A + #endif /* _TEGRA30_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index 341951b..a9e1b46 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -531,6 +531,63 @@ enum pmux_vddio { PMUX_VDDIO_NONE }; +#define PGRP_SLWF_NONE -1 +#define PGRP_SLWF_MAX 3 +#define PGRP_SLWR_NONE PGRP_SLWF_NONE +#define PGRP_SLWR_MAX PGRP_SLWF_MAX + +#define PGRP_DRVUP_NONE -1 +#define PGRP_DRVUP_MAX 127 +#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE +#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX + +/* return 1 if a padgrp is in range */ +#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT)) + +/* return 1 if a slew-rate rising/falling edge value is in range */ +#define pmux_pad_slw_isvalid(slw) (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)) + +/* return 1 if a driver output pull-up/down strength code value is in range */ +#define pmux_pad_drv_isvalid(drv) (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)) + +/* return 1 if a low-power mode value is in range */ +#define pmux_pad_lpmd_isvalid(lpm) (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)) + +/* Defines a pin group cfg's low-power mode select */ +enum pgrp_lpmd { + PGRP_LPMD_X8 = 0, + PGRP_LPMD_X4, + PGRP_LPMD_X2, + PGRP_LPMD_X, + PGRP_LPMD_NONE = -1, +}; + +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pgrp_schmt { + PGRP_SCHMT_DISABLE = 0, + PGRP_SCHMT_ENABLE = 1, +}; + +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pgrp_hsm { + PGRP_HSM_DISABLE = 0, + PGRP_HSM_ENABLE = 1, +}; + +/* + * This defines the configuration for a pin group's pad control config + */ +struct padctrl_config { + enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ + int slwf; /* falling edge slew */ + int slwr; /* rising edge slew */ + int drvup; /* pull-up drive strength */ + int drvdn; /* pull-down drive strength */ + enum pgrp_lpmd lpmd; /* low-power mode selection */ + enum pgrp_schmt schmt; /* schmidt enable */ + enum pgrp_hsm hsm; /* high-speed mode enable */ +}; + /* t30 pin drive group and pin mux registers */ #define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) #define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ @@ -600,4 +657,12 @@ void pinmux_config_table(struct pingroup_config *config, int len); /* Set a group of pins from a table */ void pinmux_init(void); +/** + * Set the GP pad configs + * + * @param config List of config items + * @param len Number of config items in list + */ +void padgrp_config_table(struct padctrl_config *config, int len); + #endif /* _TEGRA30_PINMUX_H_ */ diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index df4cb6b..08e9b7b 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2013 * NVIDIA Corporation * * See file CREDITS for list of people who contributed to this @@ -23,6 +23,7 @@ #include #include +#include #include "pinmux-config-cardhu.h" /* @@ -36,4 +37,7 @@ void pinmux_init(void) pinmux_config_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl)); } diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h index 8428bba..51d2b94 100644 --- a/board/nvidia/cardhu/pinmux-config-cardhu.h +++ b/board/nvidia/cardhu/pinmux-config-cardhu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -53,6 +53,18 @@ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ } +#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PGRP_LPMD_##_lpmd, \ + .schmt = PGRP_SCHMT_##_schmt, \ + .hsm = PGRP_HSM_##_hsm, \ + } + static struct pingroup_config tegra3_pinmux_common[] = { /* SDMMC1 pinmux */ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), @@ -326,4 +338,9 @@ static struct pingroup_config unused_pins_lowpower[] = { DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT), }; -#endif /* _PINMUX_CONFIG_CARDHU_H_ */ +static struct padctrl_config cardhu_padctrl[] = { + /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_CARDHU_H_ */ -- cgit v0.10.2 From 1baa4e72c63f8038bb2f874827bebee0eef58fe7 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 26 Feb 2013 11:14:17 -0700 Subject: Tegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now) Took these values directly from the kernel dts files. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 9483e80..ccf154f 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -184,4 +184,36 @@ clocks = <&tegra_car 105>; status = "disabled"; }; + + sdhci@78000000 { + compatible = "nvidia,tegra30-sdhci"; + reg = <0x78000000 0x200>; + interrupts = <0 14 0x04>; + clocks = <&tegra_car 14>; + status = "disabled"; + }; + + sdhci@78000200 { + compatible = "nvidia,tegra30-sdhci"; + reg = <0x78000200 0x200>; + interrupts = <0 15 0x04>; + clocks = <&tegra_car 9>; + status = "disabled"; + }; + + sdhci@78000400 { + compatible = "nvidia,tegra30-sdhci"; + reg = <0x78000400 0x200>; + interrupts = <0 19 0x04>; + clocks = <&tegra_car 69>; + status = "disabled"; + }; + + sdhci@78000600 { + compatible = "nvidia,tegra30-sdhci"; + reg = <0x78000600 0x200>; + interrupts = <0 31 0x04>; + clocks = <&tegra_car 15>; + status = "disabled"; + }; }; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index 48039c9..4d22b48 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -12,6 +12,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000000"; }; memory { @@ -48,4 +50,17 @@ status = "okay"; spi-max-frequency = <25000000>; }; + + sdhci@78000000 { + status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + wp-gpios = <&gpio 155 0>; /* gpio PT3 */ + power-gpios = <&gpio 31 0>; /* gpio PD7 */ + bus-width = <4>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; }; -- cgit v0.10.2 From 38797bcb1f8306429409ca2831309342b77a2e37 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 26 Feb 2013 11:17:43 -0700 Subject: Tegra: MMC: Added/update SDMMC registers/base addresses for T20/T30 Removed SDMMC base addresses from tegra.h since they're no longer used. Added additional vendor-specific SD/MMC registers and bus power defines. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index bd18f5f..2a3f830 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -22,10 +22,7 @@ #ifndef __TEGRA_MMC_H_ #define __TEGRA_MMC_H_ -#define TEGRA_SDMMC1_BASE 0xC8000000 -#define TEGRA_SDMMC2_BASE 0xC8000200 -#define TEGRA_SDMMC3_BASE 0xC8000400 -#define TEGRA_SDMMC4_BASE 0xC8000600 +#include #define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */ @@ -64,12 +61,30 @@ struct tegra_mmc { unsigned char admaerr; /* offset 54h */ unsigned char res4[3]; /* RESERVED, offset 55h-57h */ unsigned long admaaddr; /* offset 58h-5Fh */ - unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ + unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */ unsigned short slotintstatus; /* offset FCh */ unsigned short hcver; /* HOST Version */ - unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */ + unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ + unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */ + unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */ + unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */ + unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */ + unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */ + unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */ + unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */ + unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */ + unsigned int res6[47]; /* 0x124 ~ 0x1DC */ + unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */ + unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */ + unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */ + unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */ }; +#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0) +#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1) +#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1) +#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1) + #define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) @@ -119,6 +134,12 @@ struct tegra_mmc { #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) +/* SDMMC1/3 settings from section 24.6 of T30 TRM */ +#define MEMCOMP_PADCTRL_VREF 7 +#define AUTO_CAL_ENABLED (1 << 29) +#define AUTO_CAL_PD_OFFSET (0x70 << 8) +#define AUTO_CAL_PU_OFFSET (0x62 << 0) + struct mmc_host { struct tegra_mmc *reg; int id; /* device id/number, 0-3 */ @@ -132,5 +153,7 @@ struct mmc_host { unsigned int clock; /* Current clock (MHz) */ }; +void pad_init_mmc(struct mmc_host *host); + #endif /* __ASSEMBLY__ */ #endif /* __TEGRA_MMC_H_ */ -- cgit v0.10.2 From 190be1f9b74b0c8c2f1b2735774a6536758837af Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 26 Feb 2013 12:26:55 -0700 Subject: Tegra30: MMC: Add SD bus power-rail and SDMMC pad init routines T30 requires specific SDMMC pad programming, and bus power-rail bringup. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index 08e9b7b..3544b41 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -25,6 +25,10 @@ #include #include #include "pinmux-config-cardhu.h" +#include + +#define PMU_I2C_ADDRESS 0x2D +#define MAX_I2C_RETRY 3 /* * Routine: pinmux_init @@ -41,3 +45,50 @@ void pinmux_init(void) /* Initialize any non-default pad configs (APB_MISC_GP regs) */ padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl)); } + +#if defined(CONFIG_TEGRA_MMC) +/* + * Do I2C/PMU writes to bring up SD card bus power + * + */ +void board_sdmmc_voltage_init(void) +{ + uchar reg, data_buffer[1]; + int i; + + i2c_set_bus_num(0); /* PMU is on bus 0 */ + + /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */ + data_buffer[0] = 0x65; + reg = 0x32; + + for (i = 0; i < MAX_I2C_RETRY; ++i) { + if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) + udelay(100); + } + + /* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */ + data_buffer[0] = 0x09; + reg = 0x67; + + for (i = 0; i < MAX_I2C_RETRY; ++i) { + if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) + udelay(100); + } +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* + * NOTE: We don't do mmc-specific pin muxes here. + * They were done globally in pinmux_init(). + */ + + /* Bring up the SDIO1 power rail */ + board_sdmmc_voltage_init(); +} +#endif /* MMC */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index babbe08..7d9f361 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -49,6 +49,7 @@ #include #endif #ifdef CONFIG_TEGRA_MMC +#include #include #endif #include @@ -245,4 +246,32 @@ int board_mmc_init(bd_t *bd) return 0; } -#endif + +void pad_init_mmc(struct mmc_host *host) +{ +#if defined(CONFIG_TEGRA30) + enum periph_id id = host->mmc_id; + u32 val; + + debug("%s: sdmmc address = %08x, id = %d\n", __func__, + (unsigned int)host->reg, id); + + /* Set the pad drive strength for SDMMC1 or 3 only */ + if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { + debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", + __func__); + return; + } + + val = readl(&host->reg->sdmemcmppadctl); + val &= 0xFFFFFFF0; + val |= MEMCOMP_PADCTRL_VREF; + writel(val, &host->reg->sdmemcmppadctl); + + val = readl(&host->reg->autocalcfg); + val &= 0xFFFF0000; + val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; + writel(val, &host->reg->autocalcfg); +#endif /* T30 */ +} +#endif /* MMC */ -- cgit v0.10.2 From 2d348a1652f1d1211ab82cb0c7a57a3362830d71 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 26 Feb 2013 12:31:26 -0700 Subject: mmc: Tegra: Add SD bus power/voltage function and MMC pad init call. Tegra30 requires the SD Bus Voltage & Power bits be set in the SD Power Control register. Tegra20 works w/o them set, but do it anyway for those SoCs as it's part of the SD spec. Also call a common board pad init routine (pad_init_mmc) in mmc_reset(), used by Tegra30 only for now. Note that Tegra20 SD/MMC HW differs enough from Tegra20 that a new compatible entry is used in the fdt compat_names/id tables. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 455a690..e86bc68 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -21,7 +21,6 @@ #include #include -#include #include #include #include @@ -38,6 +37,38 @@ struct mmc_host mmc_host[MAX_HOSTS]; #error "Please enable device tree support to use this driver" #endif +static void mmc_set_power(struct mmc_host *host, unsigned short power) +{ + u8 pwr = 0; + debug("%s: power = %x\n", __func__, power); + + if (power != (unsigned short)-1) { + switch (1 << power) { + case MMC_VDD_165_195: + pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; + break; + } + } + debug("%s: pwr = %X\n", __func__, pwr); + + /* Set the bus voltage first (if any) */ + writeb(pwr, &host->reg->pwrcon); + if (pwr == 0) + return; + + /* Now enable bus power */ + pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER; + writeb(pwr, &host->reg->pwrcon); +} + static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data, struct bounce_buffer *bbstate) { @@ -334,8 +365,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) debug(" mmc_change_clock called\n"); /* - * Change Tegra SDMMCx clock divisor here. Source is 216MHz, - * PLLP_OUT0 + * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0 */ if (clock == 0) goto out; @@ -410,7 +440,7 @@ static void mmc_set_ios(struct mmc *mmc) debug("mmc_set_ios: hostctl = %08X\n", ctrl); } -static void mmc_reset(struct mmc_host *host) +static void mmc_reset(struct mmc_host *host, struct mmc *mmc) { unsigned int timeout; debug(" mmc_reset called\n"); @@ -436,6 +466,14 @@ static void mmc_reset(struct mmc_host *host) timeout--; udelay(1000); } + + /* Set SD bus voltage & enable bus power */ + mmc_set_power(host, fls(mmc->voltages) - 1); + debug("%s: power control = %02X, host control = %02X\n", __func__, + readb(&host->reg->pwrcon), readb(&host->reg->hostctl)); + + /* Make sure SDIO pads are set up */ + pad_init_mmc(host); } static int mmc_core_init(struct mmc *mmc) @@ -444,7 +482,7 @@ static int mmc_core_init(struct mmc *mmc) unsigned int mask; debug(" mmc_core_init called\n"); - mmc_reset(host); + mmc_reset(host, mmc); host->version = readw(&host->reg->hcver); debug("host version = %x\n", host->version); @@ -642,12 +680,21 @@ void tegra_mmc_init(void) const void *blob = gd->fdt_blob; debug("%s entry\n", __func__); + /* See if any Tegra30 MMC controllers are present */ count = fdtdec_find_aliases_for_id(blob, "sdhci", - COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS); - debug("%s: count of sdhci nodes is %d\n", __func__, count); + COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS); + debug("%s: count of T30 sdhci nodes is %d\n", __func__, count); + if (process_nodes(blob, node_list, count)) { + printf("%s: Error processing T30 mmc node(s)!\n", __func__); + return; + } + /* Now look for any Tegra20 MMC controllers */ + count = fdtdec_find_aliases_for_id(blob, "sdhci", + COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS); + debug("%s: count of T20 sdhci nodes is %d\n", __func__, count); if (process_nodes(blob, node_list, count)) { - printf("%s: Error processing mmc node(s)!\n", __func__); + printf("%s: Error processing T20 mmc node(s)!\n", __func__); return; } } -- cgit v0.10.2 From f4e4e0b0e3405785a5a4b46913a9476175adc12d Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Mon, 4 Mar 2013 14:07:18 -0700 Subject: Tegra30: mmc: Add Tegra30 SDMMC compatible entry to fdtdec & driver Tegra30 SD/MMC controller differs enough from Tegra20 that it needs its own entry in the compat_names/compat_id tables and in the Tegra MMC driver. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/include/fdtdec.h b/include/fdtdec.h index 32730d2..2189483 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -71,7 +71,8 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ - COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra SDMMC controller */ + COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ + COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */ COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 000130f..43f29f5 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -46,6 +46,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"), COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), + COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"), COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"), -- cgit v0.10.2 From ca557b386d957a853e085259b4c501b7a0ee1ee2 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 26 Feb 2013 12:36:22 -0700 Subject: Tegra30: MMC: Enable DT MMC driver support for Tegra30 Cardhu boards Tested on my Cardhu-A04 tablet, eMMC and SD-Card work fine, can load a kernel off of an SD card OK, card detect works, and the env is now stored in eMMC (end of the 2nd 'boot' sector, same as Tegra20). Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 1616b39..18c7eb8 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -47,7 +47,25 @@ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_CMD_I2C -#define CONFIG_ENV_IS_NOWHERE +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_FS_EXT4 +#define CONFIG_FS_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ #define CONFIG_TEGRA_SLINK diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 04517e1..bd1dfe8 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -86,4 +86,7 @@ /* Total I2C ports on Tegra30 */ #define TEGRA_I2C_NUM_CONTROLLERS 5 +/* Misc utility code */ +#define CONFIG_BOUNCE_BUFFER + #endif /* _TEGRA30_COMMON_H_ */ -- cgit v0.10.2 From a885f85214dcd358b29a2ffe69ab4f9b515b95e9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 28 Feb 2013 15:03:45 +0000 Subject: ARM: tegra: make bounce buffer option common All Tegra devices will need CONFIG_BOUNCE_BUFFER. Move it to tegra-common.h to ensure it's always set. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 80c846c..080feb0 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -155,4 +155,7 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT +/* Misc utility code */ +#define CONFIG_BOUNCE_BUFFER + #endif /* _TEGRA_COMMON_H_ */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 33e5f52..dac8245 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -114,7 +114,4 @@ #define CONFIG_SYS_NAND_SELF_INIT #define CONFIG_SYS_NAND_ONFI_DETECTION -/* Misc utility code */ -#define CONFIG_BOUNCE_BUFFER - #endif /* _TEGRA20_COMMON_H_ */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index bd1dfe8..04517e1 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -86,7 +86,4 @@ /* Total I2C ports on Tegra30 */ #define TEGRA_I2C_NUM_CONTROLLERS 5 -/* Misc utility code */ -#define CONFIG_BOUNCE_BUFFER - #endif /* _TEGRA30_COMMON_H_ */ -- cgit v0.10.2 From 2c1af9dcdcf4ede8d153c0918beca9067ec0eb36 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 28 Feb 2013 15:03:46 +0000 Subject: disk: define HAVE_BLOCK_DEVICE in a common place This set of ifdefs is used in a number of places. Move its definition somewhere common so it doesn't have to be repeated. Signed-off-by: Stephen Warren Acked-by: Simon Glass Acked-by: Tom Rini Signed-off-by: Tom Warren diff --git a/disk/part.c b/disk/part.c index 58a4563..d73625c 100644 --- a/disk/part.c +++ b/disk/part.c @@ -35,16 +35,6 @@ #define PRINTF(fmt,args...) #endif -/* Rather than repeat this expression each time, add a define for it */ -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) ) -#define HAVE_BLOCK_DEVICE -#endif - struct block_drvr { char *name; block_dev_desc_t* (*get_dev)(int dev); diff --git a/disk/part_amiga.c b/disk/part_amiga.c index dc7d462..0e6d82d 100644 --- a/disk/part_amiga.c +++ b/disk/part_amiga.c @@ -26,11 +26,7 @@ #include #include "part_amiga.h" -#if defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) +#ifdef HAVE_BLOCK_DEVICE #undef AMIGA_DEBUG diff --git a/disk/part_dos.c b/disk/part_dos.c index 3fe901b..37087a6 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -35,12 +35,7 @@ #include #include "part_dos.h" -#if defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) +#ifdef HAVE_BLOCK_DEVICE /* Convert char[4] in little endian format to the host format integer */ diff --git a/disk/part_efi.c b/disk/part_efi.c index 7665017..b3fd0e9 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -39,13 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) - +#ifdef HAVE_BLOCK_DEVICE /** * efi_crc32() - EFI version of crc32 function * @buf: buffer to calculate crc32 of diff --git a/disk/part_iso.c b/disk/part_iso.c index 4401790..49639af 100644 --- a/disk/part_iso.c +++ b/disk/part_iso.c @@ -25,12 +25,7 @@ #include #include "part_iso.h" -#if defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) +#ifdef HAVE_BLOCK_DEVICE /* #define ISO_PART_DEBUG */ diff --git a/disk/part_mac.c b/disk/part_mac.c index cb443ac..74dc12f 100644 --- a/disk/part_mac.c +++ b/disk/part_mac.c @@ -34,12 +34,7 @@ #include #include "part_mac.h" -#if defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) +#ifdef HAVE_BLOCK_DEVICE /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ #ifndef __ldiv_t_defined diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index bfb9680..653ff2b 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -26,4 +26,14 @@ #define CONFIG_EXT4_WRITE #endif +/* Rather than repeat this expression each time, add a define for it */ +#if defined(CONFIG_CMD_IDE) || \ + defined(CONFIG_CMD_SATA) || \ + defined(CONFIG_CMD_SCSI) || \ + defined(CONFIG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) +#define HAVE_BLOCK_DEVICE +#endif + #endif /* __CONFIG_FALLBACKS_H */ -- cgit v0.10.2 From 4123c4ea23cd8b9f3313bccb6c2add87b06412a3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 28 Feb 2013 15:03:47 +0000 Subject: disk: define HAVE_BLOCK_DEVICE if CONFIG_CMD_PART Various code that is conditional upon HAVE_BLOCK_DEVICE is required by code conditional upon CONFIG_CMD_PART. So, enable HAVE_BLOCK_DEVICE if CONFIG_CMD_PART is enabled. Signed-off-by: Stephen Warren Acked-by: Simon Glass Acked-by: Tom Rini Signed-off-by: Tom Warren diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 653ff2b..9298d0e 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -31,6 +31,7 @@ defined(CONFIG_CMD_SATA) || \ defined(CONFIG_CMD_SCSI) || \ defined(CONFIG_CMD_USB) || \ + defined(CONFIG_CMD_PART) || \ defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) #define HAVE_BLOCK_DEVICE -- cgit v0.10.2 From 11d9c0303949c2e9c2a176f81c0d7355c76bb546 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 28 Feb 2013 15:03:48 +0000 Subject: ARM: tegra: enable a common set of disk-related commands everywhere Enable a common set of partition types, filesystems, and related commands in tegra-common.h, so that they are available on all Tegra boards. This allows boot.scr (loaded and executed by the default built-in environment) on those boards to assume that certain features are always available. Do this in tegra-common.h, so that individual board files can undefine the features if they really don't want any of them. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 18c7eb8..55dc83d 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -53,14 +53,6 @@ #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_FS_EXT4 -#define CONFIG_FS_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE) diff --git a/include/configs/colibri_t20_iris.h b/include/configs/colibri_t20_iris.h index 0e5f281..856c860 100644 --- a/include/configs/colibri_t20_iris.h +++ b/include/configs/colibri_t20_iris.h @@ -40,12 +40,6 @@ #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC -/* File system support */ -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - /* USB host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 8d1fd47..0c73f86 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -56,14 +56,6 @@ #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_FS_EXT4 -#define CONFIG_FS_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC - /* NAND support */ #define CONFIG_CMD_NAND #define CONFIG_TEGRA_NAND diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index bae4ba0..57a50d7 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -66,11 +66,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - #define CONFIG_FIT #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 2edb4aa..eac1ef9 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -44,14 +44,6 @@ #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_FS_EXT4 -#define CONFIG_FS_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE) diff --git a/include/configs/plutux.h b/include/configs/plutux.h index deee237..4cfe88a 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -65,11 +65,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - #define CONFIG_FIT #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index de0c777..f66173e 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -70,14 +70,6 @@ #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_FS_EXT4 -#define CONFIG_FS_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE) diff --git a/include/configs/tec.h b/include/configs/tec.h index caeb9cd..f90f5c7 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -73,11 +73,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - #define CONFIG_FIT #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 080feb0..4cc35e5 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -88,6 +88,18 @@ #define CONFIG_COMMAND_HISTORY #define CONFIG_AUTO_COMPLETE +/* turn on commonly used storage-related commands */ + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_FS_EXT4 +#define CONFIG_FS_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_PART + #define CONFIG_SYS_NO_FLASH #define CONFIG_CONSOLE_MUX diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index dac8245..311680e 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -108,9 +108,6 @@ /* Total I2C ports on Tegra20 */ #define TEGRA_I2C_NUM_CONTROLLERS 4 -#define CONFIG_PARTITION_UUIDS -#define CONFIG_CMD_PART - #define CONFIG_SYS_NAND_SELF_INIT #define CONFIG_SYS_NAND_ONFI_DETECTION diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 334d3a3..0644f7a 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -67,14 +67,6 @@ #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_FS_EXT4 -#define CONFIG_FS_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC - /* Environment in SPI */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_MAX_HZ 48000000 diff --git a/include/configs/ventana.h b/include/configs/ventana.h index b55ebc9..5755f11 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -50,14 +50,6 @@ #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_FS_EXT4 -#define CONFIG_FS_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC - /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE) diff --git a/include/configs/whistler.h b/include/configs/whistler.h index 1e554d8..9542c7e 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -59,14 +59,6 @@ #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_FS_EXT4 -#define CONFIG_FS_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FS_GENERIC - /* * Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes * the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If -- cgit v0.10.2 From b3b6ddff0bb6768af7532da4cee5362fbe41ec4b Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Wed, 13 Mar 2013 15:00:54 -0700 Subject: Tegra114: pinmux: Fix bad CAM_MCLK func 3 table entry This caused CAM_MCLK's pinmux reg to be locked out, since the table parsing code couldn't find a matching entry for VI_ALT3 and wrote garbage to the register. Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c index 27b5f69..16368c5 100644 --- a/arch/arm/cpu/tegra114-common/pinmux.c +++ b/arch/arm/cpu/tegra114-common/pinmux.c @@ -226,7 +226,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4), PIN_RESERVED, /* Reserved by t114: 0x3280 */ - PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT2, RSVD4), + PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4), PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4), PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3), PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4), -- cgit v0.10.2 From 36c48be1104664ab79e5655327f39812e979c6aa Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Wed, 13 Mar 2013 15:13:47 -0700 Subject: Tegra114: Fix/update GP padcfg register struct Differences in padcfg registers (some removed, some added) between Tegra30 and Tegra114 weren't picked up when I first ported this file. Signed-off-by: Tom Warren diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h index c538bdd..1ef1a14 100644 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h @@ -27,7 +27,7 @@ struct apb_misc_gp_ctlr { u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ + u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ @@ -35,25 +35,43 @@ struct apb_misc_gp_ctlr { u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */ + u32 reserved1; /* 0x8C: */ u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */ - u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */ - u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */ + u32 reserved2[3]; /* 0xA4 - 0xAC: */ u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */ - u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */ - u32 reserved1[7]; /* 0xD0-0xE8: */ + u32 reserved3[9]; /* 0xC8-0xE8: */ u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ + u32 reserved4[3]; /* 0xF0-0xF8: */ + u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ + u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ + u32 reserved5[3]; /* 0x104-0x10C: */ + u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ + u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ + u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ + u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ + u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ + u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ + u32 reserved6; /* 0x128: */ + u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ + u32 reserved7[2]; /* 0x130 - 0x134: */ + u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ + u32 reserved8[22]; /* 0x13C - 0x190: */ + u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ + u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ + u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ + u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ + u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ + u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ + u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ }; #endif /* _TEGRA114_GP_PADCTRL_H_ */ -- cgit v0.10.2 From f31a5443a8b52a613fcafc0330a303420eafcca4 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Wed, 13 Mar 2013 15:40:33 -0700 Subject: Tegra114: Dalmore: Always use DEFAULT instead of DISABLE for lock bits The pinmux code issues a warning if the caller attempts to disable the lock bit in a pinmux register, since this is impossible (once it's locked, the only way to unlock it is to reset the device/pmt controller). The I2C/DDC/CEC/USB macros expect a lock setting to be passed in, and the previous setting of DISABLE caused the pinmux table parsing code to issue the warning. Changing the lock bits in these table entries to DEFAULT (i.e. don't touch it) fixes this. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index d258819..cb48b3b 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -120,8 +120,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT), /* I2C3 pinmux */ - I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), /* VI pinmux */ VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), @@ -133,8 +133,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), /* UARTD pinmux */ DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), @@ -212,8 +212,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT), /* I2CPWR pinmux (I2C5) */ - I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), /* SYSCLK pinmux */ DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), @@ -240,8 +240,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), /* UARTB pinmux */ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), @@ -261,14 +261,14 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), /* CEC pinmux */ - CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), /* I2C4 pinmux */ - DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH), - DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), /* USB pinmux */ - USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* nct */ DEFAULT_PINMUX(GPIO_X6_AUD, SPI6, UP, TRISTATE, INPUT), -- cgit v0.10.2 From 5647c0343176d8ea257abf44211c493ef139d3e8 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Mon, 11 Mar 2013 17:07:21 -0700 Subject: Tegra114: fdt: Move aliases from dtsi to dts file as per other Tegras All other Tegra boards have their alias nodes in the .dts file Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index dfeac53..701c0f9 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -3,14 +3,6 @@ / { compatible = "nvidia,tegra114"; - aliases { - i2c0 = "/i2c@7000d000"; - i2c1 = "/i2c@7000c000"; - i2c2 = "/i2c@7000c400"; - i2c3 = "/i2c@7000c500"; - i2c4 = "/i2c@7000c700"; - }; - tegra_car: clock { compatible = "nvidia,tegra114-car"; reg = <0x60006000 0x1000>; diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts index 3e1e1ea..30cf1fb 100644 --- a/board/nvidia/dts/tegra114-dalmore.dts +++ b/board/nvidia/dts/tegra114-dalmore.dts @@ -6,6 +6,14 @@ model = "NVIDIA Dalmore"; compatible = "nvidia,dalmore", "nvidia,tegra114"; + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + }; + memory { device_type = "memory"; reg = <0x80000000 0x80000000>; -- cgit v0.10.2 From 477393e7875cf4261f107fdfb8887309ea7fc3f7 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Mon, 11 Mar 2013 16:43:49 -0700 Subject: Tegra114: Dalmore: Add pad config tables/code based on pinmux code Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, no padcfg entries exist. SDIO3CFG will be added when the MMC driver is added as per the TRM to work with the SD-card slot on Dalmore E1611. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c index 16368c5..4983a05 100644 --- a/arch/arm/cpu/tegra114-common/pinmux.c +++ b/arch/arm/cpu/tegra114-common/pinmux.c @@ -39,6 +39,19 @@ struct tegra_pingroup_desc { #define PMUX_IO_RESET_SHIFT 8 #define PMUX_RCV_SEL_SHIFT 9 +#define PGRP_HSM_SHIFT 2 +#define PGRP_SCHMT_SHIFT 3 +#define PGRP_LPMD_SHIFT 4 +#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT) +#define PGRP_DRVDN_SHIFT 12 +#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT) +#define PGRP_DRVUP_SHIFT 20 +#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT) +#define PGRP_SLWR_SHIFT 28 +#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT) +#define PGRP_SLWF_SHIFT 30 +#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT) + /* Convenient macro for defining pin group properties */ #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ { \ @@ -544,3 +557,184 @@ void pinmux_config_table(struct pingroup_config *config, int len) for (i = 0; i < len; i++) pinmux_config_pingroup(&config[i]); } + +static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_slwf = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and slwf */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_slw_isvalid(slwf)); + + /* NONE means unspecified/do not change/use POR value */ + if (slwf == PGRP_SLWF_NONE) + return 0; + + reg = readl(pad_slwf); + reg &= ~PGRP_SLWF_MASK; + reg |= (slwf << PGRP_SLWF_SHIFT); + writel(reg, pad_slwf); + + return 0; +} + +static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_slwr = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and slwr */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_slw_isvalid(slwr)); + + /* NONE means unspecified/do not change/use POR value */ + if (slwr == PGRP_SLWR_NONE) + return 0; + + reg = readl(pad_slwr); + reg &= ~PGRP_SLWR_MASK; + reg |= (slwr << PGRP_SLWR_SHIFT); + writel(reg, pad_slwr); + + return 0; +} + +static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_drvup = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and drvup */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_drv_isvalid(drvup)); + + /* NONE means unspecified/do not change/use POR value */ + if (drvup == PGRP_DRVUP_NONE) + return 0; + + reg = readl(pad_drvup); + reg &= ~PGRP_DRVUP_MASK; + reg |= (drvup << PGRP_DRVUP_SHIFT); + writel(reg, pad_drvup); + + return 0; +} + +static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_drvdn = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and drvdn */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_drv_isvalid(drvdn)); + + /* NONE means unspecified/do not change/use POR value */ + if (drvdn == PGRP_DRVDN_NONE) + return 0; + + reg = readl(pad_drvdn); + reg &= ~PGRP_DRVDN_MASK; + reg |= (drvdn << PGRP_DRVDN_SHIFT); + writel(reg, pad_drvdn); + + return 0; +} + +static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_lpmd = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad and lpmd value */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_lpmd_isvalid(lpmd)); + + /* NONE means unspecified/do not change/use POR value */ + if (lpmd == PGRP_LPMD_NONE) + return 0; + + reg = readl(pad_lpmd); + reg &= ~PGRP_LPMD_MASK; + reg |= (lpmd << PGRP_LPMD_SHIFT); + writel(reg, pad_lpmd); + + return 0; +} + +static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_schmt = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad */ + assert(pmux_padgrp_isvalid(pad)); + + /* NONE means unspecified/do not change/use POR value */ + if (schmt == PGRP_SCHMT_NONE) + return 0; + + reg = readl(pad_schmt); + reg &= ~(1 << PGRP_SCHMT_SHIFT); + if (schmt == PGRP_SCHMT_ENABLE) + reg |= (0x1 << PGRP_SCHMT_SHIFT); + writel(reg, pad_schmt); + + return 0; +} +static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_hsm = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad */ + assert(pmux_padgrp_isvalid(pad)); + + /* NONE means unspecified/do not change/use POR value */ + if (hsm == PGRP_HSM_NONE) + return 0; + + reg = readl(pad_hsm); + reg &= ~(1 << PGRP_HSM_SHIFT); + if (hsm == PGRP_HSM_ENABLE) + reg |= (0x1 << PGRP_HSM_SHIFT); + writel(reg, pad_hsm); + + return 0; +} + +void padctrl_config_pingroup(struct padctrl_config *config) +{ + enum pdrive_pingrp pad = config->padgrp; + + padgrp_set_drvup_slwf(pad, config->slwf); + padgrp_set_drvdn_slwr(pad, config->slwr); + padgrp_set_drvup(pad, config->drvup); + padgrp_set_drvdn(pad, config->drvdn); + padgrp_set_lpmd(pad, config->lpmd); + padgrp_set_schmt(pad, config->schmt); + padgrp_set_hsm(pad, config->hsm); +} + +void padgrp_config_table(struct padctrl_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + padctrl_config_pingroup(&config[i]); +} diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 53905cb..9c22c08 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -215,34 +215,35 @@ enum pdrive_pingrp { PDRIVE_PINGROUP_AT5, PDRIVE_PINGROUP_CDEV1, PDRIVE_PINGROUP_CDEV2, - PDRIVE_PINGROUP_CSUS, - PDRIVE_PINGROUP_DAP1, + PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */ PDRIVE_PINGROUP_DAP2, PDRIVE_PINGROUP_DAP3, PDRIVE_PINGROUP_DAP4, PDRIVE_PINGROUP_DBG, - PDRIVE_PINGROUP_SDIO3, + PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */ PDRIVE_PINGROUP_SPI, PDRIVE_PINGROUP_UAA, PDRIVE_PINGROUP_UAB, PDRIVE_PINGROUP_UART2, PDRIVE_PINGROUP_UART3, - PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */ - PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */ - PDRIVE_PINGROUP_DDC, + PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */ + PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */ PDRIVE_PINGROUP_GMA, - PDRIVE_PINGROUP_GME, + PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */ PDRIVE_PINGROUP_GMF, PDRIVE_PINGROUP_GMG, PDRIVE_PINGROUP_GMH, PDRIVE_PINGROUP_OWR, PDRIVE_PINGROUP_UAD, - PDRIVE_PINGROUP_GPV, PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */ PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */ - PDRIVE_PINGROUP_AT6, + PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */ PDRIVE_PINGROUP_DAP5, PDRIVE_PINGROUP_VBUS, + PDRIVE_PINGROUP_AO3, + PDRIVE_PINGROUP_HVC, + PDRIVE_PINGROUP_SDIO4, + PDRIVE_PINGROUP_AO0, PDRIVE_PINGROUP_COUNT, }; @@ -470,10 +471,73 @@ enum pmux_vddio { PMUX_VDDIO_NONE }; -/* T114 pin drive group and pin mux registers */ -#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) -#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ - PDRIVE_PINGROUP_COUNT) +#define PGRP_SLWF_NONE -1 +#define PGRP_SLWF_MAX 3 +#define PGRP_SLWR_NONE PGRP_SLWF_NONE +#define PGRP_SLWR_MAX PGRP_SLWF_MAX + +#define PGRP_DRVUP_NONE -1 +#define PGRP_DRVUP_MAX 127 +#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE +#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX + +#define PGRP_SCHMT_NONE -1 +#define PGRP_HSM_NONE PGRP_SCHMT_NONE + +/* return 1 if a padgrp is in range */ +#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT)) + +/* return 1 if a slew-rate rising/falling edge value is in range */ +#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \ + (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))) + +/* return 1 if a driver output pull-up/down strength code value is in range */ +#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \ + (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))) + +/* return 1 if a low-power mode value is in range */ +#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \ + (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))) + +/* Defines a pin group cfg's low-power mode select */ +enum pgrp_lpmd { + PGRP_LPMD_X8 = 0, + PGRP_LPMD_X4, + PGRP_LPMD_X2, + PGRP_LPMD_X, + PGRP_LPMD_NONE = -1, +}; + +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pgrp_schmt { + PGRP_SCHMT_DISABLE = 0, + PGRP_SCHMT_ENABLE = 1, +}; + +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pgrp_hsm { + PGRP_HSM_DISABLE = 0, + PGRP_HSM_ENABLE = 1, +}; + +/* + * This defines the configuration for a pin group's pad control config + */ +struct padctrl_config { + enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ + int slwf; /* falling edge slew */ + int slwr; /* rising edge slew */ + int drvup; /* pull-up drive strength */ + int drvdn; /* pull-down drive strength */ + enum pgrp_lpmd lpmd; /* low-power mode selection */ + enum pgrp_schmt schmt; /* schmidt enable */ + enum pgrp_hsm hsm; /* high-speed mode enable */ +}; + +/* t114 pin drive group and pin mux registers */ +#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) +#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ + PDRIVE_PINGROUP_COUNT) struct pmux_tri_ctlr { uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ @@ -541,4 +605,12 @@ void pinmux_config_table(struct pingroup_config *config, int len); /* Set a group of pins from a table */ void pinmux_init(void); -#endif /* _TEGRA114_PINMUX_H_ */ +/** + * Set the GP pad configs + * + * @param config List of config items + * @param len Number of config items in list + */ +void padgrp_config_table(struct padctrl_config *config, int len); + +#endif /* _TEGRA114_PINMUX_H_ */ diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index cb48b3b..3ef6f4e 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -79,6 +79,18 @@ #define USB_PINMUX CEC_PINMUX +#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PGRP_LPMD_##_lpmd, \ + .schmt = PGRP_SCHMT_##_schmt, \ + .hsm = PGRP_HSM_##_hsm, \ + } + static struct pingroup_config tegra114_pinmux_common[] = { /* EXTPERIPH1 pinmux */ DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), -- cgit v0.10.2 From 030752addc757190a65154dd4d77c9b7044c063e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 14 Mar 2013 02:32:54 +0000 Subject: nitrogen6x: Fix RAM size variable Fix the following build error when buildig nitrogen6s1g: nitrogen6x.c:89:17: error: 'CONFIG_DDR_MB' undeclared (first use in this function) nitrogen6x.c:89:17: note: each undeclared identifier is reported only once for each function it appears in Reported-by: Albert Aribaud Signed-off-by: Fabio Estevam diff --git a/boards.cfg b/boards.cfg index fb3b197..84f96e0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -260,7 +260,7 @@ nitrogen6dl2g arm armv7 nitrogen6x boundar nitrogen6q arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 nitrogen6q2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 nitrogen6s arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 -nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,SDRAM_MB=1024 +nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 cm_t35 arm armv7 cm_t35 - omap3 omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 -- cgit v0.10.2 From 19a0f7fa271de0345bb2df90d443c547c41e8037 Mon Sep 17 00:00:00 2001 From: "fabio.estevam@freescale.com" Date: Thu, 14 Mar 2013 02:32:55 +0000 Subject: nitrogen: Use unsigned long to specify the total RAM size When building for the nitrogen boards with 2GiB the following warning happens: nitrogen6x.c:89:38: warning: integer overflow in expression [-Woverflow] 2GiB can not fit in 32-bits, so use ulong instead. Reported-by: Albert Aribaud Signed-off-by: Fabio Estevam diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 0dbb6d2..229c237 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -86,7 +86,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = CONFIG_DDR_MB * 1024 * 1024; + gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); return 0; } -- cgit v0.10.2