From 0d3972cfcd6dff18d110d2ee01ad99e3623bfd45 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 6 Jan 2016 11:26:51 +0800 Subject: fsl/ddr: Add workaround for ERRATUM_A009942 During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 49b113d..83a207c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -118,6 +118,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 +#define CONFIG_SYS_FSL_ERRATUM_A009942 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 3fca5c2..0d9dd0b 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -55,6 +55,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ u32 *vref_seq = vref_seq1; #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ulong ddr_freq; + u32 tmp; +#endif #ifdef CONFIG_FSL_DDR_BIST u32 mtcr, err_detect, err_sbe; u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; @@ -227,6 +231,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[25], 0x9000); } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + tmp = ddr_in32(&ddr->debug[28]); + if (ddr_freq <= 1333) + ddr_out32(&ddr->debug[28], tmp | 0x0080006a); + else if (ddr_freq <= 1600) + ddr_out32(&ddr->debug[28], tmp | 0x0070006f); + else if (ddr_freq <= 1867) + ddr_out32(&ddr->debug[28], tmp | 0x00700076); + else if (ddr_freq <= 2133) + ddr_out32(&ddr->debug[28], tmp | 0x0060007b); +#endif + /* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is * deasserted. Clocks start when any chip select is enabled and clock -- cgit v0.10.2 From 58e4ad1deee26425a6e0623481a0ced6a0c2db4e Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Mon, 4 Jan 2016 11:03:44 +0800 Subject: armv8/ls1043aqds: Add support for >2GB memory This patch also exposes the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie Reviewed-by: York Sun diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 42d9068..3d3c533 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -132,9 +132,22 @@ void dram_init_banksize(void) * The address needs to add the offset of its bank. */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } } diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index d6696ca..576fa46 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -303,6 +303,16 @@ int board_init(void) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 398f1c3..02247b3 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -33,7 +33,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 -- cgit v0.10.2 From 98d9aa4013d9ad4df199297e79d955f55bd6eead Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Thu, 31 Dec 2015 18:29:02 +0800 Subject: freescale/qixis: Add support for booting from SD/QSPI 1.Use "qixis_reset sd" to boot from SD 2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support 3.Use "qixis_reset qspi" to boot from QSPI flash On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be pin-multiplexed. So the switches are different between SD boot with IFC support and SD boot with QSPI support. The default booting from SD is with IFC support. Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS. Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 9f6b0e7..113295f 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -216,6 +216,39 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #else printf("Not implemented\n"); #endif + } else if (strcmp(argv[1], "sd") == 0) { +#ifdef QIXIS_LBMAP_SD + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_SD); + set_rcw_src(QIXIS_RCW_SRC_SD); + QIXIS_WRITE(rcfg_ctl, 0x20); + QIXIS_WRITE(rcfg_ctl, 0x21); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "sd_qspi") == 0) { +#ifdef QIXIS_LBMAP_SD_QSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_SD_QSPI); + set_rcw_src(QIXIS_RCW_SRC_SD); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "qspi") == 0) { +#ifdef QIXIS_LBMAP_QSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_QSPI); + set_rcw_src(QIXIS_RCW_SRC_QSPI); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); +#else + printf("Not implemented\n"); +#endif } else if (strcmp(argv[1], "watchdog") == 0) { static char *period[9] = {"2s", "4s", "8s", "16s", "32s", "1min", "2min", "4min", "8min"}; @@ -255,6 +288,9 @@ U_BOOT_CMD( "- hard reset to default bank\n" "qixis_reset altbank - reset to alternate bank\n" "qixis_reset nand - reset to nand\n" + "qixis_reset sd - reset to sd\n" + "qixis_reset sd_qspi - reset to sd with qspi support\n" + "qixis_reset qspi - reset to qspi\n" "qixis watchdog - set the watchdog period\n" " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" "qixis_reset dump - display the QIXIS registers\n" -- cgit v0.10.2 From a4b7d68c647a14b62e400dc4e298794a3357bdd1 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Thu, 31 Dec 2015 18:29:03 +0800 Subject: armv8/ls1043aqds: fix qixis_reset command issue Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 02247b3..04b215c 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -212,7 +212,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x44 +#define QIXIS_RST_CTL_RESET 0x41 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -- cgit v0.10.2 From ee2a4eee8f7eb3128da3b9bcd72bd1de1e04e5b0 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Thu, 31 Dec 2015 18:29:04 +0800 Subject: armv8/ls1043aqds: enable qixis_reset command to boot from NAND/SD Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 04b215c..12e845f 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -212,6 +212,10 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_RCW_SRC_NAND 0x106 +#define QIXIS_RCW_SRC_SD 0x040 #define QIXIS_RST_CTL_RESET 0x41 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -- cgit v0.10.2 From 6f14e257c472c895499c186b602861e90f2656b5 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 24 Dec 2015 17:25:06 +0530 Subject: armv8: fsl-lsch3: fixup SYSCLK frequency in device tree SYSCLK frequency is dependent on on-board switch settings. It may vary as per requirement. boot-loader is aware of board switch configurations. So Fixup Linux device tree from boot-loader. Signed-off-by: Prabhakar Kushwaha CC: Mingkai Hu Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index eafdd71..4e4861d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -190,6 +190,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif + do_fixup_by_compat_u32(blob, "fixed-clock", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif -- cgit v0.10.2 From a994b3deb00bf3177cdf9f92060baec4f640f466 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 16 Dec 2015 16:45:41 +0800 Subject: driver/ddr/fsl: Add workaround for A009663 Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 83a207c..f1b164f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -118,7 +118,9 @@ #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009942 + #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -167,6 +169,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 #else #error SoC not defined diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index f066480..424fe87 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -131,6 +131,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #else #error SoC not defined #endif diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index a493556..3b06ae4 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -326,6 +326,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) puts("Work-around for Erratum XFI on B4860QDS enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + puts("Work-around for Erratum A009663 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 674fac8..eccc146 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -808,6 +808,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) @@ -856,6 +857,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 0d9dd0b..6f76980 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -155,7 +155,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + ddr_out32(&ddr->sdram_interval, + regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); +#else ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#endif ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); #ifndef CONFIG_SYS_FSL_DDR_EMU @@ -397,6 +402,11 @@ step2: if (timeout <= 0) printf("Waiting for D_INIT timeout. Memory may not work.\n"); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#endif + #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { /* exit self-refresh */ diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 9ea8b63..3699c04 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -129,6 +129,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG2_ODT_ONLY_READ 2 #define SDRAM_CFG2_ODT_ALWAYS 3 +#define SDRAM_INTERVAL_BSTOPRE 0x3FFF #define TIMING_CFG_2_CPO_MASK 0x0F800000 #if defined(CONFIG_SYS_FSL_DDR_VER) && \ -- cgit v0.10.2 From 1ef7ac70e24c40553307d5246cfa6ebd7394f2f1 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Wed, 16 Dec 2015 13:50:57 +0800 Subject: arm: ls1021a: Adjust sata register default values Updated the default sata register values to enhance the performance and stability. Signed-off-by: Tang Yuantian Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c index deeb674..144f2c3 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c @@ -11,11 +11,11 @@ /* port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28183411 -#define AHCI_PORT_PHY_3_CFG 0x0e081004 -#define AHCI_PORT_PHY_4_CFG 0x00480811 -#define AHCI_PORT_PHY_5_CFG 0x192c96a4 -#define AHCI_PORT_TRANS_CFG 0x08000025 +#define AHCI_PORT_PHY_2_CFG 0x28183414 +#define AHCI_PORT_PHY_3_CFG 0x0e080e06 +#define AHCI_PORT_PHY_4_CFG 0x064a080b +#define AHCI_PORT_PHY_5_CFG 0x2aa86470 +#define AHCI_PORT_TRANS_CFG 0x08000029 #define SATA_ECC_REG_ADDR 0x20220520 #define SATA_ECC_DISABLE 0x00020000 -- cgit v0.10.2 From c238ad0a33469c02c6e6ef3cbcf335d959e04650 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Mon, 14 Dec 2015 18:05:35 +0800 Subject: armv8: fsl-layerscape: fixes lsch2 serdes registers define Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 21b803f..8a4b0d7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -451,7 +451,8 @@ struct ccsr_serdes { u32 res_0c; /* 0x00c */ u32 pllcr3; u32 pllcr4; - u8 res_18[0x20-0x18]; + u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ + u8 res_1c[0x20-0x1c]; } bank[2]; u8 res_40[0x90-0x40]; u32 srdstcalcr; /* 0x90 TX Calibration Control */ @@ -459,25 +460,25 @@ struct ccsr_serdes { u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ u8 res_a4[0xb0-0xa4]; u32 srdsgr0; /* 0xb0 General Register 0 */ - u8 res_b4[0xe0-0xb4]; - u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ - u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ - u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ - u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ - u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ - u8 res_f4[0x100-0xf4]; + u8 res_b4[0x100-0xb4]; struct { - u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ + u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ u8 res_104[0x120-0x104]; - } srdslnpssr[4]; - u8 res_180[0x300-0x180]; - u32 srdspexeqcr; - u32 srdspexeqpcr[11]; - u8 res_330[0x400-0x330]; - u32 srdspexapcr; - u8 res_404[0x440-0x404]; - u32 srdspexbpcr; - u8 res_444[0x800-0x444]; + } lnpssr[4]; /* Lane A, B, C, D */ + u8 res_180[0x200-0x180]; + u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ + u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ + u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ + u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ + u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ + u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ + u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ + u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ + u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ + u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ + u32 srdspccra; /* 0x228 Protocol Configuration A */ + u32 srdspccrb; /* 0x22c Protocol Configuration B */ + u8 res_230[0x800-0x230]; struct { u32 gcr0; /* 0x800 General Control Register 0 */ u32 gcr1; /* 0x804 General Control Register 1 */ @@ -490,8 +491,34 @@ struct ccsr_serdes { u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ u8 res_824[0x83c-0x824]; u32 tcsr3; - } lane[4]; /* Lane A, B, C, D, E, F, G, H */ - u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ + } lane[4]; /* Lane A, B, C, D */ + u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ + struct { + u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ + u8 res_1004[0x1040-0x1004]; + } pcie[3]; + u8 res_10c0[0x1800-0x10c0]; + struct { + u8 res_1800[0x1804-0x1800]; + u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ + u8 res_1808[0x180c-0x1808]; + u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ + } sgmii[4]; /* Lane A, B, C, D */ + u8 res_1840[0x1880-0x1840]; + struct { + u8 res_1880[0x1884-0x1880]; + u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ + u8 res_1888[0x188c-0x1888]; + u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ + } qsgmii[2]; /* Lane A, B */ + u8 res_18a0[0x1980-0x18a0]; + struct { + u8 res_1980[0x1984-0x1980]; + u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ + u8 res_1988[0x198c-0x1988]; + u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ + } xfi[2]; /* Lane A, B */ + u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ }; #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 -- cgit v0.10.2 From 81dfdee0dc6c6ca6bdf0c75e0903afefc950d512 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 14 Jan 2016 12:28:04 -0600 Subject: drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers Following commit 61bd2f75, exclude unused DDR controller from calculating RAM size for SPL boot. Signed-off-by: Ed Swarthout Reviewed-by: York Sun diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 139a3a7..479184f 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -857,6 +857,7 @@ fsl_ddr_sdram_size(void) info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; info.board_need_mem_reset = NULL; + remove_unused_controllers(&info); /* Compute it once normally. */ total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); -- cgit v0.10.2 From bc71f926e35be8af1a9491ea0332871881c7eda5 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 14:14:12 +0530 Subject: SECURE BOOT: change prototype of fsl_secboot_validate function The prototype and defination of function fsl_secboot_validate has been changed to support calling this function from another function within u-boot. Only two aruments needed: 1) header address - Mandatory 2) SHA256 string - optional Signed-off-by: Saksham Jain Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index 8bbe85b..ae6a9af 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -21,10 +21,25 @@ loop: static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + char *hash_str = NULL; + ulong haddr; + int ret; + if (argc < 2) return cmd_usage(cmdtp); + else if (argc > 2) + /* Second arg - Optional - Hash Str*/ + hash_str = argv[2]; + + /* First argument - header address -32/64bit */ + haddr = simple_strtoul(argv[1], NULL, 16); - return fsl_secboot_validate(cmdtp, flag, argc, argv); + ret = fsl_secboot_validate(haddr, hash_str); + if (ret) + return 1; + + printf("esbc_validate command successful\n"); + return 0; } /***************************************************/ diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index b510c71..282ce53 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -699,13 +699,11 @@ static inline int str2longbe(const char *p, ulong *num) return *p != '\0' && *endptr == '\0'; } -int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) +int fsl_secboot_validate(ulong haddr, char *arg_hash_str) { struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ulong hash[SHA256_BYTES/sizeof(ulong)]; char hash_str[NUM_HEX_CHARS + 1]; - ulong addr = simple_strtoul(argv[1], NULL, 16); struct fsl_secboot_img_priv *img; struct fsl_secboot_img_hdr *hdr; void *esbc; @@ -717,8 +715,8 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, struct udevice *mod_exp_dev; #endif - if (argc == 3) { - char *cp = argv[2]; + if (arg_hash_str != NULL) { + const char *cp = arg_hash_str; int i = 0; if (*cp == '0' && *(cp + 1) == 'x') @@ -731,7 +729,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, */ if (strlen(cp) != SHA256_NIBBLES) { printf("%s is not a 256 bits hex string as expected\n", - argv[2]); + arg_hash_str); return -1; } @@ -741,7 +739,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, hash_str[NUM_HEX_CHARS] = '\0'; if (!str2longbe(hash_str, &hash[i])) { printf("%s is not a 256 bits hex string ", - argv[2]); + arg_hash_str); return -1; } } @@ -757,7 +755,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, memset(img, 0, sizeof(struct fsl_secboot_img_priv)); hdr = &img->hdr; - img->ehdrloc = addr; + img->ehdrloc = haddr; esbc = (u8 *)(uintptr_t)img->ehdrloc; memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); @@ -843,8 +841,6 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, goto exit; } - printf("esbc_validate command successful\n"); - exit: - return 0; + return ret; } diff --git a/include/fsl_validate.h b/include/fsl_validate.h index a62dc74..bda802f 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -193,11 +193,10 @@ struct fsl_secboot_img_priv { */ struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */ - u32 ehdrloc; /* ESBC client location */ + ulong ehdrloc; /* ESBC client location */ }; -int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]); +int fsl_secboot_validate(ulong haddr, char *arg_hash_str); int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, -- cgit v0.10.2 From 94ba5e41402719ab8a58bf55b925867e50abcb35 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 14:14:13 +0530 Subject: SECURE BOOT: separate functions for reading keys Separate functions are created for reading and checking the sanity of Public keys: - read_validate_single_key - read_validate_ie_tbl - read_validate_srk_table Signed-off-by: Saksham Jain Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 282ce53..ef7a5ae 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -24,6 +24,10 @@ #define SHA256_NIBBLES (256/4) #define NUM_HEX_CHARS (sizeof(ulong) * 2) +#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ + ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ + ((key_len) == 2 * KEY_SIZE_BYTES)) + /* This array contains DER value for SHA-256 */ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, @@ -179,20 +183,97 @@ static u32 is_key_revoked(u32 keynum, u32 rev_flag) return 0; } -/* It validates srk_table key lengths.*/ -static u32 validate_srk_tbl(struct srk_table *tbl, u32 num_entries) +/* It read validates srk_table key lengths.*/ +static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img) { int i = 0; - for (i = 0; i < num_entries; i++) { - if (!((tbl[i].key_len == 2 * KEY_SIZE_BYTES/4) || - (tbl[i].key_len == 2 * KEY_SIZE_BYTES/2) || - (tbl[i].key_len == 2 * KEY_SIZE_BYTES))) + u32 ret, key_num, key_revoc_flag, size; + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + + if ((hdr->len_kr.num_srk == 0) || + (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) + return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; + + key_num = hdr->len_kr.srk_sel; + if (key_num == 0 || key_num > hdr->len_kr.num_srk) + return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; + + /* Get revoc key from sfp */ + key_revoc_flag = get_key_revoc(); + ret = is_key_revoked(key_num, key_revoc_flag); + if (ret) + return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; + + size = hdr->len_kr.num_srk * sizeof(struct srk_table); + + memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); + + for (i = 0; i < hdr->len_kr.num_srk; i++) { + if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len)) return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN; } + + img->key_len = img->srk_tbl[key_num - 1].key_len; + + memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), + img->key_len); + return 0; } #endif +static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + + /* check key length */ + if (!CHECK_KEY_LEN(hdr->key_len)) + return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; + + memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); + + img->key_len = hdr->key_len; + + return 0; +} + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + u32 ie_key_len, ie_revoc_flag, ie_num; + struct ie_key_info *ie_info; + + if (get_ie_info_addr(&img->ie_addr)) + return ERROR_IE_TABLE_NOT_FOUND; + ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; + if (ie_info->num_keys == 0 || ie_info->num_keys > 32) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; + + ie_num = hdr->ie_key_sel; + if (ie_num == 0 || ie_num > ie_info->num_keys) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; + + ie_revoc_flag = ie_info->key_revok; + if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) + return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; + + ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; + + if (!CHECK_KEY_LEN(ie_key_len)) + return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; + + memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), + ie_key_len); + + img->key_len = ie_key_len; + return 0; +} +#endif + + /* This function return length of public key.*/ static inline u32 get_key_len(struct fsl_secboot_img_priv *img) { @@ -541,13 +622,9 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) struct fsl_secboot_img_hdr *hdr = &img->hdr; void *esbc = (u8 *)(uintptr_t)img->ehdrloc; u8 *k, *s; + u32 ret = 0; + #ifdef CONFIG_KEY_REVOCATION - u32 ret; - u32 key_num, key_revoc_flag, size; -#endif -#if defined(CONFIG_FSL_ISBC_KEY_EXT) - struct ie_key_info *ie_info; - u32 ie_num, ie_revoc_flag, ie_key_len; #endif int key_found = 0; @@ -568,80 +645,26 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) /* Key checking*/ #ifdef CONFIG_KEY_REVOCATION if (check_srk(img)) { - if ((hdr->len_kr.num_srk == 0) || - (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) - return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; - - key_num = hdr->len_kr.srk_sel; - if (key_num == 0 || key_num > hdr->len_kr.num_srk) - return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; - - /* Get revoc key from sfp */ - key_revoc_flag = get_key_revoc(); - ret = is_key_revoked(key_num, key_revoc_flag); - if (ret) - return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; - - size = hdr->len_kr.num_srk * sizeof(struct srk_table); - - memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); - - ret = validate_srk_tbl(img->srk_tbl, hdr->len_kr.num_srk); - + ret = read_validate_srk_tbl(img); if (ret != 0) return ret; - - img->key_len = img->srk_tbl[key_num - 1].key_len; - - memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), - img->key_len); - key_found = 1; } #endif #if defined(CONFIG_FSL_ISBC_KEY_EXT) if (!key_found && check_ie(img)) { - if (get_ie_info_addr(&img->ie_addr)) - return ERROR_IE_TABLE_NOT_FOUND; - ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; - if (ie_info->num_keys == 0 || ie_info->num_keys > 32) - return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; - - ie_num = hdr->ie_key_sel; - if (ie_num == 0 || ie_num > ie_info->num_keys) - return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; - - ie_revoc_flag = ie_info->key_revok; - if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) - return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; - - ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; - - if (!((ie_key_len == 2 * KEY_SIZE_BYTES / 4) || - (ie_key_len == 2 * KEY_SIZE_BYTES / 2) || - (ie_key_len == 2 * KEY_SIZE_BYTES))) - return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; - - memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), - ie_key_len); - - img->key_len = ie_key_len; + ret = read_validate_ie_tbl(img); + if (ret != 0) + return ret; key_found = 1; } #endif if (key_found == 0) { - /* check key length */ - if (!((hdr->key_len == 2 * KEY_SIZE_BYTES / 4) || - (hdr->key_len == 2 * KEY_SIZE_BYTES / 2) || - (hdr->key_len == 2 * KEY_SIZE_BYTES))) - return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; - - memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); - - img->key_len = hdr->key_len; - + ret = read_validate_single_key(img); + if (ret != 0) + return ret; key_found = 1; } -- cgit v0.10.2 From 6629261ddd9d78c3cd8193b05c00a2a9bdc74796 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 14:14:14 +0530 Subject: SECURE BOOT: separate function created for signature The code for image hash calculation, hash calculation from RSA signature and comparison of hashes has been mobed to a separate function. Signed-off-by: Saksham Jain Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index ef7a5ae..08a2f79 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -721,6 +721,58 @@ static inline int str2longbe(const char *p, ulong *num) return *p != '\0' && *endptr == '\0'; } +/* Function to calculate the ESBC Image Hash + * and hash from Digital signature. + * The Two hash's are compared to yield the + * result of signature validation. + */ +static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) +{ + int ret; + uint32_t key_len; + struct key_prop prop; +#if !defined(USE_HOSTCC) + struct udevice *mod_exp_dev; +#endif + ret = calc_esbchdr_esbc_hash(img); + if (ret) + return ret; + + /* Construct encoded hash EM' wrt PKCSv1.5 */ + construct_img_encoded_hash_second(img); + + /* Fill prop structure for public key */ + memset(&prop, 0, sizeof(struct key_prop)); + key_len = get_key_len(img) / 2; + prop.modulus = img->img_key; + prop.public_exponent = img->img_key + key_len; + prop.num_bits = key_len * 8; + prop.exp_len = key_len; + + ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); + if (ret) { + printf("RSA: Can't find Modular Exp implementation\n"); + return -EINVAL; + } + + ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, + &prop, img->img_encoded_hash); + if (ret) + return ret; + + /* + * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 + * memcmp returns zero on success + * memcmp returns non-zero on failure + */ + ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, + img->hdr.sign_len); + + if (ret) + return ERROR_ESBC_CLIENT_HASH_COMPARE_EM; + + return 0; +} int fsl_secboot_validate(ulong haddr, char *arg_hash_str) { @@ -732,11 +784,6 @@ int fsl_secboot_validate(ulong haddr, char *arg_hash_str) void *esbc; int ret, i, hash_cmd = 0; u32 srk_hash[8]; - uint32_t key_len; - struct key_prop prop; -#if !defined(USE_HOSTCC) - struct udevice *mod_exp_dev; -#endif if (arg_hash_str != NULL) { const char *cp = arg_hash_str; @@ -821,46 +868,9 @@ int fsl_secboot_validate(ulong haddr, char *arg_hash_str) goto exit; } - ret = calc_esbchdr_esbc_hash(img); - if (ret) { - fsl_secblk_handle_error(ret); - goto exit; - } - - /* Construct encoded hash EM' wrt PKCSv1.5 */ - construct_img_encoded_hash_second(img); - - /* Fill prop structure for public key */ - memset(&prop, 0, sizeof(struct key_prop)); - key_len = get_key_len(img) / 2; - prop.modulus = img->img_key; - prop.public_exponent = img->img_key + key_len; - prop.num_bits = key_len * 8; - prop.exp_len = key_len; - - ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); - if (ret) { - printf("RSA: Can't find Modular Exp implementation\n"); - return -EINVAL; - } - - ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, - &prop, img->img_encoded_hash); - if (ret) { - fsl_secblk_handle_error(ret); - goto exit; - } - - /* - * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 - * memcmp returns zero on success - * memcmp returns non-zero on failure - */ - ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, - img->hdr.sign_len); - + ret = calculate_cmp_img_sig(img); if (ret) { - fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_EM); + fsl_secboot_handle_error(ret); goto exit; } -- cgit v0.10.2 From b055a0fd867b11e40944b3414026d37ea00e0840 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 14:14:15 +0530 Subject: SECURE BOOT: support for validation of dynamic image Some images to be validated are relocated to a dynamic address at run time. So, these addresses cannot be known befor hand while signing the images and creating the header offline. So, support is required to pass the image address to the validate function as an argument. If an address is provided to the function, the address field in Header is not read and is treated as a reserved field. Signed-off-by: Saksham Jain Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index ae6a9af..ca7c737 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -22,7 +22,7 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *hash_str = NULL; - ulong haddr; + uintptr_t haddr; int ret; if (argc < 2) @@ -32,9 +32,13 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, hash_str = argv[2]; /* First argument - header address -32/64bit */ - haddr = simple_strtoul(argv[1], NULL, 16); + haddr = (uintptr_t)simple_strtoul(argv[1], NULL, 16); - ret = fsl_secboot_validate(haddr, hash_str); + /* With esbc_validate command, Image address must be + * part of header. So, the function is called + * by passing this argument as 0. + */ + ret = fsl_secboot_validate(haddr, hash_str, 0); if (ret) return 1; diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 08a2f79..de40081 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -536,13 +536,8 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) return ret; /* Update hash for actual Image */ -#ifdef CONFIG_ESBC_ADDR_64BIT ret = algo->hash_update(algo, ctx, - (u8 *)(uintptr_t)img->hdr.pimg64, img->hdr.img_size, 1); -#else - ret = algo->hash_update(algo, ctx, - (u8 *)(uintptr_t)img->hdr.pimg, img->hdr.img_size, 1); -#endif + (u8 *)img->img_addr, img->img_size, 1); if (ret) return ret; @@ -632,16 +627,25 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) return ERROR_ESBC_CLIENT_HEADER_BARKER; -#ifdef CONFIG_ESBC_ADDR_64BIT - sprintf(buf, "%llx", hdr->pimg64); -#else - sprintf(buf, "%x", hdr->pimg); -#endif + /* If Image Address is not passed as argument to function, + * then Address and Size must be read from the Header. + */ + if (img->img_addr == 0) { + #ifdef CONFIG_ESBC_ADDR_64BIT + img->img_addr = hdr->pimg64; + #else + img->img_addr = hdr->pimg; + #endif + } + + sprintf(buf, "%lx", img->img_addr); setenv("img_addr", buf); if (!hdr->img_size) return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE; + img->img_size = hdr->img_size; + /* Key checking*/ #ifdef CONFIG_KEY_REVOCATION if (check_srk(img)) { @@ -774,7 +778,8 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) return 0; } -int fsl_secboot_validate(ulong haddr, char *arg_hash_str) +int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, + uintptr_t img_addr) { struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ulong hash[SHA256_BYTES/sizeof(ulong)]; @@ -824,9 +829,11 @@ int fsl_secboot_validate(ulong haddr, char *arg_hash_str) memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + /* Update the information in Private Struct */ hdr = &img->hdr; img->ehdrloc = haddr; - esbc = (u8 *)(uintptr_t)img->ehdrloc; + img->img_addr = img_addr; + esbc = (u8 *)img->ehdrloc; memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); diff --git a/include/fsl_validate.h b/include/fsl_validate.h index bda802f..ad14867 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -193,10 +193,13 @@ struct fsl_secboot_img_priv { */ struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */ - ulong ehdrloc; /* ESBC client location */ + uintptr_t ehdrloc; /* ESBC Header location */ + uintptr_t img_addr; /* ESBC Image Location */ + uint32_t img_size; /* ESBC Image Size */ }; -int fsl_secboot_validate(ulong haddr, char *arg_hash_str); +int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, + uintptr_t img_loc); int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, -- cgit v0.10.2 From 191e3c0527100cb980f0cd714f469b701d7050ae Mon Sep 17 00:00:00 2001 From: Pratiyush Mohan Srivastava Date: Tue, 22 Dec 2015 16:47:35 +0530 Subject: armv8: Enable all 8 DPMAC ports in LS2080A Personality LS2080A has support for 8 DPMAC ports out of which only 5 ports can be used at a time. Enabling all 8 DPMAC ports of LS2080A personality. Signed-off-by: Pratiyush Mohan Srivastava Acked-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index 8ef4f1c..ea3114c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -28,12 +28,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII1 } }, {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, -#ifdef CONFIG_LS2080A - {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } }, -#endif -#ifdef CONFIG_LS2085A {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, -#endif {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, -- cgit v0.10.2 From aa4ba7f7a276566f4d0814c41314a629050c6208 Mon Sep 17 00:00:00 2001 From: Pratiyush Mohan Srivastava Date: Tue, 22 Dec 2015 16:48:43 +0530 Subject: armv8: ls2040a: Add support of LS2040A SoC Freescale's LS2040A is a another personality of LS2080A SoC without AIOP support consisting of 4 armv8 cores. Signed-off-by: Pratiyush Mohan Srivastava Acked-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index e030430..b10ee43 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -12,6 +12,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS2085, LS2085, 8), CPU_TYPE_ENTRY(LS2045, LS2045, 4), CPU_TYPE_ENTRY(LS1043, LS1043, 4), + CPU_TYPE_ENTRY(LS2040, LS2040, 4), }; #ifndef CONFIG_SYS_DCACHE_OFF diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 1565592..ea78e15 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -45,6 +45,7 @@ struct cpu_type { #define SVR_LS2045 0x870120 #define SVR_LS2080 0x870110 #define SVR_LS2085 0x870100 +#define SVR_LS2040 0x870130 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) -- cgit v0.10.2 From 52c11d4f08ee3028688c1956718594cd47e2f0e2 Mon Sep 17 00:00:00 2001 From: Pratiyush Mohan Srivastava Date: Tue, 22 Dec 2015 16:49:34 +0530 Subject: armv8: ls2080a: Increase MC's DDR size to 512 MB Freescale's management complex (MC) uses System DDR for internal usage. Increase used System DDR size from 256MB to 512 MB. Signed-off-by: Pratiyush Mohan Srivastava Acked-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4ae7d11..7323e10 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -196,7 +196,7 @@ unsigned long long get_qixis_addr(void); */ #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif -- cgit v0.10.2 From c088326597cad019618a98f6fc65bc1dd92eb301 Mon Sep 17 00:00:00 2001 From: Pratiyush Mohan Srivastava Date: Tue, 22 Dec 2015 16:50:19 +0530 Subject: drivers: net: fsl_mc: Compare pointer value qbman_swp_mc_start Current code compares the return pointer of function qbman_cena_write_start with NULL. Instead the value of the return pointer should be compared. Signed-off-by: Pratiyush Mohan Srivastava Acked-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.c b/drivers/net/fsl-mc/dpio/qbman_portal.c index 449ff8a..4b64c8a 100644 --- a/drivers/net/fsl-mc/dpio/qbman_portal.c +++ b/drivers/net/fsl-mc/dpio/qbman_portal.c @@ -102,12 +102,14 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) void *qbman_swp_mc_start(struct qbman_swp *p) { void *ret; + int *return_val; #ifdef QBMAN_CHECKING BUG_ON(p->mc.check != swp_mc_can_start); #endif ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR); #ifdef QBMAN_CHECKING - if (!ret) + return_val = (int *)ret; + if (!(*return_val)) p->mc.check = swp_mc_can_submit; #endif return ret; -- cgit v0.10.2 From ef6c55a240a0ce303617cde81b08ac96f56a89d7 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:22 +0530 Subject: secure_boot: include/configs: make secure boot header file uniform The file fsl_secure_boot.h must be included in config file for Secure Boot. This is not required to be protected by any macro. CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be turned on. The above was missing in some config files and all files have been made uniform in this respect. Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 806302b..b29e71c 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -34,6 +34,11 @@ #define CONFIG_FSL_ISBC_KEY_EXT #endif +#ifdef CONFIG_LS1043A +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#define CONFIG_ESBC_ADDR_64BIT +#endif + #ifndef CONFIG_FIT_SIGNATURE #define CONFIG_EXTRA_ENV \ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 16920c6..890dcbb 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -567,4 +567,8 @@ #include +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 951cbc4..fb41a7d 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -39,6 +39,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #endif +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg @@ -936,8 +938,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 4a0f5b2..113df37 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -33,6 +33,8 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* support deep sleep */ #ifdef CONFIG_PPC_T1024 #define CONFIG_DEEP_SLEEP @@ -948,8 +950,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 9e151da..5fd93a1 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -835,8 +835,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #endif diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index da65f56..eec2971 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -938,8 +938,9 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #endif diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a0cecc6..019878a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -933,8 +933,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 312b0eb..3665b7d 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -889,8 +889,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index e8b1eca..ee4494a 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -659,12 +659,15 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MISC_INIT_R /* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM #define CONFIG_CMD_HASH #define CONFIG_SHA_HW_ACCEL +#endif + +#include #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB -#include #endif #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 317ba62..d20062a 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -517,12 +517,15 @@ #define CONFIG_MISC_INIT_R /* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM #define CONFIG_CMD_HASH #define CONFIG_SHA_HW_ACCEL +#endif + +#include #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB -#include #endif #endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 677d281..e80ac27 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -197,6 +197,8 @@ #define CONFIG_DOS_PARTITION #endif +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* FMan ucode */ #define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN @@ -252,4 +254,10 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 12e845f..4929d98 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -405,4 +405,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_MII #define CONFIG_CMDLINE_TAG +#include + #endif /* __LS1043AQDS_H__ */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 585114f..dbdcc51 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -291,14 +291,6 @@ #define CONFIG_CMD_EXT2 #endif -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#define CONFIG_CMD_BLOB -/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ -#define CONFIG_ESBC_ADDR_64BIT -#endif - #include #endif /* __LS1043ARDB_H__ */ -- cgit v0.10.2 From 74eecd820f251c6700c828d662a600c01651217f Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:23 +0530 Subject: secure_boot: include/configs: move definition of CONFIG_CMD_BLOB CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index b29e71c..8491a72 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -9,6 +9,7 @@ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 87415b1..7d217a6 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -10,6 +10,7 @@ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_DM diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 9fb5cee..bcbae50 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -924,8 +924,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index d0e5a25..89907dc 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -722,8 +722,4 @@ combinations. this should be removed later #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 890dcbb..16920c6 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -567,8 +567,4 @@ #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f9776c0..3c0faca 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -952,8 +952,4 @@ extern unsigned long get_sdram_size(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b2e51b5..f250e7f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -756,8 +756,4 @@ unsigned long get_board_sys_clk(unsigned long dummy); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index fb41a7d..e5df784 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -946,8 +946,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 113df37..3cda3b1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -958,8 +958,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 5fd93a1..2e7892f 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -837,8 +837,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index eec2971..5fc3497 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -940,8 +940,4 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 019878a..a56208c 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -935,9 +935,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#undef CONFIG_CMD_USB -#endif - #endif /* __T208xQDS_H */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 3665b7d..b5290a1 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -891,9 +891,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#undef CONFIG_CMD_USB -#endif - #endif /* __T2080RDB_H */ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 1b94f64..91857d6 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -644,8 +644,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 73279c8..eb4d52c 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -837,13 +837,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -/* Secure Boot target was not getting build for T4240 because of - * increased binary size. So the size is being reduced by removing USB - * which is anyways not used in Secure Environment. - */ -#undef CONFIG_CMD_USB -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index aef37dd..a099eee 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -765,8 +765,4 @@ #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ee4494a..c90f531 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -666,8 +666,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index d20062a..f820de3 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -524,8 +524,4 @@ #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif -- cgit v0.10.2 From bdc22074c511def222f93d1a9d94ec95c462c062 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:24 +0530 Subject: secure_boot: split the secure boot functionality in two parts There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 8491a72..0da0599 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,6 +8,14 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_SECURE_BOOT + +#ifndef CONFIG_FIT_SIGNATURE +#define CONFIG_CHAIN_OF_TRUST +#endif + +#endif + +#ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON @@ -40,8 +48,6 @@ #define CONFIG_ESBC_ADDR_64BIT #endif -#ifndef CONFIG_FIT_SIGNATURE - #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfffffff;" \ "setenv initrd_high 0xcfffffff;" \ @@ -50,8 +56,6 @@ /* The address needs to be modified according to NOR memory map */ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000 -#include -#endif -#endif - +#include +#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 7d217a6..41058d1 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -9,19 +9,11 @@ #include #ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_CMD_BLOB -#define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM -#define CONFIG_RSA -#define CONFIG_RSA_FREESCALE_EXP -#ifndef CONFIG_FSL_CAAM -#define CONFIG_FSL_CAAM -#endif + +#ifndef CONFIG_FIT_SIGNATURE +#define CONFIG_CHAIN_OF_TRUST #endif -#ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 #elif defined(CONFIG_BSC9132QDS) @@ -76,8 +68,25 @@ */ #define CONFIG_FSL_ISBC_KEY_EXT #endif +#endif /* #ifdef CONFIG_SECURE_BOOT */ + +#ifdef CONFIG_CHAIN_OF_TRUST + +#define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB +#define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_PROG_HW_ACCEL +#define CONFIG_RSA +#define CONFIG_RSA_FREESCALE_EXP + +#ifndef CONFIG_DM +#define CONFIG_DM +#endif + +#ifndef CONFIG_FSL_CAAM +#define CONFIG_FSL_CAAM +#endif -#ifndef CONFIG_FIT_SIGNATURE /* If Boot Script is not on NOR and is required to be copied on RAM */ #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 @@ -105,10 +114,8 @@ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 #endif -#endif - -#include -#endif +#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ -#endif +#include +#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h new file mode 100644 index 0000000..45dda56 --- /dev/null +++ b/include/config_fsl_chain_trust.h @@ -0,0 +1,101 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_FSL_CHAIN_TRUST_H +#define __CONFIG_FSL_CHAIN_TRUST_H + +/* For secure boot, since ENVIRONMENT in flash/external memories is + * not verified, undef CONFIG_ENV_xxx and set default env + * (CONFIG_ENV_IS_NOWHERE) + */ +#ifdef CONFIG_SECURE_BOOT + +#undef CONFIG_ENV_IS_IN_EEPROM +#undef CONFIG_ENV_IS_IN_NAND +#undef CONFIG_ENV_IS_IN_MMC +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#undef CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_IS_NOWHERE + +#endif + +#ifdef CONFIG_CHAIN_OF_TRUST + +#ifndef CONFIG_EXTRA_ENV +#define CONFIG_EXTRA_ENV "" +#endif + +/* + * Control should not reach back to uboot after validation of images + * for secure boot flow and therefore bootscript should have + * the bootm command. If control reaches back to uboot anyhow + * after validating images, core should just spin. + */ + +/* + * Define the key hash for boot script here if public/private key pair used to + * sign bootscript are different from the SRK hash put in the fuse + * Example of defining KEY_HASH is + * #define CONFIG_BOOTSCRIPT_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + */ + +#ifdef CONFIG_BOOTSCRIPT_KEY_HASH +#define CONFIG_SECBOOT \ + "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ + "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ + "ramdisk_size=600000\';" \ + CONFIG_EXTRA_ENV \ + "esbc_validate $bs_hdraddr " \ + __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ + "source $img_addr;" \ + "esbc_halt\0" +#else +#define CONFIG_SECBOOT \ + "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ + "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ + "ramdisk_size=600000\';" \ + CONFIG_EXTRA_ENV \ + "esbc_validate $bs_hdraddr;" \ + "source $img_addr;" \ + "esbc_halt\0" +#endif + +/* For secure boot flow, default environment used will be used */ +#if defined(CONFIG_SYS_RAMBOOT) +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_COPY_ENV \ + "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ + "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \ + "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ + "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \ + "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ + "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" + +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_BS_COPY_CMD \ + "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ + "nand read $bs_ram $bs_flash $bs_size ;" +#endif /* CONFIG_RAMBOOT_NAND */ +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ + +#endif + +#ifndef CONFIG_BS_COPY_ENV +#define CONFIG_BS_COPY_ENV +#endif + +#ifndef CONFIG_BS_COPY_CMD +#define CONFIG_BS_COPY_CMD +#endif + +#define CONFIG_CHAIN_BOOT_CMD CONFIG_BS_COPY_ENV \ + CONFIG_BS_COPY_CMD \ + CONFIG_SECBOOT + +#endif +#endif diff --git a/include/config_fsl_secboot.h b/include/config_fsl_secboot.h deleted file mode 100644 index fc6788a..0000000 --- a/include/config_fsl_secboot.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_FSL_SECBOOT_H -#define __CONFIG_FSL_SECBOOT_H - -#ifdef CONFIG_SECURE_BOOT - -#ifndef CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_CMD_ESBC_VALIDATE -#endif - -#ifndef CONFIG_EXTRA_ENV -#define CONFIG_EXTRA_ENV "" -#endif - -/* - * Control should not reach back to uboot after validation of images - * for secure boot flow and therefore bootscript should have - * the bootm command. If control reaches back to uboot anyhow - * after validating images, core should just spin. - */ - -/* - * Define the key hash for boot script here if public/private key pair used to - * sign bootscript are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_BOOTSCRIPT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - */ - -#ifdef CONFIG_BOOTSCRIPT_KEY_HASH -#define CONFIG_SECBOOT \ - "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=600000\';" \ - CONFIG_EXTRA_ENV \ - "esbc_validate $bs_hdraddr " \ - __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ - "source $img_addr;" \ - "esbc_halt\0" -#else -#define CONFIG_SECBOOT \ - "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=600000\';" \ - CONFIG_EXTRA_ENV \ - "esbc_validate $bs_hdraddr;" \ - "source $img_addr;" \ - "esbc_halt\0" -#endif - -/* For secure boot flow, default environment used will be used */ -#if defined(CONFIG_SYS_RAMBOOT) -#ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BS_COPY_ENV \ - "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ - "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \ - "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ - "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \ - "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ - "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" - -#if defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_BS_COPY_CMD \ - "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ - "nand read $bs_ram $bs_flash $bs_size ;" -#endif /* CONFIG_RAMBOOT_NAND */ -#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ - -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#undef CONFIG_ENV_IS_IN_SPI_FLASH -#elif defined(CONFIG_RAMBOOT_NAND) -#undef CONFIG_ENV_IS_IN_NAND -#elif defined(CONFIG_RAMBOOT_SDCARD) -#undef CONFIG_ENV_IS_IN_MMC -#endif -#else /*CONFIG_SYS_RAMBOOT*/ -#undef CONFIG_ENV_IS_IN_FLASH -#endif - -#define CONFIG_ENV_IS_NOWHERE - -#ifndef CONFIG_BS_COPY_ENV -#define CONFIG_BS_COPY_ENV -#endif - -#ifndef CONFIG_BS_COPY_CMD -#define CONFIG_BS_COPY_CMD -#endif - -#define CONFIG_SECBOOT_CMD CONFIG_BS_COPY_ENV \ - CONFIG_BS_COPY_CMD \ - CONFIG_SECBOOT -/* - * We don't want boot delay for secure boot flow - * before autoboot starts - */ -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 0 -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT_CMD - -/* - * CONFIG_ZERO_BOOTDELAY_CHECK should not be defined for - * secure boot flow as defining this would enable a user to - * reach uboot prompt by pressing some key before start of - * autoboot - */ -#undef CONFIG_ZERO_BOOTDELAY_CHECK - -#endif -#endif -- cgit v0.10.2 From 0a6b2714adfffce6a1497bd2ed6cbf4f7b4b0236 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:25 +0530 Subject: secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8a4b0d7..0bad0c7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -218,6 +218,9 @@ struct ccsr_gur { #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 + u8 res_140[0x200-0x140]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res_210[0x300-0x210]; diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 89339fe..0a80772 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -120,6 +120,8 @@ struct ccsr_gur { u32 brrl; /* Boot release */ u8 res_0e8[0x100-0xe8]; u32 rcwsr[16]; /* Reset control word status */ +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 u8 res_140[0x200-0x140]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res_210[0x300-0x210]; diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 101b8db..fd8aba4 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1749,6 +1749,8 @@ typedef struct ccsr_gur { u32 brrl; /* Boot release */ u8 res17[24]; u32 rcwsr[16]; /* Reset control word status */ +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 @@ -2194,6 +2196,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 #endif +#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000 /* The 8544 RM says this is bit 26, but it's really bit 24 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 u8 res1[8]; diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c new file mode 100644 index 0000000..ff67bd7 --- /dev/null +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -0,0 +1,53 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#ifdef CONFIG_LS102XA +#include +#endif + +#if defined(CONFIG_MPC85xx) +#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#else +#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR +#endif + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define gur_in32(a) in_le32(a) +#else +#define gur_in32(a) in_be32(a) +#endif + +/* Check the Boot Mode. If Secure, return 1 else return 0 */ +int fsl_check_boot_mode_secure(void) +{ + uint32_t val; + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); + + val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; + if (val == ITS_MASK) + return 1; + +#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) + /* For PBL based platforms check the SB_EN bit in RCWSR */ + val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; + if (val == RCW_SB_EN_MASK) + return 1; +#endif + +#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) + /* For Non-PBL Platforms, check the Device Status register 2*/ + val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; + if (val != MPC85xx_PORDEVSR2_SBC_MASK) + return 1; + +#endif + return 0; +} -- cgit v0.10.2 From d041288586b05164c84794a5956ddc5fb8939115 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:26 +0530 Subject: secure_boot: enable chain of trust for ARM platforms Chain of Trust is enabled for ARM platforms (LS1021 and LS1043). In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 23d6b73..d97a445 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -12,6 +12,9 @@ #include #include #include +#ifdef CONFIG_CHAIN_OF_TRUST +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -241,6 +244,9 @@ int board_late_init(void) #ifdef CONFIG_SCSI_AHCI_PLAT sata_init(); #endif +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif return 0; } diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 51d2814..be114ce 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -76,5 +76,6 @@ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o ifdef CONFIG_SECURE_BOOT obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o endif +obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o endif diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index ff67bd7..ecfcc82 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -51,3 +51,20 @@ int fsl_check_boot_mode_secure(void) #endif return 0; } + +int fsl_setenv_chain_of_trust(void) +{ + /* Check Boot Mode + * If Boot Mode is Non-Secure, no changes are required + */ + if (fsl_check_boot_mode_secure() == 0) + return 0; + + /* If Boot mode is Secure, set the environment variables + * bootdelay = 0 (To disable Boot Prompt) + * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) + */ + setenv("bootdelay", "0"); + setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); + return 0; +} diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index be3358a..5f4ec9d 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "../common/sleep.h" #include "../common/qixis.h" @@ -369,6 +370,9 @@ int board_late_init(void) #ifdef CONFIG_SCSI_AHCI_PLAT ls1021a_sata_init(); #endif +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif return 0; } diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 8eaff5f..b85774c 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -30,6 +30,7 @@ #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" #endif +#include DECLARE_GLOBAL_DATA_PTR; @@ -549,6 +550,9 @@ int board_late_init(void) #ifdef CONFIG_SCSI_AHCI_PLAT ls1021a_sata_init(); #endif +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif return 0; } diff --git a/include/fsl_validate.h b/include/fsl_validate.h index ad14867..83efcf4 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -205,4 +205,6 @@ int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc, int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int fsl_check_boot_mode_secure(void); +int fsl_setenv_chain_of_trust(void); #endif -- cgit v0.10.2 From d0a6d7ce55ec40d23ad96b549d596afd8f70735c Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:27 +0530 Subject: secure_boot: enable chain of trust for PowerPC platforms Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 13a7d0f..d51616b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -27,6 +27,9 @@ #include #include #include "mp.h" +#ifdef CONFIG_CHAIN_OF_TRUST +#include +#endif #ifdef CONFIG_FSL_CAAM #include #endif @@ -1009,3 +1012,14 @@ void cpu_secondary_init_r(void) qe_reset(); #endif } + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif + + return 0; +} +#endif diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 41058d1..c45cace 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -87,6 +87,13 @@ #define CONFIG_FSL_CAAM #endif +/* fsl_setenv_chain_of_trust() must be called from + * board_late_init() + */ +#ifndef CONFIG_BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT +#endif + /* If Boot Script is not on NOR and is required to be copied on RAM */ #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 -- cgit v0.10.2 From 856b284617eea5688ccf5f4655f8d70ac5ae5fbb Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:28 +0530 Subject: secure_boot: change error handler for esbc_validate In case of error while executing esbc_validate command, SNVS transition and issue of reset is required only for secure-boot. If boot mode is non-secure, this is not required. Similarly, esbc_halt command which puts the core in Spin Loop is applicable only for Secure Boot. Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index ca7c737..dfa3e21 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -11,6 +11,11 @@ static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + if (fsl_check_boot_mode_secure() == 0) { + printf("Boot Mode is Non-Secure. Not entering spin loop.\n"); + return 0; + } + printf("Core is entering spin loop.\n"); loop: goto loop; @@ -64,6 +69,6 @@ U_BOOT_CMD( U_BOOT_CMD( esbc_halt, 1, 0, do_esbc_halt, - "Put the core in spin loop ", + "Put the core in spin loop (Secure Boot Only)", "" ); diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index de40081..8fd6dd6 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -370,6 +370,13 @@ void fsl_secboot_handle_error(int error) printf("ERROR :: %x :: %s\n", error, e->name); } + /* If Boot Mode is secure, transition the SNVS state and issue + * reset based on type of failure and ITS setting. + * If Boot mode is non-secure, return from this function. + */ + if (fsl_check_boot_mode_secure() == 0) + return; + switch (error) { case ERROR_ESBC_CLIENT_HEADER_BARKER: case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE: -- cgit v0.10.2 From 9a696f56fcabc3d7ddd120712cc3a70b085ea412 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 24 Dec 2015 15:32:37 +0530 Subject: driver: net: fsl-mc: Add version check for MC objects Check and compare version of management complex's object with the version supported by Freescale ldpaa2 ethernet driver. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index bac4610..b773e35 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -655,6 +655,26 @@ int fsl_mc_ldpaa_init(bd_t *bis) return 0; } +static int dprc_version_check(struct fsl_mc_io *mc_io, uint16_t handle) +{ + struct dprc_attributes attr; + int error; + + memset(&attr, 0, sizeof(struct dprc_attributes)); + error = dprc_get_attributes(mc_io, MC_CMD_NO_FLAGS, handle, &attr); + if (error == 0) { + if ((attr.version.major != DPRC_VER_MAJOR) || + (attr.version.minor != DPRC_VER_MINOR)) { + printf("DPRC version mismatch found %u.%u,", + attr.version.major, + attr.version.minor); + printf("supported version is %u.%u\n", + DPRC_VER_MAJOR, DPRC_VER_MINOR); + } + } + return error; +} + static int dpio_init(void) { struct qbman_swp_desc p_des; @@ -688,11 +708,18 @@ static int dpio_init(void) goto err_get_attr; } + if ((attr.version.major != DPIO_VER_MAJOR) || + (attr.version.minor != DPIO_VER_MINOR)) { + printf("DPIO version mismatch found %u.%u,", + attr.version.major, attr.version.minor); + printf("supported version is %u.%u\n", + DPIO_VER_MAJOR, DPIO_VER_MINOR); + } + dflt_dpio->dpio_id = attr.id; #ifdef DEBUG printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id); #endif - err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); if (err < 0) { printf("dpio_enable() failed %d\n", err); @@ -784,6 +811,12 @@ static int dprc_init(void) goto err_root_open; } + err = dprc_version_check(root_mc_io, root_dprc_handle); + if (err < 0) { + printf("dprc_version_check() failed: %d\n", err); + goto err_root_open; + } + cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED | DPRC_CFG_OPT_OBJ_CREATE_ALLOWED | DPRC_CFG_OPT_ALLOC_ALLOWED; @@ -906,6 +939,14 @@ static int dpbp_init(void) goto err_get_attr; } + if ((dpbp_attr.version.major != DPBP_VER_MAJOR) || + (dpbp_attr.version.minor != DPBP_VER_MINOR)) { + printf("DPBP version mismatch found %u.%u,", + dpbp_attr.version.major, dpbp_attr.version.minor); + printf("supported version is %u.%u\n", + DPBP_VER_MAJOR, DPBP_VER_MINOR); + } + dflt_dpbp->dpbp_attr.id = dpbp_attr.id; #ifdef DEBUG printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id); @@ -994,6 +1035,14 @@ static int dpni_init(void) goto err_get_attr; } + if ((dpni_attr.version.major != DPNI_VER_MAJOR) || + (dpni_attr.version.minor != DPNI_VER_MINOR)) { + printf("DPNI version mismatch found %u.%u,", + dpni_attr.version.major, dpni_attr.version.minor); + printf("supported version is %u.%u\n", + DPNI_VER_MAJOR, DPNI_VER_MINOR); + } + dflt_dpni->dpni_id = dpni_attr.id; #ifdef DEBUG printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id); diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 3857122..dd9af4e 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -599,6 +599,29 @@ static void ldpaa_dpbp_free(void) dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); } +static int ldpaa_dpmac_version_check(struct fsl_mc_io *mc_io, + struct ldpaa_eth_priv *priv) +{ + struct dpmac_attr attr; + int error; + + memset(&attr, 0, sizeof(struct dpmac_attr)); + error = dpmac_get_attributes(mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + &attr); + if (error == 0) { + if ((attr.version.major != DPMAC_VER_MAJOR) || + (attr.version.minor != DPMAC_VER_MINOR)) { + printf("DPMAC version mismatch found %u.%u,", + attr.version.major, attr.version.minor); + printf("supported version is %u.%u\n", + DPMAC_VER_MAJOR, DPMAC_VER_MINOR); + } + } + + return error; +} + static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv) { int err = 0; @@ -609,6 +632,11 @@ static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv) &priv->dpmac_handle); if (err) printf("dpmac_create() failed\n"); + + err = ldpaa_dpmac_version_check(dflt_mc_io, priv); + if (err < 0) + printf("ldpaa_dpmac_version_check() failed: %d\n", err); + return err; } -- cgit v0.10.2 From 53e353fc3e52ae8161d3977aac655f551a56a3a1 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 24 Dec 2015 15:32:49 +0530 Subject: driver: net: fsl-mc: flib changes for MC FW 9.0.0 MC firmware version 9.0.0 contains - Support of new APIs - Update in existing APIs - Change in Major and minor version of DPAA2 objects This patch contains modifications in FLIB files to support new MC firmware version. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c index eacb3c8..41bf56a 100644 --- a/drivers/net/fsl-mc/dpni.c +++ b/drivers/net/fsl-mc/dpni.c @@ -8,6 +8,26 @@ #include #include +int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg, + uint8_t *ext_cfg_buf) +{ + uint64_t *ext_params = (uint64_t *)ext_cfg_buf; + + DPNI_PREP_EXTENDED_CFG(ext_params, cfg); + + return 0; +} + +int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg, + const uint8_t *ext_cfg_buf) +{ + uint64_t *ext_params = (uint64_t *)ext_cfg_buf; + + DPNI_EXT_EXTENDED_CFG(ext_params, cfg); + + return 0; +} + int dpni_open(struct fsl_mc_io *mc_io, uint32_t cmd_flags, int dpni_id, @@ -162,6 +182,7 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR, cmd_flags, token); + DPNI_CMD_GET_ATTR(cmd, attr); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -174,6 +195,23 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, return 0; } +int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_error_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR, + cmd_flags, + token); + DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, @@ -602,3 +640,46 @@ int dpni_get_rx_flow(struct fsl_mc_io *mc_io, return 0; } + +int dpni_set_tx_conf(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + const struct dpni_tx_conf_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF, + cmd_flags, + token); + DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_get_tx_conf(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + struct dpni_tx_conf_attr *attr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF, + cmd_flags, + token); + DPNI_CMD_GET_TX_CONF(cmd, flow_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + DPNI_RSP_GET_TX_CONF(cmd, attr); + + return 0; +} diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index dd9af4e..09163a6 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -798,9 +798,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) priv->tx_flow_id = DPNI_NEW_FLOW_ID; memset(&dflt_tx_flow, 0, sizeof(dflt_tx_flow)); - dflt_tx_flow.options = DPNI_TX_FLOW_OPT_ONLY_TX_ERROR; - dflt_tx_flow.conf_err_cfg.use_default_queue = 0; - dflt_tx_flow.conf_err_cfg.errors_only = 1; + dflt_tx_flow.use_common_tx_conf_queue = 0; err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, &priv->tx_flow_id, &dflt_tx_flow); diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 92c5437..b1ad46e 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -15,7 +15,7 @@ /* DPBP Version */ #define DPBP_VER_MAJOR 2 -#define DPBP_VER_MINOR 1 +#define DPBP_VER_MINOR 2 /* Command IDs */ #define DPBP_CMDID_CLOSE 0x800 diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index 0bc0b44..d8c458f 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -9,7 +9,7 @@ /* DPIO Version */ #define DPIO_VER_MAJOR 3 -#define DPIO_VER_MINOR 1 +#define DPIO_VER_MINOR 2 /* Command IDs */ #define DPIO_CMDID_CLOSE 0x800 @@ -45,6 +45,7 @@ do { \ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\ MC_RSP_OP(cmd, 3, 0, 16, uint16_t, attr->version.major);\ MC_RSP_OP(cmd, 3, 16, 16, uint16_t, attr->version.minor);\ + MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\ } while (0) /* Data Path I/O Portal API @@ -195,6 +196,7 @@ int dpio_reset(struct fsl_mc_io *mc_io, * @channel_mode: Notification channel mode * @num_priorities: Number of priorities for the notification channel (1-8); * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' + * @qbman_version: QBMAN version */ struct dpio_attr { int id; @@ -212,6 +214,7 @@ struct dpio_attr { uint16_t qbman_portal_id; enum dpio_channel_mode channel_mode; uint8_t num_priorities; + uint32_t qbman_version; }; /** diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 24f0b48..296f3ae 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -12,7 +12,7 @@ /* DPMAC Version */ #define DPMAC_VER_MAJOR 3 -#define DPMAC_VER_MINOR 1 +#define DPMAC_VER_MINOR 2 /* Command IDs */ #define DPMAC_CMDID_CLOSE 0x800 diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h index b0a87a9..023b5bb 100644 --- a/include/fsl-mc/fsl_dpmng.h +++ b/include/fsl-mc/fsl_dpmng.h @@ -14,7 +14,7 @@ struct fsl_mc_io; /** * Management Complex firmware version information */ -#define MC_VER_MAJOR 8 +#define MC_VER_MAJOR 9 #define MC_VER_MINOR 0 /** diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index 140a009..f396dc3 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -7,8 +7,8 @@ #define _FSL_DPNI_H /* DPNI Version */ -#define DPNI_VER_MAJOR 5 -#define DPNI_VER_MINOR 1 +#define DPNI_VER_MAJOR 6 +#define DPNI_VER_MINOR 0 /* Command IDs */ #define DPNI_CMDID_OPEN 0x801 @@ -28,6 +28,7 @@ #define DPNI_CMDID_SET_TX_BUFFER_LAYOUT 0x204 #define DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT 0x205 #define DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT 0x206 +#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B #define DPNI_CMDID_GET_QDID 0x210 #define DPNI_CMDID_GET_TX_DATA_OFFSET 0x212 @@ -45,11 +46,73 @@ #define DPNI_CMDID_GET_TX_FLOW 0x237 #define DPNI_CMDID_SET_RX_FLOW 0x238 #define DPNI_CMDID_GET_RX_FLOW 0x239 +#define DPNI_CMDID_SET_TX_CONF 0x257 +#define DPNI_CMDID_GET_TX_CONF 0x258 /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_OPEN(cmd, dpni_id) \ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) +#define DPNI_PREP_EXTENDED_CFG(ext, cfg) \ +do { \ + MC_PREP_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \ + MC_PREP_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \ + MC_PREP_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \ + MC_PREP_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \ + MC_PREP_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \ + MC_PREP_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \ + MC_PREP_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \ + MC_PREP_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \ + MC_PREP_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \ + MC_PREP_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \ + MC_PREP_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \ + MC_PREP_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \ + MC_PREP_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \ + MC_PREP_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \ + MC_PREP_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \ + MC_PREP_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \ + MC_PREP_OP(ext, 4, 0, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv4); \ + MC_PREP_OP(ext, 4, 16, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv6); \ + MC_PREP_OP(ext, 4, 32, 16, uint16_t, \ + cfg->ipr_cfg.max_reass_frm_size); \ + MC_PREP_OP(ext, 5, 0, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv4); \ + MC_PREP_OP(ext, 5, 16, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv6); \ +} while (0) + +#define DPNI_EXT_EXTENDED_CFG(ext, cfg) \ +do { \ + MC_EXT_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \ + MC_EXT_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \ + MC_EXT_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \ + MC_EXT_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \ + MC_EXT_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \ + MC_EXT_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \ + MC_EXT_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \ + MC_EXT_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \ + MC_EXT_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \ + MC_EXT_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \ + MC_EXT_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \ + MC_EXT_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \ + MC_EXT_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \ + MC_EXT_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \ + MC_EXT_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \ + MC_EXT_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \ + MC_EXT_OP(ext, 4, 0, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv4); \ + MC_EXT_OP(ext, 4, 16, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv6); \ + MC_EXT_OP(ext, 4, 32, 16, uint16_t, \ + cfg->ipr_cfg.max_reass_frm_size); \ + MC_EXT_OP(ext, 5, 0, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv4); \ + MC_EXT_OP(ext, 5, 16, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv6); \ +} while (0) + /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_CREATE(cmd, cfg) \ do { \ @@ -69,32 +132,23 @@ do { \ MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \ MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \ MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \ - MC_CMD_OP(cmd, 3, 0, 8, uint8_t, cfg->adv.max_dist_per_tc[0]); \ - MC_CMD_OP(cmd, 3, 8, 8, uint8_t, cfg->adv.max_dist_per_tc[1]); \ - MC_CMD_OP(cmd, 3, 16, 8, uint8_t, cfg->adv.max_dist_per_tc[2]); \ - MC_CMD_OP(cmd, 3, 24, 8, uint8_t, cfg->adv.max_dist_per_tc[3]); \ - MC_CMD_OP(cmd, 3, 32, 8, uint8_t, cfg->adv.max_dist_per_tc[4]); \ - MC_CMD_OP(cmd, 3, 40, 8, uint8_t, cfg->adv.max_dist_per_tc[5]); \ - MC_CMD_OP(cmd, 3, 48, 8, uint8_t, cfg->adv.max_dist_per_tc[6]); \ - MC_CMD_OP(cmd, 3, 56, 8, uint8_t, cfg->adv.max_dist_per_tc[7]); \ - MC_CMD_OP(cmd, 4, 0, 16, uint16_t, \ - cfg->adv.ipr_cfg.max_reass_frm_size); \ - MC_CMD_OP(cmd, 4, 16, 16, uint16_t, \ - cfg->adv.ipr_cfg.min_frag_size_ipv4); \ - MC_CMD_OP(cmd, 4, 32, 16, uint16_t, \ - cfg->adv.ipr_cfg.min_frag_size_ipv6); \ MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \ MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \ - MC_CMD_OP(cmd, 5, 0, 16, uint16_t, \ - cfg->adv.ipr_cfg.max_open_frames_ipv4); \ - MC_CMD_OP(cmd, 5, 16, 16, uint16_t, \ - cfg->adv.ipr_cfg.max_open_frames_ipv6); \ + MC_CMD_OP(cmd, 5, 0, 64, uint64_t, cfg->adv.ext_cfg_iova); \ } while (0) /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_POOLS(cmd, cfg) \ do { \ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \ + MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \ + MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \ + MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \ + MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \ + MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \ + MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \ + MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \ + MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\ MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \ @@ -114,6 +168,10 @@ do { \ } while (0) /* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_GET_ATTR(cmd, attr) \ + MC_CMD_OP(cmd, 6, 0, 64, uint64_t, attr->ext_cfg_iova) + +/* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_ATTR(cmd, attr) \ do { \ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ @@ -127,31 +185,21 @@ do { \ MC_RSP_OP(cmd, 2, 24, 8, uint8_t, attr->max_qos_entries); \ MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->max_qos_key_size); \ MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->max_dist_key_size); \ - MC_RSP_OP(cmd, 3, 0, 8, uint8_t, attr->max_dist_per_tc[0]); \ - MC_RSP_OP(cmd, 3, 8, 8, uint8_t, attr->max_dist_per_tc[1]); \ - MC_RSP_OP(cmd, 3, 16, 8, uint8_t, attr->max_dist_per_tc[2]); \ - MC_RSP_OP(cmd, 3, 24, 8, uint8_t, attr->max_dist_per_tc[3]); \ - MC_RSP_OP(cmd, 3, 32, 8, uint8_t, attr->max_dist_per_tc[4]); \ - MC_RSP_OP(cmd, 3, 40, 8, uint8_t, attr->max_dist_per_tc[5]); \ - MC_RSP_OP(cmd, 3, 48, 8, uint8_t, attr->max_dist_per_tc[6]); \ - MC_RSP_OP(cmd, 3, 56, 8, uint8_t, attr->max_dist_per_tc[7]); \ - MC_RSP_OP(cmd, 4, 0, 16, uint16_t, \ - attr->ipr_cfg.max_reass_frm_size); \ - MC_RSP_OP(cmd, 4, 16, 16, uint16_t, \ - attr->ipr_cfg.min_frag_size_ipv4); \ - MC_RSP_OP(cmd, 4, 32, 16, uint16_t, \ - attr->ipr_cfg.min_frag_size_ipv6);\ - MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \ - MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \ - MC_RSP_OP(cmd, 5, 0, 16, uint16_t, \ - attr->ipr_cfg.max_open_frames_ipv4); \ - MC_RSP_OP(cmd, 5, 16, 16, uint16_t, \ - attr->ipr_cfg.max_open_frames_ipv6); \ + MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \ + MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \ MC_RSP_OP(cmd, 5, 32, 16, uint16_t, attr->version.major);\ MC_RSP_OP(cmd, 5, 48, 16, uint16_t, attr->version.minor);\ } while (0) /* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \ + MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \ + MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout) \ do { \ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ @@ -313,23 +361,11 @@ do { \ /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_TX_FLOW(cmd, flow_id, cfg) \ do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, \ - cfg->conf_err_cfg.queue_cfg.dest_cfg.dest_id);\ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, \ - cfg->conf_err_cfg.queue_cfg.dest_cfg.priority);\ - MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \ - cfg->conf_err_cfg.queue_cfg.dest_cfg.dest_type);\ - MC_CMD_OP(cmd, 0, 42, 1, int, cfg->conf_err_cfg.errors_only);\ MC_CMD_OP(cmd, 0, 43, 1, int, cfg->l3_chksum_gen);\ MC_CMD_OP(cmd, 0, 44, 1, int, cfg->l4_chksum_gen);\ - MC_CMD_OP(cmd, 0, 45, 1, int, \ - cfg->conf_err_cfg.use_default_queue);\ + MC_CMD_OP(cmd, 0, 45, 1, int, cfg->use_common_tx_conf_queue);\ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id);\ - MC_CMD_OP(cmd, 1, 0, 64, uint64_t, \ - cfg->conf_err_cfg.queue_cfg.user_ctx);\ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\ - MC_CMD_OP(cmd, 2, 32, 32, uint32_t, \ - cfg->conf_err_cfg.queue_cfg.options);\ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -343,21 +379,9 @@ do { \ /* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_TX_FLOW(cmd, attr) \ do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, \ - attr->conf_err_attr.queue_attr.dest_cfg.dest_id);\ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \ - attr->conf_err_attr.queue_attr.dest_cfg.priority);\ - MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \ - attr->conf_err_attr.queue_attr.dest_cfg.dest_type);\ - MC_RSP_OP(cmd, 0, 42, 1, int, attr->conf_err_attr.errors_only);\ MC_RSP_OP(cmd, 0, 43, 1, int, attr->l3_chksum_gen);\ MC_RSP_OP(cmd, 0, 44, 1, int, attr->l4_chksum_gen);\ - MC_RSP_OP(cmd, 0, 45, 1, int, \ - attr->conf_err_attr.use_default_queue);\ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, \ - attr->conf_err_attr.queue_attr.user_ctx);\ - MC_RSP_OP(cmd, 2, 32, 32, uint32_t, \ - attr->conf_err_attr.queue_attr.fqid);\ + MC_RSP_OP(cmd, 0, 45, 1, int, attr->use_common_tx_conf_queue);\ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -370,7 +394,7 @@ do { \ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \ MC_CMD_OP(cmd, 2, 16, 8, uint8_t, tc_id); \ - MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \ + MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \ MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \ MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ cfg->flc_cfg.frame_data_size);\ @@ -378,6 +402,7 @@ do { \ cfg->flc_cfg.flow_context_size);\ MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\ + MC_CMD_OP(cmd, 5, 0, 32, uint32_t, cfg->tail_drop_threshold); \ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -393,8 +418,9 @@ do { \ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\ MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type); \ - MC_CMD_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\ + MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \ + MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \ MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \ MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \ MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ @@ -405,6 +431,58 @@ do { \ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\ } while (0) +#define DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->queue_cfg.dest_cfg.priority); \ + MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \ + cfg->queue_cfg.dest_cfg.dest_type); \ + MC_CMD_OP(cmd, 0, 42, 1, int, cfg->errors_only); \ + MC_CMD_OP(cmd, 0, 46, 1, int, cfg->queue_cfg.order_preservation_en); \ + MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ + MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->queue_cfg.user_ctx); \ + MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->queue_cfg.options); \ + MC_CMD_OP(cmd, 2, 32, 32, int, cfg->queue_cfg.dest_cfg.dest_id); \ + MC_CMD_OP(cmd, 3, 0, 32, uint32_t, \ + cfg->queue_cfg.tail_drop_threshold); \ + MC_CMD_OP(cmd, 4, 0, 4, enum dpni_flc_type, \ + cfg->queue_cfg.flc_cfg.flc_type); \ + MC_CMD_OP(cmd, 4, 4, 4, enum dpni_stash_size, \ + cfg->queue_cfg.flc_cfg.frame_data_size); \ + MC_CMD_OP(cmd, 4, 8, 4, enum dpni_stash_size, \ + cfg->queue_cfg.flc_cfg.flow_context_size); \ + MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->queue_cfg.flc_cfg.options); \ + MC_CMD_OP(cmd, 5, 0, 64, uint64_t, \ + cfg->queue_cfg.flc_cfg.flow_context); \ +} while (0) + +#define DPNI_CMD_GET_TX_CONF(cmd, flow_id) \ + MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id) + +#define DPNI_RSP_GET_TX_CONF(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \ + attr->queue_attr.dest_cfg.priority); \ + MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \ + attr->queue_attr.dest_cfg.dest_type); \ + MC_RSP_OP(cmd, 0, 42, 1, int, attr->errors_only); \ + MC_RSP_OP(cmd, 0, 46, 1, int, \ + attr->queue_attr.order_preservation_en); \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->queue_attr.user_ctx); \ + MC_RSP_OP(cmd, 2, 32, 32, int, attr->queue_attr.dest_cfg.dest_id); \ + MC_RSP_OP(cmd, 3, 0, 32, uint32_t, \ + attr->queue_attr.tail_drop_threshold); \ + MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->queue_attr.fqid); \ + MC_RSP_OP(cmd, 4, 0, 4, enum dpni_flc_type, \ + attr->queue_attr.flc_cfg.flc_type); \ + MC_RSP_OP(cmd, 4, 4, 4, enum dpni_stash_size, \ + attr->queue_attr.flc_cfg.frame_data_size); \ + MC_RSP_OP(cmd, 4, 8, 4, enum dpni_stash_size, \ + attr->queue_attr.flc_cfg.flow_context_size); \ + MC_RSP_OP(cmd, 4, 32, 32, uint32_t, attr->queue_attr.flc_cfg.options); \ + MC_RSP_OP(cmd, 5, 0, 64, uint64_t, \ + attr->queue_attr.flc_cfg.flow_context); \ +} while (0) + enum net_prot { NET_PROT_NONE = 0, NET_PROT_PAYLOAD, @@ -479,6 +557,8 @@ struct fsl_mc_io; #define DPNI_ALL_TC_FLOWS (uint16_t)(-1) /* Generate new flow ID; see dpni_set_tx_flow() */ #define DPNI_NEW_FLOW_ID (uint16_t)(-1) +/* use for common tx-conf queue; see dpni_set_tx_conf_() */ +#define DPNI_COMMON_TX_CONF (uint16_t)(-1) /** * dpni_open() - Open a control session for the specified object @@ -565,22 +645,56 @@ int dpni_close(struct fsl_mc_io *mc_io, #define DPNI_OPT_FS_MASK_SUPPORT 0x00040000 /** - * struct dpni_ipr_cfg - Structure representing IP reassembly configuration - * @max_reass_frm_size: Maximum size of the reassembled frame - * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments - * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments - * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly process - * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly process + * struct dpni_extended_cfg - Structure representing extended DPNI configuration + * @tc_cfg: TCs configuration + * @ipr_cfg: IP reassembly configuration */ -struct dpni_ipr_cfg { - uint16_t max_reass_frm_size; - uint16_t min_frag_size_ipv4; - uint16_t min_frag_size_ipv6; - uint16_t max_open_frames_ipv4; - uint16_t max_open_frames_ipv6; +struct dpni_extended_cfg { + /** + * struct tc_cfg - TC configuration + * @max_dist: Maximum distribution size for Rx traffic class; + * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96, + * 112,128,192,224,256,384,448,512,768,896,1024; + * value '0' will be treated as '1'. + * other unsupported values will be round down to the nearest + * supported value. + * @max_fs_entries: Maximum FS entries for Rx traffic class; + * '0' means no support for this TC; + */ + struct { + uint16_t max_dist; + uint16_t max_fs_entries; + } tc_cfg[DPNI_MAX_TC]; + /** + * struct ipr_cfg - Structure representing IP reassembly configuration + * @max_reass_frm_size: Maximum size of the reassembled frame + * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments + * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments + * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly + * process + * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly + * process + */ + struct { + uint16_t max_reass_frm_size; + uint16_t min_frag_size_ipv4; + uint16_t min_frag_size_ipv6; + uint16_t max_open_frames_ipv4; + uint16_t max_open_frames_ipv6; + } ipr_cfg; }; /** + * dpni_prepare_extended_cfg() - function prepare extended parameters + * @cfg: extended structure + * @ext_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA + * + * This function has to be called before dpni_create() + */ +int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg, + uint8_t *ext_cfg_buf); + +/** * struct dpni_cfg - Structure representing DPNI configuration * @mac_addr: Primary MAC address * @adv: Advanced parameters; default is all zeros; @@ -599,11 +713,6 @@ struct dpni_cfg { * '0' will be treated as '1' * @max_tcs: Maximum number of traffic classes (for both Tx and Rx); * '0' will e treated as '1' - * @max_dist_per_tc: Maximum distribution size per Rx traffic class; - * Must be set to the required value minus 1; - * i.e. 0->1, 1->2, ... ,255->256; - * Non-power-of-2 values are rounded up to the next - * power-of-2 value as hardware demands it * @max_unicast_filters: Maximum number of unicast filters; * '0' is treated as '16' * @max_multicast_filters: Maximum number of multicast filters; @@ -619,16 +728,17 @@ struct dpni_cfg { * should be between '0' and max_tcs * @max_congestion_ctrl: Maximum number of congestion control groups * (CGs); covers early drop and congestion notification - * requirements for traffic classes; - * should be between '0' and max_tcs - * @ipr_cfg: IP reassembly configuration + * requirements; + * should be between '0' and ('max_tcs' + 'max_senders') + * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory + * filled with the extended configuration by calling + * dpni_prepare_extended_cfg() */ struct { uint32_t options; enum net_prot start_hdr; uint8_t max_senders; uint8_t max_tcs; - uint8_t max_dist_per_tc[DPNI_MAX_TC]; uint8_t max_unicast_filters; uint8_t max_multicast_filters; uint8_t max_vlan_filters; @@ -637,7 +747,7 @@ struct dpni_cfg { uint8_t max_dist_key_size; uint8_t max_policers; uint8_t max_congestion_ctrl; - struct dpni_ipr_cfg ipr_cfg; + uint64_t ext_cfg_iova; } adv; }; @@ -765,8 +875,6 @@ int dpni_reset(struct fsl_mc_io *mc_io, * @max_senders: Maximum number of different senders; used as the number * of dedicated Tx flows; * @max_tcs: Maximum number of traffic classes (for both Tx and Rx) - * @max_dist_per_tc: Maximum distribution size per Rx traffic class; - * Set to the required value minus 1 * @max_unicast_filters: Maximum number of unicast filters * @max_multicast_filters: Maximum number of multicast filters * @max_vlan_filters: Maximum number of VLAN filters @@ -775,7 +883,8 @@ int dpni_reset(struct fsl_mc_io *mc_io, * @max_dist_key_size: Maximum key size for the distribution look-up * @max_policers: Maximum number of policers; * @max_congestion_ctrl: Maximum number of congestion control groups (CGs); - * @ipr_cfg: IP reassembly configuration + * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory; + * call dpni_extract_extended_cfg() to extract the extended configuration */ struct dpni_attr { int id; @@ -792,7 +901,6 @@ struct dpni_attr { uint32_t options; uint8_t max_senders; uint8_t max_tcs; - uint8_t max_dist_per_tc[DPNI_MAX_TC]; uint8_t max_unicast_filters; uint8_t max_multicast_filters; uint8_t max_vlan_filters; @@ -801,7 +909,7 @@ struct dpni_attr { uint8_t max_dist_key_size; uint8_t max_policers; uint8_t max_congestion_ctrl; - struct dpni_ipr_cfg ipr_cfg; + uint64_t ext_cfg_iova; }; /** @@ -809,7 +917,7 @@ struct dpni_attr { * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object - * @attr: Returned object's attributes + * @attr: Object's attributes * * Return: '0' on Success; Error code otherwise. */ @@ -818,6 +926,87 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, uint16_t token, struct dpni_attr *attr); +/** + * dpni_extract_extended_cfg() - extract the extended parameters + * @cfg: extended structure + * @ext_cfg_buf: 256 bytes of DMA-able memory + * + * This function has to be called after dpni_get_attributes() + */ +int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg, + const uint8_t *ext_cfg_buf); + +/** + * DPNI errors + */ + +/** + * Extract out of frame header error + */ +#define DPNI_ERROR_EOFHE 0x00020000 +/** + * Frame length error + */ +#define DPNI_ERROR_FLE 0x00002000 +/** + * Frame physical error + */ +#define DPNI_ERROR_FPE 0x00001000 +/** + * Parsing header error + */ +#define DPNI_ERROR_PHE 0x00000020 +/** + * Parser L3 checksum error + */ +#define DPNI_ERROR_L3CE 0x00000004 +/** + * Parser L3 checksum error + */ +#define DPNI_ERROR_L4CE 0x00000001 + +/** + * enum dpni_error_action - Defines DPNI behavior for errors + * @DPNI_ERROR_ACTION_DISCARD: Discard the frame + * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow + * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue + */ +enum dpni_error_action { + DPNI_ERROR_ACTION_DISCARD = 0, + DPNI_ERROR_ACTION_CONTINUE = 1, + DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2 +}; + +/** + * struct dpni_error_cfg - Structure representing DPNI errors treatment + * @errors: Errors mask; use 'DPNI_ERROR__ + * @error_action: The desired action for the errors mask + * @set_frame_annotation: Set to '1' to mark the errors in frame annotation + * status (FAS); relevant only for the non-discard action + */ +struct dpni_error_cfg { + uint32_t errors; + enum dpni_error_action error_action; + int set_frame_annotation; +}; + +/** + * dpni_set_errors_behavior() - Set errors behavior + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Errors configuration + * + * this function may be called numerous times with different + * error masks + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_error_cfg *cfg); + /* DPNI buffer layout modification options */ /* Select to modify the time-stamp setting */ @@ -1254,6 +1443,8 @@ struct dpni_flc_cfg { #define DPNI_QUEUE_OPT_FLC 0x00000004 /* Select to modify the queue's order preservation */ #define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008 +/* Select to modify the queue's tail-drop threshold */ +#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010 /** * struct dpni_queue_cfg - Structure representing queue configuration @@ -1272,6 +1463,10 @@ struct dpni_flc_cfg { * @order_preservation_en: enable/disable order preservation; * valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained * in 'options' + * @tail_drop_threshold: set the queue's tail drop threshold in bytes; + * '0' value disable the threshold; maximum value is 0xE000000; + * valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained + * in 'options' */ struct dpni_queue_cfg { uint32_t options; @@ -1279,6 +1474,7 @@ struct dpni_queue_cfg { struct dpni_dest_cfg dest_cfg; struct dpni_flc_cfg flc_cfg; int order_preservation_en; + uint32_t tail_drop_threshold; }; /** @@ -1288,6 +1484,7 @@ struct dpni_queue_cfg { * @dest_cfg: Queue destination configuration * @flc_cfg: Flow context configuration * @order_preservation_en: enable/disable order preservation + * @tail_drop_threshold: queue's tail drop threshold in bytes; * @fqid: Virtual fqid value to be used for dequeue operations */ struct dpni_queue_attr { @@ -1295,6 +1492,7 @@ struct dpni_queue_attr { struct dpni_dest_cfg dest_cfg; struct dpni_flc_cfg flc_cfg; int order_preservation_en; + uint32_t tail_drop_threshold; uint32_t fqid; }; @@ -1302,10 +1500,6 @@ struct dpni_queue_attr { /* Select to modify the settings for dedicate Tx confirmation/error */ #define DPNI_TX_FLOW_OPT_TX_CONF_ERROR 0x00000001 -/*!< Select to modify the Tx confirmation and/or error setting */ -#define DPNI_TX_FLOW_OPT_ONLY_TX_ERROR 0x00000002 -/*!< Select to modify the queue configuration */ -#define DPNI_TX_FLOW_OPT_QUEUE 0x00000004 /*!< Select to modify the L3 checksum generation setting */ #define DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN 0x00000010 /*!< Select to modify the L4 checksum generation setting */ @@ -1314,41 +1508,22 @@ struct dpni_queue_attr { /** * struct dpni_tx_flow_cfg - Structure representing Tx flow configuration * @options: Flags representing the suggested modifications to the Tx flow; - * Use any combination 'DPNI_TX_FLOW_OPT_' flags - * @conf_err_cfg: Tx confirmation and error configuration; these settings are - * ignored if 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' was set at - * DPNI creation + * Use any combination 'DPNI_TX_FLOW_OPT_' flags + * @use_common_tx_conf_queue: Set to '1' to use the common (default) Tx + * confirmation and error queue; Set to '0' to use the private + * Tx confirmation and error queue; valid only if + * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' wasn't set at DPNI creation + * and 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in 'options' * @l3_chksum_gen: Set to '1' to enable L3 checksum generation; '0' to disable; - * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in - * 'options' + * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in 'options' * @l4_chksum_gen: Set to '1' to enable L4 checksum generation; '0' to disable; - * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in - * 'options' + * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in 'options' */ struct dpni_tx_flow_cfg { - uint32_t options; - /** - * struct cnf_err_cfg - Tx confirmation and error configuration - * @use_default_queue: Set to '1' to use the common (default) Tx - * confirmation and error queue; Set to '0' to use the - * private Tx confirmation and error queue; valid only if - * 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in - * 'options' - * @errors_only: Set to '1' to report back only error frames; - * Set to '0' to confirm transmission/error for all - * transmitted frames; - * valid only if 'DPNI_TX_FLOW_OPT_ONLY_TX_ERROR' is - * contained in 'options' and 'use_default_queue = 0'; - * @queue_cfg: Queue configuration; valid only if - * 'DPNI_TX_FLOW_OPT_QUEUE' is contained in 'options' - */ - struct { - int use_default_queue; - int errors_only; - struct dpni_queue_cfg queue_cfg; - } conf_err_cfg; - int l3_chksum_gen; - int l4_chksum_gen; + uint32_t options; + int use_common_tx_conf_queue; + int l3_chksum_gen; + int l4_chksum_gen; }; /** @@ -1357,10 +1532,9 @@ struct dpni_tx_flow_cfg { * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object * @flow_id: Provides (or returns) the sender's flow ID; - * for each new sender set (*flow_id) to - * 'DPNI_NEW_FLOW_ID' to generate a new flow_id; - * this ID should be used as the QDBIN argument - * in enqueue operations + * for each new sender set (*flow_id) to 'DPNI_NEW_FLOW_ID' to generate + * a new flow_id; this ID should be used as the QDBIN argument + * in enqueue operations * @cfg: Tx flow configuration * * Return: '0' on Success; Error code otherwise. @@ -1373,28 +1547,15 @@ int dpni_set_tx_flow(struct fsl_mc_io *mc_io, /** * struct dpni_tx_flow_attr - Structure representing Tx flow attributes - * @conf_err_attr: Tx confirmation and error attributes + * @use_common_tx_conf_queue: '1' if using common (default) Tx confirmation and + * error queue; '0' if using private Tx confirmation and error queue * @l3_chksum_gen: '1' if L3 checksum generation is enabled; '0' if disabled * @l4_chksum_gen: '1' if L4 checksum generation is enabled; '0' if disabled */ struct dpni_tx_flow_attr { - /** - * struct conf_err_attr - Tx confirmation and error attributes - * @use_default_queue: '1' if using common (default) Tx confirmation and - * error queue; - * '0' if using private Tx confirmation and error - * queue - * @errors_only: '1' if only error frames are reported back; '0' if all - * transmitted frames are confirmed - * @queue_attr: Queue attributes - */ - struct { - int use_default_queue; - int errors_only; - struct dpni_queue_attr queue_attr; - } conf_err_attr; - int l3_chksum_gen; - int l4_chksum_gen; + int use_common_tx_conf_queue; + int l3_chksum_gen; + int l4_chksum_gen; }; /** @@ -1403,7 +1564,7 @@ struct dpni_tx_flow_attr { * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object * @flow_id: The sender's flow ID, as returned by the - * dpni_set_tx_flow() function + * dpni_set_tx_flow() function * @attr: Returned Tx flow attributes * * Return: '0' on Success; Error code otherwise. @@ -1415,6 +1576,76 @@ int dpni_get_tx_flow(struct fsl_mc_io *mc_io, struct dpni_tx_flow_attr *attr); /** + * struct dpni_tx_conf_cfg - Structure representing Tx conf configuration + * @errors_only: Set to '1' to report back only error frames; + * Set to '0' to confirm transmission/error for all transmitted frames; + * @queue_cfg: Queue configuration + */ +struct dpni_tx_conf_cfg { + int errors_only; + struct dpni_queue_cfg queue_cfg; +}; + +/** + * dpni_set_tx_conf() - Set Tx confirmation and error queue configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @flow_id: The sender's flow ID, as returned by the + * dpni_set_tx_flow() function; + * use 'DPNI_COMMON_TX_CONF' for common tx-conf + * @cfg: Queue configuration + * + * If either 'DPNI_OPT_TX_CONF_DISABLED' or + * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, + * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; + * i.e. only serve the common tx-conf-err queue; + * if 'DPNI_OPT_TX_CONF_DISABLED' was selected, only error frames are reported + * back - successfully transmitted frames are not confirmed. Otherwise, all + * transmitted frames are sent for confirmation. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_tx_conf(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + const struct dpni_tx_conf_cfg *cfg); + +/** + * struct dpni_tx_conf_attr - Structure representing Tx conf attributes + * @errors_only: '1' if only error frames are reported back; '0' if all + * transmitted frames are confirmed + * @queue_attr: Queue attributes + */ +struct dpni_tx_conf_attr { + int errors_only; + struct dpni_queue_attr queue_attr; +}; + +/** + * dpni_get_tx_conf() - Get Tx confirmation and error queue attributes + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @flow_id: The sender's flow ID, as returned by the + * dpni_set_tx_flow() function; + * use 'DPNI_COMMON_TX_CONF' for common tx-conf + * @attr: Returned tx-conf attributes + * + * If either 'DPNI_OPT_TX_CONF_DISABLED' or + * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, + * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; + * i.e. only serve the common tx-conf-err queue; + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_tx_conf(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + struct dpni_tx_conf_attr *attr); +/** * dpni_set_rx_flow() - Set Rx flow configuration * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index a87179d..535c789 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -11,7 +11,7 @@ /* DPRC Version */ #define DPRC_VER_MAJOR 5 -#define DPRC_VER_MINOR 0 +#define DPRC_VER_MINOR 1 /* Command IDs */ #define DPRC_CMDID_CLOSE 0x800 @@ -110,6 +110,74 @@ do { \ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ + MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ + MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ + MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ + MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ + MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ + MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ + MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ + MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ + MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ + MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ + MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ + MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ + MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ + MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ + MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ + MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ + MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ + MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ + MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ + MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ + MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ + MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ + MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ + MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ + MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ + MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ + MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ + MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ + MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ + MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ + MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ + MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ + MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, obj_id);\ + MC_CMD_OP(cmd, 1, 0, 8, char, obj_type[0]);\ + MC_CMD_OP(cmd, 1, 8, 8, char, obj_type[1]);\ + MC_CMD_OP(cmd, 1, 16, 8, char, obj_type[2]);\ + MC_CMD_OP(cmd, 1, 24, 8, char, obj_type[3]);\ + MC_CMD_OP(cmd, 1, 32, 8, char, obj_type[4]);\ + MC_CMD_OP(cmd, 1, 40, 8, char, obj_type[5]);\ + MC_CMD_OP(cmd, 1, 48, 8, char, obj_type[6]);\ + MC_CMD_OP(cmd, 1, 56, 8, char, obj_type[7]);\ + MC_CMD_OP(cmd, 2, 0, 8, char, obj_type[8]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, obj_type[9]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, obj_type[10]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, obj_type[11]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, obj_type[12]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, obj_type[13]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, obj_type[14]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, obj_type[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ + MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ + MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ + MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ + MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ + MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ + MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ + MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ @@ -480,14 +548,13 @@ int dprc_close(struct fsl_mc_io *mc_io, */ #define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008 -/* IOMMU bypass - indicates whether objects of this container are permitted - * to bypass the IOMMU. - */ -#define DPRC_CFG_OPT_IOMMU_BYPASS 0x00000010 -/* AIOP - Indicates that container belongs to AIOP. */ +/* AIOP - Indicates that container belongs to AIOP. */ #define DPRC_CFG_OPT_AIOP 0x00000020 +/* IRQ Config - Indicates that the container allowed to configure its IRQs.*/ +#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED 0x00000040 + /** * struct dprc_cfg - Container configuration options * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free @@ -637,6 +704,14 @@ int dprc_get_obj_count(struct fsl_mc_io *mc_io, #define DPRC_OBJ_STATE_PLUGGED 0x00000002 /** + * Shareability flag - Object flag indicating no memory shareability. + * the object generates memory accesses that are non coherent with other + * masters; + * user is responsible for proper memory handling through IOMMU configuration. + */ +#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 + +/** * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj() * @type: Type of object: NULL terminated string * @id: ID of logical object resource @@ -647,6 +722,7 @@ int dprc_get_obj_count(struct fsl_mc_io *mc_io, * @region_count: Number of mappable regions supported by the object * @state: Object state: combination of DPRC_OBJ_STATE_ states * @label: Object label + * @flags: Object's flags */ struct dprc_obj_desc { char type[16]; @@ -658,6 +734,7 @@ struct dprc_obj_desc { uint8_t region_count; uint32_t state; char label[16]; + uint16_t flags; }; /** @@ -859,7 +936,10 @@ int dprc_disconnect(struct fsl_mc_io *mc_io, * @token: Token of DPRC object * @endpoint1: Endpoint 1 configuration parameters * @endpoint2: Returned endpoint 2 configuration parameters -* @state: Returned link state: 1 - link is up, 0 - link is down +* @state: Returned link state: +* 1 - link is up; +* 0 - link is down; +* -1 - no connection (endpoint2 information is irrelevant) * * Return: '0' on Success; -ENAVAIL if connection does not exist. */ diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index 7f87d4e..f3d1498 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -68,8 +68,11 @@ enum mc_cmd_status { #define MC_CMD_HDR_READ_TOKEN(_hdr) \ ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S)) +#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ + ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg))) + #define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ - ((_ext)[_param] |= mc_enc((_offset), (_width), _arg)) + (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width))) #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) -- cgit v0.10.2 From 879a59ac902f862daf974dcab1726b9b515e278e Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 24 Dec 2015 15:33:01 +0530 Subject: driver: net: fsl-mc: Prepare extended cfg for DPNI create Management Complex FW 9.0 puts a new requirement to prepare extended parameters which should be provided as input in dpni_create. extended parameters includes traffic class and IP reassembly configurations. So prepare extended parameters with default "0" as input for dpni_create. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index b773e35..a45a30d 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1004,6 +1004,8 @@ static int dpni_init(void) { int err; struct dpni_attr dpni_attr; + uint8_t ext_cfg_buf[256] = {0}; + struct dpni_extended_cfg dpni_extended_cfg; struct dpni_cfg dpni_cfg; dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj)); @@ -1013,10 +1015,19 @@ static int dpni_init(void) goto err_malloc; } + memset(&dpni_extended_cfg, 0, sizeof(dpni_extended_cfg)); + err = dpni_prepare_extended_cfg(&dpni_extended_cfg, &ext_cfg_buf[0]); + if (err < 0) { + err = -ENODEV; + printf("dpni_prepare_extended_cfg() failed: %d\n", err); + goto err_prepare_extended_cfg; + } + memset(&dpni_cfg, 0, sizeof(dpni_cfg)); dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER | DPNI_OPT_MULTICAST_FILTER; + dpni_cfg.adv.ext_cfg_iova = (uint64_t)&ext_cfg_buf[0]; err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpni_cfg, &dflt_dpni->dpni_handle); @@ -1057,11 +1068,12 @@ static int dpni_init(void) return 0; err_close: - free(dflt_dpni); err_get_attr: dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); err_create: +err_prepare_extended_cfg: + free(dflt_dpni); err_malloc: return err; } -- cgit v0.10.2 From 6073548a0be534c8ca52061a0d727bf156a1a816 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 24 Dec 2015 15:33:13 +0530 Subject: driver: net: ldpaa: Report back only error frames for tx Management Complex FW 9.0 puts a new requirement to provide Tx confirmation and error queue configuration by calling dpni_set_tx_conf API. Configure report of only error frames for a tx frame. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 09163a6..5138e78 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -783,6 +783,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) { struct dpni_pools_cfg pools_params; struct dpni_tx_flow_cfg dflt_tx_flow; + struct dpni_tx_conf_cfg tx_conf_cfg; int err = 0; pools_params.num_dpbp = 1; @@ -807,6 +808,17 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) return err; } + memset(&tx_conf_cfg, 0, sizeof(struct dpni_tx_conf_cfg)); + tx_conf_cfg.errors_only = true; + /*Set tx-conf and error configuration*/ + err = dpni_set_tx_conf(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + priv->tx_flow_id, &tx_conf_cfg); + if (err) { + printf("dpni_set_tx_conf() failed\n"); + return err; + } + return 0; } -- cgit v0.10.2 From 1c42beac808b484ed2ee75cc0403f0ffc3a516bd Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 24 Dec 2015 15:33:25 +0530 Subject: driver: net: ldpaa: Increase num of buffers for a pool Management Complex FW 9.0 set the hardware depletion to be 20 buffers in order to support multiple pools in DPNI. This requires driver to fill the pool with at least 21 to be able to receive frames. So, Increase number of buffers for a pool. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index af41b27..3b16150 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -24,7 +24,7 @@ enum ldpaa_eth_type { }; /* Arbitrary values for now, but we'll need to tune */ -#define LDPAA_ETH_NUM_BUFS (2 * 7) +#define LDPAA_ETH_NUM_BUFS (7 * 7) #define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2) #define LDPAA_ETH_RX_BUFFER_SIZE 2048 -- cgit v0.10.2 From 44b2036e1277eb694a5cefa1551120e1e79b41f0 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 24 Dec 2015 15:33:37 +0530 Subject: driver: net: ldpaa: Add debug info of printing DPMAC stats Add debug information prints to provide DPMAC statistics - Number of bytes received - Number of received and discard frames - Number of bytes transferred - Number of frames transferred etc. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 5138e78..7f96883 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -100,6 +100,83 @@ static void ldpaa_eth_get_dpni_counter(void) } printf("DPNI_CNT_EGR_FRAME_DISCARD =%lld\n", value); } + +static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev) +{ + struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; + int err = 0; + u64 value; + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_ING_BYTE, + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n"); + return; + } + printf("DPMAC_CNT_ING_BYTE=%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_ING_FRAME_DISCARD, + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_ING_FRAME_DISCARD failed\n"); + return; + } + printf("DPMAC_CNT_ING_FRAME_DISCARD=%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_ING_ALIGN_ERR, + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_ING_ALIGN_ERR failed\n"); + return; + } + printf("DPMAC_CNT_ING_ALIGN_ERR =%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_ING_BYTE, + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n"); + return; + } + printf("DPMAC_CNT_ING_BYTE=%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_ING_ERR_FRAME, + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_ING_ERR_FRAME failed\n"); + return; + } + printf("DPMAC_CNT_ING_ERR_FRAME=%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_EGR_BYTE , + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_EGR_BYTE failed\n"); + return; + } + printf("DPMAC_CNT_EGR_BYTE =%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_EGR_ERR_FRAME , + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_EGR_ERR_FRAME failed\n"); + return; + } + printf("DPMAC_CNT_EGR_ERR_FRAME =%lld\n", value); +} #endif static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv, @@ -436,6 +513,7 @@ static void ldpaa_eth_stop(struct eth_device *net_dev) #ifdef DEBUG ldpaa_eth_get_dpni_counter(); + ldpaa_eth_get_dpmac_counter(net_dev); #endif err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS, -- cgit v0.10.2 From 335b1936ebf48bf1df3568a8df3766d9408a1070 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 24 Dec 2015 15:33:49 +0530 Subject: driver: net: fsl-mc: Remove portal id hard-coding Management Complex firmware 9.0 has fixed the issue of dprc_destroy_container i.e. the used portal is not return to the free pool. Which was resulting in error ethernet driver want to use this portal via either DPL or dynamically in Linux. Hard-coding of portal id is removed. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index a45a30d..9e042f6 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -821,7 +821,7 @@ static int dprc_init(void) DPRC_CFG_OPT_OBJ_CREATE_ALLOWED | DPRC_CFG_OPT_ALLOC_ALLOWED; cfg.icid = DPRC_GET_ICID_FROM_POOL; - cfg.portal_id = 250; + cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL; err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle, &cfg, -- cgit v0.10.2 From e978a31b631ac40d786f80b4254c323dcc4e1a82 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 30 Dec 2015 14:19:30 +0800 Subject: mmc: fsl_esdhc: increase data transaction timeout to 500ms The MMC spec says "It is strongly recommended for hosts to implement more than 500ms timeout value even if the card indicates the 250ms maximum busy length." Even the previous value of 300ms is known to be insufficient for some cards. So, increase the timeout to 500ms. Signed-off-by: Yangbo Lu Reviewed-by: York Sun diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 1ccc576..6827ffb 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -252,8 +252,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) * Rounding up to next power of 2 * => timeout + 13 = log2(mmc->clock/4) + 1 * => timeout + 13 = fls(mmc->clock/4) + * + * However, the MMC spec "It is strongly recommended for hosts to + * implement more than 500ms timeout value even if the card + * indicates the 250ms maximum busy length." Even the previous + * value of 300ms is known to be insufficient for some cards. + * So, we use + * => timeout + 13 = fls(mmc->clock/2) */ - timeout = fls(mmc->clock/4); + timeout = fls(mmc->clock/2); timeout -= 13; if (timeout > 14) -- cgit v0.10.2 From 8c35cc3b7e2ff1d9bf44af5805e8ef5c4536ce81 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Thu, 21 Jan 2016 17:14:53 +0800 Subject: armv8/ls1043aqds: Select lpuart pins of various muxes Set Board Configuration Register to select the lpuart pins of various muxes. Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Reviewed-by: Bin Meng Reviewed-by: York Sun diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 576fa46..bb14447 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -40,6 +40,9 @@ enum { #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ +#define CFG_UART_MUX_MASK 0x6 +#define CFG_UART_MUX_SHIFT 1 +#define CFG_LPUART_EN 0x1 int checkboard(void) { @@ -218,7 +221,17 @@ void board_retimer_init(void) int board_early_init_f(void) { +#ifdef CONFIG_LPUART + u8 uart; +#endif fsl_lsch2_early_init_f(); +#ifdef CONFIG_LPUART + /* We use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[14]); + uart &= ~CFG_UART_MUX_MASK; + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; + QIXIS_WRITE(brdcfg[14], uart); +#endif return 0; } -- cgit v0.10.2 From 8e728aa915ab220e40ef68fe2b53f2fae5fbc42e Mon Sep 17 00:00:00 2001 From: Wenbin Song Date: Thu, 21 Jan 2016 17:14:54 +0800 Subject: armv8/ls1043aqds: Spilt off board device tree Move new /chosen node out of the board device tree. Signed-off-by: Wenbin Song Reviewed-by: Bin Meng Reviewed-by: York Sun diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 641510c..b3b0f4f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -97,7 +97,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb -dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \ +dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-rdb.dtb dtb-$(CONFIG_MACH_SUN4I) += \ diff --git a/arch/arm/dts/fsl-ls1043a-qds-duart.dts b/arch/arm/dts/fsl-ls1043a-qds-duart.dts new file mode 100644 index 0000000..2124e38 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-qds-duart.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1043a-qds.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-qds.dts deleted file mode 100644 index 7435222..0000000 --- a/arch/arm/dts/fsl-ls1043a-qds.dts +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. - * - * Copyright (C) 2015, Freescale Semiconductor - * - * Mingkai Hu - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; -/include/ "fsl-ls1043a.dtsi" - -/ { - model = "LS1043A QDS Board"; -}; - -&i2c0 { - status = "okay"; - pca9547@77 { - compatible = "philips,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - /* IRQ10_B */ - interrupts = <0 150 0x4>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - eeprom@56 { - compatible = "at24,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "at24,24c512"; - reg = <0x57>; - }; - - adt7461a@4c { - compatible = "adt7461a"; - reg = <0x4c>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000 - 0x2 0x0 0x0 0x7e800000 0x00010000 - 0x3 0x0 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1 0x0 0x10000>; - }; - - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - reg = <0x3 0x0 0x0000100>; - bank-width = <1>; - device-width = <1>; - ranges = <0 3 0 0x100>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi new file mode 100644 index 0000000..6fa16b8 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -0,0 +1,123 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * Mingkai Hu + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/include/ "fsl-ls1043a.dtsi" + +/ { + model = "LS1043A QDS Board"; +}; + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "philips,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + /* IRQ10_B */ + interrupts = <0 150 0x4>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "at24,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "at24,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1 0x0 0x10000>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0x3 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 3 0 0x100>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 60fb0ad..1fd530d 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -2,5 +2,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_NS16550=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_OF_CONTROL=y -- cgit v0.10.2 From 2970e14f652db18f5353f26f84e21f7dac84576d Mon Sep 17 00:00:00 2001 From: Wenbin Song Date: Thu, 21 Jan 2016 17:14:55 +0800 Subject: armv8/ls1043aqds: Add lpuart support Add lpuart support using the driver model. Signed-off-by: Wenbin Song Reviewed-by: Bin Meng Reviewed-by: York Sun diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b3b0f4f..4a01bf6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -98,6 +98,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ + fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb dtb-$(CONFIG_MACH_SUN4I) += \ diff --git a/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts new file mode 100644 index 0000000..18adb97 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1043a-qds.dtsi" + +/ { + chosen { + stdout-path = &lpuart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index 6fa16b8..b9dad72 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -121,3 +121,7 @@ &duart1 { status = "okay"; }; + +&lpuart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 85ea81e..12ea0ab 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -182,5 +182,59 @@ interrupts = <0 55 0x4>; clocks = <&clockgen 4 0>; }; + + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <0 48 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <0 49 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <0 50 0x4>; + clock-names = "ipg"; + clocks = <&sysclk>; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <0 51 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <0 52 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <0 53 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; }; }; diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig new file mode 100644 index 0000000..21d6407 --- /dev/null +++ b/configs/ls1043aqds_lpuart_defconfig @@ -0,0 +1,10 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_FSL_LPUART=y diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4929d98..e6725e3 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -88,6 +88,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg #endif +/* LPUART */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI -- cgit v0.10.2 From 25503443eee0c539e3d566d5aa59410562599f18 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 21 Jan 2016 17:33:19 +0800 Subject: mmc: fsl_esdhc: set Abort command type for CMD12 According to SD spec, CMD12, CMD52 for writing I/O abort in CCCR need to be set an Abort command type when they are sent. So, we remove all chip-specific #ifdefs and make it available for all platforms. Signed-off-by: Yangbo Lu Reviewed-by: York Sun diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 6827ffb..ea5f4bf 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -105,12 +105,9 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; -#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ - defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \ - defined(CONFIG_PPC_T4160) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; -#endif + return XFERTYP_CMD(cmd->cmdidx) | xfertyp; } -- cgit v0.10.2 From c2a4cb17b4ff194e905df76b9f7c1b5a00b99b25 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Tue, 26 Jan 2016 15:06:39 +0800 Subject: spi: fsl_qspi: fix compile warning for 64-bit platform This patch fixes the following compile warning: drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe': drivers/spi/fsl_qspi.c:937:15: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->regs = (struct fsl_qspi_regs *)plat->reg_base; ^ Just make the cast explicit. Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 542b6cf..38e5900 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -936,7 +936,7 @@ static int fsl_qspi_probe(struct udevice *bus) dm_spi_bus->max_hz = plat->speed_hz; - priv->regs = (struct fsl_qspi_regs *)plat->reg_base; + priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base; priv->flags = plat->flags; priv->speed_hz = plat->speed_hz; -- cgit v0.10.2 From 5207014deb1a465d2ac808254902100e7ea69d75 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Tue, 26 Jan 2016 15:06:40 +0800 Subject: spi: fsl_qspi: Fix qspi_op_rdid memcpy issue In current driver everytime we memcpy 4 bytes to the dest memory regardless of the remaining length. This patch adds checking the remaining length before memcpy. If the length is shorter than 4 bytes, memcpy the actual length of data to the dest memory. Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 38e5900..3553e00 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -477,8 +477,8 @@ static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) { struct fsl_qspi_regs *regs = priv->regs; - u32 mcr_reg, rbsr_reg, data; - int i, size; + u32 mcr_reg, rbsr_reg, data, size; + int i; mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, @@ -494,15 +494,15 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) ; i = 0; - size = len; - while ((RX_BUFFER_SIZE >= size) && (size > 0)) { + while ((RX_BUFFER_SIZE >= len) && (len > 0)) { rbsr_reg = qspi_read32(priv->flags, ®s->rbsr); if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { data = qspi_read32(priv->flags, ®s->rbdr[i]); data = qspi_endian_xchg(data); - memcpy(rxbuf, &data, 4); + size = (len < 4) ? len : 4; + memcpy(rxbuf, &data, size); + len -= size; rxbuf++; - size -= 4; i++; } } -- cgit v0.10.2 From 940d2b89bf36c17dfc9972111b68391c35b4e9f2 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Tue, 26 Jan 2016 15:06:41 +0800 Subject: spi: fsl_qspi: Fix qspi_op_rdsr memcpy issue In current driver, we always copy 4 bytes to the dest memory. Actually the dest memory may be shorter than 4 bytes. Add an argument to indicate the dest memory length. Avoid writing memory outside of the bounds. Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 3553e00..cb8d929 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -639,7 +639,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) qspi_write32(priv->flags, ®s->mcr, mcr_reg); } -static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf) +static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) { struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg, reg, data; @@ -662,7 +662,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf) if (reg & QSPI_RBSR_RDBFL_MASK) { data = qspi_read32(priv->flags, ®s->rbdr[0]); data = qspi_endian_xchg(data); - memcpy(rxbuf, &data, 4); + memcpy(rxbuf, &data, len); qspi_write32(priv->flags, ®s->mcr, qspi_read32(priv->flags, ®s->mcr) | QSPI_MCR_CLR_RXF_MASK); @@ -751,7 +751,7 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, } else if (priv->cur_seqid == QSPI_CMD_RDID) qspi_op_rdid(priv, din, bytes); else if (priv->cur_seqid == QSPI_CMD_RDSR) - qspi_op_rdsr(priv, din); + qspi_op_rdsr(priv, din, bytes); #ifdef CONFIG_SPI_FLASH_BAR else if ((priv->cur_seqid == QSPI_CMD_BRRD) || (priv->cur_seqid == QSPI_CMD_RDEAR)) { -- cgit v0.10.2 From 19c31285a33248e2cf95e8d44e012cd392bc04ad Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Tue, 26 Jan 2016 15:06:42 +0800 Subject: dm: env_sf: fix saveenv() to use driver model It might be missed when converting spi_flash_probe() in cmd_sf.c. This patch refers to commit fbb099183e3a ("dm: Convert spi_flash_probe() and 'sf probe' to use driver model"). Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/common/env_sf.c b/common/env_sf.c index 9409831..892e6cb 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -16,6 +16,7 @@ #include #include #include +#include #ifndef CONFIG_ENV_SPI_BUS # define CONFIG_ENV_SPI_BUS 0 @@ -51,6 +52,19 @@ int saveenv(void) char *saved_buffer = NULL, flag = OBSOLETE_FLAG; u32 saved_size, saved_offset, sector = 1; int ret; +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + + ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, + CONFIG_ENV_SPI_MODE, &new); + if (ret) { + set_default_env("!spi_flash_probe_bus_cs() failed"); + return 1; + } + + env_flash = dev_get_uclass_priv(new); +#else if (!env_flash) { env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, @@ -61,6 +75,7 @@ int saveenv(void) return 1; } } +#endif ret = env_export(&env_new); if (ret) @@ -227,6 +242,19 @@ int saveenv(void) char *saved_buffer = NULL; int ret = 1; env_t env_new; +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + + ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, + CONFIG_ENV_SPI_MODE, &new); + if (ret) { + set_default_env("!spi_flash_probe_bus_cs() failed"); + return 1; + } + + env_flash = dev_get_uclass_priv(new); +#else if (!env_flash) { env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, @@ -237,6 +265,7 @@ int saveenv(void) return 1; } } +#endif /* Is the sector larger than the env (i.e. embedded) */ if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) { -- cgit v0.10.2 From e0579a5852b3edb09f965dbbbd0b49507931be95 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Mon, 25 Jan 2016 15:16:05 +0800 Subject: armv8/ls1043aqds: add DSPI support Enable three DSPI flash memories on board. Commands: => sf probe 1:0 SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB => sf probe 1:1 SF: Detected SST25WF040B with page size 256 Bytes, erase size 4 KiB, total 512 KiB => sf probe 1:2 SF: Detected EN25S64 with page size 256 Bytes, erase size 64 KiB, total 8 MiB Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 1fd530d..f7113c5 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -4,3 +4,6 @@ CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_NS16550=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index e9d5afd..8d4370f 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -3,3 +3,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 5221ddb..bc76996 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -1,3 +1,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 6765d3d..0409e33 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -3,3 +3,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e80ac27..35d9750 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -197,6 +197,18 @@ #define CONFIG_DOS_PARTITION #endif +/* DSPI */ +#define CONFIG_FSL_DSPI +#ifdef CONFIG_FSL_DSPI +#define CONFIG_CMD_SF +#define CONFIG_DM_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO /* cs0 */ +#define CONFIG_SPI_FLASH_SST /* cs1 */ +#define CONFIG_SPI_FLASH_EON /* cs2 */ +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#endif + #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ /* FMan ucode */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index dbdcc51..506f50d 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -222,16 +222,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -/* DSPI */ -#define CONFIG_FSL_DSPI -#ifdef CONFIG_FSL_DSPI -#define CONFIG_CMD_SF -#define CONFIG_DM_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SF_DEFAULT_BUS 1 -#define CONFIG_SF_DEFAULT_CS 0 -#endif - /* * Environment */ -- cgit v0.10.2 From 166ef1e90ce404a6470a1c4910a1e84404379b86 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Mon, 25 Jan 2016 15:16:06 +0800 Subject: armv8/ls1043aqds: add QSPI support in SD boot QSPI and IFC are pin-multiplexed on LS1043A. So we use ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot. Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d97a445..7ff0148 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -222,6 +222,9 @@ void fsl_lsch2_early_init_f(void) init_early_memctl_regs(); /* tighten IFC timing */ #endif +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif /* Make SEC reads and writes snoopable */ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP); diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 12ea0ab..66b409a 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -236,5 +236,15 @@ clock-names = "ipg"; status = "disabled"; }; + qspi: quadspi@1550000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1550000 0x10000>, + <0x40000000 0x4000000>; + num-cs = <2>; + big-endian; + status = "disabled"; + }; }; }; diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS index 0c7f648..868bb72 100644 --- a/board/freescale/ls1043aqds/MAINTAINERS +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -7,3 +7,4 @@ F: configs/ls1043aqds_defconfig F: configs/ls1043aqds_nor_ddr3_defconfig F: configs/ls1043aqds_nand_defconfig F: configs/ls1043aqds_sdcard_ifc_defconfig +F: configs/ls1043aqds_sdcard_qspi_defconfig diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg new file mode 100644 index 0000000..7783521 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable QSPI; disable IFC +08100010 0a000000 00000000 00000000 +14550002 80004012 60040000 c1002000 +00000000 00000000 00000000 00038800 +20124000 00001100 00000096 00000001 diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig new file mode 100644 index 0000000..09fb1ed --- /dev/null +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -0,0 +1,10 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_SYS_NS16550=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 35d9750..8900dae 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -121,6 +121,7 @@ #endif /* IFC */ +#ifndef CONFIG_SD_BOOT_QSPI #define CONFIG_FSL_IFC /* * CONFIG_SYS_FLASH_BASE has the final address (core view) @@ -139,6 +140,7 @@ #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #endif +#endif /* I2C */ #define CONFIG_CMD_I2C @@ -205,9 +207,11 @@ #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ #define CONFIG_SPI_FLASH_SST /* cs1 */ #define CONFIG_SPI_FLASH_EON /* cs2 */ +#ifndef CONFIG_SD_BOOT_QSPI #define CONFIG_SF_DEFAULT_BUS 1 #define CONFIG_SF_DEFAULT_CS 0 #endif +#endif #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ @@ -216,9 +220,18 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 +#else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR /* FMan fireware Pre-load address */ #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index e6725e3..60d189b 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -85,8 +85,13 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_SD_BOOT +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg +#else #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg #endif +#endif /* LPUART */ #ifdef CONFIG_LPUART @@ -113,6 +118,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ +#ifndef CONFIG_SD_BOOT_QSPI #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ @@ -196,6 +202,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif #ifdef CONFIG_NAND_BOOT #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ @@ -203,6 +210,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#endif + /* * QIXIS Definitions */ @@ -219,6 +232,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_LBMAP_NAND 0x09 #define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_SD_QSPI 0xff #define QIXIS_RCW_SRC_NAND 0x106 #define QIXIS_RCW_SRC_SD 0x040 #define QIXIS_RST_CTL_RESET 0x41 @@ -347,6 +361,16 @@ unsigned long get_board_ddr_clk(void); #define VDD_MV_MIN 819 #define VDD_MV_MAX 1212 +/* QSPI device */ +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_FSL_QSPI +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +#endif +#endif + /* * Miscellaneous configurable options */ -- cgit v0.10.2 From b0f20caf6570fbc4d19c41dcedf9679784042860 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Mon, 25 Jan 2016 15:16:07 +0800 Subject: armv8/ls1043aqds: add QSPI boot support Enable the U-Boot Driver Model(DM) to use the Freescale QSPI driver. Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index b10ee43..15ade84 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -151,6 +151,8 @@ static const struct sys_mmu_table early_mmu_table[] = { { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS index 868bb72..65a0af1 100644 --- a/board/freescale/ls1043aqds/MAINTAINERS +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -8,3 +8,4 @@ F: configs/ls1043aqds_nor_ddr3_defconfig F: configs/ls1043aqds_nand_defconfig F: configs/ls1043aqds_sdcard_ifc_defconfig F: configs/ls1043aqds_sdcard_qspi_defconfig +F: configs/ls1043aqds_qspi_defconfig diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index 6261a77..a6fd7a3 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -94,3 +94,4 @@ a) Promjet Boot b) NOR boot c) NAND boot d) SD boot +e) QSPI boot diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index bb14447..01db078 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -47,7 +47,7 @@ enum { int checkboard(void) { char buf[64]; -#ifndef CONFIG_SD_BOOT +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) u8 sw; #endif @@ -55,6 +55,8 @@ int checkboard(void) #ifdef CONFIG_SD_BOOT puts("SD\n"); +#elif defined(CONFIG_QSPI_BOOT) + puts("QSPI\n"); #else sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig new file mode 100644 index 0000000..cb076c9 --- /dev/null +++ b/configs/ls1043aqds_qspi_defconfig @@ -0,0 +1,9 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_SYS_NS16550=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 8900dae..6150bc1 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -121,7 +121,7 @@ #endif /* IFC */ -#ifndef CONFIG_SD_BOOT_QSPI +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC /* * CONFIG_SYS_FLASH_BASE has the final address (core view) @@ -207,7 +207,7 @@ #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ #define CONFIG_SPI_FLASH_SST /* cs1 */ #define CONFIG_SPI_FLASH_EON /* cs2 */ -#ifndef CONFIG_SD_BOOT_QSPI +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SF_DEFAULT_BUS 1 #define CONFIG_SF_DEFAULT_CS 0 #endif @@ -220,7 +220,7 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#ifdef CONFIG_SD_BOOT_QSPI +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 #define CONFIG_ENV_SPI_BUS 0 diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 60d189b..4ab8e13 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -10,10 +10,16 @@ #include "ls1043a_common.h" #define CONFIG_DISPLAY_CPUINFO +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_DISPLAY_BOARDINFO_LATE +#else #define CONFIG_DISPLAY_BOARDINFO +#endif #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) #define CONFIG_SYS_TEXT_BASE 0x82000000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x40010000 #else #define CONFIG_SYS_TEXT_BASE 0x60100000 #endif @@ -118,7 +124,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ -#ifndef CONFIG_SD_BOOT_QSPI +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ @@ -210,7 +216,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif -#ifdef CONFIG_SD_BOOT_QSPI +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS #define CONFIG_SYS_NO_FLASH #undef CONFIG_CMD_IMLS @@ -233,8 +239,10 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_NAND 0x09 #define QIXIS_LBMAP_SD 0x00 #define QIXIS_LBMAP_SD_QSPI 0xff +#define QIXIS_LBMAP_QSPI 0xff #define QIXIS_RCW_SRC_NAND 0x106 #define QIXIS_RCW_SRC_SD 0x040 +#define QIXIS_RCW_SRC_QSPI 0x045 #define QIXIS_RST_CTL_RESET 0x41 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 @@ -362,7 +370,7 @@ unsigned long get_board_ddr_clk(void); #define VDD_MV_MAX 1212 /* QSPI device */ -#ifdef CONFIG_SD_BOOT_QSPI +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION @@ -421,6 +429,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) -- cgit v0.10.2