From e3e842f17cfe0f3f4972c462a4d3ed13ba5eb1ab Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Fri, 6 Oct 2017 19:24:09 +0200 Subject: rockchip: configs: use rockchip-common.h for rk3368 rockchip-common.h already defines values that are missing from rk3368_common.h For example BOOT_TARGET_DEVICES was defined empty and therefore distroboot had no boot targets. Signed-off-by: Klaus Goger Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 8b4155f..b643cc2 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -7,6 +7,8 @@ #ifndef __CONFIG_RK3368_COMMON_H #define __CONFIG_RK3368_COMMON_H +#include "rockchip-common.h" + #define CONFIG_SYS_CACHELINE_SIZE 64 #include @@ -44,10 +46,6 @@ "kernel_addr_r=0x280000\0" \ "ramdisk_addr_r=0x5bf0000\0" -#include - -#define BOOT_TARGET_DEVICES(func) - #include #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2 From 6e278a8c1c28efc12668d2761cb2fb0264668da4 Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Fri, 6 Oct 2017 19:24:08 +0200 Subject: rockchip: configs: only add available BOOT_TARGET_DEVICES BOOT_TARGET_DEVICES should only be added if the corresponding u-boot command is enabled. Signed-off-by: Klaus Goger Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 5e9b6de..96b5fce 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -11,22 +11,39 @@ #ifndef CONFIG_SPL_BUILD #include -/* First try to boot from SD (index 0), then eMMC (index 1 */ -#ifdef CONFIG_CMD_USB -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dchp, na) +/* First try to boot from SD (index 0), then eMMC (index 1) */ +#if CONFIG_IS_ENABLED(CMD_MMC) + #define BOOT_TARGET_MMC(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) #else -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(PXE, pxe, na) \ - func(DHCP, dchp, na) + #define BOOT_TARGET_MMC(func) #endif +#if CONFIG_IS_ENABLED(CMD_USB) + #define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else + #define BOOT_TARGET_USB(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_PXE) + #define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else + #define BOOT_TARGET_PXE(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_DHCP) + #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) +#else + #define BOOT_TARGET_DHCP(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) + #ifdef CONFIG_ARM64 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0" #else -- cgit v0.10.2 From 9f636a249c126b74e673e6d9592215f9b06c4f0b Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 12 Oct 2017 15:27:29 +0800 Subject: rockchip: rk3399: init CPU clock when rkclk_init() Init the CPU and its buses to speed up the boot time. Move rkclk_init() to a place after rk3399_configure_cpu has defined at the same time, or else there will be a warning. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Reviewed-by: Philipp Tomsich Acked-by: Philipp Tomsich diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index f45bba4..6f85a38 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -398,84 +398,6 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return 0; } -#ifdef CONFIG_SPL_BUILD -static void rkclk_init(struct rk3399_cru *cru) -{ - u32 aclk_div; - u32 hclk_div; - u32 pclk_div; - - /* - * some cru registers changed by bootrom, we'd better reset them to - * reset/default values described in TRM to avoid confusion in kernel. - * Please consider these three lines as a fix of bootrom bug. - */ - rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); - rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); - rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); - - /* configure gpll cpll */ - rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); - rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); - - /* configure perihp aclk, hclk, pclk */ - aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; - assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); - - hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; - assert((hclk_div + 1) * PERIHP_HCLK_HZ == - PERIHP_ACLK_HZ && (hclk_div < 0x4)); - - pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; - assert((pclk_div + 1) * PERIHP_PCLK_HZ == - PERIHP_ACLK_HZ && (pclk_div < 0x7)); - - rk_clrsetreg(&cru->clksel_con[14], - PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | - ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, - pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | - hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | - ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | - aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); - - /* configure perilp0 aclk, hclk, pclk */ - aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; - assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); - - hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; - assert((hclk_div + 1) * PERILP0_HCLK_HZ == - PERILP0_ACLK_HZ && (hclk_div < 0x4)); - - pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; - assert((pclk_div + 1) * PERILP0_PCLK_HZ == - PERILP0_ACLK_HZ && (pclk_div < 0x7)); - - rk_clrsetreg(&cru->clksel_con[23], - PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | - ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, - pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | - hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | - ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | - aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); - - /* perilp1 hclk select gpll as source */ - hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; - assert((hclk_div + 1) * PERILP1_HCLK_HZ == - GPLL_HZ && (hclk_div < 0x1f)); - - pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; - assert((pclk_div + 1) * PERILP1_HCLK_HZ == - PERILP1_HCLK_HZ && (hclk_div < 0x7)); - - rk_clrsetreg(&cru->clksel_con[25], - PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | - HCLK_PERILP1_PLL_SEL_MASK, - pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | - hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | - HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); -} -#endif - void rk3399_configure_cpu(struct rk3399_cru *cru, enum apll_l_frequencies apll_l_freq) { @@ -1004,6 +926,85 @@ static struct clk_ops rk3399_clk_ops = { .enable = rk3399_clk_enable, }; +#ifdef CONFIG_SPL_BUILD +static void rkclk_init(struct rk3399_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + rk3399_configure_cpu(cru, APLL_L_600_MHZ); + /* + * some cru registers changed by bootrom, we'd better reset them to + * reset/default values described in TRM to avoid confusion in kernel. + * Please consider these three lines as a fix of bootrom bug. + */ + rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); + rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); + rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); + + /* configure gpll cpll */ + rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); + rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); + + /* configure perihp aclk, hclk, pclk */ + aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; + assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; + assert((hclk_div + 1) * PERIHP_HCLK_HZ == + PERIHP_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; + assert((pclk_div + 1) * PERIHP_PCLK_HZ == + PERIHP_ACLK_HZ && (pclk_div < 0x7)); + + rk_clrsetreg(&cru->clksel_con[14], + PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | + ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, + pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | + hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | + ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | + aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); + + /* configure perilp0 aclk, hclk, pclk */ + aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; + assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; + assert((hclk_div + 1) * PERILP0_HCLK_HZ == + PERILP0_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; + assert((pclk_div + 1) * PERILP0_PCLK_HZ == + PERILP0_ACLK_HZ && (pclk_div < 0x7)); + + rk_clrsetreg(&cru->clksel_con[23], + PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | + ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, + pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | + hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | + ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | + aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); + + /* perilp1 hclk select gpll as source */ + hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; + assert((hclk_div + 1) * PERILP1_HCLK_HZ == + GPLL_HZ && (hclk_div < 0x1f)); + + pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; + assert((pclk_div + 1) * PERILP1_HCLK_HZ == + PERILP1_HCLK_HZ && (hclk_div < 0x7)); + + rk_clrsetreg(&cru->clksel_con[25], + PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | + HCLK_PERILP1_PLL_SEL_MASK, + pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | + hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | + HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); +} +#endif + static int rk3399_clk_probe(struct udevice *dev) { #ifdef CONFIG_SPL_BUILD -- cgit v0.10.2 From 36de37f5ca55ffd426f3e16ba085a4e7defdfa3b Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 25 Oct 2017 16:24:48 +0800 Subject: rockchip: rk3328: fix rockchip_get_cru api The API for get priv pointer is wrong, fix it. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich Acked-by: Philipp Tomsich diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c index 4dcac27..013d777 100644 --- a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c @@ -25,7 +25,7 @@ void *rockchip_get_cru(void) if (ret) return ERR_PTR(ret); - priv = devfdt_get_addr_ptr(dev); + priv = dev_get_priv(dev); return priv->cru; } -- cgit v0.10.2 From 4c1a60c5973be6cf1a1a8b1eb85ee93bdc21a499 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 26 Oct 2017 14:45:02 +0800 Subject: rockchip: evb-rk3328: remove CONFIG_ENV_OFFSET Remove CONFIG_ENV_OFFSET for there already have one in rockchip_common.h Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h index c792ce5..93b18b8 100644 --- a/include/configs/evb_rk3328.h +++ b/include/configs/evb_rk3328.h @@ -10,12 +10,6 @@ #include #define CONFIG_SYS_MMC_ENV_DEV 1 -/* - * SPL @ 32k for ~36k - * ENV @ 96k - * u-boot @ 128K - */ -#define CONFIG_ENV_OFFSET (96 * 1024) #define SDRAM_BANK_SIZE (2UL << 30) -- cgit v0.10.2 From 18a158979c67cd5316c84ecbc3cb4c91ee8c9e37 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Mon, 30 Oct 2017 14:44:55 +0100 Subject: rockchip: puma-rk3399: defconfig: select PHY_MICREL_KSZ90X1 The RK3368-uQ7 uses a KSZ9031 PHY on-module. Enable PHY_MICREL_KSZ90X1 in the associated defconfig (this somehow got lost with da3b9e7f). References: da3b9e7f ("Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig") Signed-off-by: Philipp Tomsich Acked-by: Philipp Tomsich diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index d8b24f1..ebbf8a9 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -57,6 +57,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -- cgit v0.10.2 From ed6be4fcdfd4db56081e366c40dee7c3fb19ef59 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Mon, 30 Oct 2017 14:44:54 +0100 Subject: rockchip: lion-rk3368: defconfig: select PHY_MICREL_KSZ90X1 The RK3368-uQ7 uses a KSZ9031 PHY on-module. Enable PHY_MICREL_KSZ90X1 in the associated defconfig. References: da3b9e7f ("Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig") Signed-off-by: Philipp Tomsich Acked-by: Philipp Tomsich diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 959180c..8dae75c 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y -- cgit v0.10.2