From 9ac0efd2925fd43080bd6930626763cd90e9521f Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:04 +0100 Subject: ppc: xilinx-ppc440: Remove support for ml507 ml507 is just a specialized version of the xilinx-ppc440-generic Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index efd3165..ba09b57 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -115,9 +115,6 @@ config TARGET_PIP405 config TARGET_XPEDITE1000 bool "Support xpedite1000" -config TARGET_ML507 - bool "Support ml507" - config TARGET_XILINX_PPC405_GENERIC bool "Support xilinx-ppc405-generic" @@ -158,7 +155,6 @@ source "board/mpl/mip405/Kconfig" source "board/mpl/pip405/Kconfig" source "board/t3corp/Kconfig" source "board/xes/xpedite1000/Kconfig" -source "board/xilinx/ml507/Kconfig" source "board/xilinx/ppc405-generic/Kconfig" source "board/xilinx/ppc440-generic/Kconfig" diff --git a/board/xilinx/ml507/Kconfig b/board/xilinx/ml507/Kconfig deleted file mode 100644 index d580a7b..0000000 --- a/board/xilinx/ml507/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ML507 - -config SYS_BOARD - default "ml507" - -config SYS_VENDOR - default "xilinx" - -config SYS_CONFIG_NAME - default "ml507" - -endif diff --git a/board/xilinx/ml507/MAINTAINERS b/board/xilinx/ml507/MAINTAINERS deleted file mode 100644 index 8b40f44..0000000 --- a/board/xilinx/ml507/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -ML507 BOARD -M: Ricardo Ribalda -S: Maintained -F: board/xilinx/ml507/ -F: include/configs/ml507.h -F: configs/ml507_defconfig -F: configs/ml507_flash_defconfig diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile deleted file mode 100644 index 9a3809f..0000000 --- a/board/xilinx/ml507/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ml507.o - -include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c deleted file mode 100644 index 83b764b..0000000 --- a/board/xilinx/ml507/ml507.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include -#include -#include - - -int checkboard(void) -{ - puts("Xilinx ML507 Board\n"); - return 0; -} diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h deleted file mode 100644 index e30e592..0000000 --- a/board/xilinx/ml507/xparameters.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * based on xparameters-ml507.h by Xilinx - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef XPARAMETER_H -#define XPARAMETER_H - -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 - -#endif diff --git a/configs/ml507_defconfig b/configs/ml507_defconfig deleted file mode 100644 index d1e4e30..0000000 --- a/configs/ml507_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_ML507=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o" -CONFIG_SYS_PROMPT="ml507:/# " -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/configs/ml507_flash_defconfig b/configs/ml507_flash_defconfig deleted file mode 100644 index 442e0ce..0000000 --- a/configs/ml507_flash_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_ML507=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/include/configs/ml507.h b/include/configs/ml507.h deleted file mode 100644 index 89a7290..0000000 --- a/include/configs/ml507.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*CPU*/ -#define CONFIG_440 1 -#define CONFIG_XILINX_ML507 1 -#include "../board/xilinx/ml507/xparameters.h" - -/*Mem Map*/ -#define CONFIG_SYS_SDRAM_SIZE_MB 256 - -/*Env*/ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x340000 -#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) - -/*Misc*/ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" - -/*Flash*/ -#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 259 -#define MTDIDS_DEFAULT "nor0=ml507-flash" -#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" - -/*Generic Configs*/ -#include - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From 70c29dcdbc2df17a27c9879bcfdf4f098734545c Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:05 +0100 Subject: ppc: xilinx-ppc405: Remove support for fx12mm It is just a specialized version of the xilinx-ppc405 Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index ba09b57..120d5cf 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -55,9 +55,6 @@ config TARGET_YOSEMITE config TARGET_YUCCA bool "Support yucca" -config TARGET_FX12MM - bool "Support fx12mm" - config TARGET_V5FX30TEVAL bool "Support v5fx30teval" @@ -136,7 +133,6 @@ source "board/amcc/sequoia/Kconfig" source "board/amcc/walnut/Kconfig" source "board/amcc/yosemite/Kconfig" source "board/amcc/yucca/Kconfig" -source "board/avnet/fx12mm/Kconfig" source "board/avnet/v5fx30teval/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" diff --git a/board/avnet/fx12mm/Kconfig b/board/avnet/fx12mm/Kconfig deleted file mode 100644 index 0b67ebd..0000000 --- a/board/avnet/fx12mm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_FX12MM - -config SYS_BOARD - default "fx12mm" - -config SYS_VENDOR - default "avnet" - -config SYS_CONFIG_NAME - default "fx12mm" - -endif diff --git a/board/avnet/fx12mm/MAINTAINERS b/board/avnet/fx12mm/MAINTAINERS deleted file mode 100644 index c92e258..0000000 --- a/board/avnet/fx12mm/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -FX12MM BOARD -M: Georg Schardt -S: Maintained -F: board/avnet/fx12mm/ -F: include/configs/fx12mm.h -F: configs/fx12mm_defconfig -F: configs/fx12mm_flash_defconfig diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile deleted file mode 100644 index 618b42f..0000000 --- a/board/avnet/fx12mm/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += fx12mm.o - -include $(srctree)/board/xilinx/ppc405-generic/Makefile diff --git a/board/avnet/fx12mm/fx12mm.c b/board/avnet/fx12mm/fx12mm.c deleted file mode 100644 index 92e1cfb..0000000 --- a/board/avnet/fx12mm/fx12mm.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2008 - * - * Author: Xilinx Inc. - * - * Modified by: - * Georg Schardt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -int checkboard(void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - if (l < 0) { - printf("Avnet Virtex4 FX12 with no serial #"); - } else { - printf("Avnet Virtex4 FX12 Minimodul # "); - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc(buf[i]); - } - } - putc('\n'); - return 0; -} diff --git a/board/avnet/fx12mm/xparameters.h b/board/avnet/fx12mm/xparameters.h deleted file mode 100644 index 94f682f..0000000 --- a/board/avnet/fx12mm/xparameters.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2008 - * - * Georg Schardt - * - * SPDX-License-Identifier: GPL-2.0+ - * - * CAUTION: This file is based on the xparameters.h automatically - * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5 - */ - -#ifndef __XPARAMETER_H__ -#define __XPARAMETER_H__ - -/* RS232 */ -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 -#define XPAR_UARTNS550_0_BASEADDR 0x83E00000 - - -/* INT_C */ -#define XPAR_XPS_INTC_0_DEVICE_ID 0 -#define XPAR_XPS_INTC_0_BASEADDR 0x81800000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2 - -/* CPU core clock */ -#define XPAR_CORE_CLOCK_FREQ_HZ 300000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 - -/* RAM */ -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 - -/* FLASH */ -#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000 - -#endif diff --git a/configs/fx12mm_defconfig b/configs/fx12mm_defconfig deleted file mode 100644 index c714d0d..0000000 --- a/configs/fx12mm_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_FX12MM=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o" -CONFIG_SYS_PROMPT="FX12MM:/# " -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_NS16550=y diff --git a/configs/fx12mm_flash_defconfig b/configs/fx12mm_flash_defconfig deleted file mode 100644 index ac38412..0000000 --- a/configs/fx12mm_flash_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_FX12MM=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_NS16550=y diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h deleted file mode 100644 index fa32a2e..0000000 --- a/include/configs/fx12mm.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2008 - * - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com - * - * Georg Schardt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec, - * see http://www.em.avnet.com - */ - -#ifndef __CONFIG_FX12_H -#define __CONFIG_FX12_H - -#include "../board/avnet/fx12mm/xparameters.h" - -/* cmd config */ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD - -/* sdram */ -#define CONFIG_SYS_SDRAM_SIZE_MB 64 - -/* environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_SYS_ENV_OFFSET 0xA0000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET) -#define CONFIG_ENV_OVERWRITE 1 - -/*Misc*/ -#define CONFIG_PREBOOT "echo U-Boot is up and running;" - -/*Flash*/ -#define CONFIG_SYS_FLASH_SIZE (4*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 71 -#define MTDIDS_DEFAULT "nor0=fx12mm-flash" -#define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)" - -#include "configs/xilinx-ppc405.h" - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From 583aefb89cdfb0fde88cd72738c487aeb54cada5 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:06 +0100 Subject: xilinx-ppc440: Remove support for v5fx30teval It is just a specialized version of xilinx-ppc440 Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 120d5cf..3959585 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -55,9 +55,6 @@ config TARGET_YOSEMITE config TARGET_YUCCA bool "Support yucca" -config TARGET_V5FX30TEVAL - bool "Support v5fx30teval" - config TARGET_CPCI2DP bool "Support CPCI2DP" @@ -133,7 +130,6 @@ source "board/amcc/sequoia/Kconfig" source "board/amcc/walnut/Kconfig" source "board/amcc/yosemite/Kconfig" source "board/amcc/yucca/Kconfig" -source "board/avnet/v5fx30teval/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" source "board/esd/plu405/Kconfig" diff --git a/board/avnet/v5fx30teval/Kconfig b/board/avnet/v5fx30teval/Kconfig deleted file mode 100644 index 079387b..0000000 --- a/board/avnet/v5fx30teval/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_V5FX30TEVAL - -config SYS_BOARD - default "v5fx30teval" - -config SYS_VENDOR - default "avnet" - -config SYS_CONFIG_NAME - default "v5fx30teval" - -endif diff --git a/board/avnet/v5fx30teval/MAINTAINERS b/board/avnet/v5fx30teval/MAINTAINERS deleted file mode 100644 index 91dde7a..0000000 --- a/board/avnet/v5fx30teval/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -V5FX30TEVAL BOARD -M: Ricardo Ribalda -S: Maintained -F: board/avnet/v5fx30teval/ -F: include/configs/v5fx30teval.h -F: configs/v5fx30teval_defconfig -F: configs/v5fx30teval_flash_defconfig diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile deleted file mode 100644 index 8c41af0..0000000 --- a/board/avnet/v5fx30teval/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += v5fx30teval.o - -include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/avnet/v5fx30teval/v5fx30teval.c b/board/avnet/v5fx30teval/v5fx30teval.c deleted file mode 100644 index 68b0eb9..0000000 --- a/board/avnet/v5fx30teval/v5fx30teval.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include -#include -#include - - -int checkboard(void) -{ - puts("Avnet Virtex 5 FX30 Evaluation Board\n"); - return 0; -} diff --git a/board/avnet/v5fx30teval/xparameters.h b/board/avnet/v5fx30teval/xparameters.h deleted file mode 100644 index 95b8c28..0000000 --- a/board/avnet/v5fx30teval/xparameters.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * based on xparameters.h by Xilinx - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef XPARAMETER_H -#define XPARAMETER_H - -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 - -#endif diff --git a/configs/v5fx30teval_defconfig b/configs/v5fx30teval_defconfig deleted file mode 100644 index 3e2ce7d..0000000 --- a/configs/v5fx30teval_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_V5FX30TEVAL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o" -CONFIG_SYS_PROMPT="v5fx30t:/# " -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/configs/v5fx30teval_flash_defconfig b/configs/v5fx30teval_flash_defconfig deleted file mode 100644 index b9b05e8..0000000 --- a/configs/v5fx30teval_flash_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_V5FX30TEVAL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/include/configs/v5fx30teval.h b/include/configs/v5fx30teval.h deleted file mode 100644 index 298fa3e..0000000 --- a/include/configs/v5fx30teval.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*CPU*/ -#define CONFIG_440 1 -#define CONFIG_XILINX_ML507 1 -#include "../board/avnet/v5fx30teval/xparameters.h" - -/*Mem Map*/ -#define CONFIG_SYS_SDRAM_SIZE_MB 64 - -/*Env*/ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x1A0000 -#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) - -/*Misc*/ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" - -/*Flash*/ -#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 131 -#define MTDIDS_DEFAULT "nor0=v5fx30t-flash" -#define MTDPARTS_DEFAULT "mtdparts=v5fx30t-flash:-(user)" - -/*Generic Configs*/ -#include - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From df48b23428e9075f4b93b78c685271738875c466 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:07 +0100 Subject: .mailmap: Add all the mail alias for Ricardo Ribalda Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/.mailmap b/.mailmap index 02dccfc..f72fef1 100644 --- a/.mailmap +++ b/.mailmap @@ -21,6 +21,9 @@ Jagan Teki Markus Klotzbuecher Prabhakar Kushwaha Rajeshwari Shinde +Ricardo Ribalda Delgado +Ricardo Ribalda +Ricardo Ribalda Sandeep Paulraj Shaohui Xie Stefan Roese -- cgit v0.10.2 From 5b218ae106498d32335dc16e3cb9f64ec3854590 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:08 +0100 Subject: mailaddr: Update mail address The old mail address will stop working soon. Update it all the files Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/arch/powerpc/cpu/ppc4xx/interrupts.c b/arch/powerpc/cpu/ppc4xx/interrupts.c index d9b5654..45997d6 100644 --- a/arch/powerpc/cpu/ppc4xx/interrupts.c +++ b/arch/powerpc/cpu/ppc4xx/interrupts.c @@ -9,7 +9,7 @@ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com * * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX) - * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * Work supported by Qtechnology (htpp://qtec.com) * * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/powerpc/cpu/ppc4xx/uic.c b/arch/powerpc/cpu/ppc4xx/uic.c index bd955ed..fb453b1 100644 --- a/arch/powerpc/cpu/ppc4xx/uic.c +++ b/arch/powerpc/cpu/ppc4xx/uic.c @@ -9,7 +9,7 @@ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com * * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX) - * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * Work supported by Qtechnology (htpp://qtec.com) * * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c index 71e1be0..1a2e917 100644 --- a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c +++ b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h index 1a6a933..9f370dd 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de * diff --git a/arch/powerpc/include/asm/xilinx_irq.h b/arch/powerpc/include/asm/xilinx_irq.h index 333a037..5766bde 100644 --- a/arch/powerpc/include/asm/xilinx_irq.h +++ b/arch/powerpc/include/asm/xilinx_irq.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/xilinx/ppc405-generic/MAINTAINERS b/board/xilinx/ppc405-generic/MAINTAINERS index 2b0c98d..ba48f50 100644 --- a/board/xilinx/ppc405-generic/MAINTAINERS +++ b/board/xilinx/ppc405-generic/MAINTAINERS @@ -1,5 +1,5 @@ PPC405-GENERIC BOARD -M: Ricardo Ribalda +M: Ricardo Ribalda S: Maintained F: board/xilinx/ppc405-generic/ F: include/configs/xilinx-ppc405-generic.h diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile index c9da870..922946d 100644 --- a/board/xilinx/ppc405-generic/Makefile +++ b/board/xilinx/ppc405-generic/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com # Work supported by Qtechnology http://www.qtec.com # # SPDX-License-Identifier: GPL-2.0+ diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c index e3dd468..8b10dba 100644 --- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h index f0ff78f..e610407 100644 --- a/board/xilinx/ppc405-generic/xparameters.h +++ b/board/xilinx/ppc405-generic/xparameters.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * based on xparameters-ml507.h by Xilinx * diff --git a/board/xilinx/ppc440-generic/MAINTAINERS b/board/xilinx/ppc440-generic/MAINTAINERS index 2d0b11a..0258c82 100644 --- a/board/xilinx/ppc440-generic/MAINTAINERS +++ b/board/xilinx/ppc440-generic/MAINTAINERS @@ -1,5 +1,5 @@ PPC440-GENERIC BOARD -M: Ricardo Ribalda +M: Ricardo Ribalda S: Maintained F: board/xilinx/ppc440-generic/ F: include/configs/xilinx-ppc440-generic.h diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile index 0acd95d..5ca57a9 100644 --- a/board/xilinx/ppc440-generic/Makefile +++ b/board/xilinx/ppc440-generic/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com # Work supported by Qtechnology http://www.qtec.com # # SPDX-License-Identifier: GPL-2.0+ diff --git a/board/xilinx/ppc440-generic/init.S b/board/xilinx/ppc440-generic/init.S index 4598a37..f9ff35f 100644 --- a/board/xilinx/ppc440-generic/init.S +++ b/board/xilinx/ppc440-generic/init.S @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c index 74df2f4..3718a76 100644 --- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c +++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h index e30e592..3c135ec 100644 --- a/board/xilinx/ppc440-generic/xparameters.h +++ b/board/xilinx/ppc440-generic/xparameters.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * based on xparameters-ml507.h by Xilinx * diff --git a/drivers/hwmon/adt7460.c b/drivers/hwmon/adt7460.c index fd05c17..9b2c5b6 100644 --- a/drivers/hwmon/adt7460.c +++ b/drivers/hwmon/adt7460.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid, ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid, ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index eb400d0..876750b 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * (C) Copyright 2008 diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h index 40fa087..bdb9372 100644 --- a/include/configs/xilinx-ppc405-generic.h +++ b/include/configs/xilinx-ppc405-generic.h @@ -1,7 +1,7 @@ /* * * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * (C) Copyright 2008 diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h index a0151fe..dcfe56e 100644 --- a/include/configs/xilinx-ppc405.h +++ b/include/configs/xilinx-ppc405.h @@ -1,7 +1,7 @@ /* * * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * (C) Copyright 2008 diff --git a/include/configs/xilinx-ppc440-generic.h b/include/configs/xilinx-ppc440-generic.h index 95b8834..769a1de 100644 --- a/include/configs/xilinx-ppc440-generic.h +++ b/include/configs/xilinx-ppc440-generic.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/include/configs/xilinx-ppc440.h b/include/configs/xilinx-ppc440.h index f457008..f521387 100644 --- a/include/configs/xilinx-ppc440.h +++ b/include/configs/xilinx-ppc440.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * SPDX-License-Identifier: GPL-2.0+ */ -- cgit v0.10.2 From 6de59eb2c2c986c824524b74f97a1c5b8c112ced Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:09 +0100 Subject: ppc: pp405-generic: Simplify Makefile As a result of the specific board removal, the Makefiles can be simplified. Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile index 922946d..2800f68 100644 --- a/board/xilinx/ppc405-generic/Makefile +++ b/board/xilinx/ppc405-generic/Makefile @@ -9,4 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o +obj-y += xilinx_ppc405_generic.o -- cgit v0.10.2 From bec8dd5fc0211a9720bb08e576110fe06fa07b45 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:10 +0100 Subject: ppc: pp440-generic: Simplify Makefile As a result of the specific board removal, the Makefiles can be simplified. Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile index 5ca57a9..4d5f410 100644 --- a/board/xilinx/ppc440-generic/Makefile +++ b/board/xilinx/ppc440-generic/Makefile @@ -9,5 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o -extra-y += ../../xilinx/ppc440-generic/init.o +obj-y += xilinx_ppc440_generic.o +extra-y += init.o -- cgit v0.10.2 From 093eb5daae62b95ae9a35c82309cb60a7c240be7 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:11 +0100 Subject: ppc: ppc440: ppc440-generic_flash_defconfig Remove redundant defconfig file. Boot via flash can be configured via Kconfig. Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/configs/xilinx-ppc440-generic_flash_defconfig b/configs/xilinx-ppc440-generic_flash_defconfig deleted file mode 100644 index 6299033..0000000 --- a/configs/xilinx-ppc440-generic_flash_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_XILINX_PPC440_GENERIC=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -- cgit v0.10.2 From 3a40457f23e240b0b1498d335d12f6c63fbe0bf6 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:12 +0100 Subject: ppc: ppc405: ppc405-generic_flash_defconfig Remove redundant defconfig file. Boot via flash can be configured via Kconfig. Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/configs/xilinx-ppc405-generic_flash_defconfig b/configs/xilinx-ppc405-generic_flash_defconfig deleted file mode 100644 index 37084fb..0000000 --- a/configs/xilinx-ppc405-generic_flash_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_XILINX_PPC405_GENERIC=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -- cgit v0.10.2 From 06a6405ad868996cece0e86f84ecd097a87f2d61 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:13 +0100 Subject: ppc: xilinx-ppc440-generic: Cleanout header files Now that there is only one header file for all ppc440 files, merge header files. Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/include/configs/xilinx-ppc440-generic.h b/include/configs/xilinx-ppc440-generic.h index 769a1de..47bc4ae 100644 --- a/include/configs/xilinx-ppc440-generic.h +++ b/include/configs/xilinx-ppc440-generic.h @@ -10,6 +10,7 @@ /*CPU*/ #define CONFIG_440 1 +#define CONFIG_XILINX_440 1 #define CONFIG_XILINX_PPC440_GENERIC 1 #include "../board/xilinx/ppc440-generic/xparameters.h" @@ -33,6 +34,6 @@ #define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" /*Generic Configs*/ -#include +#include #endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc440.h b/include/configs/xilinx-ppc440.h deleted file mode 100644 index f521387..0000000 --- a/include/configs/xilinx-ppc440.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef __CONFIG_GEN_H -#define __CONFIG_GEN_H - -/*CPU*/ -#define CONFIG_440 1 -#define CONFIG_XILINX_440 1 - -#include - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From 2150addeffbf6e4f40b30709237896a9c5de22cb Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:14 +0100 Subject: ppc: xilinx-ppc405-generic: Cleanout header files Now that there is only one header file for all ppc405 files, merge header files. Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h index bdb9372..e2d189d 100644 --- a/include/configs/xilinx-ppc405-generic.h +++ b/include/configs/xilinx-ppc405-generic.h @@ -14,6 +14,9 @@ #include "../board/xilinx/ppc405-generic/xparameters.h" +#define CONFIG_405 1 +#define CONFIG_XILINX_405 1 + /* sdram */ #define CONFIG_SYS_SDRAM_SIZE_MB 256 @@ -37,5 +40,5 @@ #define MTDIDS_DEFAULT "nor0=ppc405-flash" #define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)" -#include +#include #endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h deleted file mode 100644 index dcfe56e..0000000 --- a/include/configs/xilinx-ppc405.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com - * This work has been supported by: QTechnology http://qtec.com/ - * - * (C) Copyright 2008 - * Georg Schardt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* cpu parameter */ -#define CONFIG_405 1 -#define CONFIG_XILINX_405 1 - -#include - -#endif -- cgit v0.10.2 From 5e68f17e24f91a7a54809c20967363846869e6a3 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 13:47:46 +0100 Subject: ppc: dts: Add device tree for xilix-ppc4xx-generic Add device tree example file for xilinx-ppc440-generic and xilinx-ppc405-generic Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 5d9f5c2..80b4c0c 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -3,6 +3,8 @@ # dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb +dtb-$(CONFIG_TARGET_XILINX_PPC440_GENERIC) += xilinx-ppc440-generic.dtb +dtb-$(CONFIG_TARGET_XILINX_PPC405_GENERIC) += xilinx-ppc405-generic.dtb targets += $(dtb-y) diff --git a/arch/powerpc/dts/xilinx-ppc405-generic.dts b/arch/powerpc/dts/xilinx-ppc405-generic.dts new file mode 100644 index 0000000..6498321 --- /dev/null +++ b/arch/powerpc/dts/xilinx-ppc405-generic.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + console = &uart0; + }; + + uart0: serial@84000000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + interrupts = <0 0>; + reg = <0x84000000 0x10000>; + }; +} ; diff --git a/arch/powerpc/dts/xilinx-ppc440-generic.dts b/arch/powerpc/dts/xilinx-ppc440-generic.dts new file mode 100644 index 0000000..c83523a --- /dev/null +++ b/arch/powerpc/dts/xilinx-ppc440-generic.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + console = &uart0; + }; + + uart0: serial@8b000000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + interrupts = <0 0>; + reg = <0x8b000000 0x10000>; + }; +} ; -- cgit v0.10.2 From f9c690b0f6ac1e6a0436d304a1fdf78d0c8948c0 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:17 +0100 Subject: configs/xilinx-ppc405-generic: Typos and size -Fix typos (runnining -> running) -Increase default size Signed-off-by: Ricardo Ribalda Delgado Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h index e2d189d..6182b0e 100644 --- a/include/configs/xilinx-ppc405-generic.h +++ b/include/configs/xilinx-ppc405-generic.h @@ -29,16 +29,16 @@ #define CONFIG_ENV_OVERWRITE 1 /*Misc*/ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" +#define CONFIG_PREBOOT "echo U-Boot is up and running;" /*Flash*/ -#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR -#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 71 +#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR +#define CONFIG_SYS_FLASH_SIZE (128*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 1024 #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 -#define MTDIDS_DEFAULT "nor0=ppc405-flash" -#define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)" +#define MTDIDS_DEFAULT "nor0=flash" +#define MTDPARTS_DEFAULT "mtdparts=flash:-(user)" #include #endif /* __CONFIG_H */ -- cgit v0.10.2 From ad7321da8e5c56613b604cb91e064fbaa44b3283 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:18 +0100 Subject: configs/xilinx-ppc440-generic: Typos and size -Fix typos (runnining -> running) -Increase default size Signed-off-by: Ricardo Ribalda Delgado Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/include/configs/xilinx-ppc440-generic.h b/include/configs/xilinx-ppc440-generic.h index 47bc4ae..2af5f7f 100644 --- a/include/configs/xilinx-ppc440-generic.h +++ b/include/configs/xilinx-ppc440-generic.h @@ -21,17 +21,17 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x340000 +#define CONFIG_ENV_OFFSET 0x340000 #define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) /*Misc*/ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" +#define CONFIG_PREBOOT "echo U-Boot is up and running;" /*Flash*/ -#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 259 -#define MTDIDS_DEFAULT "nor0=ml507-flash" -#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" +#define CONFIG_SYS_FLASH_SIZE (128*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define MTDIDS_DEFAULT "nor0=flash" +#define MTDPARTS_DEFAULT "mtdparts=flash:-(user)" /*Generic Configs*/ #include -- cgit v0.10.2 From 6a2c1aaae7de22b4892ba0a12159bec346f87f0d Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:15 +0100 Subject: ppc: xilinx-ppc4xx-generic: Update xparameters.h -Remove UART address (It is now part of the dts). -Include dummy ns16550 clock -Fix address to last test Signed-off-by: Ricardo Ribalda Delgado Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h index e610407..90fe969 100644 --- a/board/xilinx/ppc405-generic/xparameters.h +++ b/board/xilinx/ppc405-generic/xparameters.h @@ -14,12 +14,12 @@ #define XPAR_IIC_EEPROM_BASEADDR 0x81600000 #define XPAR_INTC_0_BASEADDR 0x81800000 #define XPAR_SPI_0_BASEADDR 0x83400000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 #define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 #define XPAR_SPI_0_NUM_TRANSFER_BITS 8 +#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 #endif diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h index 3c135ec..e307de9 100644 --- a/board/xilinx/ppc440-generic/xparameters.h +++ b/board/xilinx/ppc440-generic/xparameters.h @@ -12,12 +12,12 @@ #define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 #define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_INTC_0_BASEADDR 0x87000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000 #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 +#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 #endif diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index 876750b..c5579e1 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -109,6 +109,7 @@ #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } #else #ifdef XPAR_UARTNS550_0_BASEADDR +#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 4 #define CONFIG_CONS_INDEX 1 -- cgit v0.10.2 From 1cc174d40f975203fa59dad7ef76da9662d18643 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 12:40:37 +0100 Subject: microblaze: Remove CONSOLE_ARG Take it from DT instead. Signed-off-by: Michal Simek diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index f93861d..64248a8 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -37,7 +37,6 @@ # define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR # define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE # define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } -# define CONSOLE_ARG "console=console=ttyUL0,115200\0" #elif XILINX_UART16550_BASEADDR # define CONFIG_SYS_NS16550_SERIAL # if defined(__MICROBLAZEEL__) @@ -54,7 +53,6 @@ /* The following table includes the supported baudrates */ # define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -# define CONSOLE_ARG "console=console=ttyS0,115200\0" #else # error Undefined uart #endif -- cgit v0.10.2 From 67659e2e94b6f8d3d1352a14c9262d79a1200252 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 12:42:16 +0100 Subject: microblaze: Move baudrate setting out driver selection Preparation of moving to DM. Uartlite ignores baudrate setting. Signed-off-by: Michal Simek diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 64248a8..10ac832 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -32,11 +32,14 @@ #endif /* uart */ +# define CONFIG_BAUDRATE 115200 +/* The following table includes the supported baudrates */ +# define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + #ifdef XILINX_UARTLITE_BASEADDR # define CONFIG_XILINX_UARTLITE # define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR -# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE -# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } #elif XILINX_UART16550_BASEADDR # define CONFIG_SYS_NS16550_SERIAL # if defined(__MICROBLAZEEL__) @@ -48,11 +51,6 @@ # define CONFIG_SYS_NS16550_COM1 \ ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) # define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ -# define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -# define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} #else # error Undefined uart #endif -- cgit v0.10.2 From 93768393d71871e4638d613acfdad6ef3cf62561 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 1 Dec 2015 14:24:20 +0100 Subject: serial: uartlite: Move driver to DM Enable SPL DM too. Signed-off-by: Michal Simek Reviewed-by: Thomas Chou diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 604f681..30ea484 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC select SUPPORT_SPL select OF_CONTROL select DM + select DM_SERIAL endchoice diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index ed336e6..6b038b8 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -1,5 +1,6 @@ CONFIG_MICROBLAZE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_DM=y CONFIG_TARGET_MICROBLAZE_GENERIC=y CONFIG_SYS_TEXT_BASE=0x29000000 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" @@ -7,4 +8,5 @@ CONFIG_SPL=y CONFIG_SYS_PROMPT="U-Boot-mONStR> " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/doc/device-tree-bindings/serial/xilinx_uartlite.txt b/doc/device-tree-bindings/serial/xilinx_uartlite.txt new file mode 100644 index 0000000..d15753c --- /dev/null +++ b/doc/device-tree-bindings/serial/xilinx_uartlite.txt @@ -0,0 +1,13 @@ +Binding for Xilinx Uartlite Controller + +Required properties: +- compatible : should be "xlnx,xps-uartlite-1.00.a", or "xlnx,opb-uartlite-1.00.b" +- reg: Should contain UART controller registers location and length. +- interrupts: Should contain UART controller interrupts. + +Example: + serial@40600000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + interrupts = <1 0>; + reg = <0x40600000 0x10000>; + }; diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt index c933b90..e5e482e 100644 --- a/doc/driver-model/serial-howto.txt +++ b/doc/driver-model/serial-howto.txt @@ -15,7 +15,6 @@ is time for maintainers to start converting over the remaining serial drivers: serial_pxa.c serial_s3c24x0.c serial_sa1100.c - serial_xuartlite.c usbtty.c You should complete this by the end of January 2016. diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 988438e..157e14d 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008-2011 Michal Simek + * (C) Copyright 2008 - 2015 Michal Simek * Clean driver and add xilinx constant from header file * * (C) Copyright 2004 Atmark Techno, Inc. @@ -10,13 +10,17 @@ #include #include +#include #include #include #include -#define SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */ -#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ -#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +DECLARE_GLOBAL_DATA_PTR; + +#define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */ +#define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */ +#define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */ +#define SR_RX_FIFO_FULL BIT(1) /* receive FIFO full */ #define ULITE_CONTROL_RST_TX 0x01 #define ULITE_CONTROL_RST_RX 0x02 @@ -28,135 +32,85 @@ struct uartlite { unsigned int control; }; -static struct uartlite *userial_ports[4] = { -#ifdef XILINX_UARTLITE_BASEADDR - [0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR, -#endif -#ifdef XILINX_UARTLITE_BASEADDR1 - [1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1, -#endif -#ifdef XILINX_UARTLITE_BASEADDR2 - [2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2, -#endif -#ifdef XILINX_UARTLITE_BASEADDR3 - [3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3 -#endif +struct uartlite_platdata { + struct uartlite *regs; }; -static void uartlite_serial_putc(const char c, const int port) +static int uartlite_serial_putc(struct udevice *dev, const char ch) { - struct uartlite *regs = userial_ports[port]; + struct uartlite_platdata *plat = dev_get_platdata(dev); + struct uartlite *regs = plat->regs; - if (c == '\n') - uartlite_serial_putc('\r', port); + if (in_be32(®s->status) & SR_TX_FIFO_FULL) + return -EAGAIN; - while (in_be32(®s->status) & SR_TX_FIFO_FULL) - ; - out_be32(®s->tx_fifo, c & 0xff); -} + out_be32(®s->tx_fifo, ch & 0xff); -static void uartlite_serial_puts(const char *s, const int port) -{ - while (*s) - uartlite_serial_putc(*s++, port); + return 0; } -static int uartlite_serial_getc(const int port) +static int uartlite_serial_getc(struct udevice *dev) { - struct uartlite *regs = userial_ports[port]; + struct uartlite_platdata *plat = dev_get_platdata(dev); + struct uartlite *regs = plat->regs; + + if (!(in_be32(®s->status) & SR_RX_FIFO_VALID_DATA)) + return -EAGAIN; - while (!(in_be32(®s->status) & SR_RX_FIFO_VALID_DATA)) - ; return in_be32(®s->rx_fifo) & 0xff; } -static int uartlite_serial_tstc(const int port) +static int uartlite_serial_pending(struct udevice *dev, bool input) { - struct uartlite *regs = userial_ports[port]; + struct uartlite_platdata *plat = dev_get_platdata(dev); + struct uartlite *regs = plat->regs; - return in_be32(®s->status) & SR_RX_FIFO_VALID_DATA; + if (input) + return in_be32(®s->status) & SR_RX_FIFO_VALID_DATA; + + return !(in_be32(®s->status) & SR_TX_FIFO_EMPTY); } -static int uartlite_serial_init(const int port) +static int uartlite_serial_probe(struct udevice *dev) { - struct uartlite *regs = userial_ports[port]; - - if (regs) { - out_be32(®s->control, 0); - out_be32(®s->control, - ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); - in_be32(®s->control); - return 0; - } + struct uartlite_platdata *plat = dev_get_platdata(dev); + struct uartlite *regs = plat->regs; - return -1; -} + out_be32(®s->control, 0); + out_be32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); + in_be32(®s->control); -/* Multi serial device functions */ -#define DECLARE_ESERIAL_FUNCTIONS(port) \ - static int userial##port##_init(void) \ - { return uartlite_serial_init(port); } \ - static void userial##port##_setbrg(void) {} \ - static int userial##port##_getc(void) \ - { return uartlite_serial_getc(port); } \ - static int userial##port##_tstc(void) \ - { return uartlite_serial_tstc(port); } \ - static void userial##port##_putc(const char c) \ - { uartlite_serial_putc(c, port); } \ - static void userial##port##_puts(const char *s) \ - { uartlite_serial_puts(s, port); } - -/* Serial device descriptor */ -#define INIT_ESERIAL_STRUCTURE(port, __name) { \ - .name = __name, \ - .start = userial##port##_init, \ - .stop = NULL, \ - .setbrg = userial##port##_setbrg, \ - .getc = userial##port##_getc, \ - .tstc = userial##port##_tstc, \ - .putc = userial##port##_putc, \ - .puts = userial##port##_puts, \ + return 0; } -DECLARE_ESERIAL_FUNCTIONS(0); -struct serial_device uartlite_serial0_device = - INIT_ESERIAL_STRUCTURE(0, "ttyUL0"); -DECLARE_ESERIAL_FUNCTIONS(1); -struct serial_device uartlite_serial1_device = - INIT_ESERIAL_STRUCTURE(1, "ttyUL1"); -DECLARE_ESERIAL_FUNCTIONS(2); -struct serial_device uartlite_serial2_device = - INIT_ESERIAL_STRUCTURE(2, "ttyUL2"); -DECLARE_ESERIAL_FUNCTIONS(3); -struct serial_device uartlite_serial3_device = - INIT_ESERIAL_STRUCTURE(3, "ttyUL3"); - -__weak struct serial_device *default_serial_console(void) +static int uartlite_serial_ofdata_to_platdata(struct udevice *dev) { - if (userial_ports[0]) - return &uartlite_serial0_device; - if (userial_ports[1]) - return &uartlite_serial1_device; - if (userial_ports[2]) - return &uartlite_serial2_device; - if (userial_ports[3]) - return &uartlite_serial3_device; - - return NULL; -} + struct uartlite_platdata *plat = dev_get_platdata(dev); -void uartlite_serial_initialize(void) -{ -#ifdef XILINX_UARTLITE_BASEADDR - serial_register(&uartlite_serial0_device); -#endif /* XILINX_UARTLITE_BASEADDR */ -#ifdef XILINX_UARTLITE_BASEADDR1 - serial_register(&uartlite_serial1_device); -#endif /* XILINX_UARTLITE_BASEADDR1 */ -#ifdef XILINX_UARTLITE_BASEADDR2 - serial_register(&uartlite_serial2_device); -#endif /* XILINX_UARTLITE_BASEADDR2 */ -#ifdef XILINX_UARTLITE_BASEADDR3 - serial_register(&uartlite_serial3_device); -#endif /* XILINX_UARTLITE_BASEADDR3 */ + plat->regs = (struct uartlite *)dev_get_addr(dev); + + return 0; } + +static const struct dm_serial_ops uartlite_serial_ops = { + .putc = uartlite_serial_putc, + .pending = uartlite_serial_pending, + .getc = uartlite_serial_getc, +}; + +static const struct udevice_id uartlite_serial_ids[] = { + { .compatible = "xlnx,opb-uartlite-1.00.b", }, + { .compatible = "xlnx,xps-uartlite-1.00.a" }, + { } +}; + +U_BOOT_DRIVER(serial_uartlite) = { + .name = "serial_uartlite", + .id = UCLASS_SERIAL, + .of_match = uartlite_serial_ids, + .ofdata_to_platdata = uartlite_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct uartlite_platdata), + .probe = uartlite_serial_probe, + .ops = &uartlite_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v0.10.2 From 4166ba3b2351aa72c372f66a54e9fb92cffbd230 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 14 Dec 2015 16:55:10 +0100 Subject: serial: uartlite: Add support for debug console Add support for debug console. Signed-off-by: Michal Simek Reviewed-by: Thomas Chou diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 83068cf..e78c5d3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -112,6 +112,13 @@ config DEBUG_UART_S5P will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running. +config DEBUG_UART_UARTLITE + bool "Xilinx Uartlite" + help + Select this to enable a debug UART using the serial_uartlite driver. + You will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_ZYNQ bool "Xilinx Zynq" help diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 157e14d..a2e9303 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -114,3 +114,29 @@ U_BOOT_DRIVER(serial_uartlite) = { .ops = &uartlite_serial_ops, .flags = DM_FLAG_PRE_RELOC, }; + +#ifdef CONFIG_DEBUG_UART_UARTLITE + +#include + +static inline void _debug_uart_init(void) +{ + struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE; + + out_be32(®s->control, 0); + out_be32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); + in_be32(®s->control); +} + +static inline void _debug_uart_putc(int ch) +{ + struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE; + + while (in_be32(®s->status) & SR_TX_FIFO_FULL) + ; + + out_be32(®s->tx_fifo, ch & 0xff); +} + +DEBUG_UART_FUNCS +#endif -- cgit v0.10.2 From 54e24d33324a1a4599d9f830a8671a61c45300fc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 12:50:05 +0100 Subject: serial: uartlite: Add uartlite to Kconfig - Move config option out of board file. - Remove uartlite address from config file Signed-off-by: Michal Simek Reviewed-by: Thomas Chou diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 8ba146c..11b3c9a 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -28,10 +28,6 @@ #define XILINX_TIMER_BASEADDR 0x41c00000 #define XILINX_TIMER_IRQ 0 -/* Uart pheriphery is RS232_Uart */ -#define XILINX_UARTLITE_BASEADDR 0x40600000 -#define XILINX_UARTLITE_BAUDRATE 115200 - /* IIC pheriphery is IIC_EEPROM */ #define XILINX_IIC_0_BASEADDR 0x40800000 #define XILINX_IIC_0_FREQ 100000 diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 6b038b8..dc4ac05 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -10,3 +10,4 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_XILINX_UARTLITE=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index e78c5d3..5c7b1fa 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -278,4 +278,11 @@ config UNIPHIER_SERIAL If you have a UniPhier based board and want to use the on-chip serial ports, say Y to this option. If unsure, say N. +config XILINX_UARTLITE + bool "Xilinx Uarlite support" + depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) + help + If you have a Xilinx based board and want to use the uartlite + serial ports, say Y to this option. If unsure, say N. + endmenu diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 10ac832..6e3c80b 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -37,10 +37,7 @@ # define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -#ifdef XILINX_UARTLITE_BASEADDR -# define CONFIG_XILINX_UARTLITE -# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR -#elif XILINX_UART16550_BASEADDR +#if XILINX_UART16550_BASEADDR # define CONFIG_SYS_NS16550_SERIAL # if defined(__MICROBLAZEEL__) # define CONFIG_SYS_NS16550_REG_SIZE -4 @@ -51,8 +48,6 @@ # define CONFIG_SYS_NS16550_COM1 \ ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) # define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ -#else -# error Undefined uart #endif /* setting reset address */ -- cgit v0.10.2 From f0e353ce5538367aa4c61a60702723f32e7c5cfb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 12:50:05 +0100 Subject: microblaze: Enable uart16550 DM by default Microblaze is uses uartlite or uart16550 as console drivers. Signed-off-by: Michal Simek diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index dc4ac05..0947c46 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -10,4 +10,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_SYS_NS16550=y CONFIG_XILINX_UARTLITE=y diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 6e3c80b..19d5506 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -37,19 +37,6 @@ # define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -#if XILINX_UART16550_BASEADDR -# define CONFIG_SYS_NS16550_SERIAL -# if defined(__MICROBLAZEEL__) -# define CONFIG_SYS_NS16550_REG_SIZE -4 -# else -# define CONFIG_SYS_NS16550_REG_SIZE 4 -# endif -# define CONFIG_CONS_INDEX 1 -# define CONFIG_SYS_NS16550_COM1 \ - ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) -# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ -#endif - /* setting reset address */ /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ -- cgit v0.10.2 From 062f078c3b44703e2e593df16e0e6d1d9935ea1c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 Dec 2015 15:39:24 +0100 Subject: microblaze: Do not print eth device when DM_ETH is enabled Doing the same fix as is done for ARM by: "Avoid calling print_eths() with driver model" (sha1: ff97380015b6b5d7d6267417a1cd6fc0e67b81bc) Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index deed6d8..8eda68b 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -205,7 +205,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_num("sram start ", (ulong)bd->bi_sramstart); print_num("sram size ", (ulong)bd->bi_sramsize); #endif -#if defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH) print_eths(); #endif printf("baudrate = %u bps\n", gd->baudrate); -- cgit v0.10.2 From 9040f4eeb9ccba084197261a72983a4bf5cdbd1e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 Dec 2015 15:01:31 +0100 Subject: microblaze: Enable PHYLIB via Kconfig Cleanup board configuration. Signed-off-by: Michal Simek diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 0947c46..fe731d0 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -10,5 +10,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_PHYLIB=y CONFIG_SYS_NS16550=y CONFIG_XILINX_UARTLITE=y diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 19d5506..f1525f5 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -336,7 +336,6 @@ # define CONFIG_CMD_MII 1 # define CONFIG_PHY_GIGE 1 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 -# define CONFIG_PHYLIB 1 # define CONFIG_PHY_ATHEROS 1 # define CONFIG_PHY_BROADCOM 1 # define CONFIG_PHY_DAVICOM 1 @@ -349,7 +348,6 @@ #else # undef CONFIG_MII # undef CONFIG_CMD_MII -# undef CONFIG_PHYLIB #endif /* SPL part */ -- cgit v0.10.2 From 576e95b428dbe4c8af9f21559d23333e4f134f9c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 13:02:10 +0100 Subject: microblaze: Remove unused I2C macros There is no i2c driver in the current u-boot. Signed-off-by: Michal Simek diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 11b3c9a..79c87fb 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -28,11 +28,6 @@ #define XILINX_TIMER_BASEADDR 0x41c00000 #define XILINX_TIMER_IRQ 0 -/* IIC pheriphery is IIC_EEPROM */ -#define XILINX_IIC_0_BASEADDR 0x40800000 -#define XILINX_IIC_0_FREQ 100000 -#define XILINX_IIC_0_BIT 0 - /* GPIO is LEDs_4Bit*/ #define XILINX_GPIO_BASEADDR 0x40000000 -- cgit v0.10.2 From 48470b7a20166a0b829d357dad7d6d557b95a1cc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 12:55:39 +0100 Subject: microblaze: Wire-up debug_uart in asm Signed-off-by: Michal Simek diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 206be3e..e9923b6 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -155,6 +155,10 @@ clear_bss: cmp r6, r5, r4 /* check if we have reach the end */ bnei r6, 2b 3: /* jumping to board_init */ +#ifdef CONFIG_DEBUG_UART + bralid r15, debug_uart_init + nop +#endif #ifndef CONFIG_SPL_BUILD or r5, r0, r0 /* flags - empty */ addi r31, r0, _gd -- cgit v0.10.2 From 2014a3debc4c35069d6bda04bfe53539a7e2a6d4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 14 Jan 2016 09:15:33 +0100 Subject: microblaze: Enable MICREL_KSZ9021 To solve enabling ETH_DM where ksz90x1_reg_field is defined only when additional Micrel type is defined. Signed-off-by: Michal Simek diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index f1525f5..30ebff3 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -342,6 +342,7 @@ # define CONFIG_PHY_LXT 1 # define CONFIG_PHY_MARVELL 1 # define CONFIG_PHY_MICREL 1 +# define CONFIG_PHY_MICREL_KSZ9021 # define CONFIG_PHY_NATSEMI 1 # define CONFIG_PHY_REALTEK 1 # define CONFIG_PHY_VITESSE 1 -- cgit v0.10.2 From 3e3f8ba26e32191659fec2804cdba29d24cf9d6d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Oct 2015 11:00:47 +0100 Subject: net: axi_emac: Fix parentheses around operand ! Fix these compilation warning by proper grouping: In function 'axi_dma_init': drivers/net/xilinx_axi_emac.c:391:7: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses] if (!(in_be32(&priv->dmatx->control) | ^ In function 'axiemac_send': drivers/net/xilinx_axi_emac.c:501:21: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses] while (timeout && (!in_be32(&priv->dmatx->status) & Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index df053fe..994affa 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -388,9 +388,9 @@ static void axi_dma_init(struct eth_device *dev) while (timeout--) { /* Check transmit/receive channel */ /* Reset is done when the reset bit is low */ - if (!(in_be32(&priv->dmatx->control) | + if (!((in_be32(&priv->dmatx->control) | in_be32(&priv->dmarx->control)) - & XAXIDMA_CR_RESET_MASK) { + & XAXIDMA_CR_RESET_MASK)) { break; } } @@ -498,8 +498,8 @@ static int axiemac_send(struct eth_device *dev, void *ptr, int len) /* Wait for transmission to complete */ debug("axiemac: Waiting for tx to be done\n"); timeout = 200; - while (timeout && (!in_be32(&priv->dmatx->status) & - (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) { + while (timeout && (!(in_be32(&priv->dmatx->status) & + (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) { timeout--; udelay(1); } -- cgit v0.10.2 From 2652a6219f975d47cc295f1e060fa54da84d761b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 10:54:53 +0100 Subject: net: axi_emac: Show phy address instead of register content Fix debug message. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 994affa..f088230 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -243,7 +243,7 @@ static int setup_phy(struct eth_device *dev) /* Found a valid PHY address */ priv->phyaddr = i; debug("axiemac: Found valid phy address, %x\n", - phyreg); + i); break; } } -- cgit v0.10.2 From f36bbcceba2891bec17add339c7ff3241c3f6d94 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 14:36:31 +0100 Subject: net: axi_emac: Pass directly pointer to register space Simplify mdio_wait function by passing regs directly. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index f088230..071e0a8 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -147,9 +147,8 @@ struct axi_regs { */ #define PHY_DETECT_MASK 0x1808 -static inline int mdio_wait(struct eth_device *dev) +static inline int mdio_wait(struct axi_regs *regs) { - struct axi_regs *regs = (struct axi_regs *)dev->iobase; u32 timeout = 200; /* Wait till MDIO interface is ready to accept a new transaction. */ @@ -171,7 +170,7 @@ static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, struct axi_regs *regs = (struct axi_regs *)dev->iobase; u32 mdioctrlreg = 0; - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & @@ -183,7 +182,7 @@ static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, out_be32(®s->mdio_mcr, mdioctrlreg); - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; /* Read data */ @@ -197,7 +196,7 @@ static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, struct axi_regs *regs = (struct axi_regs *)dev->iobase; u32 mdioctrlreg = 0; - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & @@ -212,7 +211,7 @@ static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, out_be32(®s->mdio_mcr, mdioctrlreg); - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; return 0; -- cgit v0.10.2 From 6609f35b9386f54af1c2ea43a4eb75fce3dc648f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 14:39:42 +0100 Subject: net: axi_emac: Put iobase to private structure Saving iobase directly to private structure helps with moving to DM. There is an option to load iobase from pdata but it is additional load. Pointer to private structure is available all the time. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 071e0a8..3c98065 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -86,7 +86,7 @@ struct axidma_priv { struct axidma_reg *dmatx; struct axidma_reg *dmarx; int phyaddr; - + struct axi_regs *iobase; struct phy_device *phydev; struct mii_dev *bus; }; @@ -223,7 +223,7 @@ static int setup_phy(struct eth_device *dev) u16 phyreg; u32 i, speed, emmc_reg, ret; struct axidma_priv *priv = dev->priv; - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct axi_regs *regs = priv->iobase; struct phy_device *phydev; u32 supported = SUPPORTED_10baseT_Half | @@ -629,6 +629,7 @@ int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, sprintf(dev->name, "aximac.%lx", base_addr); dev->iobase = base_addr; + priv->iobase = (struct axi_regs *)base_addr; priv->dmatx = (struct axidma_reg *)dma_addr; /* RX channel offset is 0x30 */ priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30); -- cgit v0.10.2 From 0d78abf5ba68e579c5851959565c1049d14af2a0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 14:44:38 +0100 Subject: net: axi_emac: Pass private structure to phyread/phywrite Prepare for move to DM. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 3c98065..20ff6b0 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -164,10 +164,10 @@ static inline int mdio_wait(struct axi_regs *regs) return 0; } -static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, - u16 *val) +static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, + u16 *val) { - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct axi_regs *regs = priv->iobase; u32 mdioctrlreg = 0; if (mdio_wait(regs)) @@ -190,10 +190,10 @@ static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, return 0; } -static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, - u32 data) +static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, + u32 data) { - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct axi_regs *regs = priv->iobase; u32 mdioctrlreg = 0; if (mdio_wait(regs)) @@ -236,7 +236,7 @@ static int setup_phy(struct eth_device *dev) if (priv->phyaddr == -1) { /* Detect the PHY address */ for (i = 31; i >= 0; i--) { - ret = phyread(dev, i, PHY_DETECT_REG, &phyreg); + ret = phyread(priv, i, PHY_DETECT_REG, &phyreg); if (!ret && (phyreg != 0xFFFF) && ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { /* Found a valid PHY address */ @@ -589,7 +589,7 @@ static int axiemac_miiphy_read(const char *devname, uchar addr, struct eth_device *dev = eth_get_dev(); u32 ret; - ret = phyread(dev, addr, reg, val); + ret = phyread(dev->priv, addr, reg, val); debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); return ret; } @@ -600,7 +600,7 @@ static int axiemac_miiphy_write(const char *devname, uchar addr, struct eth_device *dev = eth_get_dev(); debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); - return phywrite(dev, addr, reg, val); + return phywrite(dev->priv, addr, reg, val); } static int axiemac_bus_reset(struct mii_dev *bus) -- cgit v0.10.2 From f09854810cf99c0bf3a31a5d26b4c556186ea302 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 14:53:51 +0100 Subject: net: axi_emac: Pass private structure where possible Use axidma_priv instead of ethdevice in preparation of the DM move. Signed-off-by: Michal Simek diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 20ff6b0..77b1869 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -315,9 +315,9 @@ static void axiemac_halt(struct eth_device *dev) debug("axiemac: Halted\n"); } -static int axi_ethernet_init(struct eth_device *dev) +static int axi_ethernet_init(struct axidma_priv *priv) { - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct axi_regs *regs = priv->iobase; u32 timeout = 200; /* @@ -374,9 +374,8 @@ static int axiemac_setup_mac(struct eth_device *dev) } /* Reset DMA engine */ -static void axi_dma_init(struct eth_device *dev) +static void axi_dma_init(struct axidma_priv *priv) { - struct axidma_priv *priv = dev->priv; u32 timeout = 500; /* Reset the engine so the hardware starts from a known state */ @@ -410,10 +409,10 @@ static int axiemac_init(struct eth_device *dev, bd_t * bis) * reset, and since AXIDMA reset line is connected to AxiEthernet, this * would ensure a reset of AxiEthernet. */ - axi_dma_init(dev); + axi_dma_init(priv); /* Initialize AxiEthernet hardware. */ - if (axi_ethernet_init(dev)) + if (axi_ethernet_init(priv)) return -1; /* Disable all RX interrupts before RxBD space setup */ @@ -511,10 +510,9 @@ static int axiemac_send(struct eth_device *dev, void *ptr, int len) return 0; } -static int isrxready(struct eth_device *dev) +static int isrxready(struct axidma_priv *priv) { u32 status; - struct axidma_priv *priv = dev->priv; /* Read pending interrupts */ status = in_be32(&priv->dmarx->status); @@ -539,7 +537,7 @@ static int axiemac_recv(struct eth_device *dev) u32 temp; /* Wait for an incoming packet */ - if (!isrxready(dev)) + if (!isrxready(priv)) return 0; debug("axiemac: RX data ready\n"); -- cgit v0.10.2 From 75cc93fad73897896511f08c1529233484ff063c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 Dec 2015 15:44:41 +0100 Subject: net: axi_emac: Move driver to DM Move driver to DM. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index dfa6293..a3122da 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -105,11 +105,6 @@ int board_eth_init(bd_t *bis) { int ret = 0; -#ifdef CONFIG_XILINX_AXIEMAC - ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, - XILINX_AXIDMA_BASEADDR); -#endif - #if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR) u32 txpp = 0; u32 rxpp = 0; diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 414f530..427e754 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -103,10 +103,6 @@ int board_eth_init(bd_t *bis) { u32 ret = 0; -#ifdef CONFIG_XILINX_AXIEMAC - ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, - XILINX_AXIDMA_BASEADDR); -#endif #ifdef CONFIG_XILINX_EMACLITE u32 txpp = 0; u32 rxpp = 0; diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 77b1869..c03f8f7 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -8,12 +8,15 @@ #include #include +#include #include #include #include #include #include +DECLARE_GLOBAL_DATA_PTR; + #if !defined(CONFIG_PHYLIB) # error AXI_ETHERNET requires PHYLIB #endif @@ -87,6 +90,7 @@ struct axidma_priv { struct axidma_reg *dmarx; int phyaddr; struct axi_regs *iobase; + phy_interface_t interface; struct phy_device *phydev; struct mii_dev *bus; }; @@ -218,11 +222,11 @@ static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, } /* Setting axi emac and phy to proper setting */ -static int setup_phy(struct eth_device *dev) +static int setup_phy(struct udevice *dev) { u16 phyreg; u32 i, speed, emmc_reg, ret; - struct axidma_priv *priv = dev->priv; + struct axidma_priv *priv = dev_get_priv(dev); struct axi_regs *regs = priv->iobase; struct phy_device *phydev; @@ -298,9 +302,9 @@ static int setup_phy(struct eth_device *dev) } /* STOP DMA transfers */ -static void axiemac_halt(struct eth_device *dev) +static void axiemac_halt(struct udevice *dev) { - struct axidma_priv *priv = dev->priv; + struct axidma_priv *priv = dev_get_priv(dev); u32 temp; /* Stop the hardware */ @@ -358,16 +362,18 @@ static int axi_ethernet_init(struct axidma_priv *priv) return 0; } -static int axiemac_setup_mac(struct eth_device *dev) +static int axiemac_setup_mac(struct udevice *dev) { - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct axidma_priv *priv = dev_get_priv(dev); + struct axi_regs *regs = priv->iobase; /* Set the MAC address */ - int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) | - (dev->enetaddr[1] << 8) | (dev->enetaddr[0])); + int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | + (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); out_be32(®s->uaw0, val); - val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ; + val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4]; val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; out_be32(®s->uaw1, val); return 0; @@ -396,10 +402,10 @@ static void axi_dma_init(struct axidma_priv *priv) printf("%s: Timeout\n", __func__); } -static int axiemac_init(struct eth_device *dev, bd_t * bis) +static int axiemac_init(struct udevice *dev) { - struct axidma_priv *priv = dev->priv; - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct axidma_priv *priv = dev_get_priv(dev); + struct axi_regs *regs = priv->iobase; u32 temp; debug("axiemac: Init started\n"); @@ -458,9 +464,9 @@ static int axiemac_init(struct eth_device *dev, bd_t * bis) return 0; } -static int axiemac_send(struct eth_device *dev, void *ptr, int len) +static int axiemac_send(struct udevice *dev, void *ptr, int len) { - struct axidma_priv *priv = dev->priv; + struct axidma_priv *priv = dev_get_priv(dev); u32 timeout; if (len > PKTSIZE_ALIGN) @@ -530,15 +536,15 @@ static int isrxready(struct axidma_priv *priv) return 0; } -static int axiemac_recv(struct eth_device *dev) +static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) { u32 length; - struct axidma_priv *priv = dev->priv; + struct axidma_priv *priv = dev_get_priv(dev); u32 temp; /* Wait for an incoming packet */ if (!isrxready(priv)) - return 0; + return -1; debug("axiemac: RX data ready\n"); @@ -578,77 +584,125 @@ static int axiemac_recv(struct eth_device *dev) debug("axiemac: RX completed, framelength = %d\n", length); - return length; + return 0; } -static int axiemac_miiphy_read(const char *devname, uchar addr, - uchar reg, ushort *val) +static int axiemac_miiphy_read(struct mii_dev *bus, int addr, + int devad, int reg) { - struct eth_device *dev = eth_get_dev(); - u32 ret; + int ret; + u16 value; - ret = phyread(dev->priv, addr, reg, val); - debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); - return ret; + ret = phyread(bus->priv, addr, reg, &value); + debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, + value, ret); + return value; } -static int axiemac_miiphy_write(const char *devname, uchar addr, - uchar reg, ushort val) +static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) { - struct eth_device *dev = eth_get_dev(); - - debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); - return phywrite(dev->priv, addr, reg, val); + debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); + return phywrite(bus->priv, addr, reg, value); } -static int axiemac_bus_reset(struct mii_dev *bus) +static int axi_emac_probe(struct udevice *dev) { - debug("axiemac: Bus reset\n"); + struct axidma_priv *priv = dev_get_priv(dev); + int ret; + + priv->bus = mdio_alloc(); + priv->bus->read = axiemac_miiphy_read; + priv->bus->write = axiemac_miiphy_write; + priv->bus->priv = priv; + strcpy(priv->bus->name, "axi_emac"); + + ret = mdio_register(priv->bus); + if (ret) + return ret; + return 0; } -int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, - unsigned long dma_addr) +static int axi_emac_remove(struct udevice *dev) { - struct eth_device *dev; - struct axidma_priv *priv; + struct axidma_priv *priv = dev_get_priv(dev); - dev = calloc(1, sizeof(struct eth_device)); - if (dev == NULL) - return -1; + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); - dev->priv = calloc(1, sizeof(struct axidma_priv)); - if (dev->priv == NULL) { - free(dev); - return -1; - } - priv = dev->priv; + return 0; +} - sprintf(dev->name, "aximac.%lx", base_addr); +static const struct eth_ops axi_emac_ops = { + .start = axiemac_init, + .send = axiemac_send, + .recv = axiemac_recv, + .stop = axiemac_halt, + .write_hwaddr = axiemac_setup_mac, +}; - dev->iobase = base_addr; - priv->iobase = (struct axi_regs *)base_addr; - priv->dmatx = (struct axidma_reg *)dma_addr; +static int axi_emac_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct axidma_priv *priv = dev_get_priv(dev); + int offset = 0; + const char *phy_mode; + + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + priv->iobase = (struct axi_regs *)pdata->iobase; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "axistream-connected"); + if (offset <= 0) { + printf("%s: axistream is not found\n", __func__); + return -EINVAL; + } + priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob, + offset, "reg", 0); + if (!priv->dmatx) { + printf("%s: axi_dma register space not found\n", __func__); + return -EINVAL; + } /* RX channel offset is 0x30 */ - priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30); - dev->init = axiemac_init; - dev->halt = axiemac_halt; - dev->send = axiemac_send; - dev->recv = axiemac_recv; - dev->write_hwaddr = axiemac_setup_mac; - -#ifdef CONFIG_PHY_ADDR - priv->phyaddr = CONFIG_PHY_ADDR; -#else + priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30); + priv->phyaddr = -1; -#endif - eth_register(dev); + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy-handle"); + if (offset > 0) + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + priv->interface = pdata->phy_interface; -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write); - priv->bus = miiphy_get_dev_by_name(dev->name); - priv->bus->reset = axiemac_bus_reset; -#endif - return 1; + printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, + priv->phyaddr, phy_string_for_interface(priv->interface)); + + return 0; } + +static const struct udevice_id axi_emac_ids[] = { + { .compatible = "xlnx,axi-ethernet-1.00.a" }, + { } +}; + +U_BOOT_DRIVER(axi_emac) = { + .name = "axi_emac", + .id = UCLASS_ETH, + .of_match = axi_emac_ids, + .ofdata_to_platdata = axi_emac_ofdata_to_platdata, + .probe = axi_emac_probe, + .remove = axi_emac_remove, + .ops = &axi_emac_ops, + .priv_auto_alloc_size = sizeof(struct axidma_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/include/netdev.h b/include/netdev.h index de74b9a..b8d4e6a 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -80,8 +80,6 @@ int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); int armada100_fec_register(unsigned long base_addr); -int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, - unsigned long dma_addr); int xilinx_emaclite_of_init(const void *blob); int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp); -- cgit v0.10.2 From 5d0449d4c74ad310373bb90691b9258e8ff12c2c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 Dec 2015 16:10:05 +0100 Subject: net: axi_emac: Enable access to MDIO in probe Detect phy when driver probes. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index c03f8f7..172ccc5 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -221,11 +221,10 @@ static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, return 0; } -/* Setting axi emac and phy to proper setting */ -static int setup_phy(struct udevice *dev) +static int axiemac_phy_init(struct udevice *dev) { u16 phyreg; - u32 i, speed, emmc_reg, ret; + u32 i, ret; struct axidma_priv *priv = dev_get_priv(dev); struct axi_regs *regs = priv->iobase; struct phy_device *phydev; @@ -237,6 +236,9 @@ static int setup_phy(struct udevice *dev) SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full; + /* Set default MDIO divisor */ + out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); + if (priv->phyaddr == -1) { /* Detect the PHY address */ for (i = 31; i >= 0; i--) { @@ -259,6 +261,18 @@ static int setup_phy(struct udevice *dev) phydev->advertising = phydev->supported; priv->phydev = phydev; phy_config(phydev); + + return 0; +} + +/* Setting axi emac and phy to proper setting */ +static int setup_phy(struct udevice *dev) +{ + u32 speed, emmc_reg; + struct axidma_priv *priv = dev_get_priv(dev); + struct axi_regs *regs = priv->iobase; + struct phy_device *phydev = priv->phydev; + if (phy_startup(phydev)) { printf("axiemac: could not initialize PHY %s\n", phydev->dev->name); @@ -621,6 +635,8 @@ static int axi_emac_probe(struct udevice *dev) if (ret) return ret; + axiemac_phy_init(dev); + return 0; } -- cgit v0.10.2 From 97d2363d206483bc4b70ca8aa4f3f003af7f431f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 14:13:23 +0100 Subject: net: axi_emac: Split recv from free_pkt Call net_process_received_packet() by core. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 172ccc5..adfee8c 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -571,9 +571,14 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) #ifdef DEBUG print_buffer(&rxframe, &rxframe[0], 1, length, 16); #endif - /* Pass the received frame up for processing */ - if (length) - net_process_received_packet(rxframe, length); + + *packetp = rxframe; + return length; +} + +static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct axidma_priv *priv = dev_get_priv(dev); #ifdef DEBUG /* It is useful to clear buffer to be sure that it is consistent */ @@ -655,6 +660,7 @@ static const struct eth_ops axi_emac_ops = { .start = axiemac_init, .send = axiemac_send, .recv = axiemac_recv, + .free_pkt = axiemac_free_pkt, .stop = axiemac_halt, .write_hwaddr = axiemac_setup_mac, }; -- cgit v0.10.2 From ad499e42be291e789585cd282cf05e29612018e6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Dec 2015 09:18:12 +0100 Subject: net: axi_emac: Rename start, stop, write_hwaddr functions Rename few functions to fit to the new name convention used by DM. Suggested-by: Joe Hershberger Signed-off-by: Michal Simek diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index adfee8c..4a514d0 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -316,7 +316,7 @@ static int setup_phy(struct udevice *dev) } /* STOP DMA transfers */ -static void axiemac_halt(struct udevice *dev) +static void axiemac_stop(struct udevice *dev) { struct axidma_priv *priv = dev_get_priv(dev); u32 temp; @@ -376,7 +376,7 @@ static int axi_ethernet_init(struct axidma_priv *priv) return 0; } -static int axiemac_setup_mac(struct udevice *dev) +static int axiemac_write_hwaddr(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct axidma_priv *priv = dev_get_priv(dev); @@ -416,7 +416,7 @@ static void axi_dma_init(struct axidma_priv *priv) printf("%s: Timeout\n", __func__); } -static int axiemac_init(struct udevice *dev) +static int axiemac_start(struct udevice *dev) { struct axidma_priv *priv = dev_get_priv(dev); struct axi_regs *regs = priv->iobase; @@ -470,7 +470,7 @@ static int axiemac_init(struct udevice *dev) /* PHY setup */ if (!setup_phy(dev)) { - axiemac_halt(dev); + axiemac_stop(dev); return -1; } @@ -657,12 +657,12 @@ static int axi_emac_remove(struct udevice *dev) } static const struct eth_ops axi_emac_ops = { - .start = axiemac_init, + .start = axiemac_start, .send = axiemac_send, .recv = axiemac_recv, .free_pkt = axiemac_free_pkt, - .stop = axiemac_halt, - .write_hwaddr = axiemac_setup_mac, + .stop = axiemac_stop, + .write_hwaddr = axiemac_write_hwaddr, }; static int axi_emac_ofdata_to_platdata(struct udevice *dev) -- cgit v0.10.2 From 338a5f2bf1f3ec543dd9c6ce0d74ebe969bc7582 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 16:54:42 +0100 Subject: net: Add axi emac to Kconfig Also add dependency on PHYLIB and MII which is required. Clean PHYLIB dependency from the driver too. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index de54ca8..ee15359 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -102,6 +102,14 @@ config PCH_GBE This MAC is present in Intel Platform Controller Hub EG20T. It supports 10/100/1000 Mbps operation. +config XILINX_AXIEMAC + depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) + select PHYLIB + select MII + bool "Xilinx AXI Ethernet" + help + This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. + config ZYNQ_GEM depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP) select PHYLIB diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 4a514d0..81274ee 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -17,10 +17,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_PHYLIB) -# error AXI_ETHERNET requires PHYLIB -#endif - /* Link setup */ #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ -- cgit v0.10.2 From 8ce6947831ba6ba5a54de004be3a8c107af73166 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 Dec 2015 14:57:33 +0100 Subject: net: emaclite: Remove ancient OF probe function Prepare for DM move. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 564205d..d3d40b1 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -360,33 +360,3 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, return 1; } - -#if CONFIG_IS_ENABLED(OF_CONTROL) -int xilinx_emaclite_of_init(const void *blob) -{ - int offset = 0; - u32 ret = 0; - u32 reg; - - do { - offset = fdt_node_offset_by_compatible(blob, offset, - "xlnx,xps-ethernetlite-1.00.a"); - if (offset != -1) { - reg = fdtdec_get_addr(blob, offset, "reg"); - if (reg != FDT_ADDR_T_NONE) { - u32 rxpp = fdtdec_get_int(blob, offset, - "xlnx,rx-ping-pong", 0); - u32 txpp = fdtdec_get_int(blob, offset, - "xlnx,tx-ping-pong", 0); - ret |= xilinx_emaclite_initialize(NULL, reg, - txpp, rxpp); - } else { - debug("EMACLITE: Can't get base address\n"); - return -1; - } - } - } while (offset != -1); - - return ret; -} -#endif diff --git a/include/netdev.h b/include/netdev.h index b8d4e6a..9fc41ab 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -80,7 +80,6 @@ int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); int armada100_fec_register(unsigned long base_addr); -int xilinx_emaclite_of_init(const void *blob); int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp); int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, -- cgit v0.10.2 From d722e8641b664d129238bef361c847a8b5504b5c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 13:33:20 +0100 Subject: net: emaclite: Add MDIO support to driver Add MDIO support before move to DM. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index d3d40b1..f5e4c02 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -10,9 +10,13 @@ #include #include #include +#include #include #include +#include +#include #include +#include #undef DEBUG @@ -46,11 +50,36 @@ /* Recv interrupt enable bit */ #define XEL_RSR_RECV_IE_MASK 0x00000008UL +/* MDIO */ +#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ +#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ +#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ +#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ + +/* MDIO Address Register Bit Masks */ +#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ +#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ +#define XEL_MDIOADDR_PHYADR_SHIFT 5 +#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ + +/* MDIO Write Data Register Bit Masks */ +#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ + +/* MDIO Read Data Register Bit Masks */ +#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ + +/* MDIO Control Register Bit Masks */ +#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ +#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ + struct xemaclite { u32 nexttxbuffertouse; /* Next TX buffer to write to */ u32 nextrxbuffertouse; /* Next RX buffer to read from */ u32 txpp; /* TX ping pong buffer */ u32 rxpp; /* RX ping pong buffer */ + int phyaddr; + struct phy_device *phydev; + struct mii_dev *bus; }; static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ @@ -107,11 +136,177 @@ static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount) *to32ptr++ = alignbuffer; } +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) +static int wait_for_bit(const char *func, u32 *reg, const u32 mask, + bool set, unsigned int timeout) +{ + u32 val; + unsigned long start = get_timer(0); + + while (1) { + val = readl(reg); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > timeout) + break; + + if (ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + + udelay(1); + } + + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", + func, reg, mask, set); + + return -ETIMEDOUT; +} + +static int mdio_wait(struct eth_device *dev) +{ + return wait_for_bit(__func__, + (u32 *)(dev->iobase + XEL_MDIOCTRL_OFFSET), + XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); +} + +static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, + u16 *data) +{ + if (mdio_wait(dev)) + return 1; + + u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET); + out_be32(dev->iobase + XEL_MDIOADDR_OFFSET, + XEL_MDIOADDR_OP_MASK | + ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); + out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, + ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); + + if (mdio_wait(dev)) + return 1; + + /* Read data */ + *data = in_be32(dev->iobase + XEL_MDIORD_OFFSET); + return 0; +} + +static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, + u16 data) +{ + if (mdio_wait(dev)) + return 1; + + /* + * Write the PHY address, register number and clear the OP bit in the + * MDIO Address register and then write the value into the MDIO Write + * Data register. Finally, set the Status bit in the MDIO Control + * register to start a MDIO write transaction. + */ + u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET); + out_be32(dev->iobase + XEL_MDIOADDR_OFFSET, + ~XEL_MDIOADDR_OP_MASK & + ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); + out_be32(dev->iobase + XEL_MDIOWR_OFFSET, data); + out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, + ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); + + if (mdio_wait(dev)) + return 1; + + return 0; +} +#endif + static void emaclite_halt(struct eth_device *dev) { debug("eth_halt\n"); } +/* Use MII register 1 (MII status register) to detect PHY */ +#define PHY_DETECT_REG 1 + +/* Mask used to verify certain PHY features (or register contents) + * in the register above: + * 0x1000: 10Mbps full duplex support + * 0x0800: 10Mbps half duplex support + * 0x0008: Auto-negotiation support + */ +#define PHY_DETECT_MASK 0x1808 + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) +static int setup_phy(struct eth_device *dev) +{ + int i; + u16 phyreg; + struct xemaclite *emaclite = dev->priv; + struct phy_device *phydev; + + u32 supported = SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full; + + if (emaclite->phyaddr != -1) { + phyread(dev, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); + if ((phyreg != 0xFFFF) && + ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + debug("Default phy address %d is valid\n", + emaclite->phyaddr); + } else { + debug("PHY address is not setup correctly %d\n", + emaclite->phyaddr); + emaclite->phyaddr = -1; + } + } + + if (emaclite->phyaddr == -1) { + /* detect the PHY address */ + for (i = 31; i >= 0; i--) { + phyread(dev, i, PHY_DETECT_REG, &phyreg); + if ((phyreg != 0xFFFF) && + ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + emaclite->phyaddr = i; + debug("emaclite: Found valid phy address, %d\n", + i); + break; + } + } + } + + /* interface - look at tsec */ + phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, + PHY_INTERFACE_MODE_MII); + /* + * Phy can support 1000baseT but device NOT that's why phydev->supported + * must be setup for 1000baseT. phydev->advertising setups what speeds + * will be used for autonegotiation where 1000baseT must be disabled. + */ + phydev->supported = supported | SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full; + phydev->advertising = supported; + emaclite->phydev = phydev; + phy_config(phydev); + phy_startup(phydev); + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return 0; + } + + /* Do not setup anything */ + return 1; +} +#endif + static int emaclite_init(struct eth_device *dev, bd_t *bis) { struct xemaclite *emaclite = dev->priv; @@ -156,6 +351,13 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, XEL_RSR_RECV_IE_MASK); +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) + out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, XEL_MDIOCTRL_MDIOEN_MASK); + if (in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET) & + XEL_MDIOCTRL_MDIOEN_MASK) + if (!setup_phy(dev)) + return -1; +#endif debug("EmacLite Initialization complete\n"); return 0; } @@ -327,6 +529,28 @@ static int emaclite_recv(struct eth_device *dev) } +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) +static int emaclite_miiphy_read(const char *devname, uchar addr, + uchar reg, ushort *val) +{ + u32 ret; + struct eth_device *dev = eth_get_dev(); + + ret = phyread(dev, addr, reg, val); + debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); + return ret; +} + +static int emaclite_miiphy_write(const char *devname, uchar addr, + uchar reg, ushort val) +{ + struct eth_device *dev = eth_get_dev(); + + debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); + return phywrite(dev, addr, reg, val); +} +#endif + int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp) { @@ -356,7 +580,21 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, dev->send = emaclite_send; dev->recv = emaclite_recv; +#ifdef CONFIG_PHY_ADDR + emaclite->phyaddr = CONFIG_PHY_ADDR; +#else + emaclite->phyaddr = -1; +#endif + eth_register(dev); +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) + miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write); + emaclite->bus = miiphy_get_dev_by_name(dev->name); + + out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, + XEL_MDIOCTRL_MDIOEN_MASK); +#endif + return 1; } -- cgit v0.10.2 From 9a23c49662b3c7b95f2b49401c546bd728af2f8c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 14:18:15 +0100 Subject: net: emaclite: Convert MDIO to use register offset Use u-boot coding style how to setup and access MDIO bus. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index f5e4c02..9d413a0 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -50,12 +50,6 @@ /* Recv interrupt enable bit */ #define XEL_RSR_RECV_IE_MASK 0x00000008UL -/* MDIO */ -#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ -#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ -#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ -#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ - /* MDIO Address Register Bit Masks */ #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ @@ -72,12 +66,36 @@ #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ +struct emaclite_regs { + u32 tx_ping; /* 0x0 - TX Ping buffer */ + u32 reserved1[504]; + u32 mdioaddr; /* 0x7e4 - MDIO Address Register */ + u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */ + u32 mdiord;/* 0x7ec - MDIO Read Data Register */ + u32 mdioctrl; /* 0x7f0 - MDIO Control Register */ + u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */ + u32 global_interrupt; /* 0x7f8 - Global interrupt enable */ + u32 tx_ping_tsr; /* 0x7fc - Tx status */ + u32 tx_pong; /* 0x800 - TX Pong buffer */ + u32 reserved2[508]; + u32 tx_pong_tplr; /* 0xff4 - Tx packet length */ + u32 reserved3; /* 0xff8 */ + u32 tx_pong_tsr; /* 0xffc - Tx status */ + u32 rx_ping; /* 0x1000 - Receive Buffer */ + u32 reserved4[510]; + u32 rx_ping_rsr; /* 0x17fc - Rx status */ + u32 rx_pong; /* 0x1800 - Receive Buffer */ + u32 reserved5[510]; + u32 rx_pong_rsr; /* 0x1ffc - Rx status */ +}; + struct xemaclite { u32 nexttxbuffertouse; /* Next TX buffer to write to */ u32 nextrxbuffertouse; /* Next RX buffer to read from */ u32 txpp; /* TX ping pong buffer */ u32 rxpp; /* RX ping pong buffer */ int phyaddr; + struct emaclite_regs *regs; struct phy_device *phydev; struct mii_dev *bus; }; @@ -169,38 +187,39 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask, return -ETIMEDOUT; } -static int mdio_wait(struct eth_device *dev) +static int mdio_wait(struct emaclite_regs *regs) { - return wait_for_bit(__func__, - (u32 *)(dev->iobase + XEL_MDIOCTRL_OFFSET), + return wait_for_bit(__func__, ®s->mdioctrl, XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); } -static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, +static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, u16 *data) { - if (mdio_wait(dev)) + struct emaclite_regs *regs = emaclite->regs; + + if (mdio_wait(regs)) return 1; - u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET); - out_be32(dev->iobase + XEL_MDIOADDR_OFFSET, - XEL_MDIOADDR_OP_MASK | + u32 ctrl_reg = in_be32(®s->mdioctrl); + out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); - out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, - ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); + out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; /* Read data */ - *data = in_be32(dev->iobase + XEL_MDIORD_OFFSET); + *data = in_be32(®s->mdiord); return 0; } -static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, +static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, u16 data) { - if (mdio_wait(dev)) + struct emaclite_regs *regs = emaclite->regs; + + if (mdio_wait(regs)) return 1; /* @@ -209,15 +228,13 @@ static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, * Data register. Finally, set the Status bit in the MDIO Control * register to start a MDIO write transaction. */ - u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET); - out_be32(dev->iobase + XEL_MDIOADDR_OFFSET, - ~XEL_MDIOADDR_OP_MASK & + u32 ctrl_reg = in_be32(®s->mdioctrl); + out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); - out_be32(dev->iobase + XEL_MDIOWR_OFFSET, data); - out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, - ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); + out_be32(®s->mdiowr, data); + out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; return 0; @@ -254,7 +271,7 @@ static int setup_phy(struct eth_device *dev) SUPPORTED_100baseT_Full; if (emaclite->phyaddr != -1) { - phyread(dev, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); + phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); if ((phyreg != 0xFFFF) && ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { /* Found a valid PHY address */ @@ -270,7 +287,7 @@ static int setup_phy(struct eth_device *dev) if (emaclite->phyaddr == -1) { /* detect the PHY address */ for (i = 31; i >= 0; i--) { - phyread(dev, i, PHY_DETECT_REG, &phyreg); + phyread(emaclite, i, PHY_DETECT_REG, &phyreg); if ((phyreg != 0xFFFF) && ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { /* Found a valid PHY address */ @@ -310,6 +327,8 @@ static int setup_phy(struct eth_device *dev) static int emaclite_init(struct eth_device *dev, bd_t *bis) { struct xemaclite *emaclite = dev->priv; + struct emaclite_regs *regs = emaclite->regs; + debug("EmacLite Initialization Started\n"); /* @@ -352,9 +371,8 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) XEL_RSR_RECV_IE_MASK); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, XEL_MDIOCTRL_MDIOEN_MASK); - if (in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET) & - XEL_MDIOCTRL_MDIOEN_MASK) + out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); + if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) if (!setup_phy(dev)) return -1; #endif @@ -536,7 +554,7 @@ static int emaclite_miiphy_read(const char *devname, uchar addr, u32 ret; struct eth_device *dev = eth_get_dev(); - ret = phyread(dev, addr, reg, val); + ret = phyread(dev->priv, addr, reg, val); debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); return ret; } @@ -547,7 +565,7 @@ static int emaclite_miiphy_write(const char *devname, uchar addr, struct eth_device *dev = eth_get_dev(); debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); - return phywrite(dev, addr, reg, val); + return phywrite(dev->priv, addr, reg, val); } #endif @@ -556,6 +574,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, { struct eth_device *dev; struct xemaclite *emaclite; + struct emaclite_regs *regs; dev = calloc(1, sizeof(*dev)); if (dev == NULL) @@ -574,6 +593,8 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, sprintf(dev->name, "Xelite.%lx", base_addr); + emaclite->regs = (struct emaclite_regs *)base_addr; + regs = emaclite->regs; dev->iobase = base_addr; dev->init = emaclite_init; dev->halt = emaclite_halt; @@ -592,8 +613,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write); emaclite->bus = miiphy_get_dev_by_name(dev->name); - out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, - XEL_MDIOCTRL_MDIOEN_MASK); + out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); #endif return 1; -- cgit v0.10.2 From a0b2bfb0bfb91c17038ce2555a0e1038802b997e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 15:22:21 +0100 Subject: net: emaclite: Use indirect register access for tx_ping/pong Do initialization via indirect register access. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 9d413a0..654ad58 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -335,28 +335,28 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) * TX - TX_PING & TX_PONG initialization */ /* Restart PING TX */ - out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); + out_be32(®s->tx_ping_tsr, 0); /* Copy MAC address */ - xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH); + xemaclite_alignedwrite(dev->enetaddr, (u32)®s->tx_ping, + ENET_ADDR_LENGTH); /* Set the length */ - out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH); /* Update the MAC address in the EMAC Lite */ - out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); + out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR); /* Wait for EMAC Lite to finish with the MAC address update */ - while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) & + while ((in_be32 (®s->tx_ping_tsr) & XEL_TSR_PROG_MAC_ADDR) != 0) ; if (emaclite->txpp) { /* The same operation with PONG TX */ - out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); - xemaclite_alignedwrite(dev->enetaddr, dev->iobase + - XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); - out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); - out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, - XEL_TSR_PROG_MAC_ADDR); - while ((in_be32 (dev->iobase + XEL_TSR_OFFSET + - XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) + out_be32(®s->tx_pong_tsr, 0); + xemaclite_alignedwrite(dev->enetaddr, (u32)®s->tx_pong, + ENET_ADDR_LENGTH); + out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH); + out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); + while ((in_be32(®s->tx_pong_tsr) & + XEL_TSR_PROG_MAC_ADDR) != 0) ; } -- cgit v0.10.2 From 3af709092c6d92cf7e4e19a45fbb96e2e4d1c8f5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 15:24:23 +0100 Subject: net: emaclite: Use indirect register access for rx_ping/pong Do initialization via indirect register access. Signed-off-by: Michal Simek diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 654ad58..724b61e 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -364,11 +364,10 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) * RX - RX_PING & RX_PONG initialization */ /* Write out the value to flush the RX buffer */ - out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); + out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK); if (emaclite->rxpp) - out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, - XEL_RSR_RECV_IE_MASK); + out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); -- cgit v0.10.2 From 5a4baa33e4d0beb9708719160bfc3f91a8f9f3bf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 15:32:11 +0100 Subject: net: emaclite: Use indirect register access for TX reset Move to use indirect register access when timeout expires for resetting TX buffers. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 724b61e..72b6e0a 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -408,6 +408,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) u32 reg; u32 baseaddress; struct xemaclite *emaclite = dev->priv; + struct emaclite_regs *regs = emaclite->regs; u32 maxtry = 1000; @@ -422,10 +423,9 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) if (!maxtry) { printf("Error: Timeout waiting for ethernet TX buffer\n"); /* Restart PING TX */ - out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); + out_be32(®s->tx_ping_tsr, 0); if (emaclite->txpp) { - out_be32 (dev->iobase + XEL_TSR_OFFSET + - XEL_BUFFER_OFFSET, 0); + out_be32(®s->tx_pong_tsr, 0); } return -1; } -- cgit v0.10.2 From 26c7945a24b8bd5565e9b1481dac10ff14eca177 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 15:42:01 +0100 Subject: net: emaclite: Fix logic around available TX buffers Simplify logic how to find out if there is free TX buffer. Both buffers are checked all the time that's why logic around order can be removed. Also add check when only one buffer is available. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 72b6e0a..b0c2635 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -379,28 +379,20 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) return 0; } -static int xemaclite_txbufferavailable(struct eth_device *dev) +static int xemaclite_txbufferavailable(struct xemaclite *emaclite) { - u32 reg; - u32 txpingbusy; - u32 txpongbusy; - struct xemaclite *emaclite = dev->priv; + u32 tmp; + struct emaclite_regs *regs = emaclite->regs; /* * Read the other buffer register * and determine if the other buffer is available */ - reg = in_be32 (dev->iobase + - emaclite->nexttxbuffertouse + 0); - txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == - XEL_TSR_XMIT_BUSY_MASK); - - reg = in_be32 (dev->iobase + - (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); - txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == - XEL_TSR_XMIT_BUSY_MASK); + tmp = ~in_be32(®s->tx_ping_tsr); + if (emaclite->txpp) + tmp |= ~in_be32(®s->tx_pong_tsr); - return !(txpingbusy && txpongbusy); + return !(tmp & XEL_TSR_XMIT_BUSY_MASK); } static int emaclite_send(struct eth_device *dev, void *ptr, int len) @@ -415,7 +407,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) if (len > PKTSIZE) len = PKTSIZE; - while (!xemaclite_txbufferavailable(dev) && maxtry) { + while (xemaclite_txbufferavailable(emaclite) && maxtry) { udelay(10); maxtry--; } -- cgit v0.10.2 From 15c239c8cea70c6c86498018c8008ba8fe9830df Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 16:06:07 +0100 Subject: net: emaclite: Remove XEL_TSR_XMIT_ACTIVE_MASK flag This flag is not documented anywhere in the latest documentation that's why this patch removes it. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index b0c2635..b6f3aca 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -33,8 +33,6 @@ #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL /* Xmit interrupt enable bit */ #define XEL_TSR_XMIT_IE_MASK 0x00000008UL -/* Buffer is active, SW bit only */ -#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL /* Program the MAC address */ #define XEL_TSR_PROGRAM_MASK 0x00000002UL /* define for programming the MAC address into the EMAC Lite */ @@ -427,10 +425,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) /* Determine if the expected buffer address is empty */ reg = in_be32 (baseaddress + XEL_TSR_OFFSET); - if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) - && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) - & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { - + if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { if (emaclite->txpp) emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET; @@ -441,8 +436,6 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); reg = in_be32 (baseaddress + XEL_TSR_OFFSET); reg |= XEL_TSR_XMIT_BUSY_MASK; - if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) - reg |= XEL_TSR_XMIT_ACTIVE_MASK; out_be32 (baseaddress + XEL_TSR_OFFSET, reg); return 0; } @@ -452,9 +445,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) baseaddress ^= XEL_BUFFER_OFFSET; /* Determine if the expected buffer address is empty */ reg = in_be32 (baseaddress + XEL_TSR_OFFSET); - if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) - && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) - & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { + if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { debug("Send packet from 0x%x\n", baseaddress); /* Write the frame to the buffer */ xemaclite_alignedwrite(ptr, baseaddress, len); @@ -463,8 +454,6 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) XEL_TPLR_LENGTH_MASK_LO))); reg = in_be32 (baseaddress + XEL_TSR_OFFSET); reg |= XEL_TSR_XMIT_BUSY_MASK; - if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) - reg |= XEL_TSR_XMIT_ACTIVE_MASK; out_be32 (baseaddress + XEL_TSR_OFFSET, reg); return 0; } -- cgit v0.10.2 From 007025183626f8ba492ba29bdb88159bb7a4d53f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 16:01:50 +0100 Subject: net: emaclite: Use indirect reg access in send The original logic in the driver was exchanging buffers which are used for sending packet and tx_ping and tx_pong buffers were exchanged all the time to ensure that IP has enough time to send the packet out. Based on this "feature" send function was using nextbuffertouse variable to save which buffer should be used. Before this algorithm was called driver checked that there is free buffer available. This checking remains in the driver but driver tries to use tx_ping first if available. If not, tx_pong buffer is used instead. To reach this code the original condition is met that at least one of the buffer should be available. Testing doesn't show any performance drop when this patch is applied. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index b6f3aca..e97ce2c 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -24,8 +24,6 @@ /* EmacLite constants */ #define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ -#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ -#define XEL_TSR_OFFSET 0x07FC /* Tx status */ #define XEL_RSR_OFFSET 0x17FC /* Rx status */ #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ @@ -88,7 +86,6 @@ struct emaclite_regs { }; struct xemaclite { - u32 nexttxbuffertouse; /* Next TX buffer to write to */ u32 nextrxbuffertouse; /* Next RX buffer to read from */ u32 txpp; /* TX ping pong buffer */ u32 rxpp; /* RX ping pong buffer */ @@ -126,7 +123,7 @@ static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) *to8ptr++ = *from8ptr++; } -static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount) +static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) { u32 i; u32 alignbuffer; @@ -335,7 +332,7 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) /* Restart PING TX */ out_be32(®s->tx_ping_tsr, 0); /* Copy MAC address */ - xemaclite_alignedwrite(dev->enetaddr, (u32)®s->tx_ping, + xemaclite_alignedwrite(dev->enetaddr, ®s->tx_ping, ENET_ADDR_LENGTH); /* Set the length */ out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH); @@ -349,7 +346,7 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) if (emaclite->txpp) { /* The same operation with PONG TX */ out_be32(®s->tx_pong_tsr, 0); - xemaclite_alignedwrite(dev->enetaddr, (u32)®s->tx_pong, + xemaclite_alignedwrite(dev->enetaddr, ®s->tx_pong, ENET_ADDR_LENGTH); out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH); out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); @@ -396,7 +393,6 @@ static int xemaclite_txbufferavailable(struct xemaclite *emaclite) static int emaclite_send(struct eth_device *dev, void *ptr, int len) { u32 reg; - u32 baseaddress; struct xemaclite *emaclite = dev->priv; struct emaclite_regs *regs = emaclite->regs; @@ -420,41 +416,33 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) return -1; } - /* Determine the expected TX buffer address */ - baseaddress = (dev->iobase + emaclite->nexttxbuffertouse); - /* Determine if the expected buffer address is empty */ - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + reg = in_be32(®s->tx_ping_tsr); if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { - if (emaclite->txpp) - emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET; - - debug("Send packet from 0x%x\n", baseaddress); + debug("Send packet from tx_ping buffer\n"); /* Write the frame to the buffer */ - xemaclite_alignedwrite(ptr, baseaddress, len); - out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & - (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + xemaclite_alignedwrite(ptr, ®s->tx_ping, len); + out_be32(®s->tx_ping_tplr, len & + (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)); + reg = in_be32(®s->tx_ping_tsr); reg |= XEL_TSR_XMIT_BUSY_MASK; - out_be32 (baseaddress + XEL_TSR_OFFSET, reg); + out_be32(®s->tx_ping_tsr, reg); return 0; } if (emaclite->txpp) { - /* Switch to second buffer */ - baseaddress ^= XEL_BUFFER_OFFSET; /* Determine if the expected buffer address is empty */ - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + reg = in_be32(®s->tx_pong_tsr); if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { - debug("Send packet from 0x%x\n", baseaddress); + debug("Send packet from tx_pong buffer\n"); /* Write the frame to the buffer */ - xemaclite_alignedwrite(ptr, baseaddress, len); - out_be32 (baseaddress + XEL_TPLR_OFFSET, (len & - (XEL_TPLR_LENGTH_MASK_HI | - XEL_TPLR_LENGTH_MASK_LO))); - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + xemaclite_alignedwrite(ptr, ®s->tx_pong, len); + out_be32(®s->tx_pong_tplr, len & + (XEL_TPLR_LENGTH_MASK_HI | + XEL_TPLR_LENGTH_MASK_LO)); + reg = in_be32(®s->tx_pong_tsr); reg |= XEL_TSR_XMIT_BUSY_MASK; - out_be32 (baseaddress + XEL_TSR_OFFSET, reg); + out_be32(®s->tx_pong_tsr, reg); return 0; } } -- cgit v0.10.2 From 4d2749be62b4bf749766a030c74688031edcfbad Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 16:31:38 +0100 Subject: net: emaclite: Use indirect access in emaclite_recv When IP is configured with pong buffers, IP is receiving packets to ping and then to pong buffer and than ping again. The original logic in the driver remains there that when ping buffer is free, pong buffer is checked too and return if both are free. Signed-off-by: Michal Simek diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index e97ce2c..800345b 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -17,15 +17,12 @@ #include #include #include +#include #undef DEBUG #define ENET_ADDR_LENGTH 6 - -/* EmacLite constants */ -#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ -#define XEL_RSR_OFFSET 0x17FC /* Rx status */ -#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ +#define ETH_FCS_LEN 4 /* Octets in the FCS */ /* Xmit complete */ #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL @@ -86,7 +83,7 @@ struct emaclite_regs { }; struct xemaclite { - u32 nextrxbuffertouse; /* Next RX buffer to read from */ + bool use_rx_pong_buffer_next; /* Next RX buffer to read from */ u32 txpp; /* TX ping pong buffer */ u32 rxpp; /* RX ping pong buffer */ int phyaddr; @@ -453,63 +450,87 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) static int emaclite_recv(struct eth_device *dev) { - u32 length; - u32 reg; - u32 baseaddress; + u32 length, first_read, reg, attempt = 0; + void *addr, *ack; struct xemaclite *emaclite = dev->priv; - - baseaddress = dev->iobase + emaclite->nextrxbuffertouse; - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); - debug("Testing data at address 0x%x\n", baseaddress); - if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { - if (emaclite->rxpp) - emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET; + struct emaclite_regs *regs = emaclite->regs; + struct ethernet_hdr *eth; + struct ip_udp_hdr *ip; + +try_again: + if (!emaclite->use_rx_pong_buffer_next) { + reg = in_be32(®s->rx_ping_rsr); + debug("Testing data at rx_ping\n"); + if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { + debug("Data found in rx_ping buffer\n"); + addr = ®s->rx_ping; + ack = ®s->rx_ping_rsr; + } else { + debug("Data not found in rx_ping buffer\n"); + /* Pong buffer is not available - return immediately */ + if (!emaclite->rxpp) + return -1; + + /* Try pong buffer if this is first attempt */ + if (attempt++) + return -1; + emaclite->use_rx_pong_buffer_next = + !emaclite->use_rx_pong_buffer_next; + goto try_again; + } } else { - - if (!emaclite->rxpp) { - debug("No data was available - address 0x%x\n", - baseaddress); - return 0; + reg = in_be32(®s->rx_pong_rsr); + debug("Testing data at rx_pong\n"); + if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { + debug("Data found in rx_pong buffer\n"); + addr = ®s->rx_pong; + ack = ®s->rx_pong_rsr; } else { - baseaddress ^= XEL_BUFFER_OFFSET; - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); - if ((reg & XEL_RSR_RECV_DONE_MASK) != - XEL_RSR_RECV_DONE_MASK) { - debug("No data was available - address 0x%x\n", - baseaddress); - return 0; - } + debug("Data not found in rx_pong buffer\n"); + /* Try ping buffer if this is first attempt */ + if (attempt++) + return -1; + emaclite->use_rx_pong_buffer_next = + !emaclite->use_rx_pong_buffer_next; + goto try_again; } } - /* Get the length of the frame that arrived */ - switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) & - 0xFFFF0000 ) >> 16) { - case 0x806: - length = 42 + 20; /* FIXME size of ARP */ - debug("ARP Packet\n"); - break; - case 0x800: - length = 14 + 14 + - (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + - 0x10))) & 0xFFFF0000) >> 16); - /* FIXME size of IP packet */ - debug ("IP Packet\n"); - break; - default: - debug("Other Packet\n"); - length = PKTSIZE; - break; + + /* Read all bytes for ARP packet with 32bit alignment - 48bytes */ + first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4); + xemaclite_alignedread(addr, etherrxbuff, first_read); + + /* Detect real packet size */ + eth = (struct ethernet_hdr *)etherrxbuff; + switch (ntohs(eth->et_protlen)) { + case PROT_ARP: + length = first_read; + debug("ARP Packet %x\n", length); + break; + case PROT_IP: + ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE); + length = ntohs(ip->ip_len); + length += ETHER_HDR_SIZE + ETH_FCS_LEN; + debug("IP Packet %x\n", length); + break; + default: + debug("Other Packet\n"); + length = PKTSIZE; + break; } - xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), - etherrxbuff, length); + /* Read the rest of the packet which is longer then first read */ + if (length != first_read) + xemaclite_alignedread(addr + first_read, + etherrxbuff + first_read, + length - first_read); /* Acknowledge the frame */ - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + reg = in_be32(ack); reg &= ~XEL_RSR_RECV_DONE_MASK; - out_be32 (baseaddress + XEL_RSR_OFFSET, reg); + out_be32(ack, reg); - debug("Packet receive from 0x%x, length %dB\n", baseaddress, length); + debug("Packet receive from 0x%p, length %dB\n", addr, length); net_process_received_packet((uchar *)etherrxbuff, length); return length; -- cgit v0.10.2 From d538ee1b54b78295dbc3bd0d8c5d5fafa5c9e343 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 10 Dec 2015 17:15:52 +0100 Subject: net: emaclite: Move driver to DM Move driver to DM. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index a3122da..0e7509d 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -100,23 +99,3 @@ void board_init(void) { gpio_init(); } - -int board_eth_init(bd_t *bis) -{ - int ret = 0; - -#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR) - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif - - return ret; -} diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 427e754..e89b05d 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -99,25 +98,6 @@ int checkboard(void) } #endif -int board_eth_init(bd_t *bis) -{ - u32 ret = 0; - -#ifdef CONFIG_XILINX_EMACLITE - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif - return ret; -} - int dram_init(void) { #if CONFIG_IS_ENABLED(OF_CONTROL) diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index fe731d0..12edab8 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -10,6 +10,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_DM_ETH=y CONFIG_PHYLIB=y CONFIG_SYS_NS16550=y CONFIG_XILINX_UARTLITE=y diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 800345b..903b3e8 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -19,7 +20,7 @@ #include #include -#undef DEBUG +DECLARE_GLOBAL_DATA_PTR; #define ENET_ADDR_LENGTH 6 #define ETH_FCS_LEN 4 /* Octets in the FCS */ @@ -146,7 +147,6 @@ static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) *to32ptr++ = alignbuffer; } -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) static int wait_for_bit(const char *func, u32 *reg, const u32 mask, bool set, unsigned int timeout) { @@ -231,9 +231,8 @@ static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, return 0; } -#endif -static void emaclite_halt(struct eth_device *dev) +static void emaclite_halt(struct udevice *dev) { debug("eth_halt\n"); } @@ -249,12 +248,11 @@ static void emaclite_halt(struct eth_device *dev) */ #define PHY_DETECT_MASK 0x1808 -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) -static int setup_phy(struct eth_device *dev) +static int setup_phy(struct udevice *dev) { int i; u16 phyreg; - struct xemaclite *emaclite = dev->priv; + struct xemaclite *emaclite = dev_get_priv(dev); struct phy_device *phydev; u32 supported = SUPPORTED_10baseT_Half | @@ -314,11 +312,11 @@ static int setup_phy(struct eth_device *dev) /* Do not setup anything */ return 1; } -#endif -static int emaclite_init(struct eth_device *dev, bd_t *bis) +static int emaclite_init(struct udevice *dev) { - struct xemaclite *emaclite = dev->priv; + struct xemaclite *emaclite = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); struct emaclite_regs *regs = emaclite->regs; debug("EmacLite Initialization Started\n"); @@ -329,7 +327,7 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) /* Restart PING TX */ out_be32(®s->tx_ping_tsr, 0); /* Copy MAC address */ - xemaclite_alignedwrite(dev->enetaddr, ®s->tx_ping, + xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping, ENET_ADDR_LENGTH); /* Set the length */ out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH); @@ -343,7 +341,7 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) if (emaclite->txpp) { /* The same operation with PONG TX */ out_be32(®s->tx_pong_tsr, 0); - xemaclite_alignedwrite(dev->enetaddr, ®s->tx_pong, + xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong, ENET_ADDR_LENGTH); out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH); out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); @@ -361,12 +359,11 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) if (emaclite->rxpp) out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) if (!setup_phy(dev)) return -1; -#endif + debug("EmacLite Initialization complete\n"); return 0; } @@ -387,10 +384,10 @@ static int xemaclite_txbufferavailable(struct xemaclite *emaclite) return !(tmp & XEL_TSR_XMIT_BUSY_MASK); } -static int emaclite_send(struct eth_device *dev, void *ptr, int len) +static int emaclite_send(struct udevice *dev, void *ptr, int len) { u32 reg; - struct xemaclite *emaclite = dev->priv; + struct xemaclite *emaclite = dev_get_priv(dev); struct emaclite_regs *regs = emaclite->regs; u32 maxtry = 1000; @@ -448,7 +445,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) return -1; } -static int emaclite_recv(struct eth_device *dev) +static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp) { u32 length, first_read, reg, attempt = 0; void *addr, *ack; @@ -532,78 +529,104 @@ try_again: debug("Packet receive from 0x%p, length %dB\n", addr, length); net_process_received_packet((uchar *)etherrxbuff, length); - return length; - + return 0; } -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) -static int emaclite_miiphy_read(const char *devname, uchar addr, - uchar reg, ushort *val) +static int emaclite_miiphy_read(struct mii_dev *bus, int addr, + int devad, int reg) { u32 ret; - struct eth_device *dev = eth_get_dev(); + u16 val = 0; - ret = phyread(dev->priv, addr, reg, val); - debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); - return ret; + ret = phyread(bus->priv, addr, reg, &val); + debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret); + return val; } -static int emaclite_miiphy_write(const char *devname, uchar addr, - uchar reg, ushort val) +static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) { - struct eth_device *dev = eth_get_dev(); - - debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); - return phywrite(dev->priv, addr, reg, val); + debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); + return phywrite(bus->priv, addr, reg, value); } -#endif -int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, - int txpp, int rxpp) +static int emaclite_probe(struct udevice *dev) { - struct eth_device *dev; - struct xemaclite *emaclite; - struct emaclite_regs *regs; + struct xemaclite *emaclite = dev_get_priv(dev); + int ret; - dev = calloc(1, sizeof(*dev)); - if (dev == NULL) - return -1; + emaclite->bus = mdio_alloc(); + emaclite->bus->read = emaclite_miiphy_read; + emaclite->bus->write = emaclite_miiphy_write; + emaclite->bus->priv = emaclite; + strcpy(emaclite->bus->name, "emaclite"); - emaclite = calloc(1, sizeof(struct xemaclite)); - if (emaclite == NULL) { - free(dev); - return -1; - } + ret = mdio_register(emaclite->bus); + if (ret) + return ret; + + return 0; +} - dev->priv = emaclite; +static int emaclite_remove(struct udevice *dev) +{ + struct xemaclite *emaclite = dev_get_priv(dev); + + free(emaclite->phydev); + mdio_unregister(emaclite->bus); + mdio_free(emaclite->bus); - emaclite->txpp = txpp; - emaclite->rxpp = rxpp; + return 0; +} - sprintf(dev->name, "Xelite.%lx", base_addr); +static const struct eth_ops emaclite_ops = { + .start = emaclite_init, + .send = emaclite_send, + .recv = emaclite_recv, + .stop = emaclite_halt, +}; + +static int emaclite_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct xemaclite *emaclite = dev_get_priv(dev); + int offset = 0; - emaclite->regs = (struct emaclite_regs *)base_addr; - regs = emaclite->regs; - dev->iobase = base_addr; - dev->init = emaclite_init; - dev->halt = emaclite_halt; - dev->send = emaclite_send; - dev->recv = emaclite_recv; + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + emaclite->regs = (struct emaclite_regs *)pdata->iobase; -#ifdef CONFIG_PHY_ADDR - emaclite->phyaddr = CONFIG_PHY_ADDR; -#else emaclite->phyaddr = -1; -#endif - eth_register(dev); + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy-handle"); + if (offset > 0) + emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, + "reg", -1); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write); - emaclite->bus = miiphy_get_dev_by_name(dev->name); + emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "xlnx,tx-ping-pong", 0); + emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "xlnx,rx-ping-pong", 0); - out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); -#endif + printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs, + emaclite->phyaddr, emaclite->txpp, emaclite->rxpp); - return 1; + return 0; } + +static const struct udevice_id emaclite_ids[] = { + { .compatible = "xlnx,xps-ethernetlite-1.00.a" }, + { } +}; + +U_BOOT_DRIVER(emaclite) = { + .name = "emaclite", + .id = UCLASS_ETH, + .of_match = emaclite_ids, + .ofdata_to_platdata = emaclite_ofdata_to_platdata, + .probe = emaclite_probe, + .remove = emaclite_remove, + .ops = &emaclite_ops, + .priv_auto_alloc_size = sizeof(struct xemaclite), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/include/netdev.h b/include/netdev.h index 9fc41ab..244f23f 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -80,8 +80,6 @@ int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); int armada100_fec_register(unsigned long base_addr); -int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, - int txpp, int rxpp); int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, unsigned long ctrl_addr); /* -- cgit v0.10.2 From f03ec010158375c404f5b0ebedba7c71c1689d2f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Dec 2015 10:40:05 +0100 Subject: net: emaclite: Rename start and stop functions Rename start and stop functions to align with DM functions names. Signed-off-by: Michal Simek diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 903b3e8..7e9a31e 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -232,9 +232,9 @@ static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, return 0; } -static void emaclite_halt(struct udevice *dev) +static void emaclite_stop(struct udevice *dev) { - debug("eth_halt\n"); + debug("eth_stop\n"); } /* Use MII register 1 (MII status register) to detect PHY */ @@ -313,7 +313,7 @@ static int setup_phy(struct udevice *dev) return 1; } -static int emaclite_init(struct udevice *dev) +static int emaclite_start(struct udevice *dev) { struct xemaclite *emaclite = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_platdata(dev); @@ -580,10 +580,10 @@ static int emaclite_remove(struct udevice *dev) } static const struct eth_ops emaclite_ops = { - .start = emaclite_init, + .start = emaclite_start, .send = emaclite_send, .recv = emaclite_recv, - .stop = emaclite_halt, + .stop = emaclite_stop, }; static int emaclite_ofdata_to_platdata(struct udevice *dev) -- cgit v0.10.2 From f412b6ab5b5d0960d29c82151e8ccd40390bc786 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Dec 2015 10:52:39 +0100 Subject: net: emaclite: Let core to handle received packet Pass pointer to core to handle packet. Signed-off-by: Michal Simek diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 7e9a31e..5862bf0 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -93,7 +93,7 @@ struct xemaclite { struct mii_dev *bus; }; -static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ +static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) { @@ -528,8 +528,8 @@ try_again: out_be32(ack, reg); debug("Packet receive from 0x%p, length %dB\n", addr, length); - net_process_received_packet((uchar *)etherrxbuff, length); - return 0; + *packetp = etherrxbuff; + return length; } static int emaclite_miiphy_read(struct mii_dev *bus, int addr, -- cgit v0.10.2 From 3229c869aa663c99591e124f037c67922222e8e4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Dec 2015 09:41:49 +0100 Subject: net: emaclite: Move emaclite to Kconfig Add PHYLIB and MII dependencies and enable it by default for Microblaze. Signed-off-by: Michal Simek Acked-by: Joe Hershberger diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 79c87fb..4f44427 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -44,9 +44,6 @@ #define XILINX_SYSACE_HIGHADDR 0x4180ffff #define XILINX_SYSACE_MEM_WIDTH 16 -/* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMACLITE_BASEADDR 0x40C00000 - /* Watchdog IP is wxi_timebase_wdt_0 */ #define XILINX_WATCHDOG_BASEADDR 0x50000000 #define XILINX_WATCHDOG_IRQ 1 diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 12edab8..325c1bb 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -11,6 +11,6 @@ CONFIG_CMD_GPIO=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DM_ETH=y -CONFIG_PHYLIB=y +CONFIG_XILINX_EMACLITE=y CONFIG_SYS_NS16550=y CONFIG_XILINX_UARTLITE=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index ee15359..218e1fe 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -110,6 +110,14 @@ config XILINX_AXIEMAC help This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. +config XILINX_EMACLITE + depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) + select PHYLIB + select MII + bool "Xilinx Ethernetlite" + help + This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. + config ZYNQ_GEM depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP) select PHYLIB diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 30ebff3..004826e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -42,8 +42,7 @@ /* ethernet */ #undef CONFIG_SYS_ENET -#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL) -# define CONFIG_XILINX_EMACLITE 1 +#if defined(CONFIG_XILINX_EMACLITE) # define CONFIG_SYS_ENET #endif #if defined(XILINX_AXIEMAC_BASEADDR) -- cgit v0.10.2 From 83b76d9ef718a31f6bff31d4abbcf886d80a45ce Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Dec 2015 16:54:42 +0100 Subject: microblaze: Enable axi emac via Kconfig Enable driver by default for all platforms. Signed-off-by: Michal Simek diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 325c1bb..047ed17 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -11,6 +11,7 @@ CONFIG_CMD_GPIO=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DM_ETH=y +CONFIG_XILINX_AXIEMAC=y CONFIG_XILINX_EMACLITE=y CONFIG_SYS_NS16550=y CONFIG_XILINX_UARTLITE=y diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 004826e..45a981b 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -42,11 +42,7 @@ /* ethernet */ #undef CONFIG_SYS_ENET -#if defined(CONFIG_XILINX_EMACLITE) -# define CONFIG_SYS_ENET -#endif -#if defined(XILINX_AXIEMAC_BASEADDR) -# define CONFIG_XILINX_AXIEMAC 1 +#if defined(CONFIG_XILINX_EMACLITE) || defined(CONFIG_XILINX_AXIEMAC) # define CONFIG_SYS_ENET #endif -- cgit v0.10.2 From 502547e8ba053e3ac1b21ea9cb7d9c429d5eb86c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Dec 2015 10:27:57 +0100 Subject: microblaze: Move eth configuration to Kconfig Cleanup board specific file. Signed-off-by: Michal Simek diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 047ed17..ebd88ab 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -8,6 +8,9 @@ CONFIG_SPL=y CONFIG_SYS_PROMPT="U-Boot-mONStR> " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DM_ETH=y diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 45a981b..327f95b 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -40,14 +40,6 @@ /* setting reset address */ /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ -/* ethernet */ -#undef CONFIG_SYS_ENET -#if defined(CONFIG_XILINX_EMACLITE) || defined(CONFIG_XILINX_AXIEMAC) -# define CONFIG_SYS_ENET -#endif - -#undef ET_DEBUG - /* gpio */ #ifdef XILINX_GPIO_BASEADDR # define CONFIG_XILINX_GPIO @@ -218,12 +210,6 @@ # undef CONFIG_CMD_CACHE #endif -#ifdef CONFIG_SYS_ENET -# define CONFIG_CMD_PING -# define CONFIG_CMD_DHCP -# define CONFIG_CMD_TFTPPUT -#endif - #if defined(CONFIG_SYSTEMACE) # define CONFIG_CMD_EXT2 # define CONFIG_CMD_FAT -- cgit v0.10.2 From ed982b4d41dcab072b5e5f4014a425068f8aafe0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Dec 2015 13:06:55 +0100 Subject: microblaze: Remove systemace from board file Systemace is ancient IP which is not tested. Remove it from default configuration. Signed-off-by: Michal Simek diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 4f44427..552aaf4 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -39,11 +39,6 @@ #define XILINX_RAM_START 0x28000000 #define XILINX_RAM_SIZE 0x04000000 -/* Sysace Controller is SysACE_CompactFlash */ -#define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180ffff -#define XILINX_SYSACE_MEM_WIDTH 16 - /* Watchdog IP is wxi_timebase_wdt_0 */ #define XILINX_WATCHDOG_BASEADDR 0x50000000 #define XILINX_WATCHDOG_IRQ 1 diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 327f95b..b28fc7e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -163,16 +163,6 @@ #endif /* !SPIFLASH */ #endif /* !FLASH */ -/* system ace */ -#ifdef XILINX_SYSACE_BASEADDR -# define CONFIG_SYSTEMACE -/* #define DEBUG_SYSTEMACE */ -# define SYSTEMACE_CONFIG_FPGA -# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR -# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH -# define CONFIG_DOS_PARTITION -#endif - #if defined(XILINX_USE_ICACHE) # define CONFIG_ICACHE #else @@ -210,11 +200,6 @@ # undef CONFIG_CMD_CACHE #endif -#if defined(CONFIG_SYSTEMACE) -# define CONFIG_CMD_EXT2 -# define CONFIG_CMD_FAT -#endif - #if defined(FLASH) # define CONFIG_CMD_JFFS2 # define CONFIG_CMD_UBI -- cgit v0.10.2 From 27f24a3d62605ce247b2875f26d0ec4c433ad3e9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Dec 2015 13:12:42 +0100 Subject: microblaze: Remove CONFIG_FIT from board file And enable it via defconfig by default. Signed-off-by: Michal Simek diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index ebd88ab..e8146ee 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -5,6 +5,8 @@ CONFIG_TARGET_MICROBLAZE_GENERIC=y CONFIG_SYS_TEXT_BASE=0x29000000 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_SYS_PROMPT="U-Boot-mONStR> " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index b28fc7e..a4db3d8 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -294,7 +294,6 @@ /* Enable flat device tree support */ #define CONFIG_LMB 1 -#define CONFIG_FIT 1 #define CONFIG_OF_LIBFDT 1 #if defined(CONFIG_XILINX_AXIEMAC) -- cgit v0.10.2 From b11ec1ab9a25dbb164a1bb5c7f592c5006a767e0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Dec 2015 13:16:16 +0100 Subject: microblaze: Move CONFIG_NETCONSOLE to Kconfig Cleanup board file. Signed-off-by: Michal Simek diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index e8146ee..f30e9c1 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_NETCONSOLE=y CONFIG_DM_ETH=y CONFIG_XILINX_AXIEMAC=y CONFIG_XILINX_EMACLITE=y diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index a4db3d8..cf7deea 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -286,7 +286,6 @@ #define CONFIG_CMDLINE_EDITING -#define CONFIG_NETCONSOLE #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Use the HUSH parser */ -- cgit v0.10.2 From 85916e29df41d16cf89e48113acafe9a670770c9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Dec 2015 13:17:35 +0100 Subject: microblaze: Remove empty file - cpu.c No need to have empty unused file in architecture code. Signed-off-by: Michal Simek diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index 4955e81..0697210 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -7,5 +7,5 @@ extra-y = start.o obj-y = irq.o -obj-y += cpu.o interrupts.o cache.o exception.o timer.o +obj-y += interrupts.o cache.o exception.o timer.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/cpu.c b/arch/microblaze/cpu/cpu.c deleted file mode 100644 index 8e459d8..0000000 --- a/arch/microblaze/cpu/cpu.c +++ /dev/null @@ -1,9 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* EMPTY FILE */ -- cgit v0.10.2 From 44a3a91cb0424e887105c2bfc670b863e8f2ee71 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Dec 2015 14:45:29 +0100 Subject: microblaze: Read information about RAM from DT Do not setup ram start/size in board file. Read it from DT instead. Signed-off-by: Michal Simek diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 0e7509d..0d7bed5 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -23,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; static int reset_pin = -1; #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) ulong ram_base; void dram_init_banksize(void) @@ -57,14 +56,6 @@ int dram_init(void) return 0; }; -#else -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} -#endif int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 552aaf4..ccb528e 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -35,10 +35,6 @@ #define XILINX_FLASH_START 0x2c000000 #define XILINX_FLASH_SIZE 0x00800000 -/* Main Memory is DDR_SDRAM_64Mx32 */ -#define XILINX_RAM_START 0x28000000 -#define XILINX_RAM_SIZE 0x04000000 - /* Watchdog IP is wxi_timebase_wdt_0 */ #define XILINX_WATCHDOG_BASEADDR 0x50000000 #define XILINX_WATCHDOG_IRQ 1 diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index cf7deea..9d14192 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -68,13 +68,6 @@ # endif #endif -#if !defined(CONFIG_OF_CONTROL) || \ - (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL)) -/* ddr sdram - main memory */ -# define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START -# define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE -#endif - #define CONFIG_SYS_MALLOC_LEN 0xC0000 /* Stack location before relocation */ @@ -259,7 +252,7 @@ #define CONFIG_SYS_MAXARGS 15 #define CONFIG_SYS_LONGHELP /* default load address */ -#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START +#define CONFIG_SYS_LOAD_ADDR 0 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #define CONFIG_BOOTARGS "root=romfs" -- cgit v0.10.2 From 077fe0f5e758a9810b320a2437d52b965a63c3b7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Dec 2015 14:59:03 +0100 Subject: microblaze: Enable HUSH via Kconfig Cleanup board file. Signed-off-by: Michal Simek diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index f30e9c1..39c2ad2 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot-mONStR> " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 9d14192..3cbec65 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -281,9 +281,6 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - /* Enable flat device tree support */ #define CONFIG_LMB 1 #define CONFIG_OF_LIBFDT 1 -- cgit v0.10.2 From 38c4761c236e0d8efd6b552d6b036015097c7bd9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 11 Dec 2015 15:01:28 +0100 Subject: microblaze: Fix board_init calling sequence board_init() is in final elf file but it is not called at all. Use board_init_late() instead and call gpio_init() from it. Signed-off-by: Michal Simek diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 0d7bed5..ccd4ec9 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -76,7 +76,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -int gpio_init (void) +static int gpio_init(void) { #ifdef CONFIG_XILINX_GPIO reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); @@ -86,7 +86,9 @@ int gpio_init (void) return 0; } -void board_init(void) +int board_late_init(void) { gpio_init(); + + return 0; } diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 3cbec65..97a0d86 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -45,6 +45,7 @@ # define CONFIG_XILINX_GPIO # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR #endif +#define CONFIG_BOARD_LATE_INIT /* interrupt controller */ #ifdef XILINX_INTC_BASEADDR -- cgit v0.10.2 From f72132673a01216e760864e442f168977cce2bd2 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 11 Jan 2016 12:30:41 +0530 Subject: fpga: xilinx: Check for substring in device ID validation Check for substrings in deviceID validation check so that it can support xa bitstreams also. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index c765a74..d459a2f 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -75,8 +75,8 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, buffer[i] = *dataptr++; if (xdesc->name) { - i = strncmp(buffer, xdesc->name, strlen(xdesc->name)); - if (i) { + i = (ulong)strstr(buffer, xdesc->name); + if (!i) { printf("%s: Wrong bitstream ID for this device\n", __func__); printf("%s: Bitstream ID %s, current device ID %d/%s\n", -- cgit v0.10.2 From ddbcf8f2c2d1be734c91948a0c1b676a5eb5087f Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 9 Dec 2015 18:46:42 +0530 Subject: fpga: Add bitstream type BIT_NONE Add bitstream type BIT_NONE to the bitstream type enum. This might be useful while loading bitstreams in respective drivers. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/fpga.h b/include/fpga.h index e0d1298..d768fb1 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -46,6 +46,7 @@ typedef struct { /* typedef fpga_desc */ typedef enum { BIT_FULL = 0, BIT_PARTIAL, + BIT_NONE = 0xFF, } bitstream_type; /* root function definitions */ -- cgit v0.10.2 From 455ad585eeac5e93fcca77e22afc9bbd2f4ccc3e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 5 Jan 2016 13:51:48 +0100 Subject: fpga: Fix compilation warnings Signed-off-by: Michal Simek diff --git a/cmd/fpga.c b/cmd/fpga.c index 7f99aab..8956eb1 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -86,7 +86,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) debug("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data); } - debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data); + debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data); case 3: /* fpga */ dev = (int)simple_strtoul(argv[2], NULL, 16); @@ -107,13 +107,13 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } else #endif { - fpga_data = (void *)dev; + fpga_data = (void *)(uintptr_t)dev; debug("* fpga: cmdline image addr = 0x%08lx\n", (ulong)fpga_data); } - debug("%s: fpga_data = 0x%x\n", - __func__, (uint)fpga_data); + debug("%s: fpga_data = 0x%lx\n", + __func__, (ulong)fpga_data); dev = FPGA_INVALID_DEVICE; /* reset device num */ } -- cgit v0.10.2 From a2533183c0fb41c10682a8d516a7434ebc4b9f39 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 14 Jan 2016 11:45:52 +0100 Subject: serial: zynq: Extend compatible string list ZynqMP is using updated core with cdns,uart-r1p12 compatible string. Signed-off-by: Michal Simek Signed-off-by: Michal Simek diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 3430482..112a7a2 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -177,6 +177,7 @@ static const struct dm_serial_ops zynq_serial_ops = { static const struct udevice_id zynq_serial_ids[] = { { .compatible = "xlnx,xuartps" }, { .compatible = "cdns,uart-r1p8" }, + { .compatible = "cdns,uart-r1p12" }, { } }; -- cgit v0.10.2 From 842efb3a930aac48b471573dfe380d7bffbbc3f0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 12 Jan 2016 14:45:49 +0100 Subject: serial: zynq: Fix address reading from DM Use dev_get_addr() instead of reading reg base directly in the driver. Core function is also more robust. Signed-off-by: Michal Simek diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 112a7a2..e79d997 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -156,13 +156,8 @@ static int zynq_serial_pending(struct udevice *dev, bool input) static int zynq_serial_ofdata_to_platdata(struct udevice *dev) { struct zynq_uart_priv *priv = dev_get_priv(dev); - fdt_addr_t addr; - addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - - priv->regs = (struct uart_zynq *)addr; + priv->regs = (struct uart_zynq *)dev_get_addr(dev); return 0; } -- cgit v0.10.2 From 0179063273484ba2a869e30d36383044dfcf4087 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 19 Oct 2015 10:43:30 +0200 Subject: net: phy: ti: Enable automatic crossover mode Enable automatic crossover cable detection. Signed-off-by: Michal Simek Reviewed-by: Edgar E. Iglesias Acked-by: Joe Hershberger diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index 541a57f..c3912d5 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -41,6 +41,8 @@ /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 +#define DP83867_MDI_CROSSOVER 5 +#define DP83867_MDI_CROSSOVER_AUTO 2 /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 @@ -149,6 +151,7 @@ static int dp83867_config(struct phy_device *phydev) if (phy_interface_is_rgmii(phydev)) { ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, + (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) | (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); if (ret) return ret; -- cgit v0.10.2 From f17ea71d3a8c44c9a74ab1df1eca43b9755cb225 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 Sep 2015 17:20:01 +0200 Subject: net: zynq: Change MDC setup for arm64 MDC setting depends on pclk input clocks which varies across SoC. This driver is used by xilinx zynq and zynqmp SOC. Input clock frequence on silicon is 125MHz where divider 64 put frequency below 2.5MHz requires by spec (125/64=1.95). Signed-off-by: Michal Simek diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 97e30f3..b3821c3 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -57,7 +57,11 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ +#ifdef CONFIG_ARM64 +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ +#else #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ +#endif #ifdef CONFIG_ARM64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ -- cgit v0.10.2 From a57a4a5d830cb81bf73f241532d7867606ed61fb Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 5 Jan 2016 12:21:04 +0530 Subject: sdhci: zynq: Remove hardcoded value zero as min frequency Remove hardcoded value zero as min frequency and use config option CONFIG_ZYNQ_SDHCI_MIN_FREQ defined in board config Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 4fe3da9..f21ea52 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -13,6 +13,10 @@ #include #include +#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ +# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0 +#endif + static int arasan_sdhci_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); @@ -22,7 +26,8 @@ static int arasan_sdhci_probe(struct udevice *dev) SDHCI_QUIRK_BROKEN_R1B; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 0); + add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, + CONFIG_ZYNQ_SDHCI_MIN_FREQ); upriv->mmc = host->mmc; -- cgit v0.10.2 From 429790026021d522d51617217d4b86218cca5750 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 12 Jan 2016 15:12:15 +0530 Subject: mmc: sdhci: Clear high speed if not supported Clear high speed bit if it was not supported by the driver. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Emil Lenchak Signed-off-by: Michal Simek diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 02d71b9..ff770b1 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -530,6 +530,10 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) if (caps & SDHCI_CAN_DO_8BIT) host->cfg.host_caps |= MMC_MODE_8BIT; } + + if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) + host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); + if (host->host_caps) host->cfg.host_caps |= host->host_caps; -- cgit v0.10.2 From b21561463885d4c2f40a133dae1ff00ef3f0175f Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 12 Jan 2016 15:12:16 +0530 Subject: mmc: zynq_sdhci: Added qurik to disable high speed Add quirk to disable high speed incase the high speed was broken.This solves the issue where the the controller is used in High Speed Mode and the the hold time requirement for the JEDEC/MMC 4.41 specification is NOT met. This timing issue is not on all boards and hence provided config option to enable it when required. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Emil Lenchak Signed-off-by: Michal Simek diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index f21ea52..039ec16 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -24,6 +24,11 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; + +#ifdef CONFIG_ZYNQ_HISPD_BROKEN + host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; +#endif + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, -- cgit v0.10.2 From 67b2904819f55fd30aabc731ca7b67e480a51f85 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 5 Jan 2016 10:49:24 +0100 Subject: ARM: zynq: Remove memory division by 2 for ECC case For ECC case u-boot divided memory by 2 because one u-boot could be used for both cases when ECC is off or on. Remove this division and make sure that dts file contain the correct memory size when ECC is enabled. Signed-off-by: Michal Simek diff --git a/arch/arm/mach-zynq/ddrc.c b/arch/arm/mach-zynq/ddrc.c index 5b20acc..d74f8db 100644 --- a/arch/arm/mach-zynq/ddrc.c +++ b/arch/arm/mach-zynq/ddrc.c @@ -42,8 +42,6 @@ void zynq_ddrc_init(void) */ /* cppcheck-suppress nullPointer */ memset((void *)0, 0, 1 * 1024 * 1024); - - gd->ram_size /= 2; } else { puts("ECC disabled "); } -- cgit v0.10.2 From eb04ab3492297941b285ff552645cc1c0ed72edb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 13 Jan 2016 14:32:43 +0100 Subject: ARM: zynq: Do not select options if SPL is not enabled Zynq setups some default options for SPL but not all targets are enabling SPL. Signed-off-by: Michal Simek diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 876a620..d2dbb1a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -558,15 +558,15 @@ config ARCH_ZYNQ select CPU_V7 select SUPPORT_SPL select OF_CONTROL - select SPL_OF_CONTROL + select SPL_OF_CONTROL if SPL select DM select DM_ETH - select SPL_DM + select SPL_DM if SPL select DM_MMC select DM_SPI select DM_SERIAL select DM_SPI_FLASH - select SPL_SEPARATE_BSS + select SPL_SEPARATE_BSS if SPL config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" -- cgit v0.10.2 From c5ca2db63bddc62f7166795273dea7da3a15366b Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 11 Jan 2016 12:01:10 +0530 Subject: ARM: zynq: Define sys prompt for all Zynq boards Define CONFIG_SYS_PROMPT for all Zynq boards It was removed by: "kconfig: add config option for shell prompt" (sha1: 181bd9dc61d2da88b78f1c1138a685dae39354d6) Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 30995ba..a3a66ec 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 339e399..fbc603f 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_PICOZED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" CONFIG_SPL=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 065f855..2722ec4 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 1059689..2392243 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index a9dbda5..c99e6ec 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 6ff00c6..2bc88b8 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 75d6c55..b0fa661 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" +CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index dd65929..d913f31 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 73b17e2..6b7861a 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 577c5a9..f4e2059 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y -- cgit v0.10.2 From 448bce733c3d1a6c18502ba610bfb26da5c80f51 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 14 Jan 2016 13:01:44 +0100 Subject: ARM: zynq: Enable SPI_FLASH for zc770 xm013 platform Enable SPI flash. Signed-off-by: Michal Simek Signed-off-by: Michal Simek diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index d913f31..cfec336 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -14,4 +14,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPI_FLASH=y CONFIG_ZYNQ_GEM=y -- cgit v0.10.2 From dce7e11fe108f5ccf59562c93ae005e973760d54 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 12 Jan 2016 13:44:29 +0100 Subject: ARM: zynq: Move FLASH_BAR to Kconfig Clean up config and use Kconfig more. Signed-off-by: Michal Simek diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 2722ec4..3540653 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_GPIO=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 2392243..f333b7a 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_GPIO=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index c99e6ec..ebfdeb0 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_GPIO=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index cfec336..9672940 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -15,4 +15,5 @@ CONFIG_CMD_GPIO=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 6b7861a..5868012 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_GPIO=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 0ab6083..e8c3ef0 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -66,7 +66,6 @@ #ifdef CONFIG_ZYNQ_QSPI # define CONFIG_SF_DEFAULT_SPEED 30000000 # define CONFIG_SPI_FLASH_ISSI -# define CONFIG_SPI_FLASH_BAR # define CONFIG_CMD_SF #endif -- cgit v0.10.2 From e5c343dddcad85e8a432809fb704a6c30d538018 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 14 Jan 2016 13:06:28 +0100 Subject: ARM: zynq: Clean DTSI coding style Fix minor indentation problems. Signed-off-by: Michal Simek Reviewed-by: Soren Brinkmann Reviewed-by: Moritz Fischer Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 83be51a..2d786f0 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -234,7 +234,7 @@ interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; - } ; + }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; @@ -244,7 +244,7 @@ interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; - } ; + }; slcr: slcr@f8000000 { #address-cells = <1>; @@ -326,11 +326,11 @@ scutimer: timer@f8f00600 { interrupt-parent = <&intc>; - interrupts = < 1 13 0x301 >; + interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; - reg = < 0xf8f00600 0x20 >; + reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; - } ; + }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; -- cgit v0.10.2 From 4691941b45d168187e58ec547701b223ffeeb5b3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 12 Jan 2016 13:56:44 +0100 Subject: ARM: zynq: Fix all remaining zynq platform to use stdout-path Fix console setup for all remaining zynq boards. Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 07e2b7a..b6982c0 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -21,9 +21,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; - linux,stdout-path = &uart1; - stdout-path = &uart1; + bootargs = "root=/dev/ram rw earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 77e3bb0..ae54519 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -18,9 +18,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; - linux,stdout-path = &uart1; - stdout-path = &uart1; + bootargs = "root=/dev/ram rw earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 3e1769a..3c50b99 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -20,9 +20,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; - linux,stdout-path = &uart1; - stdout-path = &uart1; + bootargs = "root=/dev/ram rw earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 288e248..5077cdb 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -20,9 +20,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; - linux,stdout-path = &uart0; - stdout-path = &uart0; + bootargs = "root=/dev/ram rw earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { -- cgit v0.10.2 From 1c5e069b6feaef682af2f373aa1448502e54ba81 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 14 Jan 2016 14:42:28 +0100 Subject: ARM: zynq: Fix defconfig for zybo Change possition of SPI_FLASH to by align with savedefconfig. Signed-off-by: Michal Simek diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index f4e2059..ebaae49 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -13,11 +13,11 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_SPANSION=y CONFIG_ZYNQ_QSPI=y -- cgit v0.10.2 From 7ebf67a34cbde3c790503af8537868c6d1322c53 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 14 Jan 2016 13:09:16 +0100 Subject: ARM: zynq: Move spi node to aligned location Keep nodes aligned. Signed-off-by: Michal Simek Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index ae54519..4fed221 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -33,12 +33,6 @@ }; }; -&spi0 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; -}; - &can0 { status = "okay"; }; @@ -53,6 +47,12 @@ }; }; +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + &uart1 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 3c50b99..8d69f0e 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -30,12 +30,6 @@ }; }; -&spi1 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; -}; - &can1 { status = "okay"; }; @@ -60,6 +54,12 @@ }; }; +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + &uart1 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 5077cdb..77fdfcc 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -30,21 +30,6 @@ }; }; -&spi0 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; - eeprom: at25@0 { - at25,byte-len = <8192>; - at25,addr-mode = <2>; - at25,page-size = <32>; - - compatible = "atmel,at25"; - reg = <2>; - spi-max-frequency = <1000000>; - }; -}; - &can1 { status = "okay"; }; @@ -73,6 +58,21 @@ }; }; +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + eeprom: at25@0 { + at25,byte-len = <8192>; + at25,addr-mode = <2>; + at25,page-size = <32>; + + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <1000000>; + }; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; -- cgit v0.10.2 From c061d5b3dd026b4d85390c19db65604dc7451f97 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 5 Jan 2016 12:21:05 +0530 Subject: ARM64: zynqmp: ep: Define minimum sdhci frequency for ep Define minimum sdhci frequency for ep, as not defining it causes the divisor to be 2048 as per sd version but keeping clock very low on ep causes command failures. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index ec39211..ed7ae17 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -17,6 +17,7 @@ #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 +#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) #define CONFIG_ZYNQ_I2C0 #define CONFIG_SYS_I2C_ZYNQ #define CONFIG_ZYNQ_EEPROM -- cgit v0.10.2 From d041e3e15765c3e1977f125083bd7deebe83f40b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 20 Aug 2015 15:21:48 +0200 Subject: ARM64: zynqmp: Remove incorrect link to common config file Link to zynqmp common file is incorrect. Fix it by removing the whole link because it is visible from the file where to look at it. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index ed7ae17..23a69db 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -1,7 +1,5 @@ /* - * Configuration for Xilinx ZynqMP emulation - * platforms. See zynqmp-common.h for ZynqMP - * common configs + * Configuration for Xilinx ZynqMP emulation platforms * * (C) Copyright 2014 - 2015 Xilinx, Inc. * Michal Simek -- cgit v0.10.2 From 0785dfd8a7b14cb2c99fc1271c865eb2170c620b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 5 Nov 2015 08:34:35 +0100 Subject: ARM64: zynqmp: Use the same U-Boot version with/without ATF Remove SECURE_IOU option which is not needed. U-Boot itself can detect which EL level it is on and based on that use do platform setup. It also simplify usage because one Kconfig entry is gone. Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index e5a4fdd..9a19dfa 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -20,10 +20,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP -config SECURE_IOU - bool "Configure ZynqMP secure IOU" - default n - config ZYNQMP_USB bool "Configure ZynqMP USB" diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c index 9218586..40bd2ca 100644 --- a/arch/arm/cpu/armv8/zynqmp/clk.c +++ b/arch/arm/cpu/armv8/zynqmp/clk.c @@ -26,6 +26,22 @@ unsigned long get_uart_clk(int dev_id) return 133000000; } +unsigned long zynqmp_get_system_timer_freq(void) +{ + u32 ver = zynqmp_get_silicon_version(); + + switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: + return 10000; + case ZYNQMP_CSU_VERSION_EP108: + return 4000000; + case ZYNQMP_CSU_VERSION_QEMU: + return 50000000; + } + + return 100000000; +} + #ifdef CONFIG_CLOCKS /** * set_cpu_clk_info() - Initialize clock framework diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index f90cca3..45b49dc 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -15,8 +15,22 @@ DECLARE_GLOBAL_DATA_PTR; +static unsigned int zynqmp_get_silicon_version_secure(void) +{ + u32 ver; + + ver = readl(&csu_base->version); + ver &= ZYNQMP_SILICON_VER_MASK; + ver >>= ZYNQMP_SILICON_VER_SHIFT; + + return ver; +} + unsigned int zynqmp_get_silicon_version(void) { + if (current_el() == 3) + return zynqmp_get_silicon_version_secure(); + gd->cpu_clk = get_tbclk(); switch (gd->cpu_clk) { diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h index d55bc31..b18333d 100644 --- a/arch/arm/include/asm/arch-zynqmp/clk.h +++ b/arch/arm/include/asm/arch-zynqmp/clk.h @@ -9,5 +9,6 @@ #define _ASM_ARCH_CLK_H_ unsigned long get_uart_clk(int dev_id); +unsigned long zynqmp_get_system_timer_freq(void); #endif /* _ASM_ARCH_CLK_H_ */ diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index bbf89d9..5f4cfe3 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -41,11 +41,8 @@ struct crlapb_regs { #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) -#if defined(CONFIG_SECURE_IOU) -#define ZYNQMP_IOU_SCNTR 0xFF260000 -#else +#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 #define ZYNQMP_IOU_SCNTR 0xFF250000 -#endif #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 @@ -57,6 +54,14 @@ struct iou_scntr { #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) +struct iou_scntr_secure { + u32 counter_control_register; + u32 reserved0[7]; + u32 base_frequency_id_register; +}; + +#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) + /* Bootmode setting values */ #define BOOT_MODES_MASK 0x0000000F #define SD_MODE 0x00000003 @@ -106,9 +111,20 @@ struct apu_regs { #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) /* Board version value */ +#define ZYNQMP_CSU_BASEADDR 0xFFCA0000 #define ZYNQMP_CSU_VERSION_SILICON 0x0 #define ZYNQMP_CSU_VERSION_EP108 0x1 #define ZYNQMP_CSU_VERSION_VELOCE 0x2 #define ZYNQMP_CSU_VERSION_QEMU 0x3 +#define ZYNQMP_SILICON_VER_MASK 0xF000 +#define ZYNQMP_SILICON_VER_SHIFT 12 + +struct csu_regs { + u32 reserved0[17]; + u32 version; +}; + +#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 2cf4712..63c332f 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -28,10 +29,18 @@ int board_early_init_r(void) { u32 val; - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - + if (current_el() == 3) { + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + /* Program freq register in System counter */ + writel(zynqmp_get_system_timer_freq(), + &iou_scntr_secure->base_frequency_id_register); + /* And enable system counter */ + writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, + &iou_scntr_secure->counter_control_register); + } /* Program freq register in System counter and enable system counter */ writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | -- cgit v0.10.2 From be6f6af1d63d92d6c9496656d97c603b7ae17656 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 20 Aug 2015 14:01:39 +0200 Subject: ARM64: zynqmp: Add initial support for the first silicon Add basic configuration for the first silicon. Signed-off-by: Michal Simek diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c index 40bd2ca..690c72d 100644 --- a/arch/arm/cpu/armv8/zynqmp/clk.c +++ b/arch/arm/cpu/armv8/zynqmp/clk.c @@ -21,9 +21,11 @@ unsigned long get_uart_clk(int dev_id) return 48000; case ZYNQMP_CSU_VERSION_EP108: return 25000000; + case ZYNQMP_CSU_VERSION_QEMU: + return 133000000; } - return 133000000; + return 100000000; } unsigned long zynqmp_get_system_timer_freq(void) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 45b49dc..c71f291 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -38,9 +38,11 @@ unsigned int zynqmp_get_silicon_version(void) return ZYNQMP_CSU_VERSION_VELOCE; case 50000000: return ZYNQMP_CSU_VERSION_QEMU; + case 4000000: + return ZYNQMP_CSU_VERSION_EP108; } - return ZYNQMP_CSU_VERSION_EP108; + return ZYNQMP_CSU_VERSION_SILICON; } #ifndef CONFIG_SYS_DCACHE_OFF -- cgit v0.10.2 From cb9dcc6eaa1e7700d59ae8b84f5a2084b1853e1f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 14 Jan 2016 13:11:51 +0100 Subject: ARM64: zynqmp: Fix coding style in phy node Trivial fix. Signed-off-by: Michal Simek Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index 4481bd0..754604e 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -41,7 +41,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@0{ + phy0: phy@0 { reg = <0>; max-speed = <100>; }; -- cgit v0.10.2 From d3fd433f07d39481ebc942c2cf60f593a77aec5e Mon Sep 17 00:00:00 2001 From: Punnaiah Choudary Kalluri Date: Wed, 4 Nov 2015 12:34:17 +0530 Subject: ARM64: zynqmp: Correct the watchdog timer interrupt number Corrected the watchdog timer interrupt number. Origin value was for CSUPMU watchdog. Signed-off-by: Punnaiah Choudary Kalluri Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 24a34e6..f4b9401 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -559,7 +559,7 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 52 1>; + interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x1000>; timeout-sec = <10>; }; -- cgit v0.10.2 From 0d90e9d851c98200a4fc496a3ea1320a5ed2ded8 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Wed, 4 Nov 2015 11:18:09 -0800 Subject: ARM64: zynqmp: DT: Fix UART compatible string ZynqMP has r1p12 not r1p8. r1p12 contains break detection support. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index f4b9401..8733604 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -520,7 +520,7 @@ }; uart0: serial@ff000000 { - compatible = "cdns,uart-r1p8"; + compatible = "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; @@ -529,7 +529,7 @@ }; uart1: serial@ff010000 { - compatible = "cdns,uart-r1p8"; + compatible = "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; -- cgit v0.10.2 From 0a5bcc8c0d04d4dd277cfeb1edf1e7b298b0f484 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 13 Mar 2015 11:10:26 +0530 Subject: ARM64: zynqmp: Modify the SD and QSPI bootmode values Modify the SD bootmode value to 0x3 as per latest spec. Also add new boot mode QSPI 32 bit boot mode Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 5f4cfe3..5eec999 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -64,7 +64,10 @@ struct iou_scntr_secure { /* Bootmode setting values */ #define BOOT_MODES_MASK 0x0000000F +#define QSPI_MODE_24BIT 0x00000001 +#define QSPI_MODE_32BIT 0x00000002 #define SD_MODE 0x00000003 +#define NAND_MODE 0x00000004 #define EMMC_MODE 0x00000006 #define JTAG_MODE 0x00000000 diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 63c332f..cf8d6a4 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -83,6 +83,13 @@ int board_late_init(void) bootmode = reg & BOOT_MODES_MASK; switch (bootmode) { + case JTAG_MODE: + setenv("modeboot", "netboot"); + break; + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + setenv("modeboot", "qspiboot"); + break; case SD_MODE: case EMMC_MODE: setenv("modeboot", "sdboot"); -- cgit v0.10.2 From af813acd481bf3490a982e279567e49b59f28117 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 5 Oct 2015 10:51:12 +0200 Subject: ARM64: zynqmp: Add support for SD1 boot mode SD1 boot mode is using different bootmode values. Add support for this mode used on DC1. Signed-off-by: Michal Simek diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 5eec999..5879382 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -66,7 +66,8 @@ struct iou_scntr_secure { #define BOOT_MODES_MASK 0x0000000F #define QSPI_MODE_24BIT 0x00000001 #define QSPI_MODE_32BIT 0x00000002 -#define SD_MODE 0x00000003 +#define SD_MODE 0x00000003 /* sd 0 */ +#define SD_MODE1 0x00000005 /* sd 1 */ #define NAND_MODE 0x00000004 #define EMMC_MODE 0x00000006 #define JTAG_MODE 0x00000000 diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index cf8d6a4..6bdec20 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -94,6 +94,12 @@ int board_late_init(void) case EMMC_MODE: setenv("modeboot", "sdboot"); break; + case SD_MODE1: + setenv("modeboot", "sdboot1"); + break; + case NAND_MODE: + setenv("modeboot", "nandboot"); + break; default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; -- cgit v0.10.2 From fb90917c463ddbbc0538676a73d9ed305fa54322 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sun, 20 Sep 2015 17:20:42 +0200 Subject: ARM64: zynqmp: Show information about bootmode Showing information about bootmode is very useful to make sure that correct bootmode is selected. Signed-off-by: Michal Simek diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 6bdec20..9c176d0 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -82,22 +82,28 @@ int board_late_init(void) reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; + puts("Bootmode: "); switch (bootmode) { case JTAG_MODE: - setenv("modeboot", "netboot"); + puts("JTAG_MODE\n"); + setenv("modeboot", "jtagboot"); break; case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: setenv("modeboot", "qspiboot"); + puts("QSPI_MODE\n"); break; case SD_MODE: case EMMC_MODE: + puts("SD_MODE\n"); setenv("modeboot", "sdboot"); break; case SD_MODE1: + puts("SD_MODE1\n"); setenv("modeboot", "sdboot1"); break; case NAND_MODE: + puts("NAND_MODE\n"); setenv("modeboot", "nandboot"); break; default: -- cgit v0.10.2 From 78678feeacc32f4fca9cb9a4aa9168396d8101c6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 5 Oct 2015 15:59:38 +0200 Subject: ARM64: zynqmp: Differentiate EMMC boot mode Show also EMMC bootmode if selected. There is difference compare to SD bootmode. Use the same bootcommand till better boot command is created. Reported-by: Sai Pavan Boddu Signed-off-by: Michal Simek diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 9c176d0..a1d3fef 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -93,8 +93,11 @@ int board_late_init(void) setenv("modeboot", "qspiboot"); puts("QSPI_MODE\n"); break; - case SD_MODE: case EMMC_MODE: + puts("EMMC_MODE\n"); + setenv("modeboot", "sdboot"); + break; + case SD_MODE: puts("SD_MODE\n"); setenv("modeboot", "sdboot"); break; -- cgit v0.10.2 From 2d9925bce3060c91f2495e741a1220eb827338c0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 6 Nov 2015 10:22:37 +0100 Subject: ARM64: zynqmp: Fix bootmode SD_MODE1 When only sdhci1 IP is enabled and SD_MODE1 bootmode is selected U-Boot using sdboot1 variable which refers to mmc dev 1. But this device doesn't exist because only one controller is available. This patch fix logic around sdboot mode with using sdbootdev internal variable. Reported-by: Chris Kohn Acked-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index a1d3fef..ac23625 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -103,7 +103,10 @@ int board_late_init(void) break; case SD_MODE1: puts("SD_MODE1\n"); - setenv("modeboot", "sdboot1"); +#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) + setenv("sdbootdev", "1"); +#endif + setenv("modeboot", "sdboot"); break; case NAND_MODE: puts("NAND_MODE\n"); diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 03f7450..2d9f020 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -156,8 +156,10 @@ "kernel_addr=0x80000\0" \ "fdt_addr=0x7000000\0" \ "fdt_high=0x10000000\0" \ - "sdboot=mmcinfo && load mmc 0:0 $fdt_addr system.dtb && " \ - "load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" \ + "sdbootdev=0\0"\ + "sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \ + "load mmc $sdbootdev:$partid $kernel_addr Image && " \ + "booti $kernel_addr - $fdt_addr\0" \ DFU_ALT_INFO #define CONFIG_BOOTARGS "setenv bootargs console=ttyPS0,${baudrate} " \ -- cgit v0.10.2 From cce124b8b31a3c0bb07dbdd4dc62bb15dcad2377 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 13 Jan 2016 12:47:04 +0100 Subject: ARM64: zynqmp: Remove unneeded timer_init function Empty weak function is used instead. Signed-off-by: Michal Simek diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index ac23625..1a83789 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -57,11 +57,6 @@ int dram_init(void) return 0; } -int timer_init(void) -{ - return 0; -} - void reset_cpu(ulong addr) { } -- cgit v0.10.2 From d759512fc27f1c406ce5c7b166e6cf53384ee115 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 15 Oct 2015 14:34:28 +0200 Subject: ARM64: zynqmp: Enable advance memory test by default Temp space in at the beginning of OCM. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 2d9f020..f6a36a3 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -28,6 +28,9 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 + #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE -- cgit v0.10.2 From 99cb9ce029b58dd35d533371be0e333212b7798f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 5 Oct 2015 11:02:33 +0200 Subject: ARM64: zynqmp: Move memory setup to board file Setup memory size for ep108 in ep108 config file. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f6a36a3..ac68998 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -23,11 +23,6 @@ #define GICD_BASE 0xF9010000 #define GICC_BASE 0xF9020000 -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 - #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 23a69db..0204d2c 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -23,6 +23,11 @@ #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ ZYNQMP_USB1_XHCI_BASEADDR} +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + #include #endif /* __CONFIG_ZYNQMP_EP_H */ -- cgit v0.10.2 From 713b616459eb0d8a7805e31f4b8e9a6fe786b3aa Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 5 Nov 2015 08:32:14 +0100 Subject: ARM64: zynqmp: Setup correct COUNTER_FREQUENCY for silicon When U-Boot runs from EL3 system timer is setup based on this macro. Software default freq for silicon is 100MHz but enable opton to rewrite it. Emulation platform is using 4MHz. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index ac68998..dcd7552 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -43,7 +43,9 @@ #define CONFIG_OF_LIBFDT /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ -#define COUNTER_FREQUENCY 4000000 +#if !defined(COUNTER_FREQUENCY) +# define COUNTER_FREQUENCY 100000000 +#endif /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000) diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 0204d2c..9906c42 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define COUNTER_FREQUENCY 4000000 + #include #endif /* __CONFIG_ZYNQMP_EP_H */ -- cgit v0.10.2 From 15c3eb53a98f38b1261429166ac3162eadec8441 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 28 Aug 2015 13:34:37 +0200 Subject: ARM64: zynqmp: Allow overwrite identification string Keep default option there but allow overwrite it. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index dcd7552..5008722 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -35,7 +35,9 @@ /* Cache Definitions */ #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_IDENT_STRING " Xilinx ZynqMP" +#if !defined(CONFIG_IDENT_STRING) +# define CONFIG_IDENT_STRING " Xilinx ZynqMP" +#endif #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -- cgit v0.10.2 From f96fe2c0a8a72d675532d79df49cbfe3464154a5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Sep 2015 19:35:31 +0200 Subject: ARM64: zynqmp: Enable NATSEMI phys Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 5008722..eae1a49 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -193,6 +193,7 @@ # define CONFIG_MII # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHY_MARVELL +# define CONFIG_PHY_NATSEMI # define CONFIG_PHY_TI #endif -- cgit v0.10.2 From c4c96f2b3fa31a68dcb9e7a65282dbfa519aa7f9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 24 Sep 2015 20:12:29 +0200 Subject: ARM64: zynqmp: Include GbE speed/duplex detection Get right speed/duplex via mii info. Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index eae1a49..20bb359 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -195,6 +195,7 @@ # define CONFIG_PHY_MARVELL # define CONFIG_PHY_NATSEMI # define CONFIG_PHY_TI +# define CONFIG_PHY_GIGE #endif /* I2C */ -- cgit v0.10.2 From 1b19daf407869201e6515abbccac43daa5b55b84 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 7 Sep 2015 11:03:47 +0530 Subject: ARM64: zynqmp: Modify the autoboot commands Modify DFU commands to use latest kernel offsets and sizes as per modified partitions in the linux device tree. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 20bb359..0e5e28b 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -140,8 +140,8 @@ #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "set dfu_alt_info " \ - "Image ram 0x200000 0x1800000\\\\;" \ - "system.dtb ram 0x7000000 0x40000\0" \ + "Image ram $kernel_addr $kernel_size\\\\;" \ + "system.dtb ram $fdt_addr $fdt_size\0" \ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" @@ -158,6 +158,8 @@ "kernel_addr=0x80000\0" \ "fdt_addr=0x7000000\0" \ "fdt_high=0x10000000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ "sdbootdev=0\0"\ "sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \ "load mmc $sdbootdev:$partid $kernel_addr Image && " \ -- cgit v0.10.2 From 0e43140bb1118be28477d1fbe1651ca4ec6969ca Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 11 Sep 2015 11:57:25 +0530 Subject: ARM64: zynqmp: Dont use shortcut for setenv Dont use shortcut command for setenv as it wont work now due introduction of new command setexpr. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 0e5e28b..862f3e6 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -139,7 +139,7 @@ #define CONFIG_THOR_RESET_OFF #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ - "set dfu_alt_info " \ + "setenv dfu_alt_info " \ "Image ram $kernel_addr $kernel_size\\\\;" \ "system.dtb ram $fdt_addr $fdt_size\0" \ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ -- cgit v0.10.2 From 0cf0ef6af96eff3dbb4ca15b85807ed410f79eb0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 14 Jan 2016 13:44:29 +0100 Subject: ARM64: zynqmp: Do not setup bootargs Bootargs will be taken from DTS files. Signed-off-by: Michal Simek Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 862f3e6..899dd3a 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -166,8 +166,6 @@ "booti $kernel_addr - $fdt_addr\0" \ DFU_ALT_INFO -#define CONFIG_BOOTARGS "setenv bootargs console=ttyPS0,${baudrate} " \ - "earlycon=cdns,mmio,0xff000000,${baudrate}n8" #define CONFIG_PREBOOT "run bootargs" #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 5 -- cgit v0.10.2 From e2928f32e0d88c063067019a2cb8acbb6f07b221 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 5 Jan 2016 15:21:46 +0530 Subject: ARM64: zynqmp: Define auto negotiation timeout Define auto negotiation timeout as 20secs the default 4secs might not be sufficient always and hence defined for worst case. It is observed that autoneg takes moretime if connected to outside network and hence increase it to 20secs. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 899dd3a..27ef74d 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -196,6 +196,7 @@ # define CONFIG_PHY_NATSEMI # define CONFIG_PHY_TI # define CONFIG_PHY_GIGE +# define PHY_ANEG_TIMEOUT 20000 #endif /* I2C */ -- cgit v0.10.2 From 5af08556707f024edded56c3edae99430f3cfceb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 25 Jan 2016 11:04:21 +0100 Subject: ARM: zynq: zynqmp: Line up checkboard message Use space instead of tab in checkboard print to aligned it with others boards. Reported-by: David Glessner Signed-off-by: Michal Simek Reviewed-by: Moritz Fischer diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index e89b05d..01bae5d 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -93,7 +93,7 @@ int board_late_init(void) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { - puts("Board:\tXilinx Zynq\n"); + puts("Board: Xilinx Zynq\n"); return 0; } #endif diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 1a83789..44d347e 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -117,7 +117,7 @@ int board_late_init(void) int checkboard(void) { - puts("Board:\tXilinx ZynqMP\n"); + puts("Board: Xilinx ZynqMP\n"); return 0; } -- cgit v0.10.2 From 80cce2629bf5c49e44900d7e4396233b2d012921 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:19 +0100 Subject: ppc: xilinx-ppc4xx: Port to DM serial xilinx_uartlite has been ported to DM, this patch makes the xilinx-ppc405-generic and the xilinx-ppc440-generic boards use the new DM driver. Signed-off-by: Ricardo Ribalda Delgado Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 3959585..36af1b9 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -111,9 +111,17 @@ config TARGET_XPEDITE1000 config TARGET_XILINX_PPC405_GENERIC bool "Support xilinx-ppc405-generic" + select SUPPORT_SPL + select OF_CONTROL + select DM + select DM_SERIAL config TARGET_XILINX_PPC440_GENERIC bool "Support xilinx-ppc440-generic" + select SUPPORT_SPL + select OF_CONTROL + select DM + select DM_SERIAL endchoice diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c index 8b10dba..32105a8 100644 --- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -46,3 +46,7 @@ void __get_sys_info(sys_info_t *sysInfo) return; } void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); + +int get_serial_clock(void){ + return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; +} diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h index 90fe969..c3df9e5 100644 --- a/board/xilinx/ppc405-generic/xparameters.h +++ b/board/xilinx/ppc405-generic/xparameters.h @@ -19,7 +19,6 @@ #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 #define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 #define XPAR_SPI_0_NUM_TRANSFER_BITS 8 -#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef #define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 #endif diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c index 3718a76..f92a303 100644 --- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c +++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -39,3 +39,7 @@ void __get_sys_info(sys_info_t *sysInfo) return; } void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); + +int get_serial_clock(void){ + return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; +} diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h index e307de9..9685560 100644 --- a/board/xilinx/ppc440-generic/xparameters.h +++ b/board/xilinx/ppc440-generic/xparameters.h @@ -17,7 +17,6 @@ #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 #define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 -#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef #define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 #endif diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig index 53fafc3..e7132cd 100644 --- a/configs/xilinx-ppc405-generic_defconfig +++ b/configs/xilinx-ppc405-generic_defconfig @@ -7,3 +7,11 @@ CONFIG_SYS_PROMPT="xlx-ppc405:/# " # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_MALLOC_SIMPLE=y +CONFIG_XILINX_UARTLITE=y +CONFIG_SYS_NS16550=y +CONFIG_OF_EMBED=y +CONFIG_OF_CONTROL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic" diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig index 79be48a..c66357e 100644 --- a/configs/xilinx-ppc440-generic_defconfig +++ b/configs/xilinx-ppc440-generic_defconfig @@ -3,7 +3,11 @@ CONFIG_4xx=y CONFIG_TARGET_XILINX_PPC440_GENERIC=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1" CONFIG_SYS_PROMPT="board:/# " -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set +CONFIG_SYS_MALLOC_SIMPLE=y +CONFIG_XILINX_UARTLITE=y +CONFIG_SYS_NS16550=y +CONFIG_OF_EMBED=y +CONFIG_OF_CONTROL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic" diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 5c7b1fa..1ab6128 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -280,7 +280,7 @@ config UNIPHIER_SERIAL config XILINX_UARTLITE bool "Xilinx Uarlite support" - depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) + depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || 4xx) help If you have a Xilinx based board and want to use the uartlite serial ports, say Y to this option. If unsure, say N. diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index c5579e1..d01d88b 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -101,23 +101,10 @@ #define CONFIG_SYS_NO_FLASH #endif -/* serial communication */ -#ifdef XPAR_UARTLITE_0_BASEADDR -#define CONFIG_XILINX_UARTLITE -#define XILINX_UARTLITE_BASEADDR XPAR_UARTLITE_0_BASEADDR -#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE -#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } -#else -#ifdef XPAR_UARTNS550_0_BASEADDR -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 XPAR_UARTNS550_0_BASEADDR -#define CONFIG_SYS_NS16550_CLK XPAR_UARTNS550_0_CLOCK_FREQ_HZ +#define CONFIG_OF_LIBFDT 1 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 } -#endif -#endif +/* The following table includes the supported baudrates */ +# define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} #endif /* __CONFIG_H */ -- cgit v0.10.2 From cd4695da8b3341b3d7fc0a5e7cc02a1e0ab432f2 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:20 +0100 Subject: ppc: xilinx_ppc405_generic: Remove weak attributes Now that the specific boards have been removed there is no need to maintain the weak functions. Fix also CamelCase to make checkpatch happy Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c index 32105a8..5c19ac0 100644 --- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -10,42 +10,36 @@ #include #include -ulong __get_PCI_freq(void) +ulong get_PCI_freq(void) { return 0; } -ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq"))); - -int __board_pre_init(void) +int board_pre_init(void) { return 0; } -int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); -int __checkboard(void) +int checkboard(void) { puts("Xilinx PPC405 Generic Board\n"); return 0; } -int checkboard(void) __attribute__((weak, alias("__checkboard"))); -phys_size_t __initdram(int board_type) +phys_size_t initdram(int board_type) { return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); } -phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); -void __get_sys_info(sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sys_info) { - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sysInfo->freqPCI = 0; + sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sys_info->freqPCI = 0; return; } -void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); int get_serial_clock(void){ return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; -- cgit v0.10.2 From 28e92109c7b2e3eb2820f7bb6c339ba0f42a2a01 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:21 +0100 Subject: ppc: xilinx_ppc440_generic: Remove weak attributes Now that the specific boards have been removed there is no need to maintain the weak functions. Fix also CamelCase to make checkpatch happy Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c index f92a303..52c63f2 100644 --- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c +++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -10,35 +10,31 @@ #include #include -int __board_pre_init(void) +int board_pre_init(void) { return 0; } -int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); -int __checkboard(void) +int checkboard(void) { puts("Xilinx PPC440 Generic Board\n"); return 0; } -int checkboard(void) __attribute__((weak, alias("__checkboard"))); -phys_size_t __initdram(int board_type) +phys_size_t initdram(int board_type) { return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); } -phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); -void __get_sys_info(sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sys_info) { - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sysInfo->freqPCI = 0; + sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sys_info->freqPCI = 0; return; } -void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); int get_serial_clock(void){ return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; -- cgit v0.10.2 From 63053071b2d2c4c5bd3b2587812143eb8e4fe263 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:22 +0100 Subject: ppc: xilinx_ppc405_generic: Remove uncalled functions board_pre_init was not called because CONFIG_BOARD_EARLY_INIT_F was not set. Remove unused function. Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c index 5c19ac0..3729f07 100644 --- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -15,11 +15,6 @@ ulong get_PCI_freq(void) return 0; } -int board_pre_init(void) -{ - return 0; -} - int checkboard(void) { puts("Xilinx PPC405 Generic Board\n"); -- cgit v0.10.2 From 7e5281fee4b6a1f1568aac396380feeaecbd349e Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:23 +0100 Subject: ppc: xilinx_ppc440_generic: Remove uncalled functions board_pre_init was not called because CONFIG_BOARD_EARLY_INIT_F was not set. Remove unused function. Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Acked-by: Stefan Roese Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c index 52c63f2..0e3ab94 100644 --- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c +++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -10,11 +10,6 @@ #include #include -int board_pre_init(void) -{ - return 0; -} - int checkboard(void) { puts("Xilinx PPC440 Generic Board\n"); -- cgit v0.10.2 From 21909baf57085994eb35089626d68d1b5b9619f7 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 11:24:24 +0100 Subject: net: xilinx_ll_temac: Fix string overflow Size of this snprintf "lltemac.%lx" is bigger than 16 characters. Replacing it with "ll_tem.%lx" Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c index 7cc8657..ca09546 100644 --- a/drivers/net/xilinx_ll_temac.c +++ b/drivers/net/xilinx_ll_temac.c @@ -303,7 +303,8 @@ int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf) if (devinf->devname) { strncpy(dev->name, devinf->devname, sizeof(dev->name)); } else { - snprintf(dev->name, sizeof(dev->name), "lltemac.%lx", devinf->base_addr); + snprintf(dev->name, sizeof(dev->name), "ll_tem.%lx", + devinf->base_addr); devinf->devname = dev->name; } -- cgit v0.10.2 From f36919a8138ed7ecd3dbce4630e02936b13907da Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Tue, 26 Jan 2016 13:47:45 +0100 Subject: ppc: xilinx-ppc440-generic: Wire LL_TEMAC driver If the xparameters file contains a LL_TEMAC definition compile its driver and the net commands. Signed-off-by: Ricardo Ribalda Delgado Reviewed-by: Bin Meng Reviewed-by: Tom Rini Signed-off-by: Michal Simek Reviewed-by: Michal Simek diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c index 0e3ab94..d823352 100644 --- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c +++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -8,6 +8,7 @@ #include #include +#include #include int checkboard(void) @@ -34,3 +35,24 @@ void get_sys_info(sys_info_t *sys_info) int get_serial_clock(void){ return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; } + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + puts("Init xilinx temac\n"); +#ifdef XPAR_LLTEMAC_0_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, + XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR); + +#endif + +#ifdef XPAR_LLTEMAC_1_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, + XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR); +#endif + + return ret; +} diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h index 9685560..b45a6a1 100644 --- a/board/xilinx/ppc440-generic/xparameters.h +++ b/board/xilinx/ppc440-generic/xparameters.h @@ -18,5 +18,9 @@ #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 #define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 #define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 +#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80 +#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98 +#define XPAR_LLTEMAC_0_BASEADDR 0x83000000 +#define XPAR_LLTEMAC_1_BASEADDR 0x83000040 #endif diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig index c66357e..3bf2c4f 100644 --- a/configs/xilinx-ppc440-generic_defconfig +++ b/configs/xilinx-ppc440-generic_defconfig @@ -11,3 +11,7 @@ CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic" +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_NETCONSOLE=y diff --git a/include/configs/xilinx-ppc440-generic.h b/include/configs/xilinx-ppc440-generic.h index 2af5f7f..f2505a6 100644 --- a/include/configs/xilinx-ppc440-generic.h +++ b/include/configs/xilinx-ppc440-generic.h @@ -8,32 +8,42 @@ #ifndef __CONFIG_H #define __CONFIG_H -/*CPU*/ +/* CPU */ #define CONFIG_440 1 #define CONFIG_XILINX_440 1 #define CONFIG_XILINX_PPC440_GENERIC 1 #include "../board/xilinx/ppc440-generic/xparameters.h" -/*Mem Map*/ +/* Mem Map */ #define CONFIG_SYS_SDRAM_SIZE_MB 256 -/*Env*/ +/* Env */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_OFFSET 0x340000 #define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) -/*Misc*/ +/* Misc */ #define CONFIG_PREBOOT "echo U-Boot is up and running;" -/*Flash*/ +/* Flash */ #define CONFIG_SYS_FLASH_SIZE (128*1024*1024) #define CONFIG_SYS_MAX_FLASH_SECT 1024 #define MTDIDS_DEFAULT "nor0=flash" #define MTDPARTS_DEFAULT "mtdparts=flash:-(user)" -/*Generic Configs*/ +/* Net */ +#ifdef XPAR_LLTEMAC_0_BASEADDR +#define CONFIG_XILINX_LL_TEMAC +#define CONFIG_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_MARVELL +#define CONFIG_NET_RANDOM_ETHADDR +#define CONFIG_LIB_RAND +#endif + +/* Generic Configs */ #include #endif /* __CONFIG_H */ -- cgit v0.10.2