From f0ff4692ff3372dec55074a8eb444943ab095abb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 15 Aug 2006 14:15:51 +0200 Subject: Add FPGA Altera Cyclone 2 support Patch by Heiko Schocher, 15 Aug 2006 diff --git a/CHANGELOG b/CHANGELOG index 24499c5..43b8678 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add FPGA Altera Cyclone 2 support + Patch by Heiko Schocher, 15 Aug 2006 + * Fix control-c handing in CONFIG_CMDLINE_EDITING Properly pass break code back from readline. Patch by Roger Blofeld, 31 Jul 2006 diff --git a/common/Makefile b/common/Makefile index eb0b5da..7e446ec 100644 --- a/common/Makefile +++ b/common/Makefile @@ -41,7 +41,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ cmd_pci.o cmd_pcmcia.o cmd_portio.o \ cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \ cmd_usb.o cmd_vfd.o \ - command.o console.o devices.o dlmalloc.o docecc.o \ + command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \ environment.o env_common.o \ env_nand.o env_dataflash.o env_flash.o env_eeprom.o \ env_nvram.o env_nowhere.o \ diff --git a/common/altera.c b/common/altera.c index ebd5038..357d702 100644 --- a/common/altera.c +++ b/common/altera.c @@ -55,10 +55,15 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize ) } else { switch (desc->family) { case Altera_ACEX1K: + case Altera_CYC2: #if (CONFIG_FPGA & CFG_ACEX1K) PRINTF ("%s: Launching the ACEX1K Loader...\n", __FUNCTION__); ret_val = ACEX1K_load (desc, buf, bsize); +#elif (CONFIG_FPGA & CFG_CYCLON2) + PRINTF ("%s: Launching the CYCLON II Loader...\n", + __FUNCTION__); + ret_val = CYC2_load (desc, buf, bsize); #else printf ("%s: No support for ACEX1K devices.\n", __FUNCTION__); @@ -113,6 +118,9 @@ int altera_info( Altera_desc *desc ) printf ("ACEX1K\n"); break; /* Add new family types here */ + case Altera_CYC2: + printf ("CYCLON II\n"); + break; default: printf ("Unknown family type, %d\n", desc->family); } @@ -147,8 +155,11 @@ int altera_info( Altera_desc *desc ) printf ("Device Function Table @ 0x%p\n", desc->iface_fns); switch (desc->family) { case Altera_ACEX1K: + case Altera_CYC2: #if (CONFIG_FPGA & CFG_ACEX1K) ACEX1K_info (desc); +#elif (CONFIG_FPGA & CFG_CYCLON2) + CYC2_info (desc); #else /* just in case */ printf ("%s: No support for ACEX1K devices.\n", @@ -188,6 +199,14 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset) __FUNCTION__); #endif break; + case Altera_CYC2: +#if (CONFIG_FPGA & CFG_CYCLON2) + ret_val = CYC2_reloc (desc, reloc_offset); +#else + printf ("%s: No support for CYCLON II devices.\n", + __FUNCTION__); +#endif + break; /* Add new family types here */ default: printf ("%s: Unsupported family type, %d\n", diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 9a01e7d..df859bd 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -55,6 +55,7 @@ static int fpga_get_op (char *opstr); #define FPGA_LOAD 1 #define FPGA_LOADB 2 #define FPGA_DUMP 3 +#define FPGA_LOADMK 4 /* Convert bitstream data and load into the fpga */ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) @@ -251,6 +252,23 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) rc = fpga_loadbitstream(dev, fpga_data, data_size); break; + case FPGA_LOADMK: + { + image_header_t header; + image_header_t *hdr = &header; + ulong data; + + memmove (&header, (char *)fpga_data, sizeof(image_header_t)); + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + puts ("Bad Magic Number\n"); + return 1; + } + data = (char *)(fpga_data + sizeof(image_header_t)); + data_size = ntohl(hdr->ih_size); + rc = fpga_load (dev, data, data_size); + } + break; + case FPGA_DUMP: rc = fpga_dump (dev, fpga_data, data_size); break; @@ -282,6 +300,8 @@ static int fpga_get_op (char *opstr) op = FPGA_LOADB; } else if (!strcmp ("load", opstr)) { op = FPGA_LOAD; + } else if (!strcmp ("loadmk", opstr)) { + op = FPGA_LOADMK; } else if (!strcmp ("dump", opstr)) { op = FPGA_DUMP; } @@ -299,5 +319,6 @@ U_BOOT_CMD (fpga, 6, 1, do_fpga, "\tinfo\tlist known device information\n" "\tload\tLoad device from memory buffer\n" "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n" + "\tloadmk\tLoad device generated with mkimage\n" "\tdump\tLoad device to memory buffer\n"); #endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */ diff --git a/common/cyclon2.c b/common/cyclon2.c new file mode 100644 index 0000000..dce13b5 --- /dev/null +++ b/common/cyclon2.c @@ -0,0 +1,305 @@ +/* + * (C) Copyright 2006 + * Heiko Schocher, hs@denx.de + * Based on ACE1XK.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include /* core U-Boot definitions */ +#include +#include /* ACEX device family */ + +#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) + +/* Define FPGA_DEBUG to get debug printf's */ +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* Note: The assumption is that we cannot possibly run fast enough to + * overrun the device (the Slave Parallel mode can free run at 50MHz). + * If there is a need to operate slower, define CONFIG_FPGA_DELAY in + * the board config file to slow things down. + */ +#ifndef CONFIG_FPGA_DELAY +#define CONFIG_FPGA_DELAY() +#endif + +#ifndef CFG_FPGA_WAIT +#define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */ +#endif + +static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize ); +static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); +/* static int CYC2_ps_info( Altera_desc *desc ); */ +static int CYC2_ps_reloc( Altera_desc *desc, ulong reloc_offset ); + +/* ------------------------------------------------------------------------- */ +/* CYCLON2 Generic Implementation */ +int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); + ret_val = CYC2_ps_load (desc, buf, bsize); + break; + + /* Add new interface types here */ + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); + ret_val = CYC2_ps_dump (desc, buf, bsize); + break; + + /* Add new interface types here */ + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +int CYC2_info( Altera_desc *desc ) +{ + return FPGA_SUCCESS; +} + +int CYC2_reloc (Altera_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume a failure */ + + if (desc->family != Altera_CYC2) { + printf ("%s: Unsupported family type, %d\n", + __FUNCTION__, desc->family); + return FPGA_FAIL; + } else + switch (desc->iface) { + case passive_serial: + ret_val = CYC2_ps_reloc (desc, reloc_offset); + break; + + /* Add new interface types here */ + + default: + printf ("%s: Unsupported interface type, %d\n", + __FUNCTION__, desc->iface); + } + + return ret_val; +} + +/* ------------------------------------------------------------------------- */ +/* CYCLON2 Passive Serial Generic Implementation */ +static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; + int ret = 0; + + PRINTF ("%s: start with interface functions @ 0x%p\n", + __FUNCTION__, fn); + + if (fn) { + int cookie = desc->cookie; /* make a local copy */ + unsigned long ts; /* timestamp */ + + PRINTF ("%s: Function Table:\n" + "ptr:\t0x%p\n" + "struct: 0x%p\n" + "config:\t0x%p\n" + "status:\t0x%p\n" + "write:\t0x%p\n" + "done:\t0x%p\n\n", + __FUNCTION__, &fn, fn, fn->config, fn->status, + fn->write, fn->done); +#ifdef CFG_FPGA_PROG_FEEDBACK + printf ("Loading FPGA Device %d...", cookie); +#endif + + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) { + (*fn->pre) (cookie); + } + + /* Establish the initial state */ + (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ + + udelay(2); /* T_cfg > 2us */ + + /* Wait for nSTATUS to be asserted */ + ts = get_timer (0); /* get current time */ + do { + CONFIG_FPGA_DELAY (); + if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ + puts ("** Timeout waiting for STATUS to go high.\n"); + (*fn->abort) (cookie); + return FPGA_FAIL; + } + } while (!(*fn->status) (cookie)); + + /* Get ready for the burn */ + CONFIG_FPGA_DELAY (); + + ret = (*fn->write) (buf, bsize, TRUE, cookie); + if (ret) { + puts ("** Write failed.\n"); + (*fn->abort) (cookie); + return FPGA_FAIL; + } +#ifdef CFG_FPGA_PROG_FEEDBACK + puts(" OK? ..."); +#endif + + CONFIG_FPGA_DELAY (); + +#ifdef CFG_FPGA_PROG_FEEDBACK + putc (' '); /* terminate the dotted line */ +#endif + + /* + * Checking FPGA's CONF_DONE signal - correctly booted ? + */ + + if ( ! (*fn->done) (cookie) ) { + puts ("** Booting failed! CONF_DONE is still deasserted.\n"); + (*fn->abort) (cookie); + return (FPGA_FAIL); + } +#ifdef CFG_FPGA_PROG_FEEDBACK + puts(" OK\n"); +#endif + + ret_val = FPGA_SUCCESS; + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (ret_val == FPGA_SUCCESS) { + puts ("Done.\n"); + } + else { + puts ("Fail.\n"); + } +#endif + (*fn->post) (cookie); + + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + +static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize) +{ + /* Readback is only available through the Slave Parallel and */ + /* boundary-scan interfaces. */ + printf ("%s: Passive Serial Dumping is unavailable\n", + __FUNCTION__); + return FPGA_FAIL; +} + +static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset) +{ + int ret_val = FPGA_FAIL; /* assume the worst */ + Altera_CYC2_Passive_Serial_fns *fn_r, *fn = + (Altera_CYC2_Passive_Serial_fns *) (desc->iface_fns); + + if (fn) { + ulong addr; + + /* Get the relocated table address */ + addr = (ulong) fn + reloc_offset; + fn_r = (Altera_CYC2_Passive_Serial_fns *) addr; + + if (!fn_r->relocated) { + + if (memcmp (fn_r, fn, + sizeof (Altera_CYC2_Passive_Serial_fns)) + == 0) { + /* good copy of the table, fix the descriptor pointer */ + desc->iface_fns = fn_r; + } else { + PRINTF ("%s: Invalid function table at 0x%p\n", + __FUNCTION__, fn_r); + return FPGA_FAIL; + } + + PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, + desc); + + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Altera_pre_fn) addr; + + addr = (ulong) (fn->config) + reloc_offset; + fn_r->config = (Altera_config_fn) addr; + + addr = (ulong) (fn->status) + reloc_offset; + fn_r->status = (Altera_status_fn) addr; + + addr = (ulong) (fn->done) + reloc_offset; + fn_r->done = (Altera_done_fn) addr; + + addr = (ulong) (fn->write) + reloc_offset; + fn_r->write = (Altera_write_fn) addr; + + addr = (ulong) (fn->abort) + reloc_offset; + fn_r->abort = (Altera_abort_fn) addr; + + addr = (ulong) (fn->post) + reloc_offset; + fn_r->post = (Altera_post_fn) addr; + + fn_r->relocated = TRUE; + + } else { + /* this table has already been moved */ + /* XXX - should check to see if the descriptor is correct */ + desc->iface_fns = fn_r; + } + + ret_val = FPGA_SUCCESS; + } else { + printf ("%s: NULL Interface function table!\n", __FUNCTION__); + } + + return ret_val; +} + +#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */ diff --git a/include/ACEX1K.h b/include/ACEX1K.h index f75c463..f249d64 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -35,6 +35,11 @@ extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize ); extern int ACEX1K_info( Altera_desc *desc ); extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off ); +extern int CYC2_load( Altera_desc *desc, void *image, size_t size ); +extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize ); +extern int CYC2_info( Altera_desc *desc ); +extern int CYC2_reloc( Altera_desc *desc, ulong reloc_off ); + /* Slave Serial Implementation function table */ typedef struct { Altera_pre_fn pre; @@ -48,6 +53,18 @@ typedef struct { int relocated; } Altera_ACEX1K_Passive_Serial_fns; +/* Slave Serial Implementation function table */ +typedef struct { + Altera_pre_fn pre; + Altera_config_fn config; + Altera_status_fn status; + Altera_done_fn done; + Altera_write_fn write; + Altera_abort_fn abort; + Altera_post_fn post; + int relocated; +} Altera_CYC2_Passive_Serial_fns; + /* Device Image Sizes *********************************************************************/ /* ACEX1K */ @@ -60,6 +77,8 @@ typedef struct { #endif #define Altera_EP1K100_SIZE (166965*8) +#define Altera_EP2C35_SIZE 883905 + /* Descriptor Macros *********************************************************************/ /* ACEX1K devices */ diff --git a/include/altera.h b/include/altera.h index 74b6729..7b8cb4a 100644 --- a/include/altera.h +++ b/include/altera.h @@ -34,8 +34,10 @@ /* Altera Model definitions *********************************************************************/ #define CFG_ACEX1K CFG_FPGA_DEV( 0x1 ) +#define CFG_CYCLON2 CFG_FPGA_DEV( 0x2 ) #define CFG_ALTERA_ACEX1K (CFG_FPGA_ALTERA | CFG_ACEX1K) +#define CFG_ALTERA_CYCLON2 (CFG_FPGA_ALTERA | CFG_CYCLON2) /* Add new models here */ /* Altera Interface definitions @@ -56,6 +58,7 @@ typedef enum { /* typedef Altera_iface */ typedef enum { /* typedef Altera_Family */ min_altera_type, /* insert all new types after this */ Altera_ACEX1K, /* ACEX1K Family */ + Altera_CYC2, /* CYCLONII Family */ /* Add new models here */ max_altera_type /* insert all new types before this */ } Altera_Family; /* end, typedef Altera_Family */ @@ -84,6 +87,7 @@ typedef int (*Altera_status_fn)( int cookie ); typedef int (*Altera_done_fn)( int cookie ); typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); +typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie); typedef int (*Altera_abort_fn)( int cookie ); typedef int (*Altera_post_fn)( int cookie ); -- cgit v0.10.2 From 899620c2d66d4eef3b2a0034d062e71d45d886c9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 15 Aug 2006 14:22:35 +0200 Subject: Add initial support for the ALPR board from Prodrive NAND needs some additional testing Patch by Heiko Schocher, 15 Aug 2006 diff --git a/CHANGELOG b/CHANGELOG index 43b8678..f01ad9e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,10 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add initial support for the ALPR board from Prodrive + NAND needs some additional testing + Patch by Heiko Schocher, 15 Aug 2006 + * Add FPGA Altera Cyclone 2 support Patch by Heiko Schocher, 15 Aug 2006 diff --git a/Makefile b/Makefile index 128ae59..fc4ffd8 100644 --- a/Makefile +++ b/Makefile @@ -818,6 +818,9 @@ xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$( ADCIOP_config: unconfig @./mkconfig $(@:_config=) ppc ppc4xx adciop esd +alpr_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx alpr prodrive + AP1000_config:unconfig @./mkconfig $(@:_config=) ppc ppc4xx ap1000 amirix diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile new file mode 100644 index 0000000..8fc6009 --- /dev/null +++ b/board/prodrive/alpr/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o fpga.o nand.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c new file mode 100644 index 0000000..4f250c4 --- /dev/null +++ b/board/prodrive/alpr/alpr.c @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern int alpr_fpga_init(void); + +int board_early_init_f (void) +{ + unsigned long mfr; + + /*-------------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------------*/ + mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | + EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | + EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | + EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); /* */ + mtdcr (uicb0tr, 0x00000000); /* */ + mtdcr (uicb0vr, 0x00000001); /* */ + mfsdr (sdr_mfr, mfr); + mfr &= ~SDR0_MFR_ECS_MASK; + + return 0; +} + +int checkboard (void) +{ + char *s = getenv ("serial#"); + + printf ("Board: ALPR"); + if (s != NULL) { + puts (", serial# "); + puts (s); + } + putc ('\n'); + + return (0); +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller * hose ) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The ocotea board is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + return 0; + } + + /* FPGA Init */ + alpr_fpga_init (); + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + + out32r( PCIX0_BAR0, 0 ); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* The ocotea board is always configured as host. */ + return(1); +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; +#if 0 + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 PCI Configuration regs. + | Enable PowerPC440 to be a master on the PCI bus (PMM). + | Enable PowerPC440 to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +#endif +#if 1 + /*--------------------------------------------------------------------------+ + | PowerPC440 PCI Master configuration. + | Map PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r( PCIX0_POM0SA, 0 ); /* disable */ + out32r( PCIX0_POM1SA, 0 ); /* disable */ + out32r( PCIX0_POM2SA, 0 ); /* disable */ + + out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */ + out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ + + out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */ + out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ + +#endif +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + + return (ctrlc()); +} +#endif diff --git a/board/prodrive/alpr/config.mk b/board/prodrive/alpr/config.mk new file mode 100644 index 0000000..9e18335 --- /dev/null +++ b/board/prodrive/alpr/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AMCC 440GX Reference Platform (Ocotea) board +# + +#TEXT_BASE = 0xFFFE0000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFFC0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c new file mode 100644 index 0000000..78307b4 --- /dev/null +++ b/board/prodrive/alpr/fpga.c @@ -0,0 +1,264 @@ +/* + * (C) Copyright 2006 + * Heiko Schocher, DENX Software Engineering, hs@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Altera FPGA configuration support for the ALPR computer from prodrive + */ + +#include +#include +#include +#include +#include +#include +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if (CONFIG_FPGA) + +#ifdef FPGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +static unsigned long regval; + +#define SET_GPIO_REG_0(reg, bit) {\ + regval = in32(reg);\ + regval &= ~(0x80000000 >> bit);\ + out32(reg, regval);\ + } + +#define SET_GPIO_REG_1(reg, bit) {\ + regval = in32(reg);\ + regval |= (0x80000000 >> bit);\ + out32(reg, regval);\ + } + +#define GPIO_CLK_PIN 0x00002000 +#define GPIO_CLK_PIN_I 0xffffdfff +#define GPIO_DAT_PIN 0x00001000 +#define GPIO_DAT_PIN_I 0xffffefff +#define GPIO_CLKDAT_PIN_I 0xffffcfff + +#define SET_GPIO_CLK_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLK_PIN_I); +#define SET_GPIO_CLK_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_CLK_PIN); +#define SET_GPIO_DAT_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_DAT_PIN_I); +#define SET_GPIO_DAT_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_DAT_PIN); + +#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) +#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) + +#define SET_GPIO_CLK_0_Z1 out32(GPIO0_OR, (in32(GPIO0_OR) & GPIO_CLK_PIN_I) | GPIO_DAT_PIN); +#define SET_GPIO_CLK_0_Z0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLKDAT_PIN_I); + +#define FPGA_WRITE_1 { \ + SET_GPIO_CLK_0_Z1\ + SET_GPIO_CLK_1} + +#define FPGA_WRITE_0 { \ + SET_GPIO_CLK_0_Z0\ + SET_GPIO_CLK_1} + +#define P_GP(reg) (reg & 0x00023f00) + +/* Plattforminitializations */ +/* Here we have to set the FPGA Chain */ +/* PROGRAM_PROG_EN = HIGH */ +/* PROGRAM_SEL_DPR = LOW */ +int fpga_pre_fn (int cookie) +{ + unsigned long reg; + + reg = in32(GPIO0_IR); + /* Enable the FPGA Chain */ + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN); + SET_GPIO_1(CFG_GPIO_PROG_EN); + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR); + SET_GPIO_0((CFG_GPIO_SEL_DPR)); + + /* initialize the GPIO Pins */ + /* output */ + SET_GPIO_0(CFG_GPIO_CLK); + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK); + + /* output */ + SET_GPIO_0(CFG_GPIO_DATA); + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA); + + /* First we set STATUS to 0 then as an input */ + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); + SET_GPIO_0(CFG_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); + + /* output */ + SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG); + SET_GPIO_0(CFG_GPIO_CONFIG); + + /* input */ + SET_GPIO_0(CFG_GPIO_CON_DON); + SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON); + SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON); + + /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ + SET_GPIO_0(CFG_GPIO_CONFIG); + return FPGA_SUCCESS; +} + +/* Set the state of CONFIG Pin */ +int fpga_config_fn (int assert_config, int flush, int cookie) +{ + if (assert_config) { + SET_GPIO_1(CFG_GPIO_CONFIG); + } else { + SET_GPIO_0(CFG_GPIO_CONFIG); + } + return FPGA_SUCCESS; +} + +/* Returns the state of STATUS Pin */ +int fpga_status_fn (int cookie) +{ + unsigned long reg; + + reg = in32(GPIO0_IR); + if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) { + PRINTF("STATUS = HIGH\n"); + return FPGA_FAIL; + } + PRINTF("STATUS = LOW\n"); + return FPGA_SUCCESS; +} + +/* Returns the state of CONF_DONE Pin */ +int fpga_done_fn (int cookie) +{ + unsigned long reg; + reg = in32(GPIO0_IR); + if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) { + PRINTF("CONF_DON = HIGH\n"); + return FPGA_FAIL; + } + PRINTF("CONF_DON = LOW\n"); + return FPGA_SUCCESS; +} + +/* writes the complete buffer to the FPGA + writing the complete buffer in one function is very faster, + then calling it for every bit */ +int fpga_write_fn (void *buf, size_t len, int flush, int cookie) +{ + size_t bytecount = 0; + unsigned char *data = (unsigned char *) buf; + unsigned char val=0; + int i; + + while (bytecount < len) { +#ifdef CFG_FPGA_CHECK_CTRLC + if (ctrlc ()) { + return FPGA_FAIL; + } +#endif + val = data[bytecount ++ ]; + i = 8; + do { + if (val & 0x01) { + FPGA_WRITE_1; + } else { + FPGA_WRITE_0; + } + val >>= 1; + i --; + } while (i > 0); + +#ifdef CFG_FPGA_PROG_FEEDBACK + if (bytecount % (len / 40) == 0) + putc ('.'); /* let them know we are alive */ +#endif + } + return FPGA_SUCCESS; +} + +/* called, when programming is aborted */ +int fpga_abort_fn (int cookie) +{ + SET_GPIO_1((CFG_GPIO_SEL_DPR)); + return FPGA_SUCCESS; +} + +/* called, when programming was succesful */ +int fpga_post_fn (int cookie) +{ + return fpga_abort_fn (cookie); +} + +/* Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + */ +Altera_CYC2_Passive_Serial_fns fpga_fns = { + fpga_pre_fn, + fpga_config_fn, + fpga_status_fn, + fpga_done_fn, + fpga_write_fn, + fpga_abort_fn, + fpga_post_fn +}; + +Altera_desc fpga[CONFIG_FPGA_COUNT] = { + {Altera_CYC2, + passive_serial, + Altera_EP2C35_SIZE, + (void *) &fpga_fns, + NULL, + 0} +}; + +/* + * Initialize the fpga. Return 1 on success, 0 on failure. + */ +int alpr_fpga_init (void) +{ + int i; + + PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); + fpga_init (gd->reloc_off); + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); + fpga_add (fpga_altera, &fpga[i]); + } + return 1; +} + +#endif diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S new file mode 100644 index 0000000..59d3ab6 --- /dev/null +++ b/board/prodrive/alpr/init.S @@ -0,0 +1,109 @@ +/* +* Copyright (C) 2002 Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) +#if 1 + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) +#endif +#if 0 + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 3, AC_R|AC_W|SA_G|SA_I ) +#endif + + /* NAND */ + tlbentry( CFG_NAND_BASE, SZ_16M, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbtab_end diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c new file mode 100644 index 0000000..bd9ba35 --- /dev/null +++ b/board/prodrive/alpr/nand.c @@ -0,0 +1,271 @@ +/* + * (C) Copyright 2006 + * Heiko Schocher, DENX Software Engineering, hs@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include + +#if 0 +#define HS_printf(fmt,arg...) \ + printf("HS %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) +#else +#define HS_printf(fmt,arg...) \ + do { } while (0) +#endif + +#if 0 +#define CPLD_REG uchar +#else +#define CPLD_REG u16 +#endif + +struct alpr_ndfc_regs { + CPLD_REG cmd[4]; + CPLD_REG addr_wait; + CPLD_REG term; + CPLD_REG dummy; + uchar dum2[2]; + CPLD_REG data; +}; + +static u8 hwctl; +static struct alpr_ndfc_regs *alpr_ndfc; +static int alpr_chip = 0; + +#if 1 +static int pdnb3_nand_dev_ready(struct mtd_info *mtd); + +#if 1 +static u_char alpr_read (void *padr) { + return (u_char )*((u16 *)(padr)); +} +#else +static u_char alpr_read (void *padr) { + u16 hilf; + u_char ret = 0; + hilf = *((u16 *)(padr)); + ret = hilf; +printf("%p hilf: %x ret: %x\n", padr, hilf, ret); + return ret; +} +#endif + +static void alpr_write (u_char byte, void *padr) { +HS_printf("%p Byte: %x\n", padr, byte); + *(volatile u16 *)padr = (u16)(byte); +} + +#elif 0 +#define alpr_read(a) (*(volatile u16 *) (a)) +#define alpr_write(a, b) ((*(volatile u16 *) (a)) = (b)) +#else +#define alpr_read(a) readw(a) +#define alpr_write(a, b) writew(a, b) +#endif +/* + * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to + * the NAND devices. The NDFC has command, address and data registers that + * when accessed will set up the NAND flash pins appropriately. We'll use the + * hwcontrol function to save the configuration in a global variable. + * We can then use this information in the read and write functions to + * determine which NDFC register to access. + * + * There are 2 NAND devices on the board, a Hynix HY27US08561A (32 MByte). + */ +static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ +HS_printf("cmd: %x\n", cmd); + switch (cmd) { + case NAND_CTL_SETCLE: + hwctl |= 0x1; + break; + case NAND_CTL_CLRCLE: + hwctl &= ~0x1; + break; + case NAND_CTL_SETALE: + hwctl |= 0x2; + break; + case NAND_CTL_CLRALE: + hwctl &= ~0x2; + break; + case NAND_CTL_SETNCE: + break; + case NAND_CTL_CLRNCE: + alpr_write(0x00, &(alpr_ndfc->term)); + break; + } +} + +static void pdnb3_nand_write_byte(struct mtd_info *mtd, u_char byte) +{ +HS_printf("hwctl: %x %x %x %x\n", hwctl, byte, &(alpr_ndfc->cmd[alpr_chip]), &(alpr_ndfc->addr_wait)); + if (hwctl & 0x1) + alpr_write(byte, &(alpr_ndfc->cmd[alpr_chip])); + else if (hwctl & 0x2) { + alpr_write(byte, &(alpr_ndfc->addr_wait)); + } else + alpr_write(byte, &(alpr_ndfc->data)); +} + +static u_char pdnb3_nand_read_byte(struct mtd_info *mtd) +{ + return alpr_read(&(alpr_ndfc->data)); +} + +static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + +/*printf("%s chip:%d hwctl:%x size:%d\n", __FUNCTION__, alpr_chip, hwctl, len);*/ + for (i = 0; i < len; i++) { + if (hwctl & 0x1) + alpr_write(buf[i], &(alpr_ndfc->cmd[alpr_chip])); + else if (hwctl & 0x2) { + alpr_write(buf[i], &(alpr_ndfc->addr_wait)); + } else { + alpr_write(buf[i], &(alpr_ndfc->data)); + /*printf("i: %d\n", i);*/ + } + } +} + +static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) { + buf[i] = alpr_read(&(alpr_ndfc->data)); + } +} + +static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + if (buf[i] != alpr_read(&(alpr_ndfc->data))) + return i; + + return 0; +} + +static int pdnb3_nand_dev_ready(struct mtd_info *mtd) +{ +#if 1 + volatile u_char val; + +/*printf("%s aufruf\n", __FUNCTION__);*/ + /* + * Blocking read to wait for NAND to be ready + */ + val = alpr_read(&(alpr_ndfc->addr_wait)); + + /* + * Return always true + */ + return 1; +#else + u8 hwctl_org = hwctl; + unsigned long timeo; + u8 val; + + hwctl = 0x01; + pdnb3_nand_write_byte (mtd, NAND_CMD_STATUS); + hwctl = hwctl_org; + + reset_timer(); + while (1) { + if (get_timer(0) > timeo) { + printf("Timeout!"); + return 0; + } + +val = pdnb3_nand_read_byte(mtd); +/*printf("%s val: %x\n", __FUNCTION__, val);*/ + if (val & NAND_STATUS_READY) + break; + } + return 1; +#endif + +} + +static void alpr_select_chip(struct mtd_info *mtd, int chip) +{ + alpr_chip = chip; +} + +static int alpr_nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long timeo; + + if (state == FL_ERASING) + timeo = CFG_HZ * 400; + else + timeo = CFG_HZ * 20; + + if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) + this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); + else + this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + + reset_timer(); + + while (1) { + if (get_timer(0) > timeo) { + printf("Timeout!"); + return 0; + } + + if (this->read_byte(mtd) & NAND_STATUS_READY) + break; + } + return this->read_byte(mtd); +} + +void board_nand_init(struct nand_chip *nand) +{ + alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE; + + nand->eccmode = NAND_ECC_SOFT; + + /* Set address of NAND IO lines (Using Linear Data Access Region) */ + nand->IO_ADDR_R = (void __iomem *) ((ulong) alpr_ndfc + 0x10); + nand->IO_ADDR_W = (void __iomem *) ((ulong) alpr_ndfc + 0x10); + /* Reference hardware control function */ + nand->hwcontrol = pdnb3_nand_hwcontrol; + /* Set command delay time */ + nand->hwcontrol = pdnb3_nand_hwcontrol; + nand->write_byte = pdnb3_nand_write_byte; + nand->read_byte = pdnb3_nand_read_byte; + nand->write_buf = pdnb3_nand_write_buf; + nand->read_buf = pdnb3_nand_read_buf; + nand->verify_buf = pdnb3_nand_verify_buf; + nand->dev_ready = pdnb3_nand_dev_ready; + nand->select_chip = alpr_select_chip; + nand->waitfunc = alpr_nand_wait; +} +#endif diff --git a/board/prodrive/alpr/u-boot.lds b/board/prodrive/alpr/u-boot.lds new file mode 100644 index 0000000..4f04089 --- /dev/null +++ b/board/prodrive/alpr/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/prodrive/alpr/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 0b0686b..7e2c7c1 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -475,7 +475,11 @@ void pci_440_init (struct pci_controller *hose) pci_set_region(hose->regions + reg_num++, CFG_PCI_TARGBASE, CFG_PCI_MEMBASE, +#ifdef CFG_PCI_MEMSIZE + CFG_PCI_MEMSIZE, +#else 0x10000000, +#endif PCI_REGION_MEM ); #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index fab65af..d166993 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -502,6 +502,21 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) * otherwise, just check the speeds & feeds */ if (hw_p->first_init == 0) { +#if defined(CONFIG_88E1111_CLK_DELAY) + /* + * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs + * the "RGMII transmit timing control" and "RGMII receive + * timing control" bits set, so that Gbit communication works + * without problems. + * Also set the "Transmitter disable" to 1 to enable the + * transmitter. + * After setting these bits a soft-reset must occur for this + * change to become active. + */ + miiphy_read (dev->name, reg, 0x14, ®_short); + reg_short |= (1 << 7) | (1 << 1) | (1 << 0); + miiphy_write (dev->name, reg, 0x14, reg_short); +#endif miiphy_reset (dev->name, reg); #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index faeea5c..f06038e 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -351,6 +351,14 @@ long int initdram(int board_type) int i; int tr1_bank1; +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) + /* + * Soft-reset SDRAM controller. + */ + mtsdr(sdr_srst, SDR0_SRST_DMC); + mtsdr(sdr_srst, 0x00000000); +#endif + for (i=0; i + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/*----------------------------------------------------------------------- + * FPGA stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_FPGA CFG_ALTERA_CYCLON2 +#undef CFG_FPGA_CHECK_CTRLC +#undef CFG_FPGA_PROG_FEEDBACK +#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in + Reihe geschaltet -> sollte gehen, + aufpassen mit Datasize ist jetzt + halt doppelt so gross ... Seite 306 + ist das mit den multiple Device in PS + Mode erklaert ...*/ + + +/* FPGA program pin configuration */ +#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ +#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */ +#define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */ +#define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */ +#define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */ + +#define CFG_GPIO_SEL_DPR 14 /* cpu output */ +#define CFG_GPIO_SEL_AVR 15 /* cpu output */ +#define CFG_GPIO_PROG_EN 23 /* cpu output */ + +/* + * NAND-FLASH stuff + */ +#define CFG_MAX_NAND_DEVICE 2 +#define NAND_MAX_CHIPS 2 +#define CFG_NAND_BASE 0x50000000 /* NAND FLASH Base Address */ + +#if 0 +#define CONFIG_MTD_DEBUG +#define CONFIG_MTD_DEBUG_VERBOSE 4 +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ +/* Memory Bank 1 (NAND-FLASH) initialization */ +/*#define CFG_EBC_PB1AP 0x108f4380 */ /* TODO */ +/*#define CFG_EBC_PB1AP 0x7f854380 */ /* TODO */ +/*#define CFG_EBC_PB1AP 0x108553c0 */ +/*#define CFG_EBC_PB1AP 0x108053c0 */ +#define CFG_EBC_PB1AP 0x10810180 + +/*#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) *//* BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/ppc440.h b/include/ppc440.h index d5a9f66..b81e34d 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -2631,7 +2631,7 @@ #define GPIO0 0 #define GPIO1 1 -#if defined(CONFIG_440GP) +#if defined(CONFIG_440GP) || defined(CONFIG_440GX) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) #define GPIO0_OR (GPIO0_BASE+0x0) -- cgit v0.10.2 From f3443867e90d2979a7dd1c65b0d537777e1f9850 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 7 Oct 2006 11:30:52 +0200 Subject: Add CONFIG_BOARD_RESET to configure board specific reset function Patch by Stefan Roese, 07 Oct 2006 diff --git a/CHANGELOG b/CHANGELOG index e5fa93b..4af0200 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add CONFIG_BOARD_RESET to configure board specific reset function + Patch by Stefan Roese, 07 Oct 2006 + * Remove compile warnings in fpga code Patch by Stefan Roese, 18 Sep 2006 diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c index 92dc9d4..754ae44 100644 --- a/board/amcc/yellowstone/yellowstone.c +++ b/board/amcc/yellowstone/yellowstone.c @@ -552,3 +552,9 @@ void hw_watchdog_reset(void) } #endif + +void board_reset(void) +{ + /* give reset to BCSR */ + *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; +} diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 7f2e718..588ee90 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -548,3 +548,9 @@ void hw_watchdog_reset(void) } #endif + +void board_reset(void) +{ + /* give reset to BCSR */ + *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; +} diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 94478db..4e81ce2 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -41,6 +41,10 @@ DECLARE_GLOBAL_DATA_PTR; #endif +#if defined(CONFIG_BOARD_RESET) +void board_reset(void); +#endif + #if defined(CONFIG_440) #define FREQ_EBC (sys_info.freqEPB) #else @@ -414,23 +418,15 @@ int ppc440spe_revB() { int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE) - /*give reset to BCSR*/ - *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09; - +#if defined(CONFIG_BOARD_RESET) + board_reset(); #else - /* * Initiate system reset in debug control register DBCR */ - __asm__ __volatile__("lis 3, 0x3000" ::: "r3"); -#if defined(CONFIG_440) - __asm__ __volatile__("mtspr 0x134, 3"); -#else - __asm__ __volatile__("mtspr 0x3f2, 3"); -#endif + mtspr(dbcr0, 0x30000000); +#endif /* defined(CONFIG_BOARD_RESET) */ -#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/ return 1; } diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index ba27f37..58717f8 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -37,6 +37,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_BOARD_RESET 1 /* call board_reset() */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 3d7b4a2..6e942ab 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -37,6 +37,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_BOARD_RESET 1 /* call board_reset() */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the -- cgit v0.10.2 From 77d5034847d328753b80c46b83f960a14a26f40e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 7 Oct 2006 11:33:03 +0200 Subject: Remove compile warnings in fpga code Patch by Stefan Roese, 07 Oct 2006 diff --git a/CHANGELOG b/CHANGELOG index 4af0200..7ed5e66 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Remove compile warnings in fpga code + Patch by Stefan Roese, 07 Oct 2006 + * Add CONFIG_BOARD_RESET to configure board specific reset function Patch by Stefan Roese, 07 Oct 2006 diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index df859bd..3444091 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -263,9 +263,9 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) puts ("Bad Magic Number\n"); return 1; } - data = (char *)(fpga_data + sizeof(image_header_t)); + data = ((ulong)fpga_data + sizeof(image_header_t)); data_size = ntohl(hdr->ih_size); - rc = fpga_load (dev, data, data_size); + rc = fpga_load (dev, (void *)data, data_size); } break; -- cgit v0.10.2 From 5bc528fa4da751d472397b308137238a6465afd2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 7 Oct 2006 11:35:25 +0200 Subject: Update ALPR code (NAND support working now) Patch by Stefan Roese, 07 Oct 2006 diff --git a/CHANGELOG b/CHANGELOG index 7ed5e66..a21526b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Update ALPR code (NAND support working now) + Patch by Stefan Roese, 07 Oct 2006 + * Remove compile warnings in fpga code Patch by Stefan Roese, 07 Oct 2006 diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile index 993ad19..1024a41 100644 --- a/board/prodrive/alpr/Makefile +++ b/board/prodrive/alpr/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o fpga.o nand.o +COBJS = $(BOARD).o flash.o fpga.o nand.o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 4f250c4..e8435bf 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -38,11 +38,19 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ +#if 0 mtebc(xbcfg, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); +#else + mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | + EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | + EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | + EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); +#endif /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -230,19 +238,6 @@ int is_pci_host(struct pci_controller *hose) #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { - unsigned short temp_short; -#if 0 - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 PCI Configuration regs. - | Enable PowerPC440 to be a master on the PCI bus (PMM). - | Enable PowerPC440 to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -#endif -#if 1 /*--------------------------------------------------------------------------+ | PowerPC440 PCI Master configuration. | Map PLB/processor addresses to PCI memory space. @@ -265,8 +260,6 @@ void pci_master_init(struct pci_controller *hose) out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ - -#endif } #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ @@ -281,3 +274,11 @@ int post_hotkeys_pressed(void) return (ctrlc()); } #endif + +void board_reset(void) +{ + /* + * Initiate chip reset in debug control register DBCR + */ + mtspr(dbcr0, 0x20000000); +} diff --git a/board/prodrive/alpr/flash.c b/board/prodrive/alpr/flash.c new file mode 100644 index 0000000..8fa0084 --- /dev/null +++ b/board/prodrive/alpr/flash.c @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/* + * Prototypes + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); + +unsigned long flash_init(void) +{ + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; i -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ #include #include @@ -27,15 +28,15 @@ #define TLB_VALID 0x00000200 /* Supported page sizes */ - #define SZ_1K 0x00000000 #define SZ_4K 0x00000010 #define SZ_16K 0x00000020 #define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 +#define SZ_256K 0x00000040 #define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 #define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 +#define SZ_256M 0x00000090 /* Storage attributes */ #define SA_W 0x00000800 /* Write-through */ @@ -81,29 +82,23 @@ * *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab + .section .bootpg,"ax" + .globl tlbtab tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - - /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) -#if 1 - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) -#endif -#if 0 - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 3, AC_R|AC_W|SA_G|SA_I ) -#endif - - /* NAND */ - tlbentry( CFG_NAND_BASE, SZ_16M, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbtab_end + tlbtab_start + tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) + + /* NAND */ + tlbentry( CFG_NAND_BASE, SZ_4K, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbtab_end diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index bd9ba35..20a8098 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -2,6 +2,9 @@ * (C) Copyright 2006 * Heiko Schocher, DENX Software Engineering, hs@denx.de * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * * See file CREDITS for list of people who contributed to this * project. * @@ -22,69 +25,27 @@ */ #include -#include #if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include #include -#if 0 -#define HS_printf(fmt,arg...) \ - printf("HS %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) -#else -#define HS_printf(fmt,arg...) \ - do { } while (0) -#endif - -#if 0 -#define CPLD_REG uchar -#else -#define CPLD_REG u16 -#endif - struct alpr_ndfc_regs { - CPLD_REG cmd[4]; - CPLD_REG addr_wait; - CPLD_REG term; - CPLD_REG dummy; - uchar dum2[2]; - CPLD_REG data; + u16 cmd[4]; + u16 addr_wait; + u16 term; + u16 dummy; + u16 dummy2; + u16 data; }; static u8 hwctl; -static struct alpr_ndfc_regs *alpr_ndfc; -static int alpr_chip = 0; +static struct alpr_ndfc_regs *alpr_ndfc = NULL; -#if 1 -static int pdnb3_nand_dev_ready(struct mtd_info *mtd); +#define readb(addr) (u8)(*(volatile u16 *)(addr)) +#define writeb(d,addr) *(volatile u16 *)(addr) = ((u16)(d)) -#if 1 -static u_char alpr_read (void *padr) { - return (u_char )*((u16 *)(padr)); -} -#else -static u_char alpr_read (void *padr) { - u16 hilf; - u_char ret = 0; - hilf = *((u16 *)(padr)); - ret = hilf; -printf("%p hilf: %x ret: %x\n", padr, hilf, ret); - return ret; -} -#endif - -static void alpr_write (u_char byte, void *padr) { -HS_printf("%p Byte: %x\n", padr, byte); - *(volatile u16 *)padr = (u16)(byte); -} - -#elif 0 -#define alpr_read(a) (*(volatile u16 *) (a)) -#define alpr_write(a, b) ((*(volatile u16 *) (a)) = (b)) -#else -#define alpr_read(a) readw(a) -#define alpr_write(a, b) writew(a, b) -#endif /* * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to * the NAND devices. The NDFC has command, address and data registers that @@ -93,11 +54,10 @@ HS_printf("%p Byte: %x\n", padr, byte); * We can then use this information in the read and write functions to * determine which NDFC register to access. * - * There are 2 NAND devices on the board, a Hynix HY27US08561A (32 MByte). + * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte). */ -static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd) { -HS_printf("cmd: %x\n", cmd); switch (cmd) { case NAND_CTL_SETCLE: hwctl |= 0x1; @@ -114,136 +74,84 @@ HS_printf("cmd: %x\n", cmd); case NAND_CTL_SETNCE: break; case NAND_CTL_CLRNCE: - alpr_write(0x00, &(alpr_ndfc->term)); + writeb(0x00, &(alpr_ndfc->term)); break; } } -static void pdnb3_nand_write_byte(struct mtd_info *mtd, u_char byte) +static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte) { -HS_printf("hwctl: %x %x %x %x\n", hwctl, byte, &(alpr_ndfc->cmd[alpr_chip]), &(alpr_ndfc->addr_wait)); + struct nand_chip *nand = mtd->priv; + if (hwctl & 0x1) - alpr_write(byte, &(alpr_ndfc->cmd[alpr_chip])); + /* + * IO_ADDR_W used as CMD[i] reg to support multiple NAND + * chips. + */ + writeb(byte, nand->IO_ADDR_W); else if (hwctl & 0x2) { - alpr_write(byte, &(alpr_ndfc->addr_wait)); + writeb(byte, &(alpr_ndfc->addr_wait)); } else - alpr_write(byte, &(alpr_ndfc->data)); + writeb(byte, &(alpr_ndfc->data)); } -static u_char pdnb3_nand_read_byte(struct mtd_info *mtd) +static u_char alpr_nand_read_byte(struct mtd_info *mtd) { - return alpr_read(&(alpr_ndfc->data)); + return readb(&(alpr_ndfc->data)); } -static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { + struct nand_chip *nand = mtd->priv; int i; -/*printf("%s chip:%d hwctl:%x size:%d\n", __FUNCTION__, alpr_chip, hwctl, len);*/ for (i = 0; i < len; i++) { if (hwctl & 0x1) - alpr_write(buf[i], &(alpr_ndfc->cmd[alpr_chip])); - else if (hwctl & 0x2) { - alpr_write(buf[i], &(alpr_ndfc->addr_wait)); - } else { - alpr_write(buf[i], &(alpr_ndfc->data)); - /*printf("i: %d\n", i);*/ - } + /* + * IO_ADDR_W used as CMD[i] reg to support multiple NAND + * chips. + */ + writeb(buf[i], nand->IO_ADDR_W); + else if (hwctl & 0x2) + writeb(buf[i], &(alpr_ndfc->addr_wait)); + else + writeb(buf[i], &(alpr_ndfc->data)); } } -static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) { int i; for (i = 0; i < len; i++) { - buf[i] = alpr_read(&(alpr_ndfc->data)); + buf[i] = readb(&(alpr_ndfc->data)); } } -static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) { int i; for (i = 0; i < len; i++) - if (buf[i] != alpr_read(&(alpr_ndfc->data))) + if (buf[i] != readb(&(alpr_ndfc->data))) return i; return 0; } -static int pdnb3_nand_dev_ready(struct mtd_info *mtd) +static int alpr_nand_dev_ready(struct mtd_info *mtd) { -#if 1 volatile u_char val; -/*printf("%s aufruf\n", __FUNCTION__);*/ /* * Blocking read to wait for NAND to be ready */ - val = alpr_read(&(alpr_ndfc->addr_wait)); + val = readb(&(alpr_ndfc->addr_wait)); /* * Return always true */ return 1; -#else - u8 hwctl_org = hwctl; - unsigned long timeo; - u8 val; - - hwctl = 0x01; - pdnb3_nand_write_byte (mtd, NAND_CMD_STATUS); - hwctl = hwctl_org; - - reset_timer(); - while (1) { - if (get_timer(0) > timeo) { - printf("Timeout!"); - return 0; - } - -val = pdnb3_nand_read_byte(mtd); -/*printf("%s val: %x\n", __FUNCTION__, val);*/ - if (val & NAND_STATUS_READY) - break; - } - return 1; -#endif - -} - -static void alpr_select_chip(struct mtd_info *mtd, int chip) -{ - alpr_chip = chip; -} - -static int alpr_nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) -{ - unsigned long timeo; - - if (state == FL_ERASING) - timeo = CFG_HZ * 400; - else - timeo = CFG_HZ * 20; - - if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) - this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); - else - this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); - - reset_timer(); - - while (1) { - if (get_timer(0) > timeo) { - printf("Timeout!"); - return 0; - } - - if (this->read_byte(mtd) & NAND_STATUS_READY) - break; - } - return this->read_byte(mtd); } void board_nand_init(struct nand_chip *nand) @@ -252,20 +160,14 @@ void board_nand_init(struct nand_chip *nand) nand->eccmode = NAND_ECC_SOFT; - /* Set address of NAND IO lines (Using Linear Data Access Region) */ - nand->IO_ADDR_R = (void __iomem *) ((ulong) alpr_ndfc + 0x10); - nand->IO_ADDR_W = (void __iomem *) ((ulong) alpr_ndfc + 0x10); /* Reference hardware control function */ - nand->hwcontrol = pdnb3_nand_hwcontrol; + nand->hwcontrol = alpr_nand_hwcontrol; /* Set command delay time */ - nand->hwcontrol = pdnb3_nand_hwcontrol; - nand->write_byte = pdnb3_nand_write_byte; - nand->read_byte = pdnb3_nand_read_byte; - nand->write_buf = pdnb3_nand_write_buf; - nand->read_buf = pdnb3_nand_read_buf; - nand->verify_buf = pdnb3_nand_verify_buf; - nand->dev_ready = pdnb3_nand_dev_ready; - nand->select_chip = alpr_select_chip; - nand->waitfunc = alpr_nand_wait; + nand->write_byte = alpr_nand_write_byte; + nand->read_byte = alpr_nand_read_byte; + nand->write_buf = alpr_nand_write_buf; + nand->read_buf = alpr_nand_read_buf; + nand->verify_buf = alpr_nand_verify_buf; + nand->dev_ready = alpr_nand_dev_ready; } #endif diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c index 8630cc1..363631f 100644 --- a/board/prodrive/common/flash.c +++ b/board/prodrive/common/flash.c @@ -48,6 +48,7 @@ void flash_print_info(flash_info_t *info) case FLASH_MAN_AMD: printf ("AMD "); break; case FLASH_MAN_FUJ: printf ("FUJITSU "); break; case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("ST "); break; case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; default: printf ("Unknown Vendor "); break; } @@ -156,6 +157,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; + case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; diff --git a/include/configs/alpr.h b/include/configs/alpr.h index eeafcd6..c6731ba 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -31,8 +31,9 @@ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_BOARD_RESET 1 /* call board_reset() */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CONFIG_SYS_CLK_FREQ 33333000 /* external freq to pll */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -81,44 +82,28 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#if 0 /* test-only */ -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ -#endif - -/*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ @@ -177,7 +162,7 @@ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ @@ -216,24 +201,10 @@ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_88E1111_CLK_DELAY 1 /* set CLK delay on ALPR */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ -#if 0 /* test-only */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) -#else #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ CFG_CMD_DHCP | \ @@ -250,7 +221,6 @@ CFG_CMD_FPGA | \ CFG_CMD_NAND | \ CFG_CMD_REGINFO) -#endif /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -279,15 +249,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -321,7 +288,6 @@ ist das mit den multiple Device in PS Mode erklaert ...*/ - /* FPGA program pin configuration */ #define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ #define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */ @@ -336,14 +302,12 @@ /* * NAND-FLASH stuff */ -#define CFG_MAX_NAND_DEVICE 2 -#define NAND_MAX_CHIPS 2 -#define CFG_NAND_BASE 0x50000000 /* NAND FLASH Base Address */ - -#if 0 -#define CONFIG_MTD_DEBUG -#define CONFIG_MTD_DEBUG_VERBOSE 4 -#endif +#define CFG_MAX_NAND_DEVICE 4 +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE +#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \ + CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 } +#define CFG_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup @@ -353,14 +317,9 @@ /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x92015480 #define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ -/* Memory Bank 1 (NAND-FLASH) initialization */ -/*#define CFG_EBC_PB1AP 0x108f4380 */ /* TODO */ -/*#define CFG_EBC_PB1AP 0x7f854380 */ /* TODO */ -/*#define CFG_EBC_PB1AP 0x108553c0 */ -/*#define CFG_EBC_PB1AP 0x108053c0 */ -#define CFG_EBC_PB1AP 0x10810180 - -/*#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) *//* BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 1 (NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */ #define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ /* -- cgit v0.10.2 From 5c912cb1c31266c66ca59b36f9b6f87296421d75 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 7 Oct 2006 11:36:51 +0200 Subject: CFG_NAND_QUIET_TEST added to not warn upon missing NAND device Patch by Stefan Roese, 07 Oct 2006 diff --git a/CHANGELOG b/CHANGELOG index a21526b..d2d5324 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* CFG_NAND_QUIET_TEST added to not warn upon missing NAND device + Patch by Stefan Roese, 07 Oct 2006 + * Update ALPR code (NAND support working now) Patch by Stefan Roese, 07 Oct 2006 diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c index b7a5d32..b003085 100644 --- a/drivers/nand/nand_base.c +++ b/drivers/nand/nand_base.c @@ -2407,7 +2407,9 @@ int nand_scan (struct mtd_info *mtd, int maxchips) } if (!nand_flash_ids[i].name) { +#ifndef CFG_NAND_QUIET_TEST printk (KERN_WARNING "No NAND device found!!!\n"); +#endif this->select_chip(mtd, -1); return 1; } -- cgit v0.10.2 From 1c2ce2262069510f31c7d3fd7efd3d58b8c0c148 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 27 Nov 2006 14:12:17 +0100 Subject: [PATCH] Update Prodrive ALPR board support (440GX) Signed-off-by: Stefan Roese diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile index 1024a41..00dc180 100644 --- a/board/prodrive/alpr/Makefile +++ b/board/prodrive/alpr/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o fpga.o nand.o +COBJS = $(BOARD).o fpga.o nand.o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) @@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index e8435bf..2389561 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -26,6 +26,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -33,24 +34,14 @@ extern int alpr_fpga_init(void); int board_early_init_f (void) { - unsigned long mfr; - - /*-------------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------------*/ -#if 0 - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | - EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | - EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); -#else + /*------------------------------------------------------------------------- + * Initialize EBC CONFIG + *-------------------------------------------------------------------------*/ mtebc(xbcfg, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); -#endif /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -58,8 +49,8 @@ int board_early_init_f (void) mtdcr (uic0sr, 0xffffffff); /* clear all */ mtdcr (uic0er, 0x00000000); /* disable all */ mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr (uic0pr, 0xfffffe03); /* per manual */ + mtdcr (uic0tr, 0x01c00000); /* per manual */ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic0sr, 0xffffffff); /* clear all */ @@ -85,12 +76,57 @@ int board_early_init_f (void) mtdcr (uicb0pr, 0xfc000000); /* */ mtdcr (uicb0tr, 0x00000000); /* */ mtdcr (uicb0vr, 0x00000001); /* */ - mfsdr (sdr_mfr, mfr); - mfr &= ~SDR0_MFR_ECS_MASK; + + /* Setup GPIO/IRQ multiplexing */ + mtsdr(sdr_pfc0, 0x01a03e00); return 0; } +int last_stage_init(void) +{ + unsigned short reg; + + /* + * Configure LED's of both Marvell 88E1111 PHY's + * + * This has to be done after the 4xx ethernet driver is loaded, + * so "last_stage_init()" is the right place. + */ + miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®); + reg |= 0x0001; + miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg); + miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®); + reg |= 0x0001; + miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg); + + return 0; +} + +static int board_rev(void) +{ + int rev; + u32 pfc0; + + /* Setup GPIO14 & 15 as GPIO */ + mfsdr(sdr_pfc0, pfc0); + pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1; + mtsdr(sdr_pfc0, pfc0); + + /* Setup as input */ + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); + + rev = (in32(GPIO0_IR) >> 16) & 0x3; + + /* Setup GPIO14 & 15 as non GPIO again */ + mfsdr(sdr_pfc0, pfc0); + pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1); + mtsdr(sdr_pfc0, pfc0); + + return rev; +} + int checkboard (void) { char *s = getenv ("serial#"); @@ -100,7 +136,7 @@ int checkboard (void) puts (", serial# "); puts (s); } - putc ('\n'); + printf(" (Rev. %d)\n", board_rev()); return (0); } @@ -224,10 +260,26 @@ void pci_target_init(struct pci_controller * hose ) * ************************************************************************/ #if defined(CONFIG_PCI) + +static void wait_for_pci_ready(void) +{ + /* + * Configure EREADY as input + */ + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY); + udelay(1000); + + for (;;) { + if (in32(GPIO0_IR) & CFG_GPIO_EREADY) + return; + } + +} + int is_pci_host(struct pci_controller *hose) { - /* The ocotea board is always configured as host. */ - return(1); + wait_for_pci_ready(); + return 1; /* return 1 for host controller */ } #endif /* defined(CONFIG_PCI) */ @@ -274,11 +326,3 @@ int post_hotkeys_pressed(void) return (ctrlc()); } #endif - -void board_reset(void) -{ - /* - * Initiate chip reset in debug control register DBCR - */ - mtspr(dbcr0, 0x20000000); -} diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c index 78307b4..e94360f 100644 --- a/board/prodrive/alpr/fpga.c +++ b/board/prodrive/alpr/fpga.c @@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_FPGA) +#if defined(CONFIG_FPGA) #ifdef FPGA_DEBUG #define PRINTF(fmt,args...) printf (fmt ,##args) @@ -44,46 +44,38 @@ DECLARE_GLOBAL_DATA_PTR; #define PRINTF(fmt,args...) #endif -static unsigned long regval; +static unsigned long regval; -#define SET_GPIO_REG_0(reg, bit) {\ - regval = in32(reg);\ - regval &= ~(0x80000000 >> bit);\ - out32(reg, regval);\ - } - -#define SET_GPIO_REG_1(reg, bit) {\ - regval = in32(reg);\ - regval |= (0x80000000 >> bit);\ - out32(reg, regval);\ - } - -#define GPIO_CLK_PIN 0x00002000 -#define GPIO_CLK_PIN_I 0xffffdfff -#define GPIO_DAT_PIN 0x00001000 -#define GPIO_DAT_PIN_I 0xffffefff -#define GPIO_CLKDAT_PIN_I 0xffffcfff +#define SET_GPIO_REG_0(reg, bit) { \ + regval = in32(reg); \ + regval &= ~(0x80000000 >> bit); \ + out32(reg, regval); \ + } -#define SET_GPIO_CLK_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLK_PIN_I); -#define SET_GPIO_CLK_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_CLK_PIN); -#define SET_GPIO_DAT_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_DAT_PIN_I); -#define SET_GPIO_DAT_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_DAT_PIN); +#define SET_GPIO_REG_1(reg, bit) { \ + regval = in32(reg); \ + regval |= (0x80000000 >> bit); \ + out32(reg, regval); \ + } -#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) -#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) +#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) +#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) -#define SET_GPIO_CLK_0_Z1 out32(GPIO0_OR, (in32(GPIO0_OR) & GPIO_CLK_PIN_I) | GPIO_DAT_PIN); -#define SET_GPIO_CLK_0_Z0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLKDAT_PIN_I); +#define FPGA_PRG (0x80000000 >> CFG_GPIO_PROG_EN) +#define FPGA_CONFIG (0x80000000 >> CFG_GPIO_CONFIG) +#define FPGA_DATA (0x80000000 >> CFG_GPIO_DATA) +#define FPGA_CLK (0x80000000 >> CFG_GPIO_CLK) +#define OLD_VAL (FPGA_PRG | FPGA_CONFIG) -#define FPGA_WRITE_1 { \ - SET_GPIO_CLK_0_Z1\ - SET_GPIO_CLK_1} +#define SET_FPGA(data) out32(GPIO0_OR, data) -#define FPGA_WRITE_0 { \ - SET_GPIO_CLK_0_Z0\ - SET_GPIO_CLK_1} +#define FPGA_WRITE_1 { \ + SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \ + SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ -#define P_GP(reg) (reg & 0x00023f00) +#define FPGA_WRITE_0 { \ + SET_FPGA(OLD_VAL | 0 | 0 ); /* set data to 0 */ \ + SET_FPGA(OLD_VAL | FPGA_CLK | 0 );} /* set data to 1 */ /* Plattforminitializations */ /* Here we have to set the FPGA Chain */ @@ -102,7 +94,7 @@ int fpga_pre_fn (int cookie) SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR); SET_GPIO_0((CFG_GPIO_SEL_DPR)); - /* initialize the GPIO Pins */ + /* initialize the GPIO Pins */ /* output */ SET_GPIO_0(CFG_GPIO_CLK); SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK); @@ -174,7 +166,7 @@ int fpga_done_fn (int cookie) } /* writes the complete buffer to the FPGA - writing the complete buffer in one function is very faster, + writing the complete buffer in one function is much faster, then calling it for every bit */ int fpga_write_fn (void *buf, size_t len, int flush, int cookie) { @@ -182,14 +174,10 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie) unsigned char *data = (unsigned char *) buf; unsigned char val=0; int i; + int len_40 = len / 40; while (bytecount < len) { -#ifdef CFG_FPGA_CHECK_CTRLC - if (ctrlc ()) { - return FPGA_FAIL; - } -#endif - val = data[bytecount ++ ]; + val = data[bytecount++]; i = 8; do { if (val & 0x01) { @@ -202,8 +190,13 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie) } while (i > 0); #ifdef CFG_FPGA_PROG_FEEDBACK - if (bytecount % (len / 40) == 0) + if (bytecount % len_40 == 0) { putc ('.'); /* let them know we are alive */ +#ifdef CFG_FPGA_CHECK_CTRLC + if (ctrlc ()) + return FPGA_FAIL; +#endif + } #endif } return FPGA_SUCCESS; diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S index 1baa609..135674c 100644 --- a/board/prodrive/alpr/init.S +++ b/board/prodrive/alpr/init.S @@ -34,7 +34,6 @@ #define SZ_64K 0x00000030 #define SZ_256K 0x00000040 #define SZ_1M 0x00000050 -#define SZ_8M 0x00000060 #define SZ_16M 0x00000070 #define SZ_256M 0x00000090 diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index 20a8098..e63c921 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -32,19 +32,19 @@ #include struct alpr_ndfc_regs { - u16 cmd[4]; - u16 addr_wait; - u16 term; - u16 dummy; - u16 dummy2; - u16 data; + u8 cmd[4]; + u8 addr_wait; + u8 term; + u8 dummy; + u8 dummy2; + u8 data; }; static u8 hwctl; static struct alpr_ndfc_regs *alpr_ndfc = NULL; -#define readb(addr) (u8)(*(volatile u16 *)(addr)) -#define writeb(d,addr) *(volatile u16 *)(addr) = ((u16)(d)) +#define readb(addr) (u8)(*(volatile u8 *)(addr)) +#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d)) /* * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 81d49ff..8c517ba 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -470,8 +470,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #else if ((devnum == 0) || (devnum == 1)) { out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); - } - else { /* ((devnum == 2) || (devnum == 3)) */ + } else { /* ((devnum == 2) || (devnum == 3)) */ out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | (RGMII_FER_RGMII << RGMII_FER_V (3)))); @@ -808,7 +807,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; hw_p->rx_ready[i] = -1; #if 0 - printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr); + printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr); #endif } diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index faa5257..c45525d 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -426,8 +426,8 @@ int ppc440spe_revB() { int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if defined(CONFIG_BOARD_RESET) - board_reset(); +#if defined(CFG_4xx_RESET_TYPE) + mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); #else /* * Initiate system reset in debug control register DBCR diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index def46f1..4b746b0 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -321,6 +321,10 @@ cpu_init_f (void) #else val |= 0xf0000000; /* generate system reset after 2.684 seconds */ #endif +#if defined(CFG_4xx_RESET_TYPE) + val &= ~0x30000000; /* clear WRC bits */ + val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */ +#endif mtspr(tcr, val); val = mfspr(tsr); diff --git a/include/configs/alpr.h b/include/configs/alpr.h index c6731ba..60da820 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -31,25 +31,25 @@ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_BOARD_RESET 1 /* call board_reset() */ +#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33333000 /* external freq to pll */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 #define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) @@ -84,26 +84,13 @@ /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ - +#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ @@ -154,7 +141,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ + "netdev=eth3\0" \ "hostname=alpr\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ @@ -162,18 +149,19 @@ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \ + "mem=193M\0" \ "flash_nfs=run nfsargs addip addtty;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/alpr/uImage\0" \ + "rootpath=/opt/projects/alpr/nfs_root\0" \ + "bootfile=/alpr/uImage\0" \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ - "load=tftp 100000 /tftpboot/alpr/u-boot.bin\0" \ + "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ @@ -181,7 +169,7 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ #define CONFIG_BAUDRATE 115200 @@ -192,8 +180,8 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ #define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ -#define CONFIG_PHY2_ADDR 0x00 /* test-only: will be changed */ -#define CONFIG_PHY3_ADDR 0x01 /* PHY address for EMAC3 */ +#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */ +#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */ #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 @@ -251,9 +239,11 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ /*----------------------------------------------------------------------- * PCI stuff @@ -264,7 +254,7 @@ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ +#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ /* Board-specific PCI */ #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ @@ -276,11 +266,10 @@ /*----------------------------------------------------------------------- * FPGA stuff - *----------------------------------------------------------------------- - */ + *-----------------------------------------------------------------------*/ #define CONFIG_FPGA CFG_ALTERA_CYCLON2 -#undef CFG_FPGA_CHECK_CTRLC -#undef CFG_FPGA_PROG_FEEDBACK +#define CFG_FPGA_CHECK_CTRLC +#define CFG_FPGA_PROG_FEEDBACK #define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in Reihe geschaltet -> sollte gehen, aufpassen mit Datasize ist jetzt @@ -299,9 +288,16 @@ #define CFG_GPIO_SEL_AVR 15 /* cpu output */ #define CFG_GPIO_PROG_EN 23 /* cpu output */ -/* +/*----------------------------------------------------------------------- + * Definitions for GPIO setup + *-----------------------------------------------------------------------*/ +#define CFG_GPIO_EREADY (0x80000000 >> 26) +#define CFG_GPIO_REV0 (0x80000000 >> 14) +#define CFG_GPIO_REV1 (0x80000000 >> 15) + +/*----------------------------------------------------------------------- * NAND-FLASH stuff - */ + *-----------------------------------------------------------------------*/ #define CFG_MAX_NAND_DEVICE 4 #define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE #define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ @@ -320,7 +316,7 @@ /* Memory Bank 1 (NAND-FLASH) initialization */ #define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */ -#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ +#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ /* * For booting Linux, the board info and command line data @@ -333,9 +329,7 @@ */ #define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions -- cgit v0.10.2 From ec0c2ec725aec9524a177a77ce75559e644a931a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 27 Nov 2006 14:46:06 +0100 Subject: [PATCH] Remove testing 4xx enet PHY setup Signed-off-by: Stefan Roese diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 8c517ba..7a2483c 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -560,22 +560,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) * otherwise, just check the speeds & feeds */ if (hw_p->first_init == 0) { -#if defined(CONFIG_88E1111_CLK_DELAY) - /* - * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs - * the "RGMII transmit timing control" and "RGMII receive - * timing control" bits set, so that Gbit communication works - * without problems. - * Also set the "Transmitter disable" to 1 to enable the - * transmitter. - * After setting these bits a soft-reset must occur for this - * change to become active. - */ - miiphy_read (dev->name, reg, 0x14, ®_short); - reg_short |= (1 << 7) | (1 << 1) | (1 << 0); - miiphy_write (dev->name, reg, 0x14, reg_short); -#endif -#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */ +#if defined(CONFIG_M88E1111_PHY) miiphy_write (dev->name, reg, 0x14, 0x0ce3); miiphy_write (dev->name, reg, 0x18, 0x4101); miiphy_write (dev->name, reg, 0x09, 0x0e00); diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 60da820..bbe6b76 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -187,7 +187,7 @@ #define CONFIG_HAS_ETH2 #define CONFIG_HAS_ETH3 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_88E1111_CLK_DELAY 1 /* set CLK delay on ALPR */ +#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ -- cgit v0.10.2 From 1f94d162e2b5f0edc28d9fb11482502c44d218e1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 27 Nov 2006 14:48:41 +0100 Subject: [PATCH] 4xx: Fix problem with board specific reset code Signed-off-by: Stefan Roese diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index c45525d..87299c1 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -426,6 +426,9 @@ int ppc440spe_revB() { int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { +#if defined(CONFIG_BOARD_RESET) + board_reset(); +#else /* defined(CONFIG_BOARD_RESET) */ #if defined(CFG_4xx_RESET_TYPE) mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); #else -- cgit v0.10.2 From cc5ee8a92a0e3ca6f727af71b8fd206460c7afd7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 27 Nov 2006 14:49:51 +0100 Subject: [PATCH] alpr: remove unused board specific flash driver Signed-off-by: Stefan Roese diff --git a/board/prodrive/alpr/flash.c b/board/prodrive/alpr/flash.c deleted file mode 100644 index 8fa0084..0000000 --- a/board/prodrive/alpr/flash.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/* - * Prototypes - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i Date: Mon, 27 Nov 2006 14:52:04 +0100 Subject: [PATCH] 4xx: Fix problem with board specific reset code (now for real) Signed-off-by: Stefan Roese diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 87299c1..447383f 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -428,7 +428,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { #if defined(CONFIG_BOARD_RESET) board_reset(); -#else /* defined(CONFIG_BOARD_RESET) */ +#else #if defined(CFG_4xx_RESET_TYPE) mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); #else @@ -436,6 +436,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Initiate system reset in debug control register DBCR */ mtspr(dbcr0, 0x30000000); +#endif /* defined(CFG_4xx_RESET_TYPE) */ #endif /* defined(CONFIG_BOARD_RESET) */ return 1; -- cgit v0.10.2