From 035d563937b5bafbf78b17e07ac50bca47492385 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Wed, 20 Mar 2013 05:38:11 +0000 Subject: am33xx: add pll and clock support for TI814x CPSW Enables required PLLs and clocks for CPSW on TI814x. Signed-off-by: Matt Porter Reviewed-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index cb4210f..8b2878d 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -109,6 +109,8 @@ struct ad_pll { #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) /* PRCM */ +#define ENET_CLKCTRL_CMPL 0x30000 + #define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) struct cm_def { @@ -183,7 +185,7 @@ struct cm_alwon { unsigned int resv5[2]; unsigned int gpmcclkctrl; unsigned int ethernet0clkctrl; - unsigned int resv6[1]; + unsigned int ethernet1clkctrl; unsigned int mpuclkctrl; unsigned int debugssclkctrl; unsigned int l3clkctrl; @@ -203,9 +205,67 @@ struct cm_alwon { unsigned int custefuseclkctrl; }; +#define SATA_PLL_BASE (CTRL_BASE + 0x0720) + +struct sata_pll { + unsigned int pllcfg0; + unsigned int pllcfg1; + unsigned int pllcfg2; + unsigned int pllcfg3; + unsigned int pllcfg4; + unsigned int pllstatus; + unsigned int rxstatus; + unsigned int txstatus; + unsigned int testcfg; +}; + +#define SEL_IN_FREQ (0x1 << 31) +#define DIGCLRZ (0x1 << 30) +#define ENDIGLDO (0x1 << 4) +#define APLL_CP_CURR (0x1 << 3) +#define ENBGSC_REF (0x1 << 2) +#define ENPLLLDO (0x1 << 1) +#define ENPLL (0x1 << 0) + +#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF) +#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF) +#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO) +#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \ + ENPLLLDO | ENPLL) + +#define PLL_LOCK (0x1 << 0) + +#define ENSATAMODE (0x1 << 31) +#define PLLREFSEL (0x1 << 30) +#define MDIVINT (0x4b << 18) +#define EN_CLKAUX (0x1 << 5) +#define EN_CLK125M (0x1 << 4) +#define EN_CLK100M (0x1 << 3) +#define EN_CLK50M (0x1 << 2) + +#define SATA_PLLCFG1 (ENSATAMODE | \ + PLLREFSEL | \ + MDIVINT | \ + EN_CLKAUX | \ + EN_CLK125M | \ + EN_CLK100M | \ + EN_CLK50M) + +#define DIGLDO_EN_CAPLESSMODE (0x1 << 22) +#define PLLDO_EN_LDO_STABLE (0x1 << 11) +#define PLLDO_EN_BUF_CUR (0x1 << 7) +#define PLLDO_EN_LP (0x1 << 6) +#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1) + +#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \ + PLLDO_EN_LDO_STABLE | \ + PLLDO_EN_BUF_CUR | \ + PLLDO_EN_LP | \ + PLLDO_CTRL_TRIM_1_4V) const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; +const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE; /* * Enable the peripheral clock for required peripherals @@ -221,6 +281,15 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) ; + + /* Ethernet */ + writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); + while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0) + ; + writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); + while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0) + ; } /* @@ -365,6 +434,35 @@ void ddr_pll_config(unsigned int ddrpll_m) pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); } +void sata_pll_config(void) +{ + /* + * This sequence for configuring the SATA PLL + * resident in the control module is documented + * in TI8148 TRM section 21.3.1 + */ + writel(SATA_PLLCFG1, &spll->pllcfg1); + udelay(50); + + writel(SATA_PLLCFG3, &spll->pllcfg3); + udelay(50); + + writel(SATA_PLLCFG0_1, &spll->pllcfg0); + udelay(50); + + writel(SATA_PLLCFG0_2, &spll->pllcfg0); + udelay(50); + + writel(SATA_PLLCFG0_3, &spll->pllcfg0); + udelay(50); + + writel(SATA_PLLCFG0_4, &spll->pllcfg0); + udelay(50); + + while (((readl(&spll->pllstatus) & PLL_LOCK) == 0)) + ; +} + void enable_emif_clocks(void) {}; void enable_dmm_clocks(void) @@ -397,9 +495,10 @@ void pll_init() /* Enable the control module */ writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); + /* Configure PLLs */ mpu_pll_config(); - l3_pll_config(); + sata_pll_config(); /* Enable the required peripherals */ enable_per_clocks(); diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index a950ac3..8f9315c 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -29,6 +29,7 @@ /* Control Module Base Address */ #define CTRL_BASE 0x48140000 +#define CTRL_DEVICE_BASE 0x48140600 /* PRCM Base Address */ #define PRCM_BASE 0x48180000 diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 446e36b..2089a14 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -151,6 +151,9 @@ void s_init(void) */ wdt_disable(); + /* Enable timer */ + timer_init(); + /* Setup the PLLs and the clocks for the peripherals */ pll_init(); -- cgit v0.10.2 From f6f86a64ac00980ba6066417bb54f39e39d29703 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Wed, 20 Mar 2013 05:38:12 +0000 Subject: cpsw: add support for TI814x slave_regs differences TI814x's version 1 CPSW has a different slave_regs layout. Add support for the differing registers. Signed-off-by: Matt Porter Reviewed-by: Tom Rini diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 7a36850..379b679 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -109,7 +109,13 @@ struct cpsw_slave_regs { u32 flow_thresh; u32 port_vlan; u32 tx_pri_map; +#ifdef CONFIG_AM33XX u32 gap_thresh; +#elif defined(CONFIG_TI814X) + u32 ts_ctl; + u32 ts_seq_ltype; + u32 ts_vlan; +#endif u32 sa_lo; u32 sa_hi; }; -- cgit v0.10.2 From f485c8a35b38356a473208bec5ed786792c1eafe Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Wed, 20 Mar 2013 05:38:13 +0000 Subject: phy: add support for ET1011C phys Adds an ET1011C PHY driver which is derived from the Linux kernel PHY driver (drivers/net/phy/et1011c.c) from the v3.9-rc2 tag. Note that an errata workaround config option is implemented to allow for TX_CLK to be enabled even when gigabit mode is negotiated. This workaround is used on the PG1.0 TI814X EVM. Signed-off-by: Matt Porter Reviewed-by: Tom Rini diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 5e90d70..af5f4b8 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_PHYLIB_10G) += generic_10g.o COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o +COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o COBJS-$(CONFIG_PHY_LXT) += lxt.o COBJS-$(CONFIG_PHY_MARVELL) += marvell.o COBJS-$(CONFIG_PHY_MICREL) += micrel.o diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c new file mode 100644 index 0000000..5e22399 --- /dev/null +++ b/drivers/net/phy/et1011c.c @@ -0,0 +1,110 @@ +/* + * ET1011C PHY driver + * + * Derived from Linux kernel driver by Chaithrika U S + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include + +#define ET1011C_CONFIG_REG (0x16) +#define ET1011C_TX_FIFO_MASK (0x3 << 12) +#define ET1011C_TX_FIFO_DEPTH_8 (0x0 << 12) +#define ET1011C_TX_FIFO_DEPTH_16 (0x1 << 12) +#define ET1011C_INTERFACE_MASK (0x7 << 0) +#define ET1011C_GMII_INTERFACE (0x2 << 0) +#define ET1011C_SYS_CLK_EN (0x1 << 4) +#define ET1011C_TX_CLK_EN (0x1 << 5) + +#define ET1011C_STATUS_REG (0x1A) +#define ET1011C_DUPLEX_STATUS (0x1 << 7) +#define ET1011C_SPEED_MASK (0x3 << 8) +#define ET1011C_SPEED_1000 (0x2 << 8) +#define ET1011C_SPEED_100 (0x1 << 8) +#define ET1011C_SPEED_10 (0x0 << 8) + +static int et1011c_config(struct phy_device *phydev) +{ + int ctl = 0; + ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + if (ctl < 0) + return ctl; + ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | + BMCR_ANENABLE); + /* First clear the PHY */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); + + return genphy_config_aneg(phydev); +} + +static int et1011c_parse_status(struct phy_device *phydev) +{ + int mii_reg; + int speed; + + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); + + if (mii_reg & ET1011C_DUPLEX_STATUS) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + speed = mii_reg & ET1011C_SPEED_MASK; + switch (speed) { + case ET1011C_SPEED_1000: + phydev->speed = SPEED_1000; + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); + mii_reg &= ~ET1011C_TX_FIFO_MASK; + phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG, + mii_reg | + ET1011C_GMII_INTERFACE | + ET1011C_SYS_CLK_EN | +#ifdef CONFIG_PHY_ET1011C_TX_CLK_FIX + ET1011C_TX_CLK_EN | +#endif + ET1011C_TX_FIFO_DEPTH_16); + break; + case ET1011C_SPEED_100: + phydev->speed = SPEED_100; + break; + case ET1011C_SPEED_10: + phydev->speed = SPEED_10; + break; + } + + return 0; +} + +static int et1011c_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + et1011c_parse_status(phydev); + return 0; +} + +static struct phy_driver et1011c_driver = { + .name = "ET1011C", + .uid = 0x0282f014, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .config = &et1011c_config, + .startup = &et1011c_startup, +}; + +int phy_et1011c_init(void) +{ + phy_register(&et1011c_driver); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index d0ed766..f8c5481 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -430,6 +430,9 @@ int phy_init(void) #ifdef CONFIG_PHY_DAVICOM phy_davicom_init(); #endif +#ifdef CONFIG_PHY_ET1011C + phy_et1011c_init(); +#endif #ifdef CONFIG_PHY_LXT phy_lxt_init(); #endif diff --git a/include/phy.h b/include/phy.h index 58ca273..7b4ce74 100644 --- a/include/phy.h +++ b/include/phy.h @@ -223,6 +223,7 @@ int gen10g_discover_mmds(struct phy_device *phydev); int phy_atheros_init(void); int phy_broadcom_init(void); int phy_davicom_init(void); +int phy_et1011c_init(void); int phy_lxt_init(void); int phy_marvell_init(void); int phy_micrel_init(void); -- cgit v0.10.2 From cd87464d0873d2db920e6b712ef34e9c83cfe5e6 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Wed, 20 Mar 2013 05:38:14 +0000 Subject: ti814x_evm: enable CPSW support Adds CPSW support to the TI814X EVM configured with an ET1011C PHY in GMII mode. Signed-off-by: Matt Porter Reviewed-by: Tom Rini diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 2089a14..7adb524 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -17,6 +17,7 @@ */ #include +#include #include #include #include @@ -39,6 +40,8 @@ static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; #endif +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + /* UART Defines */ #ifdef CONFIG_SPL_BUILD #define UART_RESET (0x1 << 1) @@ -166,6 +169,9 @@ void s_init(void) /* Set MMC pins */ enable_mmc1_pin_mux(); + /* Set Ethernet pins */ + enable_enet_pin_mux(); + /* Enable UART */ uart_enable(); @@ -199,3 +205,69 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +#ifdef CONFIG_DRIVER_TI_CPSW +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x50, + .sliver_reg_ofs = 0x700, + .phy_id = 1, + }, + { + .slave_reg_ofs = 0x90, + .sliver_reg_ofs = 0x740, + .phy_id = 0, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x100, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0x600, + .ale_entries = 1024, + .host_port_reg_ofs = 0x28, + .hw_stats_reg_ofs = 0x400, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_1, +}; +#endif + +int board_eth_init(bd_t *bis) +{ + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + printf(" not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + printf("Unable to read MAC address. Set \n"); + } + + return cpsw_register(&cpsw_data); +} diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h index 40f8710..6aebec6 100644 --- a/board/ti/ti814x/evm.h +++ b/board/ti/ti814x/evm.h @@ -3,5 +3,6 @@ void enable_uart0_pin_mux(void); void enable_mmc1_pin_mux(void); +void enable_enet_pin_mux(void); #endif /* _EVM_H */ diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c index 137acb4..fd9f364 100644 --- a/board/ti/ti814x/mux.c +++ b/board/ti/ti814x/mux.c @@ -40,6 +40,36 @@ static struct module_pin_mux mmc1_pin_mux[] = { {-1}, }; +static struct module_pin_mux enet_pin_mux[] = { + {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */ + {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */ + {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */ + {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */ + {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */ + {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */ + {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */ + {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */ + {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */ + {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */ + {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */ + {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */ + {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */ + {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */ + {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */ + {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */ + {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */ + {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */ + {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */ + {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */ + {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */ + {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */ + {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */ + {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */ + {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */ + {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */ + {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */ +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -49,3 +79,8 @@ void enable_mmc1_pin_mux(void) { configure_module_pin_mux(mmc1_pin_mux); } + +void enable_enet_pin_mux(void) +{ + configure_module_pin_mux(enet_pin_mux); +} diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 16547e3..e646bd7 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -218,4 +218,25 @@ /* Unsupported features */ #undef CONFIG_USE_IRQ +/* Ethernet */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_ET1011C +#define CONFIG_PHY_ET1011C_TX_CLK_FIX + #endif /* ! __CONFIG_TI814X_EVM_H */ -- cgit v0.10.2 From 0208aaf6c2e0f346e8410c0e5adb0ea784f00829 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 26 Mar 2013 05:20:49 +0000 Subject: twl4030: make twl4030_i2c_write_u8 prototype consistent u-boot standard i2c register write prototype is i2c_reg_write(u8 addr, u8 reg, u8 val) twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg) does not provide consistency, so switch the prototype to be consistent with rest of u-boot i2c operations: twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val) Signed-off-by: Nishanth Menon diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 84c36ba..87d7354 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -493,17 +493,17 @@ static void setup_net_chip_gmpc(void) static void reset_net_chip(void) { /* Set GPIO1 of TPS65930 as output */ - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, - TWL4030_BASEADD_GPIO + 0x03); + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, + 0x02); /* Send a pulse on the GPIO pin */ - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, - TWL4030_BASEADD_GPIO + 0x0C); + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, + 0x02); udelay(1); - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, - TWL4030_BASEADD_GPIO + 0x09); + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, + 0x02); mdelay(40); - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, - TWL4030_BASEADD_GPIO + 0x0C); + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, + 0x02); mdelay(1); } #else @@ -600,10 +600,10 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset); /* Set GPIO6 and GPIO7 of TPS65930 as output */ val |= 0xC0; - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset); + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; /* Take both PHYs out of reset */ - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset); + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); udelay(1); return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 48eb65f..860d52d 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -332,10 +332,10 @@ void *video_hw_init(void) static void twl4030_regulator_set_mode(u8 id, u8 mode) { u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode); - twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg >> 8, - TWL4030_PM_MASTER_PB_WORD_MSB); - twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg & 0xff, - TWL4030_PM_MASTER_PB_WORD_LSB); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PB_WORD_MSB, msg >> 8); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PB_WORD_LSB, msg & 0xff); } static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) @@ -410,8 +410,8 @@ int misc_init_r(void) TWL4030_PM_MASTER_PB_CFG); /* enable I2C access to powerbus (needed for twl4030 regulator) */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x02, - TWL4030_PM_MASTER_PB_CFG); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG, + 0x02); /* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */ twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE); @@ -419,8 +419,8 @@ int misc_init_r(void) twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE); /* restore I2C access state */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, state, - TWL4030_PM_MASTER_PB_CFG); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG, + state); /* set env variable attkernaddr for relocated kernel */ sprintf(buf, "%#x", KERNEL_ADDRESS); @@ -481,8 +481,8 @@ void hw_watchdog_reset(void) /* timeout 0 means watchdog is disabled */ /* reset watchdog timeout to 31s (maximum) */ if (timeout != 0) - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 31, - TWL4030_PM_RECEIVER_WATCHDOG_CFG); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_WATCHDOG_CFG, 31); /* store last watchdog reset time */ twl_wd_time = get_timer(0); @@ -541,18 +541,18 @@ int rx51_kp_init(void) ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON; ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST; ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN; - ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl, - TWL4030_KEYPAD_KEYP_CTRL_REG); + ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, + TWL4030_KEYPAD_KEYP_CTRL_REG, ctrl); /* enable key event status */ - ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0xfe, - TWL4030_KEYPAD_KEYP_IMR1); + ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, + TWL4030_KEYPAD_KEYP_IMR1, 0xfe); /* enable interrupt generation on rising and falling */ /* this is a workaround for qemu twl4030 emulation */ - ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x57, - TWL4030_KEYPAD_KEYP_EDR); + ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, + TWL4030_KEYPAD_KEYP_EDR, 0x57); /* enable ISR clear on read */ - ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x05, - TWL4030_KEYPAD_KEYP_SIH_CTRL); + ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, + TWL4030_KEYPAD_KEYP_SIH_CTRL, 0x05); return 0; } diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 9ff5dd7..5f0c58d 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -114,8 +114,9 @@ int misc_init_r(void) /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_BB_CFG, TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV | - TWL4030_BB_CFG_BBISEL_500UA, TWL4030_PM_RECEIVER_BB_CFG); + TWL4030_BB_CFG_BBISEL_500UA); dieid_num_r(); diff --git a/drivers/misc/twl4030_led.c b/drivers/misc/twl4030_led.c index 33cea11..e150d8f 100644 --- a/drivers/misc/twl4030_led.c +++ b/drivers/misc/twl4030_led.c @@ -42,7 +42,7 @@ void twl4030_led_init(unsigned char ledon_mask) if (ledon_mask & TWL4030_LED_LEDEN_LEDBON) ledon_mask |= TWL4030_LED_LEDEN_LEDBPWM; - twl4030_i2c_write_u8(TWL4030_CHIP_LED, ledon_mask, - TWL4030_LED_LEDEN); + twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN, + ledon_mask); } diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index e7d5f13..2bf94b1 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -51,8 +51,8 @@ void twl4030_power_reset_init(void) printf("Could not initialize hardware reset\n"); } else { val |= TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON; - if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, val, - TWL4030_PM_MASTER_P1_SW_EVENTS)) { + if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_P1_SW_EVENTS, val)) { printf("Error:TWL4030: failed to write the power register\n"); printf("Could not initialize hardware reset\n"); } @@ -68,8 +68,8 @@ void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, int ret; /* Select the Voltage */ - ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val, - vsel_reg); + ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_reg, + vsel_val); if (ret != 0) { printf("Could not write vsel to reg %02x (%d)\n", vsel_reg, ret); @@ -77,8 +77,8 @@ void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, } /* Select the Device Group (enable the supply if dev_grp_sel != 0) */ - ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel, - dev_grp); + ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp, + dev_grp_sel); if (ret != 0) printf("Could not write grp_sel to reg %02x (%d)\n", dev_grp, ret); diff --git a/drivers/usb/phy/twl4030.c b/drivers/usb/phy/twl4030.c index 54d2e61..f41cc07 100644 --- a/drivers/usb/phy/twl4030.c +++ b/drivers/usb/phy/twl4030.c @@ -54,7 +54,7 @@ static int twl4030_usb_write(u8 address, u8 data) { int ret; - ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, data, address); + ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, address, data); if (ret != 0) printf("TWL4030:USB:Write[0x%x] Error %d\n", address, ret); @@ -78,40 +78,40 @@ static int twl4030_usb_read(u8 address) static void twl4030_usb_ldo_init(void) { /* Enable writing to power configuration registers */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0xC0, - TWL4030_PM_MASTER_PROTECT_KEY); - twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x0C, - TWL4030_PM_MASTER_PROTECT_KEY); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PROTECT_KEY, 0xC0); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PROTECT_KEY, 0x0C); /* put VUSB3V1 LDO in active state */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, - TWL4030_PM_RECEIVER_VUSB_DEDICATED2); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_VUSB_DEDICATED2, 0x00); /* input to VUSB3V1 LDO is from VBAT, not VBUS */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x14, - TWL4030_PM_RECEIVER_VUSB_DEDICATED1); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_VUSB_DEDICATED1, 0x14); /* turn on 3.1V regulator */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, - TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP); - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, - TWL4030_PM_RECEIVER_VUSB3V1_TYPE); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP, 0x20); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_VUSB3V1_TYPE, 0x00); /* turn on 1.5V regulator */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, - TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP); - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, - TWL4030_PM_RECEIVER_VUSB1V5_TYPE); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP, 0x20); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_VUSB1V5_TYPE, 0x00); /* turn on 1.8V regulator */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, - TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP); - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, - TWL4030_PM_RECEIVER_VUSB1V8_TYPE); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP, 0x20); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_VUSB1V8_TYPE, 0x00); /* disable access to power configuration registers */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x00, - TWL4030_PM_MASTER_PROTECT_KEY); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PROTECT_KEY, 0x00); } static void twl4030_phy_power(void) diff --git a/include/twl4030.h b/include/twl4030.h index 5aa1841..aca695d 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -638,7 +638,7 @@ * examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and * TWL4030_LED_LEDEN. */ -static inline int twl4030_i2c_write_u8(u8 chip_no, u8 val, u8 reg) +static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) { return i2c_write(chip_no, reg, 1, &val, 1); } -- cgit v0.10.2 From b29c2f0c142fdb8ef50deae1cc7c4338952fba6c Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 26 Mar 2013 05:20:50 +0000 Subject: twl4030: make twl4030_i2c_read_u8 prototype consistent u-boot standard i2c read prototype is i2c_read(addr, reg, 1, &buf, 1) twl4030_i2c_read_u8(u8 addr, u8 *val, u8 reg) does not provide consistency, so switch the prototype to be consistent with rest of u-boot i2c operations: twl4030_i2c_read_u8(u8 addr, u8 reg, u8 *val) Signed-off-by: Nishanth Menon diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 87d7354..8528680 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -448,7 +448,7 @@ int board_mmc_getcd(struct mmc *mmc) { u8 val; - if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, TWL4030_BASEADD_GPIO)) + if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) return -1; return !(val & 1); @@ -597,7 +597,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) udelay(1000); offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; - twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset); + twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); /* Set GPIO6 and GPIO7 of TPS65930 as output */ val |= 0xC0; twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 860d52d..42bf8b6 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -406,8 +406,8 @@ int misc_init_r(void) TWL4030_PM_RECEIVER_DEV_GRP_P1); /* store I2C access state */ - twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &state, - TWL4030_PM_MASTER_PB_CFG); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG, + &state); /* enable I2C access to powerbus (needed for twl4030 regulator) */ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG, @@ -475,8 +475,8 @@ void hw_watchdog_reset(void) return; /* read actual watchdog timeout */ - twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &timeout, - TWL4030_PM_RECEIVER_WATCHDOG_CFG); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_PM_RECEIVER_WATCHDOG_CFG, &timeout); /* timeout 0 means watchdog is disabled */ /* reset watchdog timeout to 31s (maximum) */ @@ -531,8 +531,8 @@ int rx51_kp_init(void) { int ret = 0; u8 ctrl; - ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl, - TWL4030_KEYPAD_KEYP_CTRL_REG); + ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, + TWL4030_KEYPAD_KEYP_CTRL_REG, &ctrl); if (ret) return ret; @@ -615,8 +615,8 @@ int rx51_kp_tstc(void) for (i = 0; i < 2; i++) { /* check interrupt register for events */ - twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &intr, - TWL4030_KEYPAD_KEYP_ISR1+(2*i)); + twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, + TWL4030_KEYPAD_KEYP_ISR1 + (2 * i), &intr); /* no event */ if (!(intr&1)) diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index 2bf94b1..6610f78 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -45,8 +45,8 @@ void twl4030_power_reset_init(void) { u8 val = 0; - if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val, - TWL4030_PM_MASTER_P1_SW_EVENTS)) { + if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_P1_SW_EVENTS, &val)) { printf("Error:TWL4030: failed to read the power register\n"); printf("Could not initialize hardware reset\n"); } else { diff --git a/drivers/usb/phy/twl4030.c b/drivers/usb/phy/twl4030.c index f41cc07..74f1dcc 100644 --- a/drivers/usb/phy/twl4030.c +++ b/drivers/usb/phy/twl4030.c @@ -66,7 +66,7 @@ static int twl4030_usb_read(u8 address) u8 data; int ret; - ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &data, address); + ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, address, &data); if (ret == 0) ret = data; else diff --git a/include/twl4030.h b/include/twl4030.h index aca695d..569ad27 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -643,7 +643,7 @@ static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) return i2c_write(chip_no, reg, 1, &val, 1); } -static inline int twl4030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg) +static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) { return i2c_read(chip_no, reg, 1, val, 1); } -- cgit v0.10.2 From 345ef20465f7b2628b6f6e93b4f2e1d7280f7b7d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 26 Mar 2013 05:20:51 +0000 Subject: twl6030: twl6030_i2c_[read|write]_u8 prototype consistent u-boot standard i2c register access prototype is i2c_read(addr, reg, 1, &buf, 1) i2c_reg_write(u8 addr, u8 reg, u8 val) twl6030_i2c_read_u8(u8 addr, u8 *val, u8 reg) twl6030_i2c_write_u8(u8 addr, u8 val, u8 reg) does not provide consistency, so switch the prototype to be consistent with rest of u-boot i2c operations: twl6030_i2c_read_u8(u8 addr, u8 reg, u8 *val) twl6030_i2c_write_u8(u8 addr, u8 reg, u8 val) Signed-off-by: Nishanth Menon diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c index c5a0038..58ad4ad 100644 --- a/drivers/power/twl6030.c +++ b/drivers/power/twl6030.c @@ -26,12 +26,12 @@ #include /* Functions to read and write from TWL6030 */ -static inline int twl6030_i2c_write_u8(u8 chip_no, u8 val, u8 reg) +static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) { return i2c_write(chip_no, reg, 1, &val, 1); } -static inline int twl6030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg) +static inline int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) { return i2c_read(chip_no, reg, 1, val, 1); } @@ -42,13 +42,13 @@ static int twl6030_gpadc_read_channel(u8 channel_no) u8 msb = 0; int ret = 0; - ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &lsb, - GPCH0_LSB + channel_no * 2); + ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, + GPCH0_LSB + channel_no * 2, &lsb); if (ret) return ret; - ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &msb, - GPCH0_MSB + channel_no * 2); + ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, + GPCH0_MSB + channel_no * 2, &msb); if (ret) return ret; @@ -60,7 +60,7 @@ static int twl6030_gpadc_sw2_trigger(void) u8 val; int ret = 0; - ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2_SP2, CTRL_P2); + ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2, CTRL_P2_SP2); if (ret) return ret; @@ -68,7 +68,7 @@ static int twl6030_gpadc_sw2_trigger(void) val = CTRL_P2_BUSY; while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) { - ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &val, CTRL_P2); + ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, CTRL_P2, &val); if (ret) return ret; udelay(1000); @@ -79,29 +79,29 @@ static int twl6030_gpadc_sw2_trigger(void) void twl6030_stop_usb_charging(void) { - twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, 0, CONTROLLER_CTRL1); + twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1, 0); return; } void twl6030_start_usb_charging(void) { - twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VICHRG_1500, - CHARGERUSB_VICHRG); - twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CIN_LIMIT_NONE, - CHARGERUSB_CINLIMIT); - twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MBAT_TEMP, - CONTROLLER_INT_MASK); - twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MASK_MCHARGERUSB_THMREG, - CHARGERUSB_INT_MASK); - twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VOREG_4P0, - CHARGERUSB_VOREG); - twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL2_VITERM_400, - CHARGERUSB_CTRL2); - twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TERM, CHARGERUSB_CTRL1); + twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, + CHARGERUSB_VICHRG, CHARGERUSB_VICHRG_1500); + twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, + CHARGERUSB_CINLIMIT, CHARGERUSB_CIN_LIMIT_NONE); + twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, + CONTROLLER_INT_MASK, MBAT_TEMP); + twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, + CHARGERUSB_INT_MASK, MASK_MCHARGERUSB_THMREG); + twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, + CHARGERUSB_VOREG, CHARGERUSB_VOREG_4P0); + twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, + CHARGERUSB_CTRL2, CHARGERUSB_CTRL2_VITERM_400); + twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL1, TERM); /* Enable USB charging */ - twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1_EN_CHARGER, - CONTROLLER_CTRL1); + twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, + CONTROLLER_CTRL1, CONTROLLER_CTRL1_EN_CHARGER); return; } @@ -111,8 +111,8 @@ int twl6030_get_battery_current(void) u8 msb = 0; u8 lsb = 0; - twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &msb, FG_REG_11); - twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &lsb, FG_REG_10); + twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, FG_REG_11, &msb); + twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, FG_REG_10, &lsb); battery_current = ((msb << 8) | lsb); /* convert 10 bit signed number to 16 bit signed number */ @@ -156,10 +156,10 @@ void twl6030_init_battery_charging(void) int ret = 0; /* Enable VBAT measurement */ - twl6030_i2c_write_u8(TWL6030_CHIP_PM, VBAT_MEAS, MISC1); + twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS); /* Enable GPADC module */ - ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, FGS | GPADCS, TOGGLE1); + ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TOGGLE1, FGS | GPADCS); if (ret) { printf("Failed to enable GPADC\n"); return; @@ -173,7 +173,7 @@ void twl6030_init_battery_charging(void) printf("Main battery voltage too low!\n"); /* Check for the presence of USB charger */ - twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &stat1, CONTROLLER_STAT1); + twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &stat1); /* check for battery presence indirectly via Fuel gauge */ if ((stat1 & VBUS_DET) && (battery_volt < 3300)) @@ -185,8 +185,8 @@ void twl6030_init_battery_charging(void) void twl6030_power_mmc_init() { /* set voltage to 3.0 and turnon for APP */ - twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x15, VMMC_CFG_VOLTATE); - twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VMMC_CFG_STATE); + twl6030_i2c_write_u8(TWL6030_CHIP_PM, VMMC_CFG_VOLTATE, 0x15); + twl6030_i2c_write_u8(TWL6030_CHIP_PM, VMMC_CFG_STATE, 0x21); } void twl6030_usb_device_settings() @@ -194,12 +194,12 @@ void twl6030_usb_device_settings() u8 data = 0; /* Select APP Group and set state to ON */ - twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VUSB_CFG_STATE); + twl6030_i2c_write_u8(TWL6030_CHIP_PM, VUSB_CFG_STATE, 0x21); - twl6030_i2c_read_u8(TWL6030_CHIP_PM, &data, MISC2); + twl6030_i2c_read_u8(TWL6030_CHIP_PM, MISC2, &data); data |= 0x10; /* Select the input supply for VBUS regulator */ - twl6030_i2c_write_u8(TWL6030_CHIP_PM, data, MISC2); + twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC2, data); } #endif -- cgit v0.10.2 From ebce10e5b2542e71e1201c85dbe3b6432569a497 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 26 Mar 2013 05:20:52 +0000 Subject: twl6030: move twl6030 register access functions to common header file twl6030_i2c_[read|write]_u8 can be used else where to access multi-function device such as twl6030, so move the register access functions to the common twl6030.h header file. Signed-off-by: Nishanth Menon diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c index 58ad4ad..d421e60 100644 --- a/drivers/power/twl6030.c +++ b/drivers/power/twl6030.c @@ -25,17 +25,6 @@ #include -/* Functions to read and write from TWL6030 */ -static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) -{ - return i2c_write(chip_no, reg, 1, &val, 1); -} - -static inline int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) -{ - return i2c_read(chip_no, reg, 1, val, 1); -} - static int twl6030_gpadc_read_channel(u8 channel_no) { u8 lsb = 0; diff --git a/include/twl6030.h b/include/twl6030.h index a9fcadb..f7ba3c7 100644 --- a/include/twl6030.h +++ b/include/twl6030.h @@ -126,6 +126,17 @@ #define GPCH0_LSB 0x57 #define GPCH0_MSB 0x58 +/* Functions to read and write from TWL6030 */ +static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) +{ + return i2c_write(chip_no, reg, 1, &val, 1); +} + +static inline int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) +{ + return i2c_read(chip_no, reg, 1, val, 1); +} + void twl6030_init_battery_charging(void); void twl6030_usb_device_settings(void); void twl6030_start_usb_charging(void); -- cgit v0.10.2 From 502dac5568df4c67d7bb53b4aca242f2435eed73 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 26 Mar 2013 05:20:53 +0000 Subject: twl6030: add header guard Add an header guard to common header file to prevent multiple includes messing things up. Signed-off-by: Nishanth Menon diff --git a/include/twl6030.h b/include/twl6030.h index f7ba3c7..029b21f 100644 --- a/include/twl6030.h +++ b/include/twl6030.h @@ -21,6 +21,9 @@ * MA 02111-1307 USA */ +#ifndef TWL6030_H +#define TWL6030_H + #include #include @@ -144,3 +147,5 @@ void twl6030_stop_usb_charging(void); int twl6030_get_battery_voltage(void); int twl6030_get_battery_current(void); void twl6030_power_mmc_init(void); + +#endif /* TWL6030_H */ -- cgit v0.10.2 From cb199102b06c5d895d2495c62554c5be998b234b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 26 Mar 2013 05:20:54 +0000 Subject: twl6035: rename to palmas TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs Rename twl6035 to palmas to allow reuse across multiple current and future platforms As part of this change, change the CONFIG_TWL6035_POWER to CONFIG_PALMAS_POWER and update usage of header file accordingly. Signed-off-by: Nishanth Menon diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 7bbb549..bf7e091 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -27,7 +27,7 @@ * MA 02111-1307 USA */ #include -#include +#include #include #include diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 55337c0..701842b 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -23,7 +23,7 @@ * MA 02111-1307 USA */ #include -#include +#include #include #include @@ -63,7 +63,7 @@ int board_eth_init(bd_t *bis) */ int misc_init_r(void) { -#ifdef CONFIG_TWL6035_POWER +#ifdef CONFIG_PALMAS_POWER twl6035_init_settings(); #endif return 0; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 166744c..b39db9e 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -107,7 +107,7 @@ static void omap4_vmmc_pbias_config(struct mmc *mmc) } #endif -#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER) +#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) static void omap5_pbias_config(struct mmc *mmc) { u32 value = 0; @@ -178,7 +178,7 @@ unsigned char mmc_board_init(struct mmc *mmc) if (mmc->block_dev.dev == 0) omap4_vmmc_pbias_config(mmc); #endif -#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER) +#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER) if (mmc->block_dev.dev == 0) omap5_pbias_config(mmc); #endif diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 1dac16a..a9c4237 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -30,7 +30,7 @@ COBJS-$(CONFIG_FTPMU010_POWER) += ftpmu010.o COBJS-$(CONFIG_TPS6586X_POWER) += tps6586x.o COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o COBJS-$(CONFIG_TWL6030_POWER) += twl6030.o -COBJS-$(CONFIG_TWL6035_POWER) += twl6035.o +COBJS-$(CONFIG_PALMAS_POWER) += palmas.o COBJS-$(CONFIG_POWER) += power_core.o COBJS-$(CONFIG_DIALOG_POWER) += power_dialog.o diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c new file mode 100644 index 0000000..8ed7742 --- /dev/null +++ b/drivers/power/palmas.c @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2012-2013 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + +/* Functions to read and write from TWL6030 */ +int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg) +{ + return i2c_write(chip_no, reg, 1, &val, 1); +} + +int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg) +{ + return i2c_read(chip_no, reg, 1, val, 1); +} + +/* To align with i2c mw/mr address, reg, val command syntax */ +static inline int palmas_write_u8(u8 chip_no, u8 reg, u8 val) +{ + return i2c_write(chip_no, reg, 1, &val, 1); +} + +static inline int palmas_read_u8(u8 chip_no, u8 reg, u8 *val) +{ + return i2c_read(chip_no, reg, 1, val, 1); +} + +void twl6035_init_settings(void) +{ + return; +} + +int twl6035_mmc1_poweron_ldo(void) +{ + u8 val = 0; + + /* set LDO9 TWL6035 to 3V */ + val = 0x2b; /* (3 -.9)*28 +1 */ + + if (palmas_write_u8(0x48, LDO9_VOLTAGE, val)) { + printf("twl6035: could not set LDO9 voltage.\n"); + return 1; + } + + /* TURN ON LDO9 */ + val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE; + + if (palmas_write_u8(0x48, LDO9_CTRL, val)) { + printf("twl6035: could not turn on LDO9.\n"); + return 1; + } + + return 0; +} diff --git a/drivers/power/twl6035.c b/drivers/power/twl6035.c deleted file mode 100644 index d3de698..0000000 --- a/drivers/power/twl6035.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include - -/* Functions to read and write from TWL6030 */ -int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg) -{ - return i2c_write(chip_no, reg, 1, &val, 1); -} - -int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg) -{ - return i2c_read(chip_no, reg, 1, val, 1); -} - -/* To align with i2c mw/mr address, reg, val command syntax */ -static inline int palmas_write_u8(u8 chip_no, u8 reg, u8 val) -{ - return i2c_write(chip_no, reg, 1, &val, 1); -} - -static inline int palmas_read_u8(u8 chip_no, u8 reg, u8 *val) -{ - return i2c_read(chip_no, reg, 1, val, 1); -} - -void twl6035_init_settings(void) -{ - return; -} - -int twl6035_mmc1_poweron_ldo(void) -{ - u8 val = 0; - - /* set LDO9 TWL6035 to 3V */ - val = 0x2b; /* (3 -.9)*28 +1 */ - - if (palmas_write_u8(0x48, LDO9_VOLTAGE, val)) { - printf("twl6035: could not set LDO9 voltage.\n"); - return 1; - } - - /* TURN ON LDO9 */ - val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE; - - if (palmas_write_u8(0x48, LDO9_CTRL, val)) { - printf("twl6035: could not turn on LDO9.\n"); - return 1; - } - - return 0; -} diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 240fdfc..c5bf51d 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -37,7 +37,7 @@ /* TWL6035 */ #ifndef CONFIG_SPL_BUILD -#define CONFIG_TWL6035_POWER +#define CONFIG_PALMAS_POWER #endif /* MMC ENV related defines */ diff --git a/include/palmas.h b/include/palmas.h new file mode 100644 index 0000000..cf836d7 --- /dev/null +++ b/include/palmas.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2012-2013 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* I2C chip addresses */ +#define PALMAS_CHIP_ADDR 0x48 + +/* 0x1XY translates to page 1, register address 0xXY */ +#define LDO9_CTRL 0x60 +#define LDO9_VOLTAGE 0x61 + +/* Bit field definitions for LDOx_CTRL */ +#define LDO_ON (1 << 4) +#define LDO_MODE_SLEEP (1 << 2) +#define LDO_MODE_ACTIVE (1 << 0) + +int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg); +int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg); +void twl6035_init_settings(void); +int twl6035_mmc1_poweron_ldo(void); diff --git a/include/twl6035.h b/include/twl6035.h deleted file mode 100644 index ce74348..0000000 --- a/include/twl6035.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* I2C chip addresses */ -#define TWL6035_CHIP_ADDR 0x48 - -/* 0x1XY translates to page 1, register address 0xXY */ -#define LDO9_CTRL 0x60 -#define LDO9_VOLTAGE 0x61 - -/* Bit field definitions for LDOx_CTRL */ -#define LDO_ON (1 << 4) -#define LDO_MODE_SLEEP (1 << 2) -#define LDO_MODE_ACTIVE (1 << 0) - -int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg); -int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg); -void twl6035_init_settings(void); -int twl6035_mmc1_poweron_ldo(void); -- cgit v0.10.2 From 12733881e94018f9a9b0cdb72c7ab55638142220 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 26 Mar 2013 05:20:55 +0000 Subject: palmas: rename init_settings to an generic palmas init Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs, rename twl6035_init_settings with an more generic palmas_init_settings Signed-off-by: Nishanth Menon diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 701842b..46db1bf 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -64,7 +64,7 @@ int board_eth_init(bd_t *bis) int misc_init_r(void) { #ifdef CONFIG_PALMAS_POWER - twl6035_init_settings(); + palmas_init_settings(); #endif return 0; } diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 8ed7742..bf36a19 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -45,7 +45,7 @@ static inline int palmas_read_u8(u8 chip_no, u8 reg, u8 *val) return i2c_read(chip_no, reg, 1, val, 1); } -void twl6035_init_settings(void) +void palmas_init_settings(void) { return; } diff --git a/include/palmas.h b/include/palmas.h index cf836d7..6618aad 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -38,5 +38,5 @@ int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg); int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg); -void twl6035_init_settings(void); +void palmas_init_settings(void); int twl6035_mmc1_poweron_ldo(void); -- cgit v0.10.2 From 384bcae013c78e020e9a04df4c7cc3b451a68811 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 26 Mar 2013 05:20:56 +0000 Subject: palmas: rename twl6035_mmc1_poweron_ldo with an palmas generic function Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs, rename twl6035_mmc1_poweron_ldo by a more generic palmas_mmc1_poweron_ldo function. Signed-off-by: Nishanth Menon diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index b39db9e..afdfa88 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -117,7 +117,7 @@ static void omap5_pbias_config(struct mmc *mmc) value |= SDCARD_BIAS_HIZ_MODE; writel(value, (*ctrl)->control_pbias); - twl6035_mmc1_poweron_ldo(); + palmas_mmc1_poweron_ldo(); value = readl((*ctrl)->control_pbias); value &= ~SDCARD_BIAS_HIZ_MODE; diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index bf36a19..489a7a9 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -50,7 +50,7 @@ void palmas_init_settings(void) return; } -int twl6035_mmc1_poweron_ldo(void) +int palmas_mmc1_poweron_ldo(void) { u8 val = 0; diff --git a/include/palmas.h b/include/palmas.h index 6618aad..305092e 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -39,4 +39,4 @@ int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg); int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg); void palmas_init_settings(void); -int twl6035_mmc1_poweron_ldo(void); +int palmas_mmc1_poweron_ldo(void); -- cgit v0.10.2 From ff2d57ea5e9b56e22c84647b9532292e5ea862f9 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 26 Mar 2013 05:20:57 +0000 Subject: palmas: use palmas_i2c_[read|write]_u8 commit 21144298 (power: twl6035: add palmas PMIC support) introduced twl6035_i2c_[read|write]_u8 Then, commit dd23e59d (omap5: pbias ldo9 turn on) introduced palmas_[read|write]_u8 for precisely the same access function. TWL6035 belongs to the palmas family, so instead of having an twl6035 API, we could use an generic palmas API instead. To stay consistent with the function naming of twl4030,6030 accessors, we use palmas_i2c_[read|write]_u8 Cc: Balaji T K Cc: Sricharan R Reported-by: Ruchika Kharwar Signed-off-by: Nishanth Menon diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 489a7a9..09c832d 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -23,28 +23,6 @@ #include #include -/* Functions to read and write from TWL6030 */ -int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg) -{ - return i2c_write(chip_no, reg, 1, &val, 1); -} - -int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg) -{ - return i2c_read(chip_no, reg, 1, val, 1); -} - -/* To align with i2c mw/mr address, reg, val command syntax */ -static inline int palmas_write_u8(u8 chip_no, u8 reg, u8 val) -{ - return i2c_write(chip_no, reg, 1, &val, 1); -} - -static inline int palmas_read_u8(u8 chip_no, u8 reg, u8 *val) -{ - return i2c_read(chip_no, reg, 1, val, 1); -} - void palmas_init_settings(void) { return; @@ -57,7 +35,7 @@ int palmas_mmc1_poweron_ldo(void) /* set LDO9 TWL6035 to 3V */ val = 0x2b; /* (3 -.9)*28 +1 */ - if (palmas_write_u8(0x48, LDO9_VOLTAGE, val)) { + if (palmas_i2c_write_u8(0x48, LDO9_VOLTAGE, val)) { printf("twl6035: could not set LDO9 voltage.\n"); return 1; } @@ -65,7 +43,7 @@ int palmas_mmc1_poweron_ldo(void) /* TURN ON LDO9 */ val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE; - if (palmas_write_u8(0x48, LDO9_CTRL, val)) { + if (palmas_i2c_write_u8(0x48, LDO9_CTRL, val)) { printf("twl6035: could not turn on LDO9.\n"); return 1; } diff --git a/include/palmas.h b/include/palmas.h index 305092e..e629fbf 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -36,7 +36,19 @@ #define LDO_MODE_SLEEP (1 << 2) #define LDO_MODE_ACTIVE (1 << 0) -int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg); -int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg); +/* + * Functions to read and write from TPS659038/TWL6035/TWL6037 + * or other Palmas family of TI PMICs + */ +static inline int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val) +{ + return i2c_write(chip_no, reg, 1, &val, 1); +} + +static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) +{ + return i2c_read(chip_no, reg, 1, val, 1); +} + void palmas_init_settings(void); int palmas_mmc1_poweron_ldo(void); -- cgit v0.10.2 From da2cc4545b7dfcff32eb2bb7feab43e1be9792f6 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 26 Mar 2013 05:20:58 +0000 Subject: palmas: add header guard Add an header guard to common header file to prevent multiple includes messing things up. Signed-off-by: Nishanth Menon diff --git a/include/palmas.h b/include/palmas.h index e629fbf..3b18589 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -20,6 +20,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +#ifndef PALMAS_H +#define PALMAS_H #include #include @@ -52,3 +54,5 @@ static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) void palmas_init_settings(void); int palmas_mmc1_poweron_ldo(void); + +#endif /* PALMAS_H */ -- cgit v0.10.2 From 3935277dbf4614215cc2510121ca837c8d321cc9 Mon Sep 17 00:00:00 2001 From: Lubomir Popov Date: Mon, 8 Apr 2013 21:49:37 +0000 Subject: OMAP5: I2C: Enable i2c5 clocks I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The i2c5 clock was however not enabled; do this here. Signed-off-by: Lubomir Popov diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ced274e..3a9352f 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -411,6 +411,7 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l4per_i2c2_clkctrl, (*prcm)->cm_l4per_i2c3_clkctrl, (*prcm)->cm_l4per_i2c4_clkctrl, + (*prcm)->cm_l4per_i2c5_clkctrl, (*prcm)->cm_l3init_hsusbtll_clkctrl, (*prcm)->cm_l3init_hsusbhost_clkctrl, (*prcm)->cm_l3init_fsusb_clkctrl, -- cgit v0.10.2 From aebe7ff2b261ed7c4eca141ecd90a63d85de9972 Mon Sep 17 00:00:00 2001 From: Lubomir Popov Date: Mon, 8 Apr 2013 21:49:40 +0000 Subject: OMAP5: I2C: Add I2C4 and I2C5 bases I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The I2C4 and I2C5 base addresses were however not defined; do this here. Signed-off-by: Lubomir Popov diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 5e62013..044ab55 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -142,6 +142,8 @@ struct watchdog { #define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) #define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) #define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) +#define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000) +#define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000) /* MUSB base */ #define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) -- cgit v0.10.2 From 2335b653d1cb971ddc467f85051fd850c3cd4a10 Mon Sep 17 00:00:00 2001 From: Lubomir Popov Date: Mon, 8 Apr 2013 21:49:43 +0000 Subject: OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5 I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. In order to be able to select one of these buses however, I2C_BUS_MAX has to be set to 5; do this here. Please note that for working bus selection, a fix to the i2c driver is required as well (subject of a separate patch). Signed-off-by: Lubomir Popov diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h index 68be03b..ec39a53 100644 --- a/arch/arm/include/asm/arch-omap5/i2c.h +++ b/arch/arm/include/asm/arch-omap5/i2c.h @@ -23,7 +23,7 @@ #ifndef _OMAP5_I2C_H_ #define _OMAP5_I2C_H_ -#define I2C_BUS_MAX 3 +#define I2C_BUS_MAX 5 #define I2C_DEFAULT_BASE I2C_BASE1 struct i2c { -- cgit v0.10.2 From 8ce4e5f9329183a162775946558092166cb7cab3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 16 Apr 2013 16:31:20 -0400 Subject: beagleboard: Update comment in get_board_rev() We are able to tell the difference between xM Rev Ax/Bx and xM Rev Cx, and have been for some time. The comment above the function however did not list this, so update. Signed-off-by: Tom Rini diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 3d9b6dd..c686f40 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -108,13 +108,14 @@ int board_init(void) /* * Routine: get_board_revision * Description: Detect if we are running on a Beagle revision Ax/Bx, - * C1/2/3, C4 or xM. This can be done by reading + * C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading * the level of GPIO173, GPIO172 and GPIO171. This should * result in * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 - * GPIO173, GPIO172, GPIO171: 0 0 0 => xM + * GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx + * GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx */ static int get_board_revision(void) { -- cgit v0.10.2 From 166e5cc6278881f2951e7c06a122ecb080dc8968 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 27 Mar 2013 20:24:42 +0000 Subject: arm: omap: emif: Fix DDR3 init after warm reset EMIF supports a global warm reset mode, during which the EMIF keeps the SDRAM content. But if leveling is enabled at the time of warm reset for DDR3, the following steps needs to be done after warm reset: 1) Keep EMIF in self refresh mode. 2) Reset PHY to bring back the PHY to a known state. 3) Start Levelling procedure. Doing the same. And also enabling DLL lock and code output after warm reset. Tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index cdb4439..11e830a 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1075,6 +1075,11 @@ static void do_sdram_init(u32 base) else ddr3_init(base, regs); } + if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { + set_lpmode_selfrefresh(base); + emif_reset_phy(base); + ddr3_leveling(base, regs); + } /* Write to the shadow registers */ emif_update_timings(base, regs); @@ -1262,10 +1267,10 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram); - if (!(in_sdram || warm_reset())) { - if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) + if (!in_sdram) { + if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) bypass_dpll((*prcm)->cm_clkmode_dpll_core); - else + else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); } -- cgit v0.10.2 From cc175e6353b088c6c79d8d51b56d76972aab5c65 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 4 Apr 2013 22:27:57 +0000 Subject: Add DDR3 support for IGEP COM AQUILA/CYGNUS. These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM. Signed-off-by: Enric Balletbo i Serra diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index fb4e78e..bb53a6a 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -117,6 +117,23 @@ #define MT41J512M8RH125_PHY_WR_DATA 0x74 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B +/* Samsung K4B2G1646E-BIH9 */ +#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06 +#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B +#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A +#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F +#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2 +#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B +#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 +#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1 +#define K4B2G1646EBIH9_RATIO 0x40 +#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1 +#define K4B2G1646EBIH9_RD_DQS 0x3B +#define K4B2G1646EBIH9_WR_DQS 0x85 +#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100 +#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1 +#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B + /** * Configure DMM */ -- cgit v0.10.2 From 5f5c1d13d3b3bb97fae1ed8c3c9e35b4af0f19e5 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 4 Apr 2013 22:27:58 +0000 Subject: ARM: Add support for IGEP COM AQUILA/CYGNUS The IGEP COM AQUILA and CYGNUS are industrial processors modules with following highlights: o AM3352/AM3354 Texas Instruments processor o Cortex-A8 ARM CPU o 3.3 volts Inputs / Outputs use industrial o 256 MB DDR3 SDRAM / 128 Megabytes FLASH o MicroSD card reader on-board o Ethernet controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Enric Balletbo i Serra diff --git a/MAINTAINERS b/MAINTAINERS index 643a5ac..a46803c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -607,6 +607,7 @@ Enric Balletbo i Serra igep0020 ARM ARMV7 (OMAP3xx SoC) igep0030 ARM ARMV7 (OMAP3xx SoC) igep0032 ARM ARMV7 (OMAP3xx SoC) + igep0033 ARM ARMV7 (AM33xx Soc) Eric Benard diff --git a/board/isee/igep0033/Makefile b/board/isee/igep0033/Makefile new file mode 100644 index 0000000..54a4b75 --- /dev/null +++ b/board/isee/igep0033/Makefile @@ -0,0 +1,46 @@ +# +# Makefile +# +# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c new file mode 100644 index 0000000..d315516 --- /dev/null +++ b/board/isee/igep0033/board.c @@ -0,0 +1,232 @@ +/* + * Board functions for IGEP COM AQUILA/CYGNUS based boards + * + * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; +#ifdef CONFIG_SPL_BUILD +static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; +#endif + +/* MII mode defines */ +#define RMII_MODE_ENABLE 0x4D + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* UART Defines */ +#ifdef CONFIG_SPL_BUILD +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +static void rtc32k_enable(void) +{ + struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; + + /* + * Unlock the RTC's registers. For more details please see the + * RTC_SS section of the TRM. In order to unlock we need to + * write these specific values (keys) in this order. + */ + writel(0x83e70b13, &rtc->kick0r); + writel(0x95a4f1e0, &rtc->kick1r); + + /* Enable the RTC 32K OSC by setting bits 3 and 6. */ + writel((1 << 3) | (1 << 6), &rtc->osc); +} + +static const struct ddr_data ddr3_data = { + .datardsratio0 = K4B2G1646EBIH9_RD_DQS, + .datawdsratio0 = K4B2G1646EBIH9_WR_DQS, + .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE, + .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = K4B2G1646EBIH9_RATIO, + .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, + .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, + + .cmd1csratio = K4B2G1646EBIH9_RATIO, + .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, + .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, + + .cmd2csratio = K4B2G1646EBIH9_RATIO, + .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, + .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG, + .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF, + .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1, + .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2, + .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3, + .zq_config = K4B2G1646EBIH9_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY, +}; +#endif + +/* + * Early system init of muxing and clocks. + */ +void s_init(void) +{ + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + +#ifdef CONFIG_SPL_BUILD + /* Setup the PLLs and the clocks for the peripherals */ + pll_init(); + + /* Enable RTC32K clock */ + rtc32k_enable(); + + /* UART softreset */ + u32 regval; + + enable_uart0_pin_mux(); + + regval = readl(&uart_base->uartsyscfg); + regval |= UART_RESET; + writel(regval, &uart_base->uartsyscfg); + while ((readl(&uart_base->uartsyssts) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + regval = readl(&uart_base->uartsyscfg); + regval |= UART_SMART_IDLE_EN; + writel(regval, &uart_base->uartsyscfg); + + gd = &gdata; + + preloader_console_init(); + + /* Configure board pin mux */ + enable_board_pin_mux(); + + config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +#endif +} + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + + gpmc_init(); + + return 0; +} + +#if defined(CONFIG_DRIVER_TI_CPSW) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv, ret = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + writel(RMII_MODE_ENABLE, &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + ret += rv; + + return ret; +} +#endif + diff --git a/board/isee/igep0033/board.h b/board/isee/igep0033/board.h new file mode 100644 index 0000000..37988e0 --- /dev/null +++ b/board/isee/igep0033/board.h @@ -0,0 +1,27 @@ +/* + * IGEP COM AQUILA/CYGNUS boards information header + * + * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * We must be able to enable uart0, for initial output. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/isee/igep0033/mux.c b/board/isee/igep0033/mux.c new file mode 100644 index 0000000..16f4add --- /dev/null +++ b/board/isee/igep0033/mux.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ + {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */ + {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */ + {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REF_CLK */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +/* + * Do board-specific muxes. + */ +void enable_board_pin_mux(void) +{ + /* NAND Flash */ + configure_module_pin_mux(nand_pin_mux); + /* SD Card */ + configure_module_pin_mux(mmc0_pin_mux); + /* Ethernet pinmux. */ + configure_module_pin_mux(rmii1_pin_mux); +} + diff --git a/boards.cfg b/boards.cfg index 31483d6..06ba979 100644 --- a/boards.cfg +++ b/boards.cfg @@ -277,6 +277,7 @@ igep0020_nand arm armv7 igep00x0 isee igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND +igep0033 arm armv7 igep0033 isee am33xx am3517_evm arm armv7 am3517evm logicpd omap3 mt_ventoux arm armv7 mt_ventoux teejet omap3 omap3_zoom1 arm armv7 zoom1 logicpd omap3 diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h new file mode 100644 index 0000000..50eafdf --- /dev/null +++ b/include/configs/igep0033.h @@ -0,0 +1,284 @@ +/* + * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_IGEP0033_H +#define __CONFIG_IGEP0033_H + +#define CONFIG_AM33XX + +#include + +/* Mach type */ +#define MACH_TYPE_IGEP0033 4521 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_IGEP0033 + +/* Clock defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* DMA defines */ +#define CONFIG_DMA_COHERENT +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_NO_FLASH + +/* Display cpuinfo */ +#define CONFIG_DISPLAY_CPUINFO + +/* Commands to include */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_MMC +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* + * Because the issues explained in doc/README.memory-test, the "mtest command + * is considered deprecated. It should not be enabled in most normal ports of + * U-Boot. + */ +#undef CONFIG_CMD_MEMTEST + +#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "rdaddr=0x81000000\0" \ + "bootfile=/boot/uImage\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loaduimagefat=load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ + "loaduimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot;" \ + "fi;" \ + "fi;" \ + +/* Max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) +/* Platform/Board specific defs */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ + +#define CONFIG_SERIAL_MULTI +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* MMC support */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* GPIO support */ +#define CONFIG_OMAP_GPIO + +/* Ethernet support */ +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_SMSC + +/* NAND support */ +#define CONFIG_NAND +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION 1 +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO + +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(SPL),"\ + "1m(U-Boot),128k(U-Boot Env),"\ + "5m(Kernel),-(File System)" + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (101 * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_NAND_AM33XX_BCH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_ECCSTEPS 4 +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#endif /* ! __CONFIG_IGEP0033_H */ -- cgit v0.10.2 From 2bcc785a1e8ffd3783c2116837fb4b4866a70cef Mon Sep 17 00:00:00 2001 From: Lubomir Popov Date: Thu, 11 Apr 2013 00:08:51 +0000 Subject: OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to work USB TLL clocks do not support 'explicit_en', only 'hw_auto' control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be moved to the clk_modules_hw_auto_essential[] array in order to make the clock work. This fix is needed (but not sufficient) for USB EHCI operation in U-Boot. Signed-off-by: Lubomir Popov diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 3a9352f..5698876 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -403,6 +403,7 @@ void enable_basic_uboot_clocks(void) }; u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -412,7 +413,6 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l4per_i2c3_clkctrl, (*prcm)->cm_l4per_i2c4_clkctrl, (*prcm)->cm_l4per_i2c5_clkctrl, - (*prcm)->cm_l3init_hsusbtll_clkctrl, (*prcm)->cm_l3init_hsusbhost_clkctrl, (*prcm)->cm_l3init_fsusb_clkctrl, 0 -- cgit v0.10.2 From 85b7ac4588c3128e3702f7232b3fd46c7cd7cf43 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 11 Apr 2013 05:22:10 +0000 Subject: omap5_common: Add optargs variable for kernel command line args Add 'optargs' variable to be set to additional kernel arguments, similar to omap3*/am3* usage. Cc: Sricharan R Signed-off-by: Tom Rini diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index c21c387..7528f4c 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -150,10 +150,12 @@ "usbtty=cdc_acm\0" \ "vram=16M\0" \ "partitions=" PARTS_DEFAULT "\0" \ + "optargs=\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext4 rootwait\0" \ "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ "vram=${vram} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ -- cgit v0.10.2 From 15191c91a240bd8683ca40e6c4b8b8c44b98412f Mon Sep 17 00:00:00 2001 From: Mark Jackson Date: Wed, 17 Apr 2013 08:22:47 +0000 Subject: Remove duplicate / unused #defines on AM335x boards As part of a review of a recent patch to add a new AM335x board, Tom found several duplicate and/or unused #defines. This patch simply removes them. The two affected configs have been recompiled to check nothing was broken (from a compilation point of view !!) Reported-by: Tom Rini Signed-off-by: Mark Jackson diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ef00306..5739422 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -196,7 +196,6 @@ + (8 * 1024 * 1024)) #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ -#define CONFIG_SYS_HZ 1000 /* 1ms clock */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC @@ -260,12 +259,11 @@ /* Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SERIAL_MULTI #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ @@ -360,11 +358,7 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ECCSTEPS 4 -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index d0ea74e..2e3f08b 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -129,7 +129,6 @@ + (8 * 1024 * 1024)) #define CONFIG_SYS_LOAD_ADDR 0x80007fc0 /* Default load address */ -#define CONFIG_SYS_HZ 1000 /* 1ms clock */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC @@ -158,13 +157,12 @@ /* Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ #define CONFIG_CONS_INDEX 1 /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SERIAL_MULTI #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -- cgit v0.10.2 From 0b1b60c77954df19b5a601e2ba87614f2d0bbb8b Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 17 Apr 2013 20:49:40 +0000 Subject: ARM: OMAP5: Fix warm reset with USB cable connected Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state. There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed. In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time. Signed-off-by: Lokesh Vutla [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak diff --git a/README b/README index 0bc0af5..4531891 100644 --- a/README +++ b/README @@ -3323,6 +3323,10 @@ Configuration Settings: offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than directly. You should not need to touch this setting. +- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only) + This is set by OMAP boards for the max time that reset should + be asserted. See doc/README.omap-reset-time for details on how + the value can be calulated on a given board. The following definitions that deal with the placement and management of environment data (variable area); in general, we support the diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 2b955c7..99910cd 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -716,6 +716,7 @@ void prcm_init(void) setup_non_essential_dplls(); enable_non_essential_clocks(); #endif + setup_warmreset_time(); break; default: break; diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/cpu/armv7/omap-common/reset.c index 587bb47..57ea9d9 100644 --- a/arch/arm/cpu/armv7/omap-common/reset.c +++ b/arch/arm/cpu/armv7/omap-common/reset.c @@ -39,3 +39,7 @@ u32 __weak warm_reset(void) { return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK); } + +void __weak setup_warmreset_time(void) +{ +} diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 2f4b247..d29df78 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -363,3 +363,22 @@ u32 warm_reset(void) { return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK; } + +void setup_warmreset_time(void) +{ + u32 rst_time, rst_val; + +#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC + rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC; +#else + rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC; +#endif + rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT; + + if (rst_time > RSTTIME1_MASK) + rst_time = RSTTIME1_MASK; + + rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK; + rst_val |= rst_time; + writel(rst_val, (*prcm)->prm_rsttime); +} diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index b8a61fe..e9f6a32 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -729,6 +729,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, .prm_rstctrl = 0x4ae07c00, .prm_rstst = 0x4ae07c04, + .prm_rsttime = 0x4ae07c08, .prm_vc_val_bypass = 0x4ae07ca0, .prm_vc_cfg_i2c_mode = 0x4ae07cb4, .prm_vc_cfg_i2c_clk = 0x4ae07cb8, @@ -952,6 +953,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_wkupaon_scrm_clkctrl = 0x4ae07890, .prm_rstctrl = 0x4ae07d00, .prm_rstst = 0x4ae07d04, + .prm_rsttime = 0x4ae07d08, .prm_vc_val_bypass = 0x4ae07da0, .prm_vc_cfg_i2c_mode = 0x4ae07db4, .prm_vc_cfg_i2c_clk = 0x4ae07db8, diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index d5f1868..ac9c1f8 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -58,6 +58,7 @@ void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); +void setup_warmreset_time(void); /* * This is used to verify if the configuration header * was executed by Romcode prior to control of transfer diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index cfde374..68afa76 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -190,6 +190,10 @@ #define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 #define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) +/* PRM_RSTTIME */ +#define RSTTIME1_SHIFT 0 +#define RSTTIME1_MASK (0x3ff << 0) + /* Clock frequencies */ #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 @@ -251,4 +255,10 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 +/* + * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. + * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles + * into microsec and passing the value. + */ +#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 #endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index e66ab44..393c8bf 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -64,6 +64,7 @@ u32 warm_reset(void); void force_emif_self_refresh(void); void get_ioregs(const struct ctrl_ioregs **regs); void srcomp_enable(void); +void setup_warmreset_time(void); /* * This is used to verify if the configuration header @@ -122,4 +123,13 @@ static inline u32 omap_hw_init_context(void) #endif } +static inline u32 div_round_up(u32 num, u32 den) +{ + return (num + den - 1)/den; +} + +static inline u32 usec_to_32k(u32 usec) +{ + return div_round_up(32768 * usec, 1000000); +} #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 091ddb5..6d377d5 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -316,6 +316,7 @@ struct prcm_regs { u32 cm_wkupaon_io_srcomp_clkctrl; u32 prm_rstctrl; u32 prm_rstst; + u32 prm_rsttime; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; diff --git a/doc/README.omap-reset-time b/doc/README.omap-reset-time new file mode 100644 index 0000000..0c974ba --- /dev/null +++ b/doc/README.omap-reset-time @@ -0,0 +1,20 @@ +README on how reset time on OMAPs should be calculated + +CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC: +Most OMAPs' provide a way to specify the time for +which the reset should be held low while the voltages +and Oscillator outputs stabilize. + +This time is mostly board and PMIC dependent. Hence the +boards are expected to specify a pre-computed time +using the above option, (the details on how to compute +the value are given below) without which a default time +as specified by CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC +is used. + +The value for CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC +can be computed using a summation of the below 3 parameters +-1- Time taken by the Osciallator to stop and restart +-2- PMIC OTP time +-3- Voltage ramp time, which can be derived using the +PMIC slew rate and value of voltage ramp needed. diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index c5bf51d..c791789 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -54,4 +54,5 @@ #define CONFIG_SYS_PROMPT "OMAP5430 EVM # " +#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 #endif /* __CONFIG_OMAP5_EVM_H */ -- cgit v0.10.2 From 34f667bbc4819607735dd56df17c8f1789af40d1 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Thu, 18 Apr 2013 06:29:53 +0000 Subject: ARM:Panda:Fix device tree loading for the panda-es Fix the device tree loading for panda(4430) and panda-es(4460) Modify the board name if a 4460 panda or panda-es is detected at run time. In the findfdt add a check for the panda-es board name and load the panda-es device tree blob. Signed-off-by: Dan Murphy diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index cab0598..2bbe392 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -82,6 +82,12 @@ int misc_init_r(void) if (omap_revision() == OMAP4430_ES1_0) return 0; +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (omap_revision() >= OMAP4460_ES1_0 || + omap_revision() <= OMAP4460_ES1_1) + setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es")); +#endif + gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO); phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO); diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 1fd3097..68faeca 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -176,7 +176,9 @@ "if test $board_name = sdp4430; then " \ "setenv fdtfile omap4-sdp.dtb; fi; " \ "if test $board_name = panda; then " \ - "setenv fdtfile omap4-panda-es.dtb; fi\0" \ + "setenv fdtfile omap4-panda.dtb; fi;" \ + "if test $board_name = panda-es; then " \ + "setenv fdtfile omap4-panda-es.dtb; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ #define CONFIG_BOOTCOMMAND \ -- cgit v0.10.2 From 584506bee694643214152ed2bec9a99df9a244d6 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Thu, 18 Apr 2013 06:29:54 +0000 Subject: ARM: Panda: Add flag to allow runtime enviroment varibale mods Add the flag to allow runtime enviroment variable modifications. This is being added so that the board-name can be modified at runtime to indicate either a panda(4430) or a panda-es(4460) Signed-off-by: Dan Murphy diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index eacb5f5..abf586b 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -66,4 +66,6 @@ #define CONFIG_SYS_PROMPT "Panda # " +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #endif /* __CONFIG_PANDA_H */ -- cgit v0.10.2 From 811acf923d8a0052f22b50306d9362d7e0f8e108 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Mon, 22 Apr 2013 01:06:53 +0000 Subject: cm-t35: move cm-t35 to live in compulab directory Currently the cm-t35 support code lives under board/cm_t35 directory. Some of the code can be shared with other/future CompuLab boards, so move the cm-t35 to live under board/compulab/cm_t35 directory. Signed-off-by: Igor Grinberg Tested-by: Nikita Kiryanov diff --git a/board/cm_t35/Makefile b/board/cm_t35/Makefile deleted file mode 100644 index bde56e6..0000000 --- a/board/cm_t35/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o -COBJS-$(CONFIG_LCD) += display.o - -COBJS := cm_t35.o leds.o $(COBJS-y) - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c deleted file mode 100644 index 8528680..0000000 --- a/board/cm_t35/cm_t35.c +++ /dev/null @@ -1,617 +0,0 @@ -/* - * (C) Copyright 2011 CompuLab, Ltd. - * - * Authors: Mike Rapoport - * Igor Grinberg - * - * Derived from omap3evm and Beagle Board by - * Manikandan Pillai - * Richard Woodruff - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "eeprom.h" - -DECLARE_GLOBAL_DATA_PTR; - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "CM-T3x board", - "NAND", -}; - -static u32 gpmc_net_config[GPMC_MAX_REG] = { - NET_GPMC_CONFIG1, - NET_GPMC_CONFIG2, - NET_GPMC_CONFIG3, - NET_GPMC_CONFIG4, - NET_GPMC_CONFIG5, - NET_GPMC_CONFIG6, - 0 -}; - -static u32 gpmc_nand_config[GPMC_MAX_REG] = { - SMNAND_GPMC_CONFIG1, - SMNAND_GPMC_CONFIG2, - SMNAND_GPMC_CONFIG3, - SMNAND_GPMC_CONFIG4, - SMNAND_GPMC_CONFIG5, - SMNAND_GPMC_CONFIG6, - 0, -}; - -#ifdef CONFIG_LCD -#ifdef CONFIG_CMD_NAND -static int splash_load_from_nand(u32 bmp_load_addr) -{ - struct bmp_header *bmp_hdr; - int res, splash_screen_nand_offset = 0x100000; - size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); - - if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) - goto splash_address_too_high; - - res = nand_read_skip_bad(&nand_info[nand_curr_device], - splash_screen_nand_offset, &bmp_header_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); - if (res < 0) - return res; - - bmp_hdr = (struct bmp_header *)bmp_load_addr; - bmp_size = le32_to_cpu(bmp_hdr->file_size); - - if (bmp_load_addr + bmp_size >= gd->start_addr_sp) - goto splash_address_too_high; - - return nand_read_skip_bad(&nand_info[nand_curr_device], - splash_screen_nand_offset, &bmp_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); - -splash_address_too_high: - printf("Error: splashimage address too high. Data overwrites U-Boot " - "and/or placed beyond DRAM boundaries.\n"); - - return -1; -} -#else -static inline int splash_load_from_nand(void) -{ - return -1; -} -#endif /* CONFIG_CMD_NAND */ - -int board_splash_screen_prepare(void) -{ - char *env_splashimage_value; - u32 bmp_load_addr; - - env_splashimage_value = getenv("splashimage"); - if (env_splashimage_value == NULL) - return -1; - - bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); - if (bmp_load_addr == 0) { - printf("Error: bad splashimage address specified\n"); - return -1; - } - - return splash_load_from_nand(bmp_load_addr); -} -#endif /* CONFIG_LCD */ - -/* - * Routine: board_init - * Description: hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - - enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], - CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); - - /* board id for Linux */ - if (get_cpu_family() == CPU_OMAP34XX) - gd->bd->bi_arch_number = MACH_TYPE_CM_T35; - else - gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; - - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - -#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); -#endif - - return 0; -} - -static u32 cm_t3x_rev; - -/* - * Routine: get_board_rev - * Description: read system revision - */ -u32 get_board_rev(void) -{ - if (!cm_t3x_rev) - cm_t3x_rev = cm_t3x_eeprom_get_board_rev(); - - return cm_t3x_rev; -}; - -/* - * Routine: misc_init_r - * Description: display die ID - */ -int misc_init_r(void) -{ - u32 board_rev = get_board_rev(); - u32 rev_major = board_rev / 100; - u32 rev_minor = board_rev - (rev_major * 100); - - if ((rev_minor / 10) * 10 == rev_minor) - rev_minor = rev_minor / 10; - - printf("PCB: %u.%u\n", rev_major, rev_minor); - dieid_num_r(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -static void cm_t3x_set_common_muxconf(void) -{ - /* SDRC */ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ - - /* GPMC */ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ - - /* SB-T35 Ethernet */ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ - - /* DVI enable */ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ - - /* CM-T3x Ethernet */ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ - MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ - MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ - - /* DSS */ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ - - /* serial interface */ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ - - /* mUSB */ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ - - /* USB EHCI */ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ - - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ - - /* SB_T35_USB_HUB_RESET_GPIO */ - MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ - - /* I2C1 */ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ - /* I2C2 */ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ - /* I2C3 */ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ - - /* control and debug */ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ - - /* MMC1 */ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ -} - -static void cm_t35_set_muxconf(void) -{ - /* DSS */ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ - - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ - - /* MMC1 */ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ -} - -static void cm_t3730_set_muxconf(void) -{ - /* DSS */ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ - - MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ - MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ - MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ - MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ - MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ -} - -void set_muxconf_regs(void) -{ - cm_t3x_set_common_muxconf(); - - if (get_cpu_family() == CPU_OMAP34XX) - cm_t35_set_muxconf(); - else - cm_t3730_set_muxconf(); -} - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_getcd(struct mmc *mmc) -{ - u8 val; - - if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) - return -1; - - return !(val & 1); -} - -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, 59); -} -#endif - -/* - * Routine: setup_net_chip_gmpc - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip_gmpc(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], - CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], - SB_T35_SMC911X_BASE, GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); -} - -#ifdef CONFIG_DRIVER_OMAP34XX_I2C -/* - * Routine: reset_net_chip - * Description: reset the Ethernet controller via TPS65930 GPIO - */ -static void reset_net_chip(void) -{ - /* Set GPIO1 of TPS65930 as output */ - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, - 0x02); - /* Send a pulse on the GPIO pin */ - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, - 0x02); - udelay(1); - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, - 0x02); - mdelay(40); - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, - 0x02); - mdelay(1); -} -#else -static inline void reset_net_chip(void) {} -#endif - -#ifdef CONFIG_SMC911X -/* - * Routine: handle_mac_address - * Description: prepare MAC address for on-board Ethernet. - */ -static int handle_mac_address(void) -{ - unsigned char enetaddr[6]; - int rc; - - rc = eth_getenv_enetaddr("ethaddr", enetaddr); - if (rc) - return 0; - - rc = cm_t3x_eeprom_read_mac_addr(enetaddr); - if (rc) - return rc; - - if (!is_valid_ether_addr(enetaddr)) - return -1; - - return eth_setenv_enetaddr("ethaddr", enetaddr); -} - - -/* - * Routine: board_eth_init - * Description: initialize module and base-board Ethernet chips - */ -int board_eth_init(bd_t *bis) -{ - int rc = 0, rc1 = 0; - - setup_net_chip_gmpc(); - reset_net_chip(); - - rc1 = handle_mac_address(); - if (rc1) - printf("No MAC address found! "); - - rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); - if (rc1 > 0) - rc++; - - rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); - if (rc1 > 0) - rc++; - - return rc; -} -#endif - -void __weak get_board_serial(struct tag_serialnr *serialnr) -{ - /* - * This corresponds to what happens when we can communicate with the - * eeprom but don't get a valid board serial value. - */ - serialnr->low = 0; - serialnr->high = 0; -}; - -#ifdef CONFIG_USB_EHCI_OMAP -struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, -}; - -#define SB_T35_USB_HUB_RESET_GPIO 167 -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - u8 val; - int offset; - - if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { - printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", - SB_T35_USB_HUB_RESET_GPIO); - return -1; - } - - gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); - udelay(10); - gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); - udelay(1000); - - offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; - twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); - /* Set GPIO6 and GPIO7 of TPS65930 as output */ - val |= 0xC0; - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); - offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; - /* Take both PHYs out of reset */ - twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); - udelay(1); - - return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(void) -{ - return omap_ehci_hcd_stop(); -} - -#endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/cm_t35/display.c b/board/cm_t35/display.c deleted file mode 100644 index a004ea1..0000000 --- a/board/cm_t35/display.c +++ /dev/null @@ -1,420 +0,0 @@ -/* - * (C) Copyright 2012 CompuLab, Ltd. - * - * Authors: Nikita Kiryanov - * - * Parsing code based on linux/drivers/video/pxafb.c - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -enum display_type { - NONE, - DVI, - DVI_CUSTOM, -}; - -#define CMAP_ADDR 0x80100000 - -/* - * The frame buffer is allocated before we have the chance to parse user input. - * To make sure enough memory is allocated for all resolutions, we define - * vl_{col | row} to the maximal resolution supported by OMAP3. - */ -vidinfo_t panel_info = { - .vl_col = 1400, - .vl_row = 1050, - .vl_bpix = LCD_BPP, - .cmap = (ushort *)CMAP_ADDR, -}; - -static struct panel_config panel_cfg; -static enum display_type lcd_def; - -/* - * A note on DVI presets; - * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can - * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to - * support two BMP types with one setting. - */ -static const struct panel_config preset_dvi_640X480 = { - .lcd_size = PANEL_LCD_SIZE(640, 480), - .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96), - .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2), - .divisor = 12 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -static const struct panel_config preset_dvi_800X600 = { - .lcd_size = PANEL_LCD_SIZE(800, 600), - .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128), - .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4), - .divisor = 8 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -static const struct panel_config preset_dvi_1024X768 = { - .lcd_size = PANEL_LCD_SIZE(1024, 768), - .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136), - .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6), - .divisor = 5 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -static const struct panel_config preset_dvi_1152X864 = { - .lcd_size = PANEL_LCD_SIZE(1152, 864), - .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128), - .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3), - .divisor = 3 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -static const struct panel_config preset_dvi_1280X960 = { - .lcd_size = PANEL_LCD_SIZE(1280, 960), - .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112), - .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3), - .divisor = 3 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -static const struct panel_config preset_dvi_1280X1024 = { - .lcd_size = PANEL_LCD_SIZE(1280, 1024), - .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112), - .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3), - .divisor = 3 | (1 << 16), - .data_lines = LCD_INTERFACE_24_BIT, - .panel_type = ACTIVE_DISPLAY, - .load_mode = 2, - .gfx_format = GFXFORMAT_RGB16, -}; - -/* - * set_resolution_params() - * - * Due to usage of multiple display related APIs resolution data is located in - * more than one place. This function updates them all. - */ -static void set_resolution_params(int x, int y) -{ - panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y); - panel_info.vl_col = x; - panel_info.vl_row = y; - lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; -} - -static void set_preset(const struct panel_config preset, int x_res, int y_res) -{ - panel_cfg = preset; - set_resolution_params(x_res, y_res); -} - -static enum display_type set_dvi_preset(const struct panel_config preset, - int x_res, int y_res) -{ - set_preset(preset, x_res, y_res); - return DVI; -} - -/* - * parse_mode() - parse the mode parameter of custom lcd settings - * - * @mode: x - * - * Returns -1 on error, 0 on success. - */ -static int parse_mode(const char *mode) -{ - unsigned int modelen = strlen(mode); - int res_specified = 0; - unsigned int xres = 0, yres = 0; - int yres_specified = 0; - int i; - - for (i = modelen - 1; i >= 0; i--) { - switch (mode[i]) { - case 'x': - if (!yres_specified) { - yres = simple_strtoul(&mode[i + 1], NULL, 0); - yres_specified = 1; - } else { - goto done_parsing; - } - - break; - case '0' ... '9': - break; - default: - goto done_parsing; - } - } - - if (i < 0 && yres_specified) { - xres = simple_strtoul(mode, NULL, 0); - res_specified = 1; - } - -done_parsing: - if (res_specified) { - set_resolution_params(xres, yres); - } else { - printf("LCD: invalid mode: %s\n", mode); - return -1; - } - - return 0; -} - -#define PIXEL_CLK_NUMERATOR (26 * 432 / 39) -/* - * parse_pixclock() - Parse the pixclock parameter of custom lcd settings - * - * @pixclock: the desired pixel clock - * - * Returns -1 on error, 0 on success. - * - * Handling the pixel_clock: - * - * Pixel clock is defined in the OMAP35x TRM as follows: - * pixel_clock = - * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) / - * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] * - * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1)) - * - * In practice, this means that in order to set the - * divisor for the desired pixel clock one needs to - * solve the following equation: - * - * 26 * 432 / (39 * ) = DSS.DISPC_DIVISOR[6:0] - * - * NOTE: the explicit equation above is reduced. Do not - * try to infer anything from these numbers. - */ -static int parse_pixclock(char *pixclock) -{ - int divisor, pixclock_val; - char *pixclk_start = pixclock; - - pixclock_val = simple_strtoul(pixclock, &pixclock, 10); - divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val); - /* 0 and 1 are illegal values for PCD */ - if (divisor <= 1) - divisor = 2; - - panel_cfg.divisor = divisor | (1 << 16); - if (pixclock[0] != '\0') { - printf("LCD: invalid value for pixclock:%s\n", pixclk_start); - return -1; - } - - return 0; -} - -/* - * parse_setting() - parse a single setting of custom lcd parameters - * - * @setting: The custom lcd setting : - * - * Returns -1 on failure, 0 on success. - */ -static int parse_setting(char *setting) -{ - int num_val; - char *setting_start = setting; - - if (!strncmp(setting, "mode:", 5)) { - return parse_mode(setting + 5); - } else if (!strncmp(setting, "pixclock:", 9)) { - return parse_pixclock(setting + 9); - } else if (!strncmp(setting, "left:", 5)) { - num_val = simple_strtoul(setting + 5, &setting, 0); - panel_cfg.timing_h |= DSS_HBP(num_val); - } else if (!strncmp(setting, "right:", 6)) { - num_val = simple_strtoul(setting + 6, &setting, 0); - panel_cfg.timing_h |= DSS_HFP(num_val); - } else if (!strncmp(setting, "upper:", 6)) { - num_val = simple_strtoul(setting + 6, &setting, 0); - panel_cfg.timing_v |= DSS_VBP(num_val); - } else if (!strncmp(setting, "lower:", 6)) { - num_val = simple_strtoul(setting + 6, &setting, 0); - panel_cfg.timing_v |= DSS_VFP(num_val); - } else if (!strncmp(setting, "hsynclen:", 9)) { - num_val = simple_strtoul(setting + 9, &setting, 0); - panel_cfg.timing_h |= DSS_HSW(num_val); - } else if (!strncmp(setting, "vsynclen:", 9)) { - num_val = simple_strtoul(setting + 9, &setting, 0); - panel_cfg.timing_v |= DSS_VSW(num_val); - } else if (!strncmp(setting, "hsync:", 6)) { - if (simple_strtoul(setting + 6, &setting, 0) == 0) - panel_cfg.pol_freq |= DSS_IHS; - else - panel_cfg.pol_freq &= ~DSS_IHS; - } else if (!strncmp(setting, "vsync:", 6)) { - if (simple_strtoul(setting + 6, &setting, 0) == 0) - panel_cfg.pol_freq |= DSS_IVS; - else - panel_cfg.pol_freq &= ~DSS_IVS; - } else if (!strncmp(setting, "outputen:", 9)) { - if (simple_strtoul(setting + 9, &setting, 0) == 0) - panel_cfg.pol_freq |= DSS_IEO; - else - panel_cfg.pol_freq &= ~DSS_IEO; - } else if (!strncmp(setting, "pixclockpol:", 12)) { - if (simple_strtoul(setting + 12, &setting, 0) == 0) - panel_cfg.pol_freq |= DSS_IPC; - else - panel_cfg.pol_freq &= ~DSS_IPC; - } else if (!strncmp(setting, "active", 6)) { - panel_cfg.panel_type = ACTIVE_DISPLAY; - return 0; /* Avoid sanity check below */ - } else if (!strncmp(setting, "passive", 7)) { - panel_cfg.panel_type = PASSIVE_DISPLAY; - return 0; /* Avoid sanity check below */ - } else if (!strncmp(setting, "display:", 8)) { - if (!strncmp(setting + 8, "dvi", 3)) { - lcd_def = DVI_CUSTOM; - return 0; /* Avoid sanity check below */ - } - } else { - printf("LCD: unknown option %s\n", setting_start); - return -1; - } - - if (setting[0] != '\0') { - printf("LCD: invalid value for %s\n", setting_start); - return -1; - } - - return 0; -} - -/* - * env_parse_customlcd() - parse custom lcd params from an environment variable. - * - * @custom_lcd_params: The environment variable containing the lcd params. - * - * Returns -1 on failure, 0 on success. - */ -static int parse_customlcd(char *custom_lcd_params) -{ - char params_cpy[160]; - char *setting; - - strncpy(params_cpy, custom_lcd_params, 160); - setting = strtok(params_cpy, ","); - while (setting) { - if (parse_setting(setting) < 0) - return -1; - - setting = strtok(NULL, ","); - } - - /* Currently we don't support changing this via custom lcd params */ - panel_cfg.data_lines = LCD_INTERFACE_24_BIT; - panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */ - - return 0; -} - -/* - * env_parse_displaytype() - parse display type. - * - * Parses the environment variable "displaytype", which contains the - * name of the display type or preset, in which case it applies its - * configurations. - * - * Returns the type of display that was specified. - */ -static enum display_type env_parse_displaytype(char *displaytype) -{ - if (!strncmp(displaytype, "dvi640x480", 10)) - return set_dvi_preset(preset_dvi_640X480, 640, 480); - else if (!strncmp(displaytype, "dvi800x600", 10)) - return set_dvi_preset(preset_dvi_800X600, 800, 600); - else if (!strncmp(displaytype, "dvi1024x768", 11)) - return set_dvi_preset(preset_dvi_1024X768, 1024, 768); - else if (!strncmp(displaytype, "dvi1152x864", 11)) - return set_dvi_preset(preset_dvi_1152X864, 1152, 864); - else if (!strncmp(displaytype, "dvi1280x960", 11)) - return set_dvi_preset(preset_dvi_1280X960, 1280, 960); - else if (!strncmp(displaytype, "dvi1280x1024", 12)) - return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024); - - return NONE; -} - -void lcd_ctrl_init(void *lcdbase) -{ - struct prcm *prcm = (struct prcm *)PRCM_BASE; - char *custom_lcd; - char *displaytype = getenv("displaytype"); - - if (displaytype == NULL) - return; - - lcd_def = env_parse_displaytype(displaytype); - /* If we did not recognize the preset, check if it's an env variable */ - if (lcd_def == NONE) { - custom_lcd = getenv(displaytype); - if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0) - return; - } - - panel_cfg.frame_buffer = lcdbase; - omap3_dss_panel_config(&panel_cfg); - /* - * Pixel clock is defined with many divisions and only few - * multiplications of the system clock. Since DSS FCLK divisor is set - * to 16 by default, we need to set it to a smaller value, like 3 - * (chosen via trial and error). - */ - clrsetbits_le32(&prcm->clksel_dss, 0xF, 3); -} - -void lcd_enable(void) -{ - if (lcd_def == DVI || lcd_def == DVI_CUSTOM) { - gpio_direction_output(54, 0); /* Turn on DVI */ - omap3_dss_enable(); - } -} - -void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {} diff --git a/board/cm_t35/eeprom.c b/board/cm_t35/eeprom.c deleted file mode 100644 index b0af103..0000000 --- a/board/cm_t35/eeprom.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2011 CompuLab, Ltd. - * - * Authors: Nikita Kiryanov - * Igor Grinberg - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include -#include - -#define EEPROM_LAYOUT_VER_OFFSET 44 -#define BOARD_SERIAL_OFFSET 20 -#define BOARD_SERIAL_OFFSET_LEGACY 8 -#define BOARD_REV_OFFSET 0 -#define BOARD_REV_OFFSET_LEGACY 6 -#define BOARD_REV_SIZE 2 -#define MAC_ADDR_OFFSET 4 -#define MAC_ADDR_OFFSET_LEGACY 0 - -#define LAYOUT_INVALID 0 -#define LAYOUT_LEGACY 0xff - -static int eeprom_layout; /* Implicitly LAYOUT_INVALID */ - -static int cm_t3x_eeprom_read(uint offset, uchar *buf, int len) -{ - return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len); -} - -static int eeprom_setup_layout(void) -{ - int res; - - if (eeprom_layout != LAYOUT_INVALID) - return 0; - - res = cm_t3x_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, - (uchar *)&eeprom_layout, 1); - if (res) { - eeprom_layout = LAYOUT_INVALID; - return res; - } - - if (eeprom_layout == 0 || eeprom_layout >= 0x20) - eeprom_layout = LAYOUT_LEGACY; - - return 0; -} - -void get_board_serial(struct tag_serialnr *serialnr) -{ - u32 serial[2]; - uint offset; - - memset(serialnr, 0, sizeof(*serialnr)); - if (eeprom_setup_layout()) - return; - - offset = (eeprom_layout != LAYOUT_LEGACY) ? - BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY; - if (cm_t3x_eeprom_read(offset, (uchar *)serial, 8)) - return; - - if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) { - serialnr->low = serial[0]; - serialnr->high = serial[1]; - } -} - -/* - * Routine: cm_t3x_eeprom_read_mac_addr - * Description: read mac address and store it in buf. - */ -int cm_t3x_eeprom_read_mac_addr(uchar *buf) -{ - uint offset; - - if (eeprom_setup_layout()) - return 0; - - offset = (eeprom_layout != LAYOUT_LEGACY) ? - MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY; - return cm_t3x_eeprom_read(offset, buf, 6); -} - -/* - * Routine: cm_t3x_eeprom_get_board_rev - * Description: read system revision from eeprom - */ -u32 cm_t3x_eeprom_get_board_rev(void) -{ - u32 rev = 0; - char str[5]; /* Legacy representation can contain at most 4 digits */ - uint offset = BOARD_REV_OFFSET_LEGACY; - - if (eeprom_setup_layout()) - return 0; - - if (eeprom_layout != LAYOUT_LEGACY) - offset = BOARD_REV_OFFSET; - - if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) - return 0; - - /* - * Convert legacy syntactic representation to semantic - * representation. i.e. for rev 1.00: 0x100 --> 0x64 - */ - if (eeprom_layout == LAYOUT_LEGACY) { - sprintf(str, "%x", rev); - rev = simple_strtoul(str, NULL, 10); - } - - return rev; -}; diff --git a/board/cm_t35/eeprom.h b/board/cm_t35/eeprom.h deleted file mode 100644 index 38824d1..0000000 --- a/board/cm_t35/eeprom.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2011 CompuLab, Ltd. - * - * Authors: Nikita Kiryanov - * Igor Grinberg - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ -#ifndef _EEPROM_ -#define _EEPROM_ - -#ifdef CONFIG_DRIVER_OMAP34XX_I2C -int cm_t3x_eeprom_read_mac_addr(uchar *buf); -u32 cm_t3x_eeprom_get_board_rev(void); -#else -static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf) -{ - return 1; -} -static inline u32 cm_t3x_eeprom_get_board_rev(void) -{ - return 0; -} -#endif - -#endif diff --git a/board/cm_t35/leds.c b/board/cm_t35/leds.c deleted file mode 100644 index 48ad598..0000000 --- a/board/cm_t35/leds.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2011 - * CompuLab, Ltd. - * - * Author: Igor Grinberg - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ -#include -#include -#include - -static unsigned int leds[] = { GREEN_LED_GPIO }; - -void __led_init(led_id_t mask, int state) -{ - if (gpio_request(leds[mask], "") != 0) { - printf("%s: failed requesting GPIO%u\n", __func__, leds[mask]); - return; - } - - gpio_direction_output(leds[mask], 0); -} - -void __led_set(led_id_t mask, int state) -{ - gpio_set_value(leds[mask], state == STATUS_LED_ON); -} - -void __led_toggle(led_id_t mask) -{ - gpio_set_value(leds[mask], !gpio_get_value(leds[mask])); -} diff --git a/board/compulab/cm_t35/Makefile b/board/compulab/cm_t35/Makefile new file mode 100644 index 0000000..31d9bbb --- /dev/null +++ b/board/compulab/cm_t35/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2011 - 2013 CompuLab, Ltd. +# +# Authors: Nikita Kiryanov +# Igor Grinberg +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o +COBJS-$(CONFIG_LCD) += display.o + +COBJS := cm_t35.o leds.o $(COBJS-y) + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c new file mode 100644 index 0000000..b0b80e5 --- /dev/null +++ b/board/compulab/cm_t35/cm_t35.c @@ -0,0 +1,617 @@ +/* + * (C) Copyright 2011 - 2013 CompuLab, Ltd. + * + * Authors: Mike Rapoport + * Igor Grinberg + * + * Derived from omap3evm and Beagle Board by + * Manikandan Pillai + * Richard Woodruff + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "CM-T3x board", + "NAND", +}; + +static u32 gpmc_net_config[GPMC_MAX_REG] = { + NET_GPMC_CONFIG1, + NET_GPMC_CONFIG2, + NET_GPMC_CONFIG3, + NET_GPMC_CONFIG4, + NET_GPMC_CONFIG5, + NET_GPMC_CONFIG6, + 0 +}; + +static u32 gpmc_nand_config[GPMC_MAX_REG] = { + SMNAND_GPMC_CONFIG1, + SMNAND_GPMC_CONFIG2, + SMNAND_GPMC_CONFIG3, + SMNAND_GPMC_CONFIG4, + SMNAND_GPMC_CONFIG5, + SMNAND_GPMC_CONFIG6, + 0, +}; + +#ifdef CONFIG_LCD +#ifdef CONFIG_CMD_NAND +static int splash_load_from_nand(u32 bmp_load_addr) +{ + struct bmp_header *bmp_hdr; + int res, splash_screen_nand_offset = 0x100000; + size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); + + if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) + goto splash_address_too_high; + + res = nand_read_skip_bad(&nand_info[nand_curr_device], + splash_screen_nand_offset, &bmp_header_size, + NULL, nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); + if (res < 0) + return res; + + bmp_hdr = (struct bmp_header *)bmp_load_addr; + bmp_size = le32_to_cpu(bmp_hdr->file_size); + + if (bmp_load_addr + bmp_size >= gd->start_addr_sp) + goto splash_address_too_high; + + return nand_read_skip_bad(&nand_info[nand_curr_device], + splash_screen_nand_offset, &bmp_size, + NULL, nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); + +splash_address_too_high: + printf("Error: splashimage address too high. Data overwrites U-Boot " + "and/or placed beyond DRAM boundaries.\n"); + + return -1; +} +#else +static inline int splash_load_from_nand(void) +{ + return -1; +} +#endif /* CONFIG_CMD_NAND */ + +int board_splash_screen_prepare(void) +{ + char *env_splashimage_value; + u32 bmp_load_addr; + + env_splashimage_value = getenv("splashimage"); + if (env_splashimage_value == NULL) + return -1; + + bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); + if (bmp_load_addr == 0) { + printf("Error: bad splashimage address specified\n"); + return -1; + } + + return splash_load_from_nand(bmp_load_addr); +} +#endif /* CONFIG_LCD */ + +/* + * Routine: board_init + * Description: hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], + CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); + + /* board id for Linux */ + if (get_cpu_family() == CPU_OMAP34XX) + gd->bd->bi_arch_number = MACH_TYPE_CM_T35; + else + gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#endif + + return 0; +} + +static u32 cm_t3x_rev; + +/* + * Routine: get_board_rev + * Description: read system revision + */ +u32 get_board_rev(void) +{ + if (!cm_t3x_rev) + cm_t3x_rev = cm_t3x_eeprom_get_board_rev(); + + return cm_t3x_rev; +}; + +/* + * Routine: misc_init_r + * Description: display die ID + */ +int misc_init_r(void) +{ + u32 board_rev = get_board_rev(); + u32 rev_major = board_rev / 100; + u32 rev_minor = board_rev - (rev_major * 100); + + if ((rev_minor / 10) * 10 == rev_minor) + rev_minor = rev_minor / 10; + + printf("PCB: %u.%u\n", rev_major, rev_minor); + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +static void cm_t3x_set_common_muxconf(void) +{ + /* SDRC */ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ + + /* GPMC */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ + + /* SB-T35 Ethernet */ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ + + /* DVI enable */ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ + + /* CM-T3x Ethernet */ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ + MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ + MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ + + /* DSS */ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ + + /* serial interface */ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ + + /* mUSB */ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ + + /* USB EHCI */ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ + + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ + + /* SB_T35_USB_HUB_RESET_GPIO */ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ + + /* I2C1 */ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ + /* I2C2 */ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ + /* I2C3 */ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ + + /* control and debug */ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ + + /* MMC1 */ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ +} + +static void cm_t35_set_muxconf(void) +{ + /* DSS */ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ + + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ + + /* MMC1 */ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ +} + +static void cm_t3730_set_muxconf(void) +{ + /* DSS */ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ + + MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ + MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ + MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ + MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ + MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ +} + +void set_muxconf_regs(void) +{ + cm_t3x_set_common_muxconf(); + + if (get_cpu_family() == CPU_OMAP34XX) + cm_t35_set_muxconf(); + else + cm_t3730_set_muxconf(); +} + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_getcd(struct mmc *mmc) +{ + u8 val; + + if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) + return -1; + + return !(val & 1); +} + +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, -1, 59); +} +#endif + +/* + * Routine: setup_net_chip_gmpc + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip_gmpc(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], + CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], + SB_T35_SMC911X_BASE, GPMC_SIZE_16M); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); +} + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C +/* + * Routine: reset_net_chip + * Description: reset the Ethernet controller via TPS65930 GPIO + */ +static void reset_net_chip(void) +{ + /* Set GPIO1 of TPS65930 as output */ + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, + 0x02); + /* Send a pulse on the GPIO pin */ + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, + 0x02); + udelay(1); + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, + 0x02); + mdelay(40); + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, + 0x02); + mdelay(1); +} +#else +static inline void reset_net_chip(void) {} +#endif + +#ifdef CONFIG_SMC911X +/* + * Routine: handle_mac_address + * Description: prepare MAC address for on-board Ethernet. + */ +static int handle_mac_address(void) +{ + unsigned char enetaddr[6]; + int rc; + + rc = eth_getenv_enetaddr("ethaddr", enetaddr); + if (rc) + return 0; + + rc = cm_t3x_eeprom_read_mac_addr(enetaddr); + if (rc) + return rc; + + if (!is_valid_ether_addr(enetaddr)) + return -1; + + return eth_setenv_enetaddr("ethaddr", enetaddr); +} + + +/* + * Routine: board_eth_init + * Description: initialize module and base-board Ethernet chips + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0, rc1 = 0; + + setup_net_chip_gmpc(); + reset_net_chip(); + + rc1 = handle_mac_address(); + if (rc1) + printf("No MAC address found! "); + + rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); + if (rc1 > 0) + rc++; + + rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); + if (rc1 > 0) + rc++; + + return rc; +} +#endif + +void __weak get_board_serial(struct tag_serialnr *serialnr) +{ + /* + * This corresponds to what happens when we can communicate with the + * eeprom but don't get a valid board serial value. + */ + serialnr->low = 0; + serialnr->high = 0; +}; + +#ifdef CONFIG_USB_EHCI_OMAP +struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, +}; + +#define SB_T35_USB_HUB_RESET_GPIO 167 +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + u8 val; + int offset; + + if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { + printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", + SB_T35_USB_HUB_RESET_GPIO); + return -1; + } + + gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); + udelay(10); + gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); + udelay(1000); + + offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; + twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); + /* Set GPIO6 and GPIO7 of TPS65930 as output */ + val |= 0xC0; + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); + offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; + /* Take both PHYs out of reset */ + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); + udelay(1); + + return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(void) +{ + return omap_ehci_hcd_stop(); +} + +#endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/compulab/cm_t35/display.c b/board/compulab/cm_t35/display.c new file mode 100644 index 0000000..adc4853 --- /dev/null +++ b/board/compulab/cm_t35/display.c @@ -0,0 +1,420 @@ +/* + * (C) Copyright 2012 - 2013 CompuLab, Ltd. + * + * Authors: Nikita Kiryanov + * + * Parsing code based on linux/drivers/video/pxafb.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum display_type { + NONE, + DVI, + DVI_CUSTOM, +}; + +#define CMAP_ADDR 0x80100000 + +/* + * The frame buffer is allocated before we have the chance to parse user input. + * To make sure enough memory is allocated for all resolutions, we define + * vl_{col | row} to the maximal resolution supported by OMAP3. + */ +vidinfo_t panel_info = { + .vl_col = 1400, + .vl_row = 1050, + .vl_bpix = LCD_BPP, + .cmap = (ushort *)CMAP_ADDR, +}; + +static struct panel_config panel_cfg; +static enum display_type lcd_def; + +/* + * A note on DVI presets; + * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can + * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to + * support two BMP types with one setting. + */ +static const struct panel_config preset_dvi_640X480 = { + .lcd_size = PANEL_LCD_SIZE(640, 480), + .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96), + .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2), + .divisor = 12 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_800X600 = { + .lcd_size = PANEL_LCD_SIZE(800, 600), + .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128), + .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4), + .divisor = 8 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1024X768 = { + .lcd_size = PANEL_LCD_SIZE(1024, 768), + .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136), + .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6), + .divisor = 5 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1152X864 = { + .lcd_size = PANEL_LCD_SIZE(1152, 864), + .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128), + .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3), + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1280X960 = { + .lcd_size = PANEL_LCD_SIZE(1280, 960), + .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112), + .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3), + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +static const struct panel_config preset_dvi_1280X1024 = { + .lcd_size = PANEL_LCD_SIZE(1280, 1024), + .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112), + .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3), + .divisor = 3 | (1 << 16), + .data_lines = LCD_INTERFACE_24_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + +/* + * set_resolution_params() + * + * Due to usage of multiple display related APIs resolution data is located in + * more than one place. This function updates them all. + */ +static void set_resolution_params(int x, int y) +{ + panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y); + panel_info.vl_col = x; + panel_info.vl_row = y; + lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; +} + +static void set_preset(const struct panel_config preset, int x_res, int y_res) +{ + panel_cfg = preset; + set_resolution_params(x_res, y_res); +} + +static enum display_type set_dvi_preset(const struct panel_config preset, + int x_res, int y_res) +{ + set_preset(preset, x_res, y_res); + return DVI; +} + +/* + * parse_mode() - parse the mode parameter of custom lcd settings + * + * @mode: x + * + * Returns -1 on error, 0 on success. + */ +static int parse_mode(const char *mode) +{ + unsigned int modelen = strlen(mode); + int res_specified = 0; + unsigned int xres = 0, yres = 0; + int yres_specified = 0; + int i; + + for (i = modelen - 1; i >= 0; i--) { + switch (mode[i]) { + case 'x': + if (!yres_specified) { + yres = simple_strtoul(&mode[i + 1], NULL, 0); + yres_specified = 1; + } else { + goto done_parsing; + } + + break; + case '0' ... '9': + break; + default: + goto done_parsing; + } + } + + if (i < 0 && yres_specified) { + xres = simple_strtoul(mode, NULL, 0); + res_specified = 1; + } + +done_parsing: + if (res_specified) { + set_resolution_params(xres, yres); + } else { + printf("LCD: invalid mode: %s\n", mode); + return -1; + } + + return 0; +} + +#define PIXEL_CLK_NUMERATOR (26 * 432 / 39) +/* + * parse_pixclock() - Parse the pixclock parameter of custom lcd settings + * + * @pixclock: the desired pixel clock + * + * Returns -1 on error, 0 on success. + * + * Handling the pixel_clock: + * + * Pixel clock is defined in the OMAP35x TRM as follows: + * pixel_clock = + * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) / + * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] * + * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1)) + * + * In practice, this means that in order to set the + * divisor for the desired pixel clock one needs to + * solve the following equation: + * + * 26 * 432 / (39 * ) = DSS.DISPC_DIVISOR[6:0] + * + * NOTE: the explicit equation above is reduced. Do not + * try to infer anything from these numbers. + */ +static int parse_pixclock(char *pixclock) +{ + int divisor, pixclock_val; + char *pixclk_start = pixclock; + + pixclock_val = simple_strtoul(pixclock, &pixclock, 10); + divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val); + /* 0 and 1 are illegal values for PCD */ + if (divisor <= 1) + divisor = 2; + + panel_cfg.divisor = divisor | (1 << 16); + if (pixclock[0] != '\0') { + printf("LCD: invalid value for pixclock:%s\n", pixclk_start); + return -1; + } + + return 0; +} + +/* + * parse_setting() - parse a single setting of custom lcd parameters + * + * @setting: The custom lcd setting : + * + * Returns -1 on failure, 0 on success. + */ +static int parse_setting(char *setting) +{ + int num_val; + char *setting_start = setting; + + if (!strncmp(setting, "mode:", 5)) { + return parse_mode(setting + 5); + } else if (!strncmp(setting, "pixclock:", 9)) { + return parse_pixclock(setting + 9); + } else if (!strncmp(setting, "left:", 5)) { + num_val = simple_strtoul(setting + 5, &setting, 0); + panel_cfg.timing_h |= DSS_HBP(num_val); + } else if (!strncmp(setting, "right:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_h |= DSS_HFP(num_val); + } else if (!strncmp(setting, "upper:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_v |= DSS_VBP(num_val); + } else if (!strncmp(setting, "lower:", 6)) { + num_val = simple_strtoul(setting + 6, &setting, 0); + panel_cfg.timing_v |= DSS_VFP(num_val); + } else if (!strncmp(setting, "hsynclen:", 9)) { + num_val = simple_strtoul(setting + 9, &setting, 0); + panel_cfg.timing_h |= DSS_HSW(num_val); + } else if (!strncmp(setting, "vsynclen:", 9)) { + num_val = simple_strtoul(setting + 9, &setting, 0); + panel_cfg.timing_v |= DSS_VSW(num_val); + } else if (!strncmp(setting, "hsync:", 6)) { + if (simple_strtoul(setting + 6, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IHS; + else + panel_cfg.pol_freq &= ~DSS_IHS; + } else if (!strncmp(setting, "vsync:", 6)) { + if (simple_strtoul(setting + 6, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IVS; + else + panel_cfg.pol_freq &= ~DSS_IVS; + } else if (!strncmp(setting, "outputen:", 9)) { + if (simple_strtoul(setting + 9, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IEO; + else + panel_cfg.pol_freq &= ~DSS_IEO; + } else if (!strncmp(setting, "pixclockpol:", 12)) { + if (simple_strtoul(setting + 12, &setting, 0) == 0) + panel_cfg.pol_freq |= DSS_IPC; + else + panel_cfg.pol_freq &= ~DSS_IPC; + } else if (!strncmp(setting, "active", 6)) { + panel_cfg.panel_type = ACTIVE_DISPLAY; + return 0; /* Avoid sanity check below */ + } else if (!strncmp(setting, "passive", 7)) { + panel_cfg.panel_type = PASSIVE_DISPLAY; + return 0; /* Avoid sanity check below */ + } else if (!strncmp(setting, "display:", 8)) { + if (!strncmp(setting + 8, "dvi", 3)) { + lcd_def = DVI_CUSTOM; + return 0; /* Avoid sanity check below */ + } + } else { + printf("LCD: unknown option %s\n", setting_start); + return -1; + } + + if (setting[0] != '\0') { + printf("LCD: invalid value for %s\n", setting_start); + return -1; + } + + return 0; +} + +/* + * env_parse_customlcd() - parse custom lcd params from an environment variable. + * + * @custom_lcd_params: The environment variable containing the lcd params. + * + * Returns -1 on failure, 0 on success. + */ +static int parse_customlcd(char *custom_lcd_params) +{ + char params_cpy[160]; + char *setting; + + strncpy(params_cpy, custom_lcd_params, 160); + setting = strtok(params_cpy, ","); + while (setting) { + if (parse_setting(setting) < 0) + return -1; + + setting = strtok(NULL, ","); + } + + /* Currently we don't support changing this via custom lcd params */ + panel_cfg.data_lines = LCD_INTERFACE_24_BIT; + panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */ + + return 0; +} + +/* + * env_parse_displaytype() - parse display type. + * + * Parses the environment variable "displaytype", which contains the + * name of the display type or preset, in which case it applies its + * configurations. + * + * Returns the type of display that was specified. + */ +static enum display_type env_parse_displaytype(char *displaytype) +{ + if (!strncmp(displaytype, "dvi640x480", 10)) + return set_dvi_preset(preset_dvi_640X480, 640, 480); + else if (!strncmp(displaytype, "dvi800x600", 10)) + return set_dvi_preset(preset_dvi_800X600, 800, 600); + else if (!strncmp(displaytype, "dvi1024x768", 11)) + return set_dvi_preset(preset_dvi_1024X768, 1024, 768); + else if (!strncmp(displaytype, "dvi1152x864", 11)) + return set_dvi_preset(preset_dvi_1152X864, 1152, 864); + else if (!strncmp(displaytype, "dvi1280x960", 11)) + return set_dvi_preset(preset_dvi_1280X960, 1280, 960); + else if (!strncmp(displaytype, "dvi1280x1024", 12)) + return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024); + + return NONE; +} + +void lcd_ctrl_init(void *lcdbase) +{ + struct prcm *prcm = (struct prcm *)PRCM_BASE; + char *custom_lcd; + char *displaytype = getenv("displaytype"); + + if (displaytype == NULL) + return; + + lcd_def = env_parse_displaytype(displaytype); + /* If we did not recognize the preset, check if it's an env variable */ + if (lcd_def == NONE) { + custom_lcd = getenv(displaytype); + if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0) + return; + } + + panel_cfg.frame_buffer = lcdbase; + omap3_dss_panel_config(&panel_cfg); + /* + * Pixel clock is defined with many divisions and only few + * multiplications of the system clock. Since DSS FCLK divisor is set + * to 16 by default, we need to set it to a smaller value, like 3 + * (chosen via trial and error). + */ + clrsetbits_le32(&prcm->clksel_dss, 0xF, 3); +} + +void lcd_enable(void) +{ + if (lcd_def == DVI || lcd_def == DVI_CUSTOM) { + gpio_direction_output(54, 0); /* Turn on DVI */ + omap3_dss_enable(); + } +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {} diff --git a/board/compulab/cm_t35/eeprom.c b/board/compulab/cm_t35/eeprom.c new file mode 100644 index 0000000..b0af103 --- /dev/null +++ b/board/compulab/cm_t35/eeprom.c @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2011 CompuLab, Ltd. + * + * Authors: Nikita Kiryanov + * Igor Grinberg + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include +#include + +#define EEPROM_LAYOUT_VER_OFFSET 44 +#define BOARD_SERIAL_OFFSET 20 +#define BOARD_SERIAL_OFFSET_LEGACY 8 +#define BOARD_REV_OFFSET 0 +#define BOARD_REV_OFFSET_LEGACY 6 +#define BOARD_REV_SIZE 2 +#define MAC_ADDR_OFFSET 4 +#define MAC_ADDR_OFFSET_LEGACY 0 + +#define LAYOUT_INVALID 0 +#define LAYOUT_LEGACY 0xff + +static int eeprom_layout; /* Implicitly LAYOUT_INVALID */ + +static int cm_t3x_eeprom_read(uint offset, uchar *buf, int len) +{ + return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len); +} + +static int eeprom_setup_layout(void) +{ + int res; + + if (eeprom_layout != LAYOUT_INVALID) + return 0; + + res = cm_t3x_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, + (uchar *)&eeprom_layout, 1); + if (res) { + eeprom_layout = LAYOUT_INVALID; + return res; + } + + if (eeprom_layout == 0 || eeprom_layout >= 0x20) + eeprom_layout = LAYOUT_LEGACY; + + return 0; +} + +void get_board_serial(struct tag_serialnr *serialnr) +{ + u32 serial[2]; + uint offset; + + memset(serialnr, 0, sizeof(*serialnr)); + if (eeprom_setup_layout()) + return; + + offset = (eeprom_layout != LAYOUT_LEGACY) ? + BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY; + if (cm_t3x_eeprom_read(offset, (uchar *)serial, 8)) + return; + + if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) { + serialnr->low = serial[0]; + serialnr->high = serial[1]; + } +} + +/* + * Routine: cm_t3x_eeprom_read_mac_addr + * Description: read mac address and store it in buf. + */ +int cm_t3x_eeprom_read_mac_addr(uchar *buf) +{ + uint offset; + + if (eeprom_setup_layout()) + return 0; + + offset = (eeprom_layout != LAYOUT_LEGACY) ? + MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY; + return cm_t3x_eeprom_read(offset, buf, 6); +} + +/* + * Routine: cm_t3x_eeprom_get_board_rev + * Description: read system revision from eeprom + */ +u32 cm_t3x_eeprom_get_board_rev(void) +{ + u32 rev = 0; + char str[5]; /* Legacy representation can contain at most 4 digits */ + uint offset = BOARD_REV_OFFSET_LEGACY; + + if (eeprom_setup_layout()) + return 0; + + if (eeprom_layout != LAYOUT_LEGACY) + offset = BOARD_REV_OFFSET; + + if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) + return 0; + + /* + * Convert legacy syntactic representation to semantic + * representation. i.e. for rev 1.00: 0x100 --> 0x64 + */ + if (eeprom_layout == LAYOUT_LEGACY) { + sprintf(str, "%x", rev); + rev = simple_strtoul(str, NULL, 10); + } + + return rev; +}; diff --git a/board/compulab/cm_t35/eeprom.h b/board/compulab/cm_t35/eeprom.h new file mode 100644 index 0000000..38824d1 --- /dev/null +++ b/board/compulab/cm_t35/eeprom.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2011 CompuLab, Ltd. + * + * Authors: Nikita Kiryanov + * Igor Grinberg + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#ifndef _EEPROM_ +#define _EEPROM_ + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C +int cm_t3x_eeprom_read_mac_addr(uchar *buf); +u32 cm_t3x_eeprom_get_board_rev(void); +#else +static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf) +{ + return 1; +} +static inline u32 cm_t3x_eeprom_get_board_rev(void) +{ + return 0; +} +#endif + +#endif diff --git a/board/compulab/cm_t35/leds.c b/board/compulab/cm_t35/leds.c new file mode 100644 index 0000000..dcae135 --- /dev/null +++ b/board/compulab/cm_t35/leds.c @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2011 - 2013 CompuLab, Ltd. + * + * Author: Igor Grinberg + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include +#include +#include + +static unsigned int leds[] = { GREEN_LED_GPIO }; + +void __led_init(led_id_t mask, int state) +{ + if (gpio_request(leds[mask], "") != 0) { + printf("%s: failed requesting GPIO%u\n", __func__, leds[mask]); + return; + } + + gpio_direction_output(leds[mask], 0); +} + +void __led_set(led_id_t mask, int state) +{ + gpio_set_value(leds[mask], state == STATUS_LED_ON); +} + +void __led_toggle(led_id_t mask) +{ + gpio_set_value(leds[mask], !gpio_get_value(leds[mask])); +} diff --git a/boards.cfg b/boards.cfg index 06ba979..63d0ebe 100644 --- a/boards.cfg +++ b/boards.cfg @@ -268,10 +268,10 @@ nitrogen6s arm armv7 nitrogen6x boundar nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 wandboard_dl arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 wandboard_solo arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 -cm_t35 arm armv7 cm_t35 - omap3 omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 dig297 arm armv7 dig297 comelit omap3 +cm_t35 arm armv7 cm_t35 compulab omap3 igep0020 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND igep0020_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND -- cgit v0.10.2 From 26528632aa16ba8d6368fa872f9ea1ad9973bf86 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Mon, 22 Apr 2013 01:06:54 +0000 Subject: MAINTAINERS: fix the cm-t35 board name "cm-t35" in U-Boot source code is called "cm_t35". Make the change "cm-t35" -> "cm_t35" for better greppability. Signed-off-by: Igor Grinberg diff --git a/MAINTAINERS b/MAINTAINERS index a46803c..d86f0f1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -684,7 +684,7 @@ Simon Guinot Igor Grinberg - cm-t35 ARM ARMV7 (OMAP3xx Soc) + cm_t35 ARM ARMV7 (OMAP3xx Soc) Stefan Herbrechtsmeier -- cgit v0.10.2 From 0b800a6b267de24466ca5a463db6497d7362f128 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Mon, 22 Apr 2013 01:06:55 +0000 Subject: cm-t35: update config file Several minor updates to the cm-t35 config file. Signed-off-by: Igor Grinberg Tested-by: Nikita Kiryanov diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 726714d..c6e357a 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -135,12 +135,12 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ - "1920k(u-boot),128k(u-boot-env),"\ + "1920k(u-boot),256k(u-boot-env),"\ "4m(kernel),-(fs)" #define CONFIG_CMD_I2C /* I2C serial bus support */ @@ -182,14 +182,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ - /* partition */ - /* Environment information */ #define CONFIG_BOOTDELAY 10 #define CONFIG_ZERO_BOOTDELAY_CHECK @@ -204,9 +196,9 @@ "defaultdisplay=dvi\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ + "mmcrootfstype=ext4 rootwait\0" \ "nandroot=/dev/mtdblock4 rw\0" \ - "nandrootfstype=jffs2\0" \ + "nandrootfstype=ubifs\0" \ "mmcargs=setenv bootargs console=${console} " \ "mpurate=${mpurate} " \ "vram=${vram} " \ @@ -232,7 +224,7 @@ "bootm ${loadaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ + "nand read ${loadaddr} 2a0000 400000; " \ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ -- cgit v0.10.2 From 81ac7e51ccf2984e9c0964a883d6b7e8fe875aad Mon Sep 17 00:00:00 2001 From: Eric Benard Date: Mon, 22 Apr 2013 05:54:59 +0000 Subject: da850: provide davinci_enable_uart0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this is needed to bring UART0 out of reset but this function currently only exists for dm644x/355/365/646x when da850 (at least am1808 also need it). Signed-off-by: Eric Bénard diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index ff2e2e3..127beb8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -32,6 +32,14 @@ #include #include +void davinci_enable_uart0(void) +{ + lpsc_on(DAVINCI_LPSC_UART0); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x00006001; +} + #if defined(CONFIG_SYS_DA850_PLL_INIT) void da850_waitloop(unsigned long loopcnt) { diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 6eed6c9..a9017e4 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -346,6 +346,8 @@ void davinci_errata_workarounds(void); #define PSC_PSC0_MODULE_ID_CNT 16 #define PSC_PSC1_MODULE_ID_CNT 32 +#define UART0_PWREMU_MGMT (0x01c42030) + struct davinci_psc_regs { dv_reg revid; dv_reg rsvd0[71]; -- cgit v0.10.2 From 34fa07063a7f5fc437bcaa71156182bb3bf2f516 Mon Sep 17 00:00:00 2001 From: Eric Benard Date: Mon, 22 Apr 2013 05:55:00 +0000 Subject: davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit these variables are curently defined in several config files but the driver doesn't use them and defaults to hardcoded values in nand_defs.h It's interesting to be able to change this hardcoded valude when the hardware is not using the default adress signals to drive ALE and CLE and two configuration defines already exist for this purpose so use them. Signed-off-by: Eric Bénard diff --git a/arch/arm/include/asm/arch-davinci/nand_defs.h b/arch/arm/include/asm/arch-davinci/nand_defs.h index 10f3a39..4a30813 100644 --- a/arch/arm/include/asm/arch-davinci/nand_defs.h +++ b/arch/arm/include/asm/arch-davinci/nand_defs.h @@ -36,6 +36,15 @@ #define MASK_ALE 0x08 #endif +#ifdef CONFIG_SYS_NAND_MASK_CLE +#undef MASK_CLE +#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE +#endif +#ifdef CONFIG_SYS_NAND_MASK_ALE +#undef MASK_ALE +#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE +#endif + #define NAND_READ_START 0x00 #define NAND_READ_END 0x30 #define NAND_STATUS 0x70 diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index f7ac256..198892b 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -109,8 +109,8 @@ #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_CLE_MASK 0x10 -#define CONFIG_SYS_ALE_MASK 0x8 +#define CONFIG_SYS_NAND_MASK_CLE 0x10 +#define CONFIG_SYS_NAND_MASK_ALE 0x8 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #endif diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 583568d..c420967 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -199,8 +199,8 @@ #define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_CLE_MASK 0x10 -#define CONFIG_SYS_ALE_MASK 0x8 +#define CONFIG_SYS_NAND_MASK_CLE 0x10 +#define CONFIG_SYS_NAND_MASK_ALE 0x8 #undef CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index 2d63b67..97bc972 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -118,8 +118,8 @@ #define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_CLE_MASK 0x10 -#define CONFIG_SYS_ALE_MASK 0x8 +#define CONFIG_SYS_NAND_MASK_CLE 0x10 +#define CONFIG_SYS_NAND_MASK_ALE 0x8 #undef CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h index d6371fc..cabc06e 100644 --- a/include/configs/tnetv107x_evm.h +++ b/include/configs/tnetv107x_evm.h @@ -82,8 +82,8 @@ #define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE -#define CONFIG_SYS_CLE_MASK 0x10 -#define CONFIG_SYS_ALE_MASK 0x8 +#define CONFIG_SYS_NAND_MASK_CLE 0x10 +#define CONFIG_SYS_NAND_MASK_ALE 0x8 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_PARTITIONS #define CONFIG_CMD_MTDPARTS -- cgit v0.10.2 From 30bba0175122150c330ff95132e048a39bf978eb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 25 Apr 2013 16:46:04 -0400 Subject: am33xx: Fix warning with CONFIG_DISPLAY_CPUINFO The arm_freq and ddr_freq variables are unused, so remove. Fixup whitespace slightly while in here. Reviewed-by: Peter Korsgaard Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 5fd8b47..ac049ac 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -92,7 +92,6 @@ u32 get_sysboot_value(void) int print_cpuinfo(void) { char *cpu_s, *sec_s; - int arm_freq, ddr_freq; switch (get_cpu_type()) { case AM335X: @@ -123,10 +122,7 @@ int print_cpuinfo(void) sec_s = "?"; } - printf("%s-%s rev %d\n", - cpu_s, sec_s, get_cpu_rev()); - - /* TODO: Print ARM and DDR frequencies */ + printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev()); return 0; } -- cgit v0.10.2 From 76db5b8f59d0c9c9eb73f1595f8fbc557e7a16eb Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Wed, 24 Apr 2013 00:41:21 +0000 Subject: ARM: OMAP: Make omap_boot_parameters common across socs omap_boot_parameters is same and defined for each soc. So move this to a common place to reuse it across socs. Signed-off-by: Sricharan R diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index d28f9a8..7e3bb9c 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -35,29 +35,4 @@ #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #endif - -/* ROM code defines */ -/* Boot device */ -#define BOOT_DEVICE_MASK 0xFF -#define BOOT_DEVICE_OFFSET 0x8 -#define DEV_DESC_PTR_OFFSET 0x4 -#define DEV_DATA_PTR_OFFSET 0x18 -#define BOOT_MODE_OFFSET 0x8 -#define RESET_REASON_OFFSET 0x9 -#define CH_FLAGS_OFFSET 0xA - -#define CH_FLAGS_CHSETTINGS (0x1 << 0) -#define CH_FLAGS_CHRAM (0x1 << 1) -#define CH_FLAGS_CHFLASH (0x1 << 2) -#define CH_FLAGS_CHMMCSD (0x1 << 3) - -#ifndef __ASSEMBLY__ -struct omap_boot_parameters { - char *boot_message; - unsigned int mem_boot_descriptor; - unsigned char omap_bootdevice; - unsigned char reset_reason; - unsigned char ch_flags; -}; -#endif #endif diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index ad984da..9ad1e82 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -155,28 +155,4 @@ struct s32ktimer { #define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) #define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) -/* ROM code defines */ -/* Boot device */ -#define BOOT_DEVICE_MASK 0xFF -#define BOOT_DEVICE_OFFSET 0x8 -#define DEV_DESC_PTR_OFFSET 0x4 -#define DEV_DATA_PTR_OFFSET 0x18 -#define BOOT_MODE_OFFSET 0x8 -#define RESET_REASON_OFFSET 0x9 -#define CH_FLAGS_OFFSET 0xA - -#define CH_FLAGS_CHSETTINGS (0x1 << 0) -#define CH_FLAGS_CHRAM (0x1 << 1) -#define CH_FLAGS_CHFLASH (0x1 << 2) -#define CH_FLAGS_CHMMCSD (0x1 << 3) - -#ifndef __ASSEMBLY__ -struct omap_boot_parameters { - char *boot_message; - unsigned int mem_boot_descriptor; - unsigned char omap_bootdevice; - unsigned char reset_reason; - unsigned char ch_flags; -}; -#endif #endif diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 887fcaa..3bf5afa 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -214,21 +214,6 @@ struct s32ktimer { #define OMAP4460_ES1_0 0x44600100 #define OMAP4460_ES1_1 0x44600110 -/* ROM code defines */ -/* Boot device */ -#define BOOT_DEVICE_MASK 0xFF -#define BOOT_DEVICE_OFFSET 0x8 -#define DEV_DESC_PTR_OFFSET 0x4 -#define DEV_DATA_PTR_OFFSET 0x18 -#define BOOT_MODE_OFFSET 0x8 -#define RESET_REASON_OFFSET 0x9 -#define CH_FLAGS_OFFSET 0xA - -#define CH_FLAGS_CHSETTINGS (0x1 << 0) -#define CH_FLAGS_CHRAM (0x1 << 1) -#define CH_FLAGS_CHFLASH (0x1 << 2) -#define CH_FLAGS_CHMMCSD (0x1 << 3) - /* CONTROL_SRCOMP_XXX_SIDE */ #define OVERRIDE_XS_SHIFT 30 #define OVERRIDE_XS_MASK (1 << 30) @@ -249,14 +234,6 @@ struct srcomp_params { s8 multiply_factor; }; -struct omap_boot_parameters { - char *boot_message; - unsigned int mem_boot_descriptor; - unsigned char omap_bootdevice; - unsigned char reset_reason; - unsigned char ch_flags; -}; - struct ctrl_ioregs { u32 ctrl_ddrch; u32 ctrl_lpddr2ch; diff --git a/arch/arm/include/asm/omap_boot.h b/arch/arm/include/asm/omap_boot.h new file mode 100644 index 0000000..87a9530 --- /dev/null +++ b/arch/arm/include/asm/omap_boot.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2013 + * Texas Instruments, + * + * Sricharan R + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* ROM code defines */ +/* Boot device */ +#define BOOT_DEVICE_MASK 0xFF +#define BOOT_DEVICE_OFFSET 0x8 +#define DEV_DESC_PTR_OFFSET 0x4 +#define DEV_DATA_PTR_OFFSET 0x18 +#define BOOT_MODE_OFFSET 0x8 +#define RESET_REASON_OFFSET 0x9 +#define CH_FLAGS_OFFSET 0xA + +#define CH_FLAGS_CHSETTINGS (0x1 << 0) +#define CH_FLAGS_CHRAM (0x1 << 1) +#define CH_FLAGS_CHFLASH (0x1 << 2) +#define CH_FLAGS_CHMMCSD (0x1 << 3) + +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + char *boot_message; + unsigned int mem_boot_descriptor; + unsigned char omap_bootdevice; + unsigned char reset_reason; + unsigned char ch_flags; +}; +#endif -- cgit v0.10.2 From f92f2277a6cadfdc703a6700593cac3d8211bf53 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Wed, 24 Apr 2013 00:41:22 +0000 Subject: ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow. Signed-off-by: Sricharan R diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c index 53f6063..0ddf35f 100644 --- a/arch/arm/cpu/armv7/omap4/emif.c +++ b/arch/arm/cpu/armv7/omap4/emif.c @@ -31,8 +31,8 @@ #include #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM; -u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN; +u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM; +u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN; #endif #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 04977b4..06a2fc8 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -40,7 +40,7 @@ struct dplls const **dplls_data = struct vcores_data const **omap_vcores = (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; struct omap_sys_ctrl_regs const **ctrl = - (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL; + (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; /* * The M & N values in the following tables are created using the diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 2db517b..81f5a48 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -34,10 +34,11 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; +u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; static const struct gpio_bank gpio_bank_44xx[6] = { { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX }, diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c index 3f37abd..b4c1319 100644 --- a/arch/arm/cpu/armv7/omap5/emif.c +++ b/arch/arm/cpu/armv7/omap5/emif.c @@ -32,8 +32,8 @@ #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) -static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM; -static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN; +static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM; +static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN; #endif #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 5698876..604fa42 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -41,7 +41,7 @@ struct dplls const **dplls_data = struct vcores_data const **omap_vcores = (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; struct omap_sys_ctrl_regs const **ctrl = - (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL; + (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; /* OPP HIGH FREQUENCY for ES2.0 */ static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index d29df78..e192fea 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -37,10 +37,11 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV; +u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; static struct gpio_bank gpio_bank_54xx[6] = { { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX }, diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 9ad1e82..e9a6ffe 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -143,16 +143,4 @@ struct s32ktimer { #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4030D000 -/* Temporary SRAM stack used while low level init is done */ -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START -/* SRAM scratch space entries */ -#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR -#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) -#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) -#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) -#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) -#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) -#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) -#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) - #endif diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 3bf5afa..4f43a90 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -191,19 +191,6 @@ struct s32ktimer { /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START -/* - * SRAM scratch space entries - */ -#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR -#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) -#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) -#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) -#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) -#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) -#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) - /* Silicon revisions */ #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF #define OMAP4430_ES1_0 0x44300100 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 6d377d5..837b69f 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -584,4 +584,18 @@ static inline u32 omap_revision(void) /* DRA7XX */ #define DRA752_ES1_0 0x07520100 + +/* + * SRAM scratch space entries + */ +#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR +#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) +#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) +#define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) +#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) +#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) +#define OMAP_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) #endif /* _OMAP_COMMON_H_ */ -- cgit v0.10.2 From fda06812a068f916f64d9d1b3d1730e8213195b3 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Wed, 24 Apr 2013 00:41:23 +0000 Subject: ARM: OMAP: Correct save_boot_params and replace with 'C' function Currently save_boot_params saves the boot parameters passed from romcode. But this is not stored in a writable location consistently. So the current code would not work for a 'XIP' boot. Change this by saving the boot parameters in 'gd' which is always writable. Also add a 'C' function instead of an assembly code that is more readable. Signed-off-by: Sricharan R diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 70d16a8..c710784 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -101,11 +101,6 @@ void omap_rev_string(void) } #ifdef CONFIG_SPL_BUILD -static void init_boot_params(void) -{ - boot_params_ptr = (u32 *) &boot_params; -} - void spl_display_print(void) { omap_rev_string(); @@ -116,6 +111,42 @@ void __weak srcomp_enable(void) { } +static void save_omap_boot_params(void) +{ + u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); + u8 boot_device; + u32 dev_desc, dev_data; + + if ((rom_params < NON_SECURE_SRAM_START) || + (rom_params > NON_SECURE_SRAM_END)) + return; + + /* + * rom_params can be type casted to omap_boot_parameters and + * used. But it not correct to assume that romcode structure + * encoding would be same as u-boot. So use the defined offsets. + */ + gd->arch.omap_boot_params.omap_bootdevice = boot_device = + *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + + gd->arch.omap_boot_params.ch_flags = + *((u8 *)(rom_params + CH_FLAGS_OFFSET)); + + if ((boot_device >= MMC_BOOT_DEVICES_START) && + (boot_device <= MMC_BOOT_DEVICES_END)) { + if ((omap_hw_init_context() == + OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) { + gd->arch.omap_boot_params.omap_bootmode = + *((u8 *)(rom_params + BOOT_MODE_OFFSET)); + } else { + dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET)); + dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET)); + gd->arch.omap_boot_params.omap_bootmode = + *((u32 *)(dev_data + BOOT_MODE_OFFSET)); + } + } +} + /* * Routine: s_init * Description: Does early system init of watchdog, muxing, andclocks @@ -132,6 +163,14 @@ void __weak srcomp_enable(void) */ void s_init(void) { + /* + * Save the boot parameters passed from romcode. + * We cannot delay the saving further than this, + * to prevent overwrites. + */ +#ifdef CONFIG_SPL_BUILD + save_omap_boot_params(); +#endif init_omap_revision(); hw_data_init(); @@ -156,7 +195,6 @@ void s_init(void) /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); - init_boot_params(); #endif } diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 37ac0da..7611d0a 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -24,6 +24,10 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#ifdef CONFIG_OMAP +#include +#endif + /* Architecture-specific global data */ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) @@ -51,6 +55,10 @@ struct arch_global_data { unsigned long tlb_addr; unsigned long tlb_size; #endif + +#ifdef CONFIG_OMAP + struct omap_boot_parameters omap_boot_params; +#endif }; #include diff --git a/arch/arm/include/asm/omap_boot.h b/arch/arm/include/asm/omap_boot.h index 87a9530..a803965 100644 --- a/arch/arm/include/asm/omap_boot.h +++ b/arch/arm/include/asm/omap_boot.h @@ -45,5 +45,6 @@ struct omap_boot_parameters { unsigned char omap_bootdevice; unsigned char reset_reason; unsigned char ch_flags; + unsigned long omap_bootmode; }; #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 837b69f..eebc9c7 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -597,5 +597,7 @@ static inline u32 omap_revision(void) #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) -#define OMAP_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) +#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28) + #endif /* _OMAP_COMMON_H_ */ -- cgit v0.10.2 From 4a0eb75752167bef51993307a10677295cef315b Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Wed, 24 Apr 2013 00:41:24 +0000 Subject: ARM: OMAP: Cleanup boot parameters usage The boot parameters are read from individual variables assigned for each of them. This been corrected and now they are stored as a part of the global data 'gd' structure. So read them from 'gd' instead. Signed-off-by: Sricharan R [trini: Add igep0033 hunk] Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 0d45528..0a15aa4 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -37,7 +37,13 @@ ENTRY(lowlevel_init) */ ldr sp, =CONFIG_SYS_INIT_SP_ADDR bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - +#ifdef CONFIG_SPL_BUILD + ldr r8, =gdata +#else + sub sp, #GD_SIZE + bic sp, sp, #7 + mov r8, sp +#endif /* * Save the old lr(passed in ip) and the current lr to stack */ diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 24cbe2d..bff7e9c 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -23,31 +23,17 @@ #include #include -/* - * This is used to verify if the configuration header - * was executed by rom code prior to control of transfer - * to the bootloader. SPL is responsible for saving and - * passing the boot_params pointer to the u-boot. - */ -struct omap_boot_parameters boot_params __attribute__ ((section(".data"))); +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD -/* - * We use static variables because global data is not ready yet. - * Initialized data is available in SPL right from the beginning. - * We would not typically need to save these parameters in regular - * U-Boot. This is needed only in SPL at the moment. - */ -u32 omap_bootmode = MMCSD_MODE_FAT; - u32 spl_boot_device(void) { - return (u32) (boot_params.omap_bootdevice); + return (u32) (gd->arch.omap_boot_params.omap_bootdevice); } u32 spl_boot_mode(void) { - return omap_bootmode; + return gd->arch.omap_boot_params.omap_bootmode; } void spl_board_init(void) @@ -73,4 +59,15 @@ int board_mmc_init(bd_t *bis) } return 0; } + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + typedef void __noreturn (*image_entry_noargs_t)(u32 *); + image_entry_noargs_t image_entry = + (image_entry_noargs_t) spl_image->entry_point; + + debug("image entry point: 0x%X\n", spl_image->entry_point); + /* Pass the saved boot_params from rom code */ + image_entry((u32 *)&gd->arch.omap_boot_params); +} #endif diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 90b3c8a..c489536 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -28,59 +28,13 @@ #include #include +#include #include #include ENTRY(save_boot_params) - /* - * See if the rom code passed pointer is valid: - * It is not valid if it is not in non-secure SRAM - * This may happen if you are booting with the help of - * debugger - */ - ldr r2, =NON_SECURE_SRAM_START - cmp r2, r0 - bgt 1f - ldr r2, =NON_SECURE_SRAM_END - cmp r2, r0 - blt 1f - - /* - * store the boot params passed from rom code or saved - * and passed by SPL - */ - cmp r0, #0 - beq 1f - ldr r1, =boot_params + ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS str r0, [r1] -#ifdef CONFIG_SPL_BUILD - /* Store the boot device in spl_boot_device */ - ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device - and r2, #BOOT_DEVICE_MASK - ldr r3, =boot_params - strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1 - - /* - * boot mode is only valid for device that can be raw or FAT booted. - * in other cases it may be fatal to look. While platforms differ - * in the values used for each MMC slot, they are contiguous. - */ - cmp r2, #MMC_BOOT_DEVICES_START - blt 2f - cmp r2, #MMC_BOOT_DEVICES_END - bgt 2f - /* Store the boot mode (raw/FAT) in omap_bootmode */ - ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr - ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr - ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode - ldr r3, =omap_bootmode - str r2, [r3] -#endif -2: - ldrb r2, [r0, #CH_FLAGS_OFFSET] - ldr r3, =boot_params - strb r2, [r3, #CH_FLAGS_OFFSET] -1: bx lr ENDPROC(save_boot_params) diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index ac9c1f8..039a1f2 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -27,6 +27,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + struct omap_sysinfo { char *board_string; }; @@ -59,13 +61,6 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void setup_warmreset_time(void); -/* - * This is used to verify if the configuration header - * was executed by Romcode prior to control of transfer - * to the bootloader. SPL is responsible for saving and - * passing this to the u-boot. - */ -extern struct omap_boot_parameters boot_params; static inline u32 running_from_sdram(void) { @@ -85,7 +80,7 @@ static inline u8 uboot_loaded_by_spl(void) * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a * mandatory section if CH is present. */ - if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) + if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) return 0; else return running_from_sdram(); diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 393c8bf..b79161d 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -27,6 +27,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + struct pad_conf_entry { u32 offset; u32 val; @@ -66,14 +68,6 @@ void get_ioregs(const struct ctrl_ioregs **regs); void srcomp_enable(void); void setup_warmreset_time(void); -/* - * This is used to verify if the configuration header - * was executed by Romcode prior to control of transfer - * to the bootloader. SPL is responsible for saving and - * passing this to the u-boot. - */ -extern struct omap_boot_parameters boot_params; - static inline u32 running_from_sdram(void) { u32 pc; @@ -92,7 +86,7 @@ static inline u8 uboot_loaded_by_spl(void) * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a * mandatory section if CH is present. */ - if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) + if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) return 0; else return running_from_sdram(); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index eebc9c7..ee7b188 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -25,6 +25,8 @@ #ifndef _OMAP_COMMON_H_ #define _OMAP_COMMON_H_ +#ifndef __ASSEMBLY__ + #include #define NUM_SYS_CLKS 8 @@ -558,6 +560,7 @@ static inline u32 omap_revision(void) extern u32 *const omap_si_rev; return *omap_si_rev; } +#endif /* * silicon revisions. diff --git a/common/spl/spl.c b/common/spl/spl.c index 6715e0d..e6aa89b 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -125,17 +125,13 @@ void spl_parse_image_header(const struct image_header *header) __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { - typedef void __noreturn (*image_entry_noargs_t)(u32 *); + typedef void __noreturn (*image_entry_noargs_t)(void); + image_entry_noargs_t image_entry = (image_entry_noargs_t) spl_image->entry_point; debug("image entry point: 0x%X\n", spl_image->entry_point); - /* Pass the saved boot_params from rom code */ -#if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU) - image_entry = (image_entry_noargs_t)0x80100000; -#endif - u32 boot_params_ptr_addr = (u32)&boot_params_ptr; - image_entry((u32 *)boot_params_ptr_addr); + image_entry(); } #ifdef CONFIG_SPL_RAM_DEVICE diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 5739422..941054d 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -17,6 +17,7 @@ #define __CONFIG_AM335X_EVM_H #define CONFIG_AM33XX +#define CONFIG_OMAP #include diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 50eafdf..14063a8 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -15,6 +15,7 @@ #define __CONFIG_IGEP0033_H #define CONFIG_AM33XX +#define CONFIG_OMAP #include diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 2e3f08b..cc8d317 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -20,6 +20,7 @@ #define __CONFIG_PCM051_H #define CONFIG_AM33XX +#define CONFIG_OMAP #include diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index e646bd7..6c423df 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -19,6 +19,7 @@ #define CONFIG_TI81XX #define CONFIG_TI814X #define CONFIG_SYS_NO_FLASH +#define CONFIG_OMAP #include diff --git a/include/spl.h b/include/spl.h index b40be80..4bc1dd1 100644 --- a/include/spl.h +++ b/include/spl.h @@ -44,7 +44,6 @@ struct spl_image_info { #define SPL_COPY_PAYLOAD_ONLY 1 extern struct spl_image_info spl_image; -extern u32 *boot_params_ptr; /* SPL common functions */ void preloader_console_init(void); -- cgit v0.10.2 From 47c6ea076eb51e624f8744d93db5cd70b97dc25d Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Wed, 24 Apr 2013 00:41:25 +0000 Subject: ARM: OMAP: Add arch_cpu_init function The boot parameters passed from SPL to UBOOT must be saved as a part of uboot's gd data as early as possible, before we will inadvertently overwrite it. So adding a arch_cpu_init for the required Socs to save it. Signed-off-by: Sricharan R [trini: Add igep0033 hunk] Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index c710784..1645120 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -147,6 +147,17 @@ static void save_omap_boot_params(void) } } +#ifdef CONFIG_ARCH_CPU_INIT +/* + * SOC specific cpu init + */ +int arch_cpu_init(void) +{ + save_omap_boot_params(); + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + /* * Routine: s_init * Description: Does early system init of watchdog, muxing, andclocks diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 941054d..f019134 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -294,6 +294,9 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_SYS_CONSOLE_INFO_QUIET diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 14063a8..1912d7d 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -157,6 +157,9 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_SYS_CONSOLE_INFO_QUIET diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 68faeca..d6448b0 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -87,6 +87,10 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} + +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + /* I2C */ #define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 7528f4c..deb5e9f 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -86,6 +86,9 @@ #define CONFIG_BAUDRATE 115200 +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + /* I2C */ #define CONFIG_HARD_I2C #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index cc8d317..478f805 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -193,6 +193,9 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_CONSOLE_INFO_QUIET diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 6c423df..eac5ad0 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -163,6 +163,9 @@ #define CONFIG_BAUDRATE 115200 +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_CONSOLE_INFO_QUIET -- cgit v0.10.2