From 5f8afd704c09a557f7303eac22d18c76f855c1cb Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 24 Mar 2016 22:37:08 +0100 Subject: sunxi: Add conditional magic sram poke for A33 I noticed that for certain SoC versions boot0 does a magic poke when build for A33. I'm not aware of this actually being necessary anywhere, but better safe then sorry. Signed-off-by: Hans de Goede Acked-by: Ian Campbell diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 7653148..bf58fa9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -120,18 +120,30 @@ void s_init(void) */ #if defined CONFIG_MACH_SUN6I setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); -#elif defined CONFIG_MACH_SUN8I_A23 - uint version; +#elif defined CONFIG_MACH_SUN8I + __maybe_unused uint version; /* Unlock sram version info reg, read it, relock */ setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); - version = readl(SUNXI_SRAMC_BASE + 0x24); + version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); - if ((version & 0xffff0000) == 0x16500000) + /* + * Ideally this would be a switch case, but we do not know exactly + * which versions there are and which version needs which settings, + * so reproduce the per SoC code from the BSP. + */ +#if defined CONFIG_MACH_SUN8I_A23 + if (version == 0x1650) setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); else /* 0x1661 ? */ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); +#elif defined CONFIG_MACH_SUN8I_A33 + if (version != 0x1667) + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); +#endif + /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */ + /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ #endif #if defined CONFIG_MACH_SUN6I || \ -- cgit v0.10.2 From c74384c68011c894a3543f7aca7bc387c1ab4a16 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 24 Mar 2016 22:38:23 +0100 Subject: sunxi: Print soc-id from sram controller for sun8i boards As the need for various magic sram pokes has shown this maybe useful info to have. e.g. this shows one of my a23 tablets having an id of 1661 rather then the usual 1650 for the a23. Signed-off-by: Hans de Goede Acked-by: Ian Campbell diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index b9bc70c..c0eabdf 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -38,6 +38,20 @@ int sunxi_get_ss_bonding_id(void) } #endif +#ifdef CONFIG_MACH_SUN8I +uint sunxi_get_sram_id(void) +{ + uint id; + + /* Unlock sram info reg, read it, relock */ + setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); + id = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; + clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); + + return id; +} +#endif + #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { @@ -66,15 +80,15 @@ int print_cpuinfo(void) #elif defined CONFIG_MACH_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); #elif defined CONFIG_MACH_SUN8I_A23 - puts("CPU: Allwinner A23 (SUN8I)\n"); + printf("CPU: Allwinner A23 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_A33 - puts("CPU: Allwinner A33 (SUN8I)\n"); + printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id()); +#elif defined CONFIG_MACH_SUN8I_A83T + printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_H3 - puts("CPU: Allwinner H3 (SUN8I)\n"); + printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN9I puts("CPU: Allwinner A80 (SUN9I)\n"); -#elif defined CONFIG_MACH_SUN8I_A83T - puts("CPU: Allwinner A83T (SUN8I)\n"); #else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); -- cgit v0.10.2 From 525d187afb418a4deef8916844f5f7744da402a8 Mon Sep 17 00:00:00 2001 From: Michael Haas Date: Fri, 25 Mar 2016 18:22:50 +0100 Subject: net: phy: Optionally force master mode for RTL PHY This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this define is set, RTL8211x PHYs (except for the RTL8211F) will have their 1000BASE-T master/slave autonegotiation disabled and forced to master mode. This is helpful for PHYs like the RTL8211C which produce unstable links in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB and A20-OLinuXino-Lime2. There is no proper way to identify affected PHYs in software as the RTL8211C shares its UID with the RTL8211B. Thus, this fix requires the introduction of an #ifdef. CC: fradav@gmail.com CC: merker@debian.org CC: hdegoede@redhat.com CC: ijc@hellion.org.uk CC: joe.hershberger@ni.com Signed-off-by: Michael Haas Tested-by: Karsten Merker Acked-by: Joe Hershberger Signed-off-by: Hans de Goede diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 2a229b8..e0008fd 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -13,6 +13,27 @@ config PHYLIB help Enable Ethernet PHY (physical media interface) support. +config RTL8211X_PHY_FORCE_MASTER + bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode" + depends on PHYLIB + help + Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F). + This can work around link stability and data corruption issues on gigabit + links which can occur in slave mode on certain PHYs, e.g. on the + RTL8211C(L). + + Please note that two directly connected devices (i.e. via crossover cable) + will not be able to establish a link between each other if they both force + master mode. Multiple devices forcing master mode when connected by a + network switch do not pose a problem as the switch configures its affected + ports into slave mode. + + This option only affects gigabit links. If you must establish a direct + connection between two devices which both force master mode, try forcing + the link speed to 100MBit/s. + + If unsure, say N. + menuconfig NETDEVICES bool "Network device support" depends on NET diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 259a87f..359ec50 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -12,6 +12,10 @@ #define PHY_AUTONEGOTIATE_TIMEOUT 5000 +/* RTL8211x 1000BASE-T Control Register */ +#define MIIM_RTL8211x_CTRL1000T_MSCE (1 << 12); +#define MIIM_RTL8211X_CTRL1000T_MASTER (1 << 11); + /* RTL8211x PHY Status Register */ #define MIIM_RTL8211x_PHY_STATUS 0x11 #define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000 @@ -53,7 +57,14 @@ static int rtl8211x_config(struct phy_device *phydev) */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, MIIM_RTL8211x_PHY_INTR_DIS); - +#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER + unsigned int reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); + /* force manual master/slave configuration */ + reg |= MIIM_RTL8211x_CTRL1000T_MSCE; + /* force master mode */ + reg |= MIIM_RTL8211X_CTRL1000T_MASTER; + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); +#endif /* read interrupt status just to clear it */ phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); -- cgit v0.10.2 From 7e4e7e4618c67311fac0d4f8af6bedbbbfe68c9b Mon Sep 17 00:00:00 2001 From: Michael Haas Date: Fri, 25 Mar 2016 18:22:51 +0100 Subject: sunxi: A20-Olimex-SOM-EVB: Force 8211CL to master Force master mode for 1000BASE-T operation on the A20-Olimex-SOM-EVB. Karsten Merker reports that this change is necessary to get a reliable link at gigabit speeds. Signed-off-by: Michael Haas Acked-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index 001d31b..1603b6f 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -16,5 +16,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y +CONFIG_RTL8211X_PHY_FORCE_MASTER=y CONFIG_ETH_DESIGNWARE=y CONFIG_USB_EHCI_HCD=y -- cgit v0.10.2 From 53866b6fc54142a2e7ab79d1c2b0f4313c29a2ec Mon Sep 17 00:00:00 2001 From: Michael Haas Date: Fri, 25 Mar 2016 18:22:52 +0100 Subject: sunxi: A20-OLinuXino-Lime2: Force 8211CL to master Force master mode on the A20-OLinuXino-Lime2. This change is required to get a reliable link at gigabit speeds. Signed-off-by: Michael Haas Acked-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index b5181c6..62a8338 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -13,5 +13,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y +CONFIG_RTL8211X_PHY_FORCE_MASTER=y CONFIG_ETH_DESIGNWARE=y CONFIG_USB_EHCI_HCD=y -- cgit v0.10.2 From affa020559bca31d6531e19cb1f009c22705a73d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 31 Mar 2016 14:38:14 +0200 Subject: sunxi: Enable LDO3 and LDO4 at 2.8V on OLinuxIno Lime boards LDO3 and LDO4 are used to power port E resp. port G, which are exposed on gpio headers, so enable them at 2.8V as specified in the schematic. Signed-off-by: Hans de Goede diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index af96f5b..25b48d9 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -13,4 +13,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y +CONFIG_AXP_ALDO3_VOLT=2800 +CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_USB_EHCI_HCD=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index 62a8338..419cdfb 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -15,4 +15,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)" CONFIG_CMD_GPIO=y CONFIG_RTL8211X_PHY_FORCE_MASTER=y CONFIG_ETH_DESIGNWARE=y +CONFIG_AXP_ALDO3_VOLT=2800 +CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_USB_EHCI_HCD=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index e27698d..151a0a3 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -12,4 +12,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)" # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y CONFIG_ETH_DESIGNWARE=y +CONFIG_AXP_ALDO3_VOLT=2800 +CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_USB_EHCI_HCD=y -- cgit v0.10.2 From b270eaa0cb607273ec7df980897d236806389d87 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:46 +0800 Subject: power: axp818: Remove undefined axp818_init() axp818_init() is declared, but never defined. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/include/axp818.h b/include/axp818.h index 46d05ad..c2f9847 100644 --- a/include/axp818.h +++ b/include/axp818.h @@ -53,8 +53,6 @@ #define AXP818_ALDO2_CTRL 0x29 #define AXP818_ALDO3_CTRL 0x2a -int axp818_init(void); - /* For axp_gpio.c */ #define AXP_POWER_STATUS 0x00 #define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) -- cgit v0.10.2 From 96fccb175fc3241768ce83fee47158ab506e9d8b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:55 +0800 Subject: musb: sunxi: Add support for A83T Like the Allwinner A33 SoC, the A83T is missing the config register from the musb USB DRD hardware block. Use a known working value for it. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index 4dc9abb..0f18dd7 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -434,7 +434,7 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase) static inline u8 musb_read_configdata(void __iomem *mbase) { -#ifdef CONFIG_MACH_SUN8I_A33 +#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T /* allwinner saves a reg, and we need to hardcode this */ return 0xde; #else -- cgit v0.10.2 From 81a8aa3a3969b3ec50ee27addcc4eaa0cb37aa94 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:56 +0800 Subject: sunxi: axp: Generalize register macros for VBUS drive GPIO VBUS drive is supported on AXP221 and later PMICs. Rework the macros so we can support this on later PMICs without too much work. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c index bd2ac89..ec00827 100644 --- a/drivers/gpio/axp_gpio.c +++ b/drivers/gpio/axp_gpio.c @@ -59,10 +59,11 @@ static int axp_gpio_direction_output(struct udevice *dev, unsigned pin, u8 reg; switch (pin) { -#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */ +#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC + /* Only available on later PMICs */ case SUNXI_GPIO_AXP0_VBUS_ENABLE: - ret = pmic_bus_clrbits(AXP221_MISC_CTRL, - AXP221_MISC_CTRL_N_VBUSEN_FUNC); + ret = pmic_bus_clrbits(AXP_MISC_CTRL, + AXP_MISC_CTRL_N_VBUSEN_FUNC); if (ret) return ret; @@ -90,10 +91,11 @@ static int axp_gpio_get_value(struct udevice *dev, unsigned pin) mask = AXP_POWER_STATUS_VBUS_PRESENT; break; #endif -#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */ +#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC + /* Only available on later PMICs */ case SUNXI_GPIO_AXP0_VBUS_ENABLE: - ret = pmic_bus_read(AXP221_VBUS_IPSOUT, &val); - mask = AXP221_VBUS_IPSOUT_DRIVEBUS; + ret = pmic_bus_read(AXP_VBUS_IPSOUT, &val); + mask = AXP_VBUS_IPSOUT_DRIVEBUS; break; #endif default: @@ -115,14 +117,15 @@ static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val) u8 reg; switch (pin) { -#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */ +#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC + /* Only available on later PMICs */ case SUNXI_GPIO_AXP0_VBUS_ENABLE: if (val) - return pmic_bus_setbits(AXP221_VBUS_IPSOUT, - AXP221_VBUS_IPSOUT_DRIVEBUS); + return pmic_bus_setbits(AXP_VBUS_IPSOUT, + AXP_VBUS_IPSOUT_DRIVEBUS); else - return pmic_bus_clrbits(AXP221_VBUS_IPSOUT, - AXP221_VBUS_IPSOUT_DRIVEBUS); + return pmic_bus_clrbits(AXP_VBUS_IPSOUT, + AXP_VBUS_IPSOUT_DRIVEBUS); #endif default: reg = axp_get_gpio_ctrl_reg(pin); diff --git a/include/axp221.h b/include/axp221.h index 04cd8c2..b4b64b0 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -43,12 +43,8 @@ #define AXP221_ALDO1_CTRL 0x28 #define AXP221_ALDO2_CTRL 0x29 #define AXP221_ALDO3_CTRL 0x2a -#define AXP221_VBUS_IPSOUT 0x30 -#define AXP221_VBUS_IPSOUT_DRIVEBUS (1 << 2) #define AXP221_SHUTDOWN 0x32 #define AXP221_SHUTDOWN_POWEROFF (1 << 7) -#define AXP221_MISC_CTRL 0x8f -#define AXP221_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) #define AXP221_PAGE 0xff /* Page 1 addresses */ @@ -57,6 +53,10 @@ /* For axp_gpio.c */ #define AXP_POWER_STATUS 0x00 #define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_VBUS_IPSOUT 0x30 +#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP_MISC_CTRL 0x8f +#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x92 #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ -- cgit v0.10.2 From b25b7ad16e1b2afa531612ce0b48d84d801c38d8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:57 +0800 Subject: sunxi: axp: Support VBUS drive GPIO on AXP818 AXP818 supports VBUS drive function, even though the manual does not mention it. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/include/axp818.h b/include/axp818.h index c2f9847..b24c790 100644 --- a/include/axp818.h +++ b/include/axp818.h @@ -55,7 +55,11 @@ /* For axp_gpio.c */ #define AXP_POWER_STATUS 0x00 -#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_VBUS_IPSOUT 0x30 +#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) +#define AXP_MISC_CTRL 0x8f +#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x92 #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ -- cgit v0.10.2 From 4c6a9ca103f953b6e5e6dfcd56fb558e61ca3c05 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:47 +0800 Subject: power: axp818: Fix DCDC5 default voltage DCDC5 is designed to supply VCC-DRAM, which is normally 1.5V for DDR3, 1.35V for DDR3L, and 1.2V for LPDDR3. Also remove CONFIG_AXP_DCDC5_VOLT from h8_homlet_v2_defconfig. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index 4742aaf6..1f492ab 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -12,4 +12,3 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_AXP_DCDC1_VOLT=3000 -CONFIG_AXP_DCDC5_VOLT=1500 diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index adc6455..548fe26 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -118,13 +118,12 @@ config AXP_DCDC4_VOLT config AXP_DCDC5_VOLT int "axp pmic dcdc5 voltage" depends on AXP221_POWER || AXP818_POWER - default 1800 if AXP818_POWER default 1500 if MACH_SUN6I || MACH_SUN8I ---help--- Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to disable dcdc5. On A23 / A31 / A33 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V, - 1.8V for A83T. + 1.35V if DDR3L is used. config AXP_ALDO1_VOLT int "axp pmic (a)ldo1 voltage" -- cgit v0.10.2 From 38491d9c6515eafd97d881cab0420652f07d92a5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:48 +0800 Subject: power: axp818: Add support for FLDOs The FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY on the A83T/H8. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 2d5335f..2271c89 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -486,6 +486,12 @@ void sunxi_board_init(void) power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); #endif + +#ifdef CONFIG_AXP818_POWER + power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); + power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); + power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); +#endif #endif printf("DRAM:"); ramsize = sunxi_dram_init(); diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 548fe26..937b9aa 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -238,6 +238,33 @@ config AXP_ELDO3_VOLT 1.2V for the SSD2828 chip (converter of parallel LCD interface into MIPI DSI). +config AXP_FLDO1_VOLT + int "axp pmic fldo1 voltage" + depends on AXP818_POWER + default 0 if MACH_SUN8I_A83T + ---help--- + Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to + disable fldo1. + On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is + used. + +config AXP_FLDO2_VOLT + int "axp pmic eldo2 voltage" + depends on AXP818_POWER + default 900 if MACH_SUN8I_A83T + ---help--- + Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to + disable fldo2. + On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V. + +config AXP_FLDO3_VOLT + int "axp pmic fldo3 voltage" + depends on AXP818_POWER + default 0 + ---help--- + Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to + disable fldo3. + config SY8106A_VOUT1_VOLT int "SY8106A pmic VOUT1 voltage" depends on SY8106A_POWER diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c index e885d02..3ac05ff 100644 --- a/drivers/power/axp818.c +++ b/drivers/power/axp818.c @@ -191,6 +191,40 @@ int axp_set_eldo(int eldo_num, unsigned int mvolt) AXP818_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1)); } +int axp_set_fldo(int fldo_num, unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (fldo_num < 1 || fldo_num > 3) + return -EINVAL; + + if (mvolt == 0) + return pmic_bus_clrbits(AXP818_OUTPUT_CTRL3, + AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1)); + + if (fldo_num < 3) { + cfg = axp818_mvolt_to_cfg(mvolt, 700, 1450, 50); + ret = pmic_bus_write(AXP818_FLDO1_CTRL + (fldo_num - 1), cfg); + } else { + /* + * Special case for FLDO3, which is DCDC5 / 2 or FLDOIN / 2 + * Since FLDOIN is unknown, test against DCDC5. + */ + if (mvolt * 2 == CONFIG_AXP_DCDC5_VOLT) + ret = pmic_bus_clrbits(AXP818_FLDO2_3_CTRL, + AXP818_FLDO2_3_CTRL_FLDO3_VOL); + else + ret = pmic_bus_setbits(AXP818_FLDO2_3_CTRL, + AXP818_FLDO2_3_CTRL_FLDO3_VOL); + } + if (ret) + return ret; + + return pmic_bus_setbits(AXP818_OUTPUT_CTRL3, + AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1)); +} + int axp_init(void) { u8 axp_chip_id; diff --git a/include/axp818.h b/include/axp818.h index b24c790..5630eed 100644 --- a/include/axp818.h +++ b/include/axp818.h @@ -41,6 +41,7 @@ #define AXP818_ELDO3_CTRL 0x1b #define AXP818_FLDO1_CTRL 0x1c #define AXP818_FLDO2_3_CTRL 0x1d +#define AXP818_FLDO2_3_CTRL_FLDO3_VOL (1 << 4) #define AXP818_DCDC1_CTRL 0x20 #define AXP818_DCDC2_CTRL 0x21 #define AXP818_DCDC3_CTRL 0x22 diff --git a/include/axp_pmic.h b/include/axp_pmic.h index 0f14683..b203cc8 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -31,6 +31,7 @@ int axp_set_aldo3(unsigned int mvolt); int axp_set_aldo4(unsigned int mvolt); int axp_set_dldo(int dldo_num, unsigned int mvolt); int axp_set_eldo(int eldo_num, unsigned int mvolt); +int axp_set_fldo(int fldo_num, unsigned int mvolt); int axp_init(void); int axp_get_sid(unsigned int *sid); -- cgit v0.10.2 From 9c85a40c40f047ecd61caa972711dda8d9621d4e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:49 +0800 Subject: sunxi: h8_homlet_v2: Set DCDC1 to default voltage (3.3V) The schematics of the h8_homlet_v2 show DCDC1 set to 3.3V. Some Allwinner-based boards set it to 3.0V to conserve power. Since the h8_homlet_v2 is a set-top box board with external power, there is no such requirement. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index 1f492ab..538a2c2 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -11,4 +11,3 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -CONFIG_AXP_DCDC1_VOLT=3000 -- cgit v0.10.2 From 5bbda173a911882e982a4c253e21f789275902c9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:50 +0800 Subject: sunxi: h8_homlet_v2: Set DLDO4 to 3.3V DLDO4 supplies power to the PD pins, and the AC200 Ethernet PHY / composite video encoder. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index 538a2c2..4ede071 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -11,3 +11,4 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_AXP_DLDO4_VOLT=3300 -- cgit v0.10.2 From 0c935acb9e5dcc0b5889c95a5f3d4163c8638c70 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:51 +0800 Subject: sunxi: usb_phy: Add support for A83T USB PHYs The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host, 1 for USB HSIC. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c index 0749fbd..fa375f1 100644 --- a/arch/arm/cpu/armv7/sunxi/usb_phy.c +++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c @@ -34,6 +34,16 @@ #define REG_PHY_UNK_H3 0x420 #define REG_PMU_UNK_H3 0x810 +/* A83T specific control bits for PHY0 */ +#define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5) +#define SUNXI_PHY_CTL_SIDDQ BIT(3) + +/* A83T HSIC specific bits */ +#define SUNXI_EHCI_HS_FORCE BIT(20) +#define SUNXI_EHCI_CONNECT_DET BIT(17) +#define SUNXI_EHCI_CONNECT_INT BIT(16) +#define SUNXI_EHCI_HSIC BIT(1) + static struct sunxi_usb_phy { int usb_rst_mask; int gpio_vbus; @@ -56,7 +66,12 @@ static struct sunxi_usb_phy { }, #if CONFIG_SUNXI_USB_PHYS >= 3 { +#ifdef CONFIG_MACH_SUN8I_A83T + .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK | + CCM_USB_CTRL_12M_CLK, +#else .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, +#endif .id = 2, .base = SUNXI_USB2_BASE, }, @@ -97,8 +112,8 @@ static int get_id_detect_gpio(int index) return -EINVAL; } -static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, - int data, int len) +__maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, + int data, int len) { int j = 0, usbc_bit = 0; void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR; @@ -137,6 +152,10 @@ static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); } +#elif defined CONFIG_MACH_SUN8I_A83T +static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) +{ +} #else static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { @@ -174,6 +193,13 @@ static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable) SUNXI_EHCI_AHB_INCRX_ALIGN_EN | SUNXI_EHCI_ULPI_BYPASS_EN; +#ifdef CONFIG_MACH_SUN8I_A83T + if (phy->id == 2) + bits |= SUNXI_EHCI_HS_FORCE | + SUNXI_EHCI_CONNECT_INT | + SUNXI_EHCI_HSIC; +#endif + if (enable) setbits_le32(addr, bits); else @@ -184,9 +210,11 @@ static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable) void sunxi_usb_phy_enable_squelch_detect(int index, int enable) { +#ifndef CONFIG_MACH_SUN8I_A83T struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2); +#endif } void sunxi_usb_phy_init(int index) @@ -204,6 +232,15 @@ void sunxi_usb_phy_init(int index) if (phy->id != 0) sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN); + +#ifdef CONFIG_MACH_SUN8I_A83T + if (phy->id == 0) { + setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, + SUNXI_PHY_CTL_VBUSVLDEXT); + clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, + SUNXI_PHY_CTL_SIDDQ); + } +#endif } void sunxi_usb_phy_exit(int index) @@ -218,6 +255,13 @@ void sunxi_usb_phy_exit(int index) if (phy->id != 0) sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN); +#ifdef CONFIG_MACH_SUN8I_A83T + if (phy->id == 0) { + setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, + SUNXI_PHY_CTL_SIDDQ); + } +#endif + clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); } diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 7c0ab1e..eb5db4e 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -20,6 +20,8 @@ #ifdef CONFIG_MACH_SUN8I_H3 #define CONFIG_SUNXI_USB_PHYS 4 +#elif defined CONFIG_MACH_SUN8I_A83T + #define CONFIG_SUNXI_USB_PHYS 3 #else #define CONFIG_SUNXI_USB_PHYS 2 #endif -- cgit v0.10.2 From 93bac9531078cd615b5e27dc313f0df84d8d29bd Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:52 +0800 Subject: sunxi: clk: Fix USB PHY clock macros for A83T The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks. Also there is only 1 OHCI. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h index 5f93d7f..5e1346e 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -224,14 +224,14 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) -#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +#define CCM_USB_CTRL_HSIC_RST (0x1 << 2) /* There is no global phy clk gate on sun6i, define as 0 */ #define CCM_USB_CTRL_PHYGATE 0 #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) -#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_USB_CTRL_HSIC_CLK (0x1 << 10) +#define CCM_USB_CTRL_12M_CLK (0x1 << 11) #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 -- cgit v0.10.2 From 3655f287b6eb9f9dfd35d9229bd0d53fa400877d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:53 +0800 Subject: sunxi: ehci: Add A83T compatible We have a separate compatible for almost each SoC. Add one for the A83T. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 677a5d3..d5eb492 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -91,6 +91,7 @@ static const struct udevice_id ehci_usb_ids[] = { { .compatible = "allwinner,sun6i-a31-ehci", }, { .compatible = "allwinner,sun7i-a20-ehci", }, { .compatible = "allwinner,sun8i-a23-ehci", }, + { .compatible = "allwinner,sun8i-a83t-ehci", }, { .compatible = "allwinner,sun8i-h3-ehci", }, { .compatible = "allwinner,sun9i-a80-ehci", }, { } -- cgit v0.10.2 From 045ae7e3393fc940b183b3f2ea9c9edd62d9e810 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:54 +0800 Subject: sunxi: ohci: Add A83T compatible We have a separate compatible for almost each SoC. Add one for the A83T. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index d4fb95a..6f3f4ce 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -94,6 +94,7 @@ static const struct udevice_id ohci_usb_ids[] = { { .compatible = "allwinner,sun6i-a31-ohci", }, { .compatible = "allwinner,sun7i-a20-ohci", }, { .compatible = "allwinner,sun8i-a23-ohci", }, + { .compatible = "allwinner,sun8i-a83t-ohci", }, { .compatible = "allwinner,sun8i-h3-ohci", }, { .compatible = "allwinner,sun9i-a80-ohci", }, { } -- cgit v0.10.2 From 3cc7177913eb83cae6e20b2f71d4db40fb4d37e7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:58 +0800 Subject: sunxi: h8_homlet_v2: Enable USB Kconfig options in defconfig The h8_homlet_v2 has 2 USB host ports, one connected to the OTG controller, one connected to the EHCI/OHCI pair. Also provide the card detect pin for MMC. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index 4ede071..e04d96b 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -4,6 +4,9 @@ CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_USB0_VBUS_PIN="PL5" +CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -12,3 +15,5 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_HOST=y -- cgit v0.10.2 From 7e4c5d207398ac38c5b97a7c99d79f0a518cc015 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:26:59 +0800 Subject: sunxi: Cubietruck Plus: Enable USB Kconfig options in defconfig The Cubietruck Plus uses all 3 USB controllers: - USB OTG functions are provided by the musb USB OTG controller - Onboard SATA is provied by a USB-SATA bridge connected to USB1 - The USB host ports on the board are provided by an HSIC USB hub FLDO1 is set to 1.2V for HSIC. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index bb0b336..d625c21 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -6,13 +6,21 @@ CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_I2C0_ENABLE=y +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_USB0_ID_DET="PH11" +CONFIG_USB1_VBUS_PIN="PD29" +CONFIG_USB2_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="RGMII,MACPWR=SUNXI_GPD(20)" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y CONFIG_AXP_DLDO3_VOLT=2500 CONFIG_AXP_DLDO4_VOLT=3300 +CONFIG_AXP_FLDO1_VOLT=1200 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_HOST=y -- cgit v0.10.2 From b0bea66789817a1e3ac11c6303e1b3126ba50eec Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:27:00 +0800 Subject: sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi This provides the minimal changes to the A83T dtsi to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi index d3473f8..0fe73e1 100644 --- a/arch/arm/dts/sun8i-a83t.dtsi +++ b/arch/arm/dts/sun8i-a83t.dtsi @@ -224,5 +224,39 @@ #interrupt-cells = <3>; interrupts = ; }; + + usb_otg: usb@01c19000 { + compatible = "allwinner,sun8i-a33-musb"; + interrupts = ; + interrupt-names = "mc"; + status = "disabled"; + }; + + ehci0: usb@01c1a000 { + compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = ; + status = "disabled"; + }; + + ohci0: usb@01c1a400 { + compatible = "allwinner,sun8i-a83t-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = ; + status = "disabled"; + }; + + ehci1: usb@01c1b000 { + compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = ; + status = "disabled"; + }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun8i-a83t-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = ; + }; }; }; -- cgit v0.10.2 From d02e647432c06ef01ae8d0f4532bd1a3e8e14b1e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:27:01 +0800 Subject: sunxi: Enable USB on Cubietruck Plus This provides the minimal changes to the Cubietruck Plus dts to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts index 88b1e09..8437c8f 100644 --- a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts @@ -58,8 +58,20 @@ }; }; +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_b>; status = "okay"; }; + +&usb_otg { + status = "okay"; +}; -- cgit v0.10.2 From fa06f7ed11bd90874f97fbfe6adc6a8aeacce8c0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Mar 2016 00:27:02 +0800 Subject: sunxi: Enable USB nodes for H8Homlet v2 This provides the minimal changes to the H8Homlet v2 dts to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index 342e1d3..c8495d7 100644 --- a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -57,8 +57,20 @@ }; }; +&ehci0 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_b>; status = "okay"; }; + +&usb_otg { + status = "okay"; +}; -- cgit v0.10.2 From e6e505b93cb3fd264227c65ae1bfc9e4681555d8 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Tue, 29 Mar 2016 17:29:06 +0200 Subject: sunxi: Move cpu independent code to mach directory Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while most of it is just generic code that could as well be used on an AArch64 SoC. Move all files that are not really tied to armv7 into a new mach-sunxi directory. Signed-off-by: Alexander Graf Acked-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6defdfb..ce006ae 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -54,6 +54,7 @@ machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx +machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_STM32) += stm32 diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index ce8e571..4d2274a 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -8,38 +8,10 @@ # SPDX-License-Identifier: GPL-2.0+ # obj-y += timer.o -obj-y += board.o -obj-y += clock.o -obj-y += cpu_info.o -obj-y += dram_helpers.o -obj-y += pinmux.o -ifndef CONFIG_MACH_SUN9I -obj-y += usb_phy.o -endif -obj-$(CONFIG_MACH_SUN6I) += prcm.o -obj-$(CONFIG_MACH_SUN8I) += prcm.o -obj-$(CONFIG_MACH_SUN9I) += prcm.o -obj-$(CONFIG_MACH_SUN6I) += p2wi.o -obj-$(CONFIG_MACH_SUN8I) += rsb.o -obj-$(CONFIG_MACH_SUN9I) += rsb.o -obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o -obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o -obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o -obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o -ifdef CONFIG_MACH_SUN8I_A83T -obj-y += clock_sun8i_a83t.o -else -obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o -endif -obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o + obj-$(CONFIG_MACH_SUN6I) += tzpc.o obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o -obj-$(CONFIG_AXP152_POWER) += pmic_bus.o -obj-$(CONFIG_AXP209_POWER) += pmic_bus.o -obj-$(CONFIG_AXP221_POWER) += pmic_bus.o -obj-$(CONFIG_AXP818_POWER) += pmic_bus.o - ifndef CONFIG_SPL_BUILD ifdef CONFIG_ARMV7_PSCI obj-$(CONFIG_MACH_SUN6I) += psci_sun6i.o @@ -49,13 +21,5 @@ endif endif ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o -obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o -obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o -obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o -obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o -obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o -obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o -obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o obj-y += fel_utils.o endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c deleted file mode 100644 index bf58fa9..0000000 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * (C) Copyright 2012 Henrik Nordstrom - * - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. - * Tom Cubie - * - * Some init for sunxi platform. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#ifdef CONFIG_SPL_BUILD -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -struct fel_stash { - uint32_t sp; - uint32_t lr; - uint32_t cpsr; - uint32_t sctlr; - uint32_t vbar; - uint32_t cr; -}; - -struct fel_stash fel_stash __attribute__((section(".data"))); - -static int gpio_init(void) -{ -#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) - /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ - sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); - sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); -#endif -#if defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); -#else - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); -#endif - sunxi_gpio_set_pull(SUNXI_GPF(4), 1); -#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) - sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); - sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3) - sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); - sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) - sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); - sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); - sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); - sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); - sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); - sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); - sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); - sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); -#else -#error Unsupported console port number. Please fix pin mux settings in board.c -#endif - - return 0; -} - -int spl_board_load_image(void) -{ - debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); - return_to_fel(fel_stash.sp, fel_stash.lr); - - return 0; -} - -void s_init(void) -{ - /* - * Undocumented magic taken from boot0, without this DRAM - * access gets messed up (seems cache related). - * The boot0 sources describe this as: "config ema for cache sram" - */ -#if defined CONFIG_MACH_SUN6I - setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); -#elif defined CONFIG_MACH_SUN8I - __maybe_unused uint version; - - /* Unlock sram version info reg, read it, relock */ - setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); - version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; - clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); - - /* - * Ideally this would be a switch case, but we do not know exactly - * which versions there are and which version needs which settings, - * so reproduce the per SoC code from the BSP. - */ -#if defined CONFIG_MACH_SUN8I_A23 - if (version == 0x1650) - setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); - else /* 0x1661 ? */ - setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); -#elif defined CONFIG_MACH_SUN8I_A33 - if (version != 0x1667) - setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); -#endif - /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */ - /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ -#endif - -#if defined CONFIG_MACH_SUN6I || \ - defined CONFIG_MACH_SUN7I || \ - defined CONFIG_MACH_SUN8I - /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #1 << 6\n" - "mcr p15, 0, r0, c1, c0, 1\n"); -#endif -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 - /* Enable non-secure access to some peripherals */ - tzpc_init(); -#endif - - clock_init(); - timer_init(); - gpio_init(); - i2c_init_board(); - eth_init_board(); -} - -#ifdef CONFIG_SPL_BUILD -DECLARE_GLOBAL_DATA_PTR; - -/* The sunxi internal brom will try to loader external bootloader - * from mmc0, nand flash, mmc2. - */ -u32 spl_boot_device(void) -{ - __maybe_unused struct mmc *mmc0, *mmc1; - /* - * When booting from the SD card or NAND memory, the "eGON.BT0" - * signature is expected to be found in memory at the address 0x0004 - * (see the "mksunxiboot" tool, which generates this header). - * - * When booting in the FEL mode over USB, this signature is patched in - * memory and replaced with something else by the 'fel' tool. This other - * signature is selected in such a way, that it can't be present in a - * valid bootable SD card image (because the BROM would refuse to - * execute the SPL in this case). - * - * This checks for the signature and if it is not found returns to - * the FEL code in the BROM to wait and receive the main u-boot - * binary over USB. If it is found, it determines where SPL was - * read from. - */ - if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ - return BOOT_DEVICE_BOARD; - - /* The BROM will try to boot from mmc0 first, so try that first. */ -#ifdef CONFIG_MMC - mmc_initialize(gd->bd); - mmc0 = find_mmc_device(0); - if (sunxi_mmc_has_egon_boot_signature(mmc0)) - return BOOT_DEVICE_MMC1; -#endif - - /* Fallback to booting NAND if enabled. */ - if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT)) - return BOOT_DEVICE_NAND; - -#ifdef CONFIG_MMC - if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) { - mmc1 = find_mmc_device(1); - if (sunxi_mmc_has_egon_boot_signature(mmc1)) - return BOOT_DEVICE_MMC2; - } -#endif - - panic("Could not determine boot source\n"); - return -1; /* Never reached */ -} - -/* No confirmation data available in SPL yet. Hardcode bootmode */ -u32 spl_boot_mode(void) -{ - return MMCSD_MODE_RAW; -} - -void board_init_f(ulong dummy) -{ - spl_init(); - preloader_console_init(); - -#ifdef CONFIG_SPL_I2C_SUPPORT - /* Needed early by sunxi_board_init if PMU is enabled */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - sunxi_board_init(); -} -#endif - -void reset_cpu(ulong addr) -{ -#ifdef CONFIG_SUNXI_GEN_SUN4I - static const struct sunxi_wdog *wdog = - &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; - - /* Set the watchdog for its shortest interval (.5s) and wait */ - writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); - writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); - - while (1) { - /* sun5i sometimes gets stuck without this */ - writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); - } -#endif -#ifdef CONFIG_SUNXI_GEN_SUN6I - static const struct sunxi_wdog *wdog = - ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; - - /* Set the watchdog for its shortest interval (.5s) and wait */ - writel(WDT_CFG_RESET, &wdog->cfg); - writel(WDT_MODE_EN, &wdog->mode); - writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); - while (1) { } -#endif -} - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c deleted file mode 100644 index 0b8fc94..0000000 --- a/arch/arm/cpu/armv7/sunxi/clock.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. - * Tom Cubie - * - * (C) Copyright 2013 Luke Kenneth Casson Leighton - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -__weak void clock_init_sec(void) -{ -} - -int clock_init(void) -{ -#ifdef CONFIG_SPL_BUILD - clock_init_safe(); -#endif - clock_init_uart(); - clock_init_sec(); - - return 0; -} - -/* These functions are shared between various SoCs so put them here. */ -#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I -int clock_twi_onoff(int port, int state) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - if (port == 5) { - if (state) - prcm_apb0_enable( - PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); - else - prcm_apb0_disable( - PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); - return 0; - } - - /* set the apb clock gate and reset for twi */ - if (state) { - setbits_le32(&ccm->apb2_gate, - CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); - setbits_le32(&ccm->apb2_reset_cfg, - 1 << (APB2_RESET_TWI_SHIFT + port)); - } else { - clrbits_le32(&ccm->apb2_reset_cfg, - 1 << (APB2_RESET_TWI_SHIFT + port)); - clrbits_le32(&ccm->apb2_gate, - CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); - } - - return 0; -} -#endif diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c deleted file mode 100644 index 7e6bd61..0000000 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * sun4i, sun5i and sun7i specific clock code - * - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. - * Tom Cubie - * - * (C) Copyright 2013 Luke Kenneth Casson Leighton - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_SPL_BUILD -void clock_init_safe(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* Set safe defaults until PMU is configured */ - writel(AXI_DIV_1 << AXI_DIV_SHIFT | - AHB_DIV_2 << AHB_DIV_SHIFT | - APB0_DIV_1 << APB0_DIV_SHIFT | - CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, - &ccm->cpu_ahb_apb0_cfg); - writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); - sdelay(200); - writel(AXI_DIV_1 << AXI_DIV_SHIFT | - AHB_DIV_2 << AHB_DIV_SHIFT | - APB0_DIV_1 << APB0_DIV_SHIFT | - CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, - &ccm->cpu_ahb_apb0_cfg); -#ifdef CONFIG_MACH_SUN7I - setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); -#endif - writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); -#ifdef CONFIG_SUNXI_AHCI - setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); - setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); -#endif -} -#endif - -void clock_init_uart(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* uart clock source is apb1 */ - writel(APB1_CLK_SRC_OSC24M| - APB1_CLK_RATE_N_1| - APB1_CLK_RATE_M(1), - &ccm->apb1_clk_div_cfg); - - /* open the clock for uart */ - setbits_le32(&ccm->apb1_gate, - CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1)); -} - -int clock_twi_onoff(int port, int state) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* set the apb clock gate for twi */ - if (state) - setbits_le32(&ccm->apb1_gate, - CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); - else - clrbits_le32(&ccm->apb1_gate, - CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ - 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \ - 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \ - 0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \ - 16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \ - (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \ - 2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \ - (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \ - (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \ - 0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \ - 0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \ - (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT) - -static struct { - u32 pll1_cfg; - unsigned int freq; -} pll1_para[] = { - /* This array must be ordered by frequency. */ - { PLL1_CFG(31, 1, 0, 0), 1488000000}, - { PLL1_CFG(30, 1, 0, 0), 1440000000}, - { PLL1_CFG(29, 1, 0, 0), 1392000000}, - { PLL1_CFG(28, 1, 0, 0), 1344000000}, - { PLL1_CFG(27, 1, 0, 0), 1296000000}, - { PLL1_CFG(26, 1, 0, 0), 1248000000}, - { PLL1_CFG(25, 1, 0, 0), 1200000000}, - { PLL1_CFG(24, 1, 0, 0), 1152000000}, - { PLL1_CFG(23, 1, 0, 0), 1104000000}, - { PLL1_CFG(22, 1, 0, 0), 1056000000}, - { PLL1_CFG(21, 1, 0, 0), 1008000000}, - { PLL1_CFG(20, 1, 0, 0), 960000000 }, - { PLL1_CFG(19, 1, 0, 0), 912000000 }, - { PLL1_CFG(16, 1, 0, 0), 768000000 }, - /* Final catchall entry 384MHz*/ - { PLL1_CFG(16, 0, 0, 0), 0 }, - -}; - -void clock_set_pll1(unsigned int hz) -{ - int i = 0; - int axi, ahb, apb0; - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* Find target frequency */ - while (pll1_para[i].freq > hz) - i++; - - hz = pll1_para[i].freq; - if (! hz) - hz = 384000000; - - /* Calculate system clock divisors */ - axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ - ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ - apb0 = 2; /* Max 150MHz */ - - printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); - - /* Map divisors to register values */ - axi = axi - 1; - if (ahb > 4) - ahb = 3; - else if (ahb > 2) - ahb = 2; - else if (ahb > 1) - ahb = 1; - else - ahb = 0; - - apb0 = apb0 - 1; - - /* Switch to 24MHz clock while changing PLL1 */ - writel(AXI_DIV_1 << AXI_DIV_SHIFT | - AHB_DIV_2 << AHB_DIV_SHIFT | - APB0_DIV_1 << APB0_DIV_SHIFT | - CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, - &ccm->cpu_ahb_apb0_cfg); - sdelay(20); - - /* Configure sys clock divisors */ - writel(axi << AXI_DIV_SHIFT | - ahb << AHB_DIV_SHIFT | - apb0 << APB0_DIV_SHIFT | - CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, - &ccm->cpu_ahb_apb0_cfg); - - /* Configure PLL1 at the desired frequency */ - writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg); - sdelay(200); - - /* Switch CPU to PLL1 */ - writel(axi << AXI_DIV_SHIFT | - ahb << AHB_DIV_SHIFT | - apb0 << APB0_DIV_SHIFT | - CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, - &ccm->cpu_ahb_apb0_cfg); - sdelay(20); -} -#endif - -void clock_set_pll3(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - if (clk == 0) { - clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); - return; - } - - /* PLL3 rate = 3000000 * m */ - writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | - CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg); -} - -unsigned int clock_get_pll3(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll3_cfg); - int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT); - return 3000000 * m; -} - -unsigned int clock_get_pll5p(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll5_cfg); - int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT); - int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1; - int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT); - return (24000000 * n * k) >> p; -} - -unsigned int clock_get_pll6(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll6_cfg); - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); - int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; - return 24000000 * n * k / 2; -} - -void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) -{ - int pll = clock_get_pll5p(); - int div = 1; - - while ((pll / div) > hz) - div++; - - writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P | - CCM_DE_CTRL_M(div), clk_cfg); -} diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c deleted file mode 100644 index 15272c9..0000000 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * sun6i specific clock code - * - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. - * Tom Cubie - * - * (C) Copyright 2013 Luke Kenneth Casson Leighton - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_SPL_BUILD -void clock_init_safe(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_prcm_reg * const prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; - - /* Set PLL ldo voltage without this PLL6 does not work properly */ - clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, - PRCM_PLL_CTRL_LDO_KEY); - clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, - PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | - PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); - clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); - - clock_set_pll1(408000000); - - writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); - while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) - ; - - writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); - - writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); - writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); -} -#endif - -void clock_init_sec(void) -{ -#ifdef CONFIG_MACH_SUN8I_H3 - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - setbits_le32(&ccm->ccu_sec_switch, - CCM_SEC_SWITCH_MBUS_NONSEC | - CCM_SEC_SWITCH_BUS_NONSEC | - CCM_SEC_SWITCH_PLL_NONSEC); -#endif -} - -void clock_init_uart(void) -{ -#if CONFIG_CONS_INDEX < 5 - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* uart clock source is apb2 */ - writel(APB2_CLK_SRC_OSC24M| - APB2_CLK_RATE_N_1| - APB2_CLK_RATE_M(1), - &ccm->apb2_div); - - /* open the clock for uart */ - setbits_le32(&ccm->apb2_gate, - CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + - CONFIG_CONS_INDEX - 1)); - - /* deassert uart reset */ - setbits_le32(&ccm->apb2_reset_cfg, - 1 << (APB2_RESET_UART_SHIFT + - CONFIG_CONS_INDEX - 1)); -#else - /* enable R_PIO and R_UART clocks, and de-assert resets */ - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); -#endif -} - -#ifdef CONFIG_SPL_BUILD -void clock_set_pll1(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - const int p = 0; - int k = 1; - int m = 1; - - if (clk > 1152000000) { - k = 2; - } else if (clk > 768000000) { - k = 3; - m = 2; - } - - /* Switch to 24MHz clock while changing PLL1 */ - writel(AXI_DIV_3 << AXI_DIV_SHIFT | - ATB_DIV_2 << ATB_DIV_SHIFT | - CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, - &ccm->cpu_axi_cfg); - - /* - * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored) - * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m - */ - writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | - CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | - CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); - sdelay(200); - - /* Switch CPU to PLL1 */ - writel(AXI_DIV_3 << AXI_DIV_SHIFT | - ATB_DIV_2 << ATB_DIV_SHIFT | - CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, - &ccm->cpu_axi_cfg); -} -#endif - -void clock_set_pll3(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ - - if (clk == 0) { - clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); - return; - } - - /* PLL3 rate = 24000000 * n / m */ - writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | - CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m), - &ccm->pll3_cfg); -} - -void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - const int max_n = 32; - int k = 1, m = 2; - - if (sigma_delta_enable) - writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); - - /* PLL5 rate = 24000000 * n * k / m */ - if (clk > 24000000 * k * max_n / m) { - m = 1; - if (clk > 24000000 * k * max_n / m) - k = 2; - } - writel(CCM_PLL5_CTRL_EN | - (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | - CCM_PLL5_CTRL_UPD | - CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | - CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); - - udelay(5500); -} - -#ifdef CONFIG_MACH_SUN6I -void clock_set_mipi_pll(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - unsigned int k, m, n, value, diff; - unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff; - unsigned int src = clock_get_pll3(); - - /* All calculations are in KHz to avoid overflows */ - clk /= 1000; - src /= 1000; - - /* Pick the closest lower clock */ - for (k = 1; k <= 4; k++) { - for (m = 1; m <= 16; m++) { - for (n = 1; n <= 16; n++) { - value = src * n * k / m; - if (value > clk) - continue; - - diff = clk - value; - if (diff < best_diff) { - best_diff = diff; - best_k = k; - best_m = m; - best_n = n; - } - if (diff == 0) - goto done; - } - } - } - -done: - writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN | - CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) | - CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg); -} -#endif - -#ifdef CONFIG_MACH_SUN8I_A33 -void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - if (sigma_delta_enable) - writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg); - - writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD | - (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) | - CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg); - - while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD) - ; -} -#endif - -unsigned int clock_get_pll3(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll3_cfg); - int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; - int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; - - /* Multiply by 1000 after dividing by m to avoid integer overflows */ - return (24000 * n / m) * 1000; -} - -unsigned int clock_get_pll6(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll6_cfg); - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; - int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; - return 24000000 * n * k / 2; -} - -unsigned int clock_get_mipi_pll(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->mipi_pll_cfg); - unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1; - unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1; - unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1; - unsigned int src = clock_get_pll3(); - - /* Multiply by 1000 after dividing by m to avoid integer overflows */ - return ((src / 1000) * n * k / m) * 1000; -} - -void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) -{ - int pll = clock_get_pll6() * 2; - int div = 1; - - while ((pll / div) > hz) - div++; - - writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), - clk_cfg); -} diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c deleted file mode 100644 index 3e8728f..0000000 --- a/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * A83 specific clock code - * - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. - * Tom Cubie - * - * (C) Copyright 2015 Vishnu Patekar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_SPL_BUILD -void clock_init_safe(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - clock_set_pll1(408000000); - /* enable pll_hsic, default is 480M */ - writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg); - writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); - while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {} - - /* switch to default 24MHz before changing to hsic */ - writel(0x0, &ccm->cci400_cfg); - sdelay(50); - writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg); - sdelay(100); - - /* switch before changing pll6 */ - clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK, - AHB1_CLK_SRC_OSC24M); - writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); - while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {} - - writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); - writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset); - writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg); - - /* timestamp */ - writel(1, 0x01720000); -} -#endif - -void clock_init_uart(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* uart clock source is apb2 */ - writel(APB2_CLK_SRC_OSC24M| - APB2_CLK_RATE_N_1| - APB2_CLK_RATE_M(1), - &ccm->apb2_div); - - /* open the clock for uart */ - setbits_le32(&ccm->apb2_gate, - CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + - CONFIG_CONS_INDEX - 1)); - - /* deassert uart reset */ - setbits_le32(&ccm->apb2_reset_cfg, - 1 << (APB2_RESET_UART_SHIFT + - CONFIG_CONS_INDEX - 1)); -} - -#ifdef CONFIG_SPL_BUILD -void clock_set_pll1(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - const int p = 0; - - /* Switch to 24MHz clock while changing PLL1 */ - writel(AXI_DIV_2 << AXI0_DIV_SHIFT | - AXI_DIV_2 << AXI1_DIV_SHIFT | - CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT | - CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT, - &ccm->cpu_axi_cfg); - - /* clk = 24*n/p, p is ignored if clock is >288MHz */ - writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 | - CCM_PLL1_CTRL_N(clk / 24000000), - &ccm->pll1_c0_cfg); - while (!(readl(&ccm->pll_stable_status) & 0x01)) {} - - writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 | - CCM_PLL1_CTRL_N(clk / (24000000)), - &ccm->pll1_c1_cfg); - while (!(readl(&ccm->pll_stable_status) & 0x02)) {} - - /* Switch CPU to PLL1 */ - writel(AXI_DIV_2 << AXI0_DIV_SHIFT | - AXI_DIV_2 << AXI1_DIV_SHIFT | - CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT | - CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, - &ccm->cpu_axi_cfg); -} -#endif - -void clock_set_pll5(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - unsigned int div1 = 0, div2 = 0; - - /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */ - writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD | - CCM_PLL5_CTRL_N(clk / (24000000)) | - div2 << CCM_PLL5_DIV2_SHIFT | - div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg); - - udelay(5500); -} - - -unsigned int clock_get_pll6(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - uint32_t rval = readl(&ccm->pll6_cfg); - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); - int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> - CCM_PLL6_CTRL_DIV1_SHIFT) + 1; - int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> - CCM_PLL6_CTRL_DIV2_SHIFT) + 1; - return 24000000 * n / div1 / div2; -} diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c deleted file mode 100644 index 180634c..0000000 --- a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * sun9i specific clock code - * - * (C) Copyright 2015 Hans de Goede - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -void clock_init_uart(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* open the clock for uart */ - setbits_le32(&ccm->apb1_gate, - CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT + - CONFIG_CONS_INDEX - 1)); - /* deassert uart reset */ - setbits_le32(&ccm->apb1_reset_cfg, - 1 << (APB1_RESET_UART_SHIFT + - CONFIG_CONS_INDEX - 1)); - - /* Dup with clock_init_safe(), drop once sun9i SPL support lands */ - writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg); -} - -int clock_twi_onoff(int port, int state) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - if (port > 4) - return -1; - - /* set the apb reset and clock gate for twi */ - if (state) { - setbits_le32(&ccm->apb1_gate, - CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); - setbits_le32(&ccm->apb1_reset_cfg, - 1 << (APB1_RESET_TWI_SHIFT + port)); - } else { - clrbits_le32(&ccm->apb1_reset_cfg, - 1 << (APB1_RESET_TWI_SHIFT + port)); - clrbits_le32(&ccm->apb1_gate, - CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); - } - - return 0; -} - -unsigned int clock_get_pll4_periph0(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll4_periph0_cfg); - int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT); - int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT); - int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1; - const int k = 1; - - return ((24000000 * n * k) >> p) / m; -} diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c deleted file mode 100644 index c0eabdf..0000000 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. - * Tom Cubie - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_MACH_SUN6I -int sunxi_get_ss_bonding_id(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - static int bonding_id = -1; - - if (bonding_id != -1) - return bonding_id; - - /* Enable Security System */ - setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS); - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS); - - bonding_id = readl(SUNXI_SS_BASE); - bonding_id = (bonding_id >> 16) & 0x7; - - /* Disable Security System again */ - clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS); - clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS); - - return bonding_id; -} -#endif - -#ifdef CONFIG_MACH_SUN8I -uint sunxi_get_sram_id(void) -{ - uint id; - - /* Unlock sram info reg, read it, relock */ - setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); - id = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; - clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); - - return id; -} -#endif - -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void) -{ -#ifdef CONFIG_MACH_SUN4I - puts("CPU: Allwinner A10 (SUN4I)\n"); -#elif defined CONFIG_MACH_SUN5I - u32 val = readl(SUNXI_SID_BASE + 0x08); - switch ((val >> 12) & 0xf) { - case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break; - case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break; - case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break; - default: puts("CPU: Allwinner A1X (SUN5I)\n"); - } -#elif defined CONFIG_MACH_SUN6I - switch (sunxi_get_ss_bonding_id()) { - case SUNXI_SS_BOND_ID_A31: - puts("CPU: Allwinner A31 (SUN6I)\n"); - break; - case SUNXI_SS_BOND_ID_A31S: - puts("CPU: Allwinner A31s (SUN6I)\n"); - break; - default: - printf("CPU: Allwinner A31? (SUN6I, id: %d)\n", - sunxi_get_ss_bonding_id()); - } -#elif defined CONFIG_MACH_SUN7I - puts("CPU: Allwinner A20 (SUN7I)\n"); -#elif defined CONFIG_MACH_SUN8I_A23 - printf("CPU: Allwinner A23 (SUN8I %04x)\n", sunxi_get_sram_id()); -#elif defined CONFIG_MACH_SUN8I_A33 - printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id()); -#elif defined CONFIG_MACH_SUN8I_A83T - printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id()); -#elif defined CONFIG_MACH_SUN8I_H3 - printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id()); -#elif defined CONFIG_MACH_SUN9I - puts("CPU: Allwinner A80 (SUN9I)\n"); -#else -#warning Please update cpu_info.c with correct CPU information - puts("CPU: SUNXI Family\n"); -#endif - return 0; -} -#endif - -int sunxi_get_sid(unsigned int *sid) -{ -#ifdef CONFIG_AXP221_POWER - return axp_get_sid(sid); -#elif defined SUNXI_SID_BASE - int i; - - for (i = 0; i< 4; i++) - sid[i] = readl(SUNXI_SID_BASE + 4 * i); - - return 0; -#else - return -ENODEV; -#endif -} diff --git a/arch/arm/cpu/armv7/sunxi/dram_helpers.c b/arch/arm/cpu/armv7/sunxi/dram_helpers.c deleted file mode 100644 index 9a94e1b..0000000 --- a/arch/arm/cpu/armv7/sunxi/dram_helpers.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * DRAM init helper functions - * - * (C) Copyright 2015 Hans de Goede - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * Wait up to 1s for value to be set in given part of reg. - */ -void mctl_await_completion(u32 *reg, u32 mask, u32 val) -{ - unsigned long tmo = timer_get_us() + 1000000; - - while ((readl(reg) & mask) != val) { - if (timer_get_us() > tmo) - panic("Timeout initialising DRAM\n"); - } -} - -/* - * Test if memory at offset offset matches memory at begin of DRAM - */ -bool mctl_mem_matches(u32 offset) -{ - /* Try to write different values to RAM at two addresses */ - writel(0, CONFIG_SYS_SDRAM_BASE); - writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset); - /* Check if the same value is actually observed when reading back */ - return readl(CONFIG_SYS_SDRAM_BASE) == - readl(CONFIG_SYS_SDRAM_BASE + offset); -} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c deleted file mode 100644 index f7b4915..0000000 --- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c +++ /dev/null @@ -1,737 +0,0 @@ -/* - * sunxi DRAM controller initialization - * (C) Copyright 2012 Henrik Nordstrom - * (C) Copyright 2013 Luke Kenneth Casson Leighton - * - * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c - * and earlier U-Boot Allwiner A10 SPL work - * - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. - * Berg Xing - * Tom Cubie - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Unfortunately the only documentation we have on the sun7i DRAM - * controller is Allwinner boot0 + boot1 code, and that code uses - * magic numbers & shifts with no explanations. Hence this code is - * rather undocumented and full of magic. - */ - -#include -#include -#include -#include -#include -#include - -#define CPU_CFG_CHIP_VER(n) ((n) << 6) -#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3) -#define CPU_CFG_CHIP_REV_A 0x0 -#define CPU_CFG_CHIP_REV_C1 0x1 -#define CPU_CFG_CHIP_REV_C2 0x2 -#define CPU_CFG_CHIP_REV_B 0x3 - -/* - * Wait up to 1s for mask to be clear in given reg. - */ -static inline void await_bits_clear(u32 *reg, u32 mask) -{ - mctl_await_completion(reg, mask, 0); -} - -/* - * Wait up to 1s for mask to be set in given reg. - */ -static inline void await_bits_set(u32 *reg, u32 mask) -{ - mctl_await_completion(reg, mask, mask); -} - -/* - * This performs the external DRAM reset by driving the RESET pin low and - * then high again. According to the DDR3 spec, the RESET pin needs to be - * kept low for at least 200 us. - */ -static void mctl_ddr3_reset(void) -{ - struct sunxi_dram_reg *dram = - (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - -#ifdef CONFIG_MACH_SUN4I - struct sunxi_timer_reg *timer = - (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; - u32 reg_val; - - writel(0, &timer->cpu_cfg); - reg_val = readl(&timer->cpu_cfg); - - if ((reg_val & CPU_CFG_CHIP_VER_MASK) != - CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) { - setbits_le32(&dram->mcr, DRAM_MCR_RESET); - udelay(200); - clrbits_le32(&dram->mcr, DRAM_MCR_RESET); - } else -#endif - { - clrbits_le32(&dram->mcr, DRAM_MCR_RESET); - udelay(200); - setbits_le32(&dram->mcr, DRAM_MCR_RESET); - } - /* After the RESET pin is de-asserted, the DDR3 spec requires to wait - * for additional 500 us before driving the CKE pin (Clock Enable) - * high. The duration of this delay can be configured in the SDR_IDCR - * (Initialization Delay Configuration Register) and applied - * automatically by the DRAM controller during the DDR3 initialization - * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and - * can't provide sufficient delay at DRAM clock frequencies higher than - * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to - * 533 MHz according to the datasheet). Additionally, there is no - * official documentation for the SDR_IDCR register anywhere, and - * there is always a chance that we are interpreting it wrong. - * Better be safe than sorry, so add an explicit delay here. */ - udelay(500); -} - -static void mctl_set_drive(void) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - -#ifdef CONFIG_MACH_SUN7I - clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), -#else - clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), -#endif - DRAM_MCR_MODE_EN(0x3) | - 0xffc); -} - -static void mctl_itm_disable(void) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - - clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); -} - -static void mctl_itm_enable(void) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - - clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); -} - -static void mctl_itm_reset(void) -{ - mctl_itm_disable(); - udelay(1); /* ITM reset needs a bit of delay */ - mctl_itm_enable(); - udelay(1); -} - -static void mctl_enable_dll0(u32 phase) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - - clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, - ((phase >> 16) & 0x3f) << 6); - clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE); - udelay(2); - - clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE); - udelay(22); - - clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET); - udelay(22); -} - -/* Get the number of DDR byte lanes */ -static u32 mctl_get_number_of_lanes(void) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) == - DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT)) - return 4; - else - return 2; -} - -/* - * Note: This differs from pm/standby in that it checks the bus width - */ -static void mctl_enable_dllx(u32 phase) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - u32 i, number_of_lanes; - - number_of_lanes = mctl_get_number_of_lanes(); - - for (i = 1; i <= number_of_lanes; i++) { - clrsetbits_le32(&dram->dllcr[i], 0xf << 14, - (phase & 0xf) << 14); - clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET, - DRAM_DLLCR_DISABLE); - phase >>= 4; - } - udelay(2); - - for (i = 1; i <= number_of_lanes; i++) - clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | - DRAM_DLLCR_DISABLE); - udelay(22); - - for (i = 1; i <= number_of_lanes; i++) - clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE, - DRAM_DLLCR_NRESET); - udelay(22); -} - -static u32 hpcr_value[32] = { -#ifdef CONFIG_MACH_SUN5I - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0x1031, 0x1031, 0x0735, 0x1035, - 0x1035, 0x0731, 0x1031, 0, - 0x0301, 0x0301, 0x0301, 0x0301, - 0x0301, 0x0301, 0x0301, 0 -#endif -#ifdef CONFIG_MACH_SUN4I - 0x0301, 0x0301, 0x0301, 0x0301, - 0x0301, 0x0301, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0x1031, 0x1031, 0x0735, 0x5031, - 0x1035, 0x0731, 0x1031, 0x0735, - 0x1035, 0x1031, 0x0731, 0x1035, - 0x1031, 0x0301, 0x0301, 0x0731 -#endif -#ifdef CONFIG_MACH_SUN7I - 0x0301, 0x0301, 0x0301, 0x0301, - 0x0301, 0x0301, 0x0301, 0x0301, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0x1031, 0x1031, 0x0735, 0x1035, - 0x1035, 0x0731, 0x1031, 0x0735, - 0x1035, 0x1031, 0x0731, 0x1035, - 0x0001, 0x1031, 0, 0x1031 - /* last row differs from boot0 source table - * 0x1031, 0x0301, 0x0301, 0x0731 - * but boot0 code skips #28 and #30, and sets #29 and #31 to the - * value from #28 entry (0x1031) - */ -#endif -}; - -static void mctl_configure_hostport(void) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - u32 i; - - for (i = 0; i < 32; i++) - writel(hpcr_value[i], &dram->hpcr[i]); -} - -static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) -{ - u32 reg_val; - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - u32 pll5p_clk, pll6x_clk; - u32 pll5p_div, pll6x_div; - u32 pll5p_rate, pll6x_rate; - - /* setup DRAM PLL */ - reg_val = readl(&ccm->pll5_cfg); - reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */ - reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */ - reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */ - reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */ -#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT - /* Old kernels are hardcoded to P=1 (divide by 2) */ - reg_val |= CCM_PLL5_CTRL_P(1); -#endif - if (clk >= 540 && clk < 552) { - /* dram = 540MHz */ - reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); - reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); - reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); - } else if (clk >= 512 && clk < 528) { - /* dram = 512MHz */ - reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); - reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4)); - reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); - } else if (clk >= 496 && clk < 504) { - /* dram = 496MHz */ - reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); - reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); - reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); - } else if (clk >= 468 && clk < 480) { - /* dram = 468MHz */ - reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); - reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); - reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); - } else if (clk >= 396 && clk < 408) { - /* dram = 396MHz */ - reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); - reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); - reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); - } else { - /* any other frequency that is a multiple of 24 */ - reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); - reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); - reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); - } - reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */ - reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */ - writel(reg_val, &ccm->pll5_cfg); - udelay(5500); - - setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); - -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) - /* reset GPS */ - clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); - setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); - udelay(1); - clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); -#endif - - /* setup MBUS clock */ - if (!mbus_clk) - mbus_clk = 300; - - /* PLL5P and PLL6 are the potential clock sources for MBUS */ - pll6x_clk = clock_get_pll6() / 1000000; -#ifdef CONFIG_MACH_SUN7I - pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ -#endif - pll5p_clk = clock_get_pll5p() / 1000000; - pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk); - pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk); - pll6x_rate = pll6x_clk / pll6x_div; - pll5p_rate = pll5p_clk / pll5p_div; - - if (pll6x_div <= 16 && pll6x_rate > pll5p_rate) { - /* use PLL6 as the MBUS clock source */ - reg_val = CCM_MBUS_CTRL_GATE | - CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) | - CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | - CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll6x_div)); - } else if (pll5p_div <= 16) { - /* use PLL5P as the MBUS clock source */ - reg_val = CCM_MBUS_CTRL_GATE | - CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) | - CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | - CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll5p_div)); - } else { - panic("Bad mbus_clk\n"); - } - writel(reg_val, &ccm->mbus_clk_cfg); - - /* - * open DRAMC AHB & DLL register clock - * close it first - */ -#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) - clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); -#else - clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); -#endif - udelay(22); - - /* then open it */ -#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) - setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); -#else - setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); -#endif - udelay(22); -} - -/* - * The data from rslrX and rdgrX registers (X=rank) is stored - * in a single 32-bit value using the following format: - * bits [31:26] - DQS gating system latency for byte lane 3 - * bits [25:24] - DQS gating phase select for byte lane 3 - * bits [23:18] - DQS gating system latency for byte lane 2 - * bits [17:16] - DQS gating phase select for byte lane 2 - * bits [15:10] - DQS gating system latency for byte lane 1 - * bits [ 9:8 ] - DQS gating phase select for byte lane 1 - * bits [ 7:2 ] - DQS gating system latency for byte lane 0 - * bits [ 1:0 ] - DQS gating phase select for byte lane 0 - */ -static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - u32 lane, number_of_lanes = mctl_get_number_of_lanes(); - /* rank0 gating system latency (3 bits per lane: cycles) */ - u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1); - /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */ - u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1); - for (lane = 0; lane < number_of_lanes; lane++) { - u32 tmp = dqs_gating_delay >> (lane * 8); - slr &= ~(7 << (lane * 3)); - slr |= ((tmp >> 2) & 7) << (lane * 3); - dgr &= ~(3 << (lane * 2)); - dgr |= (tmp & 3) << (lane * 2); - } - writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1); - writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1); -} - -static int dramc_scan_readpipe(void) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - u32 reg_val; - - /* data training trigger */ - clrbits_le32(&dram->csr, DRAM_CSR_FAILED); - setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); - - /* check whether data training process has completed */ - await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING); - - /* check data training result */ - reg_val = readl(&dram->csr); - if (reg_val & DRAM_CSR_FAILED) - return -1; - - return 0; -} - -static void dramc_clock_output_en(u32 on) -{ -#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - - if (on) - setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); - else - clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); -#endif -#ifdef CONFIG_MACH_SUN4I - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (on) - setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); - else - clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); -#endif -} - -/* tRFC in nanoseconds for different densities (from the DDR3 spec) */ -static const u16 tRFC_DDR3_table[6] = { - /* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */ - 90, 90, 110, 160, 300, 350 -}; - -static void dramc_set_autorefresh_cycle(u32 clk, u32 density) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - u32 tRFC, tREFI; - - tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000; - tREFI = (7987 * clk) >> 10; /* <= 7.8us */ - - writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr); -} - -/* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */ -static u32 ddr3_write_recovery(u32 clk) -{ - u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */ - u32 twr_ck = (twr_ns * clk + 999) / 1000; - if (twr_ck < 5) - return 1; - else if (twr_ck <= 8) - return twr_ck - 4; - else if (twr_ck <= 10) - return 5; - else - return 6; -} - -/* - * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this - * means that DRAM is currently in self-refresh mode and retaining the old - * data. Since we have no idea what to do in this situation yet, just set this - * register to 0 and initialize DRAM in the same way as on any normal reboot - * (discarding whatever was stored there). - * - * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic - * value for this write operation to have any effect. On sun5i hadware this - * magic value is not necessary. And on sun4i hardware the writes to this - * register seem to have no effect at all. - */ -static void mctl_disable_power_save(void) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - writel(0x16510000, &dram->ppwrsctl); -} - -/* - * After the DRAM is powered up or reset, the DDR3 spec requires to wait at - * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct - * (SDR_IDCR) register appears to configure this delay, which gets applied - * right at the time when the DRAM initialization is activated in the - * 'mctl_ddr3_initialize' function. - */ -static void mctl_set_cke_delay(void) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - - /* The CKE delay is represented in DRAM clock cycles, multiplied by N - * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to - * the maximum possible value 0x1ffff, just like in the Allwinner's - * boot0 bootloader. The resulting delay value is somewhere between - * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i - * with 360 MHz DRAM clock speed). */ - setbits_le32(&dram->idcr, 0x1ffff); -} - -/* - * This triggers the DRAM initialization. It performs sending the mode registers - * to the DRAM among other things. Very likely the ZQCL command is also getting - * executed (to do the initial impedance calibration on the DRAM side of the - * wire). The memory controller and the PHY must be already configured before - * calling this function. - */ -static void mctl_ddr3_initialize(void) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - setbits_le32(&dram->ccr, DRAM_CCR_INIT); - await_bits_clear(&dram->ccr, DRAM_CCR_INIT); -} - -/* - * Perform impedance calibration on the DRAM controller side of the wire. - */ -static void mctl_set_impedance(u32 zq, bool odt_en) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - u32 reg_val; - u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF; - -#ifndef CONFIG_MACH_SUN7I - /* Appears that some kind of automatically initiated default - * ZQ calibration is already in progress at this point on sun4i/sun5i - * hardware, but not on sun7i. So it is reasonable to wait for its - * completion before doing anything else. */ - await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE); -#endif - - /* ZQ calibration is not really useful unless ODT is enabled */ - if (!odt_en) - return; - -#ifdef CONFIG_MACH_SUN7I - /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock - * unless bit 24 is set in SDR_ZQCR1. Not much is known about the - * SDR_ZQCR1 register, but there are hints indicating that it might - * be related to periodic impedance re-calibration. This particular - * magic value is borrowed from the Allwinner boot0 bootloader, and - * using it helps to avoid troubles */ - writel((1 << 24) | (1 << 1), &dram->zqcr1); -#endif - - /* Needed at least for sun5i, because it does not self clear there */ - clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); - - if (zdata) { - /* Set the user supplied impedance data */ - reg_val = DRAM_ZQCR0_ZDEN | zdata; - writel(reg_val, &dram->zqcr0); - /* no need to wait, this takes effect immediately */ - } else { - /* Do the calibration using the external resistor */ - reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog); - writel(reg_val, &dram->zqcr0); - /* Wait for the new impedance configuration to settle */ - await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE); - } - - /* Needed at least for sun5i, because it does not self clear there */ - clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); - - /* Set I/O configure register */ - writel(DRAM_IOCR_ODT_EN, &dram->iocr); -} - -static unsigned long dramc_init_helper(struct dram_para *para) -{ - struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - u32 reg_val; - u32 density; - int ret_val; - - /* - * only single rank DDR3 is supported by this code even though the - * hardware can theoretically support DDR2 and up to two ranks - */ - if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1) - return 0; - - /* setup DRAM relative clock */ - mctl_setup_dram_clock(para->clock, para->mbus_clock); - - /* Disable any pad power save control */ - mctl_disable_power_save(); - - mctl_set_drive(); - - /* dram clock off */ - dramc_clock_output_en(0); - -#ifdef CONFIG_MACH_SUN4I - /* select dram controller 1 */ - writel(DRAM_CSEL_MAGIC, &dram->csel); -#endif - - mctl_itm_disable(); - mctl_enable_dll0(para->tpr3); - - /* configure external DRAM */ - reg_val = DRAM_DCR_TYPE_DDR3; - reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3); - - if (para->density == 256) - density = DRAM_DCR_CHIP_DENSITY_256M; - else if (para->density == 512) - density = DRAM_DCR_CHIP_DENSITY_512M; - else if (para->density == 1024) - density = DRAM_DCR_CHIP_DENSITY_1024M; - else if (para->density == 2048) - density = DRAM_DCR_CHIP_DENSITY_2048M; - else if (para->density == 4096) - density = DRAM_DCR_CHIP_DENSITY_4096M; - else if (para->density == 8192) - density = DRAM_DCR_CHIP_DENSITY_8192M; - else - density = DRAM_DCR_CHIP_DENSITY_256M; - - reg_val |= DRAM_DCR_CHIP_DENSITY(density); - reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1); - reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1); - reg_val |= DRAM_DCR_CMD_RANK_ALL; - reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE); - writel(reg_val, &dram->dcr); - - dramc_clock_output_en(1); - - mctl_set_impedance(para->zq, para->odt_en); - - mctl_set_cke_delay(); - - mctl_ddr3_reset(); - - udelay(1); - - await_bits_clear(&dram->ccr, DRAM_CCR_INIT); - - mctl_enable_dllx(para->tpr3); - - /* set refresh period */ - dramc_set_autorefresh_cycle(para->clock, density); - - /* set timing parameters */ - writel(para->tpr0, &dram->tpr0); - writel(para->tpr1, &dram->tpr1); - writel(para->tpr2, &dram->tpr2); - - reg_val = DRAM_MR_BURST_LENGTH(0x0); -#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)) - reg_val |= DRAM_MR_POWER_DOWN; -#endif - reg_val |= DRAM_MR_CAS_LAT(para->cas - 4); - reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock)); - writel(reg_val, &dram->mr); - - writel(para->emr1, &dram->emr); - writel(para->emr2, &dram->emr2); - writel(para->emr3, &dram->emr3); - - /* disable drift compensation and set passive DQS window mode */ - clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); - -#ifdef CONFIG_MACH_SUN7I - /* Command rate timing mode 2T & 1T */ - if (para->tpr4 & 0x1) - setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T); -#endif - /* initialize external DRAM */ - mctl_ddr3_initialize(); - - /* scan read pipe value */ - mctl_itm_enable(); - - /* Hardware DQS gate training */ - ret_val = dramc_scan_readpipe(); - - if (ret_val < 0) - return 0; - - /* allow to override the DQS training results with a custom delay */ - if (para->dqs_gating_delay) - mctl_set_dqs_gating_delay(0, para->dqs_gating_delay); - - /* set the DQS gating window type */ - if (para->active_windowing) - clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE); - else - setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE); - - mctl_itm_reset(); - - /* configure all host port */ - mctl_configure_hostport(); - - return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); -} - -unsigned long dramc_init(struct dram_para *para) -{ - unsigned long dram_size, actual_density; - - /* If the dram configuration is not provided, use a default */ - if (!para) - return 0; - - /* if everything is known, then autodetection is not necessary */ - if (para->io_width && para->bus_width && para->density) - return dramc_init_helper(para); - - /* try to autodetect the DRAM bus width and density */ - para->io_width = 16; - para->bus_width = 32; -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) - /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */ - para->density = 4096; -#else - /* all A0-A15 address lines on A20, which allow density 8192 */ - para->density = 8192; -#endif - - dram_size = dramc_init_helper(para); - if (!dram_size) { - /* if 32-bit bus width failed, try 16-bit bus width instead */ - para->bus_width = 16; - dram_size = dramc_init_helper(para); - if (!dram_size) { - /* if 16-bit bus width also failed, then bail out */ - return dram_size; - } - } - - /* check if we need to adjust the density */ - actual_density = (dram_size >> 17) * para->io_width / para->bus_width; - - if (actual_density != para->density) { - /* update the density and re-initialize DRAM again */ - para->density = actual_density; - dram_size = dramc_init_helper(para); - } - - return dram_size; -} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c deleted file mode 100644 index 5dbbf61..0000000 --- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Sun6i platform dram controller init. - * - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. - * Berg Xing - * Tom Cubie - * - * (C) Copyright 2014 Hans de Goede - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include - -#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000) - -struct dram_sun6i_para { - u8 bus_width; - u8 chan; - u8 rank; - u8 rows; - u16 page_size; -}; - -static void mctl_sys_init(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - const int dram_clk_div = 2; - - clock_set_pll5(DRAM_CLK * dram_clk_div, false); - - clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, - CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST | - CCM_DRAMCLK_CFG_UPD); - mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); - - writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg); - - /* deassert mctl reset */ - setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); - - /* enable mctl clock */ - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); -} - -static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para) -{ - struct sunxi_mctl_phy_reg *mctl_phy; - - if (ch_index == 0) - mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; - else - mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; - - /* disable + reset dlls */ - writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr); - writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr); - writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr); - if (para->bus_width == 32) { - writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr); - writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr); - } - udelay(2); - - /* enable + reset dlls */ - writel(0, &mctl_phy->acdllcr); - writel(0, &mctl_phy->dx0dllcr); - writel(0, &mctl_phy->dx1dllcr); - if (para->bus_width == 32) { - writel(0, &mctl_phy->dx2dllcr); - writel(0, &mctl_phy->dx3dllcr); - } - udelay(22); - - /* enable and release reset of dlls */ - writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr); - writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr); - writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr); - if (para->bus_width == 32) { - writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr); - writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr); - } - udelay(22); -} - -static bool mctl_rank_detect(u32 *gsr0, int rank) -{ - const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank; - const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank; - - mctl_await_completion(gsr0, done, done); - mctl_await_completion(gsr0 + 0x10, done, done); - - return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err); -} - -static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_mctl_ctl_reg *mctl_ctl; - struct sunxi_mctl_phy_reg *mctl_phy; - - if (ch_index == 0) { - mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; - } else { - mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE; - mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; - } - - writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd); - mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0); - - /* PHY initialization */ - writel(MCTL_PGCR, &mctl_phy->pgcr); - writel(MCTL_MR0, &mctl_phy->mr0); - writel(MCTL_MR1, &mctl_phy->mr1); - writel(MCTL_MR2, &mctl_phy->mr2); - writel(MCTL_MR3, &mctl_phy->mr3); - - writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST, - &mctl_phy->ptr0); - - writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1); - writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2); - - writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) | - (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) | - (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0), - &mctl_phy->dtpr0); - - writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) | - (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) | - ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) | - (MCTL_TAOND << 0), &mctl_phy->dtpr1); - - writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) | - (MCTL_TEXSR << 0), &mctl_phy->dtpr2); - - writel(1, &mctl_ctl->dfitphyupdtype0); - writel(MCTL_DCR_DDR3, &mctl_phy->dcr); - writel(MCTL_DSGCR, &mctl_phy->dsgcr); - writel(MCTL_DXCCR, &mctl_phy->dxccr); - writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr); - writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr); - writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr); - writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr); - - mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03); - - writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1); - - setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); - writel(MCTL_PIR_STEP1, &mctl_phy->pir); - udelay(10); - mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f); - - /* rank detect */ - if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) { - para->rank = 1; - clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK); - } - - /* - * channel detect, check channel 1 dx0 and dx1 have rank 0, if not - * assume nothing is connected to channel 1. - */ - if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) { - para->chan = 1; - clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); - return; - } - - /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */ - if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) { - para->bus_width = 16; - para->page_size = 2048; - setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE); - setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE); - clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN); - clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN); - } - - setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); - writel(MCTL_PIR_STEP2, &mctl_phy->pir); - udelay(10); - mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11); - - if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK) - panic("Training error initialising DRAM\n"); - - /* Move to configure state */ - writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl); - mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01); - - /* Set number of clks per micro-second */ - writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u); - /* Set number of clks per 100 nano-seconds */ - writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n); - /* Set memory timing registers */ - writel(MCTL_TREFI, &mctl_ctl->trefi); - writel(MCTL_TMRD, &mctl_ctl->tmrd); - writel(MCTL_TRFC, &mctl_ctl->trfc); - writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp); - writel(MCTL_TRTW, &mctl_ctl->trtw); - writel(MCTL_TAL, &mctl_ctl->tal); - writel(MCTL_TCL, &mctl_ctl->tcl); - writel(MCTL_TCWL, &mctl_ctl->tcwl); - writel(MCTL_TRAS, &mctl_ctl->tras); - writel(MCTL_TRC, &mctl_ctl->trc); - writel(MCTL_TRCD, &mctl_ctl->trcd); - writel(MCTL_TRRD, &mctl_ctl->trrd); - writel(MCTL_TRTP, &mctl_ctl->trtp); - writel(MCTL_TWR, &mctl_ctl->twr); - writel(MCTL_TWTR, &mctl_ctl->twtr); - writel(MCTL_TEXSR, &mctl_ctl->texsr); - writel(MCTL_TXP, &mctl_ctl->txp); - writel(MCTL_TXPDLL, &mctl_ctl->txpdll); - writel(MCTL_TZQCS, &mctl_ctl->tzqcs); - writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi); - writel(MCTL_TDQS, &mctl_ctl->tdqs); - writel(MCTL_TCKSRE, &mctl_ctl->tcksre); - writel(MCTL_TCKSRX, &mctl_ctl->tcksrx); - writel(MCTL_TCKE, &mctl_ctl->tcke); - writel(MCTL_TMOD, &mctl_ctl->tmod); - writel(MCTL_TRSTL, &mctl_ctl->trstl); - writel(MCTL_TZQCL, &mctl_ctl->tzqcl); - writel(MCTL_TMRR, &mctl_ctl->tmrr); - writel(MCTL_TCKESR, &mctl_ctl->tckesr); - writel(MCTL_TDPD, &mctl_ctl->tdpd); - - /* Unknown magic performed by boot0 */ - setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3); - clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f); - - /* Select 16/32-bits mode for MCTL */ - if (para->bus_width == 16) - setbits_le32(&mctl_ctl->ppcfg, 1); - - /* Set DFI timing registers */ - writel(MCTL_TCWL, &mctl_ctl->dfitphywrl); - writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden); - writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl); - writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0); - - writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg); - - /* DFI update configuration register */ - writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg); - - /* Move to access state */ - writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl); - mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x03); -} - -static void mctl_com_init(struct dram_sun6i_para *para) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_mctl_phy_reg * const mctl_phy1 = - (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; - struct sunxi_prcm_reg * const prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; - - writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 | - ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) | - MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | - MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); - - /* Unknown magic performed by boot0 */ - setbits_le32(&mctl_com->dbgcr, (1 << 6)); - - if (para->chan == 1) { - /* Shutdown channel 1 */ - setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE); - setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE); - clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE); - /* - * CH0 ?? this is what boot0 does. Leave as is until we can - * confirm this. - */ - setbits_le32(&prcm->vdd_sys_pwroff, - PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF); - } -} - -static void mctl_port_cfg(void) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* enable DRAM AXI clock for CPU access */ - setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM); - - /* Bunch of magic writes performed by boot0 */ - writel(0x00400302, &mctl_com->rmcr[0]); - writel(0x01000307, &mctl_com->rmcr[1]); - writel(0x00400302, &mctl_com->rmcr[2]); - writel(0x01000307, &mctl_com->rmcr[3]); - writel(0x01000307, &mctl_com->rmcr[4]); - writel(0x01000303, &mctl_com->rmcr[6]); - writel(0x01000303, &mctl_com->mmcr[0]); - writel(0x00400310, &mctl_com->mmcr[1]); - writel(0x01000307, &mctl_com->mmcr[2]); - writel(0x01000303, &mctl_com->mmcr[3]); - writel(0x01800303, &mctl_com->mmcr[4]); - writel(0x01800303, &mctl_com->mmcr[5]); - writel(0x01800303, &mctl_com->mmcr[6]); - writel(0x01800303, &mctl_com->mmcr[7]); - writel(0x01000303, &mctl_com->mmcr[8]); - writel(0x00000002, &mctl_com->mmcr[15]); - writel(0x00000310, &mctl_com->mbagcr[0]); - writel(0x00400310, &mctl_com->mbagcr[1]); - writel(0x00400310, &mctl_com->mbagcr[2]); - writel(0x00000307, &mctl_com->mbagcr[3]); - writel(0x00000317, &mctl_com->mbagcr[4]); - writel(0x00000307, &mctl_com->mbagcr[5]); -} - -unsigned long sunxi_dram_init(void) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - u32 offset; - int bank, bus, columns; - - /* Set initial parameters, these get modified by the autodetect code */ - struct dram_sun6i_para para = { - .bus_width = 32, - .chan = 2, - .rank = 2, - .page_size = 4096, - .rows = 16, - }; - - /* A31s only has one channel */ - if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S) - para.chan = 1; - - mctl_sys_init(); - - mctl_dll_init(0, ¶); - setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); - - if (para.chan == 2) { - mctl_dll_init(1, ¶); - setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); - } - - setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN); - - mctl_channel_init(0, ¶); - if (para.chan == 2) - mctl_channel_init(1, ¶); - - mctl_com_init(¶); - mctl_port_cfg(); - - /* - * Change to 1 ch / sequence / 8192 byte pages / 16 rows / - * 8 bit banks / 1 rank mode. - */ - clrsetbits_le32(&mctl_com->cr, - MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK | - MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, - MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE | - MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) | - MCTL_CR_BANK(1) | MCTL_CR_RANK(1)); - - /* Detect and set page size */ - for (columns = 7; columns < 20; columns++) { - if (mctl_mem_matches(1 << columns)) - break; - } - bus = (para.bus_width == 32) ? 2 : 1; - columns -= bus; - para.page_size = (1 << columns) * (bus << 1); - clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK, - MCTL_CR_PAGE_SIZE(para.page_size)); - - /* Detect and set rows */ - for (para.rows = 11; para.rows < 16; para.rows++) { - offset = 1 << (para.rows + columns + bus); - if (mctl_mem_matches(offset)) - break; - } - clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, - MCTL_CR_ROW(para.rows)); - - /* Detect bank size */ - offset = 1 << (para.rows + columns + bus + 2); - bank = mctl_mem_matches(offset) ? 0 : 1; - - /* Restore interleave, chan and rank values, set bank size */ - clrsetbits_le32(&mctl_com->cr, - MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE | - MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, - MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) | - MCTL_CR_RANK(para.rank)); - - return 1 << (para.rank + para.rows + bank + columns + para.chan + bus); -} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c deleted file mode 100644 index c53671a..0000000 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Sun8i platform dram controller init. - * - * (C) Copyright 2014 Hans de Goede - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Note this code uses a lot of magic hex values, that is because this code - * simply replays the init sequence as done by the Allwinner boot0 code, so - * we do not know what these values mean. There are no symbolic constants for - * these magic values, since we do not know how to name them and making up - * names for them is not useful. - * - * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one - * found in the TI Keystone2 documentation: - * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf - * "Table4-2 DDR3 PHY Registers" - * This may be used as a (possible) reference for future work / cleanups. - */ - -#include -#include -#include -#include -#include -#include - -static const struct dram_para dram_para = { - .clock = CONFIG_DRAM_CLK, - .type = 3, - .zq = CONFIG_DRAM_ZQ, - .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), - .odt_correction = CONFIG_DRAM_ODT_CORRECTION, - .para1 = 0, /* not used (only used when tpr13 bit 31 is set */ - .para2 = 0, /* not used (only used when tpr13 bit 31 is set */ - .mr0 = 6736, - .mr1 = 4, - .mr2 = 16, - .mr3 = 0, - /* tpr0 - 10 contain timing constants or-ed together in u32 vals */ - .tpr0 = 0x2ab83def, - .tpr1 = 0x18082356, - .tpr2 = 0x00034156, - .tpr3 = 0x448c5533, - .tpr4 = 0x08010d00, - .tpr5 = 0x0340b20f, - .tpr6 = 0x20d118cc, - .tpr7 = 0x14062485, - .tpr8 = 0x220d1d52, - .tpr9 = 0x1e078c22, - .tpr10 = 0x3c, - .tpr11 = 0, /* not used */ - .tpr12 = 0, /* not used */ - .tpr13 = 0x30000, -}; - -static void mctl_sys_init(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* enable pll5, note the divide by 2 is deliberate! */ - clock_set_pll5(dram_para.clock * 1000000 / 2, - dram_para.tpr13 & 0x40000); - - /* deassert ahb mctl reset */ - setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); - - /* enable ahb mctl clock */ - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); -} - -static void mctl_apply_odt_correction(u32 *reg, int correction) -{ - int val; - - val = (readl(reg) >> 8) & 0xff; - val += correction; - - /* clamp */ - if (val < 0) - val = 0; - else if (val > 255) - val = 255; - - clrsetbits_le32(reg, 0xff00, val << 8); -} - -static void mctl_init(u32 *bus_width) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - struct sunxi_mctl_phy_reg * const mctl_phy = - (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; - - if (dram_para.tpr13 & 0x20) - writel(0x40b, &mctl_phy->dcr); - else - writel(0x1000040b, &mctl_phy->dcr); - - if (dram_para.clock >= 480) - writel(0x5c000, &mctl_phy->dllgcr); - else - writel(0xdc000, &mctl_phy->dllgcr); - - writel(0x0a003e3f, &mctl_phy->pgcr0); - writel(0x03008421, &mctl_phy->pgcr1); - - writel(dram_para.mr0, &mctl_phy->mr0); - writel(dram_para.mr1, &mctl_phy->mr1); - writel(dram_para.mr2, &mctl_phy->mr2); - writel(dram_para.mr3, &mctl_phy->mr3); - - if (!(dram_para.tpr13 & 0x10000)) { - clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000); - clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000); - } - - /* - * All the masking and shifting below converts what I assume are DDR - * timing constants from Allwinner dram_para tpr format to the actual - * timing registers format. - */ - - writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2); - writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3); - writel((dram_para.tpr0 & 0x3ff00000) >> 2 | - (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4); - - writel(dram_para.tpr3, &mctl_phy->dtpr0); - writel(dram_para.tpr4, &mctl_phy->dtpr2); - - writel(0x01000081, &mctl_phy->dtcr); - - if (dram_para.clock <= 240 || !dram_para.odt_en) { - clrbits_le32(&mctl_phy->dx0gcr, 0x600); - clrbits_le32(&mctl_phy->dx1gcr, 0x600); - } - if (dram_para.clock <= 240) { - writel(0, &mctl_phy->odtcr); - writel(0, &mctl_ctl->odtmap); - } - - writel(((dram_para.tpr5 & 0x0f00) << 12) | - ((dram_para.tpr5 & 0x00f8) << 9) | - ((dram_para.tpr5 & 0x0007) << 8), - &mctl_ctl->rfshctl0); - - writel(((dram_para.tpr5 & 0x0003f000) << 12) | - ((dram_para.tpr5 & 0x00fc0000) >> 2) | - ((dram_para.tpr5 & 0x3f000000) >> 16) | - ((dram_para.tpr6 & 0x0000003f) >> 0), - &mctl_ctl->dramtmg0); - - writel(((dram_para.tpr6 & 0x000007c0) << 10) | - ((dram_para.tpr6 & 0x0000f800) >> 3) | - ((dram_para.tpr6 & 0x003f0000) >> 16), - &mctl_ctl->dramtmg1); - - writel(((dram_para.tpr6 & 0x0fc00000) << 2) | - ((dram_para.tpr7 & 0x0000001f) << 16) | - ((dram_para.tpr7 & 0x000003e0) << 3) | - ((dram_para.tpr7 & 0x0000fc00) >> 10), - &mctl_ctl->dramtmg2); - - writel(((dram_para.tpr7 & 0x03ff0000) >> 16) | - ((dram_para.tpr6 & 0xf0000000) >> 16), - &mctl_ctl->dramtmg3); - - writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) | - ((dram_para.tpr8 & 0x00000007) << 16) | - ((dram_para.tpr8 & 0x00000038) << 5) | - ((dram_para.tpr8 & 0x000003c0) >> 6), - &mctl_ctl->dramtmg4); - - writel(((dram_para.tpr8 & 0x00003c00) << 14) | - ((dram_para.tpr8 & 0x0003c000) << 2) | - ((dram_para.tpr8 & 0x00fc0000) >> 10) | - ((dram_para.tpr8 & 0x0f000000) >> 24), - &mctl_ctl->dramtmg5); - - writel(0x00000008, &mctl_ctl->dramtmg8); - - writel(((dram_para.tpr8 & 0xf0000000) >> 4) | - ((dram_para.tpr9 & 0x00007c00) << 6) | - ((dram_para.tpr9 & 0x000003e0) << 3) | - ((dram_para.tpr9 & 0x0000001f) >> 0), - &mctl_ctl->pitmg0); - - setbits_le32(&mctl_ctl->pitmg1, 0x80000); - - writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001, - &mctl_ctl->sched); - - writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); - writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); - - writel(0x00000000, &mctl_ctl->pimisc); - writel(0x80000000, &mctl_ctl->upd0); - - writel(((dram_para.tpr9 & 0xffc00000) >> 22) | - ((dram_para.tpr10 & 0x00000fff) << 16), - &mctl_ctl->rfshtmg); - - if (dram_para.tpr13 & 0x20) - writel(0x01040001, &mctl_ctl->mstr); - else - writel(0x01040401, &mctl_ctl->mstr); - - if (!(dram_para.tpr13 & 0x20000)) { - writel(0x00000002, &mctl_ctl->pwrctl); - writel(0x00008001, &mctl_ctl->pwrtmg); - } - - writel(0x00000001, &mctl_ctl->rfshctl3); - writel(0x00000001, &mctl_ctl->pimisc); - - /* deassert dram_clk_cfg reset */ - setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); - - setbits_le32(&mctl_com->ccr, 0x80000); - - /* zq stuff */ - writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1); - - writel(0x00000003, &mctl_phy->pir); - udelay(10); - mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09); - - writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2); - writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); - - /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */ - writel(0x000005f3, &mctl_phy->pir); - udelay(10); - mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03); - - if (readl(&mctl_phy->dx1gsr0) & 0x1000000) { - *bus_width = 8; - writel(0, &mctl_phy->dx1gcr); - writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); - writel(0x5f3, &mctl_phy->pir); - udelay(10000); - setbits_le32(&mctl_ctl->mstr, 0x1000); - } else - *bus_width = 16; - - if (dram_para.odt_correction) { - mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, - dram_para.odt_correction); - mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, - dram_para.odt_correction); - } - - mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01); - - writel(0x08003e3f, &mctl_phy->pgcr0); - writel(0x00000000, &mctl_ctl->rfshctl3); -} - -unsigned long sunxi_dram_init(void) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - const u32 columns = 13; - u32 bus, bus_width, offset, page_size, rows; - - mctl_sys_init(); - mctl_init(&bus_width); - - if (bus_width == 16) { - page_size = 8; - bus = 1; - } else { - page_size = 7; - bus = 0; - } - - if (!(dram_para.tpr13 & 0x80000000)) { - /* Detect and set rows */ - writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size), - &mctl_com->cr); - setbits_le32(&mctl_com->swonr, 0x0003ffff); - for (rows = 11; rows < 16; rows++) { - offset = 1 << (rows + columns + bus); - if (mctl_mem_matches(offset)) - break; - } - clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, - MCTL_CR_ROW(rows)); - } else { - rows = (dram_para.para1 >> 16) & 0xff; - writel(((dram_para.para2 & 0x000000f0) << 11) | - ((rows - 1) << 4) | - ((dram_para.para1 & 0x0f000000) >> 22) | - 0x31000 | MCTL_CR_PAGE_SIZE(page_size), - &mctl_com->cr); - setbits_le32(&mctl_com->swonr, 0x0003ffff); - } - - /* Setup DRAM master priority? If this is left out things still work */ - writel(0x00000008, &mctl_com->mcr0_0); - writel(0x0001000d, &mctl_com->mcr1_0); - writel(0x00000004, &mctl_com->mcr0_1); - writel(0x00000080, &mctl_com->mcr1_1); - writel(0x00000004, &mctl_com->mcr0_2); - writel(0x00000019, &mctl_com->mcr1_2); - writel(0x00000004, &mctl_com->mcr0_3); - writel(0x00000080, &mctl_com->mcr1_3); - writel(0x00000004, &mctl_com->mcr0_4); - writel(0x01010040, &mctl_com->mcr1_4); - writel(0x00000004, &mctl_com->mcr0_5); - writel(0x0001002f, &mctl_com->mcr1_5); - writel(0x00000004, &mctl_com->mcr0_6); - writel(0x00010020, &mctl_com->mcr1_6); - writel(0x00000004, &mctl_com->mcr0_7); - writel(0x00010020, &mctl_com->mcr1_7); - writel(0x00000008, &mctl_com->mcr0_8); - writel(0x00000001, &mctl_com->mcr1_8); - writel(0x00000008, &mctl_com->mcr0_9); - writel(0x00000005, &mctl_com->mcr1_9); - writel(0x00000008, &mctl_com->mcr0_10); - writel(0x00000003, &mctl_com->mcr1_10); - writel(0x00000008, &mctl_com->mcr0_11); - writel(0x00000005, &mctl_com->mcr1_11); - writel(0x00000008, &mctl_com->mcr0_12); - writel(0x00000003, &mctl_com->mcr1_12); - writel(0x00000008, &mctl_com->mcr0_13); - writel(0x00000004, &mctl_com->mcr1_13); - writel(0x00000008, &mctl_com->mcr0_14); - writel(0x00000002, &mctl_com->mcr1_14); - writel(0x00000008, &mctl_com->mcr0_15); - writel(0x00000003, &mctl_com->mcr1_15); - writel(0x00010138, &mctl_com->bwcr); - - return 1 << (rows + columns + bus); -} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c deleted file mode 100644 index fa1620c..0000000 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Sun8i a33 platform dram controller init. - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang - * (C) Copyright 2015 Vishnu Patekar - * (C) Copyright 2015 Hans de Goede - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include - -/* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */ -#define DRAM_CLK_MUL 2 -#define DRAM_CLK_DIV 4 -#define DRAM_SIGMA_DELTA_ENABLE 1 - -struct dram_para { - u8 cs1; - u8 seq; - u8 bank; - u8 rank; - u8 rows; - u8 bus_width; - u16 page_size; -}; - -static void mctl_set_cr(struct dram_para *para) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - - writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | - MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 | - (para->seq ? MCTL_CR_SEQUENCE : 0) | - ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | - MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | - MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), - &mctl_com->cr); -} - -static void auto_detect_dram_size(struct dram_para *para) -{ - u8 orig_rank = para->rank; - int rows, columns; - - /* Row detect */ - para->page_size = 512; - para->seq = 1; - para->rows = 16; - para->rank = 1; - mctl_set_cr(para); - for (rows = 11 ; rows < 16 ; rows++) { - if (mctl_mem_matches(1 << (rows + 9))) /* row-column */ - break; - } - - /* Column (page size) detect */ - para->rows = 11; - para->page_size = 8192; - mctl_set_cr(para); - for (columns = 9 ; columns < 13 ; columns++) { - if (mctl_mem_matches(1 << columns)) - break; - } - - para->seq = 0; - para->rank = orig_rank; - para->rows = rows; - para->page_size = 1 << columns; - mctl_set_cr(para); -} - -static inline int ns_to_t(int nanoseconds) -{ - const unsigned int ctrl_freq = - CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV; - - return (ctrl_freq * nanoseconds + 999) / 1000; -} - -static void auto_set_timing_para(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - u32 reg_val; - - u8 tccd = 2; - u8 tfaw = ns_to_t(50); - u8 trrd = max(ns_to_t(10), 4); - u8 trcd = ns_to_t(15); - u8 trc = ns_to_t(53); - u8 txp = max(ns_to_t(8), 3); - u8 twtr = max(ns_to_t(8), 4); - u8 trtp = max(ns_to_t(8), 4); - u8 twr = max(ns_to_t(15), 3); - u8 trp = ns_to_t(15); - u8 tras = ns_to_t(38); - - u16 trefi = ns_to_t(7800) / 32; - u16 trfc = ns_to_t(350); - - /* Fixed timing parameters */ - u8 tmrw = 0; - u8 tmrd = 4; - u8 tmod = 12; - u8 tcke = 3; - u8 tcksrx = 5; - u8 tcksre = 5; - u8 tckesr = 4; - u8 trasmax = 24; - u8 tcl = 6; /* CL 12 */ - u8 tcwl = 4; /* CWL 8 */ - u8 t_rdata_en = 4; - u8 wr_latency = 2; - - u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ - u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ - u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ - u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ - - u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ - u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ - u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ - - /* Set work mode register */ - mctl_set_cr(para); - /* Set mode register */ - writel(MCTL_MR0, &mctl_ctl->mr0); - writel(MCTL_MR1, &mctl_ctl->mr1); - writel(MCTL_MR2, &mctl_ctl->mr2); - writel(MCTL_MR3, &mctl_ctl->mr3); - /* Set dram timing */ - reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); - writel(reg_val, &mctl_ctl->dramtmg0); - reg_val = (txp << 16) | (trtp << 8) | (trc << 0); - writel(reg_val, &mctl_ctl->dramtmg1); - reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); - writel(reg_val, &mctl_ctl->dramtmg2); - reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); - writel(reg_val, &mctl_ctl->dramtmg3); - reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); - writel(reg_val, &mctl_ctl->dramtmg4); - reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); - writel(reg_val, &mctl_ctl->dramtmg5); - /* Set two rank timing and exit self-refresh timing */ - reg_val = readl(&mctl_ctl->dramtmg8); - reg_val &= ~(0xff << 8); - reg_val &= ~(0xff << 0); - reg_val |= (0x33 << 8); - reg_val |= (0x8 << 0); - writel(reg_val, &mctl_ctl->dramtmg8); - /* Set phy interface time */ - reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) - | (wr_latency << 0); - /* PHY interface write latency and read latency configure */ - writel(reg_val, &mctl_ctl->pitmg0); - /* Set phy time PTR0-2 use default */ - writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3); - writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4); - /* Set refresh timing */ - reg_val = (trefi << 16) | (trfc << 0); - writel(reg_val, &mctl_ctl->rfshtmg); -} - -static void mctl_set_pir(u32 val) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - writel(val, &mctl_ctl->pir); - mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1); -} - -static void mctl_data_train_cfg(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - if (para->rank == 2) - clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); - else - clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); -} - -static int mctl_train_dram(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - mctl_data_train_cfg(para); - mctl_set_pir(0x5f3); - - return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; -} - -static int mctl_channel_init(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - u32 low_data_lines_status; /* Training status of datalines 0 - 7 */ - u32 high_data_lines_status; /* Training status of datalines 8 - 15 */ - - auto_set_timing_para(para); - - /* Disable dram VTC */ - clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0); - - /* Set ODT */ - if ((CONFIG_DRAM_CLK > 400) && IS_ENABLED(CONFIG_DRAM_ODT_EN)) { - setbits_le32(DXnGCR0(0), 0x3 << 9); - setbits_le32(DXnGCR0(1), 0x3 << 9); - } else { - clrbits_le32(DXnGCR0(0), 0x3 << 9); - clrbits_le32(DXnGCR0(1), 0x3 << 9); - } - - /* set PLL configuration */ - if (CONFIG_DRAM_CLK >= 480) - setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18); - else - setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18); - - /* Auto detect dram config, set 2 rank and 16bit bus-width */ - para->cs1 = 0; - para->rank = 2; - para->bus_width = 16; - mctl_set_cr(para); - - /* Open DQS gating */ - clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); - clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7)); - - mctl_data_train_cfg(para); - - /* ZQ calibration */ - writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1); - /* CA calibration */ - mctl_set_pir(0x00000003); - /* More ZQ calibration */ - writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2); - writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1); - - /* DQS gate training */ - if (mctl_train_dram(para) != 0) { - low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03; - high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03; - - if (low_data_lines_status == 0x3) - return -EIO; - - /* DRAM has only one rank */ - para->rank = 1; - mctl_set_cr(para); - - if (low_data_lines_status == high_data_lines_status) - goto done; /* 16 bit bus, 1 rank */ - - if (!(low_data_lines_status & high_data_lines_status)) { - /* Retry 16 bit bus-width with CS1 set */ - para->cs1 = 1; - mctl_set_cr(para); - if (mctl_train_dram(para) == 0) - goto done; - } - - /* Try 8 bit bus-width */ - writel(0x0, DXnGCR0(1)); /* Disable high DQ */ - para->cs1 = 0; - para->bus_width = 8; - mctl_set_cr(para); - if (mctl_train_dram(para) != 0) - return -EIO; - } -done: - /* Check the dramc status */ - mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); - - /* Close DQS gating */ - setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6); - - /* Enable master access */ - writel(0xffffffff, &mctl_com->maer); - - return 0; -} - -static void mctl_sys_init(struct dram_para *para) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - - clrsetbits_le32(&ccm->dram_pll_cfg, CCM_DRAMPLL_CFG_SRC_MASK, - CCM_DRAMPLL_CFG_SRC_PLL11); - - clock_set_pll11(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL, - DRAM_SIGMA_DELTA_ENABLE); - - clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, - CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) | - CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD); - mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); - - setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); - setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); - setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); - - /* Set dram master access priority */ - writel(0x0, &mctl_com->mapr); - writel(0x0f802f01, &mctl_ctl->sched); - writel(0x0000400f, &mctl_ctl->clken); /* normal */ - - udelay(250); -} - -unsigned long sunxi_dram_init(void) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - struct dram_para para = { - .cs1 = 0, - .bank = 1, - .rank = 1, - .rows = 15, - .bus_width = 16, - .page_size = 2048, - }; - - mctl_sys_init(¶); - - if (mctl_channel_init(¶) != 0) - return 0; - - auto_detect_dram_size(¶); - - /* Enable master software clk */ - writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); - - /* Set DRAM ODT MAP */ - if (para.rank == 2) - writel(0x00000303, &mctl_ctl->odtmap); - else - writel(0x00000201, &mctl_ctl->odtmap); - - return para.page_size * (para.bus_width / 8) * - (1 << (para.bank + para.rank + para.rows)); -} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c deleted file mode 100644 index 55df1b9..0000000 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c +++ /dev/null @@ -1,472 +0,0 @@ -/* - * Sun8i a33 platform dram controller init. - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang - * (C) Copyright 2015 Vishnu Patekar - * (C) Copyright 2015 Hans de Goede - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include - -#define DRAM_CLK_MUL 2 -#define DRAM_CLK_DIV 1 - -struct dram_para { - u8 cs1; - u8 seq; - u8 bank; - u8 rank; - u8 rows; - u8 bus_width; - u8 dram_type; - u16 page_size; -}; - -static void mctl_set_cr(struct dram_para *para) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - - writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | - MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | - (para->seq ? MCTL_CR_SEQUENCE : 0) | - ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | - MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | - MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), - &mctl_com->cr); -} - -static void auto_detect_dram_size(struct dram_para *para) -{ - u8 orig_rank = para->rank; - int rows, columns; - - /* Row detect */ - para->page_size = 512; - para->seq = 1; - para->rows = 16; - para->rank = 1; - mctl_set_cr(para); - for (rows = 11 ; rows < 16 ; rows++) { - if (mctl_mem_matches(1 << (rows + 9))) /* row-column */ - break; - } - - /* Column (page size) detect */ - para->rows = 11; - para->page_size = 8192; - mctl_set_cr(para); - for (columns = 9 ; columns < 13 ; columns++) { - if (mctl_mem_matches(1 << columns)) - break; - } - - para->seq = 0; - para->rank = orig_rank; - para->rows = rows; - para->page_size = 1 << columns; - mctl_set_cr(para); -} - -static inline int ns_to_t(int nanoseconds) -{ - const unsigned int ctrl_freq = - CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV; - - return (ctrl_freq * nanoseconds + 999) / 1000; -} - -static void auto_set_timing_para(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - u32 reg_val; - - u8 tccd = 2; - u8 tfaw = ns_to_t(50); - u8 trrd = max(ns_to_t(10), 4); - u8 trcd = ns_to_t(15); - u8 trc = ns_to_t(53); - u8 txp = max(ns_to_t(8), 3); - u8 twtr = max(ns_to_t(8), 4); - u8 trtp = max(ns_to_t(8), 4); - u8 twr = max(ns_to_t(15), 3); - u8 trp = ns_to_t(15); - u8 tras = ns_to_t(38); - - u16 trefi = ns_to_t(7800) / 32; - u16 trfc = ns_to_t(350); - - /* Fixed timing parameters */ - u8 tmrw = 0; - u8 tmrd = 4; - u8 tmod = 12; - u8 tcke = 3; - u8 tcksrx = 5; - u8 tcksre = 5; - u8 tckesr = 4; - u8 trasmax = 24; - u8 tcl = 6; /* CL 12 */ - u8 tcwl = 4; /* CWL 8 */ - u8 t_rdata_en = 4; - u8 wr_latency = 2; - - u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ - u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ - u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ - u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ - - u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ - u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ - u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ - - /* Set work mode register */ - mctl_set_cr(para); - /* Set mode register */ - if (para->dram_type == DRAM_TYPE_DDR3) { - writel(MCTL_MR0, &mctl_ctl->mr0); - writel(MCTL_MR1, &mctl_ctl->mr1); - writel(MCTL_MR2, &mctl_ctl->mr2); - writel(MCTL_MR3, &mctl_ctl->mr3); - } else if (para->dram_type == DRAM_TYPE_LPDDR3) { - writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0); - writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1); - writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2); - writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3); - - /* timing parameters for LPDDR3 */ - tfaw = max(ns_to_t(50), 4); - trrd = max(ns_to_t(10), 2); - trcd = max(ns_to_t(24), 2); - trc = ns_to_t(70); - txp = max(ns_to_t(8), 2); - twtr = max(ns_to_t(8), 2); - trtp = max(ns_to_t(8), 2); - trp = max(ns_to_t(27), 2); - tras = ns_to_t(42); - trefi = ns_to_t(3900) / 32; - trfc = ns_to_t(210); - tmrw = 5; - tmrd = 5; - tckesr = 5; - tcwl = 3; /* CWL 8 */ - t_rdata_en = 5; - tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ - tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */ - tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 200us */ - tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ - twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */ - twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */ - trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */ - } - /* Set dram timing */ - reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); - writel(reg_val, &mctl_ctl->dramtmg0); - reg_val = (txp << 16) | (trtp << 8) | (trc << 0); - writel(reg_val, &mctl_ctl->dramtmg1); - reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); - writel(reg_val, &mctl_ctl->dramtmg2); - reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); - writel(reg_val, &mctl_ctl->dramtmg3); - reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); - writel(reg_val, &mctl_ctl->dramtmg4); - reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); - writel(reg_val, &mctl_ctl->dramtmg5); - /* Set two rank timing and exit self-refresh timing */ - reg_val = readl(&mctl_ctl->dramtmg8); - reg_val &= ~(0xff << 8); - reg_val &= ~(0xff << 0); - reg_val |= (0x33 << 8); - reg_val |= (0x8 << 0); - writel(reg_val, &mctl_ctl->dramtmg8); - /* Set phy interface time */ - reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) - | (wr_latency << 0); - /* PHY interface write latency and read latency configure */ - writel(reg_val, &mctl_ctl->pitmg0); - /* Set phy time PTR0-2 use default */ - writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3); - writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4); - /* Set refresh timing */ - reg_val = (trefi << 16) | (trfc << 0); - writel(reg_val, &mctl_ctl->rfshtmg); -} - -static void mctl_set_pir(u32 val) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - writel(val, &mctl_ctl->pir); - mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1); -} - -static void mctl_data_train_cfg(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - if (para->rank == 2) - clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); - else - clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); -} - -static int mctl_train_dram(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - mctl_data_train_cfg(para); - mctl_set_pir(0x5f3); - - return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; -} - -static void set_master_priority(void) -{ - writel(0x00a0000d, MCTL_MASTER_CFG0(0)); - writel(0x00500064, MCTL_MASTER_CFG1(0)); - writel(0x07000009, MCTL_MASTER_CFG0(1)); - writel(0x00000600, MCTL_MASTER_CFG1(1)); - writel(0x01000009, MCTL_MASTER_CFG0(3)); - writel(0x00000064, MCTL_MASTER_CFG1(3)); - writel(0x08000009, MCTL_MASTER_CFG0(4)); - writel(0x00000640, MCTL_MASTER_CFG1(4)); - writel(0x20000308, MCTL_MASTER_CFG0(8)); - writel(0x00001000, MCTL_MASTER_CFG1(8)); - writel(0x02800009, MCTL_MASTER_CFG0(9)); - writel(0x00000100, MCTL_MASTER_CFG1(9)); - writel(0x01800009, MCTL_MASTER_CFG0(5)); - writel(0x00000100, MCTL_MASTER_CFG1(5)); - writel(0x01800009, MCTL_MASTER_CFG0(7)); - writel(0x00000100, MCTL_MASTER_CFG1(7)); - writel(0x00640009, MCTL_MASTER_CFG0(6)); - writel(0x00000032, MCTL_MASTER_CFG1(6)); - writel(0x0100000d, MCTL_MASTER_CFG0(2)); - writel(0x00500080, MCTL_MASTER_CFG1(2)); -} - -static int mctl_channel_init(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - u32 low_data_lines_status; /* Training status of datalines 0 - 7 */ - u32 high_data_lines_status; /* Training status of datalines 8 - 15 */ - u32 i, rval; - - auto_set_timing_para(para); - - /* Set dram master access priority */ - writel(0x000101a0, &mctl_com->bwcr); - /* set cpu high priority */ - writel(0x1, &mctl_com->mapr); - set_master_priority(); - udelay(250); - - /* Disable dram VTC */ - clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30); - clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26); - - writel(0x94be6fa3, MCTL_PROTECT); - udelay(100); - clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16); - writel(0x0, MCTL_PROTECT); - udelay(100); - - - /* Set ODT */ - if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) - rval = 0x0; - else - rval = 0x2; - - for (i = 0 ; i < 11 ; i++) { - clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16), - rval << 24); - clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16), - rval << 24); - clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16), - rval << 24); - clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16), - rval << 24); - } - - for (i = 0; i < 31; i++) - clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26); - - /* set PLL configuration */ - if (CONFIG_DRAM_CLK >= 480) - setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19); - else - setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19); - - /* Auto detect dram config, set 2 rank and 16bit bus-width */ - para->cs1 = 0; - para->rank = 2; - para->bus_width = 16; - mctl_set_cr(para); - - /* Open DQS gating */ - clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); - clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7)); - - if (para->dram_type == DRAM_TYPE_LPDDR3) - clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) , - 0x1 << 31); - if (readl(&mctl_com->cr) & 0x1) - writel(0x00000303, &mctl_ctl->odtmap); - else - writel(0x00000201, &mctl_ctl->odtmap); - - mctl_data_train_cfg(para); - /* ZQ calibration */ - clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff); - clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff); - /* CA calibration */ - - if (para->dram_type == DRAM_TYPE_DDR3) - mctl_set_pir(0x0201f3 | 0x1<<10); - else - mctl_set_pir(0x020173 | 0x1<<10); - - /* DQS gate training */ - if (mctl_train_dram(para) != 0) { - low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03; - high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03; - - if (low_data_lines_status == 0x3) - return -EIO; - - /* DRAM has only one rank */ - para->rank = 1; - mctl_set_cr(para); - - if (low_data_lines_status == high_data_lines_status) - goto done; /* 16 bit bus, 1 rank */ - - if (!(low_data_lines_status & high_data_lines_status)) { - /* Retry 16 bit bus-width with CS1 set */ - para->cs1 = 1; - mctl_set_cr(para); - if (mctl_train_dram(para) == 0) - goto done; - } - - /* Try 8 bit bus-width */ - writel(0x0, DXnGCR0(1)); /* Disable high DQ */ - para->cs1 = 0; - para->bus_width = 8; - mctl_set_cr(para); - if (mctl_train_dram(para) != 0) - return -EIO; - } -done: - /* Check the dramc status */ - mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); - - /* Close DQS gating */ - setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6); - - /* set PGCR3,CKE polarity */ - writel(0x00aa0060, &mctl_ctl->pgcr3); - /* Enable master access */ - writel(0xffffffff, &mctl_com->maer); - - return 0; -} - -static void mctl_sys_init(struct dram_para *para) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); - clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); - clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); - clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); - clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); - udelay(1000); - clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31); - - clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL); - - clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, - CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) | - CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD); - mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); - - setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); - setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); - setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); - - para->rank = 2; - para->bus_width = 16; - mctl_set_cr(para); - - /* Set dram master access priority */ - writel(0x0000e00f, &mctl_ctl->clken); /* normal */ - - udelay(250); -} - -unsigned long sunxi_dram_init(void) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - struct dram_para para = { - .cs1 = 0, - .bank = 1, - .rank = 1, - .rows = 15, - .bus_width = 16, - .page_size = 2048, - }; - -#if defined(CONFIG_MACH_SUN8I_A83T) -#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7) - para.dram_type = CONFIG_DRAM_TYPE; -#else -#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3) -#endif -#endif - setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8); - - writel(0, (SUNXI_PRCM_BASE + 0x1e8)); - udelay(10); - - mctl_sys_init(¶); - - if (mctl_channel_init(¶) != 0) - return 0; - - auto_detect_dram_size(¶); - - /* Enable master software clk */ - writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); - - /* Set DRAM ODT MAP */ - if (para.rank == 2) - writel(0x00000303, &mctl_ctl->odtmap); - else - writel(0x00000201, &mctl_ctl->odtmap); - - return para.page_size * (para.bus_width / 8) * - (1 << (para.bank + para.rank + para.rows)); -} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c deleted file mode 100644 index 2020d75..0000000 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * sun8i H3 platform dram controller init - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang - * (C) Copyright 2015 Vishnu Patekar - * (C) Copyright 2015 Hans de Goede - * (C) Copyright 2015 Jens Kuske - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include - -struct dram_para { - u32 read_delays; - u32 write_delays; - u16 page_size; - u8 bus_width; - u8 dual_rank; - u8 row_bits; -}; - -static inline int ns_to_t(int nanoseconds) -{ - const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; - - return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); -} - -static u32 bin_to_mgray(int val) -{ - static const u8 lookup_table[32] = { - 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, - 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, - 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d, - 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11, - }; - - return lookup_table[clamp(val, 0, 31)]; -} - -static int mgray_to_bin(u32 val) -{ - static const u8 lookup_table[32] = { - 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, - 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b, - 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b, - 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15, - }; - - return lookup_table[val & 0x1f]; -} - -static void mctl_phy_init(u32 val) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - writel(val | PIR_INIT, &mctl_ctl->pir); - mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1); -} - -static void mctl_dq_delay(u32 read, u32 write) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - int i, j; - u32 val; - - for (i = 0; i < 4; i++) { - val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) | - DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2); - - for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++) - writel(val, &mctl_ctl->datx[i].iocr[j]); - } - - clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); - - for (i = 0; i < 4; i++) { - val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) | - DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf); - - writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]); - writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]); - } - - setbits_le32(&mctl_ctl->pgcr[0], 1 << 26); - - udelay(1); -} - -static void mctl_set_master_priority(void) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - - /* enable bandwidth limit windows and set windows size 1us */ - writel(0x00010190, &mctl_com->bwcr); - - /* set cpu high priority */ - writel(0x00000001, &mctl_com->mapr); - - writel(0x0200000d, &mctl_com->mcr[0][0]); - writel(0x00800100, &mctl_com->mcr[0][1]); - writel(0x06000009, &mctl_com->mcr[1][0]); - writel(0x01000400, &mctl_com->mcr[1][1]); - writel(0x0200000d, &mctl_com->mcr[2][0]); - writel(0x00600100, &mctl_com->mcr[2][1]); - writel(0x0100000d, &mctl_com->mcr[3][0]); - writel(0x00200080, &mctl_com->mcr[3][1]); - writel(0x07000009, &mctl_com->mcr[4][0]); - writel(0x01000640, &mctl_com->mcr[4][1]); - writel(0x0100000d, &mctl_com->mcr[5][0]); - writel(0x00200080, &mctl_com->mcr[5][1]); - writel(0x01000009, &mctl_com->mcr[6][0]); - writel(0x00400080, &mctl_com->mcr[6][1]); - writel(0x0100000d, &mctl_com->mcr[7][0]); - writel(0x00400080, &mctl_com->mcr[7][1]); - writel(0x0100000d, &mctl_com->mcr[8][0]); - writel(0x00400080, &mctl_com->mcr[8][1]); - writel(0x04000009, &mctl_com->mcr[9][0]); - writel(0x00400100, &mctl_com->mcr[9][1]); - writel(0x2000030d, &mctl_com->mcr[10][0]); - writel(0x04001800, &mctl_com->mcr[10][1]); - writel(0x04000009, &mctl_com->mcr[11][0]); - writel(0x00400120, &mctl_com->mcr[11][1]); -} - -static void mctl_set_timing_params(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - u8 tccd = 2; - u8 tfaw = ns_to_t(50); - u8 trrd = max(ns_to_t(10), 4); - u8 trcd = ns_to_t(15); - u8 trc = ns_to_t(53); - u8 txp = max(ns_to_t(8), 3); - u8 twtr = max(ns_to_t(8), 4); - u8 trtp = max(ns_to_t(8), 4); - u8 twr = max(ns_to_t(15), 3); - u8 trp = ns_to_t(15); - u8 tras = ns_to_t(38); - u16 trefi = ns_to_t(7800) / 32; - u16 trfc = ns_to_t(350); - - u8 tmrw = 0; - u8 tmrd = 4; - u8 tmod = 12; - u8 tcke = 3; - u8 tcksrx = 5; - u8 tcksre = 5; - u8 tckesr = 4; - u8 trasmax = 24; - - u8 tcl = 6; /* CL 12 */ - u8 tcwl = 4; /* CWL 8 */ - u8 t_rdata_en = 4; - u8 wr_latency = 2; - - u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ - u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ - u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ - u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ - - u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ - u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ - u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ - - /* set mode register */ - writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ - writel(0x40, &mctl_ctl->mr[1]); - writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ - writel(0x0, &mctl_ctl->mr[3]); - - /* set DRAM timing */ - writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | - DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), - &mctl_ctl->dramtmg[0]); - writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), - &mctl_ctl->dramtmg[1]); - writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | - DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), - &mctl_ctl->dramtmg[2]); - writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), - &mctl_ctl->dramtmg[3]); - writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | - DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); - writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | - DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), - &mctl_ctl->dramtmg[5]); - - /* set two rank timing */ - clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), - (0x66 << 8) | (0x10 << 0)); - - /* set PHY interface timing, write latency and read latency configure */ - writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | - (wr_latency << 0), &mctl_ctl->pitmg[0]); - - /* set PHY timing, PTR0-2 use default */ - writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); - writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); - - /* set refresh timing */ - writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); -} - -static void mctl_zq_calibration(struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - int i; - u16 zq_val[6]; - u8 val; - - writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); - - for (i = 0; i < 6; i++) { - u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; - - writel((zq << 20) | (zq << 16) | (zq << 12) | - (zq << 8) | (zq << 4) | (zq << 0), - &mctl_ctl->zqcr); - - writel(PIR_CLRSR, &mctl_ctl->pir); - mctl_phy_init(PIR_ZCAL); - - zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; - writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); - - writel(PIR_CLRSR, &mctl_ctl->pir); - mctl_phy_init(PIR_ZCAL); - - val = readl(&mctl_ctl->zqdr[0]) >> 24; - zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; - } - - writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); - writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); - writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); -} - -static void mctl_set_cr(struct dram_para *para) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - - writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | - MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) | - (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | - MCTL_CR_PAGE_SIZE(para->page_size) | - MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); -} - -static void mctl_sys_init(struct dram_para *para) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); - clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); - clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); - clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); - clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); - udelay(10); - - clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); - udelay(1000); - - clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false); - clrsetbits_le32(&ccm->dram_clk_cfg, - CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK, - CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 | - CCM_DRAMCLK_CFG_UPD); - mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); - - setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); - setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); - setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); - - setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); - udelay(10); - - writel(0xc00e, &mctl_ctl->clken); - udelay(500); -} - -static int mctl_channel_init(struct dram_para *para) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - unsigned int i; - - mctl_set_cr(para); - mctl_set_timing_params(para); - mctl_set_master_priority(); - - /* setting VTC, default disable all VT */ - clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); - clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); - - /* increase DFI_PHY_UPD clock */ - writel(PROTECT_MAGIC, &mctl_com->protect); - udelay(100); - clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16); - writel(0x0, &mctl_com->protect); - udelay(100); - - /* set dramc odt */ - for (i = 0; i < 4; i++) - clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) | - (0x1 << 1) | (0x3 << 2) | (0x3 << 12) | - (0x3 << 14), - IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2); - - /* AC PDR should always ON */ - setbits_le32(&mctl_ctl->aciocr, 0x1 << 1); - - /* set DQS auto gating PD mode */ - setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6); - - /* dx ddr_clk & hdr_clk dynamic mode */ - clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); - - /* dphy & aphy phase select 270 degree */ - clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), - (0x1 << 10) | (0x2 << 8)); - - /* set half DQ */ - if (para->bus_width != 32) { - writel(0x0, &mctl_ctl->datx[2].gcr); - writel(0x0, &mctl_ctl->datx[3].gcr); - } - - /* data training configuration */ - clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, - (para->dual_rank ? 0x3 : 0x1) << 24); - - - if (para->read_delays || para->write_delays) { - mctl_dq_delay(para->read_delays, para->write_delays); - udelay(50); - } - - mctl_zq_calibration(para); - - mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST | - PIR_DRAMINIT | PIR_QSGATE); - - /* detect ranks and bus width */ - if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { - /* only one rank */ - if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) || - ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) { - clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); - para->dual_rank = 0; - } - - /* only half DQ width */ - if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) || - ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) { - writel(0x0, &mctl_ctl->datx[2].gcr); - writel(0x0, &mctl_ctl->datx[3].gcr); - para->bus_width = 16; - } - - mctl_set_cr(para); - udelay(20); - - /* re-train */ - mctl_phy_init(PIR_QSGATE); - if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) - return 1; - } - - /* check the dramc status */ - mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); - - /* liuke added for refresh debug */ - setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); - udelay(10); - clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); - udelay(10); - - /* set PGCR3, CKE polarity */ - writel(0x00aa0060, &mctl_ctl->pgcr[3]); - - /* power down zq calibration module for power save */ - setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN); - - /* enable master access */ - writel(0xffffffff, &mctl_com->maer); - - return 0; -} - -static void mctl_auto_detect_dram_size(struct dram_para *para) -{ - /* detect row address bits */ - para->page_size = 512; - para->row_bits = 16; - mctl_set_cr(para); - - for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) - if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size)) - break; - - /* detect page size */ - para->page_size = 8192; - mctl_set_cr(para); - - for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2) - if (mctl_mem_matches(para->page_size)) - break; -} - -unsigned long sunxi_dram_init(void) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - struct dram_para para = { - .read_delays = 0x00007979, /* dram_tpr12 */ - .write_delays = 0x6aaa0000, /* dram_tpr11 */ - .dual_rank = 0, - .bus_width = 32, - .row_bits = 15, - .page_size = 4096, - }; - - mctl_sys_init(¶); - if (mctl_channel_init(¶)) - return 0; - - if (para.dual_rank) - writel(0x00000303, &mctl_ctl->odtmap); - else - writel(0x00000201, &mctl_ctl->odtmap); - udelay(1); - - /* odt delay */ - writel(0x0c000400, &mctl_ctl->odtcfg); - - /* clear credit value */ - setbits_le32(&mctl_com->cccr, 1 << 31); - udelay(10); - - mctl_auto_detect_dram_size(¶); - mctl_set_cr(¶); - - return (1 << (para.row_bits + 3)) * para.page_size * - (para.dual_rank ? 2 : 1); -} diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c deleted file mode 100644 index 26a9cfc..0000000 --- a/arch/arm/cpu/armv7/sunxi/p2wi.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Sunxi A31 Power Management Unit - * - * (C) Copyright 2013 Oliver Schinagl - * http://linux-sunxi.org - * - * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work - * - * (C) Copyright 2006-2013 - * Allwinner Technology Co., Ltd. - * Berg Xing - * Tom Cubie - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void p2wi_init(void) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - - /* Enable p2wi and PIO clk, and de-assert their resets */ - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); - - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); - - /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ - writel(P2WI_CTRL_RESET, &p2wi->ctrl); - sdelay(0x100); - writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8), - &p2wi->cc); -} - -int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - unsigned long tmo = timer_get_us() + 1000000; - - writel(P2WI_PM_DEV_ADDR(slave_addr) | - P2WI_PM_CTRL_ADDR(ctrl_reg) | - P2WI_PM_INIT_DATA(init_data) | - P2WI_PM_INIT_SEND, - &p2wi->pm); - - while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) { - if (timer_get_us() > tmo) - return -ETIME; - } - - return 0; -} - -static int p2wi_await_trans(void) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - unsigned long tmo = timer_get_us() + 1000000; - int ret; - u8 reg; - - while (1) { - reg = readl(&p2wi->status); - if (reg & P2WI_STAT_TRANS_ERR) { - ret = -EIO; - break; - } - if (reg & P2WI_STAT_TRANS_DONE) { - ret = 0; - break; - } - if (timer_get_us() > tmo) { - ret = -ETIME; - break; - } - } - writel(reg, &p2wi->status); /* Clear status bits */ - return ret; -} - -int p2wi_read(const u8 addr, u8 *data) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - int ret; - - writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); - writel(P2WI_DATA_NUM_BYTES(1) | - P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes); - writel(P2WI_STAT_TRANS_DONE, &p2wi->status); - writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); - - ret = p2wi_await_trans(); - - *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK; - return ret; -} - -int p2wi_write(const u8 addr, u8 data) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - - writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); - writel(P2WI_DATA_BYTE_1(data), &p2wi->data0); - writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes); - writel(P2WI_STAT_TRANS_DONE, &p2wi->status); - writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); - - return p2wi_await_trans(); -} diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c deleted file mode 100644 index b026f78..0000000 --- a/arch/arm/cpu/armv7/sunxi/pinmux.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. - * Tom Cubie - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) -{ - u32 index = GPIO_CFG_INDEX(bank_offset); - u32 offset = GPIO_CFG_OFFSET(bank_offset); - - clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset); -} - -void sunxi_gpio_set_cfgpin(u32 pin, u32 val) -{ - u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); - - sunxi_gpio_set_cfgbank(pio, pin, val); -} - -int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) -{ - u32 index = GPIO_CFG_INDEX(bank_offset); - u32 offset = GPIO_CFG_OFFSET(bank_offset); - u32 cfg; - - cfg = readl(&pio->cfg[0] + index); - cfg >>= offset; - - return cfg & 0xf; -} - -int sunxi_gpio_get_cfgpin(u32 pin) -{ - u32 bank = GPIO_BANK(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); - - return sunxi_gpio_get_cfgbank(pio, pin); -} - -int sunxi_gpio_set_drv(u32 pin, u32 val) -{ - u32 bank = GPIO_BANK(pin); - u32 index = GPIO_DRV_INDEX(pin); - u32 offset = GPIO_DRV_OFFSET(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); - - clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); - - return 0; -} - -int sunxi_gpio_set_pull(u32 pin, u32 val) -{ - u32 bank = GPIO_BANK(pin); - u32 index = GPIO_PULL_INDEX(pin); - u32 offset = GPIO_PULL_OFFSET(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); - - clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); - - return 0; -} diff --git a/arch/arm/cpu/armv7/sunxi/pmic_bus.c b/arch/arm/cpu/armv7/sunxi/pmic_bus.c deleted file mode 100644 index 5b81a8d..0000000 --- a/arch/arm/cpu/armv7/sunxi/pmic_bus.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * (C) Copyright 2015 Hans de Goede - * - * Sunxi PMIC bus access helpers - * - * The axp152 & axp209 use an i2c bus, the axp221 uses the p2wi bus and the - * axp223 uses the rsb bus, these functions abstract this. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#define AXP152_I2C_ADDR 0x30 - -#define AXP209_I2C_ADDR 0x34 - -#define AXP221_CHIP_ADDR 0x68 -#define AXP221_CTRL_ADDR 0x3e -#define AXP221_INIT_DATA 0x3e - -/* AXP818 device and runtime addresses are same as AXP223 */ -#define AXP223_DEVICE_ADDR 0x3a3 -#define AXP223_RUNTIME_ADDR 0x2d - -int pmic_bus_init(void) -{ - /* This cannot be 0 because it is used in SPL before BSS is ready */ - static int needs_init = 1; - __maybe_unused int ret; - - if (!needs_init) - return 0; - -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER -# ifdef CONFIG_MACH_SUN6I - p2wi_init(); - ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, - AXP221_INIT_DATA); -# else - ret = rsb_init(); - if (ret) - return ret; - - ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR); -# endif - if (ret) - return ret; -#endif - - needs_init = 0; - return 0; -} - -int pmic_bus_read(u8 reg, u8 *data) -{ -#ifdef CONFIG_AXP152_POWER - return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP209_POWER - return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER -# ifdef CONFIG_MACH_SUN6I - return p2wi_read(reg, data); -# else - return rsb_read(AXP223_RUNTIME_ADDR, reg, data); -# endif -#endif -} - -int pmic_bus_write(u8 reg, u8 data) -{ -#ifdef CONFIG_AXP152_POWER - return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP209_POWER - return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER -# ifdef CONFIG_MACH_SUN6I - return p2wi_write(reg, data); -# else - return rsb_write(AXP223_RUNTIME_ADDR, reg, data); -# endif -#endif -} - -int pmic_bus_setbits(u8 reg, u8 bits) -{ - int ret; - u8 val; - - ret = pmic_bus_read(reg, &val); - if (ret) - return ret; - - val |= bits; - return pmic_bus_write(reg, val); -} - -int pmic_bus_clrbits(u8 reg, u8 bits) -{ - int ret; - u8 val; - - ret = pmic_bus_read(reg, &val); - if (ret) - return ret; - - val &= ~bits; - return pmic_bus_write(reg, val); -} diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c deleted file mode 100644 index e1d091f..0000000 --- a/arch/arm/cpu/armv7/sunxi/prcm.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Sunxi A31 Power Management Unit - * - * (C) Copyright 2013 Oliver Schinagl - * http://linux-sunxi.org - * - * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work - * - * (C) Copyright 2006-2013 - * Allwinner Technology Co., Ltd. - * Berg Xing - * Tom Cubie - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -/* APB0 clock gate and reset bit offsets are the same. */ -void prcm_apb0_enable(u32 flags) -{ - struct sunxi_prcm_reg *prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; - - /* open the clock for module */ - setbits_le32(&prcm->apb0_gate, flags); - - /* deassert reset for module */ - setbits_le32(&prcm->apb0_reset, flags); -} - -void prcm_apb0_disable(u32 flags) -{ - struct sunxi_prcm_reg *prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; - - /* assert reset for module */ - clrbits_le32(&prcm->apb0_reset, flags); - - /* close the clock for module */ - clrbits_le32(&prcm->apb0_gate, flags); -} diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c deleted file mode 100644 index 6fd11f1..0000000 --- a/arch/arm/cpu/armv7/sunxi/rsb.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * (C) Copyright 2014 Hans de Goede - * - * Based on allwinner u-boot sources rsb code which is: - * (C) Copyright 2007-2013 - * Allwinner Technology Co., Ltd. - * lixiang - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -static int rsb_set_device_mode(void); - -static void rsb_cfg_io(void) -{ -#ifdef CONFIG_MACH_SUN8I - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); - sunxi_gpio_set_pull(SUNXI_GPL(0), 1); - sunxi_gpio_set_pull(SUNXI_GPL(1), 1); - sunxi_gpio_set_drv(SUNXI_GPL(0), 2); - sunxi_gpio_set_drv(SUNXI_GPL(1), 2); -#elif defined CONFIG_MACH_SUN9I - sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB); - sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB); - sunxi_gpio_set_pull(SUNXI_GPN(0), 1); - sunxi_gpio_set_pull(SUNXI_GPN(1), 1); - sunxi_gpio_set_drv(SUNXI_GPN(0), 2); - sunxi_gpio_set_drv(SUNXI_GPN(1), 2); -#else -#error unsupported MACH_SUNXI -#endif -} - -static void rsb_set_clk(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - u32 div = 0; - u32 cd_odly = 0; - - /* Source is Hosc24M, set RSB clk to 3Mhz */ - div = 24000000 / 3000000 / 2 - 1; - cd_odly = div >> 1; - if (!cd_odly) - cd_odly = 1; - - writel((cd_odly << 8) | div, &rsb->ccr); -} - -int rsb_init(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - /* Enable RSB and PIO clk, and de-assert their resets */ - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); - - /* Setup external pins */ - rsb_cfg_io(); - - writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); - rsb_set_clk(); - - return rsb_set_device_mode(); -} - -static int rsb_await_trans(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - unsigned long tmo = timer_get_us() + 1000000; - u32 stat; - int ret; - - while (1) { - stat = readl(&rsb->stat); - if (stat & RSB_STAT_LBSY_INT) { - ret = -EBUSY; - break; - } - if (stat & RSB_STAT_TERR_INT) { - ret = -EIO; - break; - } - if (stat & RSB_STAT_TOVER_INT) { - ret = 0; - break; - } - if (timer_get_us() > tmo) { - ret = -ETIME; - break; - } - } - writel(stat, &rsb->stat); /* Clear status bits */ - - return ret; -} - -static int rsb_set_device_mode(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - unsigned long tmo = timer_get_us() + 1000000; - - writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA, - &rsb->dmcr); - - while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) { - if (timer_get_us() > tmo) - return -ETIME; - } - - return rsb_await_trans(); -} - -static int rsb_do_trans(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS); - return rsb_await_trans(); -} - -int rsb_set_device_address(u16 device_addr, u16 runtime_addr) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) | - RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr); - writel(RSB_CMD_SET_RTSADDR, &rsb->cmd); - - return rsb_do_trans(); -} - -int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); - writel(reg_addr, &rsb->addr); - writel(data, &rsb->data); - writel(RSB_CMD_BYTE_WRITE, &rsb->cmd); - - return rsb_do_trans(); -} - -int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - int ret; - - writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); - writel(reg_addr, &rsb->addr); - writel(RSB_CMD_BYTE_READ, &rsb->cmd); - - ret = rsb_do_trans(); - if (ret) - return ret; - - *data = readl(&rsb->data) & 0xff; - - return 0; -} diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c deleted file mode 100644 index fa375f1..0000000 --- a/arch/arm/cpu/armv7/sunxi/usb_phy.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Sunxi usb-phy code - * - * Copyright (C) 2015 Hans de Goede - * Copyright (C) 2014 Roman Byshko - * - * Based on code from - * Allwinner Technology Co., Ltd. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#define SUNXI_USB_PMU_IRQ_ENABLE 0x800 -#ifdef CONFIG_MACH_SUN8I_A33 -#define SUNXI_USB_CSR 0x410 -#else -#define SUNXI_USB_CSR 0x404 -#endif -#define SUNXI_USB_PASSBY_EN 1 - -#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) -#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9) -#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8) -#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0) - -#define REG_PHY_UNK_H3 0x420 -#define REG_PMU_UNK_H3 0x810 - -/* A83T specific control bits for PHY0 */ -#define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5) -#define SUNXI_PHY_CTL_SIDDQ BIT(3) - -/* A83T HSIC specific bits */ -#define SUNXI_EHCI_HS_FORCE BIT(20) -#define SUNXI_EHCI_CONNECT_DET BIT(17) -#define SUNXI_EHCI_CONNECT_INT BIT(16) -#define SUNXI_EHCI_HSIC BIT(1) - -static struct sunxi_usb_phy { - int usb_rst_mask; - int gpio_vbus; - int gpio_vbus_det; - int gpio_id_det; - int id; - int init_count; - int power_on_count; - int base; -} sunxi_usb_phy[] = { - { - .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK, - .id = 0, - .base = SUNXI_USB0_BASE, - }, - { - .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK, - .id = 1, - .base = SUNXI_USB1_BASE, - }, -#if CONFIG_SUNXI_USB_PHYS >= 3 - { -#ifdef CONFIG_MACH_SUN8I_A83T - .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK | - CCM_USB_CTRL_12M_CLK, -#else - .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, -#endif - .id = 2, - .base = SUNXI_USB2_BASE, - }, -#endif -#if CONFIG_SUNXI_USB_PHYS >= 4 - { - .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK, - .id = 3, - .base = SUNXI_USB3_BASE, - } -#endif -}; - -static int get_vbus_gpio(int index) -{ - switch (index) { - case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN); - case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN); - case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN); - case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN); - } - return -EINVAL; -} - -static int get_vbus_detect_gpio(int index) -{ - switch (index) { - case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET); - } - return -EINVAL; -} - -static int get_id_detect_gpio(int index) -{ - switch (index) { - case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET); - } - return -EINVAL; -} - -__maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, - int data, int len) -{ - int j = 0, usbc_bit = 0; - void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR; - -#ifdef CONFIG_MACH_SUN8I_A33 - /* CSR needs to be explicitly initialized to 0 on A33 */ - writel(0, dest); -#endif - - usbc_bit = 1 << (phy->id * 2); - for (j = 0; j < len; j++) { - /* set the bit address to be written */ - clrbits_le32(dest, 0xff << 8); - setbits_le32(dest, (addr + j) << 8); - - clrbits_le32(dest, usbc_bit); - /* set data bit */ - if (data & 0x1) - setbits_le32(dest, 1 << 7); - else - clrbits_le32(dest, 1 << 7); - - setbits_le32(dest, usbc_bit); - - clrbits_le32(dest, usbc_bit); - - data >>= 1; - } -} - -#if defined CONFIG_MACH_SUN8I_H3 -static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) -{ - if (phy->id == 0) - clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); - - clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); -} -#elif defined CONFIG_MACH_SUN8I_A83T -static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) -{ -} -#else -static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) -{ - /* The following comments are machine - * translated from Chinese, you have been warned! - */ - - /* Regulation 45 ohms */ - if (phy->id == 0) - usb_phy_write(phy, 0x0c, 0x01, 1); - - /* adjust PHY's magnitude and rate */ - usb_phy_write(phy, 0x20, 0x14, 5); - - /* threshold adjustment disconnect */ -#if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I - usb_phy_write(phy, 0x2a, 2, 2); -#else - usb_phy_write(phy, 0x2a, 3, 2); -#endif - - return; -} -#endif - -static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable) -{ - unsigned long bits = 0; - void *addr; - - addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE; - - bits = SUNXI_EHCI_AHB_ICHR8_EN | - SUNXI_EHCI_AHB_INCR4_BURST_EN | - SUNXI_EHCI_AHB_INCRX_ALIGN_EN | - SUNXI_EHCI_ULPI_BYPASS_EN; - -#ifdef CONFIG_MACH_SUN8I_A83T - if (phy->id == 2) - bits |= SUNXI_EHCI_HS_FORCE | - SUNXI_EHCI_CONNECT_INT | - SUNXI_EHCI_HSIC; -#endif - - if (enable) - setbits_le32(addr, bits); - else - clrbits_le32(addr, bits); - - return; -} - -void sunxi_usb_phy_enable_squelch_detect(int index, int enable) -{ -#ifndef CONFIG_MACH_SUN8I_A83T - struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; - - usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2); -#endif -} - -void sunxi_usb_phy_init(int index) -{ - struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - phy->init_count++; - if (phy->init_count != 1) - return; - - setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); - - sunxi_usb_phy_config(phy); - - if (phy->id != 0) - sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN); - -#ifdef CONFIG_MACH_SUN8I_A83T - if (phy->id == 0) { - setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, - SUNXI_PHY_CTL_VBUSVLDEXT); - clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, - SUNXI_PHY_CTL_SIDDQ); - } -#endif -} - -void sunxi_usb_phy_exit(int index) -{ - struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - phy->init_count--; - if (phy->init_count != 0) - return; - - if (phy->id != 0) - sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN); - -#ifdef CONFIG_MACH_SUN8I_A83T - if (phy->id == 0) { - setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, - SUNXI_PHY_CTL_SIDDQ); - } -#endif - - clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); -} - -void sunxi_usb_phy_power_on(int index) -{ - struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; - - phy->power_on_count++; - if (phy->power_on_count != 1) - return; - - if (phy->gpio_vbus >= 0) - gpio_set_value(phy->gpio_vbus, 1); -} - -void sunxi_usb_phy_power_off(int index) -{ - struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; - - phy->power_on_count--; - if (phy->power_on_count != 0) - return; - - if (phy->gpio_vbus >= 0) - gpio_set_value(phy->gpio_vbus, 0); -} - -int sunxi_usb_phy_power_is_on(int index) -{ - struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; - - return phy->power_on_count > 0; -} - -int sunxi_usb_phy_vbus_detect(int index) -{ - struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; - int err, retries = 3; - - if (phy->gpio_vbus_det < 0) - return phy->gpio_vbus_det; - - err = gpio_get_value(phy->gpio_vbus_det); - /* - * Vbus may have been provided by the board and just been turned of - * some milliseconds ago on reset, what we're measuring then is a - * residual charge on Vbus, sleep a bit and try again. - */ - while (err > 0 && retries--) { - mdelay(100); - err = gpio_get_value(phy->gpio_vbus_det); - } - - return err; -} - -int sunxi_usb_phy_id_detect(int index) -{ - struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; - - if (phy->gpio_id_det < 0) - return phy->gpio_id_det; - - return gpio_get_value(phy->gpio_id_det); -} - -int sunxi_usb_phy_probe(void) -{ - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_usb_phy *phy; - int i, ret = 0; - - for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { - phy = &sunxi_usb_phy[i]; - - phy->gpio_vbus = get_vbus_gpio(i); - if (phy->gpio_vbus >= 0) { - ret = gpio_request(phy->gpio_vbus, "usb_vbus"); - if (ret) - return ret; - ret = gpio_direction_output(phy->gpio_vbus, 0); - if (ret) - return ret; - } - - phy->gpio_vbus_det = get_vbus_detect_gpio(i); - if (phy->gpio_vbus_det >= 0) { - ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det"); - if (ret) - return ret; - ret = gpio_direction_input(phy->gpio_vbus_det); - if (ret) - return ret; - } - - phy->gpio_id_det = get_id_detect_gpio(i); - if (phy->gpio_id_det >= 0) { - ret = gpio_request(phy->gpio_id_det, "usb_id_det"); - if (ret) - return ret; - ret = gpio_direction_input(phy->gpio_id_det); - if (ret) - return ret; - sunxi_gpio_set_pull(phy->gpio_id_det, - SUNXI_GPIO_PULL_UP); - } - } - - setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); - - return 0; -} - -int sunxi_usb_phy_remove(void) -{ - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_usb_phy *phy; - int i; - - clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); - - for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { - phy = &sunxi_usb_phy[i]; - - if (phy->gpio_vbus >= 0) - gpio_free(phy->gpio_vbus); - - if (phy->gpio_vbus_det >= 0) - gpio_free(phy->gpio_vbus_det); - - if (phy->gpio_id_det >= 0) - gpio_free(phy->gpio_id_det); - } - - return 0; -} diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile new file mode 100644 index 0000000..114cc03 --- /dev/null +++ b/arch/arm/mach-sunxi/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2012 Henrik Nordstrom +# +# Based on some other Makefile +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o +obj-y += clock.o +obj-y += cpu_info.o +obj-y += dram_helpers.o +obj-y += pinmux.o +ifndef CONFIG_MACH_SUN9I +obj-y += usb_phy.o +endif +obj-$(CONFIG_MACH_SUN6I) += prcm.o +obj-$(CONFIG_MACH_SUN8I) += prcm.o +obj-$(CONFIG_MACH_SUN9I) += prcm.o +obj-$(CONFIG_MACH_SUN6I) += p2wi.o +obj-$(CONFIG_MACH_SUN8I) += rsb.o +obj-$(CONFIG_MACH_SUN9I) += rsb.o +obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o +obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o +ifdef CONFIG_MACH_SUN8I_A83T +obj-y += clock_sun8i_a83t.o +else +obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o +endif +obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o + +obj-$(CONFIG_AXP152_POWER) += pmic_bus.o +obj-$(CONFIG_AXP209_POWER) += pmic_bus.o +obj-$(CONFIG_AXP221_POWER) += pmic_bus.o +obj-$(CONFIG_AXP818_POWER) += pmic_bus.o + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o +obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o +obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o +obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o +obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o +obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o +obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o +obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o +endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c new file mode 100644 index 0000000..bf58fa9 --- /dev/null +++ b/arch/arm/mach-sunxi/board.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Some init for sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#ifdef CONFIG_SPL_BUILD +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct fel_stash { + uint32_t sp; + uint32_t lr; + uint32_t cpsr; + uint32_t sctlr; + uint32_t vbar; + uint32_t cr; +}; + +struct fel_stash fel_stash __attribute__((section(".data"))); + +static int gpio_init(void) +{ +#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) + /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); +#endif +#if defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); +#else + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); +#endif + sunxi_gpio_set_pull(SUNXI_GPF(4), 1); +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3) + sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); + sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); + sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); +#else +#error Unsupported console port number. Please fix pin mux settings in board.c +#endif + + return 0; +} + +int spl_board_load_image(void) +{ + debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); + return_to_fel(fel_stash.sp, fel_stash.lr); + + return 0; +} + +void s_init(void) +{ + /* + * Undocumented magic taken from boot0, without this DRAM + * access gets messed up (seems cache related). + * The boot0 sources describe this as: "config ema for cache sram" + */ +#if defined CONFIG_MACH_SUN6I + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); +#elif defined CONFIG_MACH_SUN8I + __maybe_unused uint version; + + /* Unlock sram version info reg, read it, relock */ + setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); + version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; + clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); + + /* + * Ideally this would be a switch case, but we do not know exactly + * which versions there are and which version needs which settings, + * so reproduce the per SoC code from the BSP. + */ +#if defined CONFIG_MACH_SUN8I_A23 + if (version == 0x1650) + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); + else /* 0x1661 ? */ + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); +#elif defined CONFIG_MACH_SUN8I_A33 + if (version != 0x1667) + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); +#endif + /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */ + /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ +#endif + +#if defined CONFIG_MACH_SUN6I || \ + defined CONFIG_MACH_SUN7I || \ + defined CONFIG_MACH_SUN8I + /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #1 << 6\n" + "mcr p15, 0, r0, c1, c0, 1\n"); +#endif +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 + /* Enable non-secure access to some peripherals */ + tzpc_init(); +#endif + + clock_init(); + timer_init(); + gpio_init(); + i2c_init_board(); + eth_init_board(); +} + +#ifdef CONFIG_SPL_BUILD +DECLARE_GLOBAL_DATA_PTR; + +/* The sunxi internal brom will try to loader external bootloader + * from mmc0, nand flash, mmc2. + */ +u32 spl_boot_device(void) +{ + __maybe_unused struct mmc *mmc0, *mmc1; + /* + * When booting from the SD card or NAND memory, the "eGON.BT0" + * signature is expected to be found in memory at the address 0x0004 + * (see the "mksunxiboot" tool, which generates this header). + * + * When booting in the FEL mode over USB, this signature is patched in + * memory and replaced with something else by the 'fel' tool. This other + * signature is selected in such a way, that it can't be present in a + * valid bootable SD card image (because the BROM would refuse to + * execute the SPL in this case). + * + * This checks for the signature and if it is not found returns to + * the FEL code in the BROM to wait and receive the main u-boot + * binary over USB. If it is found, it determines where SPL was + * read from. + */ + if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ + return BOOT_DEVICE_BOARD; + + /* The BROM will try to boot from mmc0 first, so try that first. */ +#ifdef CONFIG_MMC + mmc_initialize(gd->bd); + mmc0 = find_mmc_device(0); + if (sunxi_mmc_has_egon_boot_signature(mmc0)) + return BOOT_DEVICE_MMC1; +#endif + + /* Fallback to booting NAND if enabled. */ + if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT)) + return BOOT_DEVICE_NAND; + +#ifdef CONFIG_MMC + if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) { + mmc1 = find_mmc_device(1); + if (sunxi_mmc_has_egon_boot_signature(mmc1)) + return BOOT_DEVICE_MMC2; + } +#endif + + panic("Could not determine boot source\n"); + return -1; /* Never reached */ +} + +/* No confirmation data available in SPL yet. Hardcode bootmode */ +u32 spl_boot_mode(void) +{ + return MMCSD_MODE_RAW; +} + +void board_init_f(ulong dummy) +{ + spl_init(); + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + /* Needed early by sunxi_board_init if PMU is enabled */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + sunxi_board_init(); +} +#endif + +void reset_cpu(ulong addr) +{ +#ifdef CONFIG_SUNXI_GEN_SUN4I + static const struct sunxi_wdog *wdog = + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; + + /* Set the watchdog for its shortest interval (.5s) and wait */ + writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); + + while (1) { + /* sun5i sometimes gets stuck without this */ + writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); + } +#endif +#ifdef CONFIG_SUNXI_GEN_SUN6I + static const struct sunxi_wdog *wdog = + ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; + + /* Set the watchdog for its shortest interval (.5s) and wait */ + writel(WDT_CFG_RESET, &wdog->cfg); + writel(WDT_MODE_EN, &wdog->mode); + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); + while (1) { } +#endif +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c new file mode 100644 index 0000000..0b8fc94 --- /dev/null +++ b/arch/arm/mach-sunxi/clock.c @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +__weak void clock_init_sec(void) +{ +} + +int clock_init(void) +{ +#ifdef CONFIG_SPL_BUILD + clock_init_safe(); +#endif + clock_init_uart(); + clock_init_sec(); + + return 0; +} + +/* These functions are shared between various SoCs so put them here. */ +#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (port == 5) { + if (state) + prcm_apb0_enable( + PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); + else + prcm_apb0_disable( + PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C); + return 0; + } + + /* set the apb clock gate and reset for twi */ + if (state) { + setbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); + setbits_le32(&ccm->apb2_reset_cfg, + 1 << (APB2_RESET_TWI_SHIFT + port)); + } else { + clrbits_le32(&ccm->apb2_reset_cfg, + 1 << (APB2_RESET_TWI_SHIFT + port)); + clrbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port)); + } + + return 0; +} +#endif diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c new file mode 100644 index 0000000..7e6bd61 --- /dev/null +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -0,0 +1,238 @@ +/* + * sun4i, sun5i and sun7i specific clock code + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Set safe defaults until PMU is configured */ + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); + sdelay(200); + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); +#ifdef CONFIG_MACH_SUN7I + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); +#endif + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); +#ifdef CONFIG_SUNXI_AHCI + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); + setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); +#endif +} +#endif + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* uart clock source is apb1 */ + writel(APB1_CLK_SRC_OSC24M| + APB1_CLK_RATE_N_1| + APB1_CLK_RATE_M(1), + &ccm->apb1_clk_div_cfg); + + /* open the clock for uart */ + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1)); +} + +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* set the apb clock gate for twi */ + if (state) + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); + else + clrbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ + 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \ + 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \ + 0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \ + 16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \ + (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \ + 2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \ + (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \ + (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \ + 0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \ + 0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \ + (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT) + +static struct { + u32 pll1_cfg; + unsigned int freq; +} pll1_para[] = { + /* This array must be ordered by frequency. */ + { PLL1_CFG(31, 1, 0, 0), 1488000000}, + { PLL1_CFG(30, 1, 0, 0), 1440000000}, + { PLL1_CFG(29, 1, 0, 0), 1392000000}, + { PLL1_CFG(28, 1, 0, 0), 1344000000}, + { PLL1_CFG(27, 1, 0, 0), 1296000000}, + { PLL1_CFG(26, 1, 0, 0), 1248000000}, + { PLL1_CFG(25, 1, 0, 0), 1200000000}, + { PLL1_CFG(24, 1, 0, 0), 1152000000}, + { PLL1_CFG(23, 1, 0, 0), 1104000000}, + { PLL1_CFG(22, 1, 0, 0), 1056000000}, + { PLL1_CFG(21, 1, 0, 0), 1008000000}, + { PLL1_CFG(20, 1, 0, 0), 960000000 }, + { PLL1_CFG(19, 1, 0, 0), 912000000 }, + { PLL1_CFG(16, 1, 0, 0), 768000000 }, + /* Final catchall entry 384MHz*/ + { PLL1_CFG(16, 0, 0, 0), 0 }, + +}; + +void clock_set_pll1(unsigned int hz) +{ + int i = 0; + int axi, ahb, apb0; + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Find target frequency */ + while (pll1_para[i].freq > hz) + i++; + + hz = pll1_para[i].freq; + if (! hz) + hz = 384000000; + + /* Calculate system clock divisors */ + axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ + ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ + apb0 = 2; /* Max 150MHz */ + + printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); + + /* Map divisors to register values */ + axi = axi - 1; + if (ahb > 4) + ahb = 3; + else if (ahb > 2) + ahb = 2; + else if (ahb > 1) + ahb = 1; + else + ahb = 0; + + apb0 = apb0 - 1; + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + sdelay(20); + + /* Configure sys clock divisors */ + writel(axi << AXI_DIV_SHIFT | + ahb << AHB_DIV_SHIFT | + apb0 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + + /* Configure PLL1 at the desired frequency */ + writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg); + sdelay(200); + + /* Switch CPU to PLL1 */ + writel(axi << AXI_DIV_SHIFT | + ahb << AHB_DIV_SHIFT | + apb0 << APB0_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + sdelay(20); +} +#endif + +void clock_set_pll3(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (clk == 0) { + clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); + return; + } + + /* PLL3 rate = 3000000 * m */ + writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | + CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg); +} + +unsigned int clock_get_pll3(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll3_cfg); + int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT); + return 3000000 * m; +} + +unsigned int clock_get_pll5p(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll5_cfg); + int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT); + int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1; + int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT); + return (24000000 * n * k) >> p; +} + +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); + int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; + return 24000000 * n * k / 2; +} + +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) +{ + int pll = clock_get_pll5p(); + int div = 1; + + while ((pll / div) > hz) + div++; + + writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P | + CCM_DE_CTRL_M(div), clk_cfg); +} diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c new file mode 100644 index 0000000..15272c9 --- /dev/null +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -0,0 +1,274 @@ +/* + * sun6i specific clock code + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* Set PLL ldo voltage without this PLL6 does not work properly */ + clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, + PRCM_PLL_CTRL_LDO_KEY); + clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, + PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); + clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); + + clock_set_pll1(408000000); + + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) + ; + + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); + + writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); + writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); +} +#endif + +void clock_init_sec(void) +{ +#ifdef CONFIG_MACH_SUN8I_H3 + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + setbits_le32(&ccm->ccu_sec_switch, + CCM_SEC_SWITCH_MBUS_NONSEC | + CCM_SEC_SWITCH_BUS_NONSEC | + CCM_SEC_SWITCH_PLL_NONSEC); +#endif +} + +void clock_init_uart(void) +{ +#if CONFIG_CONS_INDEX < 5 + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* uart clock source is apb2 */ + writel(APB2_CLK_SRC_OSC24M| + APB2_CLK_RATE_N_1| + APB2_CLK_RATE_M(1), + &ccm->apb2_div); + + /* open the clock for uart */ + setbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + + /* deassert uart reset */ + setbits_le32(&ccm->apb2_reset_cfg, + 1 << (APB2_RESET_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); +#else + /* enable R_PIO and R_UART clocks, and de-assert resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); +#endif +} + +#ifdef CONFIG_SPL_BUILD +void clock_set_pll1(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + int k = 1; + int m = 1; + + if (clk > 1152000000) { + k = 2; + } else if (clk > 768000000) { + k = 3; + m = 2; + } + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_3 << AXI_DIV_SHIFT | + ATB_DIV_2 << ATB_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); + + /* + * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored) + * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m + */ + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | + CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | + CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); + sdelay(200); + + /* Switch CPU to PLL1 */ + writel(AXI_DIV_3 << AXI_DIV_SHIFT | + ATB_DIV_2 << ATB_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); +} +#endif + +void clock_set_pll3(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ + + if (clk == 0) { + clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); + return; + } + + /* PLL3 rate = 24000000 * n / m */ + writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | + CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m), + &ccm->pll3_cfg); +} + +void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int max_n = 32; + int k = 1, m = 2; + + if (sigma_delta_enable) + writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); + + /* PLL5 rate = 24000000 * n * k / m */ + if (clk > 24000000 * k * max_n / m) { + m = 1; + if (clk > 24000000 * k * max_n / m) + k = 2; + } + writel(CCM_PLL5_CTRL_EN | + (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | + CCM_PLL5_CTRL_UPD | + CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | + CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); + + udelay(5500); +} + +#ifdef CONFIG_MACH_SUN6I +void clock_set_mipi_pll(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + unsigned int k, m, n, value, diff; + unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff; + unsigned int src = clock_get_pll3(); + + /* All calculations are in KHz to avoid overflows */ + clk /= 1000; + src /= 1000; + + /* Pick the closest lower clock */ + for (k = 1; k <= 4; k++) { + for (m = 1; m <= 16; m++) { + for (n = 1; n <= 16; n++) { + value = src * n * k / m; + if (value > clk) + continue; + + diff = clk - value; + if (diff < best_diff) { + best_diff = diff; + best_k = k; + best_m = m; + best_n = n; + } + if (diff == 0) + goto done; + } + } + } + +done: + writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN | + CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) | + CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg); +} +#endif + +#ifdef CONFIG_MACH_SUN8I_A33 +void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (sigma_delta_enable) + writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg); + + writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD | + (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) | + CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg); + + while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD) + ; +} +#endif + +unsigned int clock_get_pll3(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll3_cfg); + int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; + int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; + + /* Multiply by 1000 after dividing by m to avoid integer overflows */ + return (24000 * n / m) * 1000; +} + +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; + int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; + return 24000000 * n * k / 2; +} + +unsigned int clock_get_mipi_pll(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->mipi_pll_cfg); + unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1; + unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1; + unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1; + unsigned int src = clock_get_pll3(); + + /* Multiply by 1000 after dividing by m to avoid integer overflows */ + return ((src / 1000) * n * k / m) * 1000; +} + +void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) +{ + int pll = clock_get_pll6() * 2; + int div = 1; + + while ((pll / div) > hz) + div++; + + writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), + clk_cfg); +} diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c new file mode 100644 index 0000000..3e8728f --- /dev/null +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -0,0 +1,136 @@ +/* + * A83 specific clock code + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * (C) Copyright 2015 Vishnu Patekar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + clock_set_pll1(408000000); + /* enable pll_hsic, default is 480M */ + writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg); + writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); + while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {} + + /* switch to default 24MHz before changing to hsic */ + writel(0x0, &ccm->cci400_cfg); + sdelay(50); + writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg); + sdelay(100); + + /* switch before changing pll6 */ + clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK, + AHB1_CLK_SRC_OSC24M); + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {} + + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); + writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset); + writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg); + + /* timestamp */ + writel(1, 0x01720000); +} +#endif + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* uart clock source is apb2 */ + writel(APB2_CLK_SRC_OSC24M| + APB2_CLK_RATE_N_1| + APB2_CLK_RATE_M(1), + &ccm->apb2_div); + + /* open the clock for uart */ + setbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + + /* deassert uart reset */ + setbits_le32(&ccm->apb2_reset_cfg, + 1 << (APB2_RESET_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); +} + +#ifdef CONFIG_SPL_BUILD +void clock_set_pll1(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_2 << AXI0_DIV_SHIFT | + AXI_DIV_2 << AXI1_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT | + CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); + + /* clk = 24*n/p, p is ignored if clock is >288MHz */ + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 | + CCM_PLL1_CTRL_N(clk / 24000000), + &ccm->pll1_c0_cfg); + while (!(readl(&ccm->pll_stable_status) & 0x01)) {} + + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 | + CCM_PLL1_CTRL_N(clk / (24000000)), + &ccm->pll1_c1_cfg); + while (!(readl(&ccm->pll_stable_status) & 0x02)) {} + + /* Switch CPU to PLL1 */ + writel(AXI_DIV_2 << AXI0_DIV_SHIFT | + AXI_DIV_2 << AXI1_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT | + CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); +} +#endif + +void clock_set_pll5(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + unsigned int div1 = 0, div2 = 0; + + /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */ + writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD | + CCM_PLL5_CTRL_N(clk / (24000000)) | + div2 << CCM_PLL5_DIV2_SHIFT | + div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg); + + udelay(5500); +} + + +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); + int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> + CCM_PLL6_CTRL_DIV1_SHIFT) + 1; + int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> + CCM_PLL6_CTRL_DIV2_SHIFT) + 1; + return 24000000 * n / div1 / div2; +} diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c new file mode 100644 index 0000000..180634c --- /dev/null +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -0,0 +1,68 @@ +/* + * sun9i specific clock code + * + * (C) Copyright 2015 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* open the clock for uart */ + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + /* deassert uart reset */ + setbits_le32(&ccm->apb1_reset_cfg, + 1 << (APB1_RESET_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + + /* Dup with clock_init_safe(), drop once sun9i SPL support lands */ + writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg); +} + +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (port > 4) + return -1; + + /* set the apb reset and clock gate for twi */ + if (state) { + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); + setbits_le32(&ccm->apb1_reset_cfg, + 1 << (APB1_RESET_TWI_SHIFT + port)); + } else { + clrbits_le32(&ccm->apb1_reset_cfg, + 1 << (APB1_RESET_TWI_SHIFT + port)); + clrbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); + } + + return 0; +} + +unsigned int clock_get_pll4_periph0(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll4_periph0_cfg); + int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT); + int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT); + int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1; + const int k = 1; + + return ((24000000 * n * k) >> p) / m; +} diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c new file mode 100644 index 0000000..c0eabdf --- /dev/null +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MACH_SUN6I +int sunxi_get_ss_bonding_id(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + static int bonding_id = -1; + + if (bonding_id != -1) + return bonding_id; + + /* Enable Security System */ + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS); + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS); + + bonding_id = readl(SUNXI_SS_BASE); + bonding_id = (bonding_id >> 16) & 0x7; + + /* Disable Security System again */ + clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS); + clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS); + + return bonding_id; +} +#endif + +#ifdef CONFIG_MACH_SUN8I +uint sunxi_get_sram_id(void) +{ + uint id; + + /* Unlock sram info reg, read it, relock */ + setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); + id = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; + clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); + + return id; +} +#endif + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ +#ifdef CONFIG_MACH_SUN4I + puts("CPU: Allwinner A10 (SUN4I)\n"); +#elif defined CONFIG_MACH_SUN5I + u32 val = readl(SUNXI_SID_BASE + 0x08); + switch ((val >> 12) & 0xf) { + case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break; + case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break; + case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break; + default: puts("CPU: Allwinner A1X (SUN5I)\n"); + } +#elif defined CONFIG_MACH_SUN6I + switch (sunxi_get_ss_bonding_id()) { + case SUNXI_SS_BOND_ID_A31: + puts("CPU: Allwinner A31 (SUN6I)\n"); + break; + case SUNXI_SS_BOND_ID_A31S: + puts("CPU: Allwinner A31s (SUN6I)\n"); + break; + default: + printf("CPU: Allwinner A31? (SUN6I, id: %d)\n", + sunxi_get_ss_bonding_id()); + } +#elif defined CONFIG_MACH_SUN7I + puts("CPU: Allwinner A20 (SUN7I)\n"); +#elif defined CONFIG_MACH_SUN8I_A23 + printf("CPU: Allwinner A23 (SUN8I %04x)\n", sunxi_get_sram_id()); +#elif defined CONFIG_MACH_SUN8I_A33 + printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id()); +#elif defined CONFIG_MACH_SUN8I_A83T + printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id()); +#elif defined CONFIG_MACH_SUN8I_H3 + printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id()); +#elif defined CONFIG_MACH_SUN9I + puts("CPU: Allwinner A80 (SUN9I)\n"); +#else +#warning Please update cpu_info.c with correct CPU information + puts("CPU: SUNXI Family\n"); +#endif + return 0; +} +#endif + +int sunxi_get_sid(unsigned int *sid) +{ +#ifdef CONFIG_AXP221_POWER + return axp_get_sid(sid); +#elif defined SUNXI_SID_BASE + int i; + + for (i = 0; i< 4; i++) + sid[i] = readl(SUNXI_SID_BASE + 4 * i); + + return 0; +#else + return -ENODEV; +#endif +} diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c new file mode 100644 index 0000000..9a94e1b --- /dev/null +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -0,0 +1,37 @@ +/* + * DRAM init helper functions + * + * (C) Copyright 2015 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * Wait up to 1s for value to be set in given part of reg. + */ +void mctl_await_completion(u32 *reg, u32 mask, u32 val) +{ + unsigned long tmo = timer_get_us() + 1000000; + + while ((readl(reg) & mask) != val) { + if (timer_get_us() > tmo) + panic("Timeout initialising DRAM\n"); + } +} + +/* + * Test if memory at offset offset matches memory at begin of DRAM + */ +bool mctl_mem_matches(u32 offset) +{ + /* Try to write different values to RAM at two addresses */ + writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset); + /* Check if the same value is actually observed when reading back */ + return readl(CONFIG_SYS_SDRAM_BASE) == + readl(CONFIG_SYS_SDRAM_BASE + offset); +} diff --git a/arch/arm/mach-sunxi/dram_sun4i.c b/arch/arm/mach-sunxi/dram_sun4i.c new file mode 100644 index 0000000..f7b4915 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_sun4i.c @@ -0,0 +1,737 @@ +/* + * sunxi DRAM controller initialization + * (C) Copyright 2012 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c + * and earlier U-Boot Allwiner A10 SPL work + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Unfortunately the only documentation we have on the sun7i DRAM + * controller is Allwinner boot0 + boot1 code, and that code uses + * magic numbers & shifts with no explanations. Hence this code is + * rather undocumented and full of magic. + */ + +#include +#include +#include +#include +#include +#include + +#define CPU_CFG_CHIP_VER(n) ((n) << 6) +#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3) +#define CPU_CFG_CHIP_REV_A 0x0 +#define CPU_CFG_CHIP_REV_C1 0x1 +#define CPU_CFG_CHIP_REV_C2 0x2 +#define CPU_CFG_CHIP_REV_B 0x3 + +/* + * Wait up to 1s for mask to be clear in given reg. + */ +static inline void await_bits_clear(u32 *reg, u32 mask) +{ + mctl_await_completion(reg, mask, 0); +} + +/* + * Wait up to 1s for mask to be set in given reg. + */ +static inline void await_bits_set(u32 *reg, u32 mask) +{ + mctl_await_completion(reg, mask, mask); +} + +/* + * This performs the external DRAM reset by driving the RESET pin low and + * then high again. According to the DDR3 spec, the RESET pin needs to be + * kept low for at least 200 us. + */ +static void mctl_ddr3_reset(void) +{ + struct sunxi_dram_reg *dram = + (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + +#ifdef CONFIG_MACH_SUN4I + struct sunxi_timer_reg *timer = + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; + u32 reg_val; + + writel(0, &timer->cpu_cfg); + reg_val = readl(&timer->cpu_cfg); + + if ((reg_val & CPU_CFG_CHIP_VER_MASK) != + CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) { + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(200); + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + } else +#endif + { + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(200); + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + } + /* After the RESET pin is de-asserted, the DDR3 spec requires to wait + * for additional 500 us before driving the CKE pin (Clock Enable) + * high. The duration of this delay can be configured in the SDR_IDCR + * (Initialization Delay Configuration Register) and applied + * automatically by the DRAM controller during the DDR3 initialization + * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and + * can't provide sufficient delay at DRAM clock frequencies higher than + * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to + * 533 MHz according to the datasheet). Additionally, there is no + * official documentation for the SDR_IDCR register anywhere, and + * there is always a chance that we are interpreting it wrong. + * Better be safe than sorry, so add an explicit delay here. */ + udelay(500); +} + +static void mctl_set_drive(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + +#ifdef CONFIG_MACH_SUN7I + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), +#else + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), +#endif + DRAM_MCR_MODE_EN(0x3) | + 0xffc); +} + +static void mctl_itm_disable(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); +} + +static void mctl_itm_enable(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); +} + +static void mctl_itm_reset(void) +{ + mctl_itm_disable(); + udelay(1); /* ITM reset needs a bit of delay */ + mctl_itm_enable(); + udelay(1); +} + +static void mctl_enable_dll0(u32 phase) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + ((phase >> 16) & 0x3f) << 6); + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE); + udelay(2); + + clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE); + udelay(22); + + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET); + udelay(22); +} + +/* Get the number of DDR byte lanes */ +static u32 mctl_get_number_of_lanes(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) == + DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT)) + return 4; + else + return 2; +} + +/* + * Note: This differs from pm/standby in that it checks the bus width + */ +static void mctl_enable_dllx(u32 phase) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 i, number_of_lanes; + + number_of_lanes = mctl_get_number_of_lanes(); + + for (i = 1; i <= number_of_lanes; i++) { + clrsetbits_le32(&dram->dllcr[i], 0xf << 14, + (phase & 0xf) << 14); + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET, + DRAM_DLLCR_DISABLE); + phase >>= 4; + } + udelay(2); + + for (i = 1; i <= number_of_lanes; i++) + clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | + DRAM_DLLCR_DISABLE); + udelay(22); + + for (i = 1; i <= number_of_lanes; i++) + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE, + DRAM_DLLCR_NRESET); + udelay(22); +} + +static u32 hpcr_value[32] = { +#ifdef CONFIG_MACH_SUN5I + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0, + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0x0301, 0 +#endif +#ifdef CONFIG_MACH_SUN4I + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x5031, + 0x1035, 0x0731, 0x1031, 0x0735, + 0x1035, 0x1031, 0x0731, 0x1035, + 0x1031, 0x0301, 0x0301, 0x0731 +#endif +#ifdef CONFIG_MACH_SUN7I + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0x0301, 0x0301, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0x0735, + 0x1035, 0x1031, 0x0731, 0x1035, + 0x0001, 0x1031, 0, 0x1031 + /* last row differs from boot0 source table + * 0x1031, 0x0301, 0x0301, 0x0731 + * but boot0 code skips #28 and #30, and sets #29 and #31 to the + * value from #28 entry (0x1031) + */ +#endif +}; + +static void mctl_configure_hostport(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 i; + + for (i = 0; i < 32; i++) + writel(hpcr_value[i], &dram->hpcr[i]); +} + +static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) +{ + u32 reg_val; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + u32 pll5p_clk, pll6x_clk; + u32 pll5p_div, pll6x_div; + u32 pll5p_rate, pll6x_rate; + + /* setup DRAM PLL */ + reg_val = readl(&ccm->pll5_cfg); + reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */ + reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */ + reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */ + reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */ +#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT + /* Old kernels are hardcoded to P=1 (divide by 2) */ + reg_val |= CCM_PLL5_CTRL_P(1); +#endif + if (clk >= 540 && clk < 552) { + /* dram = 540MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); + } else if (clk >= 512 && clk < 528) { + /* dram = 512MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); + } else if (clk >= 496 && clk < 504) { + /* dram = 496MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); + } else if (clk >= 468 && clk < 480) { + /* dram = 468MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); + } else if (clk >= 396 && clk < 408) { + /* dram = 396MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); + } else { + /* any other frequency that is a multiple of 24 */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); + } + reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */ + reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */ + writel(reg_val, &ccm->pll5_cfg); + udelay(5500); + + setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); + +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) + /* reset GPS */ + clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); + udelay(1); + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); +#endif + + /* setup MBUS clock */ + if (!mbus_clk) + mbus_clk = 300; + + /* PLL5P and PLL6 are the potential clock sources for MBUS */ + pll6x_clk = clock_get_pll6() / 1000000; +#ifdef CONFIG_MACH_SUN7I + pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ +#endif + pll5p_clk = clock_get_pll5p() / 1000000; + pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk); + pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk); + pll6x_rate = pll6x_clk / pll6x_div; + pll5p_rate = pll5p_clk / pll5p_div; + + if (pll6x_div <= 16 && pll6x_rate > pll5p_rate) { + /* use PLL6 as the MBUS clock source */ + reg_val = CCM_MBUS_CTRL_GATE | + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) | + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll6x_div)); + } else if (pll5p_div <= 16) { + /* use PLL5P as the MBUS clock source */ + reg_val = CCM_MBUS_CTRL_GATE | + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) | + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll5p_div)); + } else { + panic("Bad mbus_clk\n"); + } + writel(reg_val, &ccm->mbus_clk_cfg); + + /* + * open DRAMC AHB & DLL register clock + * close it first + */ +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); +#else + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); +#endif + udelay(22); + + /* then open it */ +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); +#else + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); +#endif + udelay(22); +} + +/* + * The data from rslrX and rdgrX registers (X=rank) is stored + * in a single 32-bit value using the following format: + * bits [31:26] - DQS gating system latency for byte lane 3 + * bits [25:24] - DQS gating phase select for byte lane 3 + * bits [23:18] - DQS gating system latency for byte lane 2 + * bits [17:16] - DQS gating phase select for byte lane 2 + * bits [15:10] - DQS gating system latency for byte lane 1 + * bits [ 9:8 ] - DQS gating phase select for byte lane 1 + * bits [ 7:2 ] - DQS gating system latency for byte lane 0 + * bits [ 1:0 ] - DQS gating phase select for byte lane 0 + */ +static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 lane, number_of_lanes = mctl_get_number_of_lanes(); + /* rank0 gating system latency (3 bits per lane: cycles) */ + u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1); + /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */ + u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1); + for (lane = 0; lane < number_of_lanes; lane++) { + u32 tmp = dqs_gating_delay >> (lane * 8); + slr &= ~(7 << (lane * 3)); + slr |= ((tmp >> 2) & 7) << (lane * 3); + dgr &= ~(3 << (lane * 2)); + dgr |= (tmp & 3) << (lane * 2); + } + writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1); + writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1); +} + +static int dramc_scan_readpipe(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + + /* data training trigger */ + clrbits_le32(&dram->csr, DRAM_CSR_FAILED); + setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); + + /* check whether data training process has completed */ + await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING); + + /* check data training result */ + reg_val = readl(&dram->csr); + if (reg_val & DRAM_CSR_FAILED) + return -1; + + return 0; +} + +static void dramc_clock_output_en(u32 on) +{ +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + if (on) + setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); + else + clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); +#endif +#ifdef CONFIG_MACH_SUN4I + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + if (on) + setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); + else + clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT); +#endif +} + +/* tRFC in nanoseconds for different densities (from the DDR3 spec) */ +static const u16 tRFC_DDR3_table[6] = { + /* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */ + 90, 90, 110, 160, 300, 350 +}; + +static void dramc_set_autorefresh_cycle(u32 clk, u32 density) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 tRFC, tREFI; + + tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000; + tREFI = (7987 * clk) >> 10; /* <= 7.8us */ + + writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr); +} + +/* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */ +static u32 ddr3_write_recovery(u32 clk) +{ + u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */ + u32 twr_ck = (twr_ns * clk + 999) / 1000; + if (twr_ck < 5) + return 1; + else if (twr_ck <= 8) + return twr_ck - 4; + else if (twr_ck <= 10) + return 5; + else + return 6; +} + +/* + * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this + * means that DRAM is currently in self-refresh mode and retaining the old + * data. Since we have no idea what to do in this situation yet, just set this + * register to 0 and initialize DRAM in the same way as on any normal reboot + * (discarding whatever was stored there). + * + * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic + * value for this write operation to have any effect. On sun5i hadware this + * magic value is not necessary. And on sun4i hardware the writes to this + * register seem to have no effect at all. + */ +static void mctl_disable_power_save(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + writel(0x16510000, &dram->ppwrsctl); +} + +/* + * After the DRAM is powered up or reset, the DDR3 spec requires to wait at + * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct + * (SDR_IDCR) register appears to configure this delay, which gets applied + * right at the time when the DRAM initialization is activated in the + * 'mctl_ddr3_initialize' function. + */ +static void mctl_set_cke_delay(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + /* The CKE delay is represented in DRAM clock cycles, multiplied by N + * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to + * the maximum possible value 0x1ffff, just like in the Allwinner's + * boot0 bootloader. The resulting delay value is somewhere between + * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i + * with 360 MHz DRAM clock speed). */ + setbits_le32(&dram->idcr, 0x1ffff); +} + +/* + * This triggers the DRAM initialization. It performs sending the mode registers + * to the DRAM among other things. Very likely the ZQCL command is also getting + * executed (to do the initial impedance calibration on the DRAM side of the + * wire). The memory controller and the PHY must be already configured before + * calling this function. + */ +static void mctl_ddr3_initialize(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + setbits_le32(&dram->ccr, DRAM_CCR_INIT); + await_bits_clear(&dram->ccr, DRAM_CCR_INIT); +} + +/* + * Perform impedance calibration on the DRAM controller side of the wire. + */ +static void mctl_set_impedance(u32 zq, bool odt_en) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF; + +#ifndef CONFIG_MACH_SUN7I + /* Appears that some kind of automatically initiated default + * ZQ calibration is already in progress at this point on sun4i/sun5i + * hardware, but not on sun7i. So it is reasonable to wait for its + * completion before doing anything else. */ + await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE); +#endif + + /* ZQ calibration is not really useful unless ODT is enabled */ + if (!odt_en) + return; + +#ifdef CONFIG_MACH_SUN7I + /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock + * unless bit 24 is set in SDR_ZQCR1. Not much is known about the + * SDR_ZQCR1 register, but there are hints indicating that it might + * be related to periodic impedance re-calibration. This particular + * magic value is borrowed from the Allwinner boot0 bootloader, and + * using it helps to avoid troubles */ + writel((1 << 24) | (1 << 1), &dram->zqcr1); +#endif + + /* Needed at least for sun5i, because it does not self clear there */ + clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); + + if (zdata) { + /* Set the user supplied impedance data */ + reg_val = DRAM_ZQCR0_ZDEN | zdata; + writel(reg_val, &dram->zqcr0); + /* no need to wait, this takes effect immediately */ + } else { + /* Do the calibration using the external resistor */ + reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog); + writel(reg_val, &dram->zqcr0); + /* Wait for the new impedance configuration to settle */ + await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE); + } + + /* Needed at least for sun5i, because it does not self clear there */ + clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); + + /* Set I/O configure register */ + writel(DRAM_IOCR_ODT_EN, &dram->iocr); +} + +static unsigned long dramc_init_helper(struct dram_para *para) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + u32 density; + int ret_val; + + /* + * only single rank DDR3 is supported by this code even though the + * hardware can theoretically support DDR2 and up to two ranks + */ + if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1) + return 0; + + /* setup DRAM relative clock */ + mctl_setup_dram_clock(para->clock, para->mbus_clock); + + /* Disable any pad power save control */ + mctl_disable_power_save(); + + mctl_set_drive(); + + /* dram clock off */ + dramc_clock_output_en(0); + +#ifdef CONFIG_MACH_SUN4I + /* select dram controller 1 */ + writel(DRAM_CSEL_MAGIC, &dram->csel); +#endif + + mctl_itm_disable(); + mctl_enable_dll0(para->tpr3); + + /* configure external DRAM */ + reg_val = DRAM_DCR_TYPE_DDR3; + reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3); + + if (para->density == 256) + density = DRAM_DCR_CHIP_DENSITY_256M; + else if (para->density == 512) + density = DRAM_DCR_CHIP_DENSITY_512M; + else if (para->density == 1024) + density = DRAM_DCR_CHIP_DENSITY_1024M; + else if (para->density == 2048) + density = DRAM_DCR_CHIP_DENSITY_2048M; + else if (para->density == 4096) + density = DRAM_DCR_CHIP_DENSITY_4096M; + else if (para->density == 8192) + density = DRAM_DCR_CHIP_DENSITY_8192M; + else + density = DRAM_DCR_CHIP_DENSITY_256M; + + reg_val |= DRAM_DCR_CHIP_DENSITY(density); + reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1); + reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1); + reg_val |= DRAM_DCR_CMD_RANK_ALL; + reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE); + writel(reg_val, &dram->dcr); + + dramc_clock_output_en(1); + + mctl_set_impedance(para->zq, para->odt_en); + + mctl_set_cke_delay(); + + mctl_ddr3_reset(); + + udelay(1); + + await_bits_clear(&dram->ccr, DRAM_CCR_INIT); + + mctl_enable_dllx(para->tpr3); + + /* set refresh period */ + dramc_set_autorefresh_cycle(para->clock, density); + + /* set timing parameters */ + writel(para->tpr0, &dram->tpr0); + writel(para->tpr1, &dram->tpr1); + writel(para->tpr2, &dram->tpr2); + + reg_val = DRAM_MR_BURST_LENGTH(0x0); +#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)) + reg_val |= DRAM_MR_POWER_DOWN; +#endif + reg_val |= DRAM_MR_CAS_LAT(para->cas - 4); + reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock)); + writel(reg_val, &dram->mr); + + writel(para->emr1, &dram->emr); + writel(para->emr2, &dram->emr2); + writel(para->emr3, &dram->emr3); + + /* disable drift compensation and set passive DQS window mode */ + clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); + +#ifdef CONFIG_MACH_SUN7I + /* Command rate timing mode 2T & 1T */ + if (para->tpr4 & 0x1) + setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T); +#endif + /* initialize external DRAM */ + mctl_ddr3_initialize(); + + /* scan read pipe value */ + mctl_itm_enable(); + + /* Hardware DQS gate training */ + ret_val = dramc_scan_readpipe(); + + if (ret_val < 0) + return 0; + + /* allow to override the DQS training results with a custom delay */ + if (para->dqs_gating_delay) + mctl_set_dqs_gating_delay(0, para->dqs_gating_delay); + + /* set the DQS gating window type */ + if (para->active_windowing) + clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE); + else + setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE); + + mctl_itm_reset(); + + /* configure all host port */ + mctl_configure_hostport(); + + return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); +} + +unsigned long dramc_init(struct dram_para *para) +{ + unsigned long dram_size, actual_density; + + /* If the dram configuration is not provided, use a default */ + if (!para) + return 0; + + /* if everything is known, then autodetection is not necessary */ + if (para->io_width && para->bus_width && para->density) + return dramc_init_helper(para); + + /* try to autodetect the DRAM bus width and density */ + para->io_width = 16; + para->bus_width = 32; +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) + /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */ + para->density = 4096; +#else + /* all A0-A15 address lines on A20, which allow density 8192 */ + para->density = 8192; +#endif + + dram_size = dramc_init_helper(para); + if (!dram_size) { + /* if 32-bit bus width failed, try 16-bit bus width instead */ + para->bus_width = 16; + dram_size = dramc_init_helper(para); + if (!dram_size) { + /* if 16-bit bus width also failed, then bail out */ + return dram_size; + } + } + + /* check if we need to adjust the density */ + actual_density = (dram_size >> 17) * para->io_width / para->bus_width; + + if (actual_density != para->density) { + /* update the density and re-initialize DRAM again */ + para->density = actual_density; + dram_size = dramc_init_helper(para); + } + + return dram_size; +} diff --git a/arch/arm/mach-sunxi/dram_sun6i.c b/arch/arm/mach-sunxi/dram_sun6i.c new file mode 100644 index 0000000..5dbbf61 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_sun6i.c @@ -0,0 +1,411 @@ +/* + * Sun6i platform dram controller init. + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * (C) Copyright 2014 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000) + +struct dram_sun6i_para { + u8 bus_width; + u8 chan; + u8 rank; + u8 rows; + u16 page_size; +}; + +static void mctl_sys_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int dram_clk_div = 2; + + clock_set_pll5(DRAM_CLK * dram_clk_div, false); + + clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, + CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST | + CCM_DRAMCLK_CFG_UPD); + mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); + + writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg); + + /* deassert mctl reset */ + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + + /* enable mctl clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); +} + +static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para) +{ + struct sunxi_mctl_phy_reg *mctl_phy; + + if (ch_index == 0) + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + else + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + + /* disable + reset dlls */ + writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr); + writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr); + } + udelay(2); + + /* enable + reset dlls */ + writel(0, &mctl_phy->acdllcr); + writel(0, &mctl_phy->dx0dllcr); + writel(0, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(0, &mctl_phy->dx2dllcr); + writel(0, &mctl_phy->dx3dllcr); + } + udelay(22); + + /* enable and release reset of dlls */ + writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr); + if (para->bus_width == 32) { + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr); + writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr); + } + udelay(22); +} + +static bool mctl_rank_detect(u32 *gsr0, int rank) +{ + const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank; + const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank; + + mctl_await_completion(gsr0, done, done); + mctl_await_completion(gsr0 + 0x10, done, done); + + return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err); +} + +static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg *mctl_ctl; + struct sunxi_mctl_phy_reg *mctl_phy; + + if (ch_index == 0) { + mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + } else { + mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE; + mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + } + + writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd); + mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0); + + /* PHY initialization */ + writel(MCTL_PGCR, &mctl_phy->pgcr); + writel(MCTL_MR0, &mctl_phy->mr0); + writel(MCTL_MR1, &mctl_phy->mr1); + writel(MCTL_MR2, &mctl_phy->mr2); + writel(MCTL_MR3, &mctl_phy->mr3); + + writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST, + &mctl_phy->ptr0); + + writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1); + writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2); + + writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) | + (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) | + (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0), + &mctl_phy->dtpr0); + + writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) | + (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) | + ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) | + (MCTL_TAOND << 0), &mctl_phy->dtpr1); + + writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) | + (MCTL_TEXSR << 0), &mctl_phy->dtpr2); + + writel(1, &mctl_ctl->dfitphyupdtype0); + writel(MCTL_DCR_DDR3, &mctl_phy->dcr); + writel(MCTL_DSGCR, &mctl_phy->dsgcr); + writel(MCTL_DXCCR, &mctl_phy->dxccr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr); + writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr); + + mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03); + + writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1); + + setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); + writel(MCTL_PIR_STEP1, &mctl_phy->pir); + udelay(10); + mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f); + + /* rank detect */ + if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) { + para->rank = 1; + clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK); + } + + /* + * channel detect, check channel 1 dx0 and dx1 have rank 0, if not + * assume nothing is connected to channel 1. + */ + if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) { + para->chan = 1; + clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); + return; + } + + /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */ + if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) { + para->bus_width = 16; + para->page_size = 2048; + setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE); + setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE); + clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN); + clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN); + } + + setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); + writel(MCTL_PIR_STEP2, &mctl_phy->pir); + udelay(10); + mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11); + + if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK) + panic("Training error initialising DRAM\n"); + + /* Move to configure state */ + writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl); + mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01); + + /* Set number of clks per micro-second */ + writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u); + /* Set number of clks per 100 nano-seconds */ + writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n); + /* Set memory timing registers */ + writel(MCTL_TREFI, &mctl_ctl->trefi); + writel(MCTL_TMRD, &mctl_ctl->tmrd); + writel(MCTL_TRFC, &mctl_ctl->trfc); + writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp); + writel(MCTL_TRTW, &mctl_ctl->trtw); + writel(MCTL_TAL, &mctl_ctl->tal); + writel(MCTL_TCL, &mctl_ctl->tcl); + writel(MCTL_TCWL, &mctl_ctl->tcwl); + writel(MCTL_TRAS, &mctl_ctl->tras); + writel(MCTL_TRC, &mctl_ctl->trc); + writel(MCTL_TRCD, &mctl_ctl->trcd); + writel(MCTL_TRRD, &mctl_ctl->trrd); + writel(MCTL_TRTP, &mctl_ctl->trtp); + writel(MCTL_TWR, &mctl_ctl->twr); + writel(MCTL_TWTR, &mctl_ctl->twtr); + writel(MCTL_TEXSR, &mctl_ctl->texsr); + writel(MCTL_TXP, &mctl_ctl->txp); + writel(MCTL_TXPDLL, &mctl_ctl->txpdll); + writel(MCTL_TZQCS, &mctl_ctl->tzqcs); + writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi); + writel(MCTL_TDQS, &mctl_ctl->tdqs); + writel(MCTL_TCKSRE, &mctl_ctl->tcksre); + writel(MCTL_TCKSRX, &mctl_ctl->tcksrx); + writel(MCTL_TCKE, &mctl_ctl->tcke); + writel(MCTL_TMOD, &mctl_ctl->tmod); + writel(MCTL_TRSTL, &mctl_ctl->trstl); + writel(MCTL_TZQCL, &mctl_ctl->tzqcl); + writel(MCTL_TMRR, &mctl_ctl->tmrr); + writel(MCTL_TCKESR, &mctl_ctl->tckesr); + writel(MCTL_TDPD, &mctl_ctl->tdpd); + + /* Unknown magic performed by boot0 */ + setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3); + clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f); + + /* Select 16/32-bits mode for MCTL */ + if (para->bus_width == 16) + setbits_le32(&mctl_ctl->ppcfg, 1); + + /* Set DFI timing registers */ + writel(MCTL_TCWL, &mctl_ctl->dfitphywrl); + writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden); + writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl); + writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0); + + writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg); + + /* DFI update configuration register */ + writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg); + + /* Move to access state */ + writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl); + mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x03); +} + +static void mctl_com_init(struct dram_sun6i_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_phy_reg * const mctl_phy1 = + (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; + struct sunxi_prcm_reg * const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 | + ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) | + MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | + MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); + + /* Unknown magic performed by boot0 */ + setbits_le32(&mctl_com->dbgcr, (1 << 6)); + + if (para->chan == 1) { + /* Shutdown channel 1 */ + setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE); + setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE); + clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE); + /* + * CH0 ?? this is what boot0 does. Leave as is until we can + * confirm this. + */ + setbits_le32(&prcm->vdd_sys_pwroff, + PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF); + } +} + +static void mctl_port_cfg(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* enable DRAM AXI clock for CPU access */ + setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM); + + /* Bunch of magic writes performed by boot0 */ + writel(0x00400302, &mctl_com->rmcr[0]); + writel(0x01000307, &mctl_com->rmcr[1]); + writel(0x00400302, &mctl_com->rmcr[2]); + writel(0x01000307, &mctl_com->rmcr[3]); + writel(0x01000307, &mctl_com->rmcr[4]); + writel(0x01000303, &mctl_com->rmcr[6]); + writel(0x01000303, &mctl_com->mmcr[0]); + writel(0x00400310, &mctl_com->mmcr[1]); + writel(0x01000307, &mctl_com->mmcr[2]); + writel(0x01000303, &mctl_com->mmcr[3]); + writel(0x01800303, &mctl_com->mmcr[4]); + writel(0x01800303, &mctl_com->mmcr[5]); + writel(0x01800303, &mctl_com->mmcr[6]); + writel(0x01800303, &mctl_com->mmcr[7]); + writel(0x01000303, &mctl_com->mmcr[8]); + writel(0x00000002, &mctl_com->mmcr[15]); + writel(0x00000310, &mctl_com->mbagcr[0]); + writel(0x00400310, &mctl_com->mbagcr[1]); + writel(0x00400310, &mctl_com->mbagcr[2]); + writel(0x00000307, &mctl_com->mbagcr[3]); + writel(0x00000317, &mctl_com->mbagcr[4]); + writel(0x00000307, &mctl_com->mbagcr[5]); +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + u32 offset; + int bank, bus, columns; + + /* Set initial parameters, these get modified by the autodetect code */ + struct dram_sun6i_para para = { + .bus_width = 32, + .chan = 2, + .rank = 2, + .page_size = 4096, + .rows = 16, + }; + + /* A31s only has one channel */ + if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S) + para.chan = 1; + + mctl_sys_init(); + + mctl_dll_init(0, ¶); + setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); + + if (para.chan == 2) { + mctl_dll_init(1, ¶); + setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); + } + + setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN); + + mctl_channel_init(0, ¶); + if (para.chan == 2) + mctl_channel_init(1, ¶); + + mctl_com_init(¶); + mctl_port_cfg(); + + /* + * Change to 1 ch / sequence / 8192 byte pages / 16 rows / + * 8 bit banks / 1 rank mode. + */ + clrsetbits_le32(&mctl_com->cr, + MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK | + MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, + MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE | + MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) | + MCTL_CR_BANK(1) | MCTL_CR_RANK(1)); + + /* Detect and set page size */ + for (columns = 7; columns < 20; columns++) { + if (mctl_mem_matches(1 << columns)) + break; + } + bus = (para.bus_width == 32) ? 2 : 1; + columns -= bus; + para.page_size = (1 << columns) * (bus << 1); + clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK, + MCTL_CR_PAGE_SIZE(para.page_size)); + + /* Detect and set rows */ + for (para.rows = 11; para.rows < 16; para.rows++) { + offset = 1 << (para.rows + columns + bus); + if (mctl_mem_matches(offset)) + break; + } + clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, + MCTL_CR_ROW(para.rows)); + + /* Detect bank size */ + offset = 1 << (para.rows + columns + bus + 2); + bank = mctl_mem_matches(offset) ? 0 : 1; + + /* Restore interleave, chan and rank values, set bank size */ + clrsetbits_le32(&mctl_com->cr, + MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE | + MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK, + MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) | + MCTL_CR_RANK(para.rank)); + + return 1 << (para.rank + para.rows + bank + columns + para.chan + bus); +} diff --git a/arch/arm/mach-sunxi/dram_sun8i_a23.c b/arch/arm/mach-sunxi/dram_sun8i_a23.c new file mode 100644 index 0000000..c53671a --- /dev/null +++ b/arch/arm/mach-sunxi/dram_sun8i_a23.c @@ -0,0 +1,343 @@ +/* + * Sun8i platform dram controller init. + * + * (C) Copyright 2014 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Note this code uses a lot of magic hex values, that is because this code + * simply replays the init sequence as done by the Allwinner boot0 code, so + * we do not know what these values mean. There are no symbolic constants for + * these magic values, since we do not know how to name them and making up + * names for them is not useful. + * + * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one + * found in the TI Keystone2 documentation: + * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf + * "Table4-2 DDR3 PHY Registers" + * This may be used as a (possible) reference for future work / cleanups. + */ + +#include +#include +#include +#include +#include +#include + +static const struct dram_para dram_para = { + .clock = CONFIG_DRAM_CLK, + .type = 3, + .zq = CONFIG_DRAM_ZQ, + .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), + .odt_correction = CONFIG_DRAM_ODT_CORRECTION, + .para1 = 0, /* not used (only used when tpr13 bit 31 is set */ + .para2 = 0, /* not used (only used when tpr13 bit 31 is set */ + .mr0 = 6736, + .mr1 = 4, + .mr2 = 16, + .mr3 = 0, + /* tpr0 - 10 contain timing constants or-ed together in u32 vals */ + .tpr0 = 0x2ab83def, + .tpr1 = 0x18082356, + .tpr2 = 0x00034156, + .tpr3 = 0x448c5533, + .tpr4 = 0x08010d00, + .tpr5 = 0x0340b20f, + .tpr6 = 0x20d118cc, + .tpr7 = 0x14062485, + .tpr8 = 0x220d1d52, + .tpr9 = 0x1e078c22, + .tpr10 = 0x3c, + .tpr11 = 0, /* not used */ + .tpr12 = 0, /* not used */ + .tpr13 = 0x30000, +}; + +static void mctl_sys_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* enable pll5, note the divide by 2 is deliberate! */ + clock_set_pll5(dram_para.clock * 1000000 / 2, + dram_para.tpr13 & 0x40000); + + /* deassert ahb mctl reset */ + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + + /* enable ahb mctl clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); +} + +static void mctl_apply_odt_correction(u32 *reg, int correction) +{ + int val; + + val = (readl(reg) >> 8) & 0xff; + val += correction; + + /* clamp */ + if (val < 0) + val = 0; + else if (val > 255) + val = 255; + + clrsetbits_le32(reg, 0xff00, val << 8); +} + +static void mctl_init(u32 *bus_width) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + struct sunxi_mctl_phy_reg * const mctl_phy = + (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + + if (dram_para.tpr13 & 0x20) + writel(0x40b, &mctl_phy->dcr); + else + writel(0x1000040b, &mctl_phy->dcr); + + if (dram_para.clock >= 480) + writel(0x5c000, &mctl_phy->dllgcr); + else + writel(0xdc000, &mctl_phy->dllgcr); + + writel(0x0a003e3f, &mctl_phy->pgcr0); + writel(0x03008421, &mctl_phy->pgcr1); + + writel(dram_para.mr0, &mctl_phy->mr0); + writel(dram_para.mr1, &mctl_phy->mr1); + writel(dram_para.mr2, &mctl_phy->mr2); + writel(dram_para.mr3, &mctl_phy->mr3); + + if (!(dram_para.tpr13 & 0x10000)) { + clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000); + clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000); + } + + /* + * All the masking and shifting below converts what I assume are DDR + * timing constants from Allwinner dram_para tpr format to the actual + * timing registers format. + */ + + writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2); + writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3); + writel((dram_para.tpr0 & 0x3ff00000) >> 2 | + (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4); + + writel(dram_para.tpr3, &mctl_phy->dtpr0); + writel(dram_para.tpr4, &mctl_phy->dtpr2); + + writel(0x01000081, &mctl_phy->dtcr); + + if (dram_para.clock <= 240 || !dram_para.odt_en) { + clrbits_le32(&mctl_phy->dx0gcr, 0x600); + clrbits_le32(&mctl_phy->dx1gcr, 0x600); + } + if (dram_para.clock <= 240) { + writel(0, &mctl_phy->odtcr); + writel(0, &mctl_ctl->odtmap); + } + + writel(((dram_para.tpr5 & 0x0f00) << 12) | + ((dram_para.tpr5 & 0x00f8) << 9) | + ((dram_para.tpr5 & 0x0007) << 8), + &mctl_ctl->rfshctl0); + + writel(((dram_para.tpr5 & 0x0003f000) << 12) | + ((dram_para.tpr5 & 0x00fc0000) >> 2) | + ((dram_para.tpr5 & 0x3f000000) >> 16) | + ((dram_para.tpr6 & 0x0000003f) >> 0), + &mctl_ctl->dramtmg0); + + writel(((dram_para.tpr6 & 0x000007c0) << 10) | + ((dram_para.tpr6 & 0x0000f800) >> 3) | + ((dram_para.tpr6 & 0x003f0000) >> 16), + &mctl_ctl->dramtmg1); + + writel(((dram_para.tpr6 & 0x0fc00000) << 2) | + ((dram_para.tpr7 & 0x0000001f) << 16) | + ((dram_para.tpr7 & 0x000003e0) << 3) | + ((dram_para.tpr7 & 0x0000fc00) >> 10), + &mctl_ctl->dramtmg2); + + writel(((dram_para.tpr7 & 0x03ff0000) >> 16) | + ((dram_para.tpr6 & 0xf0000000) >> 16), + &mctl_ctl->dramtmg3); + + writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) | + ((dram_para.tpr8 & 0x00000007) << 16) | + ((dram_para.tpr8 & 0x00000038) << 5) | + ((dram_para.tpr8 & 0x000003c0) >> 6), + &mctl_ctl->dramtmg4); + + writel(((dram_para.tpr8 & 0x00003c00) << 14) | + ((dram_para.tpr8 & 0x0003c000) << 2) | + ((dram_para.tpr8 & 0x00fc0000) >> 10) | + ((dram_para.tpr8 & 0x0f000000) >> 24), + &mctl_ctl->dramtmg5); + + writel(0x00000008, &mctl_ctl->dramtmg8); + + writel(((dram_para.tpr8 & 0xf0000000) >> 4) | + ((dram_para.tpr9 & 0x00007c00) << 6) | + ((dram_para.tpr9 & 0x000003e0) << 3) | + ((dram_para.tpr9 & 0x0000001f) >> 0), + &mctl_ctl->pitmg0); + + setbits_le32(&mctl_ctl->pitmg1, 0x80000); + + writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001, + &mctl_ctl->sched); + + writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); + writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); + + writel(0x00000000, &mctl_ctl->pimisc); + writel(0x80000000, &mctl_ctl->upd0); + + writel(((dram_para.tpr9 & 0xffc00000) >> 22) | + ((dram_para.tpr10 & 0x00000fff) << 16), + &mctl_ctl->rfshtmg); + + if (dram_para.tpr13 & 0x20) + writel(0x01040001, &mctl_ctl->mstr); + else + writel(0x01040401, &mctl_ctl->mstr); + + if (!(dram_para.tpr13 & 0x20000)) { + writel(0x00000002, &mctl_ctl->pwrctl); + writel(0x00008001, &mctl_ctl->pwrtmg); + } + + writel(0x00000001, &mctl_ctl->rfshctl3); + writel(0x00000001, &mctl_ctl->pimisc); + + /* deassert dram_clk_cfg reset */ + setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); + + setbits_le32(&mctl_com->ccr, 0x80000); + + /* zq stuff */ + writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1); + + writel(0x00000003, &mctl_phy->pir); + udelay(10); + mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09); + + writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2); + writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); + + /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */ + writel(0x000005f3, &mctl_phy->pir); + udelay(10); + mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03); + + if (readl(&mctl_phy->dx1gsr0) & 0x1000000) { + *bus_width = 8; + writel(0, &mctl_phy->dx1gcr); + writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); + writel(0x5f3, &mctl_phy->pir); + udelay(10000); + setbits_le32(&mctl_ctl->mstr, 0x1000); + } else + *bus_width = 16; + + if (dram_para.odt_correction) { + mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, + dram_para.odt_correction); + mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, + dram_para.odt_correction); + } + + mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01); + + writel(0x08003e3f, &mctl_phy->pgcr0); + writel(0x00000000, &mctl_ctl->rfshctl3); +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + const u32 columns = 13; + u32 bus, bus_width, offset, page_size, rows; + + mctl_sys_init(); + mctl_init(&bus_width); + + if (bus_width == 16) { + page_size = 8; + bus = 1; + } else { + page_size = 7; + bus = 0; + } + + if (!(dram_para.tpr13 & 0x80000000)) { + /* Detect and set rows */ + writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size), + &mctl_com->cr); + setbits_le32(&mctl_com->swonr, 0x0003ffff); + for (rows = 11; rows < 16; rows++) { + offset = 1 << (rows + columns + bus); + if (mctl_mem_matches(offset)) + break; + } + clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, + MCTL_CR_ROW(rows)); + } else { + rows = (dram_para.para1 >> 16) & 0xff; + writel(((dram_para.para2 & 0x000000f0) << 11) | + ((rows - 1) << 4) | + ((dram_para.para1 & 0x0f000000) >> 22) | + 0x31000 | MCTL_CR_PAGE_SIZE(page_size), + &mctl_com->cr); + setbits_le32(&mctl_com->swonr, 0x0003ffff); + } + + /* Setup DRAM master priority? If this is left out things still work */ + writel(0x00000008, &mctl_com->mcr0_0); + writel(0x0001000d, &mctl_com->mcr1_0); + writel(0x00000004, &mctl_com->mcr0_1); + writel(0x00000080, &mctl_com->mcr1_1); + writel(0x00000004, &mctl_com->mcr0_2); + writel(0x00000019, &mctl_com->mcr1_2); + writel(0x00000004, &mctl_com->mcr0_3); + writel(0x00000080, &mctl_com->mcr1_3); + writel(0x00000004, &mctl_com->mcr0_4); + writel(0x01010040, &mctl_com->mcr1_4); + writel(0x00000004, &mctl_com->mcr0_5); + writel(0x0001002f, &mctl_com->mcr1_5); + writel(0x00000004, &mctl_com->mcr0_6); + writel(0x00010020, &mctl_com->mcr1_6); + writel(0x00000004, &mctl_com->mcr0_7); + writel(0x00010020, &mctl_com->mcr1_7); + writel(0x00000008, &mctl_com->mcr0_8); + writel(0x00000001, &mctl_com->mcr1_8); + writel(0x00000008, &mctl_com->mcr0_9); + writel(0x00000005, &mctl_com->mcr1_9); + writel(0x00000008, &mctl_com->mcr0_10); + writel(0x00000003, &mctl_com->mcr1_10); + writel(0x00000008, &mctl_com->mcr0_11); + writel(0x00000005, &mctl_com->mcr1_11); + writel(0x00000008, &mctl_com->mcr0_12); + writel(0x00000003, &mctl_com->mcr1_12); + writel(0x00000008, &mctl_com->mcr0_13); + writel(0x00000004, &mctl_com->mcr1_13); + writel(0x00000008, &mctl_com->mcr0_14); + writel(0x00000002, &mctl_com->mcr1_14); + writel(0x00000008, &mctl_com->mcr0_15); + writel(0x00000003, &mctl_com->mcr1_15); + writel(0x00010138, &mctl_com->bwcr); + + return 1 << (rows + columns + bus); +} diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c new file mode 100644 index 0000000..fa1620c --- /dev/null +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -0,0 +1,362 @@ +/* + * Sun8i a33 platform dram controller init. + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang + * (C) Copyright 2015 Vishnu Patekar + * (C) Copyright 2015 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +/* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */ +#define DRAM_CLK_MUL 2 +#define DRAM_CLK_DIV 4 +#define DRAM_SIGMA_DELTA_ENABLE 1 + +struct dram_para { + u8 cs1; + u8 seq; + u8 bank; + u8 rank; + u8 rows; + u8 bus_width; + u16 page_size; +}; + +static void mctl_set_cr(struct dram_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | + MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 | + (para->seq ? MCTL_CR_SEQUENCE : 0) | + ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | + MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | + MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), + &mctl_com->cr); +} + +static void auto_detect_dram_size(struct dram_para *para) +{ + u8 orig_rank = para->rank; + int rows, columns; + + /* Row detect */ + para->page_size = 512; + para->seq = 1; + para->rows = 16; + para->rank = 1; + mctl_set_cr(para); + for (rows = 11 ; rows < 16 ; rows++) { + if (mctl_mem_matches(1 << (rows + 9))) /* row-column */ + break; + } + + /* Column (page size) detect */ + para->rows = 11; + para->page_size = 8192; + mctl_set_cr(para); + for (columns = 9 ; columns < 13 ; columns++) { + if (mctl_mem_matches(1 << columns)) + break; + } + + para->seq = 0; + para->rank = orig_rank; + para->rows = rows; + para->page_size = 1 << columns; + mctl_set_cr(para); +} + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = + CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV; + + return (ctrl_freq * nanoseconds + 999) / 1000; +} + +static void auto_set_timing_para(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + u32 reg_val; + + u8 tccd = 2; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 4); + u8 trcd = ns_to_t(15); + u8 trc = ns_to_t(53); + u8 txp = max(ns_to_t(8), 3); + u8 twtr = max(ns_to_t(8), 4); + u8 trtp = max(ns_to_t(8), 4); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(38); + + u16 trefi = ns_to_t(7800) / 32; + u16 trfc = ns_to_t(350); + + /* Fixed timing parameters */ + u8 tmrw = 0; + u8 tmrd = 4; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 24; + u8 tcl = 6; /* CL 12 */ + u8 tcwl = 4; /* CWL 8 */ + u8 t_rdata_en = 4; + u8 wr_latency = 2; + + u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ + u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* Set work mode register */ + mctl_set_cr(para); + /* Set mode register */ + writel(MCTL_MR0, &mctl_ctl->mr0); + writel(MCTL_MR1, &mctl_ctl->mr1); + writel(MCTL_MR2, &mctl_ctl->mr2); + writel(MCTL_MR3, &mctl_ctl->mr3); + /* Set dram timing */ + reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); + writel(reg_val, &mctl_ctl->dramtmg0); + reg_val = (txp << 16) | (trtp << 8) | (trc << 0); + writel(reg_val, &mctl_ctl->dramtmg1); + reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); + writel(reg_val, &mctl_ctl->dramtmg2); + reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); + writel(reg_val, &mctl_ctl->dramtmg3); + reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); + writel(reg_val, &mctl_ctl->dramtmg4); + reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); + writel(reg_val, &mctl_ctl->dramtmg5); + /* Set two rank timing and exit self-refresh timing */ + reg_val = readl(&mctl_ctl->dramtmg8); + reg_val &= ~(0xff << 8); + reg_val &= ~(0xff << 0); + reg_val |= (0x33 << 8); + reg_val |= (0x8 << 0); + writel(reg_val, &mctl_ctl->dramtmg8); + /* Set phy interface time */ + reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) + | (wr_latency << 0); + /* PHY interface write latency and read latency configure */ + writel(reg_val, &mctl_ctl->pitmg0); + /* Set phy time PTR0-2 use default */ + writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3); + writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4); + /* Set refresh timing */ + reg_val = (trefi << 16) | (trfc << 0); + writel(reg_val, &mctl_ctl->rfshtmg); +} + +static void mctl_set_pir(u32 val) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + writel(val, &mctl_ctl->pir); + mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1); +} + +static void mctl_data_train_cfg(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + if (para->rank == 2) + clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); + else + clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); +} + +static int mctl_train_dram(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + mctl_data_train_cfg(para); + mctl_set_pir(0x5f3); + + return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; +} + +static int mctl_channel_init(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + u32 low_data_lines_status; /* Training status of datalines 0 - 7 */ + u32 high_data_lines_status; /* Training status of datalines 8 - 15 */ + + auto_set_timing_para(para); + + /* Disable dram VTC */ + clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0); + + /* Set ODT */ + if ((CONFIG_DRAM_CLK > 400) && IS_ENABLED(CONFIG_DRAM_ODT_EN)) { + setbits_le32(DXnGCR0(0), 0x3 << 9); + setbits_le32(DXnGCR0(1), 0x3 << 9); + } else { + clrbits_le32(DXnGCR0(0), 0x3 << 9); + clrbits_le32(DXnGCR0(1), 0x3 << 9); + } + + /* set PLL configuration */ + if (CONFIG_DRAM_CLK >= 480) + setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18); + else + setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18); + + /* Auto detect dram config, set 2 rank and 16bit bus-width */ + para->cs1 = 0; + para->rank = 2; + para->bus_width = 16; + mctl_set_cr(para); + + /* Open DQS gating */ + clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); + clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7)); + + mctl_data_train_cfg(para); + + /* ZQ calibration */ + writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1); + /* CA calibration */ + mctl_set_pir(0x00000003); + /* More ZQ calibration */ + writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2); + writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1); + + /* DQS gate training */ + if (mctl_train_dram(para) != 0) { + low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03; + high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03; + + if (low_data_lines_status == 0x3) + return -EIO; + + /* DRAM has only one rank */ + para->rank = 1; + mctl_set_cr(para); + + if (low_data_lines_status == high_data_lines_status) + goto done; /* 16 bit bus, 1 rank */ + + if (!(low_data_lines_status & high_data_lines_status)) { + /* Retry 16 bit bus-width with CS1 set */ + para->cs1 = 1; + mctl_set_cr(para); + if (mctl_train_dram(para) == 0) + goto done; + } + + /* Try 8 bit bus-width */ + writel(0x0, DXnGCR0(1)); /* Disable high DQ */ + para->cs1 = 0; + para->bus_width = 8; + mctl_set_cr(para); + if (mctl_train_dram(para) != 0) + return -EIO; + } +done: + /* Check the dramc status */ + mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); + + /* Close DQS gating */ + setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6); + + /* Enable master access */ + writel(0xffffffff, &mctl_com->maer); + + return 0; +} + +static void mctl_sys_init(struct dram_para *para) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + clrsetbits_le32(&ccm->dram_pll_cfg, CCM_DRAMPLL_CFG_SRC_MASK, + CCM_DRAMPLL_CFG_SRC_PLL11); + + clock_set_pll11(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL, + DRAM_SIGMA_DELTA_ENABLE); + + clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, + CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) | + CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD); + mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); + + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); + + /* Set dram master access priority */ + writel(0x0, &mctl_com->mapr); + writel(0x0f802f01, &mctl_ctl->sched); + writel(0x0000400f, &mctl_ctl->clken); /* normal */ + + udelay(250); +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + struct dram_para para = { + .cs1 = 0, + .bank = 1, + .rank = 1, + .rows = 15, + .bus_width = 16, + .page_size = 2048, + }; + + mctl_sys_init(¶); + + if (mctl_channel_init(¶) != 0) + return 0; + + auto_detect_dram_size(¶); + + /* Enable master software clk */ + writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); + + /* Set DRAM ODT MAP */ + if (para.rank == 2) + writel(0x00000303, &mctl_ctl->odtmap); + else + writel(0x00000201, &mctl_ctl->odtmap); + + return para.page_size * (para.bus_width / 8) * + (1 << (para.bank + para.rank + para.rows)); +} diff --git a/arch/arm/mach-sunxi/dram_sun8i_a83t.c b/arch/arm/mach-sunxi/dram_sun8i_a83t.c new file mode 100644 index 0000000..55df1b9 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_sun8i_a83t.c @@ -0,0 +1,472 @@ +/* + * Sun8i a33 platform dram controller init. + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang + * (C) Copyright 2015 Vishnu Patekar + * (C) Copyright 2015 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +#define DRAM_CLK_MUL 2 +#define DRAM_CLK_DIV 1 + +struct dram_para { + u8 cs1; + u8 seq; + u8 bank; + u8 rank; + u8 rows; + u8 bus_width; + u8 dram_type; + u16 page_size; +}; + +static void mctl_set_cr(struct dram_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | + MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | + (para->seq ? MCTL_CR_SEQUENCE : 0) | + ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | + MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | + MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), + &mctl_com->cr); +} + +static void auto_detect_dram_size(struct dram_para *para) +{ + u8 orig_rank = para->rank; + int rows, columns; + + /* Row detect */ + para->page_size = 512; + para->seq = 1; + para->rows = 16; + para->rank = 1; + mctl_set_cr(para); + for (rows = 11 ; rows < 16 ; rows++) { + if (mctl_mem_matches(1 << (rows + 9))) /* row-column */ + break; + } + + /* Column (page size) detect */ + para->rows = 11; + para->page_size = 8192; + mctl_set_cr(para); + for (columns = 9 ; columns < 13 ; columns++) { + if (mctl_mem_matches(1 << columns)) + break; + } + + para->seq = 0; + para->rank = orig_rank; + para->rows = rows; + para->page_size = 1 << columns; + mctl_set_cr(para); +} + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = + CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV; + + return (ctrl_freq * nanoseconds + 999) / 1000; +} + +static void auto_set_timing_para(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u32 reg_val; + + u8 tccd = 2; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 4); + u8 trcd = ns_to_t(15); + u8 trc = ns_to_t(53); + u8 txp = max(ns_to_t(8), 3); + u8 twtr = max(ns_to_t(8), 4); + u8 trtp = max(ns_to_t(8), 4); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(38); + + u16 trefi = ns_to_t(7800) / 32; + u16 trfc = ns_to_t(350); + + /* Fixed timing parameters */ + u8 tmrw = 0; + u8 tmrd = 4; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 24; + u8 tcl = 6; /* CL 12 */ + u8 tcwl = 4; /* CWL 8 */ + u8 t_rdata_en = 4; + u8 wr_latency = 2; + + u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ + u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* Set work mode register */ + mctl_set_cr(para); + /* Set mode register */ + if (para->dram_type == DRAM_TYPE_DDR3) { + writel(MCTL_MR0, &mctl_ctl->mr0); + writel(MCTL_MR1, &mctl_ctl->mr1); + writel(MCTL_MR2, &mctl_ctl->mr2); + writel(MCTL_MR3, &mctl_ctl->mr3); + } else if (para->dram_type == DRAM_TYPE_LPDDR3) { + writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0); + writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1); + writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2); + writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3); + + /* timing parameters for LPDDR3 */ + tfaw = max(ns_to_t(50), 4); + trrd = max(ns_to_t(10), 2); + trcd = max(ns_to_t(24), 2); + trc = ns_to_t(70); + txp = max(ns_to_t(8), 2); + twtr = max(ns_to_t(8), 2); + trtp = max(ns_to_t(8), 2); + trp = max(ns_to_t(27), 2); + tras = ns_to_t(42); + trefi = ns_to_t(3900) / 32; + trfc = ns_to_t(210); + tmrw = 5; + tmrd = 5; + tckesr = 5; + tcwl = 3; /* CWL 8 */ + t_rdata_en = 5; + tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */ + tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 200us */ + tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */ + twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */ + trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */ + } + /* Set dram timing */ + reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); + writel(reg_val, &mctl_ctl->dramtmg0); + reg_val = (txp << 16) | (trtp << 8) | (trc << 0); + writel(reg_val, &mctl_ctl->dramtmg1); + reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); + writel(reg_val, &mctl_ctl->dramtmg2); + reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); + writel(reg_val, &mctl_ctl->dramtmg3); + reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0); + writel(reg_val, &mctl_ctl->dramtmg4); + reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); + writel(reg_val, &mctl_ctl->dramtmg5); + /* Set two rank timing and exit self-refresh timing */ + reg_val = readl(&mctl_ctl->dramtmg8); + reg_val &= ~(0xff << 8); + reg_val &= ~(0xff << 0); + reg_val |= (0x33 << 8); + reg_val |= (0x8 << 0); + writel(reg_val, &mctl_ctl->dramtmg8); + /* Set phy interface time */ + reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) + | (wr_latency << 0); + /* PHY interface write latency and read latency configure */ + writel(reg_val, &mctl_ctl->pitmg0); + /* Set phy time PTR0-2 use default */ + writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3); + writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4); + /* Set refresh timing */ + reg_val = (trefi << 16) | (trfc << 0); + writel(reg_val, &mctl_ctl->rfshtmg); +} + +static void mctl_set_pir(u32 val) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + writel(val, &mctl_ctl->pir); + mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1); +} + +static void mctl_data_train_cfg(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + if (para->rank == 2) + clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); + else + clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); +} + +static int mctl_train_dram(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + mctl_data_train_cfg(para); + mctl_set_pir(0x5f3); + + return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; +} + +static void set_master_priority(void) +{ + writel(0x00a0000d, MCTL_MASTER_CFG0(0)); + writel(0x00500064, MCTL_MASTER_CFG1(0)); + writel(0x07000009, MCTL_MASTER_CFG0(1)); + writel(0x00000600, MCTL_MASTER_CFG1(1)); + writel(0x01000009, MCTL_MASTER_CFG0(3)); + writel(0x00000064, MCTL_MASTER_CFG1(3)); + writel(0x08000009, MCTL_MASTER_CFG0(4)); + writel(0x00000640, MCTL_MASTER_CFG1(4)); + writel(0x20000308, MCTL_MASTER_CFG0(8)); + writel(0x00001000, MCTL_MASTER_CFG1(8)); + writel(0x02800009, MCTL_MASTER_CFG0(9)); + writel(0x00000100, MCTL_MASTER_CFG1(9)); + writel(0x01800009, MCTL_MASTER_CFG0(5)); + writel(0x00000100, MCTL_MASTER_CFG1(5)); + writel(0x01800009, MCTL_MASTER_CFG0(7)); + writel(0x00000100, MCTL_MASTER_CFG1(7)); + writel(0x00640009, MCTL_MASTER_CFG0(6)); + writel(0x00000032, MCTL_MASTER_CFG1(6)); + writel(0x0100000d, MCTL_MASTER_CFG0(2)); + writel(0x00500080, MCTL_MASTER_CFG1(2)); +} + +static int mctl_channel_init(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + u32 low_data_lines_status; /* Training status of datalines 0 - 7 */ + u32 high_data_lines_status; /* Training status of datalines 8 - 15 */ + u32 i, rval; + + auto_set_timing_para(para); + + /* Set dram master access priority */ + writel(0x000101a0, &mctl_com->bwcr); + /* set cpu high priority */ + writel(0x1, &mctl_com->mapr); + set_master_priority(); + udelay(250); + + /* Disable dram VTC */ + clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30); + clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26); + + writel(0x94be6fa3, MCTL_PROTECT); + udelay(100); + clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16); + writel(0x0, MCTL_PROTECT); + udelay(100); + + + /* Set ODT */ + if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) + rval = 0x0; + else + rval = 0x2; + + for (i = 0 ; i < 11 ; i++) { + clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16), + rval << 24); + clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16), + rval << 24); + clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16), + rval << 24); + clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16), + rval << 24); + } + + for (i = 0; i < 31; i++) + clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26); + + /* set PLL configuration */ + if (CONFIG_DRAM_CLK >= 480) + setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19); + else + setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19); + + /* Auto detect dram config, set 2 rank and 16bit bus-width */ + para->cs1 = 0; + para->rank = 2; + para->bus_width = 16; + mctl_set_cr(para); + + /* Open DQS gating */ + clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); + clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7)); + + if (para->dram_type == DRAM_TYPE_LPDDR3) + clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) , + 0x1 << 31); + if (readl(&mctl_com->cr) & 0x1) + writel(0x00000303, &mctl_ctl->odtmap); + else + writel(0x00000201, &mctl_ctl->odtmap); + + mctl_data_train_cfg(para); + /* ZQ calibration */ + clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff); + clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff); + /* CA calibration */ + + if (para->dram_type == DRAM_TYPE_DDR3) + mctl_set_pir(0x0201f3 | 0x1<<10); + else + mctl_set_pir(0x020173 | 0x1<<10); + + /* DQS gate training */ + if (mctl_train_dram(para) != 0) { + low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03; + high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03; + + if (low_data_lines_status == 0x3) + return -EIO; + + /* DRAM has only one rank */ + para->rank = 1; + mctl_set_cr(para); + + if (low_data_lines_status == high_data_lines_status) + goto done; /* 16 bit bus, 1 rank */ + + if (!(low_data_lines_status & high_data_lines_status)) { + /* Retry 16 bit bus-width with CS1 set */ + para->cs1 = 1; + mctl_set_cr(para); + if (mctl_train_dram(para) == 0) + goto done; + } + + /* Try 8 bit bus-width */ + writel(0x0, DXnGCR0(1)); /* Disable high DQ */ + para->cs1 = 0; + para->bus_width = 8; + mctl_set_cr(para); + if (mctl_train_dram(para) != 0) + return -EIO; + } +done: + /* Check the dramc status */ + mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); + + /* Close DQS gating */ + setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6); + + /* set PGCR3,CKE polarity */ + writel(0x00aa0060, &mctl_ctl->pgcr3); + /* Enable master access */ + writel(0xffffffff, &mctl_com->maer); + + return 0; +} + +static void mctl_sys_init(struct dram_para *para) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); + clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); + udelay(1000); + clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31); + + clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL); + + clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, + CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) | + CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD); + mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); + + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); + + para->rank = 2; + para->bus_width = 16; + mctl_set_cr(para); + + /* Set dram master access priority */ + writel(0x0000e00f, &mctl_ctl->clken); /* normal */ + + udelay(250); +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + struct dram_para para = { + .cs1 = 0, + .bank = 1, + .rank = 1, + .rows = 15, + .bus_width = 16, + .page_size = 2048, + }; + +#if defined(CONFIG_MACH_SUN8I_A83T) +#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7) + para.dram_type = CONFIG_DRAM_TYPE; +#else +#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3) +#endif +#endif + setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8); + + writel(0, (SUNXI_PRCM_BASE + 0x1e8)); + udelay(10); + + mctl_sys_init(¶); + + if (mctl_channel_init(¶) != 0) + return 0; + + auto_detect_dram_size(¶); + + /* Enable master software clk */ + writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); + + /* Set DRAM ODT MAP */ + if (para.rank == 2) + writel(0x00000303, &mctl_ctl->odtmap); + else + writel(0x00000201, &mctl_ctl->odtmap); + + return para.page_size * (para.bus_width / 8) * + (1 << (para.bank + para.rank + para.rows)); +} diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c new file mode 100644 index 0000000..2020d75 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c @@ -0,0 +1,469 @@ +/* + * sun8i H3 platform dram controller init + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang + * (C) Copyright 2015 Vishnu Patekar + * (C) Copyright 2015 Hans de Goede + * (C) Copyright 2015 Jens Kuske + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +struct dram_para { + u32 read_delays; + u32 write_delays; + u16 page_size; + u8 bus_width; + u8 dual_rank; + u8 row_bits; +}; + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +static u32 bin_to_mgray(int val) +{ + static const u8 lookup_table[32] = { + 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, + 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, + 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d, + 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11, + }; + + return lookup_table[clamp(val, 0, 31)]; +} + +static int mgray_to_bin(u32 val) +{ + static const u8 lookup_table[32] = { + 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, + 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b, + 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b, + 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15, + }; + + return lookup_table[val & 0x1f]; +} + +static void mctl_phy_init(u32 val) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + writel(val | PIR_INIT, &mctl_ctl->pir); + mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1); +} + +static void mctl_dq_delay(u32 read, u32 write) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + int i, j; + u32 val; + + for (i = 0; i < 4; i++) { + val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) | + DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2); + + for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++) + writel(val, &mctl_ctl->datx[i].iocr[j]); + } + + clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); + + for (i = 0; i < 4; i++) { + val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) | + DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf); + + writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]); + writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]); + } + + setbits_le32(&mctl_ctl->pgcr[0], 1 << 26); + + udelay(1); +} + +static void mctl_set_master_priority(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + /* enable bandwidth limit windows and set windows size 1us */ + writel(0x00010190, &mctl_com->bwcr); + + /* set cpu high priority */ + writel(0x00000001, &mctl_com->mapr); + + writel(0x0200000d, &mctl_com->mcr[0][0]); + writel(0x00800100, &mctl_com->mcr[0][1]); + writel(0x06000009, &mctl_com->mcr[1][0]); + writel(0x01000400, &mctl_com->mcr[1][1]); + writel(0x0200000d, &mctl_com->mcr[2][0]); + writel(0x00600100, &mctl_com->mcr[2][1]); + writel(0x0100000d, &mctl_com->mcr[3][0]); + writel(0x00200080, &mctl_com->mcr[3][1]); + writel(0x07000009, &mctl_com->mcr[4][0]); + writel(0x01000640, &mctl_com->mcr[4][1]); + writel(0x0100000d, &mctl_com->mcr[5][0]); + writel(0x00200080, &mctl_com->mcr[5][1]); + writel(0x01000009, &mctl_com->mcr[6][0]); + writel(0x00400080, &mctl_com->mcr[6][1]); + writel(0x0100000d, &mctl_com->mcr[7][0]); + writel(0x00400080, &mctl_com->mcr[7][1]); + writel(0x0100000d, &mctl_com->mcr[8][0]); + writel(0x00400080, &mctl_com->mcr[8][1]); + writel(0x04000009, &mctl_com->mcr[9][0]); + writel(0x00400100, &mctl_com->mcr[9][1]); + writel(0x2000030d, &mctl_com->mcr[10][0]); + writel(0x04001800, &mctl_com->mcr[10][1]); + writel(0x04000009, &mctl_com->mcr[11][0]); + writel(0x00400120, &mctl_com->mcr[11][1]); +} + +static void mctl_set_timing_params(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 2; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 4); + u8 trcd = ns_to_t(15); + u8 trc = ns_to_t(53); + u8 txp = max(ns_to_t(8), 3); + u8 twtr = max(ns_to_t(8), 4); + u8 trtp = max(ns_to_t(8), 4); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(38); + u16 trefi = ns_to_t(7800) / 32; + u16 trfc = ns_to_t(350); + + u8 tmrw = 0; + u8 tmrd = 4; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 24; + + u8 tcl = 6; /* CL 12 */ + u8 tcwl = 4; /* CWL 8 */ + u8 t_rdata_en = 4; + u8 wr_latency = 2; + + u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ + u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* set mode register */ + writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ + writel(0x40, &mctl_ctl->mr[1]); + writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ + writel(0x0, &mctl_ctl->mr[3]); + + /* set DRAM timing */ + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), + &mctl_ctl->dramtmg[0]); + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), + &mctl_ctl->dramtmg[1]); + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), + &mctl_ctl->dramtmg[2]); + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), + &mctl_ctl->dramtmg[3]); + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), + &mctl_ctl->dramtmg[5]); + + /* set two rank timing */ + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), + (0x66 << 8) | (0x10 << 0)); + + /* set PHY interface timing, write latency and read latency configure */ + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | + (wr_latency << 0), &mctl_ctl->pitmg[0]); + + /* set PHY timing, PTR0-2 use default */ + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); + + /* set refresh timing */ + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); +} + +static void mctl_zq_calibration(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + int i; + u16 zq_val[6]; + u8 val; + + writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); + + for (i = 0; i < 6; i++) { + u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; + + writel((zq << 20) | (zq << 16) | (zq << 12) | + (zq << 8) | (zq << 4) | (zq << 0), + &mctl_ctl->zqcr); + + writel(PIR_CLRSR, &mctl_ctl->pir); + mctl_phy_init(PIR_ZCAL); + + zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; + writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); + + writel(PIR_CLRSR, &mctl_ctl->pir); + mctl_phy_init(PIR_ZCAL); + + val = readl(&mctl_ctl->zqdr[0]) >> 24; + zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; + } + + writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); + writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); + writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); +} + +static void mctl_set_cr(struct dram_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | + MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) | + (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | + MCTL_CR_PAGE_SIZE(para->page_size) | + MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); +} + +static void mctl_sys_init(struct dram_para *para) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); + clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); + udelay(10); + + clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); + udelay(1000); + + clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false); + clrsetbits_le32(&ccm->dram_clk_cfg, + CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK, + CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 | + CCM_DRAMCLK_CFG_UPD); + mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); + + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); + + setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); + udelay(10); + + writel(0xc00e, &mctl_ctl->clken); + udelay(500); +} + +static int mctl_channel_init(struct dram_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + unsigned int i; + + mctl_set_cr(para); + mctl_set_timing_params(para); + mctl_set_master_priority(); + + /* setting VTC, default disable all VT */ + clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); + clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); + + /* increase DFI_PHY_UPD clock */ + writel(PROTECT_MAGIC, &mctl_com->protect); + udelay(100); + clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16); + writel(0x0, &mctl_com->protect); + udelay(100); + + /* set dramc odt */ + for (i = 0; i < 4; i++) + clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) | + (0x1 << 1) | (0x3 << 2) | (0x3 << 12) | + (0x3 << 14), + IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2); + + /* AC PDR should always ON */ + setbits_le32(&mctl_ctl->aciocr, 0x1 << 1); + + /* set DQS auto gating PD mode */ + setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6); + + /* dx ddr_clk & hdr_clk dynamic mode */ + clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); + + /* dphy & aphy phase select 270 degree */ + clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), + (0x1 << 10) | (0x2 << 8)); + + /* set half DQ */ + if (para->bus_width != 32) { + writel(0x0, &mctl_ctl->datx[2].gcr); + writel(0x0, &mctl_ctl->datx[3].gcr); + } + + /* data training configuration */ + clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, + (para->dual_rank ? 0x3 : 0x1) << 24); + + + if (para->read_delays || para->write_delays) { + mctl_dq_delay(para->read_delays, para->write_delays); + udelay(50); + } + + mctl_zq_calibration(para); + + mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST | + PIR_DRAMINIT | PIR_QSGATE); + + /* detect ranks and bus width */ + if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { + /* only one rank */ + if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) || + ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) { + clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); + para->dual_rank = 0; + } + + /* only half DQ width */ + if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) || + ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) { + writel(0x0, &mctl_ctl->datx[2].gcr); + writel(0x0, &mctl_ctl->datx[3].gcr); + para->bus_width = 16; + } + + mctl_set_cr(para); + udelay(20); + + /* re-train */ + mctl_phy_init(PIR_QSGATE); + if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) + return 1; + } + + /* check the dramc status */ + mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); + + /* liuke added for refresh debug */ + setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); + udelay(10); + clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); + udelay(10); + + /* set PGCR3, CKE polarity */ + writel(0x00aa0060, &mctl_ctl->pgcr[3]); + + /* power down zq calibration module for power save */ + setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN); + + /* enable master access */ + writel(0xffffffff, &mctl_com->maer); + + return 0; +} + +static void mctl_auto_detect_dram_size(struct dram_para *para) +{ + /* detect row address bits */ + para->page_size = 512; + para->row_bits = 16; + mctl_set_cr(para); + + for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) + if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size)) + break; + + /* detect page size */ + para->page_size = 8192; + mctl_set_cr(para); + + for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2) + if (mctl_mem_matches(para->page_size)) + break; +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + struct dram_para para = { + .read_delays = 0x00007979, /* dram_tpr12 */ + .write_delays = 0x6aaa0000, /* dram_tpr11 */ + .dual_rank = 0, + .bus_width = 32, + .row_bits = 15, + .page_size = 4096, + }; + + mctl_sys_init(¶); + if (mctl_channel_init(¶)) + return 0; + + if (para.dual_rank) + writel(0x00000303, &mctl_ctl->odtmap); + else + writel(0x00000201, &mctl_ctl->odtmap); + udelay(1); + + /* odt delay */ + writel(0x0c000400, &mctl_ctl->odtcfg); + + /* clear credit value */ + setbits_le32(&mctl_com->cccr, 1 << 31); + udelay(10); + + mctl_auto_detect_dram_size(¶); + mctl_set_cr(¶); + + return (1 << (para.row_bits + 3)) * para.page_size * + (para.dual_rank ? 2 : 1); +} diff --git a/arch/arm/mach-sunxi/p2wi.c b/arch/arm/mach-sunxi/p2wi.c new file mode 100644 index 0000000..26a9cfc --- /dev/null +++ b/arch/arm/mach-sunxi/p2wi.c @@ -0,0 +1,117 @@ +/* + * Sunxi A31 Power Management Unit + * + * (C) Copyright 2013 Oliver Schinagl + * http://linux-sunxi.org + * + * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work + * + * (C) Copyright 2006-2013 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void p2wi_init(void) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + + /* Enable p2wi and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); + + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); + + /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ + writel(P2WI_CTRL_RESET, &p2wi->ctrl); + sdelay(0x100); + writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8), + &p2wi->cc); +} + +int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + unsigned long tmo = timer_get_us() + 1000000; + + writel(P2WI_PM_DEV_ADDR(slave_addr) | + P2WI_PM_CTRL_ADDR(ctrl_reg) | + P2WI_PM_INIT_DATA(init_data) | + P2WI_PM_INIT_SEND, + &p2wi->pm); + + while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) { + if (timer_get_us() > tmo) + return -ETIME; + } + + return 0; +} + +static int p2wi_await_trans(void) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + unsigned long tmo = timer_get_us() + 1000000; + int ret; + u8 reg; + + while (1) { + reg = readl(&p2wi->status); + if (reg & P2WI_STAT_TRANS_ERR) { + ret = -EIO; + break; + } + if (reg & P2WI_STAT_TRANS_DONE) { + ret = 0; + break; + } + if (timer_get_us() > tmo) { + ret = -ETIME; + break; + } + } + writel(reg, &p2wi->status); /* Clear status bits */ + return ret; +} + +int p2wi_read(const u8 addr, u8 *data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + int ret; + + writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); + writel(P2WI_DATA_NUM_BYTES(1) | + P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes); + writel(P2WI_STAT_TRANS_DONE, &p2wi->status); + writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); + + ret = p2wi_await_trans(); + + *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK; + return ret; +} + +int p2wi_write(const u8 addr, u8 data) +{ + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + + writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); + writel(P2WI_DATA_BYTE_1(data), &p2wi->data0); + writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes); + writel(P2WI_STAT_TRANS_DONE, &p2wi->status); + writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); + + return p2wi_await_trans(); +} diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c new file mode 100644 index 0000000..b026f78 --- /dev/null +++ b/arch/arm/mach-sunxi/pinmux.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) +{ + u32 index = GPIO_CFG_INDEX(bank_offset); + u32 offset = GPIO_CFG_OFFSET(bank_offset); + + clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset); +} + +void sunxi_gpio_set_cfgpin(u32 pin, u32 val) +{ + u32 bank = GPIO_BANK(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + sunxi_gpio_set_cfgbank(pio, pin, val); +} + +int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) +{ + u32 index = GPIO_CFG_INDEX(bank_offset); + u32 offset = GPIO_CFG_OFFSET(bank_offset); + u32 cfg; + + cfg = readl(&pio->cfg[0] + index); + cfg >>= offset; + + return cfg & 0xf; +} + +int sunxi_gpio_get_cfgpin(u32 pin) +{ + u32 bank = GPIO_BANK(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + return sunxi_gpio_get_cfgbank(pio, pin); +} + +int sunxi_gpio_set_drv(u32 pin, u32 val) +{ + u32 bank = GPIO_BANK(pin); + u32 index = GPIO_DRV_INDEX(pin); + u32 offset = GPIO_DRV_OFFSET(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); + + return 0; +} + +int sunxi_gpio_set_pull(u32 pin, u32 val) +{ + u32 bank = GPIO_BANK(pin); + u32 index = GPIO_PULL_INDEX(pin); + u32 offset = GPIO_PULL_OFFSET(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); + + return 0; +} diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c new file mode 100644 index 0000000..5b81a8d --- /dev/null +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2015 Hans de Goede + * + * Sunxi PMIC bus access helpers + * + * The axp152 & axp209 use an i2c bus, the axp221 uses the p2wi bus and the + * axp223 uses the rsb bus, these functions abstract this. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define AXP152_I2C_ADDR 0x30 + +#define AXP209_I2C_ADDR 0x34 + +#define AXP221_CHIP_ADDR 0x68 +#define AXP221_CTRL_ADDR 0x3e +#define AXP221_INIT_DATA 0x3e + +/* AXP818 device and runtime addresses are same as AXP223 */ +#define AXP223_DEVICE_ADDR 0x3a3 +#define AXP223_RUNTIME_ADDR 0x2d + +int pmic_bus_init(void) +{ + /* This cannot be 0 because it is used in SPL before BSS is ready */ + static int needs_init = 1; + __maybe_unused int ret; + + if (!needs_init) + return 0; + +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +# ifdef CONFIG_MACH_SUN6I + p2wi_init(); + ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, + AXP221_INIT_DATA); +# else + ret = rsb_init(); + if (ret) + return ret; + + ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR); +# endif + if (ret) + return ret; +#endif + + needs_init = 0; + return 0; +} + +int pmic_bus_read(u8 reg, u8 *data) +{ +#ifdef CONFIG_AXP152_POWER + return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); +#elif defined CONFIG_AXP209_POWER + return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +# ifdef CONFIG_MACH_SUN6I + return p2wi_read(reg, data); +# else + return rsb_read(AXP223_RUNTIME_ADDR, reg, data); +# endif +#endif +} + +int pmic_bus_write(u8 reg, u8 data) +{ +#ifdef CONFIG_AXP152_POWER + return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); +#elif defined CONFIG_AXP209_POWER + return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +# ifdef CONFIG_MACH_SUN6I + return p2wi_write(reg, data); +# else + return rsb_write(AXP223_RUNTIME_ADDR, reg, data); +# endif +#endif +} + +int pmic_bus_setbits(u8 reg, u8 bits) +{ + int ret; + u8 val; + + ret = pmic_bus_read(reg, &val); + if (ret) + return ret; + + val |= bits; + return pmic_bus_write(reg, val); +} + +int pmic_bus_clrbits(u8 reg, u8 bits) +{ + int ret; + u8 val; + + ret = pmic_bus_read(reg, &val); + if (ret) + return ret; + + val &= ~bits; + return pmic_bus_write(reg, val); +} diff --git a/arch/arm/mach-sunxi/prcm.c b/arch/arm/mach-sunxi/prcm.c new file mode 100644 index 0000000..e1d091f --- /dev/null +++ b/arch/arm/mach-sunxi/prcm.c @@ -0,0 +1,47 @@ +/* + * Sunxi A31 Power Management Unit + * + * (C) Copyright 2013 Oliver Schinagl + * http://linux-sunxi.org + * + * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work + * + * (C) Copyright 2006-2013 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* APB0 clock gate and reset bit offsets are the same. */ +void prcm_apb0_enable(u32 flags) +{ + struct sunxi_prcm_reg *prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* open the clock for module */ + setbits_le32(&prcm->apb0_gate, flags); + + /* deassert reset for module */ + setbits_le32(&prcm->apb0_reset, flags); +} + +void prcm_apb0_disable(u32 flags) +{ + struct sunxi_prcm_reg *prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* assert reset for module */ + clrbits_le32(&prcm->apb0_reset, flags); + + /* close the clock for module */ + clrbits_le32(&prcm->apb0_gate, flags); +} diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c new file mode 100644 index 0000000..6fd11f1 --- /dev/null +++ b/arch/arm/mach-sunxi/rsb.c @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2014 Hans de Goede + * + * Based on allwinner u-boot sources rsb code which is: + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. + * lixiang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static int rsb_set_device_mode(void); + +static void rsb_cfg_io(void) +{ +#ifdef CONFIG_MACH_SUN8I + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); + sunxi_gpio_set_pull(SUNXI_GPL(0), 1); + sunxi_gpio_set_pull(SUNXI_GPL(1), 1); + sunxi_gpio_set_drv(SUNXI_GPL(0), 2); + sunxi_gpio_set_drv(SUNXI_GPL(1), 2); +#elif defined CONFIG_MACH_SUN9I + sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB); + sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB); + sunxi_gpio_set_pull(SUNXI_GPN(0), 1); + sunxi_gpio_set_pull(SUNXI_GPN(1), 1); + sunxi_gpio_set_drv(SUNXI_GPN(0), 2); + sunxi_gpio_set_drv(SUNXI_GPN(1), 2); +#else +#error unsupported MACH_SUNXI +#endif +} + +static void rsb_set_clk(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + u32 div = 0; + u32 cd_odly = 0; + + /* Source is Hosc24M, set RSB clk to 3Mhz */ + div = 24000000 / 3000000 / 2 - 1; + cd_odly = div >> 1; + if (!cd_odly) + cd_odly = 1; + + writel((cd_odly << 8) | div, &rsb->ccr); +} + +int rsb_init(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + /* Enable RSB and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); + + /* Setup external pins */ + rsb_cfg_io(); + + writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); + rsb_set_clk(); + + return rsb_set_device_mode(); +} + +static int rsb_await_trans(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + unsigned long tmo = timer_get_us() + 1000000; + u32 stat; + int ret; + + while (1) { + stat = readl(&rsb->stat); + if (stat & RSB_STAT_LBSY_INT) { + ret = -EBUSY; + break; + } + if (stat & RSB_STAT_TERR_INT) { + ret = -EIO; + break; + } + if (stat & RSB_STAT_TOVER_INT) { + ret = 0; + break; + } + if (timer_get_us() > tmo) { + ret = -ETIME; + break; + } + } + writel(stat, &rsb->stat); /* Clear status bits */ + + return ret; +} + +static int rsb_set_device_mode(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + unsigned long tmo = timer_get_us() + 1000000; + + writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA, + &rsb->dmcr); + + while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) { + if (timer_get_us() > tmo) + return -ETIME; + } + + return rsb_await_trans(); +} + +static int rsb_do_trans(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS); + return rsb_await_trans(); +} + +int rsb_set_device_address(u16 device_addr, u16 runtime_addr) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) | + RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr); + writel(RSB_CMD_SET_RTSADDR, &rsb->cmd); + + return rsb_do_trans(); +} + +int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); + writel(reg_addr, &rsb->addr); + writel(data, &rsb->data); + writel(RSB_CMD_BYTE_WRITE, &rsb->cmd); + + return rsb_do_trans(); +} + +int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + int ret; + + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); + writel(reg_addr, &rsb->addr); + writel(RSB_CMD_BYTE_READ, &rsb->cmd); + + ret = rsb_do_trans(); + if (ret) + return ret; + + *data = readl(&rsb->data) & 0xff; + + return 0; +} diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c new file mode 100644 index 0000000..fa375f1 --- /dev/null +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -0,0 +1,400 @@ +/* + * Sunxi usb-phy code + * + * Copyright (C) 2015 Hans de Goede + * Copyright (C) 2014 Roman Byshko + * + * Based on code from + * Allwinner Technology Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SUNXI_USB_PMU_IRQ_ENABLE 0x800 +#ifdef CONFIG_MACH_SUN8I_A33 +#define SUNXI_USB_CSR 0x410 +#else +#define SUNXI_USB_CSR 0x404 +#endif +#define SUNXI_USB_PASSBY_EN 1 + +#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) +#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9) +#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8) +#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0) + +#define REG_PHY_UNK_H3 0x420 +#define REG_PMU_UNK_H3 0x810 + +/* A83T specific control bits for PHY0 */ +#define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5) +#define SUNXI_PHY_CTL_SIDDQ BIT(3) + +/* A83T HSIC specific bits */ +#define SUNXI_EHCI_HS_FORCE BIT(20) +#define SUNXI_EHCI_CONNECT_DET BIT(17) +#define SUNXI_EHCI_CONNECT_INT BIT(16) +#define SUNXI_EHCI_HSIC BIT(1) + +static struct sunxi_usb_phy { + int usb_rst_mask; + int gpio_vbus; + int gpio_vbus_det; + int gpio_id_det; + int id; + int init_count; + int power_on_count; + int base; +} sunxi_usb_phy[] = { + { + .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK, + .id = 0, + .base = SUNXI_USB0_BASE, + }, + { + .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK, + .id = 1, + .base = SUNXI_USB1_BASE, + }, +#if CONFIG_SUNXI_USB_PHYS >= 3 + { +#ifdef CONFIG_MACH_SUN8I_A83T + .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK | + CCM_USB_CTRL_12M_CLK, +#else + .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, +#endif + .id = 2, + .base = SUNXI_USB2_BASE, + }, +#endif +#if CONFIG_SUNXI_USB_PHYS >= 4 + { + .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK, + .id = 3, + .base = SUNXI_USB3_BASE, + } +#endif +}; + +static int get_vbus_gpio(int index) +{ + switch (index) { + case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN); + case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN); + case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN); + case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN); + } + return -EINVAL; +} + +static int get_vbus_detect_gpio(int index) +{ + switch (index) { + case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET); + } + return -EINVAL; +} + +static int get_id_detect_gpio(int index) +{ + switch (index) { + case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET); + } + return -EINVAL; +} + +__maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, + int data, int len) +{ + int j = 0, usbc_bit = 0; + void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR; + +#ifdef CONFIG_MACH_SUN8I_A33 + /* CSR needs to be explicitly initialized to 0 on A33 */ + writel(0, dest); +#endif + + usbc_bit = 1 << (phy->id * 2); + for (j = 0; j < len; j++) { + /* set the bit address to be written */ + clrbits_le32(dest, 0xff << 8); + setbits_le32(dest, (addr + j) << 8); + + clrbits_le32(dest, usbc_bit); + /* set data bit */ + if (data & 0x1) + setbits_le32(dest, 1 << 7); + else + clrbits_le32(dest, 1 << 7); + + setbits_le32(dest, usbc_bit); + + clrbits_le32(dest, usbc_bit); + + data >>= 1; + } +} + +#if defined CONFIG_MACH_SUN8I_H3 +static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) +{ + if (phy->id == 0) + clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); + + clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); +} +#elif defined CONFIG_MACH_SUN8I_A83T +static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) +{ +} +#else +static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) +{ + /* The following comments are machine + * translated from Chinese, you have been warned! + */ + + /* Regulation 45 ohms */ + if (phy->id == 0) + usb_phy_write(phy, 0x0c, 0x01, 1); + + /* adjust PHY's magnitude and rate */ + usb_phy_write(phy, 0x20, 0x14, 5); + + /* threshold adjustment disconnect */ +#if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I + usb_phy_write(phy, 0x2a, 2, 2); +#else + usb_phy_write(phy, 0x2a, 3, 2); +#endif + + return; +} +#endif + +static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable) +{ + unsigned long bits = 0; + void *addr; + + addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE; + + bits = SUNXI_EHCI_AHB_ICHR8_EN | + SUNXI_EHCI_AHB_INCR4_BURST_EN | + SUNXI_EHCI_AHB_INCRX_ALIGN_EN | + SUNXI_EHCI_ULPI_BYPASS_EN; + +#ifdef CONFIG_MACH_SUN8I_A83T + if (phy->id == 2) + bits |= SUNXI_EHCI_HS_FORCE | + SUNXI_EHCI_CONNECT_INT | + SUNXI_EHCI_HSIC; +#endif + + if (enable) + setbits_le32(addr, bits); + else + clrbits_le32(addr, bits); + + return; +} + +void sunxi_usb_phy_enable_squelch_detect(int index, int enable) +{ +#ifndef CONFIG_MACH_SUN8I_A83T + struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; + + usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2); +#endif +} + +void sunxi_usb_phy_init(int index) +{ + struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + phy->init_count++; + if (phy->init_count != 1) + return; + + setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); + + sunxi_usb_phy_config(phy); + + if (phy->id != 0) + sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN); + +#ifdef CONFIG_MACH_SUN8I_A83T + if (phy->id == 0) { + setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, + SUNXI_PHY_CTL_VBUSVLDEXT); + clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, + SUNXI_PHY_CTL_SIDDQ); + } +#endif +} + +void sunxi_usb_phy_exit(int index) +{ + struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + phy->init_count--; + if (phy->init_count != 0) + return; + + if (phy->id != 0) + sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN); + +#ifdef CONFIG_MACH_SUN8I_A83T + if (phy->id == 0) { + setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR, + SUNXI_PHY_CTL_SIDDQ); + } +#endif + + clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); +} + +void sunxi_usb_phy_power_on(int index) +{ + struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; + + phy->power_on_count++; + if (phy->power_on_count != 1) + return; + + if (phy->gpio_vbus >= 0) + gpio_set_value(phy->gpio_vbus, 1); +} + +void sunxi_usb_phy_power_off(int index) +{ + struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; + + phy->power_on_count--; + if (phy->power_on_count != 0) + return; + + if (phy->gpio_vbus >= 0) + gpio_set_value(phy->gpio_vbus, 0); +} + +int sunxi_usb_phy_power_is_on(int index) +{ + struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; + + return phy->power_on_count > 0; +} + +int sunxi_usb_phy_vbus_detect(int index) +{ + struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; + int err, retries = 3; + + if (phy->gpio_vbus_det < 0) + return phy->gpio_vbus_det; + + err = gpio_get_value(phy->gpio_vbus_det); + /* + * Vbus may have been provided by the board and just been turned of + * some milliseconds ago on reset, what we're measuring then is a + * residual charge on Vbus, sleep a bit and try again. + */ + while (err > 0 && retries--) { + mdelay(100); + err = gpio_get_value(phy->gpio_vbus_det); + } + + return err; +} + +int sunxi_usb_phy_id_detect(int index) +{ + struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; + + if (phy->gpio_id_det < 0) + return phy->gpio_id_det; + + return gpio_get_value(phy->gpio_id_det); +} + +int sunxi_usb_phy_probe(void) +{ + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_usb_phy *phy; + int i, ret = 0; + + for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { + phy = &sunxi_usb_phy[i]; + + phy->gpio_vbus = get_vbus_gpio(i); + if (phy->gpio_vbus >= 0) { + ret = gpio_request(phy->gpio_vbus, "usb_vbus"); + if (ret) + return ret; + ret = gpio_direction_output(phy->gpio_vbus, 0); + if (ret) + return ret; + } + + phy->gpio_vbus_det = get_vbus_detect_gpio(i); + if (phy->gpio_vbus_det >= 0) { + ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det"); + if (ret) + return ret; + ret = gpio_direction_input(phy->gpio_vbus_det); + if (ret) + return ret; + } + + phy->gpio_id_det = get_id_detect_gpio(i); + if (phy->gpio_id_det >= 0) { + ret = gpio_request(phy->gpio_id_det, "usb_id_det"); + if (ret) + return ret; + ret = gpio_direction_input(phy->gpio_id_det); + if (ret) + return ret; + sunxi_gpio_set_pull(phy->gpio_id_det, + SUNXI_GPIO_PULL_UP); + } + } + + setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); + + return 0; +} + +int sunxi_usb_phy_remove(void) +{ + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_usb_phy *phy; + int i; + + clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); + + for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { + phy = &sunxi_usb_phy[i]; + + if (phy->gpio_vbus >= 0) + gpio_free(phy->gpio_vbus); + + if (phy->gpio_vbus_det >= 0) + gpio_free(phy->gpio_vbus_det); + + if (phy->gpio_id_det >= 0) + gpio_free(phy->gpio_id_det); + } + + return 0; +} -- cgit v0.10.2 From 8434f0357624ad7345450d8c765264637dfd7cd1 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Tue, 29 Mar 2016 17:29:07 +0200 Subject: sunxi: Depend SPL configs on SUPPORT_SPL We currently depend SPL config options on specific machine types which doesn't scale. Fortunately there's already a kconfig variable that tells us whether we want to build SPL code at all, so just depend them on this. Signed-off-by: Alexander Graf Acked-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9851065..b82ec18 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -538,8 +538,8 @@ config ARCH_SUNXI select OF_BOARD_SETUP select OF_CONTROL select OF_SEPARATE - select SPL_STACK_R if !MACH_SUN9I - select SPL_SYS_MALLOC_SIMPLE if !MACH_SUN9I + select SPL_STACK_R if SUPPORT_SPL + select SPL_SYS_MALLOC_SIMPLE if SUPPORT_SPL select SYS_NS16550 select USB select USB_STORAGE -- cgit v0.10.2 From 0ea5a04fbcd72ebb37eb4b3f744374fdf551d3b7 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Tue, 29 Mar 2016 17:29:09 +0200 Subject: sunxi: Explicitly cast u32 pointer conversions Some parts of the sunxi code cast explicitly between u32 values and pointers. This is not a problem in practice, because all 64bit SoCs today only use the lower 32 bits for their phyical address space. But we need to make sure that the compiler is sure this is not an accident as well. Signed-off-by: Alexander Graf Acked-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index c0eabdf..b885ea1 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -105,7 +105,7 @@ int sunxi_get_sid(unsigned int *sid) int i; for (i = 0; i< 4; i++) - sid[i] = readl(SUNXI_SID_BASE + 4 * i); + sid[i] = readl((ulong)SUNXI_SID_BASE + 4 * i); return 0; #else diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 9a94e1b..50318d2 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -30,8 +30,8 @@ bool mctl_mem_matches(u32 offset) { /* Try to write different values to RAM at two addresses */ writel(0, CONFIG_SYS_SDRAM_BASE); - writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset); + writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); /* Check if the same value is actually observed when reading back */ return readl(CONFIG_SYS_SDRAM_BASE) == - readl(CONFIG_SYS_SDRAM_BASE + offset); + readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); } diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index fa375f1..b258ce4 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -52,7 +52,7 @@ static struct sunxi_usb_phy { int id; int init_count; int power_on_count; - int base; + ulong base; } sunxi_usb_phy[] = { { .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK, diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 7b33094..44d1a76 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -339,7 +339,7 @@ static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; if (data) { - if ((u32) data->dest & 0x3) { + if ((u32)(long)data->dest & 0x3) { error = -1; goto out; } -- cgit v0.10.2 From d96ebc468d0dff6eb6f069bba03b3f0e33aa22de Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Tue, 29 Mar 2016 17:29:10 +0200 Subject: sunxi: Add support for Allwinner A64 SoCs The Allwinner A64 SoC is used in the Pine64. This patch adds all bits necessary to compile U-Boot for it running in AArch64 mode. Unfortunately SPL is not ready yet due to legal problems, so we need to boot using the binary boot0 for now. Signed-off-by: Siarhei Siamashka [agraf: remove SPL code, move to AArch64] Signed-off-by: Alexander Graf Acked-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/arch/arm/dts/a64.dtsi b/arch/arm/dts/a64.dtsi new file mode 100644 index 0000000..f3ad000 --- /dev/null +++ b/arch/arm/dts/a64.dtsi @@ -0,0 +1,564 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * based on the Allwinner H3 dtsi: + * Copyright (C) 2015 Jens Kuske + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +/ { + compatible = "allwinner,a64"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6", "pll6x2"; + }; + + pll6d2: pll6d2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll6 0>; + clock-output-names = "pll6d2"; + }; + + /* dummy clock until pll6 can be reused */ + pll8: pll8_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1>; + clock-output-names = "pll8"; + }; + + cpu: cpu_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20050 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; + }; + + axi: axi_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb1: ahb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clock-output-names = "ahb1"; + }; + + ahb2: ahb2_clk@01c2005c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ahb2-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&ahb1>, <&pll6d2>; + clock-output-names = "ahb2"; + }; + + apb1: apb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + clock-output-names = "apb1"; + }; + + apb2: apb2_clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>; + clock-output-names = "apb2"; + }; + + bus_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,a64-bus-gates-clk", + "allwinner,sun8i-h3-bus-gates-clk"; + reg = <0x01c20060 0x14>; + clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; + clock-names = "ahb1", "ahb2", "apb1", "apb2"; + clock-indices = <1>, + <5>, <6>, <8>, + <9>, <10>, <13>, + <14>, <17>, <18>, + <19>, <20>, + <21>, <23>, + <24>, <25>, + <28>, <29>, + <32>, <35>, + <36>, <37>, + <40>, <43>, + <44>, <52>, <53>, + <54>, <64>, + <65>, <69>, <72>, + <76>, <77>, <78>, + <96>, <97>, <98>, + <101>, + <112>, <113>, + <114>, <115>, + <116>, <135>; + clock-output-names = "bus_mipidsi", + "bus_ce", "bus_dma", "bus_mmc0", + "bus_mmc1", "bus_mmc2", "bus_nand", + "bus_sdram", "bus_gmac", "bus_ts", + "bus_hstimer", "bus_spi0", + "bus_spi1", "bus_otg", + "bus_otg_ehci0", "bus_ehci0", + "bus_otg_ohci0", "bus_ohci0", + "bus_ve", "bus_lcd0", + "bus_lcd1", "bus_deint", + "bus_csi", "bus_hdmi", + "bus_de", "bus_gpu", "bus_msgbox", + "bus_spinlock", "bus_codec", + "bus_spdif", "bus_pio", "bus_ths", + "bus_i2s0", "bus_i2s1", "bus_i2s2", + "bus_i2c0", "bus_i2c1", "bus_i2c2", + "bus_scr", + "bus_uart0", "bus_uart1", + "bus_uart2", "bus_uart3", + "bus_uart4", "bus_dbg"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + }; + + regulators { + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&bus_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb_rst 8>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&bus_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb_rst 9>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&bus_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ahb_rst 10>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,a64-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = , + , + ; + clocks = <&bus_gates 69>; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <2>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PB8", "PB9"; + allwinner,function = "uart0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart0_pins_b: uart0@1 { + allwinner,pins = "PF2", "PF3"; + allwinner,function = "uart0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart1_pins: uart1@0 { + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; + allwinner,function = "uart1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart2_pins: uart2@0 { + allwinner,pins = "PB0", "PB1", "PB2", "PB3"; + allwinner,function = "uart2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart3_pins_a: uart3@0 { + allwinner,pins = "PD0", "PD1"; + allwinner,function = "uart3"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart3_pins_b: uart3@1 { + allwinner,pins = "PH4", "PH5", "PH6", "PH7"; + allwinner,function = "uart3"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart4_pins: uart4@0 { + allwinner,pins = "PD2", "PD3", "PD4", "PD5"; + allwinner,function = "uart4"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_pins: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_default_cd_pin: mmc0_cd_pin@0 { + allwinner,pins = "PF6"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc1_pins: mmc1@0 { + allwinner,pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc2_pins: mmc2@0 { + allwinner,pins = "PC1", "PC5", "PC6", "PC8", + "PC9", "PC10"; + allwinner,function = "mmc2"; + allwinner,drive = ; + allwinner,pull = ; + }; + }; + + ahb_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-ahb1-reset"; + reg = <0x01c202c0 0xc>; + }; + + apb1_rst: reset@01c202d0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d0 0x4>; + }; + + apb2_rst: reset@01c202d8 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d8 0x4>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 112>; + resets = <&apb2_rst 16>; + reset-names = "apb2"; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 113>; + resets = <&apb2_rst 17>; + reset-names = "apb2"; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 114>; + resets = <&apb2_rst 18>; + reset-names = "apb2"; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 115>; + resets = <&apb2_rst 19>; + reset-names = "apb2"; + status = "disabled"; + }; + + uart4: serial@01c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 116>; + resets = <&apb2_rst 20>; + reset-names = "apb2"; + status = "disabled"; + }; + + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = , + ; + }; + }; + + gic: interrupt-controller@{ + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x01C81000 0x1000>, + <0x01C82000 0x2000>, + <0x01C84000 0x2000>, + <0x01C86000 0x2000>; + interrupts = ; + }; +}; diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 6c0573f..3747f74 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -17,7 +17,8 @@ /* clock control module regs definition */ #if defined(CONFIG_MACH_SUN8I_A83T) #include -#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) +#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ + defined(CONFIG_MACH_SUN50I) #include #elif defined(CONFIG_MACH_SUN9I) #include diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 9de7754..f2990db 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -350,10 +350,12 @@ struct sunxi_ccm_reg { #define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30) #define CCM_HDMI_CTRL_GATE (0x1 << 31) -#ifndef CONFIG_MACH_SUN8I -#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ -#else +#if defined(CONFIG_MACH_SUN50I) +#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */ +#elif defined(CONFIG_MACH_SUN8I) #define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */ +#else +#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ #endif #define MBUS_CLK_GATE (0x1 << 31) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 649f6cd..1ace548 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -159,6 +159,7 @@ enum sunxi_gpio_number { #define SUN8I_GPB_UART2 2 #define SUN8I_A33_GPB_UART0 3 #define SUN8I_A83T_GPB_UART0 2 +#define SUN50I_GPB_UART0 4 #define SUNXI_GPC_NAND 2 #define SUNXI_GPC_SDC2 3 diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index a129dd4..ca9a4f9 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -12,8 +12,11 @@ #define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ #define SPL_HEADER_VERSION 1 -/* Note: A80 will require special handling here: SPL_ADDR 0x10000 */ +#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) +#define SPL_ADDR 0x10000 +#else #define SPL_ADDR 0x0 +#endif /* boot head definition from sun4i boot code */ struct boot_file_head { diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 114cc03..ad3d6c4 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN50I) += clock_sun6i.o ifdef CONFIG_MACH_SUN8I_A83T obj-y += clock_sun8i_a83t.o else diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index bf58fa9..20149da 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -40,6 +40,30 @@ struct fel_stash { struct fel_stash fel_stash __attribute__((section(".data"))); +#ifdef CONFIG_MACH_SUN50I +#include + +static struct mm_region sunxi_mem_map[] = { + { + /* SRAM, MMIO regions */ + .base = 0x0UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, { + /* RAM */ + .base = 0x40000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; +struct mm_region *mem_map = sunxi_mem_map; +#endif + static int gpio_init(void) { #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) @@ -76,6 +100,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); @@ -265,7 +293,7 @@ void reset_cpu(ulong addr) #endif } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index b885ea1..76b6719 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -89,6 +89,8 @@ int print_cpuinfo(void) printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN9I puts("CPU: Allwinner A80 (SUN9I)\n"); +#elif defined CONFIG_MACH_SUN50I + puts("CPU: Allwinner A64 (SUN50I)\n"); #else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 5e72fac..464fa0f 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -77,6 +77,11 @@ config MACH_SUN8I_H3 select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT +config MACH_SUN50I + bool "sun50i (Allwinner A64)" + select ARM64 + select SUNXI_GEN_SUN6I + config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" select CPU_V7 @@ -213,6 +218,7 @@ config DRAM_ODT_CORRECTION endif config SYS_CLK_FREQ + default 816000000 if MACH_SUN50I default 912000000 if MACH_SUN7I default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I @@ -223,6 +229,7 @@ config SYS_CONFIG_NAME default "sun7i" if MACH_SUN7I default "sun8i" if MACH_SUN8I default "sun9i" if MACH_SUN9I + default "sun50i" if MACH_SUN50I config SYS_BOARD default "sunxi" @@ -604,7 +611,7 @@ config GMAC_TX_DELAY Set the GMAC Transmit Clock Delay Chain value. config SPL_STACK_R_ADDR - default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I + default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I default 0x2fe00000 if MACH_SUN9I endif diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 2271c89..ccf4129 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -21,6 +21,9 @@ #include #include #include +#ifndef CONFIG_ARM64 +#include +#endif #include #include #include @@ -73,18 +76,38 @@ DECLARE_GLOBAL_DATA_PTR; /* add board specific code here */ int board_init(void) { - int id_pfr1, ret; + __maybe_unused int id_pfr1, ret; gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); +#ifndef CONFIG_ARM64 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); debug("id_pfr1: 0x%08x\n", id_pfr1); /* Generic Timer Extension available? */ - if ((id_pfr1 >> 16) & 0xf) { + if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { + uint32_t freq; + debug("Setting CNTFRQ\n"); - /* CNTFRQ == 24 MHz */ - asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); + + /* + * CNTFRQ is a secure register, so we will crash if we try to + * write this from the non-secure world (read is OK, though). + * In case some bootcode has already set the correct value, + * we avoid the risk of writing to it. + */ + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); + if (freq != CONFIG_TIMER_CLK_FREQ) { + debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", + freq, CONFIG_TIMER_CLK_FREQ); +#ifdef CONFIG_NON_SECURE + printf("arch timer frequency is wrong, but cannot adjust it\n"); +#else + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(CONFIG_TIMER_CLK_FREQ)); +#endif + } } +#endif /* !CONFIG_ARM64 */ ret = axp_gpio_init(); if (ret) @@ -264,7 +287,7 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(SUNXI_GPC(24), 2); } -#elif defined(CONFIG_MACH_SUN8I) +#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) /* SDC2: PC5-PC6, PC8-PC16 */ for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); @@ -547,7 +570,7 @@ void get_board_serial(struct tag_serialnr *serialnr) */ static void parse_spl_header(const uint32_t spl_addr) { - struct boot_file_head *spl = (void *)spl_addr; + struct boot_file_head *spl = (void *)(ulong)spl_addr; if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) { uint8_t spl_header_version = spl->spl_signature[3]; if (spl_header_version == SPL_HEADER_VERSION) { diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 44d1a76..ce2dc4a 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -480,6 +480,10 @@ struct mmc *sunxi_mmc_init(int sdc_no) cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; cfg->host_caps = MMC_MODE_4BIT; +#ifdef CONFIG_MACH_SUN50I + if (sdc_no == 2) + cfg->host_caps = MMC_MODE_8BIT; +#endif cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 937b9aa..3c41bca 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -10,7 +10,7 @@ choice default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 default AXP818_POWER if MACH_SUN8I_A83T - default SUNXI_NO_PMIC if MACH_SUN8I_H3 + default SUNXI_NO_PMIC if MACH_SUN8I_H3 || MACH_SUN50I config SUNXI_NO_PMIC boolean "board without a pmic" diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h new file mode 100644 index 0000000..0fdb4c7 --- /dev/null +++ b/include/configs/sun50i.h @@ -0,0 +1,25 @@ +/* + * Configuration settings for the Allwinner A64 (sun50i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A64 specific configuration + */ + +#define CONFIG_SUNXI_USB_PHYS 1 + +#define COUNTER_FREQUENCY CONFIG_TIMER_CLK_FREQ +#define GICD_BASE 0x1c81000 +#define GICC_BASE 0x1c82000 + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index 93863b5..95ccc35 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -25,7 +25,6 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_PSCI_NR_CPUS 4 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE -#define CONFIG_TIMER_CLK_FREQ 24000000 /* * Include common sunxi configuration where most the settings are diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 56101a9..0dd2902 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -22,7 +22,6 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE -#define CONFIG_TIMER_CLK_FREQ 24000000 /* * Include common sunxi configuration where most the settings are diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index eb5db4e..bf1b740 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -40,8 +40,6 @@ #endif #endif -#define CONFIG_TIMER_CLK_FREQ 24000000 - /* * Include common sunxi configuration where most the settings are */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index a3994e1..8f11eb9 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -56,6 +56,7 @@ /* CPU */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_TIMER_CLK_FREQ 24000000 /* * The DRAM Base differs between some models. We cannot use macros for the @@ -90,7 +91,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ -#ifdef CONFIG_MACH_SUN9I +#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) /* * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is * slightly bigger. Note that it is possible to map the first 32 KiB of the @@ -99,7 +100,7 @@ * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. */ #define CONFIG_SYS_INIT_RAM_ADDR 0x10000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x0a000 /* 40 KiB */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */ #else #define CONFIG_SYS_INIT_RAM_ADDR 0x0 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ @@ -188,8 +189,16 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE +#if defined(CONFIG_MACH_SUN9I) +#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* ? KiB on sun9i */ +#elif defined(CONFIG_MACH_SUN50I) +#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x7fe0 /* 32 KiB on sun50i */ +#else #define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ #define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ +#endif #define CONFIG_SPL_LIBDISK_SUPPORT @@ -197,14 +206,22 @@ #define CONFIG_SPL_MMC_SUPPORT #endif +#ifndef CONFIG_ARM64 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" +#endif #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */ #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ +#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) +/* FIXME: 40 KiB instead of 32 KiB ? */ +#define LOW_LEVEL_SRAM_STACK 0x00018000 +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK +#else /* end of 32 KiB in sram */ #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK +#endif /* I2C */ #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ -- cgit v0.10.2 From 7adbd1165c600e5e57fc31989148ad578214c6c4 Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Tue, 29 Mar 2016 17:29:11 +0200 Subject: sunxi: Add Pine64+ support The Pine64+ is a system based on the Allwinner A64 SoC. It is capable of running AArch64 code and thus is the first of its kind for the sunxi target. This patch adds a defconfig and device tree chunks for it. Signed-off-by: Siarhei Siamashka [agraf: Change patch description] Signed-off-by: Alexander Graf Acked-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 50bcc0b..ea635e4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -206,6 +206,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-orangepi-2.dtb \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-plus.dtb +dtb-$(CONFIG_MACH_SUN50I) += \ + pine64_plus.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/dts/pine64.dts b/arch/arm/dts/pine64.dts new file mode 100644 index 0000000..dcc998f --- /dev/null +++ b/arch/arm/dts/pine64.dts @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/memreserve/ 0x45000000 0x00200000; +/memreserve/ 0x41010000 0x00010800; +/memreserve/ 0x40100000 0x00006000; + +#include "pine64_common.dtsi" + +/ { + model = "Pine64"; + compatible = "pine64,pine64", "allwinner,a64"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x40000000 0x20000000>; + }; +}; diff --git a/arch/arm/dts/pine64_common.dtsi b/arch/arm/dts/pine64_common.dtsi new file mode 100644 index 0000000..d968d76 --- /dev/null +++ b/arch/arm/dts/pine64_common.dtsi @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "a64.dtsi" + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>; + vmmc-supply = <®_vcc3v3>; + cd-gpios = <&pio 5 6 0>; + cd-inverted; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/pine64_plus.dts b/arch/arm/dts/pine64_plus.dts new file mode 100644 index 0000000..5daff51 --- /dev/null +++ b/arch/arm/dts/pine64_plus.dts @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/memreserve/ 0x45000000 0x00200000; +/memreserve/ 0x41010000 0x00010800; +/memreserve/ 0x40100000 0x00006000; + +#include "pine64_common.dtsi" + +/ { + model = "Pine64+"; + compatible = "pine64,pine64_plus", "allwinner,a64"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */ + memory { + reg = <0x40000000 0x40000000>; + }; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 5f2f4fe..430d770 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -63,6 +63,8 @@ F: configs/q8_a33_tablet_800x480_defconfig F: configs/q8_a33_tablet_1024x600_defconfig F: include/configs/sun9i.h F: configs/Merrii_A80_Optimus_defconfig +F: include/configs/sun50i.h +F: configs/pine64_plus_defconfig A20-OLIMEX-SOM-EVB BOARD M: Marcus Cooper diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig new file mode 100644 index 0000000..c37d378 --- /dev/null +++ b/configs/pine64_plus_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I=y +CONFIG_DRAM_CLK=672 +CONFIG_DRAM_ZQ=3881915 +# CONFIG_VIDEO is not set +CONFIG_DEFAULT_DEVICE_TREE="pine64_plus" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y -- cgit v0.10.2 From 3ffe39ed2b66af71c7271d0cef2a248b5bf7dfdb Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 30 Mar 2016 17:53:56 +0200 Subject: sunxi: Reserve ATF memory space on A64 On the A64 we usually boot with ATF running in EL3. ATF as it is available today resides in the first 16MB of RAM. So we should make sure we reserve that space in our memory maps. Signed-off-by: Alexander Graf Acked-by: Hans de Goede Signed-off-by: Hans de Goede diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ccf4129..3cf3614 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -133,6 +133,15 @@ int dram_init(void) return 0; } +#ifdef CONFIG_MACH_SUN50I +void dram_init_banksize(void) +{ + /* We need to reserve the first 16MB of RAM for ATF */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024); + gd->bd->bi_dram[0].size = get_effective_memsize() - (16 * 1024 * 1024); +} +#endif + #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) static void nand_pinmux_setup(void) { -- cgit v0.10.2