From 282a82e8a10ce6ef132d7a809101fdaed951001c Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Wed, 6 Aug 2014 18:14:35 +0800 Subject: mmc: set correct block size value in bfin sdh driver Wait data transfer till the data end bit other than the data block end bit is set. Acked-by: Pantelis Antoniou Signed-off-by: Sonic Zhang diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index bcd6a3e..9bdfbbc 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -138,9 +138,9 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) if (data->flags & MMC_DATA_WRITE) return UNUSABLE_ERR; #ifndef RSI_BLKSZ - data_ctl |= ((ffs(data_size) - 1) << 4); + data_ctl |= ((ffs(data->blocksize) - 1) << 4); #else - bfin_write_SDH_BLK_SIZE(data_size); + bfin_write_SDH_BLK_SIZE(data->blocksize); #endif data_ctl |= DTX_DIR; bfin_write_SDH_DATA_CTL(data_ctl); @@ -189,7 +189,8 @@ static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, do { udelay(1); status = bfin_read_SDH_STATUS(); - } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN))); + } while (!(status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | + RX_OVERRUN))); if (status & DAT_TIME_OUT) { bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT); -- cgit v0.10.2 From 021a80559f4293368558cc10dbbc75b26ecab059 Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Fri, 8 Aug 2014 09:47:22 +0200 Subject: mmc: fix ERASE_GRP_DEF handling if we set manually this bit on the eMMC card using mmc_switch(...), we also have to set it within our (before read) internal structure 'ext_csd'. Otherwise following checks on this will fail. Acked-by: Pantelis Antoniou Signed-off-by: Hannes Petermaier diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index a26f3ce..52a8e36 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1010,6 +1010,8 @@ static int mmc_startup(struct mmc *mmc) if (err) return err; + else + ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; /* Read out group size from ext_csd */ mmc->erase_grp_size = -- cgit v0.10.2 From 6dc93e7087ccac1acb6910ac8838d9e90c602fe4 Mon Sep 17 00:00:00 2001 From: Peter Bigot Date: Tue, 2 Sep 2014 18:31:23 -0500 Subject: mmc: restore capacity when switching to partition 0 The capacity and lba for an MMC device with part_num 0 reflects the whole device. When mmc_switch_part() successfully switches to a partition, the capacity is changed to that partition. As partition 0 does not physically exist, attempts to switch back to the whole device will indicate an error, but the capacity setting for the whole device must still be restored to match the partition. Signed-off-by: Peter A. Bigot Tested-by: Tom Rini Acked-by: Pantelis Antoniou diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 52a8e36..e4a28d4 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -594,10 +594,15 @@ int mmc_switch_part(int dev_num, unsigned int part_num) ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, (mmc->part_config & ~PART_ACCESS_MASK) | (part_num & PART_ACCESS_MASK)); - if (ret) - return ret; - return mmc_set_capacity(mmc, part_num); + /* + * Set the capacity if the switch succeeded or was intended + * to return to representing the raw device. + */ + if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) + ret = mmc_set_capacity(mmc, part_num); + + return ret; } int mmc_getcd(struct mmc *mmc) -- cgit v0.10.2 From 19345d7c9483b84578da5206b3c604b534121d88 Mon Sep 17 00:00:00 2001 From: Peter Bigot Date: Wed, 3 Sep 2014 12:22:43 -0500 Subject: env_mmc: correct fini partition to match init partition The code to set the MMC partition uses an weak function to obtain the correct partition number. Use that instead of the compile-time default when deciding whether it needs to switch back. Fixes: 6e7b7df4df43574 ("env_mmc: support env partition setup in runtime") Signed-off-by: Peter A. Bigot Acked-by: Dmitry Lifshitz Acked-by: Pantelis Antoniou diff --git a/common/env_mmc.c b/common/env_mmc.c index a7621a8..14648e3 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -113,7 +113,7 @@ static void fini_mmc_for_env(struct mmc *mmc) #ifdef CONFIG_SPL_BUILD dev = 0; #endif - if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) + if (mmc_get_env_part(mmc) != mmc->part_num) mmc_switch_part(dev, mmc->part_num); #endif } -- cgit v0.10.2 From bcd06989b860c691f5afbd1c03d1b0d9e9970cdc Mon Sep 17 00:00:00 2001 From: Mario Schuknecht Date: Mon, 25 Aug 2014 14:12:26 +0200 Subject: mvebu_mmc: Driver addition In function mvebu_mmc_write notice command timeout. It is possible that a command is done, but a timeout occurred. Enable timeout in set bus function. Set window registers. Without that I could not use the driver on a Kirkwood 88F6282 SoC. Set high capacity and 52MHz driver feature. Signed-off-by: Mario Schuknecht Reviewed-by: Stefan Roese Acked-by: Pantelis Antoniou diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c index 9759198..d34e743 100644 --- a/drivers/mmc/mvebu_mmc.c +++ b/drivers/mmc/mvebu_mmc.c @@ -17,8 +17,12 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #define DRIVER_NAME "MVEBU_MMC" +#define MVEBU_TARGET_DRAM 0 + static void mvebu_mmc_write(u32 offs, u32 val) { writel(val, CONFIG_SYS_MMC_BASE + (offs)); @@ -164,6 +168,9 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, return TIMEOUT; } } + if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) & + (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) + return TIMEOUT; /* Handling response */ if (cmd->resp_type & MMC_RSP_136) { @@ -271,6 +278,7 @@ static void mvebu_mmc_set_bus(unsigned int bus) /* default to maximum timeout */ ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); + ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN; ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN; @@ -296,6 +304,55 @@ static void mvebu_mmc_set_ios(struct mmc *mmc) mvebu_mmc_set_clk(mmc->clock); } +/* + * Set window register. + */ +static void mvebu_window_setup(void) +{ + int i; + + for (i = 0; i < 4; i++) { + mvebu_mmc_write(WINDOW_CTRL(i), 0); + mvebu_mmc_write(WINDOW_BASE(i), 0); + } + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + u32 size, base, attrib; + + /* Enable DRAM bank */ + switch (i) { + case 0: + attrib = KWCPU_ATTR_DRAM_CS0; + break; + case 1: + attrib = KWCPU_ATTR_DRAM_CS1; + break; + case 2: + attrib = KWCPU_ATTR_DRAM_CS2; + break; + case 3: + attrib = KWCPU_ATTR_DRAM_CS3; + break; + default: + /* invalide bank, disable access */ + attrib = 0; + break; + } + + size = gd->bd->bi_dram[i].size; + base = gd->bd->bi_dram[i].start; + if (size && attrib) { + mvebu_mmc_write(WINDOW_CTRL(i), + MVCPU_WIN_CTRL_DATA(size, + MVEBU_TARGET_DRAM, + attrib, + MVCPU_WIN_ENABLE)); + } else { + mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE); + } + mvebu_mmc_write(WINDOW_BASE(i), base); + } +} + static int mvebu_mmc_initialize(struct mmc *mmc) { debug("%s: mvebu_mmc_initialize", DRIVER_NAME); @@ -322,6 +379,8 @@ static int mvebu_mmc_initialize(struct mmc *mmc) mvebu_mmc_write(SDIO_NOR_INTR_EN, 0); mvebu_mmc_write(SDIO_ERR_INTR_EN, 0); + mvebu_window_setup(); + /* SW reset */ mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); @@ -342,7 +401,8 @@ static struct mmc_config mvebu_mmc_cfg = { .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX, .f_max = MVEBU_MMC_CLOCKRATE_MAX, .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .host_caps = MMC_MODE_4BIT | MMC_MODE_HS, + .host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC | + MMC_MODE_HS_52MHz, .part_type = PART_TYPE_DOS, .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, }; -- cgit v0.10.2 From 786a27b7ec9efd1ebf50008050e3cff9ce458198 Mon Sep 17 00:00:00 2001 From: Mario Schuknecht Date: Tue, 30 Sep 2014 17:04:42 +0200 Subject: mmc: Fix mmc bus width After setting the bus width, the extended CSD register is read. Some selected fields are compared with previously read extended CSD register fields. In this comparison the EXT_CSD_ERASE_GROUP_DEF field is compared. But this field is previously written under certain circumstances. And then the comparison fails. Only compare read-only fields. Therefore compare field EXT_CSD_HC_WP_GRP_SIZE instead of field EXT_CSD_ERASE_GROUP_DEF. Signed-off-by: Mario Schuknecht Acked-by: Pantelis Antoniou diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index e4a28d4..44a4feb 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1134,10 +1134,11 @@ static int mmc_startup(struct mmc *mmc) mmc_set_bus_width(mmc, widths[idx]); err = mmc_send_ext_csd(mmc, test_csd); + /* Only compare read only fields */ if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \ == test_csd[EXT_CSD_PARTITIONING_SUPPORT] - && ext_csd[EXT_CSD_ERASE_GROUP_DEF] \ - == test_csd[EXT_CSD_ERASE_GROUP_DEF] \ + && ext_csd[EXT_CSD_HC_WP_GRP_SIZE] \ + == test_csd[EXT_CSD_HC_WP_GRP_SIZE] \ && ext_csd[EXT_CSD_REV] \ == test_csd[EXT_CSD_REV] && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \ -- cgit v0.10.2 From fa7b88519e9158cee2b0900d26c049f09f49f8c5 Mon Sep 17 00:00:00 2001 From: Wally Yeh Date: Thu, 25 Sep 2014 23:00:16 +0800 Subject: cmd_mmc: fix bootpart-resize maxarg to 4 sub-command 'bootpart-resize' check for argc == 4, it will retrun CMD_RET_FAILURE when argc value not matched. but bootpart-resize's maxarg is 3, which means you never execute this sub-command successfully. fix it by change bootpart-resize maxarg to 4. Signed-off-by: wally.yeh Cc: Wolfgang Denk Cc: Pierre Aubert Acked-by: Pantelis Antoniou diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 1e40983..4286e26 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -602,7 +602,7 @@ static cmd_tbl_t cmd_mmc[] = { U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""), #ifdef CONFIG_SUPPORT_EMMC_BOOT U_BOOT_CMD_MKENT(bootbus, 5, 0, do_mmc_bootbus, "", ""), - U_BOOT_CMD_MKENT(bootpart-resize, 3, 0, do_mmc_boot_resize, "", ""), + U_BOOT_CMD_MKENT(bootpart-resize, 4, 0, do_mmc_boot_resize, "", ""), U_BOOT_CMD_MKENT(partconf, 5, 0, do_mmc_partconf, "", ""), U_BOOT_CMD_MKENT(rst-function, 3, 0, do_mmc_rst_func, "", ""), #endif -- cgit v0.10.2 From b966db0d7259293e2c9c216c7a5dce30dacacfd9 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Fri, 5 Sep 2014 12:49:48 +0200 Subject: dw_mmc: cleanups dw_mmc driver was responding to errors with debug(). Change that to prinf so that any errors are immediately obvious. Also adjust english in comments. Signed-off-by: Pavel Machek Acked-by: Pantelis Antoniou diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 0df30bc..4c16e7f 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -177,14 +177,16 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } } - if (i == retry) + if (i == retry) { + printf("dwmci_send_cmd: timeout..\n"); return TIMEOUT; + } if (mask & DWMCI_INTMSK_RTO) { - debug("Response Timeout..\n"); + printf("dwmci_send_cmd: Response Timeout..\n"); return TIMEOUT; } else if (mask & DWMCI_INTMSK_RE) { - debug("Response Error..\n"); + printf("dwmci_send_cmd: Response Error..\n"); return -1; } @@ -204,7 +206,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, do { mask = dwmci_readl(host, DWMCI_RINTSTS); if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { - debug("DATA ERROR!\n"); + printf("dwmci_send_cmd: DATA ERROR!\n"); return -1; } } while (!(mask & DWMCI_INTMSK_DTO)); @@ -232,16 +234,16 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) if ((freq == host->clock) || (freq == 0)) return 0; /* - * If host->get_mmc_clk didn't define, + * If host->get_mmc_clk isn't defined, * then assume that host->bus_hz is source clock value. - * host->bus_hz should be set from user. + * host->bus_hz should be set by user. */ if (host->get_mmc_clk) sclk = host->get_mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { - printf("Didn't get source clock value..\n"); + printf("dwmci_setup_bus: Didn't get source clock value..\n"); return -EINVAL; } @@ -260,7 +262,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { - printf("TIMEOUT error!!\n"); + printf("dwmci_setup_bus: timeout!\n"); return -ETIMEDOUT; } } while (status & DWMCI_CMD_START); @@ -275,7 +277,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { - printf("TIMEOUT error!!\n"); + printf("dwmci_setup_bus: timeout!\n"); return -ETIMEDOUT; } } while (status & DWMCI_CMD_START); @@ -290,7 +292,7 @@ static void dwmci_set_ios(struct mmc *mmc) struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 ctype, regs; - debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); + debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); dwmci_setup_bus(host, mmc->clock); switch (mmc->bus_width) { @@ -329,7 +331,7 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_PWREN, 1); if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { - debug("%s[%d] Fail-reset!!\n",__func__,__LINE__); + printf("%s[%d] Fail-reset!!\n", __func__, __LINE__); return -1; } -- cgit v0.10.2 From 91693055995733e268874ae75568ae316233e116 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 4 Sep 2014 12:23:09 +0300 Subject: cfi_flash: don't hide write/erase errors Partially revert commit 0d01f66d235118 (CFI: cfi_flash write fix for AMD legacy). flash_full_status_check() used to skip status register parsing when flash_status_check() returns OK. This is wrong since flash_status_check() must return OK for other status bits to be valid. Cc: Ed Swarthout Signed-off-by: Baruch Siach Signed-off-by: Stefan Roese diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index c4b5bc1..9b3175d 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -593,7 +593,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: - if ((retcode != ERR_OK) + if ((retcode == ERR_OK) && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { retcode = ERR_INVAL; printf ("Flash %s error at address %lx\n", prompt, -- cgit v0.10.2 From 4e2c4ad3604ba6f5053090749d64ed3ce5914805 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 20 Sep 2014 16:51:22 +0200 Subject: usb: ehci: Properly set hub devnum and portnr with usb-1 hubs in the chain For full / low speed devices we need to get the devnum and portnr of the tt, so of the first upstream usb-2 hub, not of the parent device (which may be a usb-1 hub). Signed-off-by: Hans de Goede diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index eaf5913..41af302 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -273,6 +273,29 @@ static inline u8 ehci_encode_speed(enum usb_device_speed speed) return QH_FULL_SPEED; } +static void ehci_update_endpt2_dev_n_port(struct usb_device *dev, + struct QH *qh) +{ + struct usb_device *ttdev; + + if (dev->speed != USB_SPEED_LOW && dev->speed != USB_SPEED_FULL) + return; + + /* + * For full / low speed devices we need to get the devnum and portnr of + * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs + * in the tree before that one! + */ + ttdev = dev; + while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH) + ttdev = ttdev->parent; + if (!ttdev->parent) + return; + + qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) | + QH_ENDPT2_HUBADDR(ttdev->parent->devnum)); +} + static int ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, int length, struct devrequest *req) @@ -390,10 +413,9 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); qh->qh_endpt1 = cpu_to_hc32(endpt); - endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) | - QH_ENDPT2_HUBADDR(dev->parent->devnum) | - QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); + endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); qh->qh_endpt2 = cpu_to_hc32(endpt); + ehci_update_endpt2_dev_n_port(dev, qh); qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); @@ -1201,12 +1223,10 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, (1 << 0)); /* S-mask: microframe 0 */ if (dev->speed == USB_SPEED_LOW || dev->speed == USB_SPEED_FULL) { - debug("TT: port: %d, hub address: %d\n", - dev->portnr, dev->parent->devnum); - qh->qh_endpt2 |= cpu_to_hc32((dev->portnr << 23) | - (dev->parent->devnum << 16) | - (0x1c << 8)); /* C-mask: microframes 2-4 */ + /* C-mask: microframes 2-4 */ + qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8)); } + ehci_update_endpt2_dev_n_port(dev, qh); td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); -- cgit v0.10.2 From ea7b30c58973d59396c71d5880a652639d479a68 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 20 Sep 2014 16:51:23 +0200 Subject: usb: ehci: Add missing cache flush to destroy_int_queue Signed-off-by: Hans de Goede diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 41af302..1a0ddc3 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1342,6 +1342,8 @@ destroy_int_queue(struct usb_device *dev, struct int_queue *queue) if (NEXT_QH(cur) == queue->first) { debug("found candidate. removing from chain\n"); cur->qh_link = queue->last->qh_link; + flush_dcache_range((uint32_t)cur, + ALIGN_END_ADDR(struct QH, cur, 1)); result = 0; break; } -- cgit v0.10.2 From 415548d88446134549917aae026f53dbbee36fd2 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 20 Sep 2014 16:51:24 +0200 Subject: usb: ehci: poll_int_queue check real qtd, not the overlay When we first start an int queue, the qh's overlay area is all zeros. This gets filled by the hc with the actual qtd values as soon as it advances the queue, but we may call poll_int_queue before then, in which case we would think the transfer has completed as the hc has not yet copied the qt_token to the overlay, so the active flag is not set. This fixes this by checking the actual qtd token, rather then the overlay. This also fixes a (theoretical) race where we see the completion in the overlay and free and re-use the qtd before the hc has completed writing back the overlay to the actual qtd. Signed-off-by: Hans de Goede diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 1a0ddc3..635a3b4 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1297,6 +1297,7 @@ fail1: void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) { struct QH *cur = queue->current; + struct qTD *cur_td; /* depleted queue */ if (cur == NULL) { @@ -1304,20 +1305,21 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) return NULL; } /* still active */ - invalidate_dcache_range((uint32_t)cur, - ALIGN_END_ADDR(struct QH, cur, 1)); - if (cur->qh_overlay.qt_token & cpu_to_hc32(0x80)) { - debug("Exit poll_int_queue with no completed intr transfer. " - "token is %x\n", cur->qh_overlay.qt_token); + cur_td = &queue->tds[queue->current - queue->first]; + invalidate_dcache_range((uint32_t)cur_td, + ALIGN_END_ADDR(struct qTD, cur_td, 1)); + if (QT_TOKEN_GET_STATUS(hc32_to_cpu(cur_td->qt_token)) & + QT_TOKEN_STATUS_ACTIVE) { + debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", + hc32_to_cpu(cur_td->qt_token)); return NULL; } if (!(cur->qh_link & QH_LINK_TERMINATE)) queue->current++; else queue->current = NULL; - debug("Exit poll_int_queue with completed intr transfer. " - "token is %x at %p (first at %p)\n", cur->qh_overlay.qt_token, - &cur->qh_overlay.qt_token, queue->first); + debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n", + hc32_to_cpu(cur_td->qt_token), cur, queue->first); return cur->buffer; } -- cgit v0.10.2 From 36b73109c49c1359a5fcc790c00717cb27468c12 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 20 Sep 2014 16:51:25 +0200 Subject: usb: ehci: Make periodic_schedules a per controller variable Periodic schedules tracks how many int_queue-s are active, and decides whether or not to en/disable the periodic schedule based on this. This is clearly a per controller thing. Signed-off-by: Hans de Goede diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 635a3b4..6323c50 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -996,6 +996,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) * Set up periodic list * Step 1: Parent QH for all periodic transfers. */ + ehcic[index].periodic_schedules = 0; periodic = &ehcic[index].periodic_queue; memset(periodic, 0, sizeof(*periodic)); periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); @@ -1154,8 +1155,6 @@ disable_periodic(struct ehci_ctrl *ctrl) return 0; } -static int periodic_schedules; - struct int_queue * create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, int elementsize, void *buffer) @@ -1278,7 +1277,7 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, debug("FATAL: periodic should never fail, but did"); goto fail3; } - periodic_schedules++; + ctrl->periodic_schedules++; debug("Exit create_int_queue\n"); return result; @@ -1335,7 +1334,7 @@ destroy_int_queue(struct usb_device *dev, struct int_queue *queue) debug("FATAL: periodic should never fail, but did"); goto out; } - periodic_schedules--; + ctrl->periodic_schedules--; struct QH *cur = &ctrl->periodic_queue; timeout = get_timer(0) + 500; /* abort after 500ms */ @@ -1357,7 +1356,7 @@ destroy_int_queue(struct usb_device *dev, struct int_queue *queue) } } - if (periodic_schedules > 0) { + if (ctrl->periodic_schedules > 0) { result = enable_periodic(ctrl); if (result < 0) debug("FATAL: periodic should never fail, but did"); diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 093eb4b..433e703 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -246,6 +246,7 @@ struct ehci_ctrl { struct QH qh_list __aligned(USB_DMA_MINALIGN); struct QH periodic_queue __aligned(USB_DMA_MINALIGN); uint32_t *periodic_list; + int periodic_schedules; int ntds; }; -- cgit v0.10.2 From 9b2393812e2b844919ac601b893e6210d5eb6e2c Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 20 Sep 2014 16:51:26 +0200 Subject: usb: kbd: Fix unaligned buffer usage in usb_kbd_setled() Signed-off-by: Hans de Goede diff --git a/common/usb_kbd.c b/common/usb_kbd.c index c34fd5c..87f4125 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -170,11 +170,12 @@ static void usb_kbd_setled(struct usb_device *dev) { struct usb_interface *iface = &dev->config.if_desc[0]; struct usb_kbd_pdata *data = dev->privptr; - uint32_t leds = data->flags & USB_KBD_LEDMASK; + ALLOC_ALIGN_BUFFER(uint32_t, leds, 1, USB_DMA_MINALIGN); + *leds = data->flags & USB_KBD_LEDMASK; usb_control_msg(dev, usb_sndctrlpipe(dev, 0), USB_REQ_SET_REPORT, USB_TYPE_CLASS | USB_RECIP_INTERFACE, - 0x200, iface->desc.bInterfaceNumber, (void *)&leds, 1, 0); + 0x200, iface->desc.bInterfaceNumber, leds, 1, 0); } #define CAPITAL_MASK 0x20 -- cgit v0.10.2 From 0ea09dfe873657df47d83d5d4e0090bbf05c6abb Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 20 Sep 2014 16:54:34 +0200 Subject: usb: kbd: Do not treat -ENODEV as an error for usb_kbd_deregister ENODEV menas no usb keyboard was registered, threat this as a successful usb_kbd_deregister. Signed-off-by: Hans de Goede diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 87f4125..4c17b0d 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -8,6 +8,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include @@ -559,7 +560,11 @@ int drv_usb_kbd_init(void) int usb_kbd_deregister(void) { #ifdef CONFIG_SYS_STDIO_DEREGISTER - return stdio_deregister(DEVNAME); + int ret = stdio_deregister(DEVNAME); + if (ret && ret != -ENODEV) + return ret; + + return 0; #else return 1; #endif -- cgit v0.10.2 From 6e78c74f62ebfa378d1a2f9b83423b23545c28bf Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 20 Sep 2014 16:54:35 +0200 Subject: usb: kbd: On a "usb reset" call usb_kbd_deregister() before calling usb_stop() We need to call usb_kbd_deregister() before calling usb_stop(). usbkbd's stdio_dev->priv points to the usb_device, and usb_kbd_testc dereferences usb_device->privptr. usb_stop zeros usb_device, leaving usb_device->privptr NULL, causing bad things (tm) to happen once control returns to the main loop and usb_kbd_testc gets called. Calling usb_kbd_deregister() avoids this. Note that we do not allow the "usb reset" to continue when the deregister fails. This will be fixed in a later patch. For the same reasons always fail "usb stop" if the usb_kbd_deregister() fails, even in the force path. This can happen when CONFIG_SYS_STDIO_DEREGISTER is not set. Signed-off-by: Hans de Goede diff --git a/common/cmd_usb.c b/common/cmd_usb.c index 2519497..b2aa44c 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -430,6 +430,16 @@ static int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* CONFIG_USB_STORAGE */ +static int do_usb_stop_keyboard(void) +{ +#ifdef CONFIG_USB_KEYBOARD + if (usb_kbd_deregister() != 0) { + printf("USB not stopped: usbkbd still using USB\n"); + return 1; + } +#endif + return 0; +} /****************************************************************************** * usb command intepreter @@ -450,6 +460,8 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((strncmp(argv[1], "reset", 5) == 0) || (strncmp(argv[1], "start", 5) == 0)) { bootstage_mark_name(BOOTSTAGE_ID_USB_START, "usb_start"); + if (do_usb_stop_keyboard() != 0) + return 1; usb_stop(); printf("(Re)start USB...\n"); if (usb_init() >= 0) { @@ -468,19 +480,10 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } if (strncmp(argv[1], "stop", 4) == 0) { -#ifdef CONFIG_USB_KEYBOARD - if (argc == 2) { - if (usb_kbd_deregister() != 0) { - printf("USB not stopped: usbkbd still" - " using USB\n"); - return 1; - } - } else { - /* forced stop, switch console in to serial */ + if (argc != 2) console_assign(stdin, "serial"); - usb_kbd_deregister(); - } -#endif + if (do_usb_stop_keyboard() != 0) + return 1; printf("stopping USB..\n"); usb_stop(); return 0; -- cgit v0.10.2 From 3f78a28037c65b92d2717b7787902a853c2506a4 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 20 Sep 2014 16:54:36 +0200 Subject: usb: kbd: Remove check for already being registered We now always properly deregister the keyboard before calling drv_usb_kbd_init(), so we can drop the check for already being registered. Signed-off-by: Hans de Goede diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 4c17b0d..d4d5f48 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -490,7 +490,7 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) /* Search for keyboard and register it if found. */ int drv_usb_kbd_init(void) { - struct stdio_dev usb_kbd_dev, *old_dev; + struct stdio_dev usb_kbd_dev; struct usb_device *dev; char *stdinname = getenv("stdin"); int error, i; @@ -509,16 +509,6 @@ int drv_usb_kbd_init(void) if (usb_kbd_probe(dev, 0) != 1) continue; - /* We found a keyboard, check if it is already registered. */ - debug("USB KBD: found set up device.\n"); - old_dev = stdio_get_by_name(DEVNAME); - if (old_dev) { - /* Already registered, just return ok. */ - debug("USB KBD: is already registered.\n"); - usb_kbd_deregister(); - return 1; - } - /* Register the keyboard */ debug("USB KBD: register.\n"); memset(&usb_kbd_dev, 0, sizeof(struct stdio_dev)); -- cgit v0.10.2 From 32d019265d1f0c334f2f86407abf295d46bd2f4d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 20 Sep 2014 16:54:37 +0200 Subject: stdio: Add force parameter to stdio_deregister In some cases we really want to move forward with a deregister, add a force parameter to allow this, and replace the dev with a nulldev in this case. Signed-off-by: Hans de Goede diff --git a/common/stdio.c b/common/stdio.c index c878103..8232815 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -34,6 +34,9 @@ char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" }; #define CONFIG_SYS_DEVICE_NULLDEV 1 #endif +#ifdef CONFIG_SYS_STDIO_DEREGISTER +#define CONFIG_SYS_DEVICE_NULLDEV 1 +#endif #ifdef CONFIG_SYS_DEVICE_NULLDEV void nulldev_putc(struct stdio_dev *dev, const char c) @@ -172,7 +175,7 @@ int stdio_register(struct stdio_dev *dev) * returns 0 if success, -1 if device is assigned and 1 if devname not found */ #ifdef CONFIG_SYS_STDIO_DEREGISTER -int stdio_deregister_dev(struct stdio_dev *dev) +int stdio_deregister_dev(struct stdio_dev *dev, int force) { int l; struct list_head *pos; @@ -181,6 +184,10 @@ int stdio_deregister_dev(struct stdio_dev *dev) /* get stdio devices (ListRemoveItem changes the dev list) */ for (l=0 ; l< MAX_FILES; l++) { if (stdio_devices[l] == dev) { + if (force) { + strcpy(temp_names[l], "nulldev"); + continue; + } /* Device is assigned -> report error */ return -1; } @@ -202,7 +209,7 @@ int stdio_deregister_dev(struct stdio_dev *dev) return 0; } -int stdio_deregister(const char *devname) +int stdio_deregister(const char *devname, int force) { struct stdio_dev *dev; @@ -211,7 +218,7 @@ int stdio_deregister(const char *devname) if (!dev) /* device not found */ return -ENODEV; - return stdio_deregister_dev(dev); + return stdio_deregister_dev(dev, force); } #endif /* CONFIG_SYS_STDIO_DEREGISTER */ diff --git a/common/usb_kbd.c b/common/usb_kbd.c index d4d5f48..dcb693d 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -550,7 +550,7 @@ int drv_usb_kbd_init(void) int usb_kbd_deregister(void) { #ifdef CONFIG_SYS_STDIO_DEREGISTER - int ret = stdio_deregister(DEVNAME); + int ret = stdio_deregister(DEVNAME, 0); if (ret && ret != -ENODEV) return ret; diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 1ac943f..fd010ca 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -198,7 +198,7 @@ static int serial_pre_remove(struct udevice *dev) #ifdef CONFIG_SYS_STDIO_DEREGISTER struct serial_dev_priv *upriv = dev->uclass_priv; - if (stdio_deregister_dev(upriv->sdev)) + if (stdio_deregister_dev(upriv->sdev), 0) return -EPERM; #endif diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 268de8e..24da23f 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -103,8 +103,8 @@ int stdio_init(void); void stdio_print_current_devices(void); #ifdef CONFIG_SYS_STDIO_DEREGISTER -int stdio_deregister(const char *devname); -int stdio_deregister_dev(struct stdio_dev *dev); +int stdio_deregister(const char *devname, int force); +int stdio_deregister_dev(struct stdio_dev *dev, int force); #endif struct list_head* stdio_get_list(void); struct stdio_dev* stdio_get_by_name(const char* name); -- cgit v0.10.2 From 8a8a2257ec55a997d97edf6664249a628248fe01 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 20 Sep 2014 16:54:38 +0200 Subject: usb: kbd: Allow "usb reset" to continue when an usb kbd is used Use the new force parameter to make the stdio_deregister succeed, replacing stdin with a nulldev, and assume that the usb keyboard will come back after the reset. Signed-off-by: Hans de Goede diff --git a/common/cmd_usb.c b/common/cmd_usb.c index b2aa44c..c192498 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -430,10 +430,10 @@ static int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* CONFIG_USB_STORAGE */ -static int do_usb_stop_keyboard(void) +static int do_usb_stop_keyboard(int force) { #ifdef CONFIG_USB_KEYBOARD - if (usb_kbd_deregister() != 0) { + if (usb_kbd_deregister(force) != 0) { printf("USB not stopped: usbkbd still using USB\n"); return 1; } @@ -460,7 +460,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((strncmp(argv[1], "reset", 5) == 0) || (strncmp(argv[1], "start", 5) == 0)) { bootstage_mark_name(BOOTSTAGE_ID_USB_START, "usb_start"); - if (do_usb_stop_keyboard() != 0) + if (do_usb_stop_keyboard(1) != 0) return 1; usb_stop(); printf("(Re)start USB...\n"); @@ -482,7 +482,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (strncmp(argv[1], "stop", 4) == 0) { if (argc != 2) console_assign(stdin, "serial"); - if (do_usb_stop_keyboard() != 0) + if (do_usb_stop_keyboard(0) != 0) return 1; printf("stopping USB..\n"); usb_stop(); diff --git a/common/usb_kbd.c b/common/usb_kbd.c index dcb693d..fdc083c 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -547,10 +547,10 @@ int drv_usb_kbd_init(void) } /* Deregister the keyboard. */ -int usb_kbd_deregister(void) +int usb_kbd_deregister(int force) { #ifdef CONFIG_SYS_STDIO_DEREGISTER - int ret = stdio_deregister(DEVNAME, 0); + int ret = stdio_deregister(DEVNAME, force); if (ret && ret != -ENODEV) return ret; diff --git a/include/usb.h b/include/usb.h index d9fedee..c355fbe 100644 --- a/include/usb.h +++ b/include/usb.h @@ -216,7 +216,7 @@ int usb_host_eth_scan(int mode); #ifdef CONFIG_USB_KEYBOARD int drv_usb_kbd_init(void); -int usb_kbd_deregister(void); +int usb_kbd_deregister(int force); #endif /* routines */ -- cgit v0.10.2 From b9c99d32466b90aa2269eca99545f045a23266ab Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 11 Sep 2014 15:26:10 +0200 Subject: usb: dfu: thor: gadget: Remove dead code This code is not used anymore in the current DFU implementation and can be safely removed. Signed-off-by: Lukasz Majewski diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 3e4f029..d040606 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -81,14 +81,6 @@ static struct usb_descriptor_header *dfu_runtime_descs[] = { NULL, }; -static const struct usb_qualifier_descriptor dev_qualifier = { - .bLength = sizeof dev_qualifier, - .bDescriptorType = USB_DT_DEVICE_QUALIFIER, - .bcdUSB = __constant_cpu_to_le16(0x0200), - .bDeviceClass = USB_CLASS_VENDOR_SPEC, - .bNumConfigurations = 1, -}; - static const char dfu_name[] = "Device Firmware Upgrade"; /* diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index c85b0fb..78519fa 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -458,16 +458,6 @@ static struct usb_endpoint_descriptor hs_int_desc = { .bInterval = 0x9, }; -static struct usb_qualifier_descriptor dev_qualifier = { - .bLength = sizeof(dev_qualifier), - .bDescriptorType = USB_DT_DEVICE_QUALIFIER, - - .bcdUSB = __constant_cpu_to_le16(0x0200), - .bDeviceClass = USB_CLASS_VENDOR_SPEC, - - .bNumConfigurations = 2, -}; - /* * This attribute vendor descriptor is necessary for correct operation with * Windows version of THOR download program -- cgit v0.10.2 From 9f3b8ed14cef1e277f1362f121e16975bba2026f Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 10 Sep 2014 08:55:00 +0200 Subject: usb: dfu: add fullspeed support for DFU DFU now can use also fullspeed. Signed-off-by: Heiko Schocher Cc: Tom Rini Cc: Lukasz Majewski Cc: Marek Vasut Cc: Liu Bin Cc: Lukas Stockmann diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index d040606..16fc9dd 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -229,6 +229,7 @@ static inline void to_dfu_mode(struct f_dfu *f_dfu) { f_dfu->usb_function.strings = dfu_strings; f_dfu->usb_function.hs_descriptors = f_dfu->function; + f_dfu->usb_function.descriptors = f_dfu->function; f_dfu->dfu_state = DFU_STATE_dfuIDLE; } @@ -236,6 +237,7 @@ static inline void to_runtime_mode(struct f_dfu *f_dfu) { f_dfu->usb_function.strings = NULL; f_dfu->usb_function.hs_descriptors = dfu_runtime_descs; + f_dfu->usb_function.descriptors = dfu_runtime_descs; } static int handle_upload(struct usb_request *req, u16 len) @@ -800,6 +802,7 @@ static int dfu_bind_config(struct usb_configuration *c) return -ENOMEM; f_dfu->usb_function.name = "dfu"; f_dfu->usb_function.hs_descriptors = dfu_runtime_descs; + f_dfu->usb_function.descriptors = dfu_runtime_descs; f_dfu->usb_function.bind = dfu_bind; f_dfu->usb_function.unbind = dfu_unbind; f_dfu->usb_function.set_alt = dfu_set_alt; -- cgit v0.10.2 From ece91016c46b9945485b41f50589ea92f1f04ce1 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 10 Sep 2014 08:55:01 +0200 Subject: arm: am335x: siemens board use in DFU mode fullspeed only Siemens boards are now using DFU in fullspeed only. For this CONFIG_USB_GADGET_DUALSPEED is undefined. Signed-off-by: Heiko Schocher Cc: Tom Rini Cc: Lukasz Majewski Cc: Marek Vasut Cc: Liu Bin Cc: Lukas Stockmann diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index bf9752f..1ce0965 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -231,7 +231,7 @@ #define CONFIG_MUSB_GADGET #define CONFIG_MUSB_PIO_ONLY #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT -#define CONFIG_USB_GADGET_DUALSPEED +#undef CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_MUSB_HOST -- cgit v0.10.2 From f9935c87b6c8e81ef8d621bd06d24a78eec8a821 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Fri, 19 Sep 2014 17:06:46 -0700 Subject: usb: f_mass_storage: set removable flag in do_inquiry based on LUN Without this flag, tools like Alex Page's USB Image Tool won't see drives exposed over USB Gadget as removable, and won't allow access to them. http://www.alexpage.de/usb-image-tool/ The code was pulled from the main-line kernel: drivers/usb/gadget/function/f_mass_storage.c Signed-off-by: Eric Nelson diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index f274d96..e045957 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -1110,6 +1110,7 @@ static int do_inquiry(struct fsg_common *common, struct fsg_buffhd *bh) memset(buf, 0, 8); buf[0] = TYPE_DISK; + buf[1] = curlun->removable ? 0x80 : 0; buf[2] = 2; /* ANSI SCSI level 2 */ buf[3] = 2; /* SCSI-2 INQUIRY data format */ buf[4] = 31; /* Additional length */ -- cgit v0.10.2 From 23d1d10c4248f1b9f838e512e7f18e600f06b348 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Fri, 19 Sep 2014 14:15:12 +0800 Subject: usb: gadget: fastboot: improve download progress bar When download is ongoing, if the actual size of one transfer is not the same as BYTES_PER_DOT, which will cause the dot won't print anymore. Then it will let the user thinking it is stuck, actually it is transfering without dot printed. So, improve the method to show the progress bar (print dot). Signed-off-by: Bo Shen Acked-by: Marek Vasut diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 38c0965..9d15f63 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -386,6 +386,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) unsigned int transfer_size = download_size - download_bytes; const unsigned char *buffer = req->buf; unsigned int buffer_size = req->actual; + unsigned int pre_dot_num, now_dot_num; if (req->status != 0) { printf("Bad status: %d\n", req->status); @@ -398,7 +399,15 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) memcpy((void *)CONFIG_USB_FASTBOOT_BUF_ADDR + download_bytes, buffer, transfer_size); + pre_dot_num = download_bytes / BYTES_PER_DOT; download_bytes += transfer_size; + now_dot_num = download_bytes / BYTES_PER_DOT; + + if (pre_dot_num != now_dot_num) { + putc('.'); + if (!(now_dot_num % 74)) + putc('\n'); + } /* Check if transfer is done */ if (download_bytes >= download_size) { @@ -420,11 +429,6 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) req->length = ep->maxpacket; } - if (download_bytes && !(download_bytes % BYTES_PER_DOT)) { - putc('.'); - if (!(download_bytes % (74 * BYTES_PER_DOT))) - putc('\n'); - } req->actual = 0; usb_ep_queue(ep, req, 0); } -- cgit v0.10.2 From e206799370f77097a29577599960b7f123f61b8c Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Sun, 28 Sep 2014 18:35:14 -0700 Subject: usb: ci_udc: respect CONFIG_USB_GADGET_DUALSPEED Force full-speed (12 Mbit/s) operation if CONFIG_USB_GADGET_DUALSPEED is not defined. The controller is capable of high-speed (480 Mbit/s) operation, but some designs may require the use of lower-speed operation. Signed-off-by: Eric Nelson diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 2572b34..b0ef35e 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -777,6 +777,11 @@ static int ci_pullup(struct usb_gadget *gadget, int is_on) /* select DEVICE mode */ writel(USBMODE_DEVICE, &udc->usbmode); +#if !defined(CONFIG_USB_GADGET_DUALSPEED) + /* Port force Full-Speed Connect */ + setbits_le32(&udc->portsc, PFSC); +#endif + writel(0xffffffff, &udc->epflush); /* Turn on the USB connection by enabling the pullup resistor */ -- cgit v0.10.2 From c674a6660e9934cf332bb007726997b1c3686bf1 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 30 Sep 2014 12:05:40 -0700 Subject: usb: gadget: fastboot: add max-download-size variable Current Android Fastboot seems to use 'max-download-size' instead of 'downloadsize' variable to indicate the maximum size of sparse segments. See function get_target_sparse_limit() in file fastboot/fastboot.c in the AOSP: https://android.googlesource.com/platform/system/core/+/master Signed-off-by: Eric Nelson diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 9d15f63..3e1c0a9 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -351,7 +351,8 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) strncat(response, FASTBOOT_VERSION, chars_left); } else if (!strcmp_l1("bootloader-version", cmd)) { strncat(response, U_BOOT_VERSION, chars_left); - } else if (!strcmp_l1("downloadsize", cmd)) { + } else if (!strcmp_l1("downloadsize", cmd) || + !strcmp_l1("max-download-size", cmd)) { char str_num[12]; sprintf(str_num, "%08x", CONFIG_USB_FASTBOOT_BUF_SIZE); -- cgit v0.10.2 From 84c24f66c2971f2a4149f60228bfc08f29ba9d30 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 30 Sep 2014 12:05:41 -0700 Subject: usb: gadget: fastboot: explicitly set radix of maximum download size The processing of the max-download-size variable requires a radix specifier, or the fastboot host tool will interpret it as an octal number. See function get_target_sparse_limit() in file fastboot/fastboot.c in the AOSP: https://android.googlesource.com/platform/system/core/+/master Signed-off-by: Eric Nelson diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 3e1c0a9..392379d 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -355,7 +355,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) !strcmp_l1("max-download-size", cmd)) { char str_num[12]; - sprintf(str_num, "%08x", CONFIG_USB_FASTBOOT_BUF_SIZE); + sprintf(str_num, "0x%08x", CONFIG_USB_FASTBOOT_BUF_SIZE); strncat(response, str_num, chars_left); } else if (!strcmp_l1("serialno", cmd)) { s = getenv("serial#"); -- cgit v0.10.2 From d1fcbae1173f00917f5a71e4c074a61120605021 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 4 Oct 2014 01:46:10 +0200 Subject: usb: tegra: ULPI regression on tegra20 Trying to enumerate USB devices connected via ULPI to T20 failed as follows: USB2: ULPI integrity check failed Git bisecting revealed the following commit being at odds: commit 2d34151f7501ddaa599897f0d89ad576126b03eb usb: tegra: refactor PHY type selection Looking at above commit one quickly identifies a copy paste error which this patch fixes. Happy ULPIing again (;-p). Signed-off-by: Marcel Ziswiler diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 33e5ea9..5f0a98e 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -305,11 +305,11 @@ static void init_phy_mux(struct fdt_usb *config, uint pts, #if defined(CONFIG_TEGRA20) if (config->periph_id == PERIPH_ID_USBD) { clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, - PTS_UTMI << PTS1_SHIFT); + pts << PTS1_SHIFT); clrbits_le32(&usbctlr->port_sc1, STS1); } else { clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, - PTS_UTMI << PTS_SHIFT); + pts << PTS_SHIFT); clrbits_le32(&usbctlr->port_sc1, STS); } #else -- cgit v0.10.2 From 0ae16cbb40a2881f6dfbe00fcb023ee7b548bc5c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 20:21:42 +0200 Subject: fpga: altera: Clean up the printing and debug Clean up the printf() statements and get rid of the PRINTF() macro by replacing it with debug_cond(). Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 6e34a8e..ed3f0c8 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -15,14 +15,8 @@ #include #include -/* Define FPGA_DEBUG to get debug printf's */ -/* #define FPGA_DEBUG */ - -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif +/* Define FPGA_DEBUG to 1 to get debug printf's */ +#define FPGA_DEBUG 0 /* Local Static Functions */ static int altera_validate (Altera_desc * desc, const char *fn); @@ -32,36 +26,39 @@ int altera_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + if (!altera_validate (desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); } else { switch (desc->family) { case Altera_ACEX1K: case Altera_CYC2: #if defined(CONFIG_FPGA_ACEX1K) - PRINTF ("%s: Launching the ACEX1K Loader...\n", - __FUNCTION__); + debug_cond(FPGA_DEBUG, + "%s: Launching the ACEX1K Loader...\n", + __func__); ret_val = ACEX1K_load (desc, buf, bsize); #elif defined(CONFIG_FPGA_CYCLON2) - PRINTF ("%s: Launching the CYCLONE II Loader...\n", - __FUNCTION__); + debug_cond(FPGA_DEBUG, + "%s: Launching the CYCLONE II Loader...\n", + __func__); ret_val = CYC2_load (desc, buf, bsize); #else - printf ("%s: No support for ACEX1K devices.\n", - __FUNCTION__); + printf("%s: No support for ACEX1K devices.\n", + __func__); #endif break; #if defined(CONFIG_FPGA_STRATIX_II) case Altera_StratixII: - PRINTF ("%s: Launching the Stratix II Loader...\n", - __FUNCTION__); + debug_cond(FPGA_DEBUG, + "%s: Launching the Stratix II Loader...\n", + __func__); ret_val = StratixII_load (desc, buf, bsize); break; #endif default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); + printf("%s: Unsupported family type, %d\n", + __func__, desc->family); } } @@ -72,31 +69,33 @@ int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + if (!altera_validate (desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); } else { switch (desc->family) { case Altera_ACEX1K: #if defined(CONFIG_FPGA_ACEX) - PRINTF ("%s: Launching the ACEX1K Reader...\n", - __FUNCTION__); + debug_cond(FPGA_DEBUG, + "%s: Launching the ACEX1K Reader...\n", + __func__); ret_val = ACEX1K_dump (desc, buf, bsize); #else - printf ("%s: No support for ACEX1K devices.\n", - __FUNCTION__); + printf("%s: No support for ACEX1K devices.\n", + __func__); #endif break; #if defined(CONFIG_FPGA_STRATIX_II) case Altera_StratixII: - PRINTF ("%s: Launching the Stratix II Reader...\n", - __FUNCTION__); + debug_cond(FPGA_DEBUG, + "%s: Launching the Stratix II Reader...\n", + __func__); ret_val = StratixII_dump (desc, buf, bsize); break; #endif default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); + printf("%s: Unsupported family type, %d\n", + __func__, desc->family); } } @@ -107,42 +106,42 @@ int altera_info( Altera_desc *desc ) { int ret_val = FPGA_FAIL; - if (altera_validate (desc, (char *)__FUNCTION__)) { - printf ("Family: \t"); + if (altera_validate (desc, (char *)__func__)) { + printf("Family: \t"); switch (desc->family) { case Altera_ACEX1K: - printf ("ACEX1K\n"); + printf("ACEX1K\n"); break; case Altera_CYC2: - printf ("CYCLON II\n"); + printf("CYCLON II\n"); break; case Altera_StratixII: - printf ("Stratix II\n"); + printf("Stratix II\n"); break; /* Add new family types here */ default: - printf ("Unknown family type, %d\n", desc->family); + printf("Unknown family type, %d\n", desc->family); } - printf ("Interface type:\t"); + printf("Interface type:\t"); switch (desc->iface) { case passive_serial: - printf ("Passive Serial (PS)\n"); + printf("Passive Serial (PS)\n"); break; case passive_parallel_synchronous: - printf ("Passive Parallel Synchronous (PPS)\n"); + printf("Passive Parallel Synchronous (PPS)\n"); break; case passive_parallel_asynchronous: - printf ("Passive Parallel Asynchronous (PPA)\n"); + printf("Passive Parallel Asynchronous (PPA)\n"); break; case passive_serial_asynchronous: - printf ("Passive Serial Asynchronous (PSA)\n"); + printf("Passive Serial Asynchronous (PSA)\n"); break; case altera_jtag_mode: /* Not used */ - printf ("JTAG Mode\n"); + printf("JTAG Mode\n"); break; case fast_passive_parallel: - printf ("Fast Passive Parallel (FPP)\n"); + printf("Fast Passive Parallel (FPP)\n"); break; case fast_passive_parallel_security: printf @@ -150,31 +149,31 @@ int altera_info( Altera_desc *desc ) break; /* Add new interface types here */ default: - printf ("Unsupported interface type, %d\n", desc->iface); + printf("Unsupported interface type, %d\n", desc->iface); } printf("Device Size: \t%zd bytes\n" - "Cookie: \t0x%x (%d)\n", - desc->size, desc->cookie, desc->cookie); + "Cookie: \t0x%x (%d)\n", + desc->size, desc->cookie, desc->cookie); if (desc->iface_fns) { - printf ("Device Function Table @ 0x%p\n", desc->iface_fns); + printf("Device Function Table @ 0x%p\n", desc->iface_fns); switch (desc->family) { case Altera_ACEX1K: case Altera_CYC2: #if defined(CONFIG_FPGA_ACEX1K) - ACEX1K_info (desc); + ACEX1K_info(desc); #elif defined(CONFIG_FPGA_CYCLON2) - CYC2_info (desc); + CYC2_info(desc); #else /* just in case */ - printf ("%s: No support for ACEX1K devices.\n", - __FUNCTION__); + printf("%s: No support for ACEX1K devices.\n", + __func__); #endif break; #if defined(CONFIG_FPGA_STRATIX_II) case Altera_StratixII: - StratixII_info (desc); + StratixII_info(desc); break; #endif /* Add new family types here */ @@ -183,12 +182,12 @@ int altera_info( Altera_desc *desc ) break; } } else { - printf ("No Device Function Table.\n"); + printf("No Device Function Table.\n"); } ret_val = FPGA_SUCCESS; } else { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + printf("%s: Invalid device descriptor\n", __func__); } return ret_val; @@ -208,17 +207,17 @@ static int altera_validate (Altera_desc * desc, const char *fn) if (desc->size) { ret_val = true; } else { - printf ("%s: NULL part size\n", fn); + printf("%s: NULL part size\n", fn); } } else { - printf ("%s: Invalid Interface type, %d\n", - fn, desc->iface); + printf("%s: Invalid Interface type, %d\n", + fn, desc->iface); } } else { - printf ("%s: Invalid family type, %d\n", fn, desc->family); + printf("%s: Invalid family type, %d\n", fn, desc->family); } } else { - printf ("%s: NULL descriptor!\n", fn); + printf("%s: NULL descriptor!\n", fn); } return ret_val; -- cgit v0.10.2 From 5561a841487fa246ebc6df17bed8eabfa33f3557 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 20:26:07 +0200 Subject: fpga: altera: Clean up altera_validate function Boldly go, where no programmer has gone before and just clean up the indentation mayhem. No functional change. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index ed3f0c8..6394afe 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -195,32 +195,31 @@ int altera_info( Altera_desc *desc ) /* ------------------------------------------------------------------------- */ -static int altera_validate (Altera_desc * desc, const char *fn) +static int altera_validate(Altera_desc *desc, const char *fn) { - int ret_val = false; - - if (desc) { - if ((desc->family > min_altera_type) && - (desc->family < max_altera_type)) { - if ((desc->iface > min_altera_iface_type) && - (desc->iface < max_altera_iface_type)) { - if (desc->size) { - ret_val = true; - } else { - printf("%s: NULL part size\n", fn); - } - } else { - printf("%s: Invalid Interface type, %d\n", - fn, desc->iface); - } - } else { - printf("%s: Invalid family type, %d\n", fn, desc->family); - } - } else { + if (!desc) { printf("%s: NULL descriptor!\n", fn); + return false; } - return ret_val; + if ((desc->family < min_altera_type) || + (desc->family > max_altera_type)) { + printf("%s: Invalid family type, %d\n", fn, desc->family); + return false; + } + + if ((desc->iface < min_altera_iface_type) || + (desc->iface > max_altera_iface_type)) { + printf("%s: Invalid Interface type, %d\n", fn, desc->iface); + return false; + } + + if (!desc->size) { + printf("%s: NULL part size\n", fn); + return false; + } + + return true; } /* ------------------------------------------------------------------------- */ -- cgit v0.10.2 From 4a4c0a5e9a2b65711f733bc2178e506131b0693b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 20:29:24 +0200 Subject: fpga: altera: More indentation trimdown Further improve the indentation in the rest of the file, where the indentation is initially a bit less brutal. There is no functional change in this patch. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 6394afe..b0f323f 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -26,40 +26,41 @@ int altera_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate (desc, (char *)__func__)) { + if (!altera_validate(desc, (char *)__func__)) { printf("%s: Invalid device descriptor\n", __func__); - } else { - switch (desc->family) { - case Altera_ACEX1K: - case Altera_CYC2: + return FPGA_FAIL; + } + + switch (desc->family) { + case Altera_ACEX1K: + case Altera_CYC2: #if defined(CONFIG_FPGA_ACEX1K) - debug_cond(FPGA_DEBUG, - "%s: Launching the ACEX1K Loader...\n", - __func__); - ret_val = ACEX1K_load (desc, buf, bsize); + debug_cond(FPGA_DEBUG, + "%s: Launching the ACEX1K Loader...\n", + __func__); + ret_val = ACEX1K_load (desc, buf, bsize); #elif defined(CONFIG_FPGA_CYCLON2) - debug_cond(FPGA_DEBUG, - "%s: Launching the CYCLONE II Loader...\n", - __func__); - ret_val = CYC2_load (desc, buf, bsize); + debug_cond(FPGA_DEBUG, + "%s: Launching the CYCLONE II Loader...\n", + __func__); + ret_val = CYC2_load (desc, buf, bsize); #else - printf("%s: No support for ACEX1K devices.\n", - __func__); + printf("%s: No support for ACEX1K devices.\n", + __func__); #endif - break; + break; #if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - debug_cond(FPGA_DEBUG, - "%s: Launching the Stratix II Loader...\n", - __func__); - ret_val = StratixII_load (desc, buf, bsize); - break; + case Altera_StratixII: + debug_cond(FPGA_DEBUG, + "%s: Launching the Stratix II Loader...\n", + __func__); + ret_val = StratixII_load (desc, buf, bsize); + break; #endif - default: - printf("%s: Unsupported family type, %d\n", - __func__, desc->family); - } + default: + printf("%s: Unsupported family type, %d\n", + __func__, desc->family); } return ret_val; @@ -71,125 +72,126 @@ int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) if (!altera_validate (desc, (char *)__func__)) { printf("%s: Invalid device descriptor\n", __func__); - } else { - switch (desc->family) { - case Altera_ACEX1K: + return FPGA_FAIL; + } + + switch (desc->family) { + case Altera_ACEX1K: #if defined(CONFIG_FPGA_ACEX) - debug_cond(FPGA_DEBUG, - "%s: Launching the ACEX1K Reader...\n", - __func__); - ret_val = ACEX1K_dump (desc, buf, bsize); + debug_cond(FPGA_DEBUG, + "%s: Launching the ACEX1K Reader...\n", + __func__); + ret_val = ACEX1K_dump (desc, buf, bsize); #else - printf("%s: No support for ACEX1K devices.\n", - __func__); + printf("%s: No support for ACEX1K devices.\n", + __func__); #endif - break; + break; #if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - debug_cond(FPGA_DEBUG, - "%s: Launching the Stratix II Reader...\n", - __func__); - ret_val = StratixII_dump (desc, buf, bsize); - break; + case Altera_StratixII: + debug_cond(FPGA_DEBUG, + "%s: Launching the Stratix II Reader...\n", + __func__); + ret_val = StratixII_dump (desc, buf, bsize); + break; #endif - default: - printf("%s: Unsupported family type, %d\n", - __func__, desc->family); - } + default: + printf("%s: Unsupported family type, %d\n", + __func__, desc->family); } return ret_val; } -int altera_info( Altera_desc *desc ) +int altera_info(Altera_desc *desc) { int ret_val = FPGA_FAIL; - if (altera_validate (desc, (char *)__func__)) { - printf("Family: \t"); - switch (desc->family) { - case Altera_ACEX1K: - printf("ACEX1K\n"); - break; - case Altera_CYC2: - printf("CYCLON II\n"); - break; - case Altera_StratixII: - printf("Stratix II\n"); - break; - /* Add new family types here */ - default: - printf("Unknown family type, %d\n", desc->family); - } + if (!altera_validate (desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); + return FPGA_FAIL; + } - printf("Interface type:\t"); - switch (desc->iface) { - case passive_serial: - printf("Passive Serial (PS)\n"); - break; - case passive_parallel_synchronous: - printf("Passive Parallel Synchronous (PPS)\n"); - break; - case passive_parallel_asynchronous: - printf("Passive Parallel Asynchronous (PPA)\n"); - break; - case passive_serial_asynchronous: - printf("Passive Serial Asynchronous (PSA)\n"); - break; - case altera_jtag_mode: /* Not used */ - printf("JTAG Mode\n"); - break; - case fast_passive_parallel: - printf("Fast Passive Parallel (FPP)\n"); - break; - case fast_passive_parallel_security: - printf - ("Fast Passive Parallel with Security (FPPS) \n"); - break; - /* Add new interface types here */ - default: - printf("Unsupported interface type, %d\n", desc->iface); - } + printf("Family: \t"); + switch (desc->family) { + case Altera_ACEX1K: + printf("ACEX1K\n"); + break; + case Altera_CYC2: + printf("CYCLON II\n"); + break; + case Altera_StratixII: + printf("Stratix II\n"); + break; + /* Add new family types here */ + default: + printf("Unknown family type, %d\n", desc->family); + } - printf("Device Size: \t%zd bytes\n" - "Cookie: \t0x%x (%d)\n", - desc->size, desc->cookie, desc->cookie); + printf("Interface type:\t"); + switch (desc->iface) { + case passive_serial: + printf("Passive Serial (PS)\n"); + break; + case passive_parallel_synchronous: + printf("Passive Parallel Synchronous (PPS)\n"); + break; + case passive_parallel_asynchronous: + printf("Passive Parallel Asynchronous (PPA)\n"); + break; + case passive_serial_asynchronous: + printf("Passive Serial Asynchronous (PSA)\n"); + break; + case altera_jtag_mode: /* Not used */ + printf("JTAG Mode\n"); + break; + case fast_passive_parallel: + printf("Fast Passive Parallel (FPP)\n"); + break; + case fast_passive_parallel_security: + printf("Fast Passive Parallel with Security (FPPS)\n"); + break; + /* Add new interface types here */ + default: + printf("Unsupported interface type, %d\n", desc->iface); + } + + printf("Device Size: \t%zd bytes\n" + "Cookie: \t0x%x (%d)\n", + desc->size, desc->cookie, desc->cookie); - if (desc->iface_fns) { - printf("Device Function Table @ 0x%p\n", desc->iface_fns); - switch (desc->family) { - case Altera_ACEX1K: - case Altera_CYC2: + if (desc->iface_fns) { + printf("Device Function Table @ 0x%p\n", desc->iface_fns); + switch (desc->family) { + case Altera_ACEX1K: + case Altera_CYC2: #if defined(CONFIG_FPGA_ACEX1K) - ACEX1K_info(desc); + ACEX1K_info(desc); #elif defined(CONFIG_FPGA_CYCLON2) - CYC2_info(desc); + CYC2_info(desc); #else - /* just in case */ - printf("%s: No support for ACEX1K devices.\n", - __func__); + /* just in case */ + printf("%s: No support for ACEX1K devices.\n", + __func__); #endif - break; + break; #if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - StratixII_info(desc); - break; + case Altera_StratixII: + StratixII_info(desc); + break; #endif - /* Add new family types here */ - default: - /* we don't need a message here - we give one up above */ - break; - } - } else { - printf("No Device Function Table.\n"); + /* Add new family types here */ + default: + /* we don't need a message here - we give one up above */ + break; } - - ret_val = FPGA_SUCCESS; } else { - printf("%s: Invalid device descriptor\n", __func__); + printf("No Device Function Table.\n"); } + ret_val = FPGA_SUCCESS; + return ret_val; } -- cgit v0.10.2 From 54c96b18a22a6ee5d5a67c057ed5d3812ac16b39 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 20:32:51 +0200 Subject: fpga: altera: Move altera_validate to the top Move the function to the top of the file to avoid forward declaration. No functional change. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index b0f323f..9e9df50 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -19,7 +19,32 @@ #define FPGA_DEBUG 0 /* Local Static Functions */ -static int altera_validate (Altera_desc * desc, const char *fn); +static int altera_validate(Altera_desc *desc, const char *fn) +{ + if (!desc) { + printf("%s: NULL descriptor!\n", fn); + return false; + } + + if ((desc->family < min_altera_type) || + (desc->family > max_altera_type)) { + printf("%s: Invalid family type, %d\n", fn, desc->family); + return false; + } + + if ((desc->iface < min_altera_iface_type) || + (desc->iface > max_altera_iface_type)) { + printf("%s: Invalid Interface type, %d\n", fn, desc->iface); + return false; + } + + if (!desc->size) { + printf("%s: NULL part size\n", fn); + return false; + } + + return true; +} /* ------------------------------------------------------------------------- */ int altera_load(Altera_desc *desc, const void *buf, size_t bsize) @@ -194,34 +219,3 @@ int altera_info(Altera_desc *desc) return ret_val; } - -/* ------------------------------------------------------------------------- */ - -static int altera_validate(Altera_desc *desc, const char *fn) -{ - if (!desc) { - printf("%s: NULL descriptor!\n", fn); - return false; - } - - if ((desc->family < min_altera_type) || - (desc->family > max_altera_type)) { - printf("%s: Invalid family type, %d\n", fn, desc->family); - return false; - } - - if ((desc->iface < min_altera_iface_type) || - (desc->iface > max_altera_iface_type)) { - printf("%s: Invalid Interface type, %d\n", fn, desc->iface); - return false; - } - - if (!desc->size) { - printf("%s: NULL part size\n", fn); - return false; - } - - return true; -} - -/* ------------------------------------------------------------------------- */ -- cgit v0.10.2 From fda915a4cf171f4ef3077adbc7bc1680a140b0d6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 20:33:54 +0200 Subject: fpga: altera: Make altera_validate return normal values Make the function return either 0 or -EINVAL, that is, normal expected error codes and success codes instead of true/false nonsense. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 9e9df50..941e7c8 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,38 +12,38 @@ * Altera FPGA support */ #include +#include #include #include /* Define FPGA_DEBUG to 1 to get debug printf's */ #define FPGA_DEBUG 0 -/* Local Static Functions */ static int altera_validate(Altera_desc *desc, const char *fn) { if (!desc) { printf("%s: NULL descriptor!\n", fn); - return false; + return -EINVAL; } if ((desc->family < min_altera_type) || (desc->family > max_altera_type)) { printf("%s: Invalid family type, %d\n", fn, desc->family); - return false; + return -EINVAL; } if ((desc->iface < min_altera_iface_type) || (desc->iface > max_altera_iface_type)) { printf("%s: Invalid Interface type, %d\n", fn, desc->iface); - return false; + return -EINVAL; } if (!desc->size) { printf("%s: NULL part size\n", fn); - return false; + return -EINVAL; } - return true; + return 0; } /* ------------------------------------------------------------------------- */ @@ -51,7 +51,7 @@ int altera_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate(desc, (char *)__func__)) { + if (altera_validate(desc, (char *)__func__)) { printf("%s: Invalid device descriptor\n", __func__); return FPGA_FAIL; } @@ -95,7 +95,7 @@ int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate (desc, (char *)__func__)) { + if (altera_validate(desc, (char *)__func__)) { printf("%s: Invalid device descriptor\n", __func__); return FPGA_FAIL; } @@ -133,7 +133,7 @@ int altera_info(Altera_desc *desc) { int ret_val = FPGA_FAIL; - if (!altera_validate (desc, (char *)__func__)) { + if (altera_validate (desc, (char *)__func__)) { printf("%s: Invalid device descriptor\n", __func__); return FPGA_FAIL; } -- cgit v0.10.2 From d44ef7ffbfef26f71d5811006f00fc82e941fe98 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 20:48:33 +0200 Subject: fpga: altera: Clean up enums in altera.h Get rid of the line-over-80 problems and zap the typedef that went alongside those enums. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/include/altera.h b/include/altera.h index ae5f7ee..e266a64 100644 --- a/include/altera.h +++ b/include/altera.h @@ -10,35 +10,57 @@ #ifndef _ALTERA_H_ #define _ALTERA_H_ -typedef enum { /* typedef Altera_iface */ - min_altera_iface_type, /* insert all new types after this */ - passive_serial, /* serial data and external clock */ - passive_parallel_synchronous, /* parallel data */ - passive_parallel_asynchronous, /* parallel data */ - passive_serial_asynchronous, /* serial data w/ internal clock (not used) */ - altera_jtag_mode, /* jtag/tap serial (not used ) */ - fast_passive_parallel, /* fast passive parallel (FPP) */ - fast_passive_parallel_security, /* fast passive parallel with security (FPPS) */ - max_altera_iface_type /* insert all new types before this */ -} Altera_iface; /* end, typedef Altera_iface */ +enum altera_iface { + /* insert all new types after this */ + min_altera_iface_type, + /* serial data and external clock */ + passive_serial, + /* parallel data */ + passive_parallel_synchronous, + /* parallel data */ + passive_parallel_asynchronous, + /* serial data w/ internal clock (not used) */ + passive_serial_asynchronous, + /* jtag/tap serial (not used ) */ + altera_jtag_mode, + /* fast passive parallel (FPP) */ + fast_passive_parallel, + /* fast passive parallel with security (FPPS) */ + fast_passive_parallel_security, + /* insert all new types before this */ + max_altera_iface_type, +}; -typedef enum { /* typedef Altera_Family */ - min_altera_type, /* insert all new types after this */ - Altera_ACEX1K, /* ACEX1K Family */ - Altera_CYC2, /* CYCLONII Family */ - Altera_StratixII, /* StratixII Family */ -/* Add new models here */ - max_altera_type /* insert all new types before this */ -} Altera_Family; /* end, typedef Altera_Family */ +enum altera_family { + /* insert all new types after this */ + min_altera_type, + /* ACEX1K Family */ + Altera_ACEX1K, + /* CYCLONII Family */ + Altera_CYC2, + /* StratixII Family */ + Altera_StratixII, -typedef struct { /* typedef Altera_desc */ - Altera_Family family; /* part type */ - Altera_iface iface; /* interface type */ - size_t size; /* bytes of data part can accept */ - void * iface_fns;/* interface function table */ - void * base; /* base interface address */ - int cookie; /* implementation specific cookie */ -} Altera_desc; /* end, typedef Altera_desc */ + /* Add new models here */ + + /* insert all new types before this */ + max_altera_type, +}; + +typedef struct { + /* part type */ + enum altera_family family; + /* interface type */ + enum altera_iface iface; + /* bytes of data part can accept */ + size_t size; + /* interface function table */ + void *iface_fns; + /* base interface address */ + void *base; + /* implementation specific cookie */ + int cookie; +} Altera_desc; /* Generic Altera Functions *********************************************************************/ -- cgit v0.10.2 From 2012f238bd4383904e898cfc26c9fd433af835aa Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 21:17:51 +0200 Subject: fpga: altera: Turn the switches into table lookup Add a table of FPGA family with matching functions associated with it and make all the code just look up the family in that table and call the associated function instead of the horrible switch voodoo which was duplicated all over the place. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 941e7c8..fd2b4f0 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -19,6 +19,26 @@ /* Define FPGA_DEBUG to 1 to get debug printf's */ #define FPGA_DEBUG 0 +static const struct altera_fpga { + enum altera_family family; + const char *name; + int (*load)(Altera_desc *, const void *, size_t); + int (*dump)(Altera_desc *, const void *, size_t); + int (*info)(Altera_desc *); +} altera_fpga[] = { +#if defined(CONFIG_FPGA_ACEX1K) + { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, + { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, +#elif defined(CONFIG_FPGA_CYCLON2) + { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, + { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, +#endif +#if defined(CONFIG_FPGA_STRATIX_II) + { Altera_StratixII, "StratixII", StratixII_load, + StratixII_dump, StratixII_info }, +#endif +}; + static int altera_validate(Altera_desc *desc, const char *fn) { if (!desc) { @@ -46,113 +66,65 @@ static int altera_validate(Altera_desc *desc, const char *fn) return 0; } -/* ------------------------------------------------------------------------- */ -int altera_load(Altera_desc *desc, const void *buf, size_t bsize) +static const struct altera_fpga * +altera_desc_to_fpga(Altera_desc *desc, const char *fn) { - int ret_val = FPGA_FAIL; /* assume a failure */ + int i; - if (altera_validate(desc, (char *)__func__)) { - printf("%s: Invalid device descriptor\n", __func__); - return FPGA_FAIL; + if (altera_validate(desc, fn)) { + printf("%s: Invalid device descriptor\n", fn); + return NULL; } - switch (desc->family) { - case Altera_ACEX1K: - case Altera_CYC2: -#if defined(CONFIG_FPGA_ACEX1K) - debug_cond(FPGA_DEBUG, - "%s: Launching the ACEX1K Loader...\n", - __func__); - ret_val = ACEX1K_load (desc, buf, bsize); -#elif defined(CONFIG_FPGA_CYCLON2) - debug_cond(FPGA_DEBUG, - "%s: Launching the CYCLONE II Loader...\n", - __func__); - ret_val = CYC2_load (desc, buf, bsize); -#else - printf("%s: No support for ACEX1K devices.\n", - __func__); -#endif - break; + for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) { + if (desc->family == altera_fpga[i].family) + break; + } -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - debug_cond(FPGA_DEBUG, - "%s: Launching the Stratix II Loader...\n", - __func__); - ret_val = StratixII_load (desc, buf, bsize); - break; -#endif - default: - printf("%s: Unsupported family type, %d\n", - __func__, desc->family); + if (i == ARRAY_SIZE(altera_fpga)) { + printf("%s: Unsupported family type, %d\n", fn, desc->family); + return NULL; } - return ret_val; + return &altera_fpga[i]; } -int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) +int altera_load(Altera_desc *desc, const void *buf, size_t bsize) { - int ret_val = FPGA_FAIL; /* assume a failure */ + const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); - if (altera_validate(desc, (char *)__func__)) { - printf("%s: Invalid device descriptor\n", __func__); + if (!fpga) return FPGA_FAIL; - } - switch (desc->family) { - case Altera_ACEX1K: -#if defined(CONFIG_FPGA_ACEX) - debug_cond(FPGA_DEBUG, - "%s: Launching the ACEX1K Reader...\n", - __func__); - ret_val = ACEX1K_dump (desc, buf, bsize); -#else - printf("%s: No support for ACEX1K devices.\n", - __func__); -#endif - break; + debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n", + __func__, fpga->name); + if (fpga->load) + return fpga->load(desc, buf, bsize); + return 0; +} -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - debug_cond(FPGA_DEBUG, - "%s: Launching the Stratix II Reader...\n", - __func__); - ret_val = StratixII_dump (desc, buf, bsize); - break; -#endif - default: - printf("%s: Unsupported family type, %d\n", - __func__, desc->family); - } +int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) +{ + const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); - return ret_val; + if (!fpga) + return FPGA_FAIL; + + debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n", + __func__, fpga->name); + if (fpga->dump) + return fpga->dump(desc, buf, bsize); + return 0; } int altera_info(Altera_desc *desc) { - int ret_val = FPGA_FAIL; + const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); - if (altera_validate (desc, (char *)__func__)) { - printf("%s: Invalid device descriptor\n", __func__); + if (!fpga) return FPGA_FAIL; - } - printf("Family: \t"); - switch (desc->family) { - case Altera_ACEX1K: - printf("ACEX1K\n"); - break; - case Altera_CYC2: - printf("CYCLON II\n"); - break; - case Altera_StratixII: - printf("Stratix II\n"); - break; - /* Add new family types here */ - default: - printf("Unknown family type, %d\n", desc->family); - } + printf("Family: \t%s\n", fpga->name); printf("Interface type:\t"); switch (desc->iface) { @@ -188,34 +160,11 @@ int altera_info(Altera_desc *desc) if (desc->iface_fns) { printf("Device Function Table @ 0x%p\n", desc->iface_fns); - switch (desc->family) { - case Altera_ACEX1K: - case Altera_CYC2: -#if defined(CONFIG_FPGA_ACEX1K) - ACEX1K_info(desc); -#elif defined(CONFIG_FPGA_CYCLON2) - CYC2_info(desc); -#else - /* just in case */ - printf("%s: No support for ACEX1K devices.\n", - __func__); -#endif - break; -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - StratixII_info(desc); - break; -#endif - /* Add new family types here */ - default: - /* we don't need a message here - we give one up above */ - break; - } + if (fpga->info) + fpga->info(desc); } else { printf("No Device Function Table.\n"); } - ret_val = FPGA_SUCCESS; - - return ret_val; + return FPGA_SUCCESS; } -- cgit v0.10.2 From f33c9305830d5f8b996a2aaea66591dc93143fe5 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Fri, 5 Sep 2014 12:49:48 +0200 Subject: mmc: dw_mmc: cleanups The dw_mmc driver was responding to errors with debug(). Change that to prinf()/puts() respectively so that any errors are immediately obvious. Also adjust english in comments. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Pantelis Antoniou Acked-by: Chin Liang See diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 0df30bc..785eed5 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -119,7 +119,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { if (get_timer(start) > timeout) { - printf("Timeout on data busy\n"); + printf("%s: Timeout on data busy\n", __func__); return TIMEOUT; } } @@ -177,14 +177,24 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } } - if (i == retry) + if (i == retry) { + printf("%s: Timeout.\n", __func__); return TIMEOUT; + } if (mask & DWMCI_INTMSK_RTO) { - debug("Response Timeout..\n"); + /* + * Timeout here is not necessarily fatal. (e)MMC cards + * will splat here when they receive CMD55 as they do + * not support this command and that is exactly the way + * to tell them apart from SD cards. Thus, this output + * below shall be debug(). eMMC cards also do not favor + * CMD8, please keep that in mind. + */ + debug("%s: Response Timeout.\n", __func__); return TIMEOUT; } else if (mask & DWMCI_INTMSK_RE) { - debug("Response Error..\n"); + printf("%s: Response Error.\n", __func__); return -1; } @@ -204,7 +214,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, do { mask = dwmci_readl(host, DWMCI_RINTSTS); if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { - debug("DATA ERROR!\n"); + printf("%s: DATA ERROR!\n", __func__); return -1; } } while (!(mask & DWMCI_INTMSK_DTO)); @@ -232,16 +242,16 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) if ((freq == host->clock) || (freq == 0)) return 0; /* - * If host->get_mmc_clk didn't define, + * If host->get_mmc_clk isn't defined, * then assume that host->bus_hz is source clock value. - * host->bus_hz should be set from user. + * host->bus_hz should be set by user. */ if (host->get_mmc_clk) sclk = host->get_mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { - printf("Didn't get source clock value..\n"); + printf("%s: Didn't get source clock value.\n", __func__); return -EINVAL; } @@ -260,7 +270,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { - printf("TIMEOUT error!!\n"); + printf("%s: Timeout!\n", __func__); return -ETIMEDOUT; } } while (status & DWMCI_CMD_START); @@ -275,7 +285,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { - printf("TIMEOUT error!!\n"); + printf("%s: Timeout!\n", __func__); return -ETIMEDOUT; } } while (status & DWMCI_CMD_START); @@ -290,7 +300,7 @@ static void dwmci_set_ios(struct mmc *mmc) struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 ctype, regs; - debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); + debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); dwmci_setup_bus(host, mmc->clock); switch (mmc->bus_width) { @@ -329,7 +339,7 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_PWREN, 1); if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { - debug("%s[%d] Fail-reset!!\n",__func__,__LINE__); + printf("%s[%d] Fail-reset!!\n", __func__, __LINE__); return -1; } -- cgit v0.10.2 From 1bf29b3d5571bed2b61581e839599337968deb80 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:18:15 +0200 Subject: mmc: dw_mmc: Fix cache alignment issue The DMA descriptors used by the DW MMC block must be aligned to cacheline size, otherwise we are unable to properly flush/inval cache over them and we get data corruption. The reason I chose this approach of expanding the structure is because the driver allocates the descriptors in bulk. This approach does waste space by inserting slop inbetween the descriptors, but it makes access to the descriptors easy as the compiler does know the real size of the structure. It also makes cache operations easy, since the size of the structure is cache aligned and the structure start address is as well. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Pantelis Antoniou Acked-by: Pavel Machek diff --git a/include/dwmmc.h b/include/dwmmc.h index b67f11b..109f7c8 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -157,7 +157,7 @@ struct dwmci_idmac { u32 cnt; u32 addr; u32 next_addr; -}; +} __aligned(ARCH_DMA_MINALIGN); static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) { -- cgit v0.10.2 From 464eec6d42cbdb5a57573d40ba64aad0e92aa689 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Tue, 9 Sep 2014 02:45:03 +0200 Subject: net: Remove unused CONFIG_DW_SEARCH_PHY from configs Remove this symbol from configs, since it's unused. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Joe Hershberger Acked-by: Chin Liang See diff --git a/include/configs/axs101.h b/include/configs/axs101.h index c22d6d0..1bf8390 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -125,7 +125,6 @@ */ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_AUTONEG -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI /* diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 5d145cd..39e9368 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -225,7 +225,6 @@ /* designware */ #define CONFIG_NET_MULTI #define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_DW_SEARCH_PHY #define CONFIG_MII #define CONFIG_PHY_GIGE #define CONFIG_DW_AUTONEG -- cgit v0.10.2 From 58ec63d6bcbe392ebed83197c90dc743f3b9e701 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Tue, 9 Sep 2014 14:26:51 +0200 Subject: net: phy: Cleanup drivers/net/phy/micrel.c Old saying says that more than three exclamation marks in a row are sign of mental disease. Cleanup micrel.c. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Joe Hershberger Acked-by: Chin Liang See diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 5d7e3be..507b9a3 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -25,8 +25,7 @@ static struct phy_driver KSZ804_driver = { #ifndef CONFIG_PHY_MICREL_KSZ9021 /* * I can't believe Micrel used the exact same part number - * for the KSZ9021 - * Shame Micrel, Shame!!!!! + * for the KSZ9021. Shame Micrel, Shame! */ static struct phy_driver KS8721_driver = { .name = "Micrel KS8721BL", @@ -40,7 +39,7 @@ static struct phy_driver KS8721_driver = { #endif -/** +/* * KSZ9021 - KSZ9031 common */ @@ -69,8 +68,8 @@ static int ksz90xx_startup(struct phy_device *phydev) phydev->speed = SPEED_10; return 0; } -#ifdef CONFIG_PHY_MICREL_KSZ9021 +#ifdef CONFIG_PHY_MICREL_KSZ9021 /* * KSZ9021 */ -- cgit v0.10.2 From 4f68678b1941af7d75f391d1189c776fb434dc08 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 00:50:37 +0200 Subject: net: dwc: Fix cache alignment issues Fix remaining cache alignment issues in the DWC Ethernet driver. Please note that the cache handling in the driver is making the code hideous and thus the next patch cleans that up. In order to make this change reviewable though, the cleanup is split from it. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Joe Hershberger Acked-by: Pavel Machek diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 7186e3b..aaf146d 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -303,7 +303,8 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) /* Flush data to be sent */ flush_dcache_range((unsigned long)desc_p->dmamac_addr, - (unsigned long)desc_p->dmamac_addr + length); + (unsigned long)desc_p->dmamac_addr + + roundup(length, ARCH_DMA_MINALIGN)); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; @@ -372,7 +373,8 @@ static int dw_eth_recv(struct eth_device *dev) /* Flush only status field - others weren't changed */ flush_dcache_range((unsigned long)&desc_p->txrx_status, (unsigned long)&desc_p->txrx_status + - sizeof(desc_p->txrx_status)); + roundup(sizeof(desc_p->txrx_status), + ARCH_DMA_MINALIGN)); /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_RX_DESCR_NUM) -- cgit v0.10.2 From 96cec17d3cd22ca2251d6f7946409933a231ce6f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:05:23 +0200 Subject: net: dwc: Make the cache handling less cryptic Add a few new variables to make the cache handling less cryptic. Add a variable for DMA and DATA descriptor start and end, so the correctness of the code is easier to inspect. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Joe Hershberger Acked-by: Pavel Machek Acked-by: Chin Liang See diff --git a/drivers/net/designware.c b/drivers/net/designware.c index aaf146d..9ded895 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -279,19 +279,21 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) struct eth_dma_regs *dma_p = priv->dma_regs_p; u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; - + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + uint32_t data_start = (uint32_t)desc_p->dmamac_addr; + uint32_t data_end = data_start + + roundup(length, ARCH_DMA_MINALIGN); /* * Strictly we only need to invalidate the "txrx_status" field * for the following check, but on some platforms we cannot - * invalidate only 4 bytes, so roundup to - * ARCH_DMA_MINALIGN. This is safe because the individual - * descriptors in the array are each aligned to - * ARCH_DMA_MINALIGN. + * invalidate only 4 bytes, so we flush the entire descriptor, + * which is 16 bytes in total. This is safe because the + * individual descriptors in the array are each aligned to + * ARCH_DMA_MINALIGN and padded appropriately. */ - invalidate_dcache_range( - (unsigned long)desc_p, - (unsigned long)desc_p + - roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN)); + invalidate_dcache_range(desc_start, desc_end); /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { @@ -299,12 +301,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) return -1; } - memcpy((void *)desc_p->dmamac_addr, packet, length); + memcpy(desc_p->dmamac_addr, packet, length); /* Flush data to be sent */ - flush_dcache_range((unsigned long)desc_p->dmamac_addr, - (unsigned long)desc_p->dmamac_addr + - roundup(length, ARCH_DMA_MINALIGN)); + flush_dcache_range(data_start, data_end); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; @@ -322,8 +322,7 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) #endif /* Flush modified buffer descriptor */ - flush_dcache_range((unsigned long)desc_p, - (unsigned long)desc_p + sizeof(struct dmamacdescr)); + flush_dcache_range(desc_start, desc_end); /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_TX_DESCR_NUM) @@ -343,11 +342,14 @@ static int dw_eth_recv(struct eth_device *dev) u32 status, desc_num = priv->rx_currdescnum; struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; int length = 0; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + uint32_t data_start = (uint32_t)desc_p->dmamac_addr; + uint32_t data_end; /* Invalidate entire buffer descriptor */ - invalidate_dcache_range((unsigned long)desc_p, - (unsigned long)desc_p + - sizeof(struct dmamacdescr)); + invalidate_dcache_range(desc_start, desc_end); status = desc_p->txrx_status; @@ -358,9 +360,8 @@ static int dw_eth_recv(struct eth_device *dev) DESC_RXSTS_FRMLENSHFT; /* Invalidate received data */ - invalidate_dcache_range((unsigned long)desc_p->dmamac_addr, - (unsigned long)desc_p->dmamac_addr + - roundup(length, ARCH_DMA_MINALIGN)); + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start, data_end); NetReceive(desc_p->dmamac_addr, length); @@ -371,10 +372,7 @@ static int dw_eth_recv(struct eth_device *dev) desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; /* Flush only status field - others weren't changed */ - flush_dcache_range((unsigned long)&desc_p->txrx_status, - (unsigned long)&desc_p->txrx_status + - roundup(sizeof(desc_p->txrx_status), - ARCH_DMA_MINALIGN)); + flush_dcache_range(desc_start, desc_end); /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_RX_DESCR_NUM) -- cgit v0.10.2 From 832472a94d1adb4f1f86e491a2387c43c960b4e2 Mon Sep 17 00:00:00 2001 From: Charles Manning Date: Thu, 6 Mar 2014 15:40:50 +1300 Subject: tools: socfpga: Add socfpga preloader signing to mkimage Like many platforms, the Altera socfpga platform requires that the preloader be "signed" in a certain way or the built-in boot ROM will not boot the code. This change automatically creates an appropriately signed preloader from an SPL image. The signed image includes a CRC which must, of course, be generated with a CRC generator that the SoCFPGA boot ROM agrees with otherwise the boot ROM will reject the image. Unfortunately the CRC used in this boot ROM is not the same as the Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a CRC but is more correctly described as a checksum. Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c. Signed-off-by: Charles Manning Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek V2: - Zap unused constant - Explicitly print an error message in case of error - Rework the hdr_checksum() function to take the *header directly instead of a plan buffer pointer diff --git a/common/image.c b/common/image.c index 38b56e3..085771c 100644 --- a/common/image.c +++ b/common/image.c @@ -138,6 +138,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",}, { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, + { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",}, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",}, { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",}, diff --git a/include/image.h b/include/image.h index 3401056..4347532 100644 --- a/include/image.h +++ b/include/image.h @@ -232,6 +232,7 @@ struct lmb; #define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */ #define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */ #define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */ +#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index 90e966d..2b05b20 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -87,6 +87,7 @@ dumpimage-mkimage-objs := aisimage.o \ os_support.o \ pblimage.o \ pbl_crc32.o \ + socfpgaimage.o \ lib/sha1.o \ lib/sha256.o \ ublimage.o \ diff --git a/tools/imagetool.c b/tools/imagetool.c index 32d6278..98717bd 100644 --- a/tools/imagetool.c +++ b/tools/imagetool.c @@ -47,6 +47,8 @@ void register_image_tool(imagetool_register_t image_register) init_ubl_image_type(); /* Init Davinci AIS support */ init_ais_image_type(); + /* Init Altera SOCFPGA support */ + init_socfpga_image_type(); /* Init TI Keystone boot image generation/list support */ init_gpimage_type(); } diff --git a/tools/imagetool.h b/tools/imagetool.h index c8af0e8..8bce059 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -168,6 +168,7 @@ void init_mxs_image_type(void); void init_fit_image_type(void); void init_ubl_image_type(void); void init_omap_image_type(void); +void init_socfpga_image_type(void); void init_gpimage_type(void); void pbl_load_uboot(int fd, struct image_tool_params *mparams); diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c new file mode 100644 index 0000000..396d8a5 --- /dev/null +++ b/tools/socfpgaimage.c @@ -0,0 +1,259 @@ +/* + * Copyright (C) 2014 Charles Manning + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Reference doc http://www.altera.com.cn/literature/hb/cyclone-v/cv_5400A.pdf + * Note this doc is not entirely accurate. Of particular interest to us is the + * "header" length field being in U32s and not bytes. + * + * "Header" is a structure of the following format. + * this is positioned at 0x40. + * + * Endian is LSB. + * + * Offset Length Usage + * ----------------------- + * 0x40 4 Validation word 0x31305341 + * 0x44 1 Version (whatever, zero is fine) + * 0x45 1 Flags (unused, zero is fine) + * 0x46 2 Length (in units of u32, including the end checksum). + * 0x48 2 Zero + * 0x4A 2 Checksum over the header. NB Not CRC32 + * + * At the end of the code we have a 32-bit CRC checksum over whole binary + * excluding the CRC. + * + * Note that the CRC used here is **not** the zlib/Adler crc32. It is the + * CRC-32 used in bzip2, ethernet and elsewhere. + * + * The image is padded out to 64k, because that is what is + * typically used to write the image to the boot medium. + */ + +#include "pbl_crc32.h" +#include "imagetool.h" +#include + +#define HEADER_OFFSET 0x40 +#define VALIDATION_WORD 0x31305341 +#define PADDED_SIZE 0x10000 + +/* To allow for adding CRC, the max input size is a bit smaller. */ +#define MAX_INPUT_SIZE (PADDED_SIZE - sizeof(uint32_t)) + +static uint8_t buffer[PADDED_SIZE]; + +static struct socfpga_header { + uint32_t validation; + uint8_t version; + uint8_t flags; + uint16_t length_u32; + uint16_t zero; + uint16_t checksum; +} header; + +/* + * The header checksum is just a very simple checksum over + * the header area. + * There is still a crc32 over the whole lot. + */ +static uint16_t hdr_checksum(struct socfpga_header *header) +{ + int len = sizeof(*header) - sizeof(header->checksum); + uint8_t *buf = (uint8_t *)header; + uint16_t ret = 0; + + while (--len) + ret += *buf++; + + return ret; +} + + +static void build_header(uint8_t *buf, uint8_t version, uint8_t flags, + uint16_t length_bytes) +{ + header.validation = htole32(VALIDATION_WORD); + header.version = version; + header.flags = flags; + header.length_u32 = htole16(length_bytes/4); + header.zero = 0; + header.checksum = htole16(hdr_checksum(&header)); + + memcpy(buf, &header, sizeof(header)); +} + +/* + * Perform a rudimentary verification of header and return + * size of image. + */ +static int verify_header(const uint8_t *buf) +{ + memcpy(&header, buf, sizeof(header)); + + if (le32toh(header.validation) != VALIDATION_WORD) + return -1; + if (le16toh(header.checksum) != hdr_checksum(&header)) + return -1; + + return le16toh(header.length_u32) * 4; +} + +/* Sign the buffer and return the signed buffer size */ +static int sign_buffer(uint8_t *buf, + uint8_t version, uint8_t flags, + int len, int pad_64k) +{ + uint32_t calc_crc; + + /* Align the length up */ + len = (len + 3) & (~3); + + /* Build header, adding 4 bytes to length to hold the CRC32. */ + build_header(buf + HEADER_OFFSET, version, flags, len + 4); + + /* Calculate and apply the CRC */ + calc_crc = ~pbl_crc32(0, (char *)buf, len); + + *((uint32_t *)(buf + len)) = htole32(calc_crc); + + if (!pad_64k) + return len + 4; + + return PADDED_SIZE; +} + +/* Verify that the buffer looks sane */ +static int verify_buffer(const uint8_t *buf) +{ + int len; /* Including 32bit CRC */ + uint32_t calc_crc; + uint32_t buf_crc; + + len = verify_header(buf + HEADER_OFFSET); + if (len < 0) { + fprintf(stderr, "Invalid header\n"); + return -1; + } + + if (len < HEADER_OFFSET || len > PADDED_SIZE) { + fprintf(stderr, "Invalid header length (%i)\n", len); + return -1; + } + + /* + * Adjust length to the base of the CRC. + * Check the CRC. + */ + len -= 4; + + calc_crc = ~pbl_crc32(0, (const char *)buf, len); + + buf_crc = le32toh(*((uint32_t *)(buf + len))); + + if (buf_crc != calc_crc) { + fprintf(stderr, "CRC32 does not match (%08x != %08x)\n", + buf_crc, calc_crc); + return -1; + } + + return 0; +} + +/* mkimage glue functions */ +static int socfpgaimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + if (image_size != PADDED_SIZE) + return -1; + + return verify_buffer(ptr); +} + +static void socfpgaimage_print_header(const void *ptr) +{ + if (verify_buffer(ptr) == 0) + printf("Looks like a sane SOCFPGA preloader\n"); + else + printf("Not a sane SOCFPGA preloader\n"); +} + +static int socfpgaimage_check_params(struct image_tool_params *params) +{ + /* Not sure if we should be accepting fflags */ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} + +static int socfpgaimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_SOCFPGAIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +/* + * To work in with the mkimage framework, we do some ugly stuff... + * + * First, socfpgaimage_vrec_header() is called. + * We prepend a fake header big enough to make the file PADDED_SIZE. + * This gives us enough space to do what we want later. + * + * Next, socfpgaimage_set_header() is called. + * We fix up the buffer by moving the image to the start of the buffer. + * We now have some room to do what we need (add CRC and padding). + */ + +static int data_size; +#define FAKE_HEADER_SIZE (PADDED_SIZE - data_size) + +static int socfpgaimage_vrec_header(struct image_tool_params *params, + struct image_type_params *tparams) +{ + struct stat sbuf; + + if (params->datafile && + stat(params->datafile, &sbuf) == 0 && + sbuf.st_size <= MAX_INPUT_SIZE) { + data_size = sbuf.st_size; + tparams->header_size = FAKE_HEADER_SIZE; + } + return 0; +} + +static void socfpgaimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + uint8_t *buf = (uint8_t *)ptr; + + /* + * This function is called after vrec_header() has been called. + * At this stage we have the FAKE_HEADER_SIZE dummy bytes followed by + * data_size image bytes. Total = PADDED_SIZE. + * We need to fix the buffer by moving the image bytes back to + * the beginning of the buffer, then actually do the signing stuff... + */ + memmove(buf, buf + FAKE_HEADER_SIZE, data_size); + memset(buf + data_size, 0, FAKE_HEADER_SIZE); + + sign_buffer(buf, 0, 0, data_size, 0); +} + +static struct image_type_params socfpgaimage_params = { + .name = "Altera SOCFPGA preloader support", + .vrec_header = socfpgaimage_vrec_header, + .header_size = 0, /* This will be modified by vrec_header() */ + .hdr = (void *)buffer, + .check_image_type = socfpgaimage_check_image_types, + .verify_header = socfpgaimage_verify_header, + .print_header = socfpgaimage_print_header, + .set_header = socfpgaimage_set_header, + .check_params = socfpgaimage_check_params, +}; + +void init_socfpga_image_type(void) +{ + register_image_type(&socfpgaimage_params); +} -- cgit v0.10.2 From ff7e9700eda14ccf8ebe399d3831ef266e743c2d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 02:44:36 +0200 Subject: arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index d51ba66..ca2d44f 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -185,6 +185,7 @@ enum dcache_option { DCACHE_OFF = 0x12, DCACHE_WRITETHROUGH = 0x1a, DCACHE_WRITEBACK = 0x1e, + DCACHE_WRITEALLOC = 0x16, }; /* Size of an MMU section */ diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 3e62d58..2155fe8 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -73,6 +73,8 @@ __weak void dram_bank_mmu_setup(int bank) i++) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) set_section_dcache(i, DCACHE_WRITETHROUGH); +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) + set_section_dcache(i, DCACHE_WRITEALLOC); #else set_section_dcache(i, DCACHE_WRITEBACK); #endif -- cgit v0.10.2 From e1f006f4384769d284530d71988d4c6dd17db4f4 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Tue, 9 Sep 2014 14:05:39 +0200 Subject: arm: socfpga: Complete the list of base addresses Add base addresses for all subsystems as documented in the Cyclone V HPS documentation. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Chin Liang See diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 2d3152d..cb062ac 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,16 +7,56 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 #define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 #define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 #define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 #define SOCFPGA_EMAC0_ADDRESS 0xff700000 #define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_STM_ADDRESS 0xfc000000 +#define SOCFPGA_DAP_ADDRESS 0xff000000 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_CAN0_ADDRESS 0xffc00000 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_ROM_ADDRESS 0xfffd0000 +#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ -- cgit v0.10.2 From be324354eebcd809bf539d2414c7c0a370847f26 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:44:39 +0200 Subject: arm: socfpga: Clean up base address file Sort the list of functional block addresses and fix indentation. No functional change. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek Acked-by: Chin Liang See diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index cb062ac..6534283 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,56 +7,56 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ -#define SOCFPGA_SDMMC_ADDRESS 0xff704000 -#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 -#define SOCFPGA_L3REGS_ADDRESS 0xff800000 -#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 -#define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_UART1_ADDRESS 0xffc03000 -#define SOCFPGA_SDR_ADDRESS 0xffc20000 -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 -#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 -#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 -#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 -#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 -#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 -#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 -#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 -#define SOCFPGA_EMAC0_ADDRESS 0xff700000 -#define SOCFPGA_EMAC1_ADDRESS 0xff702000 -#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 -#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 -#define SOCFPGA_STM_ADDRESS 0xfc000000 -#define SOCFPGA_DAP_ADDRESS 0xff000000 -#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 -#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 -#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 -#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 -#define SOCFPGA_QSPI_ADDRESS 0xff705000 -#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 -#define SOCFPGA_GPIO0_ADDRESS 0xff708000 -#define SOCFPGA_GPIO1_ADDRESS 0xff709000 -#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 -#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 -#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 -#define SOCFPGA_USB0_ADDRESS 0xffb00000 -#define SOCFPGA_USB1_ADDRESS 0xffb40000 -#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 -#define SOCFPGA_CAN0_ADDRESS 0xffc00000 -#define SOCFPGA_CAN1_ADDRESS 0xffc01000 -#define SOCFPGA_I2C0_ADDRESS 0xffc04000 -#define SOCFPGA_I2C1_ADDRESS 0xffc05000 -#define SOCFPGA_I2C2_ADDRESS 0xffc06000 -#define SOCFPGA_I2C3_ADDRESS 0xffc07000 -#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 -#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 -#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 -#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 -#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 -#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 -#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 -#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 -#define SOCFPGA_ROM_ADDRESS 0xfffd0000 -#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 +#define SOCFPGA_STM_ADDRESS 0xfc000000 +#define SOCFPGA_DAP_ADDRESS 0xff000000 +#define SOCFPGA_EMAC0_ADDRESS 0xff700000 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_CAN0_ADDRESS 0xffc00000 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 +#define SOCFPGA_ROM_ADDRESS 0xfffd0000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ -- cgit v0.10.2 From de6da9255ac4017e6bf6c98f533829a6eb67f3f6 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Tue, 9 Sep 2014 14:03:28 +0200 Subject: arm: socfpga: Add watchdog disable for socfpga This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default) diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index ecae393..b633615 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -36,6 +37,19 @@ int overwrite_console(void) } #endif +int arch_cpu_init(void) +{ + /* + * If the HW watchdog is NOT enabled, make sure it is not running, + * for example because it was enabled in the preloader. This might + * trigger a watchdog-triggered reboot of Linux kernel later. + */ +#ifndef CONFIG_HW_WATCHDOG + socfpga_watchdog_reset(); +#endif + return 0; +} + int misc_init_r(void) { return 0; diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index e320c01..5d7aba4 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -14,6 +14,18 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; +/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */ +void socfpga_watchdog_reset(void) +{ + /* assert reset for watchdog */ + setbits_le32(&reset_manager_base->per_mod_reset, + 1 << RSTMGR_PERMODRST_L4WD0_LSB); + + /* deassert watchdog from reset (watchdog in not running state) */ + clrbits_le32(&reset_manager_base->per_mod_reset, + 1 << RSTMGR_PERMODRST_L4WD0_LSB); +} + /* * Write the reset manager register to cause reset */ diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 3e95476..18506e6 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,8 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +void socfpga_watchdog_reset(void); + struct socfpga_reset_manager { u32 status; u32 ctrl; @@ -27,4 +29,6 @@ struct socfpga_reset_manager { #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 #endif +#define RSTMGR_PERMODRST_L4WD0_LSB 6 + #endif /* _RESET_MANAGER_H_ */ -- cgit v0.10.2 From 665e4caf02e4e835c5ec50d616512c6c7d99f1c0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: sysmgr: Clean up system manager Clean up the system manager register definition and add the missing register definitions in place. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c index d96521b..07c72e4 100644 --- a/arch/arm/cpu/armv7/socfpga/system_manager.c +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2013 Altera Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,21 +7,23 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + /* * Configure all the pin muxes */ void sysmgr_pinmux_init(void) { - unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET; - - const unsigned long *pval = sys_mgr_init_table; - unsigned long i; + uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0]; + int i; - for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); - i++, offset += sizeof(unsigned long)) { - writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset)); + for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) { + writel(sys_mgr_init_table[i], regs); + regs += sizeof(regs); } } diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index 838d210..90d2720 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2013 Altera Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,72 +16,122 @@ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; #endif - -#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400) - -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) - struct socfpga_system_manager { - u32 siliconid1; + /* System Manager Module */ + u32 siliconid1; /* 0x00 */ u32 siliconid2; u32 _pad_0x8_0xf[2]; - u32 wddbg; + u32 wddbg; /* 0x10 */ u32 bootinfo; u32 hpsinfo; u32 parityinj; - u32 fpgaintfgrp_gbl; + /* FPGA Interface Group */ + u32 fpgaintfgrp_gbl; /* 0x20 */ u32 fpgaintfgrp_indiv; u32 fpgaintfgrp_module; u32 _pad_0x2c_0x2f; - u32 scanmgrgrp_ctrl; + /* Scan Manager Group */ + u32 scanmgrgrp_ctrl; /* 0x30 */ u32 _pad_0x34_0x3f[3]; - u32 frzctrl_vioctrl; + /* Freeze Control Group */ + u32 frzctrl_vioctrl; /* 0x40 */ u32 _pad_0x44_0x4f[3]; - u32 frzctrl_hioctrl; + u32 frzctrl_hioctrl; /* 0x50 */ u32 frzctrl_src; u32 frzctrl_hwctrl; u32 _pad_0x5c_0x5f; - u32 emacgrp_ctrl; + /* EMAC Group */ + u32 emacgrp_ctrl; /* 0x60 */ u32 emacgrp_l3master; u32 _pad_0x68_0x6f[2]; - u32 dmagrp_ctrl; + /* DMA Controller Group */ + u32 dmagrp_ctrl; /* 0x70 */ u32 dmagrp_persecurity; u32 _pad_0x78_0x7f[2]; - u32 iswgrp_handoff[8]; - u32 _pad_0xa0_0xbf[8]; - u32 romcodegrp_ctrl; + /* Preloader (initial software) Group */ + u32 iswgrp_handoff[8]; /* 0x80 */ + u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ + /* Boot ROM Code Register Group */ + u32 romcodegrp_ctrl; /* 0xc0 */ u32 romcodegrp_cpu1startaddr; u32 romcodegrp_initswstate; u32 romcodegrp_initswlastld; - u32 romcodegrp_bootromswstate; + u32 romcodegrp_bootromswstate; /* 0xd0 */ u32 __pad_0xd4_0xdf[3]; - u32 romcodegrp_warmramgrp_enable; + /* Warm Boot from On-Chip RAM Group */ + u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ u32 romcodegrp_warmramgrp_datastart; u32 romcodegrp_warmramgrp_length; u32 romcodegrp_warmramgrp_execution; - u32 romcodegrp_warmramgrp_crc; + u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ u32 __pad_0xf4_0xff[3]; - u32 romhwgrp_ctrl; + /* Boot ROM Hardware Register Group */ + u32 romhwgrp_ctrl; /* 0x100 */ u32 _pad_0x104_0x107; + /* SDMMC Controller Group */ u32 sdmmcgrp_ctrl; u32 sdmmcgrp_l3master; - u32 nandgrp_bootstrap; + /* NAND Flash Controller Register Group */ + u32 nandgrp_bootstrap; /* 0x110 */ u32 nandgrp_l3master; + /* USB Controller Group */ u32 usbgrp_l3master; u32 _pad_0x11c_0x13f[9]; - u32 eccgrp_l2; + /* ECC Management Register Group */ + u32 eccgrp_l2; /* 0x140 */ u32 eccgrp_ocram; u32 eccgrp_usb0; u32 eccgrp_usb1; - u32 eccgrp_emac0; + u32 eccgrp_emac0; /* 0x150 */ u32 eccgrp_emac1; u32 eccgrp_dma; u32 eccgrp_can0; - u32 eccgrp_can1; + u32 eccgrp_can1; /* 0x160 */ u32 eccgrp_nand; u32 eccgrp_qspi; u32 eccgrp_sdmmc; + u32 _pad_0x170_0x3ff[164]; + /* Pin Mux Control Group */ + u32 emacio[20]; /* 0x400 */ + u32 flashio[12]; /* 0x450 */ + u32 generalio[28]; /* 0x480 */ + u32 _pad_0x4f0_0x4ff[4]; + u32 mixed1io[22]; /* 0x500 */ + u32 mixed2io[8]; /* 0x558 */ + u32 gplinmux[23]; /* 0x578 */ + u32 gplmux[71]; /* 0x5d4 */ + u32 nandusefpga; /* 0x6f0 */ + u32 _pad_0x6f4; + u32 rgmii1usefpga; /* 0x6f8 */ + u32 _pad_0x6fc_0x700[2]; + u32 i2c0usefpga; /* 0x704 */ + u32 sdmmcusefpga; /* 0x708 */ + u32 _pad_0x70c_0x710[2]; + u32 rgmii0usefpga; /* 0x714 */ + u32 _pad_0x718_0x720[3]; + u32 i2c3usefpga; /* 0x724 */ + u32 i2c2usefpga; /* 0x728 */ + u32 i2c1usefpga; /* 0x72c */ + u32 spim1usefpga; /* 0x730 */ + u32 _pad_0x734; + u32 spim0usefpga; /* 0x738 */ }; +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) +#define SYSMGR_ECC_OCRAM_EN (1 << 0) +#define SYSMGR_ECC_OCRAM_SERR (1 << 3) +#define SYSMGR_ECC_OCRAM_DERR (1 << 4) +#define SYSMGR_FPGAINTF_USEFPGA 0x1 +#define SYSMGR_FPGAINTF_SPIM0 (1 << 0) +#define SYSMGR_FPGAINTF_SPIM1 (1 << 1) +#define SYSMGR_FPGAINTF_EMAC0 (1 << 2) +#define SYSMGR_FPGAINTF_EMAC1 (1 << 3) +#define SYSMGR_FPGAINTF_NAND (1 << 4) +#define SYSMGR_FPGAINTF_SDMMC (1 << 5) + +/* FIXME: This is questionable macro. */ +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) + #endif /* _SYSTEM_MANAGER_H_ */ -- cgit v0.10.2 From 09f7e314e4d5eef939f97fa85424c9a31fc38119 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Sep 2014 07:21:16 +0200 Subject: arm: socfpga: clock: Implant order into bit definitions The bit definitions for clock manager are complete chaos. Implement some basic logical order into them. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index babac0e..dea171e 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -103,96 +103,128 @@ struct socfpga_clock_manager { u32 _pad_0xe0_0x200[72]; }; -#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 +#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 +#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001) + +#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010) +#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008) +#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004) +#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) + +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 +#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 + +/* Main PLL */ +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) +#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d + +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 -#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 -#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 -#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 + +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070) #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) + +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) + +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) + #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001) #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) -#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) -#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 + +/* Per PLL */ #define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) #define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) -#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) -#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \ - (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d + #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \ - (((x) << 0) & 0x000001ff) + +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff) + #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008) -#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007) -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) + +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 + #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0) #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 -#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 -#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) +#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007) + #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff) -#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010) -#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004) + +#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) +#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 -#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 -#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) + +/* SDR PLL */ +#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) + #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) + #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) + #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) + #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) #define MAIN_VCO_BASE \ (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \ -- cgit v0.10.2 From 4425e6285679a22522638bd4bb5281611635a30e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: clock: Drop nonsense inlining from clock manager code The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Scrub this hint. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Dinh Nguyen Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index 158501a..d032bbd 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -30,7 +30,7 @@ static const struct socfpga_clock_manager *clock_manager_base = CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) -static inline void cm_wait_for_lock(uint32_t mask) +static void cm_wait_for_lock(uint32_t mask) { register uint32_t inter_val; do { @@ -39,7 +39,7 @@ static inline void cm_wait_for_lock(uint32_t mask) } /* function to poll in the fsm busy bit */ -static inline void cm_wait_for_fsm(void) +static void cm_wait_for_fsm(void) { while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) ; @@ -49,22 +49,22 @@ static inline void cm_wait_for_fsm(void) * function to write the bypass register which requires a poll of the * busy bit */ -static inline void cm_write_bypass(uint32_t val) +static void cm_write_bypass(uint32_t val) { writel(val, &clock_manager_base->bypass); cm_wait_for_fsm(); } /* function to write the ctrl register which requires a poll of the busy bit */ -static inline void cm_write_ctrl(uint32_t val) +static void cm_write_ctrl(uint32_t val) { writel(val, &clock_manager_base->ctrl); cm_wait_for_fsm(); } /* function to write a clock register that has phase information */ -static inline void cm_write_with_phase(uint32_t value, - uint32_t reg_address, uint32_t mask) +static void cm_write_with_phase(uint32_t value, + uint32_t reg_address, uint32_t mask) { /* poll until phase is zero */ while (readl(reg_address) & mask) -- cgit v0.10.2 From 0911af00b09c065444e4f8842a67a11c0d9b03cd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Sep 2014 08:16:49 +0200 Subject: arm: socfpga: clock: Add missing stubs into board file Add some stub defines, which are used by the clock code, but are missing from the auto-generated header file for the SoCFPGA family. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Dinh Nguyen Acked-by: Pavel Machek diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h index 9bd0442..f0f59a9 100644 --- a/board/altera/socfpga/pll_config.h +++ b/board/altera/socfpga/pll_config.h @@ -94,6 +94,9 @@ /* Info for driver */ #define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ 0 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 #define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) #define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) #ifdef CONFIG_SOCFPGA_ARRIA5 -- cgit v0.10.2 From a832ddba55f79801b6f75b79e96c3f5e1469335a Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: clock: Add code to read clock configuration Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek V2: Fixed the L4 MP clock divider and synced the clock code with latest rocketboards codebase (thanks Dinh for pointing this out) diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index d032bbd..7a6b3b1 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -8,8 +8,10 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static const struct socfpga_clock_manager *clock_manager_base = - (void *)SOCFPGA_CLKMGR_ADDRESS; + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; #define CLKMGR_BYPASS_ENABLE 1 #define CLKMGR_BYPASS_DISABLE 0 @@ -358,3 +360,225 @@ void cm_basic_init(const cm_config_t *cfg) writel(~0, &clock_manager_base->per_pll.en); writel(~0, &clock_manager_base->sdr_pll.en); } + +unsigned long cm_get_mpu_clk_hz(void) +{ + uint32_t reg, clock; + + /* get the main VCO clock */ + reg = readl(&clock_manager_base->main_pll.vco); + clock = CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the MPU clock */ + reg = readl(&clock_manager_base->altera.mpuclk); + clock /= (reg + 1); + reg = readl(&clock_manager_base->main_pll.mpuclk); + clock /= (reg + 1); + return clock; +} + +unsigned long cm_get_sdram_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify SDRAM PLL clock source */ + reg = readl(&clock_manager_base->sdr_pll.vco); + reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg); + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ; + + /* get the SDRAM VCO clock */ + reg = readl(&clock_manager_base->sdr_pll.vco); + clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the SDRAM (DDR_DQS) clock */ + reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); + reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg); + clock /= (reg + 1); + + return clock; +} + +unsigned int cm_get_l4_sp_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify the source of L4 SP clock */ + reg = readl(&clock_manager_base->main_pll.l4src); + reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg); + + if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { + /* get the main VCO clock */ + reg = readl(&clock_manager_base->main_pll.vco); + clock = CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the clock prior L4 SP divider (main clk) */ + reg = readl(&clock_manager_base->altera.mainclk); + clock /= (reg + 1); + reg = readl(&clock_manager_base->main_pll.mainclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { + /* identify PER PLL clock source */ + reg = readl(&clock_manager_base->per_pll.vco); + reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + + /* get the PER VCO clock */ + reg = readl(&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(&clock_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); + } + + /* get the L4 SP clock which supplied to UART */ + reg = readl(&clock_manager_base->main_pll.maindiv); + reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg); + clock = clock / (1 << reg); + + return clock; +} + +unsigned int cm_get_mmc_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify the source of MMC clock */ + reg = readl(&clock_manager_base->per_pll.src); + reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg); + + if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) { + /* get the main VCO clock */ + reg = readl(&clock_manager_base->main_pll.vco); + clock = CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the SDMMC clock */ + reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { + /* identify PER PLL clock source */ + reg = readl(&clock_manager_base->per_pll.vco); + reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + + /* get the PER VCO clock */ + reg = readl(&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the SDMMC clock */ + reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); + clock /= (reg + 1); + } + + /* further divide by 4 as we have fixed divider at wrapper */ + clock /= 4; + return clock; +} + +unsigned int cm_get_qspi_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify the source of QSPI clock */ + reg = readl(&clock_manager_base->per_pll.src); + reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg); + + if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) { + /* get the main VCO clock */ + reg = readl(&clock_manager_base->main_pll.vco); + clock = CONFIG_HPS_CLK_OSC1_HZ / + (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the qspi clock */ + reg = readl(&clock_manager_base->main_pll.mainqspiclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { + /* identify PER PLL clock source */ + reg = readl(&clock_manager_base->per_pll.vco); + reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + + /* get the PER VCO clock */ + reg = readl(&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + + /* get the qspi clock */ + reg = readl(&clock_manager_base->per_pll.perqspiclk); + clock /= (reg + 1); + } + + return clock; +} + +static void cm_print_clock_quick_summary(void) +{ + printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); + printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000); + printf("EOSC1 %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000); + printf("EOSC2 %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000); + printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000); + printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000); + printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); + printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); + printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); +} + +int set_cpu_clk_info(void) +{ + /* Calculate the clock frequencies required for drivers */ + cm_get_l4_sp_clk_hz(); + cm_get_mmc_controller_clk_hz(); + + gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; + gd->bd->bi_dsp_freq = 0; + gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; + + return 0; +} + +int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cm_print_clock_quick_summary(); + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks, + "display clocks", + "" +); diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index dea171e..d2a9b48 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -7,6 +7,15 @@ #ifndef _CLOCK_MANAGER_H_ #define _CLOCK_MANAGER_H_ +#ifndef __ASSEMBLER__ +/* Clock speed accessors */ +unsigned long cm_get_mpu_clk_hz(void); +unsigned long cm_get_sdram_clk_hz(void); +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +#endif + typedef struct { /* main group */ uint32_t main_vco_base; @@ -89,6 +98,11 @@ struct socfpga_clock_manager_sdr_pll { u32 stat; }; +struct socfpga_clock_manager_altera { + u32 mpuclk; + u32 mainclk; +}; + struct socfpga_clock_manager { u32 ctrl; u32 bypass; @@ -100,7 +114,8 @@ struct socfpga_clock_manager { struct socfpga_clock_manager_main_pll main_pll; struct socfpga_clock_manager_per_pll per_pll; struct socfpga_clock_manager_sdr_pll sdr_pll; - u32 _pad_0xe0_0x200[72]; + struct socfpga_clock_manager_altera altera; + u32 _pad_0xe8_0x200[70]; }; #define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 @@ -118,8 +133,10 @@ struct socfpga_clock_manager { /* Main PLL */ #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) #define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) #define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) +#define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) #define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) @@ -148,7 +165,8 @@ struct socfpga_clock_manager { #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070) -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7) +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) @@ -156,16 +174,25 @@ struct socfpga_clock_manager { #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1) #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002) #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 +#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 +#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 /* Per PLL */ +#define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) #define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) #define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 #define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22) +#define CLKMGR_VCO_SSRC_EOSC1 0x0 +#define CLKMGR_VCO_SSRC_EOSC2 0x1 +#define CLKMGR_VCO_SSRC_F2S 0x2 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) @@ -191,12 +218,22 @@ struct socfpga_clock_manager { #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff) #define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) +#define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4) #define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0) #define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 +#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 +#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 +#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 +#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 +#define CLKMGR_QSPI_CLK_SRC_PER 0x2 /* SDR PLL */ +#define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) #define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) #define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) @@ -204,8 +241,10 @@ struct socfpga_clock_manager { #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22) #define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0) #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 39e9368..708309b 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -24,6 +24,7 @@ #define CONFIG_MISC_INIT_R #define CONFIG_SINGLE_BOOTLOADER #define CONFIG_SOCFPGA +#define CONFIG_CLOCKS /* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -- cgit v0.10.2 From 5d8ad0cd3a472f9eaa3b8c63b6ad5d889fce6183 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Sep 2014 08:27:16 +0200 Subject: arm: socfpga: clock: Trim down code duplication Pull out functions to read frequency of Main clock VCO and PLL clock VCO as the code is duplicated multiple times. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Dinh Nguyen Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index 7a6b3b1..ed2b419 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -361,7 +361,7 @@ void cm_basic_init(const cm_config_t *cfg) writel(~0, &clock_manager_base->sdr_pll.en); } -unsigned long cm_get_mpu_clk_hz(void) +static unsigned int cm_get_main_vco_clk_hz(void) { uint32_t reg, clock; @@ -371,6 +371,37 @@ unsigned long cm_get_mpu_clk_hz(void) (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + return clock; +} + +static unsigned int cm_get_per_vco_clk_hz(void) +{ + uint32_t reg, clock = 0; + + /* identify PER PLL clock source */ + reg = readl(&clock_manager_base->per_pll.vco); + reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = CONFIG_HPS_CLK_OSC1_HZ; + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = CONFIG_HPS_CLK_OSC2_HZ; + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; + + /* get the PER VCO clock */ + reg = readl(&clock_manager_base->per_pll.vco); + clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); + clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + + return clock; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + uint32_t reg, clock; + + clock = cm_get_main_vco_clk_hz(); + /* get the MPU clock */ reg = readl(&clock_manager_base->altera.mpuclk); clock /= (reg + 1); @@ -415,11 +446,7 @@ unsigned int cm_get_l4_sp_clk_hz(void) reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg); if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { - /* get the main VCO clock */ - reg = readl(&clock_manager_base->main_pll.vco); - clock = CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_main_vco_clk_hz(); /* get the clock prior L4 SP divider (main clk) */ reg = readl(&clock_manager_base->altera.mainclk); @@ -427,20 +454,7 @@ unsigned int cm_get_l4_sp_clk_hz(void) reg = readl(&clock_manager_base->main_pll.mainclk); clock /= (reg + 1); } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { - /* identify PER PLL clock source */ - reg = readl(&clock_manager_base->per_pll.vco); - reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); - if (reg == CLKMGR_VCO_SSRC_EOSC1) - clock = CONFIG_HPS_CLK_OSC1_HZ; - else if (reg == CLKMGR_VCO_SSRC_EOSC2) - clock = CONFIG_HPS_CLK_OSC2_HZ; - else if (reg == CLKMGR_VCO_SSRC_F2S) - clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; - - /* get the PER VCO clock */ - reg = readl(&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_per_vco_clk_hz(); /* get the clock prior L4 SP divider (periph_base_clk) */ reg = readl(&clock_manager_base->per_pll.perbaseclk); @@ -466,30 +480,13 @@ unsigned int cm_get_mmc_controller_clk_hz(void) if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) { - /* get the main VCO clock */ - reg = readl(&clock_manager_base->main_pll.vco); - clock = CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_main_vco_clk_hz(); /* get the SDMMC clock */ reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); clock /= (reg + 1); } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { - /* identify PER PLL clock source */ - reg = readl(&clock_manager_base->per_pll.vco); - reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); - if (reg == CLKMGR_VCO_SSRC_EOSC1) - clock = CONFIG_HPS_CLK_OSC1_HZ; - else if (reg == CLKMGR_VCO_SSRC_EOSC2) - clock = CONFIG_HPS_CLK_OSC2_HZ; - else if (reg == CLKMGR_VCO_SSRC_F2S) - clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; - - /* get the PER VCO clock */ - reg = readl(&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_per_vco_clk_hz(); /* get the SDMMC clock */ reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); @@ -512,30 +509,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void) if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) { - /* get the main VCO clock */ - reg = readl(&clock_manager_base->main_pll.vco); - clock = CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_main_vco_clk_hz(); /* get the qspi clock */ reg = readl(&clock_manager_base->main_pll.mainqspiclk); clock /= (reg + 1); } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { - /* identify PER PLL clock source */ - reg = readl(&clock_manager_base->per_pll.vco); - reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); - if (reg == CLKMGR_VCO_SSRC_EOSC1) - clock = CONFIG_HPS_CLK_OSC1_HZ; - else if (reg == CLKMGR_VCO_SSRC_EOSC2) - clock = CONFIG_HPS_CLK_OSC2_HZ; - else if (reg == CLKMGR_VCO_SSRC_F2S) - clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; - - /* get the PER VCO clock */ - reg = readl(&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = cm_get_per_vco_clk_hz(); /* get the qspi clock */ reg = readl(&clock_manager_base->per_pll.perqspiclk); -- cgit v0.10.2 From 44428ab6abbba58aa90b982d4d41b39cbcbec966 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 17:21:00 +0200 Subject: arm: socfpga: clock: Clean up bit definitions Clean up the clock code definitions so they are aligned with mainline standards. There are no functional changes in this patch. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index ed2b419..1cf0d77 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -13,25 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_clock_manager *clock_manager_base = (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; -#define CLKMGR_BYPASS_ENABLE 1 -#define CLKMGR_BYPASS_DISABLE 0 -#define CLKMGR_STAT_IDLE 0 -#define CLKMGR_STAT_BUSY 1 -#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0 -#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1 -#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0 -#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1 - -#define CLEAR_BGP_EN_PWRDN \ - (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) - -#define VCO_EN_BASE \ - (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ - CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ - CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) - static void cm_wait_for_lock(uint32_t mask) { register uint32_t inter_val; @@ -130,14 +111,8 @@ void cm_basic_init(const cm_config_t *cfg) writel(0, &clock_manager_base->per_pll.en); /* Put all plls in bypass */ - cm_write_bypass( - CLKMGR_BYPASS_PERPLLSRC_SET( - CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_SDRPLLSRC_SET( - CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) | - CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) | - CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE)); + cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | + CLKMGR_BYPASS_MAINPLL); /* * Put all plls VCO registers back to reset value. @@ -172,19 +147,14 @@ void cm_basic_init(const cm_config_t *cfg) * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. */ - writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN | - CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->main_pll.vco); - - writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN | - CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->per_pll.vco); - - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | - cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN | - CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->sdr_pll.vco); + writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->main_pll.vco); + + writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->per_pll.vco); + + writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->sdr_pll.vco); /* * Time starts here @@ -234,18 +204,16 @@ void cm_basic_init(const cm_config_t *cfg) /* Enable vco */ /* main pll vco */ - writel(cfg->main_vco_base | VCO_EN_BASE, + writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, &clock_manager_base->main_pll.vco); /* periferal pll */ - writel(cfg->peri_vco_base | VCO_EN_BASE, + writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, &clock_manager_base->per_pll.vco); /* sdram pll vco */ - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | - cfg->sdram_vco_base | VCO_EN_BASE, - &clock_manager_base->sdr_pll.vco); + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->sdr_pll.vco); /* L3 MP and L3 SP */ writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); @@ -296,8 +264,8 @@ void cm_basic_init(const cm_config_t *cfg) &clock_manager_base->per_pll.vco); /* assert sdram outresetall */ - writel(cfg->sdram_vco_base | VCO_EN_BASE| - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1), + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN| + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, &clock_manager_base->sdr_pll.vco); /* deassert main outresetall */ @@ -309,9 +277,8 @@ void cm_basic_init(const cm_config_t *cfg) &clock_manager_base->per_pll.vco); /* deassert sdram outresetall */ - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | - cfg->sdram_vco_base | VCO_EN_BASE, - &clock_manager_base->sdr_pll.vco); + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->sdr_pll.vco); /* * now that we've toggled outreset all, all the clocks @@ -335,18 +302,10 @@ void cm_basic_init(const cm_config_t *cfg) CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); /* Take all three PLLs out of bypass when safe mode is cleared. */ - cm_write_bypass( - CLKMGR_BYPASS_PERPLLSRC_SET( - CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_SDRPLLSRC_SET( - CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | - CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) | - CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) | - CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE)); + cm_write_bypass(0); /* clear safe mode */ - cm_write_ctrl(readl(&clock_manager_base->ctrl) | - CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK)); + cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); /* * now that safe mode is clear with clocks gated @@ -367,9 +326,11 @@ static unsigned int cm_get_main_vco_clk_hz(void) /* get the main VCO clock */ reg = readl(&clock_manager_base->main_pll.vco); - clock = CONFIG_HPS_CLK_OSC1_HZ / - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1); + clock = CONFIG_HPS_CLK_OSC1_HZ; + clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1; return clock; } @@ -380,7 +341,8 @@ static unsigned int cm_get_per_vco_clk_hz(void) /* identify PER PLL clock source */ reg = readl(&clock_manager_base->per_pll.vco); - reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg); + reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> + CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET; if (reg == CLKMGR_VCO_SSRC_EOSC1) clock = CONFIG_HPS_CLK_OSC1_HZ; else if (reg == CLKMGR_VCO_SSRC_EOSC2) @@ -390,8 +352,10 @@ static unsigned int cm_get_per_vco_clk_hz(void) /* get the PER VCO clock */ reg = readl(&clock_manager_base->per_pll.vco); - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1); + clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1; return clock; } @@ -416,7 +380,8 @@ unsigned long cm_get_sdram_clk_hz(void) /* identify SDRAM PLL clock source */ reg = readl(&clock_manager_base->sdr_pll.vco); - reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg); + reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >> + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET; if (reg == CLKMGR_VCO_SSRC_EOSC1) clock = CONFIG_HPS_CLK_OSC1_HZ; else if (reg == CLKMGR_VCO_SSRC_EOSC2) @@ -426,12 +391,15 @@ unsigned long cm_get_sdram_clk_hz(void) /* get the SDRAM VCO clock */ reg = readl(&clock_manager_base->sdr_pll.vco); - clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1); - clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1); + clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1; /* get the SDRAM (DDR_DQS) clock */ reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); - reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg); + reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; clock /= (reg + 1); return clock; @@ -443,7 +411,8 @@ unsigned int cm_get_l4_sp_clk_hz(void) /* identify the source of L4 SP clock */ reg = readl(&clock_manager_base->main_pll.l4src); - reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg); + reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >> + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET; if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { clock = cm_get_main_vco_clk_hz(); @@ -463,7 +432,8 @@ unsigned int cm_get_l4_sp_clk_hz(void) /* get the L4 SP clock which supplied to UART */ reg = readl(&clock_manager_base->main_pll.maindiv); - reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg); + reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET; clock = clock / (1 << reg); return clock; @@ -475,7 +445,8 @@ unsigned int cm_get_mmc_controller_clk_hz(void) /* identify the source of MMC clock */ reg = readl(&clock_manager_base->per_pll.src); - reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg); + reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET; if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; @@ -504,7 +475,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void) /* identify the source of QSPI clock */ reg = readl(&clock_manager_base->per_pll.src); - reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg); + reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >> + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET; if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 27efde6..bd9f338 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -19,6 +19,31 @@ DECLARE_GLOBAL_DATA_PTR; +#define MAIN_VCO_BASE ( \ + (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \ + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \ + ) + +#define PERI_VCO_BASE ( \ + (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \ + CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \ + (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \ + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \ + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \ + ) + +#define SDR_VCO_BASE ( \ + (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \ + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \ + (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \ + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \ + (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \ + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ + ) + u32 spl_boot_device(void) { return BOOT_DEVICE_RAM; @@ -33,86 +58,87 @@ void spl_board_init(void) cm_config_t cm_default_cfg = { /* main group */ MAIN_VCO_BASE, - CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT), - CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT), - CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT), - CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT), - CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT), - CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET( - CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT), - CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) | - CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) | - CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) | - CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET( - CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK), - CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET( - CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) | - CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET( - CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK), - CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET( - CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK), - CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET( - CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) | - CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET( - CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP), + (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT << + CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT << + CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT << + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT << + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT << + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT << + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET), + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK << + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK << + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK << + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK << + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET), + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP << + CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) | + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP << + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET), /* peripheral group */ PERI_VCO_BASE, - CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT), - CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT), - CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT), - CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT), - CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT), - CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET( - CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT), - CLKMGR_PERPLLGRP_DIV_USBCLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_USBCLK) | - CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) | - CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) | - CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET( - CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK), - CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET( - CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK), - CLKMGR_PERPLLGRP_SRC_QSPI_SET( - CONFIG_HPS_PERPLLGRP_SRC_QSPI) | - CLKMGR_PERPLLGRP_SRC_NAND_SET( - CONFIG_HPS_PERPLLGRP_SRC_NAND) | - CLKMGR_PERPLLGRP_SRC_SDMMC_SET( - CONFIG_HPS_PERPLLGRP_SRC_SDMMC), + (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT << + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT << + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT << + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT << + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT << + CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT << + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET), + (CONFIG_HPS_PERPLLGRP_DIV_USBCLK << + CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK << + CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK << + CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) | + (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK << + CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET), + (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK << + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET), + (CONFIG_HPS_PERPLLGRP_SRC_QSPI << + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) | + (CONFIG_HPS_PERPLLGRP_SRC_NAND << + CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) | + (CONFIG_HPS_PERPLLGRP_SRC_SDMMC << + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET), /* sdram pll group */ SDR_VCO_BASE, - CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) | - CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT), - CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) | - CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT), - CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) | - CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT), - CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET( - CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) | - CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET( - CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT), + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE << + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT << + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE << + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT << + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE << + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT << + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET), + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE << + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET), + }; debug("Freezing all I/O banks\n"); diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index d2a9b48..bc91662 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -118,165 +118,187 @@ struct socfpga_clock_manager { u32 _pad_0xe8_0x200[70]; }; -#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 -#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001) - -#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010) -#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008) -#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004) -#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) - -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 -#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 +#define CLKMGR_CTRL_SAFEMODE (1 << 0) +#define CLKMGR_CTRL_SAFEMODE_OFFSET 0 + +#define CLKMGR_BYPASS_PERPLLSRC (1 << 4) +#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 +#define CLKMGR_BYPASS_PERPLL (1 << 3) +#define CLKMGR_BYPASS_PERPLL_OFFSET 3 +#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2) +#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 +#define CLKMGR_BYPASS_SDRPLL (1 << 1) +#define CLKMGR_BYPASS_SDRPLL_OFFSET 1 +#define CLKMGR_BYPASS_MAINPLL (1 << 0) +#define CLKMGR_BYPASS_MAINPLL_OFFSET 0 + +#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 + +#define CLKMGR_STAT_BUSY (1 << 0) /* Main PLL */ -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) -#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) -#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) -#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d - -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 -#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 -#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 -#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 -#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 -#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 - -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070) -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7) -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) - -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) - -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) - -#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1) -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 -#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 -#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0) +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1) +#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2) +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d + +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 +#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 +#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 + +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 + +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c + +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 + +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0) +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1) +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 +#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 +#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 /* Per PLL */ -#define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) -#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) -#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) -#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22) -#define CLKMGR_VCO_SSRC_EOSC1 0x0 -#define CLKMGR_VCO_SSRC_EOSC2 0x1 -#define CLKMGR_VCO_SSRC_F2S 0x2 - -#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) - -#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 -#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 - -#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0) -#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) -#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007) - -#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff) - -#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4) -#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) -#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 -#define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0) -#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 -#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 -#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 -#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 -#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 -#define CLKMGR_QSPI_CLK_SRC_PER 0x2 +#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 +#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 +#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 + +#define CLKMGR_VCO_SSRC_EOSC1 0x0 +#define CLKMGR_VCO_SSRC_EOSC2 0x1 +#define CLKMGR_VCO_SSRC_F2S 0x2 + +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 + +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 + +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff + +#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 +#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c +#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 +#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 +#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 +#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 +#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 +#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 +#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 +#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 +#define CLKMGR_QSPI_CLK_SRC_PER 0x2 /* SDR PLL */ -#define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16) -#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3) -#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) -#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22) -#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) - -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) - -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) - -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) - -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) - -#define MAIN_VCO_BASE \ - (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \ - CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER)) - -#define PERI_VCO_BASE \ - (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \ - CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \ - CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER)) - -#define SDR_VCO_BASE \ - (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \ - CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \ - CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER)) +#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 +#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 +#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 + +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 #endif /* _CLOCK_MANAGER_H_ */ -- cgit v0.10.2 From 036ba54f5b713f60c17c4a28e4ad4d59fa913db9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Sep 2014 19:54:32 +0200 Subject: arm: socfpga: clock: Sync with reference code Add the missing pieces from the reference clock code from Altera. This puts the code on par with the Altera U-Boot fork for all but the SDRAM self-refresh bits, which are not part of this patch. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index 1cf0d77..d869f47 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -16,9 +16,16 @@ static const struct socfpga_clock_manager *clock_manager_base = static void cm_wait_for_lock(uint32_t mask) { register uint32_t inter_val; + uint32_t retry = 0; do { inter_val = readl(&clock_manager_base->inter) & mask; - } while (inter_val != mask); + if (inter_val == mask) + retry++; + else + retry = 0; + if (retry >= 10) + break; + } while (1); } /* function to poll in the fsm busy bit */ @@ -114,15 +121,15 @@ void cm_basic_init(const cm_config_t *cfg) cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | CLKMGR_BYPASS_MAINPLL); - /* - * Put all plls VCO registers back to reset value. - * Some code might have messed with them. - */ - writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE, + /* Put all plls VCO registers back to reset value. */ + writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, &clock_manager_base->main_pll.vco); - writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE, + writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, &clock_manager_base->per_pll.vco); - writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE, + writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, &clock_manager_base->sdr_pll.vco); /* @@ -147,14 +154,9 @@ void cm_basic_init(const cm_config_t *cfg) * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. */ - writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->main_pll.vco); - - writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->per_pll.vco); - - writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->sdr_pll.vco); + writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); + writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); + writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); /* * Time starts here @@ -189,6 +191,9 @@ void cm_basic_init(const cm_config_t *cfg) writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); /* Peri pernandsdmmcclk */ + writel(cfg->mainnandsdmmcclk, + &clock_manager_base->main_pll.mainnandsdmmcclk); + writel(cfg->pernandsdmmcclk, &clock_manager_base->per_pll.pernandsdmmcclk); @@ -318,6 +323,11 @@ void cm_basic_init(const cm_config_t *cfg) writel(~0, &clock_manager_base->main_pll.en); writel(~0, &clock_manager_base->per_pll.en); writel(~0, &clock_manager_base->sdr_pll.en); + + /* Clear the loss of lock bits (write 1 to clear) */ + writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK, + &clock_manager_base->inter); } static unsigned int cm_get_main_vco_clk_hz(void) diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index bc91662..fa49f6a 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -135,6 +135,9 @@ struct socfpga_clock_manager { #define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010 +#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008 #define CLKMGR_STAT_BUSY (1 << 0) -- cgit v0.10.2 From 498d1a62db4374c9d6223771bcbe8ae612a0f59f Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: mmc: Pick the clock from clock manager Make the SoCFPGA MMC stub pick clock via the clock manager frequency accessors instead of hard-coding the frequency. Also fix calloc() misuse. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Dinh Nguyen diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 1f96382..eb69aed 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -44,12 +45,18 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) { struct dwmci_host *host; + unsigned long clk = cm_get_mmc_controller_clk_hz(); + + if (clk == 0) { + printf("%s: MMC clock is zero!", __func__); + return -EINVAL; + } /* calloc for zero init */ - host = calloc(sizeof(struct dwmci_host), 1); + host = calloc(1, sizeof(struct dwmci_host)); if (!host) { - printf("dwmci_host calloc fail!\n"); - return -1; + printf("%s: calloc() failed!\n", __func__); + return -ENOMEM; } host->name = "SOCFPGA DWMMC"; @@ -58,7 +65,7 @@ int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) host->clksel = socfpga_dwmci_clksel; host->dev_index = index; /* fixed clock divide by 4 which due to the SDMMC wrapper */ - host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ; + host->bus_hz = clk; host->fifoth_val = MSIZE(0x2) | RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) | TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2); -- cgit v0.10.2 From 2110eeaf0fdf9b3b200076554d266459ca7ac26d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: timer: Pull the timer reload value from config file The timer reload value is a property of the timer hardware and there is no reason for this to be configurable. Place this into the timer driver just like on the other hardware. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Dinh Nguyen Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c index 58fc789..253cde3 100644 --- a/arch/arm/cpu/armv7/socfpga/timer.c +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -8,6 +8,8 @@ #include #include +#define TIMER_LOAD_VAL 0xFFFFFFFF + static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; /* diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 708309b..54343b8 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -195,8 +195,6 @@ /* This timer use eosc1 where the clock frequency is fixed * throughout any condition */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -/* reload value when timer count to zero */ -#define TIMER_LOAD_VAL 0xFFFFFFFF /* Timer info */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TIMER_RATE 2400000 -- cgit v0.10.2 From e9d6a20034788258bc5008dc2665aabe9ce28b1c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: reset: Add EMAC reset functions Add functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 5d7aba4..badc569 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -49,3 +49,20 @@ void reset_deassert_peripherals_handoff(void) { writel(0, &reset_manager_base->per_mod_reset); } + +/* Change the reset state for EMAC 0 and EMAC 1 */ +void socfpga_emac_reset(int enable) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + if (enable) { + setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); + setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); + } else { +#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS) + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); +#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS) + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); +#endif + } +} diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 18506e6..3c5ab40 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,7 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); struct socfpga_reset_manager { @@ -29,6 +30,8 @@ struct socfpga_reset_manager { #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 #endif +#define RSTMGR_PERMODRST_EMAC0_LSB 0 +#define RSTMGR_PERMODRST_EMAC1_LSB 1 #define RSTMGR_PERMODRST_L4WD0_LSB 6 #endif /* _RESET_MANAGER_H_ */ -- cgit v0.10.2 From 45d6e677106703139d2e3c10fa2d1168fb25309e Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: misc: Add proper ethernet initialization Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index b633615..872ea59 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -9,15 +9,58 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_DESIGNWARE_ETH +int cpu_eth_init(bd_t *bis) +{ +#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS + const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; +#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS + const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; +#else +#error "Incorrect CONFIG_EMAC_BASE value!" +#endif + + /* Initialize EMAC. This needs to be done at least once per boot. */ + + /* + * Putting the EMAC controller to reset when configuring the PHY + * interface select at System Manager + */ + socfpga_emac_reset(1); + + /* Clearing emac0 PHY interface select to 0 */ + clrbits_le32(&sysmgr_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); + + /* configure to PHY interface select choosed */ + setbits_le32(&sysmgr_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); + + /* Release the EMAC controller from reset */ + socfpga_emac_reset(0); + + /* initialize and register the emac */ + return designware_initialize(CONFIG_EMAC_BASE, + CONFIG_PHY_INTERFACE_MODE); +} +#endif + #if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information @@ -54,18 +97,3 @@ int misc_init_r(void) { return 0; } - - -/* - * DesignWare Ethernet initialization - */ -int cpu_eth_init(bd_t *bis) -{ -#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD) - /* initialize and register the emac */ - return designware_initialize(CONFIG_EMAC_BASE, - CONFIG_PHY_INTERFACE_MODE); -#else - return 0; -#endif -} diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index 90d2720..071ec4f 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -134,4 +134,13 @@ struct socfpga_system_manager { #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) +/* EMAC Group Bit definitions */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 + #endif /* _SYSTEM_MANAGER_H_ */ -- cgit v0.10.2 From 4e736869c6e0df7a955fd000681d6ceea636928c Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: misc: Add SD controller init Add CPU function to register and initialize the dw_mmc SD controller. This allows us to use the HPS SDMMC block. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 872ea59..bf5c668 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -10,6 +10,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -61,6 +62,18 @@ int cpu_eth_init(bd_t *bis) } #endif +#ifdef CONFIG_DWMMC +/* + * Initializes MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ + return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, + CONFIG_HPS_SDMMC_BUSWIDTH, 0); +} +#endif + #if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information -- cgit v0.10.2 From d5a3d3c9efc2738139b8b8a7c191b8b0d533aaa8 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: misc: Align print_cpuinfo() output Cosmetic change to the print_cpuinfo() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index bf5c668..f41c329 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -80,7 +80,7 @@ int cpu_mmc_init(bd_t *bis) */ int print_cpuinfo(void) { - puts("CPU : Altera SOCFPGA Platform\n"); + puts("CPU: Altera SoCFPGA Platform\n"); return 0; } #endif -- cgit v0.10.2 From 868749a61dcc29456c8b06748b6130de4940369b Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: board: Correctly set ATAG position The bi_boot_params must point to offset 0x100 in DRAM. Make it so. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index fb92852..bc8a87c 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -35,5 +35,9 @@ int board_early_init_f(void) int board_init(void) { icache_enable(); + + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + return 0; } -- cgit v0.10.2 From 604364e42cf7dd3c4980901b47ee47eb4b490e4b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: board: Align checkboard() output Cosmetic change to the checkboard() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index bc8a87c..4149842 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; */ int checkboard(void) { - puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + puts("BOARD: Altera SoCFPGA Cyclone5 Board\n"); return 0; } -- cgit v0.10.2 From 230fe9b202ff0ca396ad9a564816cc87d42daa6e Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: fpga: Add SoCFPGA FPGA programming interface Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support. diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index eb33f2c..8b6e108 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -8,5 +8,6 @@ # obj-y := lowlevel_init.o -obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o +obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ + fpga_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/fpga_manager.c b/arch/arm/cpu/armv7/socfpga/fpga_manager.c new file mode 100644 index 0000000..43fd2fe --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/fpga_manager.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2012 Altera Corporation + * All rights reserved. + * + * This file contains only support functions used also by the SoCFPGA + * platform code, the real meat is located in drivers/fpga/socfpga.c . + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Timeout count */ +#define FPGA_TIMEOUT_CNT 0x1000000 + +static struct socfpga_fpga_manager *fpgamgr_regs = + (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; + +/* Check whether FPGA Init_Done signal is high */ +static int is_fpgamgr_initdone_high(void) +{ + unsigned long val; + + val = readl(&fpgamgr_regs->gpio_ext_porta); + return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK; +} + +/* Get the FPGA mode */ +int fpgamgr_get_mode(void) +{ + unsigned long val; + + val = readl(&fpgamgr_regs->stat); + return val & FPGAMGRREGS_STAT_MODE_MASK; +} + +/* Check whether FPGA is ready to be accessed */ +int fpgamgr_test_fpga_ready(void) +{ + /* Check for init done signal */ + if (!is_fpgamgr_initdone_high()) + return 0; + + /* Check again to avoid false glitches */ + if (!is_fpgamgr_initdone_high()) + return 0; + + if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE) + return 0; + + return 1; +} + +/* Poll until FPGA is ready to be accessed or timeout occurred */ +int fpgamgr_poll_fpga_ready(void) +{ + unsigned long i; + + /* If FPGA is blank, wait till WD invoke warm reset */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + /* check for init done signal */ + if (!is_fpgamgr_initdone_high()) + continue; + /* check again to avoid false glitches */ + if (!is_fpgamgr_initdone_high()) + continue; + return 1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index f41c329..b07d97e 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -93,6 +94,39 @@ int overwrite_console(void) } #endif +#ifdef CONFIG_FPGA +/* + * FPGA programming support for SoC FPGA Cyclone V + */ +static Altera_desc altera_fpga[] = { + { + /* Family */ + Altera_SoCFPGA, + /* Interface type */ + fast_passive_parallel, + /* No limitation as additional data will be ignored */ + -1, + /* No device function table */ + NULL, + /* Base interface address specified in driver */ + NULL, + /* No cookie implementation */ + 0 + }, +}; + +/* add device descriptor to FPGA device table */ +static void socfpga_fpga_add(void) +{ + int i; + fpga_init(); + for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) + fpga_add(fpga_altera, &altera_fpga[i]); +} +#else +static inline void socfpga_fpga_add(void) {} +#endif + int arch_cpu_init(void) { /* @@ -108,5 +142,7 @@ int arch_cpu_init(void) int misc_init_r(void) { + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); return 0; } diff --git a/arch/arm/include/asm/arch-socfpga/fpga_manager.h b/arch/arm/include/asm/arch-socfpga/fpga_manager.h new file mode 100644 index 0000000..a077e22 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/fpga_manager.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2012 Altera Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FPGA_MANAGER_H_ +#define _FPGA_MANAGER_H_ + +#include + +struct socfpga_fpga_manager { + /* FPGA Manager Module */ + u32 stat; /* 0x00 */ + u32 ctrl; + u32 dclkcnt; + u32 dclkstat; + u32 gpo; /* 0x10 */ + u32 gpi; + u32 misci; /* 0x18 */ + u32 _pad_0x1c_0x82c[517]; + + /* Configuration Monitor (MON) Registers */ + u32 gpio_inten; /* 0x830 */ + u32 gpio_intmask; + u32 gpio_inttype_level; + u32 gpio_int_polarity; + u32 gpio_intstatus; /* 0x840 */ + u32 gpio_raw_intstatus; + u32 _pad_0x848; + u32 gpio_porta_eoi; + u32 gpio_ext_porta; /* 0x850 */ + u32 _pad_0x854_0x85c[3]; + u32 gpio_1s_sync; /* 0x860 */ + u32 _pad_0x864_0x868[2]; + u32 gpio_ver_id_code; + u32 gpio_config_reg2; /* 0x870 */ + u32 gpio_config_reg1; +}; + +#define FPGAMGRREGS_STAT_MODE_MASK 0x7 +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 +#define FPGAMGRREGS_STAT_MSEL_LSB 3 + +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 +#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 +#define FPGAMGRREGS_CTRL_EN_MASK 0x1 +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 + +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 + +/* FPGA Mode */ +#define FPGAMGRREGS_MODE_FPGAOFF 0x0 +#define FPGAMGRREGS_MODE_RESETPHASE 0x1 +#define FPGAMGRREGS_MODE_CFGPHASE 0x2 +#define FPGAMGRREGS_MODE_INITPHASE 0x3 +#define FPGAMGRREGS_MODE_USERMODE 0x4 +#define FPGAMGRREGS_MODE_UNKNOWN 0x5 + +/* FPGA CD Ratio Value */ +#define CDRATIO_x1 0x0 +#define CDRATIO_x2 0x1 +#define CDRATIO_x4 0x2 +#define CDRATIO_x8 0x3 + +/* SoCFPGA support functions */ +int fpgamgr_test_fpga_ready(void); +int fpgamgr_poll_fpga_ready(void); +int fpgamgr_get_mode(void); + +#endif /* _FPGA_MANAGER_H_ */ diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index dfb2e7f..6aa24d4 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -17,4 +17,5 @@ obj-y += altera.o obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o +obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o endif diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index fd2b4f0..a5bfe5d 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -37,6 +37,9 @@ static const struct altera_fpga { { Altera_StratixII, "StratixII", StratixII_load, StratixII_dump, StratixII_info }, #endif +#if defined(CONFIG_FPGA_SOCFPGA) + { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, +#endif }; static int altera_validate(Altera_desc *desc, const char *fn) diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c new file mode 100644 index 0000000..63b3566 --- /dev/null +++ b/drivers/fpga/socfpga.c @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2012 Altera Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Timeout count */ +#define FPGA_TIMEOUT_CNT 0x1000000 + +static struct socfpga_fpga_manager *fpgamgr_regs = + (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* Set CD ratio */ +static void fpgamgr_set_cd_ratio(unsigned long ratio) +{ + clrsetbits_le32(&fpgamgr_regs->ctrl, + 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB, + (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); +} + +static int fpgamgr_dclkcnt_set(unsigned long cnt) +{ + unsigned long i; + + /* Clear any existing done status */ + if (readl(&fpgamgr_regs->dclkstat)) + writel(0x1, &fpgamgr_regs->dclkstat); + + /* Write the dclkcnt */ + writel(cnt, &fpgamgr_regs->dclkcnt); + + /* Wait till the dclkcnt done */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + if (!readl(&fpgamgr_regs->dclkstat)) + continue; + + writel(0x1, &fpgamgr_regs->dclkstat); + return 0; + } + + return -ETIMEDOUT; +} + +/* Start the FPGA programming by initialize the FPGA Manager */ +static int fpgamgr_program_init(void) +{ + unsigned long msel, i; + + /* Get the MSEL value */ + msel = readl(&fpgamgr_regs->stat); + msel &= FPGAMGRREGS_STAT_MSEL_MASK; + msel >>= FPGAMGRREGS_STAT_MSEL_LSB; + + /* + * Set the cfg width + * If MSEL[3] = 1, cfg width = 32 bit + */ + if (msel & 0x8) { + setbits_le32(&fpgamgr_regs->ctrl, + FPGAMGRREGS_CTRL_CFGWDTH_MASK); + + /* To determine the CD ratio */ + /* MSEL[1:0] = 0, CD Ratio = 1 */ + if ((msel & 0x3) == 0x0) + fpgamgr_set_cd_ratio(CDRATIO_x1); + /* MSEL[1:0] = 1, CD Ratio = 4 */ + else if ((msel & 0x3) == 0x1) + fpgamgr_set_cd_ratio(CDRATIO_x4); + /* MSEL[1:0] = 2, CD Ratio = 8 */ + else if ((msel & 0x3) == 0x2) + fpgamgr_set_cd_ratio(CDRATIO_x8); + + } else { /* MSEL[3] = 0 */ + clrbits_le32(&fpgamgr_regs->ctrl, + FPGAMGRREGS_CTRL_CFGWDTH_MASK); + + /* To determine the CD ratio */ + /* MSEL[1:0] = 0, CD Ratio = 1 */ + if ((msel & 0x3) == 0x0) + fpgamgr_set_cd_ratio(CDRATIO_x1); + /* MSEL[1:0] = 1, CD Ratio = 2 */ + else if ((msel & 0x3) == 0x1) + fpgamgr_set_cd_ratio(CDRATIO_x2); + /* MSEL[1:0] = 2, CD Ratio = 4 */ + else if ((msel & 0x3) == 0x2) + fpgamgr_set_cd_ratio(CDRATIO_x4); + } + + /* To enable FPGA Manager configuration */ + clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); + + /* To enable FPGA Manager drive over configuration line */ + setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); + + /* Put FPGA into reset phase */ + setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); + + /* (1) wait until FPGA enter reset phase */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE) + break; + } + + /* If not in reset state, return error */ + if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) { + puts("FPGA: Could not reset\n"); + return -1; + } + + /* Release FPGA from reset phase */ + clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); + + /* (2) wait until FPGA enter configuration phase */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE) + break; + } + + /* If not in configuration state, return error */ + if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) { + puts("FPGA: Could not configure\n"); + return -2; + } + + /* Clear all interrupts in CB Monitor */ + writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi); + + /* Enable AXI configuration */ + setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); + + return 0; +} + +/* Write the RBF data to FPGA Manager */ +static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size) +{ + uint32_t src = (uint32_t)rbf_data; + uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS; + + /* Number of loops for 32-byte long copying. */ + uint32_t loops32 = rbf_size / 32; + /* Number of loops for 4-byte long copying + trailing bytes */ + uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4); + + asm volatile( + "1: ldmia %0!, {r0-r7}\n" + " stmia %1!, {r0-r7}\n" + " sub %1, #32\n" + " subs %2, #1\n" + " bne 1b\n" + "2: ldr %2, [%0], #4\n" + " str %2, [%1]\n" + " subs %3, #1\n" + " bne 2b\n" + : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); +} + +/* Ensure the FPGA entering config done */ +static int fpgamgr_program_poll_cd(void) +{ + const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK | + FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK; + unsigned long reg, i; + + /* (3) wait until full config done */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + reg = readl(&fpgamgr_regs->gpio_ext_porta); + + /* Config error */ + if (!(reg & mask)) { + printf("FPGA: Configuration error.\n"); + return -3; + } + + /* Config done without error */ + if (reg & mask) + break; + } + + /* Timeout happened, return error */ + if (i == FPGA_TIMEOUT_CNT) { + printf("FPGA: Timeout waiting for program.\n"); + return -4; + } + + /* Disable AXI configuration */ + clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); + + return 0; +} + +/* Ensure the FPGA entering init phase */ +static int fpgamgr_program_poll_initphase(void) +{ + unsigned long i; + + /* Additional clocks for the CB to enter initialization phase */ + if (fpgamgr_dclkcnt_set(0x4)) + return -5; + + /* (4) wait until FPGA enter init phase or user mode */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE) + break; + if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) + break; + } + + /* If not in configuration state, return error */ + if (i == FPGA_TIMEOUT_CNT) + return -6; + + return 0; +} + +/* Ensure the FPGA entering user mode */ +static int fpgamgr_program_poll_usermode(void) +{ + unsigned long i; + + /* Additional clocks for the CB to exit initialization phase */ + if (fpgamgr_dclkcnt_set(0x5000)) + return -7; + + /* (5) wait until FPGA enter user mode */ + for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { + if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) + break; + } + /* If not in configuration state, return error */ + if (i == FPGA_TIMEOUT_CNT) + return -8; + + /* To release FPGA Manager drive over configuration line */ + clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); + + return 0; +} + +/* + * FPGA Manager to program the FPGA. This is the interface used by FPGA driver. + * Return 0 for sucess, non-zero for error. + */ +int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{ + unsigned long status; + + if ((uint32_t)rbf_data & 0x3) { + puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); + return -EINVAL; + } + + /* Prior programming the FPGA, all bridges need to be shut off */ + + /* Disable all signals from hps peripheral controller to fpga */ + writel(0, &sysmgr_regs->fpgaintfgrp_module); + + /* Disable all signals from FPGA to HPS SDRAM */ +#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 + writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS); + + /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ + socfpga_bridges_reset(1); + + /* Unmap the bridges from NIC-301 */ + writel(0x1, SOCFPGA_L3REGS_ADDRESS); + + /* Initialize the FPGA Manager */ + status = fpgamgr_program_init(); + if (status) + return status; + + /* Write the RBF data to FPGA Manager */ + fpgamgr_program_write(rbf_data, rbf_size); + + /* Ensure the FPGA entering config done */ + status = fpgamgr_program_poll_cd(); + if (status) + return status; + + /* Ensure the FPGA entering init phase */ + status = fpgamgr_program_poll_initphase(); + if (status) + return status; + + /* Ensure the FPGA entering user mode */ + return fpgamgr_program_poll_usermode(); +} diff --git a/include/altera.h b/include/altera.h index e266a64..c2991ad 100644 --- a/include/altera.h +++ b/include/altera.h @@ -40,6 +40,8 @@ enum altera_family { Altera_CYC2, /* StratixII Family */ Altera_StratixII, + /* SoCFPGA Family */ + Altera_SoCFPGA, /* Add new models here */ @@ -91,4 +93,8 @@ typedef struct { Altera_post_fn post; } altera_board_specific_func; +#ifdef CONFIG_FPGA_SOCFPGA +int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#endif + #endif /* _ALTERA_H_ */ -- cgit v0.10.2 From abb25f4e9529c1b91d651c74af9bd3f1c955437b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: reset: Add function to reset FPGA bridges Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index badc569..1d3a95d 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,43 @@ void reset_deassert_peripherals_handoff(void) writel(0, &reset_manager_base->per_mod_reset); } +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +void socfpga_bridges_reset(int enable) +{ + /* For SoCFPGA-VT, this is NOP. */ +} +#else + +#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 +#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 +#define L3REGS_REMAP_OCRAM_MASK 0x01 + +void socfpga_bridges_reset(int enable) +{ + const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | + L3REGS_REMAP_HPS2FPGA_MASK | + L3REGS_REMAP_OCRAM_MASK; + + if (enable) { + /* brdmodrst */ + writel(0xffffffff, &reset_manager_base->brg_mod_reset); + } else { + /* Check signal from FPGA. */ + if (fpgamgr_poll_fpga_ready()) { + /* FPGA not ready. Wait for watchdog timeout. */ + printf("%s: fpga not ready, hanging.\n", __func__); + hang(); + } + + /* brdmodrst */ + writel(0, &reset_manager_base->brg_mod_reset); + + /* Remap the bridges into memory map */ + writel(l3mask, SOCFPGA_L3REGS_ADDRESS); + } +} +#endif + /* Change the reset state for EMAC 0 and EMAC 1 */ void socfpga_emac_reset(int enable) { diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 3c5ab40..1857b80 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,8 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +void socfpga_bridges_reset(int enable); + void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); -- cgit v0.10.2 From 807abb18f1376bcd674540e374f2ab7503caea51 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: sysmgr: Add FPGA bits into system manager Add missing system manager bits from Altera U-Boot to make the code comparable. These are the bits which depend on the FPGA manager. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c index 07c72e4..11f7bad 100644 --- a/arch/arm/cpu/armv7/socfpga/system_manager.c +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c @@ -15,6 +15,43 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; /* + * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. + * The value is not wrote to SYSMGR.FPGAINTF.MODULE but + * CONFIG_SYSMGR_ISWGRP_HANDOFF. + */ +static void populate_sysmgr_fpgaintf_module(void) +{ + uint32_t handoff_val = 0; + + /* ISWGRP_HANDOFF_FPGAINTF */ + writel(0, &sysmgr_regs->iswgrp_handoff[2]); + + /* Enable the signal for those HPS peripherals that use FPGA. */ + if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_NAND; + if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC1; + if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SDMMC; + if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC0; + if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM0; + if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM1; + + /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE + based on pinmux setting */ + setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val); + + handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]); + if (fpgamgr_test_fpga_ready()) { + /* Enable the required signals only */ + writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module); + } +} + +/* * Configure all the pin muxes */ void sysmgr_pinmux_init(void) @@ -26,4 +63,6 @@ void sysmgr_pinmux_init(void) writel(sys_mgr_init_table[i], regs); regs += sizeof(regs); } + + populate_sysmgr_fpgaintf_module(); } -- cgit v0.10.2 From 9ca2116ce49449602eb9e2f8a0cafe811bcc3086 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:27:57 +0200 Subject: arm: socfpga: cache: Define cacheline size The Cortex-A9 has 32-byte long L1 cachelines. Define this value. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 54343b8..76979b1 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -26,6 +26,8 @@ #define CONFIG_SOCFPGA #define CONFIG_CLOCKS +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x08000040 -- cgit v0.10.2 From 40e7bcdee72830fa51d9e98428f1a61f9126527e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:29:08 +0200 Subject: arm: socfpga: cache: Enable D-Cache The code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 4149842..6b98277 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -35,6 +35,7 @@ int board_early_init_f(void) int board_init(void) { icache_enable(); + dcache_enable(); /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 76979b1..de60bb2 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -18,7 +18,6 @@ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_ARMV7 -#define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ #define CONFIG_MISC_INIT_R @@ -26,6 +25,7 @@ #define CONFIG_SOCFPGA #define CONFIG_CLOCKS +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 /* base address for .text section */ -- cgit v0.10.2 From b5e9b296251f138ef9f9cfc15f408710a24831cd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:45:14 +0200 Subject: arm: socfpga: cache: Enable PL310 L2 cache Enable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index de60bb2..c8986d9 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -27,6 +27,8 @@ #define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -- cgit v0.10.2 From 181d363852b8b92e2175fd8ea220b7db444796f1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 06:28:01 +0200 Subject: arm: socfpga: scu: Add SCU register file Add the Snoop Control Unit register definition file. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/include/asm/arch-socfpga/scu.h b/arch/arm/include/asm/arch-socfpga/scu.h new file mode 100644 index 0000000..7a5b074 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/scu.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SOCFPGA_SCU_H__ +#define __SOCFPGA_SCU_H__ + +struct scu_registers { + u32 ctrl; /* 0x00 */ + u32 cfg; + u32 cpsr; + u32 iassr; + u32 _pad_0x10_0x3c[12]; /* 0x10 */ + u32 fsar; /* 0x40 */ + u32 fear; + u32 _pad_0x48_0x50[2]; + u32 acr; /* 0x54 */ + u32 sacr; +}; + +#endif /* __SOCFPGA_SCU_H__ */ -- cgit v0.10.2 From 7056efcc32081256af6172611874709c780f2007 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 06:03:38 +0200 Subject: arm: socfpga: nic301: Add NIC-301 GPV register file Add register definition for the NIC-301 used on SoCFPGA. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/include/asm/arch-socfpga/nic301.h b/arch/arm/include/asm/arch-socfpga/nic301.h new file mode 100644 index 0000000..3c8ab31 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/nic301.h @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _NIC301_REGISTERS_H_ +#define _NIC301_REGISTERS_H_ + +struct nic301_registers { + u32 remap; /* 0x0 */ + /* Security Register Group */ + u32 _pad_0x4_0x8[1]; + u32 l4main; + u32 l4sp; + u32 l4mp; /* 0x10 */ + u32 l4osc1; + u32 l4spim; + u32 stm; + u32 lwhps2fpgaregs; /* 0x20 */ + u32 _pad_0x24_0x28[1]; + u32 usb1; + u32 nanddata; + u32 _pad_0x30_0x80[20]; + u32 usb0; /* 0x80 */ + u32 nandregs; + u32 qspidata; + u32 fpgamgrdata; + u32 hps2fpgaregs; /* 0x90 */ + u32 acp; + u32 rom; + u32 ocram; + u32 sdrdata; /* 0xA0 */ + u32 _pad_0xa4_0x1fd0[1995]; + /* ID Register Group */ + u32 periph_id_4; /* 0x1FD0 */ + u32 _pad_0x1fd4_0x1fe0[3]; + u32 periph_id_0; /* 0x1FE0 */ + u32 periph_id_1; + u32 periph_id_2; + u32 periph_id_3; + u32 comp_id_0; /* 0x1FF0 */ + u32 comp_id_1; + u32 comp_id_2; + u32 comp_id_3; + u32 _pad_0x2000_0x2008[2]; + /* L4 MAIN */ + u32 l4main_fn_mod_bm_iss; + u32 _pad_0x200c_0x3008[1023]; + /* L4 SP */ + u32 l4sp_fn_mod_bm_iss; + u32 _pad_0x300c_0x4008[1023]; + /* L4 MP */ + u32 l4mp_fn_mod_bm_iss; + u32 _pad_0x400c_0x5008[1023]; + /* L4 OSC1 */ + u32 l4osc_fn_mod_bm_iss; + u32 _pad_0x500c_0x6008[1023]; + /* L4 SPIM */ + u32 l4spim_fn_mod_bm_iss; + u32 _pad_0x600c_0x7008[1023]; + /* STM */ + u32 stm_fn_mod_bm_iss; + u32 _pad_0x700c_0x7108[63]; + u32 stm_fn_mod; + u32 _pad_0x710c_0x8008[959]; + /* LWHPS2FPGA */ + u32 lwhps2fpga_fn_mod_bm_iss; + u32 _pad_0x800c_0x8108[63]; + u32 lwhps2fpga_fn_mod; + u32 _pad_0x810c_0xa008[1983]; + /* USB1 */ + u32 usb1_fn_mod_bm_iss; + u32 _pad_0xa00c_0xa044[14]; + u32 usb1_ahb_cntl; + u32 _pad_0xa048_0xb008[1008]; + /* NANDDATA */ + u32 nanddata_fn_mod_bm_iss; + u32 _pad_0xb00c_0xb108[63]; + u32 nanddata_fn_mod; + u32 _pad_0xb10c_0x20008[21439]; + /* USB0 */ + u32 usb0_fn_mod_bm_iss; + u32 _pad_0x2000c_0x20044[14]; + u32 usb0_ahb_cntl; + u32 _pad_0x20048_0x21008[1008]; + /* NANDREGS */ + u32 nandregs_fn_mod_bm_iss; + u32 _pad_0x2100c_0x21108[63]; + u32 nandregs_fn_mod; + u32 _pad_0x2110c_0x22008[959]; + /* QSPIDATA */ + u32 qspidata_fn_mod_bm_iss; + u32 _pad_0x2200c_0x22044[14]; + u32 qspidata_ahb_cntl; + u32 _pad_0x22048_0x23008[1008]; + /* FPGAMGRDATA */ + u32 fpgamgrdata_fn_mod_bm_iss; + u32 _pad_0x2300c_0x23040[13]; + u32 fpgamgrdata_wr_tidemark; /* 0x23040 */ + u32 _pad_0x23044_0x23108[49]; + u32 fn_mod; + u32 _pad_0x2310c_0x24008[959]; + /* HPS2FPGA */ + u32 hps2fpga_fn_mod_bm_iss; + u32 _pad_0x2400c_0x24040[13]; + u32 hps2fpga_wr_tidemark; /* 0x24040 */ + u32 _pad_0x24044_0x24108[49]; + u32 hps2fpga_fn_mod; + u32 _pad_0x2410c_0x25008[959]; + /* ACP */ + u32 acp_fn_mod_bm_iss; + u32 _pad_0x2500c_0x25108[63]; + u32 acp_fn_mod; + u32 _pad_0x2510c_0x26008[959]; + /* Boot ROM */ + u32 bootrom_fn_mod_bm_iss; + u32 _pad_0x2600c_0x26108[63]; + u32 bootrom_fn_mod; + u32 _pad_0x2610c_0x27008[959]; + /* On-chip RAM */ + u32 ocram_fn_mod_bm_iss; + u32 _pad_0x2700c_0x27040[13]; + u32 ocram_wr_tidemark; /* 0x27040 */ + u32 _pad_0x27044_0x27108[49]; + u32 ocram_fn_mod; + u32 _pad_0x2710c_0x42024[27590]; + /* DAP */ + u32 dap_fn_mod2; + u32 dap_fn_mod_ahb; + u32 _pad_0x4202c_0x42100[53]; + u32 dap_read_qos; /* 0x42100 */ + u32 dap_write_qos; + u32 dap_fn_mod; + u32 _pad_0x4210c_0x43100[1021]; + /* MPU */ + u32 mpu_read_qos; /* 0x43100 */ + u32 mpu_write_qos; + u32 mpu_fn_mod; + u32 _pad_0x4310c_0x44028[967]; + /* SDMMC */ + u32 sdmmc_fn_mod_ahb; + u32 _pad_0x4402c_0x44100[53]; + u32 sdmmc_read_qos; /* 0x44100 */ + u32 sdmmc_write_qos; + u32 sdmmc_fn_mod; + u32 _pad_0x4410c_0x45100[1021]; + /* DMA */ + u32 dma_read_qos; /* 0x45100 */ + u32 dma_write_qos; + u32 dma_fn_mod; + u32 _pad_0x4510c_0x46040[973]; + /* FPGA2HPS */ + u32 fpga2hps_wr_tidemark; /* 0x46040 */ + u32 _pad_0x46044_0x46100[47]; + u32 fpga2hps_read_qos; /* 0x46100 */ + u32 fpga2hps_write_qos; + u32 fpga2hps_fn_mod; + u32 _pad_0x4610c_0x47100[1021]; + /* ETR */ + u32 etr_read_qos; /* 0x47100 */ + u32 etr_write_qos; + u32 etr_fn_mod; + u32 _pad_0x4710c_0x48100[1021]; + /* EMAC0 */ + u32 emac0_read_qos; /* 0x48100 */ + u32 emac0_write_qos; + u32 emac0_fn_mod; + u32 _pad_0x4810c_0x49100[1021]; + /* EMAC1 */ + u32 emac1_read_qos; /* 0x49100 */ + u32 emac1_write_qos; + u32 emac1_fn_mod; + u32 _pad_0x4910c_0x4a028[967]; + /* USB0 */ + u32 usb0_fn_mod_ahb; + u32 _pad_0x4a02c_0x4a100[53]; + u32 usb0_read_qos; /* 0x4A100 */ + u32 usb0_write_qos; + u32 usb0_fn_mod; + u32 _pad_0x4a10c_0x4b100[1021]; + /* NAND */ + u32 nand_read_qos; /* 0x4B100 */ + u32 nand_write_qos; + u32 nand_fn_mod; + u32 _pad_0x4b10c_0x4c028[967]; + /* USB1 */ + u32 usb1_fn_mod_ahb; + u32 _pad_0x4c02c_0x4c100[53]; + u32 usb1_read_qos; /* 0x4C100 */ + u32 usb1_write_qos; + u32 usb1_fn_mod; +}; + +#endif /* _NIC301_REGISTERS_H_ */ -- cgit v0.10.2 From 60d804c2f3ddd0071348c6e65999e19b4d07d16a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 03:58:22 +0200 Subject: arm: socfpga: pl310: Map SDRAM to 0x0 Configure the PL310 address filter to make sure DRAM is mapped to 0x0. This code also configures the "remap" register of NIC-301 and sets the required 'mpuzero' bit. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index b07d97e..0fc26c2 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -12,11 +12,17 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static struct nic301_registers *nic301_regs = + (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; int dram_init(void) { @@ -142,6 +148,14 @@ int arch_cpu_init(void) int misc_init_r(void) { + /* Configure the L2 controller to make SDRAM start at 0 */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET + writel(0x2, &nic301_regs->remap); +#else + writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + writel(0x1, &pl310->pl310_addr_filter_start); +#endif + /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); return 0; -- cgit v0.10.2 From 13e81d45f80b58e57a78daf6850d4f3a6bc20d9e Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: nic301: Add NIC-301 configuration code Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA . The code sets the access permissions for the CPU to the AMBA slaves such that the CPU can access them in both secure and non-secure mode. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 0fc26c2..76186c5 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -23,6 +24,8 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; +static struct scu_registers *scu_regs = + (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; int dram_init(void) { @@ -146,8 +149,31 @@ int arch_cpu_init(void) return 0; } +/* + * Convert all NIC-301 AMBA slaves from secure to non-secure + */ +static void socfpga_nic301_slave_ns(void) +{ + writel(0x1, &nic301_regs->lwhps2fpgaregs); + writel(0x1, &nic301_regs->hps2fpgaregs); + writel(0x1, &nic301_regs->acp); + writel(0x1, &nic301_regs->rom); + writel(0x1, &nic301_regs->ocram); + writel(0x1, &nic301_regs->sdrdata); +} + int misc_init_r(void) { + socfpga_bridges_reset(1); + socfpga_nic301_slave_ns(); + + /* + * Private components security: + * U-Boot : configure private timer, global timer and cpu component + * access as non secure for kernel stage (as required by Linux) + */ + setbits_le32(&scu_regs->sacr, 0xfff); + /* Configure the L2 controller to make SDRAM start at 0 */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET writel(0x2, &nic301_regs->remap); -- cgit v0.10.2 From ddcbed04a21857cb0a457b0ff3de26c750815632 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Fri, 19 Sep 2014 04:28:23 -0500 Subject: arm: socfpga: Enable DWMMC for SOCFPGA Enable the DesignWare MMC controller driver support for SOCFPGA Cyclone5 dev kit Signed-off-by: Chin Liang See Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Tom Rini Cc: Albert Aribaud Cc: Wolfgang Denk Acked-by: Pavel Machek diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index c8986d9..0da7059 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -251,6 +251,22 @@ /* Clocks source frequency to watchdog timer */ #define CONFIG_DW_WDT_CLOCK_KHZ 25000 +/* + * MMC support + */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_SOCFPGA_DWMMC +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +/* using smaller max blk cnt to avoid flooding the limited stack we have */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +#endif /* CONFIG_MMC */ /* * SPL "Second Program Loader" aka Initial Software -- cgit v0.10.2 From 97ce274d97e9c1796d58ae34aadcbc10293cccd7 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Fri, 19 Sep 2014 05:33:19 -0500 Subject: arm: socfpga: Enable SDMMC boot for SOCFPGA U-Boot Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit. Enable the bootz command as zImage is used instead uImage. Signed-off-by: Chin Liang See Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Tom Rini Cc: Albert Aribaud Cc: Wolfgang Denk Acked-by: Pavel Machek diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 0da7059..ac08e7a 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -93,6 +93,8 @@ #include /* FAT file system support */ #define CONFIG_CMD_FAT +/* bootz command support */ +#define CONFIG_CMD_BOOTZ /* @@ -117,24 +119,36 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_CMD_RUN +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#endif /* * arguments passed to the bootm command. The value of * CONFIG_BOOTARGS goes into the environment value "bootargs". * Do note the value will overide also the chosen node in FDT blob. */ -#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=uImage\0" \ + "bootimage=zImage\0" \ "fdt_addr=100\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "fatload mmc 0:1 ${loadaddr} ${bootimage};" \ + "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ "qspiroot=/dev/mtdblock0\0" \ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ -- cgit v0.10.2 From 4ab333b765db5cd00b297b4c0e3cd3af5fe320fc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Sep 2014 13:57:40 +0200 Subject: arm: socfpga: Move cache_enable to CPU code Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Tom Rini Cc: Albert Aribaud Cc: Wolfgang Denk Acked-by: Pavel Machek diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 76186c5..7f9d7f0 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -33,6 +33,16 @@ int dram_init(void) return 0; } +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + /* * DesignWare Ethernet initialization */ diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 6b98277..0f81d89 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -34,9 +34,6 @@ int board_early_init_f(void) */ int board_init(void) { - icache_enable(); - dcache_enable(); - /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -- cgit v0.10.2 From 7249fafb1a96c014dfc0d4ccf6ea937643199e67 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: Add command to control HPS-FPGA bridges Add command to enable and disable the bridges between HPS and FPGA. This patch does have a checkpatch issue with the assembler portion, checkpatch correctly complains that there should be no whitespace before quoted newline. I do not agree that fixing this specific checkpatch issue will improve the readability, thus this one is not addressed. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Tom Rini Cc: Albert Aribaud Cc: Wolfgang Denk diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 7f9d7f0..0eab264 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -22,6 +22,8 @@ static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static struct socfpga_reset_manager *reset_manager_base = + (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = @@ -172,8 +174,14 @@ static void socfpga_nic301_slave_ns(void) writel(0x1, &nic301_regs->sdrdata); } +static uint32_t iswgrp_handoff[8]; + int misc_init_r(void) { + int i; + for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ + iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); + socfpga_bridges_reset(1); socfpga_nic301_slave_ns(); @@ -196,3 +204,70 @@ int misc_init_r(void) socfpga_fpga_add(); return 0; } + +static void socfpga_sdram_apply_static_cfg(void) +{ + const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; + const uint32_t applymask = 0x8; + uint32_t val = readl(staticcfg) | applymask; + + /* + * SDRAM staticcfg register specific: + * When applying the register setting, the CPU must not access + * SDRAM. Luckily for us, we can abuse i-cache here to help us + * circumvent the SDRAM access issue. The idea is to make sure + * that the code is in one full i-cache line by branching past + * it and back. Once it is in the i-cache, we execute the core + * of the code and apply the register settings. + * + * The code below uses 7 instructions, while the Cortex-A9 has + * 32-byte cachelines, thus the limit is 8 instructions total. + */ + asm volatile( + ".align 5 \n" + " b 2f \n" + "1: str %0, [%1] \n" + " dsb \n" + " isb \n" + " b 3f \n" + "2: b 1b \n" + "3: nop \n" + : : "r"(val), "r"(staticcfg) : "memory", "cc"); +} + +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + argv++; + + switch (*argv[0]) { + case 'e': /* Enable */ + writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); + socfpga_sdram_apply_static_cfg(); + writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); + writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); + writel(iswgrp_handoff[1], &nic301_regs->remap); + break; + case 'd': /* Disable */ + writel(0, &sysmgr_regs->fpgaintfgrp_module); + writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); + socfpga_sdram_apply_static_cfg(); + writel(0, &reset_manager_base->brg_mod_reset); + writel(1, &nic301_regs->remap); + break; + default: + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + bridge, 2, 1, do_bridge, + "SoCFPGA HPS FPGA bridge control", + "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "" +); -- cgit v0.10.2 From 47f9b4e1f3c2422ab72c66065eb92c66a9159c45 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: Clean up SoCFPGA configuration Reorganize and cleanup the configuration file for SoCFPGA. There is no functional change after this cleanup. This was necessary, since the file was a wild mess and it was impossible to make sense of it's content, let alone change something without breaking some other thing. This patch puts the contents on par with regular U-Boot standards. Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER and CONFIG_USE_IRQ, which is undefined by default. Finally, do logical reordering of the defines in the file so it's much more readable. The reordering was also necessary for the splitting as the initial one was messy. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index ac08e7a..5349a35 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -1,319 +1,288 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012 Altera Corporation * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ +#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ #include #include "../../board/altera/socfpga/pinmux_config.h" #include "../../board/altera/socfpga/iocsr_config.h" #include "../../board/altera/socfpga/pll_config.h" -/* - * High level configuration - */ +#define CONFIG_SYS_GENERIC_BOARD + /* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_ARMV7 -#undef CONFIG_USE_IRQ +#define CONFIG_SYS_THUMB_BUILD -#define CONFIG_MISC_INIT_R -#define CONFIG_SINGLE_BOOTLOADER #define CONFIG_SOCFPGA -#define CONFIG_CLOCKS -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG -/* base address for .text section */ -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TEXT_BASE 0x08000040 -#else -#define CONFIG_SYS_TEXT_BASE 0x01000040 -#endif -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_REGEX /* Enable regular expression support */ /* - * Display CPU and Board Info + * High level configuration */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO - -/* - * Enable early stage initialization at C environment - */ #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CLOCKS -/* flat device tree */ +#define CONFIG_FIT #define CONFIG_OF_LIBFDT -/* skip updating the FDT blob */ -#define CONFIG_FDT_BLOB_SKIP_UPDATE -/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ -#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) +#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) -#define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) -#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* - * Memory allocation (MALLOC) + * Memory configurations */ -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE 1024 -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x0 +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE -/* SP location before relocation, must use scratch RAM */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -/* Reserving 0x100 space at back of scratch RAM for debug info */ #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) -/* Stack pointer prior relocation, must situated at on-chip RAM */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - - -/* - * Command line configuration. - */ -#define CONFIG_SYS_NO_FLASH -#include -/* FAT file system support */ -#define CONFIG_CMD_FAT -/* bootz command support */ -#define CONFIG_CMD_BOOTZ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) - -/* - * Misc - */ -#define CONFIG_DOS_PARTITION 1 - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_PARTITIONS +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000040 #endif -/* - * Environment setup - */ - -/* Delay before automatically booting the default image */ -#define CONFIG_BOOTDELAY 3 -/* Enable auto completion of commands using TAB */ -#define CONFIG_AUTO_COMPLETE -/* use "hush" command parser */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_CMD_RUN - +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTCOMMAND "run ramboot" #else -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" #endif +#define CONFIG_LOADADDR 0x8000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* - * arguments passed to the bootm command. The value of - * CONFIG_BOOTARGS goes into the environment value "bootargs". - * Do note the value will overide also the chosen node in FDT blob. + * U-Boot general configurations */ -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "fatload mmc 0:1 ${loadaddr} ${bootimage};" \ - "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" - -/* using environment setting for stdin, stdout, stderr */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -/* Enable the call to overwrite_console() */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -/* Enable overwrite of previous console environment settings */ -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER /* - * Hardware drivers + * Cache */ +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* - * SDRAM Memory Map + * Ethernet on SoC (EMAC) */ -/* We have 1 bank of DRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -/* SDRAM Bank #1 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* SDRAM memory size */ -#define PHYS_SDRAM_1_SIZE 0x40000000 +#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_NET_MULTI +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_MII +#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) +#define CONFIG_PHYLIB +#define CONFIG_PHY_GIGE -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE +#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII +#define CONFIG_EPHY0_PHY_ADDR 0 + +/* PHY */ +#define CONFIG_EPHY1_PHY_ADDR 4 +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 -/* - * NS16550 Configuration - */ -#define UART0_BASE SOCFPGA_UART0_ADDRESS -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define V_NS16550_CLK 1000000 -#else -#define V_NS16550_CLK 100000000 #endif -#define CONFIG_BAUDRATE 115200 /* - * FLASH + * FPGA Driver */ -#define CONFIG_SYS_NO_FLASH +#ifdef CONFIG_CMD_FPGA +#define CONFIG_FPGA +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_SOCFPGA +#define CONFIG_FPGA_COUNT 1 +#endif /* * L4 OSC1 Timer 0 */ -/* This timer use eosc1 where the clock frequency is fixed - * throughout any condition */ +/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -/* Timer info */ +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TIMER_RATE 2400000 #else #define CONFIG_SYS_TIMER_RATE 25000000 #endif -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) - -#define CONFIG_ENV_IS_NOWHERE - -/* - * network support - */ -#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_DESIGNWARE_ETH 1 -#endif - -#ifdef CONFIG_DESIGNWARE_ETH -#define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS -#define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS -/* console support for network */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -/* designware */ -#define CONFIG_NET_MULTI -#define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_MII -#define CONFIG_PHY_GIGE -#define CONFIG_DW_AUTONEG -#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) -#define CONFIG_PHYLIB -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_MICREL_KSZ9021 -/* EMAC controller and PHY used */ -#define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE -#define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR -#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII -#endif /* CONFIG_DESIGNWARE_ETH */ /* * L4 Watchdog */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 +#ifdef CONFIG_HW_WATCHDOG #define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS -/* Clocks source frequency to watchdog timer */ #define CONFIG_DW_WDT_CLOCK_KHZ 25000 +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000 +#endif /* - * MMC support + * MMC Driver */ +#ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#ifdef CONFIG_MMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC #define CONFIG_DWMMC #define CONFIG_SOCFPGA_DWMMC #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +/* FIXME */ /* using smaller max blk cnt to avoid flooding the limited stack we have */ -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 -#endif /* CONFIG_MMC */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ +#endif /* - * SPL "Second Program Loader" aka Initial Software + * Serial Driver */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_NS16550_CLK 1000000 +#else +#define CONFIG_SYS_NS16550_CLK 100000000 +#endif +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 -/* Enable building of SPL globally */ -#define CONFIG_SPL_FRAMEWORK - -/* TEXT_BASE for linking the SPL binary */ -#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 +/* + * USB + * Ungate USB: + * mw 0xffd05014 0x01bef032 + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_OTG +/*#define CONFIG_USB_DWC2_REG_ADDR 0xffb00000*/ +#define CONFIG_USB_DWC2_REG_ADDR 0xffb40000 +#define CONFIG_USB_STORAGE +#endif -/* Stack size for SPL */ -#define CONFIG_SPL_STACK_SIZE (4 * 1024) +/* + * U-Boot environment + */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_HOSTNAME socfpga_cyclone5 -/* MALLOC size for SPL */ -#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "fatload mmc 0:1 ${loadaddr} ${bootimage};" \ + "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" -#define CONFIG_SPL_SERIAL_SUPPORT +/* + * SPL + */ +#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_STACK_SIZE (4 * 1024) +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */ +#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) -#define CHUNKSZ_CRC32 (1 * 1024) - +#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ #define CONFIG_CRC32_VERIFY /* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" -/* Support for common/libcommon.o in SPL binary */ #define CONFIG_SPL_LIBCOMMON_SUPPORT -/* Support for lib/libgeneric.o in SPL binary */ #define CONFIG_SPL_LIBGENERIC_SUPPORT - -/* Support for watchdog */ #define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif -#endif /* __CONFIG_H */ +#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ -- cgit v0.10.2 From 5095ee088df05bd49f87721fe244ae1b3972b546 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Mon, 8 Sep 2014 14:08:45 +0200 Subject: arm: socfpga: Split SoCFPGA configuration Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h new file mode 100644 index 0000000..49504dc --- /dev/null +++ b/include/configs/socfpga_common.h @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ +#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ + +#define CONFIG_SYS_GENERIC_BOARD + +/* Virtual target or real hardware */ +#undef CONFIG_SOCFPGA_VIRTUAL_TARGET + +#define CONFIG_ARMV7 +#define CONFIG_SYS_THUMB_BUILD + +#define CONFIG_SOCFPGA + +/* + * High level configuration + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CLOCKS + +#define CONFIG_FIT +#define CONFIG_OF_LIBFDT +#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x0 +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE + +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000040 +#endif + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Cache + */ +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS + +/* + * Ethernet on SoC (EMAC) + */ +#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_NET_MULTI +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_MII +#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) +#define CONFIG_PHYLIB +#define CONFIG_PHY_GIGE +#endif + +/* + * FPGA Driver + */ +#ifdef CONFIG_CMD_FPGA +#define CONFIG_FPGA +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_SOCFPGA +#define CONFIG_FPGA_COUNT 1 +#endif + +/* + * L4 OSC1 Timer 0 + */ +/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_TIMER_RATE 2400000 +#else +#define CONFIG_SYS_TIMER_RATE 25000000 +#endif + +/* + * L4 Watchdog + */ +#ifdef CONFIG_HW_WATCHDOG +#define CONFIG_DESIGNWARE_WATCHDOG +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +#define CONFIG_DW_WDT_CLOCK_KHZ 25000 +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000 +#endif + +/* + * MMC Driver + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_SOCFPGA_DWMMC +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +/* FIXME */ +/* using smaller max blk cnt to avoid flooding the limited stack we have */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ +#endif + +/* + * Serial Driver + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_NS16550_CLK 1000000 +#else +#define CONFIG_SYS_NS16550_CLK 100000000 +#endif +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* + * U-Boot environment + */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 4096 + +/* + * SPL + */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_STACK_SIZE (4 * 1024) +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */ +#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) + +#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ +#define CONFIG_CRC32_VERIFY + +/* Linker script for SPL */ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif + +#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 5349a35..34d9cf6 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -1,26 +1,16 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2014 Marek Vasut * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ -#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ +#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ +#define __CONFIG_SOCFPGA_CYCLONE5_H__ #include #include "../../board/altera/socfpga/pinmux_config.h" #include "../../board/altera/socfpga/iocsr_config.h" #include "../../board/altera/socfpga/pll_config.h" -#define CONFIG_SYS_GENERIC_BOARD - -/* Virtual target or real hardware */ -#undef CONFIG_SOCFPGA_VIRTUAL_TARGET - -#define CONFIG_ARMV7 -#define CONFIG_SYS_THUMB_BUILD - -#define CONFIG_SOCFPGA - /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH #include @@ -45,44 +35,8 @@ #define CONFIG_REGEX /* Enable regular expression support */ -/* - * High level configuration - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MISC_INIT_R -#define CONFIG_SYS_NO_FLASH -#define CONFIG_CLOCKS - -#define CONFIG_FIT -#define CONFIG_OF_LIBFDT -#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Memory configurations - */ +/* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x0 -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TEXT_BASE 0x08000040 -#else -#define CONFIG_SYS_TEXT_BASE 0x01000040 -#endif /* Booting Linux */ #define CONFIG_BOOTDELAY 3 @@ -96,42 +50,8 @@ #define CONFIG_LOADADDR 0x8000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Cache - */ -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS - -/* - * Ethernet on SoC (EMAC) - */ -#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -#define CONFIG_DESIGNWARE_ETH -#define CONFIG_NET_MULTI -#define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_MII -#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) -#define CONFIG_PHYLIB -#define CONFIG_PHY_GIGE - +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) #define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII #define CONFIG_EPHY0_PHY_ADDR 0 @@ -147,92 +67,8 @@ #endif -/* - * FPGA Driver - */ -#ifdef CONFIG_CMD_FPGA -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_SOCFPGA -#define CONFIG_FPGA_COUNT 1 -#endif - -/* - * L4 OSC1 Timer 0 - */ -/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TIMER_RATE 2400000 -#else -#define CONFIG_SYS_TIMER_RATE 25000000 -#endif - -/* - * L4 Watchdog - */ -#ifdef CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS -#define CONFIG_DW_WDT_CLOCK_KHZ 25000 -#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000 -#endif - -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_GENERIC_MMC -#define CONFIG_DWMMC -#define CONFIG_SOCFPGA_DWMMC -#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 -#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 -/* FIXME */ -/* using smaller max blk cnt to avoid flooding the limited stack we have */ -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ -#endif - -/* - * Serial Driver - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_NS16550_CLK 1000000 -#else -#define CONFIG_SYS_NS16550_CLK 100000000 -#endif -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * USB - * Ungate USB: - * mw 0xffd05014 0x01bef032 - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_OTG -/*#define CONFIG_USB_DWC2_REG_ADDR 0xffb00000*/ -#define CONFIG_USB_DWC2_REG_ADDR 0xffb40000 -#define CONFIG_USB_STORAGE -#endif - -/* - * U-Boot environment - */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_HOSTNAME socfpga_cyclone5 +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_cyclone5 #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ @@ -257,32 +93,7 @@ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ "bootm ${loadaddr} - ${fdt_addr}\0" -/* - * SPL - */ -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SPL_STACK_SIZE (4 * 1024) -#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */ -#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) -#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) - -#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ -#define CONFIG_CRC32_VERIFY - -/* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_WATCHDOG_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_PARTITIONS -#endif +/* The rest of the configuration is shared */ +#include -#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ +#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ -- cgit v0.10.2 From 2f210639c4f003b0d5310273979441f1bfc88eae Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 19 Sep 2014 13:28:47 +0200 Subject: arm: socfpga: Use CMD_FS_GENERIC Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the filesystem type into the environment. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 34d9cf6..8d54bf8 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -26,6 +26,7 @@ #define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_GREPENV #define CONFIG_CMD_MII #define CONFIG_CMD_MMC @@ -85,8 +86,8 @@ " root=${mmcroot} rw rootwait;" \ "bootz ${loadaddr} - ${fdt_addr}\0" \ "mmcload=mmc rescan;" \ - "fatload mmc 0:1 ${loadaddr} ${bootimage};" \ - "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ "qspiroot=/dev/mtdblock0\0" \ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ -- cgit v0.10.2 From 16b61d13bab361853564da401b15fc34ae1dfea7 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 22 Jul 2014 12:47:02 +0200 Subject: usb: musb-new: core: set MUSB_POWER_HSENAB in MUSB_POWER for host mode This bit allows the MUSB controller to negotiate for high-speed mode when the device is reset by the hub. If unset, Babble errors occur with high-speed mass storage devices right after the first packet. This condition is not caught by the interrupt handles in U-Boot, so no recovery is done, and the USB communication is stuck. To fix this, set the bit unconditionally, not only for CONFIG_USB_GADGET_DUALSPEED but also for host-only modes. Signed-off-by: Daniel Mack diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c index 4edd6d7..242cc30 100644 --- a/drivers/usb/musb-new/musb_core.c +++ b/drivers/usb/musb-new/musb_core.c @@ -942,9 +942,7 @@ void musb_start(struct musb *musb) /* put into basic highspeed mode and start session */ musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE -#ifdef CONFIG_USB_GADGET_DUALSPEED | MUSB_POWER_HSENAB -#endif /* ENSUSPEND wedges tusb */ /* | MUSB_POWER_ENSUSPEND */ ); -- cgit v0.10.2 From e2140588dd2f3e619f21d9575281b7c7ea771c09 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Wed, 1 Oct 2014 14:30:56 -0700 Subject: usb: gadget: fastboot: terminate commands with NULL Without NULL termination, various commands will read past the end of input. In particular, this was noticed with error() calls in cb_getvar and simple_strtoul() in cb_download. Since the download callback happens elsewhere, the 4k buffer should always be sufficient to handle command arguments. Signed-off-by: Eric Nelson diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 392379d..71b62e5 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -546,7 +546,14 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) error("unknown command: %s\n", cmdbuf); fastboot_tx_write_str("FAILunknown command"); } else { - func_cb(ep, req); + if (req->actual < req->length) { + u8 *buf = (u8 *)req->buf; + buf[req->actual] = 0; + func_cb(ep, req); + } else { + error("buffer overflow\n"); + fastboot_tx_write_str("FAILbuffer overflow"); + } } if (req->status == 0) { -- cgit v0.10.2 From 742de9076e8a8f44b77794b43e6175d86b897996 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 6 Oct 2014 20:23:09 -0400 Subject: Prepare v2014.10-rc3 Signed-off-by: Tom Rini diff --git a/Makefile b/Makefile index 6221113..8657417 100644 --- a/Makefile +++ b/Makefile @@ -8,7 +8,7 @@ VERSION = 2014 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* -- cgit v0.10.2 From f885b849681ce0f15c2df313f38ae06a601be506 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 30 Sep 2014 18:45:32 +0200 Subject: sunxi: Fix gmac not working reliable on the Bananapi In order for the gmac nic to work reliable on the Bananapi, we need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" of the GMAC clk register (0x01c20164) to 3. Without this about 9 out of 10 ethernet packets get lost, with this setting there is no packet loss. So far setting these bits is only necessary on the Bananapi, so this commit solves this with a bit of #ifdef CONFIG_BANANAPI code. If in the future we need to do something similar for other boards, we can create a specific CONFIG_FOO option for this then. Reported-by: Karsten Merker Signed-off-by: Hans de Goede Tested-by: Karsten Merker Tested-by: Zoltan HERPAI Tested-by: Tony Zhang Acked-by: Ian Campbell diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index e7ff952..6348d27 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -24,6 +24,15 @@ int sunxi_gmac_initialize(bd_t *bis) CCM_GMAC_CTRL_GPIT_MII); #endif + /* + * In order for the gmac nic to work reliable on the Bananapi, we + * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" + * of the GMAC clk register to 3. + */ +#ifdef CONFIG_BANANAPI + setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10); +#endif + /* Configure pin mux settings for GMAC */ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { #ifdef CONFIG_RGMII -- cgit v0.10.2 From 05968e7cfd5dcc50cfe51d03d119a5e9d77bd07c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 20:03:03 +0900 Subject: mtd: denali: fix NAND_CMD_PARAM command NAND_CMD_PARAM (0xEC) command is not working on the Denali NAND controller driver. Unlike NAND_CMD_READID (0x90), when the NAND_CMD_PARAM command is followed by an address cycle, the target device goes busy. (R/B# is deasserted) Wait until the parameter data are ready. In addition, unnecessary clear_interrupts() should be removed. Signed-off-by: Masahiro Yamada Acked-by: Chin Liang See diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index ba3de1a..d9abc7e 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1059,9 +1059,8 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, cmd); break; - case NAND_CMD_PARAM: - clear_interrupts(denali); case NAND_CMD_READID: + case NAND_CMD_PARAM: reset_buf(denali); /* sometimes ManufactureId read from register is not right * e.g. some of Micron MT29F32G08QAA MLC NAND chips @@ -1070,6 +1069,8 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, cmd); index_addr(denali, addr | 1, col & 0xFF); + if (cmd == NAND_CMD_PARAM) + udelay(50); break; case NAND_CMD_READ0: case NAND_CMD_SEQIN: -- cgit v0.10.2 From ed3c980bee74dc1bd599dd44b41b2c32ee78c0a8 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 20:03:04 +0900 Subject: mtd: denali: support NAND_CMD_RNDOUT command The function nand_flash_detect_ext_param_page() requires NAND_CMD_RNDOUT command supported. It is necessary to detect some types of ONFi-compliant devices. Without it, the error message "unsupported command received 0x5" is shown. Let's support this command on the Denali NAND controller driver. Signed-off-by: Masahiro Yamada Acked-by: Chin Liang See diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index d9abc7e..308b784 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1072,6 +1072,13 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, if (cmd == NAND_CMD_PARAM) udelay(50); break; + case NAND_CMD_RNDOUT: + addr = MODE_11 | BANK(denali->flash_bank); + index_addr(denali, addr | 0, cmd); + index_addr(denali, addr | 1, col & 0xFF); + index_addr(denali, addr | 1, col >> 8); + index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART); + break; case NAND_CMD_READ0: case NAND_CMD_SEQIN: denali->page = page; -- cgit v0.10.2 From 64a0c24726530696bf0c2cdaa75d171d957a7ee0 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Fri, 3 Oct 2014 14:29:01 +0100 Subject: pxe: Ensure we don't overflow bootargs On a couple of platforms I've tripped over long PXE append lines overflowing this array, due to having CONFIG_SYS_CBSIZE == 256. When doing preseeded Debian installs it's pretty trivial to exceed that. Since the symptom can be a silent hang or a crash add a check. Of course the affected boards would also need an increased CBSIZE to actually work. Note that due to the printing of the final bootargs string CONFIG_SYS_PBSIZE also needs to be sufficiently large. Signed-off-by: Ian Campbell [trini: Use %zd not %d in printf for all args] Signed-off-by: Tom Rini diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index 0ab1e0a..7e32c95 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -674,6 +674,15 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) char bootargs[CONFIG_SYS_CBSIZE] = ""; char finalbootargs[CONFIG_SYS_CBSIZE]; + if (strlen(label->append ?: "") + + strlen(ip_str) + strlen(mac_str) + 1 > sizeof(bootargs)) { + printf("bootarg overflow %zd+%zd+%zd+1 > %zd\n", + strlen(label->append ?: ""), + strlen(ip_str), strlen(mac_str), + sizeof(bootargs)); + return 1; + } + if (label->append) strcpy(bootargs, label->append); strcat(bootargs, ip_str); -- cgit v0.10.2 From fef3e25fc3f59da6410878614e8717020a7d7f74 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 2 Oct 2014 15:20:10 -0700 Subject: common/board_r: Fix booting issue on T4240QDS Commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 moved initr_malloc earlier than initr_unlock_ram_in_cache. This causes issue on T4240. It may be related to locked L1 d-cache and unlocked L2 cache. D- cache could and should be unlock earlier for normal operation. This patch moves initr_unlock_ram_in_cache before initr_malloc. It has been verified on the following boards, in which only T4240QDS suffered and has been since fixed: T4240QDS, T2080QDS, P5040DS, P4080DS, MPC8572DS, MPC8536DS, MPC8641HPCN, B4860QDS. Signed-off-by: York Sun CC: Scott Wood CC: Simon Glass Acked-by: Simon Glass diff --git a/common/board_r.c b/common/board_r.c index 231c6d6..c339aad 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -717,6 +717,9 @@ init_fnc_t init_sequence_r[] = { initr_caches, #endif initr_reloc_global_data, +#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) + initr_unlock_ram_in_cache, +#endif initr_barrier, initr_malloc, bootstage_relocate, @@ -759,9 +762,6 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_SYS_DELAYED_ICACHE initr_icache_enable, #endif -#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) - initr_unlock_ram_in_cache, -#endif #if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) /* * Do early PCI configuration _before_ the flash gets initialised, -- cgit v0.10.2 From 115e71f7da1f6fd96c20793842f5751897d9fdee Mon Sep 17 00:00:00 2001 From: Stefan Herbrechtsmeier Date: Tue, 16 Sep 2014 17:51:05 +0200 Subject: omap3: overo: Fix fdtfile test Commit 12cc54376768461533b55ada1b0b6d4979f40579 'omap3: overo: Select fdtfile for expansion board' wrongly missed the operator in the fdtfile test. Update the test to only overwrite an empty fdtfile environment variable. Signed-off-by: Stefan Herbrechtsmeier diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index e66f306..b17e495 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -151,7 +151,7 @@ "run mmcboot;" \ "fi;" \ "if run loadzimage; then " \ - "if test $fdtfile; then " \ + "if test -z \"${fdtfile}\"; then " \ "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \ "fi;" \ "if run loadfdt; then " \ -- cgit v0.10.2 From 02590aa31cc282cffafac559032981094f716fa9 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:01 +0300 Subject: ahci: Don't start command DMA engine before buffers are set The DMA/FIS buffers are set in ahci_port_start() which is called after ahci_host_init(). So don't start the DMA engine here (i.e. don't set FIS_RX) This fixes the following error at kernel boot on OMAP platforms (e.g. DRA7x) WARNING: CPU: 0 PID: 0 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x260/0x358() 44000000.ocp:L3 Custom Error: MASTER SATA TARGET GPMC (Idle): Data Access in User mode during Functional access Signed-off-by: Roger Quadros diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index dce99ad..a93a8e1 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -229,7 +229,6 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) * already be on in the command register. */ cmd = readl(port_mmio + PORT_CMD); - cmd |= PORT_CMD_FIS_RX; cmd |= PORT_CMD_SPIN_UP; writel_with_flush(cmd, port_mmio + PORT_CMD); -- cgit v0.10.2 From 3160b1b98603cba3c480f70e153b259171d3e4a6 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:02 +0300 Subject: OMAP5+: sata/scsi: Implement scsi_init() On OMAP platforms, SATA controller provides the SCSI subsystem so implement scsi_init(). Get rid of the unnecessary sata_init() call from dra7xx-evm and omap5-uevm board files. Signed-off-by: Roger Quadros diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index cad4fee..131d082 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -74,3 +74,9 @@ int init_sata(int dev) return ret; } + +/* On OMAP platforms SATA provides the SCSI subsystem */ +void scsi_init(void) +{ + init_sata(0); +} diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 5592fc5..37df7b2 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -93,7 +93,6 @@ int board_late_init(void) else setenv("board_name", "dra7xx"); #endif - init_sata(0); return 0; } diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 4666b38..833ffe9 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -69,12 +69,6 @@ int board_init(void) return 0; } -int board_late_init(void) -{ - init_sata(0); - return 0; -} - int board_eth_init(bd_t *bis) { return 0; diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 7e2ecd5..e8dc462 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -72,7 +72,6 @@ /* Max time to hold reset on this board, see doc/README.omap-reset-time */ #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 -#define CONFIG_BOARD_LATE_INIT #define CONFIG_CMD_SCSI #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI -- cgit v0.10.2 From d59baeb76f911d0391e73e5f6068e55ea48514f8 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:03 +0300 Subject: ARM: OMAP5+: sata: Move scsi_scan() to the right place scsi_scan() must be called as part of scsi_init() and not as part of sata_init(). Signed-off-by: Roger Quadros diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index 131d082..3b4dd3f 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -70,7 +70,6 @@ int init_sata(int dev) writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); ret = ahci_init(DWC_AHSATA_BASE); - scsi_scan(1); return ret; } @@ -79,4 +78,5 @@ int init_sata(int dev) void scsi_init(void) { init_sata(0); + scsi_scan(1); } -- cgit v0.10.2 From 76300c0d2d63bb7cb02679bf749f30ae4a1ca969 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:04 +0300 Subject: common: spl_sata: perform SCSI scan before getting device At least on OMAP, init_sata() no longer performs scsi_scan() so we must do it explicitly here. Cc: Dan Murphy Signed-off-by: Roger Quadros diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c index 2e7adca..12e16d9 100644 --- a/common/spl/spl_sata.c +++ b/common/spl/spl_sata.c @@ -32,6 +32,7 @@ void spl_sata_load_image(void) hang(); } else { /* try to recognize storage devices immediately */ + scsi_scan(0); stor_dev = scsi_get_dev(0); } -- cgit v0.10.2 From 026330af41842e7752a291012428a5ddf2c06449 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Tue, 23 Sep 2014 21:10:26 +0300 Subject: ARM: keystone: clock: fix main pll ratio div definitions The definitions for div ratio supposed to be in hex and were added in dec by mistake. Signed-off-by: Ivan Khoronzhuk diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h index e545341..85a046b 100644 --- a/arch/arm/include/asm/arch-keystone/clock_defs.h +++ b/arch/arm/include/asm/arch-keystone/clock_defs.h @@ -102,10 +102,10 @@ static struct pllctl_regs *pllctl_regs[] = { #define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) #define PLL_BWADJ_HI_MASK 0xf -#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0) -#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0) -#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1) -#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4) -#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17) +#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0) +#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0) +#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1) +#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4) +#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17) #endif /* _CLOCK_DEFS_H_ */ -- cgit v0.10.2 From 717a23b871d1563bc3a063ebceccf13a2ca2d10b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 26 Sep 2014 18:42:36 +0900 Subject: kconfig: fix another bug of "make savedefconfig" In some cases, the last lines of SPL or TPL are not output to a file. The entries remaining in the "unmatched" variable must be flushed. Signed-off-by: Masahiro Yamada Acked-by: Simon Glass diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh index 4a8737f..b5185a8 100644 --- a/scripts/multiconfig.sh +++ b/scripts/multiconfig.sh @@ -229,6 +229,8 @@ do_savedefconfig () { unmatched="$unmatched%$symbol:$line" fi done < defconfig + + output_lines="$output_lines%$unmatched" done rm -f defconfig -- cgit v0.10.2 From dc9617e0cee28808863cbb21f4528f89bc383923 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:57 +0900 Subject: powerpc: ppc4xx: remove board support for KAREF and METROBOX These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 41b525c..7c645f1 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -226,12 +226,6 @@ config TARGET_ALPR config TARGET_P3P440 bool "Support p3p440" -config TARGET_KAREF - bool "Support KAREF" - -config TARGET_METROBOX - bool "Support METROBOX" - config TARGET_XPEDITE1000 bool "Support xpedite1000" @@ -306,8 +300,6 @@ source "board/mpl/pip405/Kconfig" source "board/pcs440ep/Kconfig" source "board/prodrive/alpr/Kconfig" source "board/prodrive/p3p440/Kconfig" -source "board/sandburst/karef/Kconfig" -source "board/sandburst/metrobox/Kconfig" source "board/sbc405/Kconfig" source "board/sc3/Kconfig" source "board/t3corp/Kconfig" diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c deleted file mode 100644 index ad046be..0000000 --- a/board/sandburst/common/flash.c +++ /dev/null @@ -1,493 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * Ported from Ebony flash support - * Travis B. Sawyer - * Sandburst Corporation - */ -#include -#include -#include - - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xfff80000} /* Boot Flash */ -}; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; - } - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); - - /* Write auto select command: read Manufacturer ID */ - udelay(10000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - udelay(1000); - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - udelay(1000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - udelay(1000); - - value = addr2[0]; - - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; /* => 512 kb */ - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* reset to return to reading data */ - addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - DEBUGF("Erasing sector %p\n", addr2); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c deleted file mode 100644 index c23ef50..0000000 --- a/board/sandburst/common/sb_common.c +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include "sb_common.h" - -DECLARE_GLOBAL_DATA_PTR; - -long int fixed_sdram (void); - -/************************************************************************* - * metrobox_get_master - * - * PRI_N - active low signal. If the GPIO pin is low we are the master - * - ************************************************************************/ -int sbcommon_get_master(void) -{ - ppc440_gpio_regs_t *gpio_regs; - - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - - if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) { - return 0; - } - else { - return 1; - } -} - -/************************************************************************* - * metrobox_secondary_present - * - * Figure out if secondary/slave board is present - * - ************************************************************************/ -int sbcommon_secondary_present(void) -{ - ppc440_gpio_regs_t *gpio_regs; - - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - - if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES) - return 0; - else - return 1; -} - -/************************************************************************* - * sbcommon_get_serial_number - * - * Retrieve the board serial number via the mac address in eeprom - * - ************************************************************************/ -unsigned short sbcommon_get_serial_number(void) -{ - unsigned char buff[0x100]; - unsigned short sernum; - - /* Get the board serial number from eeprom */ - /* Initialize I2C */ - i2c_set_bus_num(0); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - memcpy(&sernum, &buff[0xF4], 2); - sernum /= 32; - - return (sernum); -} - -/************************************************************************* - * sbcommon_fans - * - * Spin up fans 2 & 3 to get some air moving. OS will take care - * of the rest. This is mostly a precaution... - * - * Assumes i2c bus 1 is ready. - * - ************************************************************************/ -void sbcommon_fans(void) -{ - /* - * Attempt to turn on 2 of the fans... - * Need to go through the bridge - */ - i2c_set_bus_num(1); - puts ("FANS: "); - - /* select fan4 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x08); /* val = bus 4 */ - - /* Turn on FAN 4 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 4 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan3 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x04); /* val = bus 3 */ - - /* Turn on FAN 3 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 3 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan2 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x02); /* val = bus 4 */ - - /* Turn on FAN 2 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 2 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan1 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x01); /* val = bus 0 */ - - /* Turn on FAN 1 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 1 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - puts ("on\n"); - i2c_set_bus_num(0); - - return; - -} - -/************************************************************************* - * initdram - * - * Initialize sdram - * - ************************************************************************/ -phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - return dram_size; -} - - -/************************************************************************* - * testdram - * - * - ************************************************************************/ -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing SDRAM: "); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("OK\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay (400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram (SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -/************************************************************************* - * board_get_enetaddr - * - * Get the ethernet MAC address for the management ethernet from the - * strap EEPROM. Note that is the BASE address for the range of - * external ethernet MACs on the board. The base + 31 is the actual - * mgmt mac address. - * - ************************************************************************/ - -void board_get_enetaddr(int macaddr_idx, uchar *enet) -{ - int i; - unsigned short tmp; - unsigned char buff[0x100], *cp; - - if (0 == macaddr_idx) { - - /* Initialize I2C */ - i2c_set_bus_num(0); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - cp = &buff[0xF0]; - - for (i = 0; i < 6; i++,cp++) - enet[i] = *cp; - - memcpy(&tmp, &enet[4], 2); - tmp += 31; - memcpy(&enet[4], &tmp, 2); - - } else { - enet[0] = 0x02; - enet[1] = 0x00; - enet[2] = 0x00; - enet[3] = 0x00; - enet[4] = 0x00; - if (1 == sbcommon_get_master() ) { - /* Master/Primary card */ - enet[5] = 0x01; - } else { - /* Slave/Secondary card */ - enet [5] = 0x02; - } - } - - return; -} - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - - return (ctrlc()); -} -#endif diff --git a/board/sandburst/common/sb_common.h b/board/sandburst/common/sb_common.h deleted file mode 100644 index 5740633..0000000 --- a/board/sandburst/common/sb_common.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __SBCOMMON_H__ -#define __SBCOMMON_H__ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include - -/* - * GPIO Settings - */ -/* Chassis settings */ -#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */ -#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */ - -/* Debug LEDs */ -#define SBCOMMON_GPIO_DBGLED_0 0x00000400 -#define SBCOMMON_GPIO_DBGLED_1 0x00000200 -#define SBCOMMON_GPIO_DBGLED_2 0x00100000 -#define SBCOMMON_GPIO_DBGLED_3 0x00000100 - -#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \ - SBCOMMON_GPIO_DBGLED_1 | \ - SBCOMMON_GPIO_DBGLED_2 | \ - SBCOMMON_GPIO_DBGLED_3) - -#define SBCOMMON_GPIO_SYS_FAULT 0x00000080 -#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040 -#define SBCOMMON_GPIO_SYS_STATUS 0x00000020 - -#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS) - -#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \ - SBCOMMON_GPIO_DBGLED_1 | \ - SBCOMMON_GPIO_DBGLED_2 | \ - SBCOMMON_GPIO_DBGLED_3 | \ - SBCOMMON_GPIO_SYS_STATUS) - -typedef struct ppc440_gpio_regs { - volatile unsigned long out; - volatile unsigned long tri_state; - volatile unsigned long dummy[4]; - volatile unsigned long open_drain; - volatile unsigned long in; -} __attribute__((packed)) ppc440_gpio_regs_t; - -int sbcommon_get_master(void); -int sbcommon_secondary_present(void); -unsigned short sbcommon_get_serial_number(void); -void sbcommon_fans(void); -void board_get_enetaddr(int macaddr_idx, uchar *enet); - -#endif /* __SBCOMMON_H__ */ diff --git a/board/sandburst/karef/Kconfig b/board/sandburst/karef/Kconfig deleted file mode 100644 index 1b04576..0000000 --- a/board/sandburst/karef/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KAREF - -config SYS_BOARD - default "karef" - -config SYS_VENDOR - default "sandburst" - -config SYS_CONFIG_NAME - default "KAREF" - -endif diff --git a/board/sandburst/karef/MAINTAINERS b/board/sandburst/karef/MAINTAINERS deleted file mode 100644 index 21510e8..0000000 --- a/board/sandburst/karef/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -KAREF BOARD -#M: Travis Sawyer -S: Orphan (since 2014-03) -F: board/sandburst/karef/ -F: include/configs/KAREF.h -F: configs/KAREF_defconfig diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile deleted file mode 100644 index ce29b41..0000000 --- a/board/sandburst/karef/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Sandburst Corporation -# Travis B. Sawyer -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# TBS: add for debugging purposes -ccflags-y += -DBUILDUSER='"$(shell whoami)"' - -obj-y = karef.o ../common/flash.o ../common/sb_common.o -extra-y += init.o diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk deleted file mode 100644 index b73986d..0000000 --- a/board/sandburst/karef/config.mk +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2005 -# Sandburst Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# Sandburst Corporation Metrobox Reference Design -# Travis B. Sawyer -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h deleted file mode 100644 index cc501c9..0000000 --- a/board/sandburst/karef/hal_ka_of_auto.h +++ /dev/null @@ -1,324 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip ka_of - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_KA_OF_AUTO_H -#define HAL_KA_OF_AUTO_H - - -/* ---------------------------------------------------------------- - * For block: 'ofem' - */ - -/* ---- Block instance addressing (for block-select) */ -#define OFEM_BLOCK_ADDR_BIT_L 6 -#define OFEM_BLOCK_ADDR_BIT_H 9 -#define OFEM_BLOCK_ADDR_WIDTH 4 - -#define OFEM_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define OFEM_REG_ADDR_BIT_L 2 -#define OFEM_REG_ADDR_BIT_H 5 -#define OFEM_REG_ADDR_WIDTH 4 - - -/* ================================================================ - * ---- Register KA_OF_OFEM_REVISION */ -#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31 -#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_RESET */ -#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004 -#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31 -#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_CNTL */ -#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018 -#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31 -#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */ -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c -#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_INTERRUPT */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008 -#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_INTERRUPT_MASK */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c -#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_SCRATCH */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010 -#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_SCRATCH_MASK */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014 -#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register KA_OF_OFEM_REVISION */ -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_RESET */ -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_CNTL */ -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */ -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_INTERRUPT */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_INTERRUPT_MASK */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register KA_OF_OFEM_SCRATCH */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_SCRATCH_MASK */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_KA_OF_AUTO_H */ diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h deleted file mode 100644 index db1cec2..0000000 --- a/board/sandburst/karef/hal_ka_sc_auto.h +++ /dev/null @@ -1,836 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip ka_sc - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_KA_SC_AUTO_H -#define HAL_KA_SC_AUTO_H - - -/* ---------------------------------------------------------------- - * For block: 'scan' - */ - -/* ---- Block instance addressing (for block-select) */ -#define SCAN_BLOCK_ADDR_BIT_L 7 -#define SCAN_BLOCK_ADDR_BIT_H 9 -#define SCAN_BLOCK_ADDR_WIDTH 3 - -#define SCAN_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define SCAN_REG_ADDR_BIT_L 2 -#define SCAN_REG_ADDR_BIT_H 6 -#define SCAN_REG_ADDR_WIDTH 5 - - -/* ================================================================ - * ---- Register KA_SC_SCAN_REVISION */ -#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31 -#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_RESET */ -#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004 -#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31 -#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_STATUS */ -#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008 -#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31 -#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_CNTL */ -#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c -#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_INFO */ -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_FROM_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_FROM_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_TO_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_TO_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_CTRL */ -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_PLL_CTRL */ -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038 -#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c -#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_DR_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040 -#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044 -#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_IN */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_MISC */ -#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054 -#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31 -#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_INTERRUPT */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c -#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_INTERRUPT_MASK */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010 -#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCRATCH */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014 -#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCRATCH_MASK */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018 -#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register KA_SC_SCAN_REVISION */ -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_RESET */ -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_STATUS */ -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_CNTL */ -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_INFO */ -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_FROM_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_FROM_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_TO_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_TO_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_CTRL */ -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_PLL_CTRL */ -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_DR_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_IN */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_MISC */ -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_INTERRUPT */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_INTERRUPT_MASK */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCRATCH */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCRATCH_MASK */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_KA_SC_AUTO_H */ diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S deleted file mode 100644 index 61c5d07..0000000 --- a/board/sandburst/karef/init.S +++ /dev/null @@ -1,39 +0,0 @@ -/* -* Copyright (C) 2005 Sandburst Corporation - * SPDX-License-Identifier: GPL-2.0+ -*/ -/* - * Ported from Ebony init.S by Travis B. Sawyer - */ - -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c deleted file mode 100644 index 96d7dcd..0000000 --- a/board/sandburst/karef/karef.c +++ /dev/null @@ -1,595 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "karef.h" -#include "karef_version.h" -#include -#include -#include -#include -#include -#include "../common/sb_common.h" -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) -#include -#endif - -void fpga_init (void); - -KAREF_BOARD_ID_ST board_id_as[] = -{ - {"Undefined"}, /* Not specified */ - {"Kamino Reference Design"}, - {"Reserved"}, /* Reserved for future use */ - {"Reserved"}, /* Reserved for future use */ -}; - -KAREF_BOARD_ID_ST ofem_board_id_as[] = -{ - {"Undefined"}, - {"1x10 + 10x2"}, - {"Reserved"}, - {"Reserved"}, -}; - -/************************************************************************* - * board_early_init_f - * - * Setup chip selects, initialize the Opto-FPGA, initialize - * interrupt polarity and triggers. - ************************************************************************/ -int board_early_init_f (void) -{ - ppc440_gpio_regs_t *gpio_regs; - - /* Enable GPIO interrupts */ - mtsdr(SDR0_PFC0, 0x00103E00); - - /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; - gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; - - /* Turn on all the leds for now */ - gpio_regs->out = SBCOMMON_GPIO_LEDS; - - /*--------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------*/ - mtebc(EBC0_CFG, - EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | - EBC_CFG_PR_32); - - /*--------------------------------------------------------------------+ - | 1/2 MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB0AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - /*--------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB1AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB2AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | KaRef Scan FPGA. Initialize bank 3 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB5AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | MAC A & B for Kamino. OFEM FPGA decodes the addresses - | Initialize bank 4 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB4AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | - EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | OFEM FPGA Initialize bank 5 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB3AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - - mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB6AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | BME-32. Initialize bank 7 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB7AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - * Setup the interrupt controller polarities, triggers, etc. - +-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000000); /* all non- critical */ - mtdcr (UIC1PR, 0xfffffe03); /* polarity */ - mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ - mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffff83ff); /* polarity */ - mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); - mtdcr (UIC0TR, 0x00000000); - mtdcr (UIC0VR, 0x00000001); - - fpga_init(); - - return 0; -} - - -/************************************************************************* - * checkboard - * - * Dump pertinent info to the console - ************************************************************************/ -int checkboard (void) -{ - sys_info_t sysinfo; - unsigned char brd_rev, brd_id; - unsigned short sernum; - unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0; - unsigned char ofem_brd_rev, ofem_brd_id; - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - - scan_id = (unsigned char)((karef_ps->revision_ul & - SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT); - - scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK) - >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT); - - brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT); - - brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT); - - ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); - - ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT); - - if (0xF != ofem_brd_id) { - ofem_id = (unsigned char)((ofem_ps->revision_ul & - SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT); - - ofem_rev = (unsigned char)((ofem_ps->revision_ul & - SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK) - >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT); - } - - get_sys_info (&sysinfo); - - sernum = sbcommon_get_serial_number(); - - printf ("Board: Sandburst Corporation Kamino Reference Design " - "Serial Number: %d\n", sernum); - printf ("%s\n", KAREF_U_BOOT_REL_STR); - - printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - if (sbcommon_get_master()) { - printf("Slot 0 - Master\nSlave board"); - if (sbcommon_secondary_present()) - printf(" present\n"); - else - printf(" not detected\n"); - } else { - printf("Slot 1 - Slave\n\n"); - } - - printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev); - printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id); - if(0xF != ofem_brd_id) { - printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev); - printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev); - } - - /* Fix the ack in the bme 32 */ - udelay(5000); - out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); - asm("eieio"); - - - return (0); -} - -/************************************************************************* - * misc_init_f - * - * Initialize I2C bus one to gain access to the fans - ************************************************************************/ -int misc_init_f (void) -{ - /* Turn on fans 3 & 4 */ - sbcommon_fans(); - - return (0); -} - -/************************************************************************* - * misc_init_r - * - * Do nothing. - ************************************************************************/ -int misc_init_r (void) -{ - unsigned short sernum; - char envstr[255]; - uchar enetaddr[6]; - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - - if(NULL != getenv("secondserial")) { - puts("secondserial is set, switching to second serial port\n"); - setenv("stderr", "serial1"); - setenv("stdout", "serial1"); - setenv("stdin", "serial1"); - } - - setenv("ubrelver", KAREF_U_BOOT_REL_STR); - - memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", - U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - setenv("bldstr", envstr); - saveenv(); - - if( getenv("autorecover")) { - setenv("autorecover", NULL); - saveenv(); - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for automatic filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type allow the system to continue to boot\n"); - } - - if( getenv("fakeled")) { - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; - karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; - setenv("bootdelay", "-1"); - saveenv(); - printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); - } - -#ifdef CONFIG_HAS_ETH0 - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(0, enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH1 - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - board_get_enetaddr(1, enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH2 - if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { - board_get_enetaddr(2, enetaddr); - eth_setenv_enetaddr("eth2addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH3 - if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { - board_get_enetaddr(3, enetaddr); - eth_setenv_enetaddr("eth3addr", enetaddr); - } -#endif - - return (0); -} - -/************************************************************************* - * ide_set_reset - ************************************************************************/ -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - KAREF_FPGA_REGS_ST *karef_ps; - /* TODO: ide reset */ - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - - if (on) { - karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; - } else { - karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; - } -} -#endif /* CONFIG_IDE_RESET */ - -/************************************************************************* - * fpga_init - ************************************************************************/ -void fpga_init(void) -{ - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - unsigned char ofem_id; - unsigned long tmp; - - /* Ensure we have power all around */ - udelay(500); - - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - tmp = - SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK; - - karef_ps->reset_ul = tmp; - - /* - * Wait a bit to allow the ofem fpga to get its brains - */ - udelay(5000); - - /* - * Check to see if the ofem is there - */ - ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); - if(0xF != ofem_id) { - tmp = - SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK | - SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | - SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; - - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - ofem_ps->reset_ul = tmp; - - ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; - } - - karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT; - - asm("eieio"); - - return; -} - -int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - memset(envstr, 0, 255); - /* - * Setup our ip address - */ - sprintf(envstr, "10.100.70.%d", sernum); - - setenv("ipaddr", envstr); - /* - * Setup the host ip address - */ - setenv("serverip", "10.100.17.10"); - - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " - "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d " - "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:" - "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33", - sernum, sernum, sernum); - - setenv("bootargs_nfs", envstr); - setenv("bootargs", envstr); - - /* - * Setup CF bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", - sernum, sernum); - - setenv("bootargs_cf", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000"); - setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000"); - - /* - * Setup compact flash boot command - */ - setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000"); - - saveenv(); - - return(1); -} - -int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - - setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type boot.\nWhen the kernel has booted" - " please type fsrecover.sh\n"); - - return(1); -} - -U_BOOT_CMD(kasetup, 1, 1, karefSetupVars, - "Set environment to factory defaults", ""); - -U_BOOT_CMD(karecover, 1, 1, karefRecover, - "Set environment to allow for fs recovery", ""); diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h deleted file mode 100644 index eb9c314..0000000 --- a/board/sandburst/karef/karef.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __KAREF_H__ -#define __KAREF_H__ -/* - * (C) Copyright 2005 - * Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Ka Reference Design OFEM FPGA Registers & definitions */ -#include "hal_ka_sc_auto.h" -#include "hal_ka_of_auto.h" - -typedef struct karef_board_id_s { - const char name[40]; -} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST; - -/* SCAN FPGA */ -typedef struct karef_fpga_regs_s -{ - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long status_ul; /* Read Only */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long boardinfo_ul; /* Read Only */ - volatile unsigned long scan_from0_ul; /* Read Only */ - volatile unsigned long scan_from1_ul; /* Read Only */ - volatile unsigned long scan_to0_ul; /* Read/Write */ - volatile unsigned long scan_to1_ul; /* Read/Write */ - volatile unsigned long scan_control_ul; /* Read/Write */ - volatile unsigned long pll_control_ul; /* Read/Write */ - volatile unsigned long core_clock_cnt_ul; /* Read/Write */ - volatile unsigned long dr_clock_cnt_ul; /* Read/Write */ - volatile unsigned long spi_clock_cnt_ul; /* Read/Write */ - volatile unsigned long brdout_data_ul; /* Read/Write */ - volatile unsigned long brdout_enable_ul; /* Read/Write */ - volatile unsigned long brdin_data_ul; /* Read Only */ - volatile unsigned long misc_ul; /* Read/Write */ -} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST; - -/* OFEM FPGA */ -typedef struct ofem_fpga_regs_s -{ - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */ -} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST; - - -#endif /* __KAREF_H__ */ diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h deleted file mode 100644 index 6c6baee..0000000 --- a/board/sandburst/karef/karef_version.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _KAREF_VERSION_H_ -#define _KAREF_VERSION_H_ -/* - * Copyright (C) 2005 Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#define KAREF_U_BOOT_REL_STR "Release 0.0.7" -#endif diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug deleted file mode 100644 index c17c8b9..0000000 --- a/board/sandburst/karef/u-boot.lds.debug +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/sandburst/karef/init.o (.text) - arch/powerpc/cpu/ppc4xx/kgdb.o (.text) - arch/powerpc/cpu/ppc4xx/traps.o (.text) - arch/powerpc/cpu/ppc4xx/interrupts.o (.text) - arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text) - arch/powerpc/cpu/ppc4xx/cpu_init.o (.text) - arch/powerpc/cpu/ppc4xx/speed.o (.text) - drivers/net/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - -/* common/env_embedded.o(.text) */ - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/sandburst/metrobox/Kconfig b/board/sandburst/metrobox/Kconfig deleted file mode 100644 index 4a771ef..0000000 --- a/board/sandburst/metrobox/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_METROBOX - -config SYS_BOARD - default "metrobox" - -config SYS_VENDOR - default "sandburst" - -config SYS_CONFIG_NAME - default "METROBOX" - -endif diff --git a/board/sandburst/metrobox/MAINTAINERS b/board/sandburst/metrobox/MAINTAINERS deleted file mode 100644 index 71d18f9..0000000 --- a/board/sandburst/metrobox/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -METROBOX BOARD -#M: Travis Sawyer -S: Orphan (since 2014-03) -F: board/sandburst/metrobox/ -F: include/configs/METROBOX.h -F: configs/METROBOX_defconfig diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile deleted file mode 100644 index 2c1028b..0000000 --- a/board/sandburst/metrobox/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# TBS: add for debugging purposes -ccflags-y += -DBUILDUSER='"$(shell whoami)"' - -obj-y = metrobox.o ../common/flash.o ../common/sb_common.o -extra-y += init.o diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk deleted file mode 100644 index 23190c8..0000000 --- a/board/sandburst/metrobox/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2005 -# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h deleted file mode 100644 index c99b38c..0000000 --- a/board/sandburst/metrobox/hal_xc_auto.h +++ /dev/null @@ -1,553 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip xc - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_XC_AUTO_H -#define HAL_XC_AUTO_H - -/* ---------------------------------------------------------------- - * For block: 'xcvr_cntl' - */ - -/* ---- Block instance addressing (for block-select) */ -#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6 -#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9 -#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4 - -#define XCVR_CNTL_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define XCVR_CNTL_REG_ADDR_BIT_L 2 -#define XCVR_CNTL_REG_ADDR_BIT_H 5 -#define XCVR_CNTL_REG_ADDR_WIDTH 4 - - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_REVISION */ -#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_RESET */ -#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004 -#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_STATUS */ -#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008 -#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_CNTL */ -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c -#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_BRD_INFO */ -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020 -#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */ -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024 -#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_INTERRUPT */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c -#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010 -#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_SCRATCH */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014 -#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018 -#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_REVISION */ -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_RESET */ -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_STATUS */ -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_CNTL */ -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_BRD_INFO */ -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */ -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_INTERRUPT */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_SCRATCH */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_XC_AUTO_H */ diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S deleted file mode 100644 index 13e340e..0000000 --- a/board/sandburst/metrobox/init.S +++ /dev/null @@ -1,37 +0,0 @@ -/* -* Copyright (C) 2005 -* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c deleted file mode 100644 index 290fa02..0000000 --- a/board/sandburst/metrobox/metrobox.c +++ /dev/null @@ -1,561 +0,0 @@ -/* - * Copyright (c) 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include "metrobox.h" -#include "metrobox_version.h" -#include -#include -#include -#include -#include -#include "../common/sb_common.h" -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) -#include -#endif - -void fpga_init (void); - -METROBOX_BOARD_ID_ST board_id_as[] = -{ {"Undefined"}, /* Not specified */ - {"2x10Gb"}, /* 2 ports, 10 GbE */ - {"20x1Gb"}, /* 20 ports, 1 GbE */ - {"Reserved"}, /* Reserved for future use */ -}; - -/************************************************************************* - * board_early_init_f - * - * Setup chip selects, initialize the Opto-FPGA, initialize - * interrupt polarity and triggers. - ************************************************************************/ -int board_early_init_f (void) -{ - ppc440_gpio_regs_t *gpio_regs; - - /* Enable GPIO interrupts */ - mtsdr(SDR0_PFC0, 0x00103E00); - - /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; - gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; - - /* Turn on all the leds for now */ - gpio_regs->out = SBCOMMON_GPIO_LEDS; - - /*--------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------*/ - mtebc(EBC0_CFG, - EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | - EBC_CFG_PR_32); - - /*--------------------------------------------------------------------+ - | 1/2 MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB0AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - /*--------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB1AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB2AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | OPTO & OFEM FPGA. Initialize bank 3 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB3AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | MAC A for metrobox - | MAC A & B for Kamino. OFEM FPGA decodes the addresses - | Initialize bank 4 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB4AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | Metrobox MAC B Initialize bank 5 with default values. - | KA REF FPGA Initialize bank 5 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB5AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB6AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | BME-32. Initialize bank 7 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB7AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - * Setup the interrupt controller polarities, triggers, etc. - +-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000000); /* all non- critical */ - mtdcr (UIC1PR, 0xfffffe03); /* polarity */ - mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ - mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffff83ff); /* polarity */ - mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); - mtdcr (UIC0TR, 0x00000000); - mtdcr (UIC0VR, 0x00000001); - - fpga_init(); - - return 0; -} - -/************************************************************************* - * checkboard - * - * Dump pertinent info to the console - ************************************************************************/ -int checkboard (void) -{ - sys_info_t sysinfo; - unsigned char brd_rev, brd_id; - unsigned short sernum; - unsigned char opto_rev, opto_id; - OPTO_FPGA_REGS_ST *opto_ps; - - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - - opto_id = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT); - - brd_rev = (unsigned char)((opto_ps->boardinfo_ul & - SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK) - >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT); - - brd_id = (unsigned char)((opto_ps->boardinfo_ul & - SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK) - >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT); - - get_sys_info (&sysinfo); - - sernum = sbcommon_get_serial_number(); - printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum); - printf ("%s\n", METROBOX_U_BOOT_REL_STR); - - printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - if (sbcommon_get_master()) { - printf("Slot 0 - Master\nSlave board"); - if (sbcommon_secondary_present()) - printf(" present\n"); - else - printf(" not detected\n"); - } else { - printf("Slot 1 - Slave\n\n"); - } - - printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev); - printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name); - - /* Fix the ack in the bme 32 */ - udelay(5000); - out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); - asm("eieio"); - - - return (0); -} - -/************************************************************************* - * misc_init_f - * - * Initialize I2C bus one to gain access to the fans - ************************************************************************/ -int misc_init_f (void) -{ - /* Turn on fans */ - sbcommon_fans(); - - return (0); -} - -/************************************************************************* - * misc_init_r - * - * Do nothing. - ************************************************************************/ -int misc_init_r (void) -{ - unsigned short sernum; - char envstr[255]; - uchar enetaddr[6]; - unsigned char opto_rev; - OPTO_FPGA_REGS_ST *opto_ps; - - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - if(NULL != getenv("secondserial")) { - puts("secondserial is set, switching to second serial port\n"); - setenv("stderr", "serial1"); - setenv("stdout", "serial1"); - setenv("stdin", "serial1"); - } - - setenv("ubrelver", METROBOX_U_BOOT_REL_STR); - - memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", - U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - setenv("bldstr", envstr); - saveenv(); - - if( getenv("autorecover")) { - setenv("autorecover", NULL); - saveenv(); - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for automatic filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type allow the system to continue to boot\n"); - } - - if( getenv("fakeled")) { - setenv("bootdelay", "-1"); - saveenv(); - printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - - if(0x12 <= opto_rev) { - opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK; - } - } - -#ifdef CONFIG_HAS_ETH0 - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(0, enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH1 - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - board_get_enetaddr(1, enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH2 - if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { - board_get_enetaddr(2, enetaddr); - eth_setenv_enetaddr("eth2addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH3 - if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { - board_get_enetaddr(3, enetaddr); - eth_setenv_enetaddr("eth3addr", enetaddr); - } -#endif - - return (0); -} - -/************************************************************************* - * ide_set_reset - ************************************************************************/ -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - if (on) { /* assert RESET */ - opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; - } else { /* release RESET */ - opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; - } -} -#endif /* CONFIG_IDE_RESET */ - -/************************************************************************* - * fpga_init - ************************************************************************/ -void fpga_init(void) -{ - OPTO_FPGA_REGS_ST *opto_ps; - unsigned char opto_rev; - unsigned long tmp; - - /* Ensure we have power all around */ - udelay(500); - - /* - * Take appropriate hw bits out of reset - */ - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - tmp = - SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK; - opto_ps->reset_ul = tmp; - /* - * Turn on the 'Slow Blink' for the System Error Led. - * Ensure FPGA rev is up to at least rev 0x12 - */ - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - if(0x12 <= opto_rev) { - opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT; - } - - asm("eieio"); - - return; -} - -int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - memset(envstr, 0, 255); - /* - * Setup our ip address - */ - sprintf(envstr, "10.100.60.%d", sernum); - - setenv("ipaddr", envstr); - /* - * Setup the host ip address - */ - setenv("serverip", "10.100.17.10"); - - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " - "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d " - "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1" - ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33", - sernum, sernum, sernum); - - setenv("bootargs_nfs", envstr); - setenv("bootargs", envstr); - - /* - * Setup CF bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", - sernum, sernum); - - setenv("bootargs_cf", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000"); - setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000"); - - /* - * Setup compact flash boot command - */ - setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000"); - - saveenv(); - - - return(1); -} - -int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none", - sernum, sernum); - - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type boot.\nWhen the kernel has booted" - " please type fsrecover.sh\n"); - - return(1); -} - -U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars, - "Set environment to factory defaults", ""); - -U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover, - "Set environment to allow for fs recovery", ""); diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h deleted file mode 100644 index d64f496..0000000 --- a/board/sandburst/metrobox/metrobox.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __METROBOX_H__ -#define __METROBOX_H__ -/* - * (C) Copyright 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -typedef struct metrobox_board_id_s { - const char name[40]; -} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST; - - -/* Metrobox Opto-FPGA registers and definitions */ -#include "hal_xc_auto.h" -typedef struct opto_fpga_regs_s { - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long status_ul; /* Read Only */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long boardinfo_ul; /* Read Only */ -} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST; - -#endif /* __METROBOX_H__ */ diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h deleted file mode 100644 index 8264f56..0000000 --- a/board/sandburst/metrobox/metrobox_version.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _METROBOX_VERSION_H_ -#define _METROBOX_VERSION_H_ -/* - * (C) Copyright 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#define METROBOX_U_BOOT_REL_STR "Release 2.0.3" - -#endif diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug deleted file mode 100644 index 7ff09c0..0000000 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/sandburst/metrobox/init.o (.text) - arch/powerpc/cpu/ppc4xx/kgdb.o (.text) - arch/powerpc/cpu/ppc4xx/traps.o (.text) - arch/powerpc/cpu/ppc4xx/interrupts.o (.text) - arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text) - arch/powerpc/cpu/ppc4xx/cpu_init.o (.text) - arch/powerpc/cpu/ppc4xx/speed.o (.text) - drivers/net/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - -/* common/env_embedded.o(.text) */ - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/configs/KAREF_defconfig b/configs/KAREF_defconfig deleted file mode 100644 index fcca3c9..0000000 --- a/configs/KAREF_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_KAREF=y diff --git a/configs/METROBOX_defconfig b/configs/METROBOX_defconfig deleted file mode 100644 index 14b471a..0000000 --- a/configs/METROBOX_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_METROBOX=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 2f5034f..92ba1e4 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +KAREF powerpc ppc4xx - - Travis Sawyer +METROBOX powerpc ppc4xx - - Travis Sawyer PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt PCI5441 nios2 - 70fbc461 2014-08-24 Scott McNutt flagadm powerpc mpc8xx aec6f8c5 2014-08-22 Kári Davíðsson diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h deleted file mode 100644 index 546b725..0000000 --- a/include/configs/KAREF.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * (C) Copyright 2004 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference - * design. - ***********************************************************************/ - -/* - * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $ - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_VERY_BIG_RAM 1 -#define CONFIG_VERSION_VARIABLE - -#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) -#define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000) -#define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000) -#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000) -#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) - -/* Here for completeness */ -#define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ -#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_PPC4XX_CH1 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */ -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ - -#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR) - -#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ -#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ -#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ -#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ -#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_PING -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT - - -/* Include NetConsole support */ -#define CONFIG_NETCONSOLE - -/* Include auto complete with tabs */ -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */ - - -/*----------------------------------------------------------------------- - * Console Buffer - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Compact Flash (in true IDE mode) - *----------------------------------------------------------------------*/ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ - -#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride - to get to the correct offset */ -#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ - -/*----------------------------------------------------------------------- - * PCI - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ -#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE) - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ -#endif - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h deleted file mode 100644 index 69ab5bb..0000000 --- a/include/configs/METROBOX.h +++ /dev/null @@ -1,349 +0,0 @@ -/* - * (C) Copyright 2004 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * METROBOX.h - configuration Sandburst MetroBox - ***********************************************************************/ - -/* - * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $ - * - * - * $Log: METROBOX.h,v $ - * Revision 1.21 2005/06/03 15:05:25 tsawyer - * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB - * - * Revision 1.20 2005/04/11 20:51:11 tsawyer - * fix ethernet - * - * Revision 1.19 2005/04/06 15:13:36 tsawyer - * Update appropriate files to coincide with u-boot 1.1.3 - * - * Revision 1.18 2005/03/10 14:16:02 tsawyer - * add def'n for cis8201 short etch option. - * - * Revision 1.17 2005/03/09 19:49:51 tsawyer - * Remove KGDB to allow use of 2nd serial port - * - * Revision 1.16 2004/12/02 19:00:23 tsawyer - * Add misc_init_f to turn on i2c-1 and all four fans before sdram init - * - * Revision 1.15 2004/09/15 18:04:12 tsawyer - * add multiple serial port support - * - * Revision 1.14 2004/09/03 15:27:51 tsawyer - * All metrobox boards are at 66.66 sys clock - * - * Revision 1.13 2004/08/05 20:27:46 tsawyer - * Remove system ace definitions, add net console support - * - * Revision 1.12 2004/07/29 20:00:13 tsawyer - * Add i2c bus 1 - * - * Revision 1.11 2004/07/21 13:44:18 tsawyer - * SystemACE is out, CF direct to local bus is in - * - * Revision 1.10 2004/06/29 19:08:55 tsawyer - * Add CONFIG_MISC_INIT_R - * - * Revision 1.9 2004/06/28 21:30:53 tsawyer - * Fix default BOOTARGS - * - * Revision 1.8 2004/06/17 15:51:08 tsawyer - * auto complete - * - * Revision 1.7 2004/06/17 15:08:49 tsawyer - * Add autocomplete - * - * Revision 1.6 2004/06/15 12:33:57 tsawyer - * debugging checkpoint - * - * Revision 1.5 2004/06/12 19:48:28 tsawyer - * Debugging checkpoint - * - * Revision 1.4 2004/06/02 13:03:06 tsawyer - * Fix eth addrs - * - * Revision 1.3 2004/05/18 19:56:10 tsawyer - * Change default bootcommand to pImage.metrobox - * - * Revision 1.2 2004/05/18 14:13:44 tsawyer - * Add bringup values for bootargs and bootcommand. - * Remove definition of ipaddress and serverip addresses. - * - * Revision 1.1 2004/04/16 15:08:54 tsawyer - * Initial Revision - * - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_METROBOX 1 /* Board is Metrobox */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_VERY_BIG_RAM 1 -#define CONFIG_VERSION_VARIABLE - -#define CONFIG_IDENT_STRING " Sandburst Metrobox" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) -#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000) -#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000) -#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ -#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_PPC4XX_CH1 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */ -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ - -#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR) - -#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none " -#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000" -#define CONFIG_BOOTDELAY 5 /* disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ -#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ -#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ -#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ -#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_PING -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT - - -/* Include NetConsole support */ -#define CONFIG_NETCONSOLE - -/* Include auto complete with tabs */ -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "MetroBox=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */ - - -/*----------------------------------------------------------------------- - * Console Buffer - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Compact Flash (in true IDE mode) - *----------------------------------------------------------------------*/ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ - -#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride - to get to the correct offset */ -#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ - -/*----------------------------------------------------------------------- - * PCI - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ -#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE) - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ -#endif - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */ - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From 1521cdc5303db2a3ec5a09231fbaa5831561bf71 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:58 +0900 Subject: powerpc: ppc4xx: remove board support for CRAYL1 This board has been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 7c645f1..d525ad3 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -106,9 +106,6 @@ config TARGET_FX12MM config TARGET_V5FX30TEVAL bool "Support v5fx30teval" -config TARGET_CRAYL1 - bool "Support CRAYL1" - config TARGET_CATCENTER bool "Support CATcenter" @@ -260,7 +257,6 @@ source "board/amcc/yosemite/Kconfig" source "board/amcc/yucca/Kconfig" source "board/avnet/fx12mm/Kconfig" source "board/avnet/v5fx30teval/Kconfig" -source "board/cray/L1/Kconfig" source "board/csb272/Kconfig" source "board/csb472/Kconfig" source "board/dave/PPChameleonEVB/Kconfig" diff --git a/board/cray/L1/.gitignore b/board/cray/L1/.gitignore deleted file mode 100644 index cd76d66..0000000 --- a/board/cray/L1/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -bootscript.c -bootscript.image diff --git a/board/cray/L1/Kconfig b/board/cray/L1/Kconfig deleted file mode 100644 index 35a290a..0000000 --- a/board/cray/L1/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CRAYL1 - -config SYS_BOARD - default "L1" - -config SYS_VENDOR - default "cray" - -config SYS_CONFIG_NAME - default "CRAYL1" - -endif diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c deleted file mode 100644 index d706ff1..0000000 --- a/board/cray/L1/L1.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define L1_MEMSIZE (32*1024*1024) - -/* the std. DHCP stufff */ -#define DHCP_ROUTER 3 -#define DHCP_NETMASK 1 -#define DHCP_BOOTFILE 67 -#define DHCP_ROOTPATH 17 -#define DHCP_HOSTNAME 12 - -/* some extras used by CRAY - * - * on the server this looks like: - * - * option L1-initrd-image code 224 = string; - * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image" - */ -#define DHCP_L1_INITRD 224 - -/* new, [better?] way via official vendor-extensions, defining an option - * space. - * on the server this looks like: - * - * option space CRAYL1; - * option CRAYL1.initrd code 3 = string; - * ..etc... - */ -#define DHCP_VENDOR_SPECX 43 -#define DHCP_VX_INITRD 3 -#define DHCP_VX_BOOTCMD 4 -#define DHCP_VX_BOOTARGS 5 -#define DHCP_VX_ROOTDEV 6 -#define DHCP_VX_FROMFLASH 7 -#define DHCP_VX_BOOTSCRIPT 8 -#define DHCP_VX_RCFILE 9 -#define DHCP_VX_MAGIC 10 - -/* Things DHCP server can tellme about. If there's no flash address, then - * they dont participate in 'update' to flash, and we force their values - * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I - * know this is a pain... - * - * If I get no bootfile, boot from flash. If rootpath, use that. If no - * rootpath use initrd in flash. - */ -typedef struct dhcp_item_s { - u8 dhcp_option; - u8 dhcp_vendor_option; - char *dhcpvalue; - char *envname; -} dhcp_item_t; -static dhcp_item_t Things[] = { - {DHCP_ROUTER, 0, NULL, "gateway"}, - {DHCP_NETMASK, 0, NULL, "netmask"}, - {DHCP_BOOTFILE, 0, NULL, "bootfile"}, - {DHCP_ROOTPATH, 0, NULL, "rootpath"}, - {DHCP_HOSTNAME, 0, NULL, "hostname"}, - {DHCP_L1_INITRD, 0, NULL, "initrd"}, -/* and the other way.. */ - {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"}, - {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"}, - {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"}, - {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL}, - {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL} -}; - -#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t))) - -extern char bootscript[]; - -/* Here is the boot logic as HUSH script. Overridden by any TFP provided - * bootscript file. - */ - -static void init_sdram (void); - -/* ------------------------------------------------------------------------- */ -int board_early_init_f (void) -{ - /* Running from ROM: global data is still READONLY */ - init_sdram (); - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - return 0; -} - -/* ------------------------------------------------------------------------- */ -int checkboard (void) -{ - return (0); -} -/* ------------------------------------------------------------------------- */ - -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ - char *s, *e; - image_header_t *hdr; - time_t timestamp; - struct rtc_time tm; - char bootcmd[32]; - - hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ()); -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - timestamp = (time_t)image_get_time (hdr); - to_tm (timestamp, &tm); - printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); - -#define FACTORY_SETTINGS 0xFFFC0000 - if ((s = getenv ("ethaddr")) == NULL) { - e = (char *) (FACTORY_SETTINGS); - if (*(e + 0) != '0' - || *(e + 1) != '0' - || *(e + 2) != ':' - || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') { - printf ("No valid MAC address in flash location 0x3C0000!\n"); - } else { - printf ("Factory MAC: %s\n", e); - setenv ("ethaddr", e); - } - } - sprintf (bootcmd,"source %X",(unsigned)bootscript); - setenv ("bootcmd", bootcmd); - return (0); -} - -/* ------------------------------------------------------------------------- */ -/* stubs so we can print dates w/o any nvram RTC.*/ -int rtc_get (struct rtc_time *tmp) -{ - return 0; -} -int rtc_set (struct rtc_time *tmp) -{ - return 0; -} -void rtc_reset (void) -{ - return; -} - -/* ------------------------------------------------------------------------- */ -/* Do sdram bank init in C so I can read it..no console to print to yet! - */ -static void init_sdram (void) -{ - unsigned long tmp; - - /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - mtdcr (SDRAM0_CFGDATA, 0x00062001); - -/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ -/* To set the appropriate timings, we need to know the SDRAM speed. */ -/* We can use the PLB speed since the SDRAM speed is the same as */ -/* the PLB speed. The PLB speed is the FBK divider times the */ -/* 405GP reference clock, which on the L1 is 25MHz. */ -/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */ -/* 150MHz; if FBK is 3, SDRAM is 150MHz. */ - - /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ - -/* write SDRAM timing for 100MHz. */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - mtdcr (SDRAM0_CFGDATA, 0x0086400D); - -/* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - mtdcr (SDRAM0_CFGDATA, 0x05F00000); - udelay (200); - -/* sdram controller.*/ - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, 0x90800000); - udelay (200); - -/* initially, disable ECC on all banks */ - udelay (200); - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp &= 0xff0fffff; - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - mtdcr (SDRAM0_CFGDATA, tmp); - - return; -} - -extern int memory_post_test (int flags); - -int testdram (void) -{ - unsigned long tmp; - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) L1_MEMSIZE; - uint *p; - - if (getenv_f("booted",NULL,0) <= 0) - { - printf ("testdram.."); - /*AA*/ - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, 0xaaaaaaaa); - return 1; - } - } - /*55*/ - for (p = pstart; p < pend; p++) - *p = 0x55555555; - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, 0x55555555); - return 1; - } - } - /*addr*/ - for (p = pstart; p < pend; p++) - *p = (unsigned)p; - for (p = pstart; p < pend; p++) { - if (*p != (unsigned)p) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, (uint)p); - return 1; - } - } - printf ("Success. "); - } - printf ("Enable ECC.."); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (600); - for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) - ; - udelay (400); - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp |= 0x00800000; - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (400); - printf ("enabled.\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ -static u8 *dhcp_env_update (u8 thing, u8 * pop) -{ - u8 i, oplen; - - oplen = *(pop + 1); - - if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) { - printf ("Whoops! failed to malloc space for DHCP thing %s\n", - Things[thing].envname); - return NULL; - } - for (i = 0; (i < oplen); i++) - if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ') - break; - *(Things[thing].dhcpvalue + i) = '\0'; - -/* set env. */ - if (Things[thing].envname) - { - setenv (Things[thing].envname, Things[thing].dhcpvalue); - } - return ((u8 *)(Things[thing].dhcpvalue)); -} - -/* ------------------------------------------------------------------------- */ -u8 *dhcp_vendorex_prep (u8 * e) -{ - u8 thing; - -/* ask for the things I want. */ - *e++ = 55; /* Parameter Request List */ - *e++ = N_THINGS; - for (thing = 0; thing < N_THINGS; thing++) - *e++ = Things[thing].dhcp_option; - *e++ = 255; - - return e; -} - -/* ------------------------------------------------------------------------- */ -/* .. return NULL means it wasnt mine, non-null means I got it..*/ -u8 *dhcp_vendorex_proc (u8 * pop) -{ - u8 oplen, *sub_op, sub_oplen, *retval; - u8 thing = 0; - - retval = NULL; - oplen = *(pop + 1); -/* if pop is vender spec indicator, there are sub-options. */ - if (*pop == DHCP_VENDOR_SPECX) { - for (sub_op = pop + 2; - oplen && (sub_oplen = *(sub_op + 1)); - oplen -= sub_oplen, sub_op += (sub_oplen + 2)) { - for (thing = 0; thing < N_THINGS; thing++) { - if (*sub_op == Things[thing].dhcp_vendor_option) { - if (!(retval = dhcp_env_update (thing, sub_op))) { - return NULL; - } - } - } - } - } else { - for (thing = 0; thing < N_THINGS; thing++) { - if (*pop == Things[thing].dhcp_option) - if (!(retval = dhcp_env_update (thing, pop))) - return NULL; - } - } - return (pop); -} diff --git a/board/cray/L1/MAINTAINERS b/board/cray/L1/MAINTAINERS deleted file mode 100644 index e43e91f..0000000 --- a/board/cray/L1/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -L1 BOARD -#M: David Updegraff -S: Orphan (since 2014-03) -F: board/cray/L1/ -F: include/configs/CRAYL1.h -F: configs/CRAYL1_defconfig diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile deleted file mode 100644 index 716a5a3..0000000 --- a/board/cray/L1/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = L1.o flash.o -obj-y += init.o -obj-y += bootscript.o - -quiet_cmd_awk = AWK $@ - cmd_awk = od -t x1 -v -A x $< | $(AWK) -f $(filter-out $<,$^) > $@ - -$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk - $(call cmd,awk) - -MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \ - -a 0 -e 0 -n bootscript -$(obj)/bootscript.image: $(src)/bootscript.hush - $(call cmd,mkimage) - -clean-files := bootscript.c bootscript.image diff --git a/board/cray/L1/bootscript.hush b/board/cray/L1/bootscript.hush deleted file mode 100644 index f2f78ad..0000000 --- a/board/cray/L1/bootscript.hush +++ /dev/null @@ -1,117 +0,0 @@ -# $Header$ -# hush bootscript for PPCBOOT on L1 -# note: all #s are in hex, do _NOT_ prefix it with 0x - -flash_rfs=ffc00000 -flash_krl=fff00000 -tftp_addr=100000 -tftp2_addr=1000000 - -if printenv booted -then - echo already booted before -else - echo first boot in environment, create and save settings - setenv booted OK - saveenv -fi - -setenv autoload no -# clear out stale env stuff, so we get fresh from dhcp. -for setting in initrd fromflash kernel rootfs rootpath -do -setenv $setting -done - -dhcp - -# if host provides us with a different bootscript, us it. -if printenv bootscript - then - tftp $tftp_addr $bootcript - if imi $tftp_addr - then - source $tftp_addr - fi -fi - -# default base kernel arguments. -setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120 - -# Have a kernel in flash? -if imi $flash_krl -then - echo ok kernel to boot from $flash_krl - setenv kernel $flash_krl -else - echo no kernel to boot from $flash_krl, need tftp -fi - -# Have a rootfs in flash? -echo test for SQUASHfs at $flash_rfs - -if imi $flash_rfs -then - echo appears to be a good initrd image at base of flash OK - setenv rootfs $flash_rfs -else - echo no image at base of flash, need nfsroot or initrd -fi - -# I boot from flash if told to and I can. -if printenv fromflash && printenv kernel && printenv rootfs -then - echo booting entirely from flash - setenv bootargs root=/dev/ram0 rw $bootargs - bootm $kernel $rootfs - echo oh no failed so I try some other stuff -fi - -# TFTP down a kernel -if printenv bootfile -then - tftp $tftp_addr $bootfile - setenv kernel $tftp_addr - echo I will boot the TFTP kernel -else - if printenv kernel - then - echo no bootfile specified, will use one from flash - else - setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image - echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile - tftp $tftp_addr $bootfile - setenv kernel $tftp_addr - fi -fi - -# the rootfs. -if printenv rootpath -then - echo rootpath is $rootpath - if printenv initrd - then - echo initrd is also specified, so use $initrd - tftp $tftp2_addr $initrd - setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs - bootm $kernel $tftp2_addr - else - echo initrd is not specified, so use NFSROOT $rootpat - setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs - bootm $kernel - fi -else - echo we have no rootpath check for one in flash - if printenv rootfs - then - echo I will use the one in flash - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs - bootm $kernel - else - setenv rootpath /export/crayl1 - echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs - bootm $kernel - fi -fi -reset diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c deleted file mode 100644 index 96a1e47..0000000 --- a/board/cray/L1/flash.c +++ /dev/null @@ -1,451 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -/* - * Modified July 20, 2001 - * Strip down to support ONLY the AMD29F032B. - * Dave Updegraff - Cray, Inc. dave@cray.com - */ - -#include -#include -#include - -/* The flash chip we use... */ -#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */ -#define FLASH_AM320B 0x0009 - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; isector_count; i++) - info->start[i] = base + (i * 0x00010000); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F032B: - info->flash_id += FLASH_AM320B; - info->sector_count = 64; - info->size = 0x0400000; /* => 4 MB */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S deleted file mode 100644 index d4723c7..0000000 --- a/board/cray/L1/init.S +++ /dev/null @@ -1,117 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ - -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*-----------------------------------------------------------------------------#include */ -#include - -#include -#include - -#include -#include - -/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */ -/* except for #1 which we use for DMA'ing to IOCA-like things, so the */ -/* control registers to set that up are determined by what we've */ -/* empirically discovered work there. */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - /*------------------------------------------------------------------- */ - /* Delay to ensure all accesses to ROM are complete before changing */ - /* bank 0 timings. 200usec should be enough. */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - - /*---------------------------------------------------------------------- */ - /* Peripheral Bank 0 (Flash) initialization */ - /*---------------------------------------------------------------------- */ - /* 0x7F8FFE80 slowest boot */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x9B01 - ori r4,r4,0x5480 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr EBC0_CFGDATA,r4 - - blr - - /*---------------------------------------------------------------------- */ - /* Peripheral Bank 1 (NVRAM/RTC) initialization */ - /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */ - /* and we do DMA on it. The ConfigurationRegister part is threfore */ - /* almost arbitrary, except that our linux driver needs to know the */ - /* address, but it can query, it.. */ - /* */ - /* The AccessParameter is CRITICAL, */ - /* thouch, since it needs to agree with the electrical timings on the */ - /* IOCA parallel interface. That value is: 0x0185,4380 */ - /* BurstModeEnable BME=0 */ - /* TransferWait TWT=3 */ - /* ChipSelectOnTiming CSN=1 */ - /* OutputEnableOnTimimg OEN=1 */ - /* WriteByteEnableOnTiming WBN=1 */ - /* WriteByteEnableOffTiming WBF=0 */ - /* TransferHold TH=1 */ - /* ReadyEnable RE=1 */ - /* SampleOnReady SOR=1 */ - /* ByteEnableMode BEM=0 */ - /* ParityEnable PEN=0 */ - /* all reserved bits=0 */ - /*---------------------------------------------------------------------- */ - /*---------------------------------------------------------------------- */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0185 /* hiword */ - ori r4,r4,0x4380 /* loword */ - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB1CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr EBC0_CFGDATA,r4 - - blr diff --git a/board/cray/L1/patchme b/board/cray/L1/patchme deleted file mode 100644 index e77ee7e..0000000 --- a/board/cray/L1/patchme +++ /dev/null @@ -1,30 +0,0 @@ -# master confi.mk -echo "CROSS_COMPILE = powerpc-linux-" >>include/config.mk - -# patch the examples/Makefile to ignore return value from OBJCOPY -sed -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile - -# add a built target for mkimage on the target architecture -sed -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile - -cat <>tools/makefile -mkimage.ppc : mkimage.o.ppc crc32.o.ppc - powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^ - powerpc-linux-strip $@ - -XFLAGS="-D__KERNEL__ -I../include -DCONFIG_4xx -Wall -Wstict-prototypes" -mkimage.o.ppc: mkimage.c - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ - -crc32.o.ppc: crc32.c - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ - -EOF - -# make an image by default out of the u-boot image -sed -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile -cat <>makefile -u-boot.image: u-boot.bin - tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@ - -EOF diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug deleted file mode 100644 index 890f592..0000000 --- a/board/cray/L1/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/cray/L1/x2c.awk b/board/cray/L1/x2c.awk deleted file mode 100644 index 9235e6c..0000000 --- a/board/cray/L1/x2c.awk +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/awk -BEGIN { print "unsigned char bootscript[] = { \n"} -{ for (i = 2; i <= NF ; i++ ) printf "0x"$i"," - print "" -} -END { print "\n};\n" } diff --git a/configs/CRAYL1_defconfig b/configs/CRAYL1_defconfig deleted file mode 100644 index ad6cbac..0000000 --- a/configs/CRAYL1_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_CRAYL1=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 92ba1e4..48e94ab 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +CRAYL1 powerpc ppc4xx - - David Updegraff KAREF powerpc ppc4xx - - Travis Sawyer METROBOX powerpc ppc4xx - - Travis Sawyer PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h deleted file mode 100644 index 788fa0f..0000000 --- a/include/configs/CRAYL1.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite.. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_CRAYL1 -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ - -/* - * Note: I make an "image" from U-Boot itself, which prefixes 0x40 - * bytes of header info, hence start address is thus shifted. - */ -#define CONFIG_SYS_TEXT_BASE 0xFFFD0040 - -#define CONFIG_SYS_CLK_FREQ 25000000 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */ -#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to - * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) - #define CONFIG_PRAM 16 - */ -#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */ -#undef CONFIG_BOOTARGS - -/* Bootcmd is overridden by the bootscript in board/cray/L1 - */ -#define CONFIG_SYS_AUTOLOAD "no" -#define CONFIG_BOOTCOMMAND "dhcp" - -/* - * ..during experiments.. - #define CONFIG_SERVERIP 10.0.0.1 - #define CONFIG_ETHADDR 00:40:a6:80:14:5 - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SDRAM_BANK0 1 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_IDENT_STRING "Cray L1" -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SOURCE 1 - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SETGETDCR -#define CONFIG_CMD_SOURCE - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * how many time to fail & restart a net-TFTP before giving up & resetting - * the board hoping that a reset of net interface might help.. - */ -#define CONFIG_NET_RESET 5 - -/* - * bauds. Just to make it compile; in our case, I read the base_baud - * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn - * drives the system clock. - */ -#define CONFIG_SYS_BASE_BAUD 403225 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_DRAM_TEST 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */ -#define CONFIG_ENV_OFFSET 0x3c8000 -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment area */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at - * 32meg-(128k+some_malloc_space+copy-of-ENV sector).. - */ -#define CONFIG_SYS_SDRAM_SIZE 32 /* megs of ram */ -#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128k for malloc space */ -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ - + CONFIG_SYS_MALLOC_LEN \ - + CONFIG_ENV_SECT_SIZE \ - + CONFIG_SYS_STACK_USAGE ) - -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE) -/* END ENVIRONNEMENT FLASH */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in OnChipMem ) - */ -#if 1 -/* On Chip Memory location */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#endif - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - */ -#define EEPROM_WRITE_ADDRESS 0xA0 -#define EEPROM_READ_ADDRESS 0xA1 - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From 9ed3246e19a42392bf0fd676dcbbe3539cc46ec1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:59 +0900 Subject: powerpc: ppc4xx: remove board support for bluestone This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: Masahiro Yamada diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index d525ad3..56abe8d 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -52,9 +52,6 @@ config TARGET_ACADIA config TARGET_BAMBOO bool "Support bamboo" -config TARGET_BLUESTONE - bool "Support bluestone" - config TARGET_BUBINGA bool "Support bubinga" @@ -239,7 +236,6 @@ endchoice source "board/amcc/acadia/Kconfig" source "board/amcc/bamboo/Kconfig" -source "board/amcc/bluestone/Kconfig" source "board/amcc/bubinga/Kconfig" source "board/amcc/canyonlands/Kconfig" source "board/amcc/ebony/Kconfig" diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 6a48526..aab65d4 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -234,20 +234,6 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif -#if defined(CONFIG_APM821XX) -#define SDR0_PINSTP_SHIFT 29 -static char *bootstrap_str[] = { - "RESERVED", - "RESERVED", - "RESERVED", - "NAND (8 bits)", - "NOR (8 bits)", - "NOR (8 bits) w/PLL Bypassed", - "I2C (Addr 0x54)", - "I2C (Addr 0x52)", -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; -#endif #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index 0b27d29..2256123 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -284,7 +284,7 @@ cpu_init_f (void) reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \ - !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE) + !defined(CONFIG_SYS_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -440,7 +440,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 4baee77..3e1a701 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -171,7 +171,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) static u8 pll_fwdv_multi_bits[] = { /* values for: 1 - 16 */ 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, @@ -232,78 +232,6 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) return 0; } -#if defined(CONFIG_APM821XX) - -void get_sys_info(sys_info_t *sysInfo) -{ - unsigned long plld; - unsigned long temp; - unsigned long mul; - unsigned long cpudv; - unsigned long plb2dv; - unsigned long ddr2dv; - - /* Calculate Forward divisor A and Feeback divisor */ - mfcpr(CPR0_PLLD, plld); - - temp = CPR0_PLLD_FWDVA(plld); - sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); - - temp = CPR0_PLLD_FDV(plld); - sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); - - /* Calculate OPB clock divisor */ - mfcpr(CPR0_OPBD, temp); - temp = CPR0_OPBD_OPBDV(temp); - sysInfo->pllOpbDiv = temp ? temp : 4; - - /* Calculate Peripheral clock divisor */ - mfcpr(CPR0_PERD, temp); - temp = CPR0_PERD_PERDV(temp); - sysInfo->pllExtBusDiv = temp ? temp : 4; - - /* Calculate CPU clock divisor */ - mfcpr(CPR0_CPUD, temp); - temp = CPR0_CPUD_CPUDV(temp); - cpudv = temp ? temp : 8; - - /* Calculate PLB2 clock divisor */ - mfcpr(CPR0_PLB2D, temp); - temp = CPR0_PLB2D_PLB2DV(temp); - plb2dv = temp ? temp : 4; - - /* Calculate DDR2 clock divisor */ - mfcpr(CPR0_DDR2D, temp); - temp = CPR0_DDR2D_DDR2DV(temp); - ddr2dv = temp ? temp : 4; - - /* Calculate 'M' based on feedback source */ - mfcpr(CPR0_PLLC, temp); - temp = CPR0_PLLC_SEL(temp); - if (temp == 0) { - /* PLL internal feedback */ - mul = sysInfo->pllFbkDiv; - } else { - /* PLL PerClk feedback */ - mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv - * plb2dv * 2 * sysInfo->pllOpbDiv * - sysInfo->pllExtBusDiv; - } - - /* Now calculate the individual clocks */ - sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1); - sysInfo->freqProcessor = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv; - sysInfo->freqPLB = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv / plb2dv / 2; - sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; - sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; - sysInfo->freqDDR = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv / ddr2dv / 2; - sysInfo->freqUART = sysInfo->freqPLB; -} - -#else /* * AMCC_TODO: verify this routine against latest EAS, cause stuff changed * with latest EAS @@ -361,7 +289,6 @@ void get_sys_info (sys_info_t * sysInfo) return; } -#endif #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 11b55d5..09a02d7 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -664,8 +664,7 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -694,7 +693,7 @@ _start: ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ - defined(CONFIG_460GT) || defined(CONFIG_APM821XX) + defined(CONFIG_460GT) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -707,8 +706,7 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) lis r2,0x7fff ori r2,r2,0xffff mfdcr r1,ISRAM1_DPC diff --git a/arch/powerpc/include/asm/apm821xx.h b/arch/powerpc/include/asm/apm821xx.h deleted file mode 100644 index d027866..0000000 --- a/arch/powerpc/include/asm/apm821xx.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _APM821XX_H_ -#define _APM821XX_H_ - -#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ - -/* Memory mapped registers */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) - -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) - -#define SDR0_SRST0_DMC 0x00200000 -#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ - -/* AHB config. */ -#define AHB_TOP 0xA4 -#define AHB_BOT 0xA5 - -/* clk divisors */ -#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ -#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ -#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ -#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ -#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ -#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ -#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/ -#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ -#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ - -/* - + * Clocking Controller - + */ -#define CPR0_CLKUPD 0x0020 -#define CPR0_PLLC 0x0040 -#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) -#define CPR0_PLLD 0x0060 -#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) -#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) -#define CPR0_CPUD 0x0080 -#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) -#define CPR0_PLB2D 0x00a0 -#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) -#define CPR0_OPBD 0x00c0 -#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) -#define CPR0_PERD 0x00e0 -#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) -#define CPR0_DDR2D 0x0100 -#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) -#define CLK_ICFG 0x0140 - -#endif /* _APM821XX_H_ */ diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 07a3fe0..952783f 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -53,8 +53,7 @@ #define EBC_NUM_BANKS 6 #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define EBC_NUM_BANKS 3 #endif diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index 4d1106b..2ae399f 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -8,8 +8,7 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -26,8 +25,7 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -41,8 +39,6 @@ #if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ISRAM1_SIZE 0x0984 /* OCM size 64k */ -#elif defined(CONFIG_APM821XX) -#define ISRAM1_SIZE 0x0784 /* OCM size 32k */ #endif /* @@ -51,7 +47,7 @@ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 12d6d03..e6fed83 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -276,7 +276,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -349,7 +349,7 @@ /* * Memory controller registers */ -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) +#if defined(CONFIG_405EX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -359,9 +359,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX || CONFIG_APM821XX */ +#else /* CONFIG_405EX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX || CONFIG_APM821XX */ +#endif /* CONFIG_405EX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -407,12 +407,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX) +#if !defined(CONFIG_405EX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) +#if defined(CONFIG_405EX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 05b4690..58e65c1 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -15,7 +15,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -236,8 +236,7 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h index e6a3bff..b8b0ff9 100644 --- a/arch/powerpc/include/asm/ppc4xx.h +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -56,10 +56,6 @@ #include #endif -#if defined(CONFIG_APM821XX) -#include -#endif - /* * Common registers for all SoC's */ diff --git a/board/amcc/bluestone/Kconfig b/board/amcc/bluestone/Kconfig deleted file mode 100644 index 255e013..0000000 --- a/board/amcc/bluestone/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_BLUESTONE - -config SYS_BOARD - default "bluestone" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "bluestone" - -endif diff --git a/board/amcc/bluestone/MAINTAINERS b/board/amcc/bluestone/MAINTAINERS deleted file mode 100644 index 9eb9bbd..0000000 --- a/board/amcc/bluestone/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BLUESTONE BOARD -#M: Tirumala Marri -S: Orphan (since 2014-03) -F: board/amcc/bluestone/ -F: include/configs/bluestone.h -F: configs/bluestone_defconfig diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile deleted file mode 100644 index 07320ce..0000000 --- a/board/amcc/bluestone/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2010, Applied Micro Circuits Corporation -# Author: Tirumala R Marri -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := bluestone.o -extra-y += init.o diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c deleted file mode 100644 index 6520f75..0000000 --- a/board/amcc/bluestone/bluestone.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Bluestone board support - * - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int board_early_init_f(void) -{ - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - - /* - * Configure PFC (Pin Function Control) registers - * UART0: 2 pins - */ - mtsdr(SDR0_PFC1, 0x0000000); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Bluestone Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int misc_init_r(void) -{ - u32 sdr0_srst1 = 0; - - /* Setup PLB4-AHB bridge based on the system address map */ - mtdcr(AHB_TOP, 0x8000004B); - mtdcr(AHB_BOT, 0x8000004B); - - /* - * The AHB Bridge core is held in reset after power-on or reset - * so enable it now - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_AHB; - mtsdr(SDR0_SRST1, sdr0_srst1); - - return 0; -} diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk deleted file mode 100644 index a947e82..0000000 --- a/board/amcc/bluestone/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2010, Applied Micro Circuits Corporation -# Author: Tirumala R Marri -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Applied Micro APM821XX Evaluation board. -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S deleted file mode 100644 index cf22ca6..0000000 --- a/board/amcc/bluestone/init.S +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* TLB 0 */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, - 4, AC_RWX | SA_G) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_RWX | SA_G) - - /* TLB-entry for OCM */ - tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, - AC_RWX | SA_I) - - /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, - CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) - tlbtab_end diff --git a/configs/bluestone_defconfig b/configs/bluestone_defconfig deleted file mode 100644 index 8f83a43..0000000 --- a/configs/bluestone_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_BLUESTONE=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 48e94ab..036bc83 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +bluestone powerpc ppc4xx - - Tirumala Marri CRAYL1 powerpc ppc4xx - - David Updegraff KAREF powerpc ppc4xx - - Travis Sawyer METROBOX powerpc ppc4xx - - Travis Sawyer diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h deleted file mode 100644 index 8bd71c6..0000000 --- a/include/configs/bluestone.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * bluestone.h - configuration for Bluestone (APM821XX) - * - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_APM821XX 1 /* APM821XX series */ -#define CONFIG_HOSTNAME bluestone - -#define CONFIG_440 1 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 -#endif - -/* - * Include common defines/options for all AMCC eval boards - */ -#include "amcc-common.h" -#define CONFIG_SYS_CLK_FREQ 50000000 - -#define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -/* EBC stuff */ -/* later mapped to this addr */ -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */ - -/* EBC Boot Space: 0xFF000000 */ -#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 -#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */ -#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ -#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/ - -#define CONFIG_SYS_SRAM_SIZE (256 << 10) -/* - * Initial RAM & stack pointer (placed in OCM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Environment - */ -/* - * Define here the location of the environment variables (FLASH). - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/* - * FLASH related - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -/* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 80 -/* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 -/* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 -/* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/* SDRAM */ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */ -#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ -#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ -#define CONFIG_DDR_ECC 1 /* with ECC support */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ - -/* - * I2C - */ -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */ - -/* I2C bootstrap EEPROM */ -#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 -#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 -#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 - -/* - * Ethernet - */ -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII -#define CONFIG_HAS_ETH0 -/* PHY address, See schematics */ -#define CONFIG_PHY_ADDR 0x1f -/* reset phy upon startup */ -#define CONFIG_PHY_RESET 1 -/* Include GbE speed/duplex detection */ -#define CONFIG_PHY_GIGE 1 -#define CONFIG_PHY_DYNAMIC_ANEG 1 - -/* - * External Bus Controller (EBC) Setup - **/ -#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \ - EBC_CFG_PTD_ENABLE | \ - EBC_CFG_RTC_2048PERCLK | \ - EBC_CFG_ATC_HI | \ - EBC_CFG_DTC_HI | \ - EBC_CFG_CTC_HI | \ - EBC_CFG_OEO_PREVIOUS) -/* NOR Flash */ -#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(64) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(1) | \ - EBC_BXAP_OEN_ENCODE(2) | \ - EBC_BXAP_WBN_ENCODE(2) | \ - EBC_BXAP_WBF_ENCODE(2) | \ - EBC_BXAP_TH_ENCODE(7) | \ - EBC_BXAP_SOR_DELAYED | \ - EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED) -/* Peripheral Bank Configuration Register - EBC_BxCR */ -#define CONFIG_SYS_EBC_PB0CR \ - (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ - EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_8BIT) - - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From e7a565638a7a727f1a4074c0b39e7de22ff3d6c9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:38:00 +0900 Subject: powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7 These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 6de9265..42e0e29 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -64,12 +64,6 @@ config TARGET_SUVD3 config TARGET_TUXX1 bool "Support tuxx1" -config TARGET_MERGERBOX - bool "Support MERGERBOX" - -config TARGET_MVBLM7 - bool "Support MVBLM7" - config TARGET_TQM834X bool "Support TQM834x" @@ -89,8 +83,6 @@ source "board/freescale/mpc837xemds/Kconfig" source "board/freescale/mpc837xerdb/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/km83xx/Kconfig" -source "board/matrix_vision/mergerbox/Kconfig" -source "board/matrix_vision/mvblm7/Kconfig" source "board/mpc8308_p1m/Kconfig" source "board/sbc8349/Kconfig" source "board/tqc/tqm834x/Kconfig" diff --git a/board/matrix_vision/mergerbox/Kconfig b/board/matrix_vision/mergerbox/Kconfig deleted file mode 100644 index 3857535..0000000 --- a/board/matrix_vision/mergerbox/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MERGERBOX - -config SYS_BOARD - default "mergerbox" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MERGERBOX" - -endif diff --git a/board/matrix_vision/mergerbox/MAINTAINERS b/board/matrix_vision/mergerbox/MAINTAINERS deleted file mode 100644 index 20bd073..0000000 --- a/board/matrix_vision/mergerbox/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MERGERBOX BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mergerbox/ -F: include/configs/MERGERBOX.h -F: configs/MERGERBOX_defconfig diff --git a/board/matrix_vision/mergerbox/Makefile b/board/matrix_vision/mergerbox/Makefile deleted file mode 100644 index 11a7fd2..0000000 --- a/board/matrix_vision/mergerbox/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mergerbox.o pci.o fpga.o sm107.o diff --git a/board/matrix_vision/mergerbox/README b/board/matrix_vision/mergerbox/README deleted file mode 100644 index 1994b65..0000000 --- a/board/matrix_vision/mergerbox/README +++ /dev/null @@ -1,59 +0,0 @@ -Matrix Vision MergerBox ------------------------ - -1. Board Description - - The MergerBox is a 120x160mm single board computing platform - for 3D Full-HD digital video processing. - - Power Supply is 10-32VDC. - -2 System Components - -2.1 CPU - Freescale MPC8377 CPU running at 800MHz core and 333MHz csb. - 256 MByte DDR-II memory @ 333MHz data rate. - 64 MByte Nor Flash on local bus. - 1 GByte Nand Flash on FCM. - 1 Vitesse VSC8601 RGMII ethernet Phys. - 1 USB host controller over ULPI I/F with 4-Port hub. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt. - 2 PCIe x1 busses on local mPCIe and cutom expansion connector. - 2 SATA host ports. - System configuration (HRCW) is taken from I2C EEPROM. - -2.2 Graphics - SM107 emebedded video controller driving a 5" 800x480 TFT panel. - Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory. - -2.3 FPGA - Altera Cyclone-IV EP4C115 with several PCI DMA engines. - Connects to 7x Gennum 3G-SDI transceivers as video interconnect - as well as a HDMI v1.4 compliant output for 3D monitoring. - Utilizes two more DDR-II controllers providing 256MB memory. - -2.4 I2C - Bus1: - AD7418 @ 0x50 for voltage/temp. monitoring. - SX8650 @ 0x90 touch controller for HMI. - EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - Bus2: - mPCIe SMBus - SiI9022A @ 0x72/0xC0 HDMI transmitter. - TCA6416A @ 0x40 + 0x42 16-Bit I/O expander. - LMH1983 @ 0xCA video PLL. - DS1338C @ 0xD0 real-time clock with embedded crystal. - 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock. - -3 Flash layout. - - reset vector is 0x00000100, i.e. low boot. - - 00000000 u-boot binary. - 00100000 FPGA raw bit file. - 00300000 FIT image holding kernel, dtb and rescue squashfs. - 03d00000 u-boot environment. - 03e00000 splash image - - mtd partitions are propagated to linux kernel via device tree blob. diff --git a/board/matrix_vision/mergerbox/fpga.c b/board/matrix_vision/mergerbox/fpga.c deleted file mode 100644 index 57552c1..0000000 --- a/board/matrix_vision/mergerbox/fpga.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2011 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mergerbox_init_fpga(void) -{ - debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - dvo &= ~FPGA_CONFIG; - gpio->dat = dvo; - udelay(5); - dvo |= FPGA_CONFIG; - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - debug("high\n"); - result = 1; - } else - debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int result = 0; - - debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - debug("high\n"); - result = 1; - } else - debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - debug("\n"); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mergerbox/fpga.h b/board/matrix_vision/mergerbox/fpga.h deleted file mode 100644 index dbe9bff..0000000 --- a/board/matrix_vision/mergerbox/fpga.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mergerbox_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mergerbox/mergerbox.c b/board/matrix_vision/mergerbox/mergerbox.c deleted file mode 100644 index 5c891d1..0000000 --- a/board/matrix_vision/mergerbox/mergerbox.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" -#include "../common/mv_common.h" - -static void setup_serdes(void) -{ - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram(void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - -phys_size_t initdram(int board_type) -{ - u32 msize; - - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; - - /* Enable PCI_CLK[0:1] */ - clk->occr |= 0xc0000000; - udelay(2000); - -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize_log2; - - msize = CONFIG_SYS_DDR_SIZE; - msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - udelay(50000); - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(1000); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - udelay(1000); - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - __asm__ __volatile__("sync"); - udelay(1000); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - udelay(2000); -#endif - setup_serdes(); - - return msize << 20; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision MergerBox\n"); - - return 0; -} - -int misc_init_r(void) -{ - u16 dim; - int result; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1]; - unsigned char mac[6], mac_verify[6]; - char *s = getenv("reset_env"); - - for (dim = 10; dim < 180; dim += 5) { - mergerbox_tft_dim(dim); - udelay(100000); - } - - if (s) - mv_reset_environment(); - - i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac)); - - /* check if Matrix Vision prefix present and export to env */ - if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) { - printf("valid MAC found in eeprom: %pM\n", mac); - eth_setenv_enetaddr("ethaddr", mac); - } else { - printf("no valid MAC found in eeprom.\n"); - - /* no: check the env */ - if (!eth_getenv_enetaddr("ethaddr", mac)) { - printf("no valid MAC found in env either.\n"); - /* TODO: ask for valid MAC */ - } else { - printf("valid MAC found in env: %pM\n", mac); - printf("updating MAC in eeprom.\n"); - - do { - result = test_and_clear_bit(20, &gpio->dat); - if (result) - printf("unprotect EEPROM failed !\n"); - udelay(20000); - } while(result); - - i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6); - udelay(20000); - - do { - result = test_and_set_bit(20, &gpio->dat); - if (result) - printf("protect EEPROM failed !\n"); - udelay(20000); - } while(result); - - printf("verify MAC %pM ... ", mac); - i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6); - - if (!strncmp((char *)mac, (char *)mac_verify, 6)) - printf("ok.\n"); - else - /* TODO: retry or do something useful */ - printf("FAILED (got %pM) !\n", mac_verify); - } - } - - return 0; -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~TFT_SPI_CPLD_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= TFT_SPI_CPLD_CS; -} - -/* control backlight pwm (display brightness). - * allow values 0-250 with 0 = turn off and 250 = max brightness - */ -void mergerbox_tft_dim(u16 value) -{ - struct spi_slave *slave; - u16 din; - u16 dout = 0; - - if (value > 0 && value < 250) - dout = 0x4000 | value; - - slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH); - spi_claim_bus(slave); - spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END); - spi_release_bus(slave); - spi_free_slave(slave); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - fdt_fixup_dr_usb(blob, bd); - ft_pci_setup(blob, bd); -} diff --git a/board/matrix_vision/mergerbox/mergerbox.h b/board/matrix_vision/mergerbox/mergerbox.h deleted file mode 100644 index 53eab28..0000000 --- a/board/matrix_vision/mergerbox/mergerbox.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MERGERBOX_H__ -#define __MERGERBOX_H__ - -#define MV_GPIO - -/* - * GPIO Bank 1 - */ -#define TFT_SPI_EN (0x80000000>>0) -#define FPGA_CONFIG (0x80000000>>1) -#define FPGA_STATUS (0x80000000>>2) -#define FPGA_CONF_DONE (0x80000000>>3) -#define FPGA_DIN (0x80000000>>4) -#define FPGA_CCLK (0x80000000>>5) -#define MAN_RST (0x80000000>>6) -#define FPGA_SYS_RST (0x80000000>>7) -#define WD_WDI (0x80000000>>8) -#define TFT_RST (0x80000000>>9) -#define HISCON_GPIO1 (0x80000000>>10) -#define HISCON_GPIO2 (0x80000000>>11) -#define B2B_GPIO2 (0x80000000>>12) -#define CCU_GPIN (0x80000000>>13) -#define CCU_GPOUT (0x80000000>>14) -#define TFT_GPIO0 (0x80000000>>15) -#define TFT_GPIO1 (0x80000000>>16) -#define TFT_GPIO2 (0x80000000>>17) -#define TFT_GPIO3 (0x80000000>>18) -#define B2B_GPIO0 (0x80000000>>19) -#define B2B_GPIO1 (0x80000000>>20) -#define TFT_SPI_CPLD_CS (0x80000000>>21) -#define TFT_SPI_CS (0x80000000>>22) -#define CCU_PWR_EN (0x80000000>>23) -#define B2B_GPIO3 (0x80000000>>24) -#define CCU_PWR_STAT (0x80000000>>25) - -#define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS) -#define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \ - TFT_SPI_CPLD_CS) -#define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST) - -/* - * GPIO Bank 2 - */ -#define SPI_FLASH_WP (0x80000000>>10) -#define SYS_EEPROM_WP (0x80000000>>11) -#define SPI_FLASH_CS (0x80000000>>22) - -#define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS) -#define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS) -#define MV_GPIO2_ODE 0 - -void mergerbox_tft_dim(u16 value); - -#endif diff --git a/board/matrix_vision/mergerbox/pci.c b/board/matrix_vision/mergerbox/pci.c deleted file mode 100644 index 480f3ed..0000000 --- a/board/matrix_vision/mergerbox/pci.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" -#include "../common/mv_common.h" - -static struct pci_region pci_regions[] = { - { - .bus_start = CONFIG_SYS_PCI_MEM_BASE, - .phys_start = CONFIG_SYS_PCI_MEM_PHYS, - .size = CONFIG_SYS_PCI_MEM_SIZE, - .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - .bus_start = CONFIG_SYS_PCI_MMIO_BASE, - .phys_start = CONFIG_SYS_PCI_MMIO_PHYS, - .size = CONFIG_SYS_PCI_MMIO_SIZE, - .flags = PCI_REGION_MEM - }, - { - .bus_start = CONFIG_SYS_PCI_IO_BASE, - .phys_start = CONFIG_SYS_PCI_IO_PHYS, - .size = CONFIG_SYS_PCI_IO_SIZE, - .flags = PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - - volatile gpio83xx_t *gpio; - gpio = (gpio83xx_t *)&immr->gpio[0]; - - gpio->dat = MV_GPIO1_DAT; - gpio->odr = MV_GPIO1_ODE; - gpio->dir = MV_GPIO1_OUT; - - gpio = (gpio83xx_t *)&immr->gpio[1]; - - gpio->dat = MV_GPIO2_DAT; - gpio->odr = MV_GPIO2_ODE; - gpio->dir = MV_GPIO2_OUT; - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - /* Enable PCI_CLK[0:1] */ - clk->occr |= 0xc0000000; - udelay(2000); - - mergerbox_init_fpga(); - mv_load_fpga(); - - mergerbox_tft_dim(0); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - udelay(2000); - - mpc83xx_pci_init(1, reg); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(2, pcie_reg); -} diff --git a/board/matrix_vision/mergerbox/sm107.c b/board/matrix_vision/mergerbox/sm107.c deleted file mode 100644 index d24f926..0000000 --- a/board/matrix_vision/mergerbox/sm107.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "../common/mv_common.h" - -#ifdef CONFIG_VIDEO -static const SMI_REGS init_regs_800x480[] = { - /* set endianess to little endian */ - {0x0005c, 0x00000000}, - /* PCI drive 12mA */ - {0x00004, 0x42401001}, - /* current clock */ - {0x0003c, 0x310a1818}, - /* clocks for pm0... */ - {0x00040, 0x0002184f}, - {0x00044, 0x2a1a0a01}, - /* GPIO */ - {0x10008, 0x00000000}, - {0x1000C, 0x00000000}, - /* panel control regs */ - {0x80000, 0x0f017106}, - {0x80004, 0x0}, - {0x80008, 0x0}, - {0x8000C, 0x00000000}, - {0x80010, 0x0c800c80}, - /* width 0x320 */ - {0x80014, 0x03200000}, - /* height 0x1e0 */ - {0x80018, 0x01E00000}, - {0x8001C, 0x0}, - {0x80020, 0x01df031f}, - {0x80024, 0x041f031f}, - {0x80028, 0x00800347}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e9}, - {0x80200, 0x00000000}, - /* ZV[0:7] */ - {0x00008, 0x00ff0000}, - /* 24-Bit TFT */ - {0x0000c, 0x3f000000}, - {0, 0} -}; - -/* - * Returns SM107 register base address. First thing called in the driver. - */ -unsigned int board_video_init(void) -{ - pci_dev_t devbusfn; - u32 addr; - - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, - (u32 *)&addr); - return addr & 0xfffffffe; - } - - return 0; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen(unsigned int base) -{ -} - -/* - * Returns SM107 framebuffer address - */ -unsigned int board_video_get_fb(void) -{ - pci_dev_t devbusfn; - u32 addr; - - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, - (u32 *)&addr); - addr &= 0xfffffffe; -#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET - addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; -#endif - return addr; - } - - printf("board_video_get_fb(): FAILED\n"); - - return 0; -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs(void) -{ - return init_regs_800x480; -} - -int board_get_width(void) -{ - return 800; -} - -int board_get_height(void) -{ - return 480; -} -#endif diff --git a/board/matrix_vision/mvblm7/.gitignore b/board/matrix_vision/mvblm7/.gitignore deleted file mode 100644 index 469f1bc..0000000 --- a/board/matrix_vision/mvblm7/.gitignore +++ /dev/null @@ -1 +0,0 @@ -bootscript.img diff --git a/board/matrix_vision/mvblm7/Kconfig b/board/matrix_vision/mvblm7/Kconfig deleted file mode 100644 index ea7a6f8..0000000 --- a/board/matrix_vision/mvblm7/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MVBLM7 - -config SYS_BOARD - default "mvblm7" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MVBLM7" - -endif diff --git a/board/matrix_vision/mvblm7/MAINTAINERS b/board/matrix_vision/mvblm7/MAINTAINERS deleted file mode 100644 index 947a14e..0000000 --- a/board/matrix_vision/mvblm7/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVBLM7 BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mvblm7/ -F: include/configs/MVBLM7.h -F: configs/MVBLM7_defconfig diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile deleted file mode 100644 index caa6cfd..0000000 --- a/board/matrix_vision/mvblm7/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mvblm7.o pci.o fpga.o - -extra-y := bootscript.img - -MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script - -$(obj)/bootscript.img: $(src)/bootscript - $(call cmd,mkimage) diff --git a/board/matrix_vision/mvblm7/README.mvblm7 b/board/matrix_vision/mvblm7/README.mvblm7 deleted file mode 100644 index a0686f7..0000000 --- a/board/matrix_vision/mvblm7/README.mvblm7 +++ /dev/null @@ -1,84 +0,0 @@ -Matrix Vision mvBlueLYNX-M7 (mvBL-M7) -------------------------------------- - -1. Board Description - - The mvBL-M7 is a 120x120mm single board computing platform - with strong focus on stereo image processing applications. - - Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) - on any port (requires add-on board). - -2 System Components - -2.1 CPU - Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. - 512MByte DDR-II memory @ 133MHz. - 8 MByte Nor Flash on local bus. - 2 Vitesse VSC8601 RGMII ethernet Phys. - 1 USB host controller over ULPI I/F. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - 1 SD-Card slot connected to SPI. - System configuration (HRCW) is taken from I2C EEPROM. - -2.2 PCI - A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. - -2.3 FPGA - Altera Cyclone-II EP2C20/35 with PCI DMA engines. - Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. - Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. - -2.3.1 I/O @ FPGA - 2x8 Outputs : Infineon High-Side Switches to Main Supply. - 2x8 Inputs : Programmable input threshold + trigger capabilities - 2 dedicated flash interfaces for illuminator boards. - Cross trigger for chaining several boards. - -2.4 I2C - Bus1: - MAX5381 DAC @ 0x60 for 1st digital input threshold. - LM75 @ 0x90 for temperature monitoring. - EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - 1st image sensor interface (slave addresses depend on sensor) - Bus2: - MAX5381 DAC @ 0x60 for 2nd digital input threshold. - 2nd image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0xFFF00100, i.e. "HIGHBOOT". - - FF800000 environment - FF802000 redundant environment - FF804000 u-boot script image - FF806000 redundant u-boot script image - FF808000 device tree blob - FF80A000 redundant device tree blob - FF80C000 tbd. - FF80E000 tbd. - FF810000 kernel - FFC00000 root FS - FFF00000 u-boot - FFF80000 FPGA raw bit file - - mtd partitions are propagated to linux kernel via device tree blob. - -4 Booting - - On startup the bootscript @ FF804000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - 3. device tree blob - name is stored in "dtb_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvblm7/bootscript b/board/matrix_vision/mvblm7/bootscript deleted file mode 100644 index dc385fd..0000000 --- a/board/matrix_vision/mvblm7/bootscript +++ /dev/null @@ -1,43 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -if test ${console} = yes; -then -setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8 -else -setenv addcons setenv bootargs \${bootargs} console=tty0 -fi -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam addcons bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c deleted file mode 100644 index c0c5bed..0000000 --- a/board/matrix_vision/mvblm7/fpga.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "fpga.h" -#include "mvblm7.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvblm7_init_fpga(void) -{ - fpga_debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - fpga_config_fn(0, 1, 0); - udelay(60); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("SET config : %s\n", assert ? "low" : "high"); - if (assert) - dvo |= FPGA_CONFIG; - else - dvo &= ~FPGA_CONFIG; - - if (flush) - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - fpga_debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - fpga_debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - fpga_debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - fpga_debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - fpga_debug("\n"); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - fpga_debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h deleted file mode 100644 index b480c09..0000000 --- a/board/matrix_vision/mvblm7/fpga.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvblm7_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c deleted file mode 100644 index f3c16a3..0000000 --- a/board/matrix_vision/mvblm7/mvblm7.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif - -#include "../common/mv_common.h" -#include "mvblm7.h" - -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - char *s = getenv("ddr_size"); - - msize = CONFIG_SYS_DDR_SIZE; - if (s) { - u32 env_ddr_size = simple_strtoul(s, NULL, 10); - if (env_ddr_size == 512) - msize = 512; - } - - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & - LAWAR_SIZE); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - - asm("sync;isync"); - udelay(600); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - asm("sync;isync"); - udelay(500); - - return msize; -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); - - /* return total bus RAM size(bytes) */ - return msize * 1024 * 1024; -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (s) { - mv_reset_environment(); - } - - return 0; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision mvBlueLYNX-M7\n"); - - return 0; -} - -#ifdef CONFIG_HARD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~MVBLM7_MMC_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= ~MVBLM7_MMC_CS; -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} - -#endif diff --git a/board/matrix_vision/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h deleted file mode 100644 index de9fec7..0000000 --- a/board/matrix_vision/mvblm7/mvblm7.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __MVBC_H__ -#define __MVBC_H__ - -#define MV_GPIO - -#define FPGA_CONFIG 0x80000000 -#define FPGA_CCLK 0x40000000 -#define FPGA_DIN 0x20000000 -#define FPGA_STATUS 0x10000000 -#define FPGA_CONF_DONE 0x08000000 - -#define WD_WDI 0x00400000 -#define WD_TS 0x00200000 -#define MAN_RST 0x00100000 - -#define MV_GPIO_DAT (WD_TS) -#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS) -#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) - -#endif diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c deleted file mode 100644 index f14837a..0000000 --- a/board/matrix_vision/mvblm7/pci.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif -#include -#include -#include -#include "mvblm7.h" -#include "fpga.h" -#include "../common/mv_common.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - int i; - volatile immap_t *immr; - volatile pcictrl83xx_t *pci_ctrl; - volatile gpio83xx_t *gpio; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - struct pci_region *reg[] = { pci_regions }; - - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) &immr->clk; - pci_ctrl = immr->pci_ctrl; - pci_law = immr->sysconf.pcilaw; - gpio = (volatile gpio83xx_t *)&immr->gpio[0]; - - gpio->dat = MV_GPIO_DAT; - gpio->odr = MV_GPIO_ODE; - gpio->dir = MV_GPIO_OUT; - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - mvblm7_init_fpga(); - mv_load_fpga(); - - gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); - - /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ - clk->occr = 0xc0000000; - - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - - for (i = 0; i < 1000; ++i) - udelay(1000); - - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} diff --git a/configs/MERGERBOX_defconfig b/configs/MERGERBOX_defconfig deleted file mode 100644 index 34a527e..0000000 --- a/configs/MERGERBOX_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC83xx=y -CONFIG_TARGET_MERGERBOX=y diff --git a/configs/MVBLM7_defconfig b/configs/MVBLM7_defconfig deleted file mode 100644 index cc81b5c..0000000 --- a/configs/MVBLM7_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC83xx=y -CONFIG_TARGET_MVBLM7=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 036bc83..3caa8cf 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +MERGERBOX powerpc mpc83xx - - Andre Schwarz +MVBLM7 powerpc mpc83xx - - Andre Schwarz bluestone powerpc ppc4xx - - Tirumala Marri CRAYL1 powerpc ppc4xx - - David Updegraff KAREF powerpc ppc4xx - - Travis Sawyer diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h deleted file mode 100644 index 19ea316..0000000 --- a/include/configs/MERGERBOX.h +++ /dev/null @@ -1,599 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 -#define CONFIG_MPC837x 1 -#define CONFIG_MPC8377 1 - -#define CONFIG_SYS_TEXT_BASE 0xFC000000 - -#define CONFIG_PCI 1 -#define CONFIG_PCI_INDIRECT_BRIDGE 1 - -#define CONFIG_MASK_AER_AO -#define CONFIG_DISPLAY_AER_FULL - -#define CONFIG_MISC_INIT_R - -/* - * On-board devices - */ -#define CONFIG_TSEC_ENET - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#define CONFIG_PCIE -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - -/* - * Hardware Reset Configuration Word stored in EEPROM. - */ -#define CONFIG_SYS_HRCW_LOW 0 -#define CONFIG_SYS_HRCW_HIGH 0 - -/* Arbiter Configuration Register */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 -#define CONFIG_SYS_ACR_RPTCNT 3 - -/* System Priority Control Regsiter */ -#define CONFIG_SYS_SPCR_TSECEP 3 - -/* System Clock Configuration Register */ -#define CONFIG_SYS_SCCR_TSEC1CM 3 -#define CONFIG_SYS_SCCR_TSEC2CM 0 -#define CONFIG_SYS_SCCR_SDHCCM 3 -#define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */ -#define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 3 -#define CONFIG_SYS_SCCR_PCIEXP2CM 3 -#define CONFIG_SYS_SCCR_PCICM 1 -#define CONFIG_SYS_SCCR_SATACM 0xFF - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x087c0000 -#define CONFIG_SYS_SICRL 0x40000000 - -/* - * Output Buffer Impedance - */ -#define CONFIG_SYS_OBIR 0x30000000 - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_83XX_DDR_USES_CS0 - -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\ - DDRCDR_NZ_HIZ | DDRCDR_ODT |\ - DDRCDR_Q_DRN) - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - -#define CONFIG_SYS_DDR_MODE_WEAK -#define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2 -#define CONFIG_SYS_DDR_CPO 0x1f - -/* SPD table located at offset 0x20 in extended adressing ROM - * used for HRCW fetch after power-on reset - */ -#define CONFIG_SPD_EEPROM -#define SPD_EEPROM_ADDRESS 0x50 -#define SPD_EEPROM_OFFSET 0x20 -#define SPD_EEPROM_ADDR_LEN 2 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (512*1024) -#define CONFIG_SYS_MALLOC_LEN (512*1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ - GENERATED_GBL_DATA_SIZE) - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_FSL_ELBC 1 - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_SIZE 64 - -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\ - BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\ - OR_GPCM_XACS | OR_GPCM_SCY_15 |\ - OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\ - OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 - -#define CONFIG_SYS_NAND_BASE 0xE0600000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\ - BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\ - OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\ - OR_FCM_TRLX | OR_FCM_EHTR) - -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -#define CONFIG_CONSOLE ttyS0 -#define CONFIG_BAUDRATE 115200 - -/* SERDES */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_FSL_SERDES2 0xe3100 - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE (256 << 20) -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20) -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE (1 << 20) - -#ifdef CONFIG_PCIE -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20) -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20) -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20) - -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20) -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20) -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20) -#endif - -#define CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -/* - * TSEC - */ -#define CONFIG_GMII /* MII PHY management */ -#define CONFIG_SYS_VSC8601_SKEWFIX -#define CONFIG_SYS_VSC8601_SKEW_TX 3 -#define CONFIG_SYS_VSC8601_SKEW_RX 3 - -#define CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x10 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHYIDX 0 - -#define CONFIG_ETHPRIME "TSEC0" -#define CONFIG_HAS_ETH0 - -/* - * SATA - */ -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#define CONFIG_CMD_SATA -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_LIB_RAND - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_USB -#define CONFIG_CMD_SPI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_SATA - -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 - -#define CONFIG_RBTREE -#define CONFIG_LZO - -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS - -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND" -#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)" - -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE 1 - -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR 0x2000000 -#define CONFIG_LOADADDR 0x4000000 -#define CONFIG_SYS_CBSIZE 256 - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -#define CONFIG_SYS_MEMTEST_START (60<<20) -#define CONFIG_SYS_MEMTEST_END (70<<20) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ -#define CONFIG_HIGH_BATS 1 - -/* DDR: cache cacheable */ -#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* unused */ -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* unused */ -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -/* - * I2C EEPROM settings - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_SIZE 0x4000 - -/* - * Environment Configuration - */ -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFD00000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - -/* - * Video - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SM501_PCI -#define VIDEO_FB_LITTLE_ENDIAN -#define CONFIG_CMD_BMP -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) - -/* - * SPI - */ -#define CONFIG_MPC8XXX_SPI - -/* - * USB - */ -#define CONFIG_SYS_USB_HOST -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#define CONFIG_USB_STORAGE -#define CONFIG_USB_KEYBOARD -/* - * - */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1000 - -#define MV_CI "MergerBox" -#define MV_VCI "MergerBox" -#define MV_FPGA_DATA 0xfc100000 -#define MV_FPGA_SIZE 0x00200000 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x02800000 -#define MV_DTB_ADDR_RAM 0x00600000 -#define MV_INITRD_ADDR_RAM 0x01000000 -#define MV_FITADDR 0xfc300000 -#define MV_SPLAH_ADDR 0xffe00000 - -#define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\ - "then; run fitboot;else;run ubiboot;fi;" -#define CONFIG_BOOTARGS "console=ttyS0,115200n8" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0"\ - "stdin=serial\0"\ - "stdout=serial\0"\ - "stderr=serial\0"\ - "boot_sqfs=1\0"\ - "usb_dr_mode=host\0"\ - "bootfile=MergerBox.fit\0"\ - "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\ - "fpga=0\0"\ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\ - "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\ - "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\ - "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\ - "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\ - "fitaddr=" __stringify(MV_FITADDR) "\0"\ - "mv_version=" U_BOOT_VERSION "\0"\ - "mtdids=" MTDIDS_DEFAULT "\0"\ - "mtdparts=" MTDPARTS_DEFAULT "\0"\ - "dhcp_client_id=" MV_CI "\0"\ - "dhcp_vendor-class-identifier=" MV_VCI "\0"\ - "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\ - "protect off all;erase $uboota +0xC0000;"\ - "cp.b $loadaddr $uboota $filesize\0"\ - "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\ - "cp.b $loadaddr $fpgadata $filesize\0"\ - "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\ - "cp.b $loadaddr $fitaddr $filesize\0"\ - "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\ - "rootfstype=squashfs\0"\ - "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\ - "rootfstype=ubifs\0"\ - "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\ - "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\ - "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\ - "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\ - "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\ - "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\ - "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\ - "imxtract $fitaddr ramdisk $mv_initrd_ram;"\ - "imxtract $fitaddr fdt $mv_dtb_ram\0"\ - "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\ - "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\ - "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\ - "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\ - "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\ - "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\ - "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\ - "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\ - "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\ - "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\ - "" - -/* - * FPGA - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_CYCLON2 - -#endif diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h deleted file mode 100644 index 1ee4d7c..0000000 --- a/include/configs/MVBLM7.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright (C) Matrix Vision GmbH 2008 - * - * Matrix Vision mvBlueLYNX-M7 configuration file - * based on Freescale's MPC8349ITX. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 -#define CONFIG_MPC834x 1 -#define CONFIG_MPC8343 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_SYS_IMMR 0xE0000000 - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_SKIP_HOST_BRIDGE -#define CONFIG_TSEC_ENET -#define CONFIG_MPC8XXX_SPI -#define CONFIG_HARD_SPI -#define MVBLM7_MMC_CS 0x04000000 -#define CONFIG_MISC_INIT_R - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* - * DDR Setup - */ -#undef CONFIG_SPD_EEPROM - -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_83XX_DDR_USES_CS0 1 -#define CONFIG_SYS_MEMTEST_START (60<<20) -#define CONFIG_SYS_MEMTEST_END (70<<20) -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \ - | DDRCDR_NZ_HIZ \ - | DDRCDR_Q_DRN) - /* 0x22000001 */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - -#define CONFIG_SYS_DDR_SIZE 512 - -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f - -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3837c322 -#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_INTERVAL 0x02000100 - -#define CONFIG_SYS_DDR_MODE 0x04040242 -#define CONFIG_SYS_DDR_MODE2 0x00800000 - -/* Flash */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - -/* - * U-Boot memory configuration - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#undef CONFIG_SYS_RAMBOOT - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 -/* LB refresh timer prescal, 266MHz/32*/ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_CONSOLE ttyS0 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 -#define MV_DTB_NAME "mvblm7.dtb" - -/* - * PCI - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCI1_MMIO_BASE \ - (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 - -#define CONFIG_NET_RETRY_COUNT 3 - -#define CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66666667 -#define CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW - -/* TSEC */ -#define CONFIG_GMII -#define CONFIG_SYS_VSC8601_SKEWFIX -#define CONFIG_SYS_VSC8601_SKEW_TX 3 -#define CONFIG_SYS_VSC8601_SKEW_RX 3 - -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 - -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_FEC1_PHY_NORXERR -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define TSEC1_PHY_ADDR 0x10 -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) - -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_FEC2_PHY_NORXERR -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) -#define TSEC2_PHY_ADDR 0x11 -#define TSEC2_PHYIDX 0 -#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) - -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_LIB_RAND - -/* USB */ -#define CONFIG_SYS_USB_HOST -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -/* - * Environment - */ -#undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFF800000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_I2C -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_USB -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_HUSH_PARSER - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x200000 - -#define CONFIG_SYS_PROMPT "mvBL-M7> " -#define CONFIG_SYS_CBSIZE 256 - -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -#define CONFIG_SYS_HRCW_LOW 0x0 -#define CONFIG_SYS_HRCW_HIGH 0x0 - -/* - * System performance - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ - -/* clocking */ -#define CONFIG_SYS_SCCR_ENCCM 0 -#define CONFIG_SYS_SCCR_USBMPHCM 0 -#define CONFIG_SYS_SCCR_USBDRCM 2 -#define CONFIG_SYS_SCCR_TSEC1CM 1 -#define CONFIG_SYS_SCCR_TSEC2CM 1 - -#define CONFIG_SYS_SICRH 0x1fef0003 -#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0) - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ - HID0_ENABLE_INSTRUCTION_CACHE) - -#define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 - -/* DDR */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* no PCI2 */ -#define CONFIG_SYS_IBAT3L 0 -#define CONFIG_SYS_IBAT3U 0 -#define CONFIG_SYS_IBAT4L 0 -#define CONFIG_SYS_IBAT4U 0 - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT7L 0 -#define CONFIG_SYS_IBAT7U 0 - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NETDEV eth0 - -/* Default path and filenames */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1000 - -#define MV_CI "mvBL-M7" -#define MV_VCI "mvBL-M7" -#define MV_FPGA_DATA 0xfff40000 -#define MV_FPGA_SIZE 0 -#define MV_KERNEL_ADDR 0xff810000 -#define MV_INITRD_ADDR 0xffb00000 -#define MV_SCRIPT_ADDR 0xff804000 -#define MV_SCRIPT_ADDR2 0xff806000 -#define MV_DTB_ADDR 0xff808000 -#define MV_INITRD_LENGTH 0x00400000 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x00100000 -#define MV_DTB_ADDR_RAM 0x00600000 -#define MV_INITRD_ADDR_RAM 0x01000000 - -#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \ - "then source ${script_addr}; " \ - "else source ${script_addr2}; " \ - "fi;" -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "fpga=0\0" \ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \ - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \ - "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \ - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \ - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \ - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \ - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \ - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \ - "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \ - "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \ - "dtb_name=" __stringify(MV_DTB_NAME) "\0" \ - "mv_version=" U_BOOT_VERSION "\0" \ - "dhcp_client_id=" MV_CI "\0" \ - "dhcp_vendor-class-identifier=" MV_VCI "\0" \ - "netretry=no\0" \ - "use_static_ipaddr=no\0" \ - "static_ipaddr=192.168.90.10\0" \ - "static_netmask=255.255.255.0\0" \ - "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvBL-M7-rfs\0" \ - "zcip=no\0" \ - "netboot=yes\0" \ - "mvtest=Ff\0" \ - "tried_bootfromflash=no\0" \ - "tried_bootfromnet=no\0" \ - "bootfile=mvblm72625.boot\0" \ - "use_dhcp=yes\0" \ - "gev_start=yes\0" \ - "mvbcdma_debug=0\0" \ - "mvbcia_debug=0\0" \ - "propdev_debug=0\0" \ - "gevss_debug=0\0" \ - "watchdog=0\0" \ - "usb_dr_mode=host\0" \ - "sensor_cnt=2\0" \ - "" - -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_CYCLON2 - -#endif -- cgit v0.10.2 From af55e35d33894295cf0f2f94c050f67d05b50944 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:38:01 +0900 Subject: powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index cca58e5..8a477e7 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -97,12 +97,6 @@ config TARGET_MUCMC52 config TARGET_UC101 bool "Support uc101" -config TARGET_MVBC_P - bool "Support MVBC_P" - -config TARGET_MVSMR - bool "Support MVSMR" - config TARGET_PCM030 bool "Support pcm030" @@ -139,8 +133,6 @@ source "board/jupiter/Kconfig" source "board/manroland/hmi1001/Kconfig" source "board/manroland/mucmc52/Kconfig" source "board/manroland/uc101/Kconfig" -source "board/matrix_vision/mvbc_p/Kconfig" -source "board/matrix_vision/mvsmr/Kconfig" source "board/mcc200/Kconfig" source "board/motionpro/Kconfig" source "board/munices/Kconfig" diff --git a/board/matrix_vision/mvbc_p/Kconfig b/board/matrix_vision/mvbc_p/Kconfig deleted file mode 100644 index 4a68493..0000000 --- a/board/matrix_vision/mvbc_p/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MVBC_P - -config SYS_BOARD - default "mvbc_p" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MVBC_P" - -endif diff --git a/board/matrix_vision/mvbc_p/MAINTAINERS b/board/matrix_vision/mvbc_p/MAINTAINERS deleted file mode 100644 index aad14ed..0000000 --- a/board/matrix_vision/mvbc_p/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVBC_P BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mvbc_p/ -F: include/configs/MVBC_P.h -F: configs/MVBC_P_defconfig diff --git a/board/matrix_vision/mvbc_p/Makefile b/board/matrix_vision/mvbc_p/Makefile deleted file mode 100644 index 4c19941..0000000 --- a/board/matrix_vision/mvbc_p/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004-2008 -# Matrix-Vision GmbH, info@matrix-vision.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mvbc_p.o fpga.o diff --git a/board/matrix_vision/mvbc_p/README.mvbc_p b/board/matrix_vision/mvbc_p/README.mvbc_p deleted file mode 100644 index a691137..0000000 --- a/board/matrix_vision/mvbc_p/README.mvbc_p +++ /dev/null @@ -1,73 +0,0 @@ -Matrix Vision mvBlueCOUGAR-P (mvBC-P) -------------------------------------- - -1. Board Description - - The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera - with main focus on GigEVision protocol in combination with local image - preprocessing. - - Power Supply is either VDC 48V or Pover over Ethernet (PoE). - -2 System Components - -2.1 CPU - Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. - 64MB SDRAM @ 133MHz. - 8 MByte Nor Flash on local bus. - 1 serial ports. Console running on ttyS0 @ 115200 8N1. - -2.2 PCI - PCI clock fixed at 66MHz. Arbitration inside FPGA. - Intel GD82541ER network MAC/PHY and FPGA connected. - -2.3 FPGA - Altera Cyclone-II EP2C8 with PCI DMA engine. - Connects to Matrix Vision specific CCD/CMOS sensor interface. - Utilizes 64MB Nand Flash. - -2.3.1 I/O @ FPGA - 2 Outputs : photo coupler - 2 Inputs : photo coupler - -2.4 I2C - LM75 @ 0x90 for temperature monitoring. - EEPROM @ 0xA0 for vendor specifics. - image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0x00000100, i.e. "LOWBOOT". - - FF800000 u-boot - FF840000 u-boot script image - FF850000 redundant u-boot script image - FF860000 FPGA raw bit file - FF8A0000 tbd. - FF900000 root FS - FFC00000 kernel - FFFC0000 device tree blob - FFFD0000 redundant device tree blob - FFFE0000 environment - FFFF0000 redundant environment - - mtd partitions are propagated to linux kernel via device tree blob. - -4 Booting - - On startup the bootscript @ FF840000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - 3. device tree blob - name is stored in "dtb_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c deleted file mode 100644 index b88f43f..0000000 --- a/board/matrix_vision/mvbc_p/fpga.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "fpga.h" -#include "mvbc_p.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C8_SIZE, - (void *) &altera_fns, - NULL, -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvbc_p_init_fpga(void) -{ - fpga_debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - fpga_config_fn(0, 1, 0); - udelay(60); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - fpga_debug("SET config : %s\n", assert ? "low" : "high"); - if (assert) - dvo |= FPGA_CONFIG; - else - dvo &= ~FPGA_CONFIG; - - if (flush) - gpio->simple_dvo = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - int result = 0; - - udelay(10); - fpga_debug("CONF_DONE check ... "); - if (gpio->simple_ival & FPGA_CONF_DONE) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - int result = 0; - - fpga_debug("STATUS check ... "); - if (gpio->sint_ival & FPGA_STATUS) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->simple_dvo = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val) -{ - int i; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - for (i=0; i<8; i++) { - dvo &= ~FPGA_CCLK; - gpio->simple_dvo = dvo; - dvo &= ~FPGA_DIN; - if (val & 1) - dvo |= FPGA_DIN; - gpio->simple_dvo = dvo; - dvo |= FPGA_CCLK; - gpio->simple_dvo = dvo; - val >>= 1; - } - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i]); - fpga_debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mvbc_p/fpga.h b/board/matrix_vision/mvbc_p/fpga.h deleted file mode 100644 index 96d3465..0000000 --- a/board/matrix_vision/mvbc_p/fpga.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvbc_p_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c deleted file mode 100644 index 8faebee..0000000 --- a/board/matrix_vision/mvbc_p/mvbc_p.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2005-2007 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga.h" -#include "mvbc_p.h" -#include "../common/mv_common.h" - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_start (int hi_addr) -{ - long hi_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit); - - /* precharge all banks */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit); - - /* precharge all banks */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit); - - /* auto refresh */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit); - - /* set mode register */ - out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit); -} - -phys_addr_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong test1, - test2; - - /* setup SDRAM chip selects */ - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); - - /* setup config registers */ - out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - if (dramsize < (1 << 20)) - dramsize = 0; - - if (dramsize > 0) - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - else - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0); - - return dramsize; -} - -void mvbc_init_gpio(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - printf("Ports : 0x%08x\n", gpio->port_config); - printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG); - - out_be32(&gpio->simple_ddr, SIMPLE_DDR); - out_be32(&gpio->simple_dvo, SIMPLE_DVO); - out_be32(&gpio->simple_ode, SIMPLE_ODE); - out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN); - - out_8(&gpio->sint_ode, SINT_ODE); - out_8(&gpio->sint_ddr, SINT_DDR); - out_8(&gpio->sint_dvo, SINT_DVO); - out_8(&gpio->sint_inten, SINT_INTEN); - out_be16(&gpio->sint_itype, SINT_ITYPE); - out_8(&gpio->sint_gpioe, SINT_GPIOEN); - - out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE); - out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR); - out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO); - out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN); - - printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe); - printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe); -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (!s) { - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - udelay(50000); - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - udelay(50000); - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - } - printf(" === FACTORY RESET ===\n"); - mv_reset_environment(); - saveenv(); - - return -1; -} - -int checkboard(void) -{ - mvbc_init_gpio(); - printf("Board: Matrix Vision mvBlueCOUGAR-P\n"); - - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1); -} - -void flash_afterinit(ulong size) -{ - out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START | - size)); - out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START | - size)); - out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size, - size)); - out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size, - size)); -} - -void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char line = 0xff; - char *s = getenv("pci_latency"); - u32 base; - u8 val = 0; - - if (s) - val = simple_strtoul(s, NULL, 16); - - if (PCI_BUS(dev) == 0) { - switch (PCI_DEV (dev)) { - case 0xa: /* FPGA */ - line = 3; - pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base); - printf("found FPGA - enable arbitration\n"); - writel(0x03, (u32*)(base + 0x80c0)); - writel(0xf0, (u32*)(base + 0x8080)); - if (val) - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val); - break; - case 0xb: /* LAN */ - line = 2; - if (val) - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val); - break; - case 0x1a: - break; - default: - printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev)); - break; - } - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line); - } -} - -struct pci_controller hose = { - fixup_irq:pci_mvbc_fixup_irq -}; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - mvbc_p_init_fpga(); - mv_load_fpga(); - pci_mpc5xxx_init(&hose); -} - -void show_boot_progress(int val) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - switch(val) { - case BOOTSTAGE_ID_START: /* FPGA ok */ - setbits_be32(&gpio->simple_dvo, LED_G0); - break; - case BOOTSTAGE_ID_NET_ETH_INIT: - setbits_be32(&gpio->simple_dvo, LED_G1); - break; - case BOOTSTAGE_ID_COPY_RAMDISK: - setbits_be32(&gpio->simple_dvo, LED_Y); - break; - case BOOTSTAGE_ID_RUN_OS: - setbits_be32(&gpio->simple_dvo, LED_R); - break; - default: - break; - } - -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/matrix_vision/mvbc_p/mvbc_p.h b/board/matrix_vision/mvbc_p/mvbc_p.h deleted file mode 100644 index be1542b..0000000 --- a/board/matrix_vision/mvbc_p/mvbc_p.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef __MVBC_H__ -#define __MVBC_H__ - -#define LED_G0 MPC5XXX_GPIO_SIMPLE_PSC2_0 -#define LED_G1 MPC5XXX_GPIO_SIMPLE_PSC2_1 -#define LED_Y MPC5XXX_GPIO_SIMPLE_PSC2_2 -#define LED_R MPC5XXX_GPIO_SIMPLE_PSC2_3 -#define ARB_X_EN MPC5XXX_GPIO_WKUP_PSC2_4 - -#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 -#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 -#define FPGA_CONF_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 -#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 -#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 - -#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 -#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 -#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 -#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 -#define FACT_RST MPC5XXX_GPIO_WKUP_6 -#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 - -#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \ - FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI) -#define SIMPLE_DVO (FPGA_CONFIG) -#define SIMPLE_ODE (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R) -#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \ - FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\ - WD_WDI | COP_PRESENT) - -#define SINT_ODE 0 -#define SINT_DDR 0 -#define SINT_DVO 0 -#define SINT_INTEN 0 -#define SINT_ITYPE 0 -#define SINT_GPIOEN (FPGA_STATUS) - -#define WKUP_ODE (MAN_RST) -#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS) -#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS) -#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY) - -#endif diff --git a/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/board/matrix_vision/mvbc_p/mvbc_p_autoscript deleted file mode 100644 index 9b21f30..0000000 --- a/board/matrix_vision/mvbc_p/mvbc_p_autoscript +++ /dev/null @@ -1,48 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -if test ${console} = yes; -then -setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8 -else -setenv addcons setenv bootargs \${bootargs} console=tty0 -fi -setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1 -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${oprofile} = yes; -then -setenv addprofile setenv bootargs \${bootargs} profile=\${profile} -fi -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvsmr/.gitignore b/board/matrix_vision/mvsmr/.gitignore deleted file mode 100644 index 469f1bc..0000000 --- a/board/matrix_vision/mvsmr/.gitignore +++ /dev/null @@ -1 +0,0 @@ -bootscript.img diff --git a/board/matrix_vision/mvsmr/Kconfig b/board/matrix_vision/mvsmr/Kconfig deleted file mode 100644 index d725c5a..0000000 --- a/board/matrix_vision/mvsmr/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MVSMR - -config SYS_BOARD - default "mvsmr" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MVSMR" - -endif diff --git a/board/matrix_vision/mvsmr/MAINTAINERS b/board/matrix_vision/mvsmr/MAINTAINERS deleted file mode 100644 index ae3cf9c..0000000 --- a/board/matrix_vision/mvsmr/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVSMR BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mvsmr/ -F: include/configs/MVSMR.h -F: configs/MVSMR_defconfig diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile deleted file mode 100644 index cef1b76..0000000 --- a/board/matrix_vision/mvsmr/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004-2008 -# Matrix-Vision GmbH, info@matrix-vision.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mvsmr.o fpga.o - -extra-y := bootscript.img - -MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script - -$(obj)/bootscript.img: $(src)/bootscript - $(call cmd,mkimage) diff --git a/board/matrix_vision/mvsmr/README.mvsmr b/board/matrix_vision/mvsmr/README.mvsmr deleted file mode 100644 index 8e34cb7..0000000 --- a/board/matrix_vision/mvsmr/README.mvsmr +++ /dev/null @@ -1,55 +0,0 @@ -Matrix Vision mvSMR -------------------- - -1. Board Description - - The mvSMR is a 75x130mm single image processing board used - in automation. Power Supply is 24VDC. - -2 System Components - -2.1 CPU - Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. - 64MB DDR-I @ 133MHz. - 8 MByte Nor Flash on local bus. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - -2.2 PCI - PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core. - -2.3 FPGA - Xilinx Spartan-3 XC3S200 with PCI DMA engine. - Connects to Matrix Vision specific CCD/CMOS sensor interface. - -2.4 I2C - EEPROM @ 0xA0 for vendor specifics. - image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0x00000100, i.e. "LOWBOOT". - - FF800000 u-boot - FF806000 u-boot script image - FF808000 u-boot environment - FF840000 FPGA raw bit file - FF880000 root FS - FFF00000 kernel - -4 Booting - - On startup the bootscript @ FF806000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvsmr/bootscript b/board/matrix_vision/mvsmr/bootscript deleted file mode 100644 index 02c802c..0000000 --- a/board/matrix_vision/mvsmr/bootscript +++ /dev/null @@ -1,42 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}' -setenv ramkernel 'setenv kernel_boot ${loadaddr}' -setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}' -setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}' -setenv bootfromflash run flashkernel cpird addcons boot24 -setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel' -if test ${console} = yes; -then -setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8' -else -setenv addcons 'setenv bootargs ${bootargs} console=tty0' -fi -setenv set_static_ip 'setenv ipaddr ${static_ipaddr}' -setenv set_static_nm 'setenv netmask ${static_netmask}' -setenv set_static_gw 'setenv gatewayip ${static_gateway}' -setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}' -if test ${servicemode} != yes; -then - echo "=== forced flash mode ===" - run set_static_ip set_static_nm set_static_gw set_ip bootfromflash -fi -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip bootfromnet addcons boot24 - else - echo "=== netboot failed ===" - fi - fi - echo "=== bootfromflash ===" - run set_static_ip set_static_nm set_static_gw set_ip bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c deleted file mode 100644 index 5189925..0000000 --- a/board/matrix_vision/mvsmr/fpga.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2010 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include "fpga.h" -#include "mvsmr.h" - -xilinx_spartan3_slave_serial_fns fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_clk_fn, - fpga_init_fn, - fpga_done_fn, - fpga_wr_fn, - 0 -}; - -xilinx_desc spartan3 = { - xilinx_spartan2, - slave_serial, - XILINX_XC3S200_SIZE, - (void *) &fpga_fns, - 0, -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvsmr_init_fpga(void) -{ - fpga_init(); - fpga_add(fpga_xilinx, &spartan3); - - return 1; -} - -int fpga_init_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (in_be32(&gpio->simple_ival) & FPGA_CONFIG) - return 0; - - return 1; -} - -int fpga_done_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - int result = 0; - - udelay(10); - if (in_be32(&gpio->simple_ival) & FPGA_DONE) - result = 1; - - return result; -} - -int fpga_pgm_fn(int assert, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (!assert) - setbits_8(&gpio->sint_dvo, FPGA_STATUS); - else - clrbits_8(&gpio->sint_dvo, FPGA_STATUS); - - return assert; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (assert_clk) - setbits_be32(&gpio->simple_dvo, FPGA_CCLK); - else - clrbits_be32(&gpio->simple_dvo, FPGA_CCLK); - - return assert_clk; -} - -int fpga_wr_fn(int assert_write, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (assert_write) - setbits_be32(&gpio->simple_dvo, FPGA_DIN); - else - clrbits_be32(&gpio->simple_dvo, FPGA_DIN); - - return assert_write; -} - -int fpga_pre_config_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - setbits_8(&gpio->sint_dvo, FPGA_STATUS); - - return 0; -} diff --git a/board/matrix_vision/mvsmr/fpga.h b/board/matrix_vision/mvsmr/fpga.h deleted file mode 100644 index 7ef878b..0000000 --- a/board/matrix_vision/mvsmr/fpga.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvsmr_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_pre_config_fn(int cookie); diff --git a/board/matrix_vision/mvsmr/mvsmr.c b/board/matrix_vision/mvsmr/mvsmr.c deleted file mode 100644 index 2c51389..0000000 --- a/board/matrix_vision/mvsmr/mvsmr.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2005-2010 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga.h" -#include "mvsmr.h" -#include "../common/mv_common.h" - -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x715f0f00 -#define SDRAM_CONFIG1 0xd3722930 -#define SDRAM_CONFIG2 0x46770000 - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_start(int hi_addr) -{ - long hi_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | - hi_bit); - - /* precharge all banks */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | - hi_bit); - - /* set mode register: extended mode */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); - - /* precharge all banks */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | - hi_bit); - - /* auto refresh */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | - hi_bit); - - /* set mode register */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit); -} - -phys_addr_t initdram(int board_type) -{ - ulong dramsize = 0; - ulong test1, - test2; - - /* setup SDRAM chip selects */ - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); - - /* setup config registers */ - out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - if (dramsize < (1 << 20)) - dramsize = 0; - - if (dramsize > 0) - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - else - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0); - - return dramsize; -} - -void mvsmr_init_gpio(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - printf("Ports : 0x%08x\n", gpio->port_config); - printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG)); - - out_be32(&gpio->simple_ddr, SIMPLE_DDR); - out_be32(&gpio->simple_dvo, SIMPLE_DVO); - out_be32(&gpio->simple_ode, SIMPLE_ODE); - out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN); - - out_8(&gpio->sint_ode, SINT_ODE); - out_8(&gpio->sint_ddr, SINT_DDR); - out_8(&gpio->sint_dvo, SINT_DVO); - out_8(&gpio->sint_inten, SINT_INTEN); - out_be16(&gpio->sint_itype, SINT_ITYPE); - out_8(&gpio->sint_gpioe, SINT_GPIOEN); - - out_8(&wu_gpio->ode, WKUP_ODE); - out_8(&wu_gpio->ddr, WKUP_DIR); - out_8(&wu_gpio->dvo, WKUP_DO); - out_8(&wu_gpio->enable, WKUP_EN); - - out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */ - out_be32(&timers->gpt1.emsr, 0x00000234); - out_be32(&timers->gpt2.emsr, 0x00000234); - out_be32(&timers->gpt3.emsr, 0x00000234); - out_be32(&timers->gpt4.emsr, 0x00000234); - out_be32(&timers->gpt5.emsr, 0x00000234); - out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */ - out_be32(&timers->gpt7.emsr, 0x00000024); -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (s) { - printf(" === FACTORY RESET ===\n"); - mv_reset_environment(); - saveenv(); - } - - return -1; -} - -void mvsmr_get_dbg_present(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - if (in_be32(&gpio->simple_ival) & COP_PRESENT) { - setenv("dbg_present", "no\0"); - setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0"); - } else { - setenv("dbg_present", "yes\0"); - setenv("bootstopkey", "s\0"); - setbits_8(&psc->command, PSC_RX_ENABLE); - } -} - -void mvsmr_get_service_mode(void) -{ - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - - if (in_8(&wu_gpio->ival) & SERVICE_MODE) - setenv("servicemode", "no\0"); - else - setenv("servicemode", "yes\0"); -} - -int mvsmr_get_mac(void) -{ - unsigned char mac[6]; - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - - if (in_8(&wu_gpio->ival) & LAN_PRSNT) { - setenv("lan_present", "no\0"); - return -1; - } else - setenv("lan_present", "yes\0"); - - i2c_read(0x50, 0, 1, mac, 6); - - eth_setenv_enetaddr("ethaddr", mac); - - return 0; -} - -int checkboard(void) -{ - mvsmr_init_gpio(); - printf("Board: Matrix Vision mvSMR\n"); - - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1); -} - -void flash_afterinit(ulong size) -{ - out_be32((u32 *)MPC5XXX_BOOTCS_START, - START_REG(CONFIG_SYS_BOOTCS_START | size)); - out_be32((u32 *)MPC5XXX_CS0_START, - START_REG(CONFIG_SYS_BOOTCS_START | size)); - out_be32((u32 *)MPC5XXX_BOOTCS_STOP, - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); - out_be32((u32 *)MPC5XXX_CS0_STOP, - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); -} - -struct pci_controller hose; - -void pci_init_board(void) -{ - mvsmr_get_dbg_present(); - mvsmr_get_service_mode(); - mvsmr_init_fpga(); - mv_load_fpga(); - pci_mpc5xxx_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - if (!mvsmr_get_mac()) - return cpu_eth_init(bis); - - return pci_eth_init(bis); -} diff --git a/board/matrix_vision/mvsmr/mvsmr.h b/board/matrix_vision/mvsmr/mvsmr.h deleted file mode 100644 index b8320f1..0000000 --- a/board/matrix_vision/mvsmr/mvsmr.h +++ /dev/null @@ -1,43 +0,0 @@ -#include - -extern void pci_mpc5xxx_init(struct pci_controller *); - -#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 -#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 -#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 -#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 -#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 -#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5 -#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6 -#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7 -#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8 -#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9 - -#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 -#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 -#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 -#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 -#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6 -#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 -#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4 -#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4 - -#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\ - S_FPGA_CCLK) -#define SIMPLE_DVO (FPGA_CONFIG) -#define SIMPLE_ODE (FPGA_CONFIG) -#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\ - S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT) - -#define SINT_ODE 0x1 -#define SINT_DDR 0x3 -#define SINT_DVO 0x1 -#define SINT_INTEN 0 -#define SINT_ITYPE 0 -#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG) - -#define WKUP_ODE (MAN_RST | S_FPGA_STATUS) -#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS) -#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS) -#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\ - FLASH_RBY | UART_EN1 | LAN_PRSNT) diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds deleted file mode 100644 index e885b7c..0000000 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2010 - * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the first two sectors (=8KB) of our S29GL flash chip */ - arch/powerpc/cpu/mpc5xxx/start.o (.text*) - arch/powerpc/cpu/mpc5xxx/traps.o (.text*) - board/matrix_vision/common/built-in.o (.text*) - - /* This is only needed to force failure if size of above code will ever */ - /* increase and grow into reserved space. */ - . = ALIGN(0x2000); /* location counter has to be 0x4000 now */ - . += 0x4000; /* ->0x8000, i.e. move to env_offset */ - - . = env_offset; /* ld error as soon as above ALIGN misplaces lc */ - common/env_embedded.o (.ppcenv) - - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/configs/MVBC_P_defconfig b/configs/MVBC_P_defconfig deleted file mode 100644 index b0351fd..0000000 --- a/configs/MVBC_P_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MVBC_P" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MVBC_P=y diff --git a/configs/MVSMR_defconfig b/configs/MVSMR_defconfig deleted file mode 100644 index a84c173..0000000 --- a/configs/MVSMR_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MVSMR=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 3caa8cf..1dcdcc7 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +MVBC_P powerpc mpc5xxx - - Andre Schwarz +MVSMR powerpc mpc5xxx - - Andre Schwarz MERGERBOX powerpc mpc83xx - - Andre Schwarz MVBLM7 powerpc mpc83xx - - Andre Schwarz bluestone powerpc ppc4xx - - Tirumala Marri diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h deleted file mode 100644 index 1ab2b3d..0000000 --- a/include/configs/MVBC_P.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2008 - * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_MPC5200 1 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFF800000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_PSC_CONSOLE 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400} - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#undef CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 -#define CONFIG_HIGH_BATS 1 - -#define MV_CI mvBlueCOUGAR-P -#define MV_VCI mvBlueCOUGAR-P -#define MV_FPGA_DATA 0xff860000 -#define MV_FPGA_SIZE 0 -#define MV_KERNEL_ADDR 0xffd00000 -#define MV_INITRD_ADDR 0xff900000 -#define MV_INITRD_LENGTH 0x00400000 -#define MV_SCRATCH_ADDR 0x00000000 -#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH -#define MV_SCRIPT_ADDR 0xff840000 -#define MV_SCRIPT_ADDR2 0xff850000 -#define MV_DTB_ADDR 0xfffc0000 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x00100000 -#define MV_DTB_ADDR_RAM 0x00600000 -#define MV_INITRD_ADDR_RAM 0x01000000 - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define MV_DTB_NAME mvbc-p.dtb -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * Supported commands - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_I2C - -#undef CONFIG_WATCHDOG - -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_LIB_RAND - -/* - * Autoboot - */ -#define CONFIG_BOOTDELAY 2 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1000 - -#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \ - then source ${script_addr}; \ - else source ${script_addr2}; \ - fi;" - -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "console=yes\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "fpga=0\0" \ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \ - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \ - "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \ - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \ - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \ - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \ - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \ - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \ - "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \ - "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \ - "dtb_name=" __stringify(MV_DTB_NAME) "\0" \ - "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \ - "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \ - "mv_version=" U_BOOT_VERSION "\0" \ - "dhcp_client_id=" __stringify(MV_CI) "\0" \ - "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \ - "netretry=no\0" \ - "use_static_ipaddr=no\0" \ - "static_ipaddr=192.168.90.10\0" \ - "static_netmask=255.255.255.0\0" \ - "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvbc-p-rfs\0" \ - "zcip=no\0" \ - "netboot=yes\0" \ - "mvtest=Ff\0" \ - "tried_bootfromflash=no\0" \ - "tried_bootfromnet=no\0" \ - "use_dhcp=yes\0" \ - "gev_start=yes\0" \ - "mvbcdma_debug=0\0" \ - "mvbcia_debug=0\0" \ - "propdev_debug=0\0" \ - "gevss_debug=0\0" \ - "watchdog=1\0" \ - "sensor_cnt=1\0" \ - "" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 - -/* - * Flash configuration - */ -#undef CONFIG_FLASH_16BIT -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_FLASH_ERASE_TOUT 50000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_LOWBOOT -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_FLASH_PROTECTION - -#define CONFIG_ENV_ADDR 0xFFFE0000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (512 << 10) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_MODULE 1 -#define CONFIG_SYS_I2C_SPEED 86000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Ethernet configuration - */ -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_E1000 -#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 } -#undef CONFIG_MPC5xxx_FEC -#undef CONFIG_PHY_ADDR -#define CONFIG_NETDEV eth0 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#undef CONFIG_SYS_LONGHELP -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00800000 -#define CONFIG_SYS_MEMTEST_END 0x02f00000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x02000000 -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x00200000 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004 - -#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x000000f0 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333303 - -#define CONFIG_SYS_RESET_ADDRESS 0x00000100 - -#undef FPGA_DEBUG -#undef CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA 1 -#define CONFIG_FPGA_CYCLON2 1 -#define CONFIG_FPGA_COUNT 1 - -#endif diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h deleted file mode 100644 index 27f730d..0000000 --- a/include/configs/MVSMR.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2010 - * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_MPC5200 1 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFF800000 -#endif -#define CONFIG_SYS_LDSCRIPT "board/matrix_vision/mvsmr/u-boot.lds" - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_PSC_CONSOLE 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\ - 230400} - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#undef CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 -#define CONFIG_HIGH_BATS 1 - -#define MV_CI mvSMR -#define MV_VCI mvSMR -#define MV_FPGA_DATA 0xff840000 -#define MV_FPGA_SIZE 0x1ff88 -#define MV_KERNEL_ADDR 0xfff00000 -#define MV_SCRIPT_ADDR 0xff806000 -#define MV_INITRD_ADDR 0xff880000 -#define MV_INITRD_LENGTH 0x00240000 -#define MV_SCRATCH_ADDR 0xffcc0000 -#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x00100000 -#define MV_INITRD_ADDR_RAM 0x00400000 - -/* - * Supported commands - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_LIB_RAND - -/* - * Autoboot - */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "abcdefg" -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_BOOTCOMMAND "source ${script_addr}" -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \ - " allocate=6M" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "console=no\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "fpga=0\0" \ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \ - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \ - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \ - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \ - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \ - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \ - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \ - "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \ - "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \ - "mv_version=" U_BOOT_VERSION "\0" \ - "dhcp_client_id=" __stringify(MV_CI) "\0" \ - "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \ - "netretry=no\0" \ - "use_static_ipaddr=no\0" \ - "static_ipaddr=192.168.0.101\0" \ - "static_netmask=255.255.255.0\0" \ - "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvsmr-rfs\0" \ - "zcip=yes\0" \ - "netboot=no\0" \ - "" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK - -/* - * Flash configuration - */ -#undef CONFIG_FLASH_16BIT -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_FLASH_ERASE_TOUT 50000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_LOWBOOT -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 - -/* used by linker script to wrap code around */ -#define CONFIG_SCRIPT_OFFSET 0x6000 -#define CONFIG_SCRIPT_SECT_SIZE 0x2000 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (512 << 10) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_MODULE 1 -#define CONFIG_SYS_I2C_SPEED 86000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Ethernet configuration - */ -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_MPC5xxx_FEC -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_NETDEV eth0 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#undef CONFIG_SYS_LONGHELP -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00800000 -#define CONFIG_SYS_MEMTEST_END 0x02f00000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x02000000 -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x00200000 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044 - -#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x000000f0 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333303 - -#define CONFIG_SYS_RESET_ADDRESS 0x00000100 - -#undef FPGA_DEBUG -#undef CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX 1 -#define CONFIG_FPGA_SPARTAN2 1 -#define CONFIG_FPGA_COUNT 1 - -#endif -- cgit v0.10.2 From 04e2a13336f0e507ef416bbede3be92b79c46594 Mon Sep 17 00:00:00 2001 From: Alexander Kochetkov Date: Mon, 29 Sep 2014 21:46:48 +0400 Subject: beagleboard: Remove side effects of i2c2 pullup resisters initialization code Fix typo of commit d4e53f063dd25e071444b87303573e7440deeb89. i2c2 pullup resisters are controlled by bit 0 of CONTROL_PROG_IO1. It's value after reset is 0x00100001. In order to clear bit 0, original code write 0xfffffffe to CONTROL_PROG_IO1 and toggle almost all default values. Original code affect following: * disable i2c1 pullup resisters * increase far end load setting for many modules * setup invalid SC/LB combination Signed-off-by: Alexander Kochetkov CC: Tom Rini CC: Steve Kipisz diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 0674afd..94b99bf 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -317,9 +317,12 @@ int misc_init_r(void) struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE; bool generate_fake_mac = false; + u32 value; /* Enable i2c2 pullup resisters */ - writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1); + value = readl(&prog_io_base->io1); + value &= ~(PRG_I2C2_PULLUPRESX); + writel(value, &prog_io_base->io1); switch (get_board_revision()) { case REVISION_AXBX: -- cgit v0.10.2 From 2ea9103924048637d28baf0f7b1dd410f6704c32 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 30 Sep 2014 10:44:01 +0200 Subject: SPDX License cleanup for LiMon imported files A number of network related files were imported from the LiMon project; these contain a somewhat unclear license statement: Copyright 1994 - 2000 Neil Russell. (See License) I analyzed the source code of LiMon v1.4.2 which was used for this import. It does not contain any "License" file, but the top level directory contains a file "COPYING", which turns out to be GPL v2 of June 1991. So it is legitimate to conclude that the LiMon derived files are also to be released under GPLv2. Mark them as such. Signed-off-by: Wolfgang Denk diff --git a/include/net.h b/include/net.h index 735b0b9..18d279e 100644 --- a/include/net.h +++ b/include/net.h @@ -3,7 +3,7 @@ * * Copyright 1994 - 2000 Neil Russell. * (See License) - * + * SPDX-License-Identifier: GPL-2.0 * * History * 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added diff --git a/net/arp.c b/net/arp.c index 20c6b2d..21ed31b 100644 --- a/net/arp.c +++ b/net/arp.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #include diff --git a/net/arp.h b/net/arp.h index bfd57e0..3a0a13a 100644 --- a/net/arp.h +++ b/net/arp.h @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ARP_H__ diff --git a/net/cdp.c b/net/cdp.c index 3d9559e..2d8fa03 100644 --- a/net/cdp.c +++ b/net/cdp.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #include diff --git a/net/cdp.h b/net/cdp.h index ec7315a..95e4ce0 100644 --- a/net/cdp.h +++ b/net/cdp.h @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #if defined(CONFIG_CMD_CDP) diff --git a/net/net.c b/net/net.c index 722089f..2bea07b 100644 --- a/net/net.c +++ b/net/net.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ /* diff --git a/net/ping.c b/net/ping.c index 0710b92..2be56ed 100644 --- a/net/ping.c +++ b/net/ping.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #include "ping.h" diff --git a/net/ping.h b/net/ping.h index 8c71be4..b672b95 100644 --- a/net/ping.h +++ b/net/ping.h @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __PING_H__ -- cgit v0.10.2 From 3f2b5bb6741fa21d7a7768be3a9be3730c9ecf3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 12:32:20 +0200 Subject: PIP405: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: David Müller diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index a6f505a..9a1b2ac 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -21,6 +21,8 @@ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#define CONFIG_SYS_GENERIC_BOARD + /*********************************************************** * Clock ***********************************************************/ -- cgit v0.10.2 From d3b88405e5ee4e37bc14cb66c12aa61b9f1b8ead Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 12:32:21 +0200 Subject: MIP405: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: David Müller diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 68824fd..147f122 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -21,6 +21,8 @@ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#define CONFIG_SYS_GENERIC_BOARD + /*********************************************************** * Note that it may also be a MIP405T board which is a subset of the * MIP405 -- cgit v0.10.2 From 13bd4d877687c6b6f1031d21b4124de336b6abb2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 12:32:22 +0200 Subject: VCMA9: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: David Müller diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index d40185e..0d8a13c 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_TEXT_BASE 0x0 +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH /* input clock of PLL (VCMA9 has 12MHz input clock) */ -- cgit v0.10.2 From 6c4c9a7c0fc54760370ad0b09fba11fd2bc9717f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 12:32:23 +0200 Subject: PATI: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: David Müller diff --git a/include/configs/PATI.h b/include/configs/PATI.h index d823b0f..65ab65d 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -21,6 +21,8 @@ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 +#define CONFIG_SYS_GENERIC_BOARD + /* Serial Console Configuration */ #define CONFIG_5xx_CONS_SCI1 #undef CONFIG_5xx_CONS_SCI2 -- cgit v0.10.2 From cf7d4505e3403a4ce039dc28c3a473414e7ea6a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 13:23:54 +0200 Subject: PATI: fix broken SPI access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix broken SPI access by adding/activating BOARD_EARLY_INIT_F functionality and calling spi_init_f() from there. Signed-off-by: David Müller diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index 5d701a7..b9d88ee 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -311,6 +311,11 @@ void user_led1(int led_on) sysconf->sc_sgpiodt2=reg; /* Data register */ } +int board_early_init_f(void) +{ + spi_init_f(); + return 0; +} /**************************************************************** * Last Stage Init diff --git a/include/configs/PATI.h b/include/configs/PATI.h index 65ab65d..3ca204e 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -98,6 +98,7 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } +#define CONFIG_BOARD_EARLY_INIT_F /*********************************************************************** * Last Stage Init -- cgit v0.10.2 From fbad4641fb194f9a864d7f666f02851770184933 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 13:53:28 +0200 Subject: VCMA9: remove EXT2 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit remove the seldomly used EXT2 support because the U-Boot binary will not fit into the 512KiB flash otherwise. Signed-off-by: David Müller diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 0d8a13c..a97f5fa 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -216,7 +216,6 @@ /* File system */ #define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS #define CONFIG_CMD_JFFS2 -- cgit v0.10.2 From 16c429c9ea91b9ccbd567ee45b7b7e4bc0778640 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Wed, 1 Oct 2014 17:22:58 +0200 Subject: multiconfig.sh: replace GNU sed specific match A SPL/TPL enabled target would was not recognized as such by BSD sed, since it relies on a GNU extension. Instead of or-ing just spell out both matches. Cc: Masahiro Yamada Signed-off-by: Jeroen Hofstee Acked-by: Masahiro Yamada diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh index b5185a8..3dadd71 100644 --- a/scripts/multiconfig.sh +++ b/scripts/multiconfig.sh @@ -69,8 +69,8 @@ get_enabled_subimages() { # CONFIG_SPL=y -> spl # CONFIG_TPL=y -> tpl - sed -n -e 's/^CONFIG_\(SPL\|TPL\)=y$/\1/p' $KCONFIG_CONFIG | \ - tr '[A-Z]' '[a-z]' + sed -n -e 's/^CONFIG_SPL=y$/spl/p' -e 's/^CONFIG_TPL=y$/tpl/p' \ + $KCONFIG_CONFIG } do_silentoldconfig () { -- cgit v0.10.2 From 703a08f2b33b92f64277b0d06d10cc83bdc617f3 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 1 Oct 2014 08:44:55 -0700 Subject: scripts/multiconfig.sh: Fix a typo Fix the spelling of "configs". Signed-off-by: York Sun CC: Masahiro Yamada Acked-by: Masahiro Yamada diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh index 3dadd71..3a963c7 100644 --- a/scripts/multiconfig.sh +++ b/scripts/multiconfig.sh @@ -120,7 +120,7 @@ do_board_defconfig () { if [ ! -r $defconfig_path ]; then echo >&2 "***" - echo >&2 "*** Can't find default configuration \"confis/$1\"!" + echo >&2 "*** Can't find default configuration \"configs/$1\"!" echo >&2 "***" exit 1 fi -- cgit v0.10.2 From 207828e215f7e8331ea3c304b922de9d155fb68e Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Fri, 3 Oct 2014 07:30:15 +0200 Subject: board/BuR: fix pinmux for MII Ethernet Interface The lines COL (collision detect) and CRS (carrier sense) needs to be connected and muxed to the CPSW MAC for a proper function in half-duplex Mode of the interface. Signed-off-by: Hannes Petermaier Cc: Tom Rini diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c index 1a5ffd5..ecb2e7a 100644 --- a/board/BuR/kwb/mux.c +++ b/board/BuR/kwb/mux.c @@ -105,6 +105,8 @@ static struct module_pin_mux i2c0_pin_mux[] = { }; static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c index 210ac71..0ba25ee 100644 --- a/board/BuR/tseries/mux.c +++ b/board/BuR/tseries/mux.c @@ -64,6 +64,8 @@ static struct module_pin_mux spi0_pin_mux[] = { }; static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ @@ -96,6 +98,7 @@ static struct module_pin_mux mii2_pin_mux[] = { {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ + {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* * MII2_CRS is shared with * NAND_WAIT0 -- cgit v0.10.2 From ae1a74ebe7b4627205703f19e60c1c2c2fa06c73 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 3 Oct 2014 11:16:19 +0200 Subject: common/board_r: remove warning in initr_mem for 64-bit phys_size_t Since on powerpc phys_size_t can be unsigned long long, this printout line can result in a not nice compile warning. Signed-off-by: Valentin Longchamp Acked-by: Simon Glass diff --git a/common/board_r.c b/common/board_r.c index c339aad..7e1a76d 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -664,7 +664,7 @@ int initr_mem(void) /* Also take the logbuffer into account (pram is in kB) */ pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; # endif - sprintf(memsz, "%ldk", (gd->ram_size / 1024) - pram); + sprintf(memsz, "%ldk", (long int) ((gd->ram_size / 1024) - pram)); setenv("mem", memsz); return 0; -- cgit v0.10.2 From 787011834ee59f5abf10fdef5a1fc14f89e8e9c0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 3 Oct 2014 15:57:00 -0400 Subject: am335x_evm: Correct BOOTCOUNT driver support We need to set the 'BE' flag here for things to work right. Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index e2f7ead..476430d 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -223,6 +223,7 @@ /* Bootcount using the RTC block */ #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_BOOTCOUNT_AM33XX +#define CONFIG_SYS_BOOTCOUNT_BE /* USB gadget RNDIS */ #define CONFIG_SPL_MUSB_NEW_SUPPORT -- cgit v0.10.2