From afc52db2f76e0215411a916af46c578fcfd02a81 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Fri, 28 Oct 2011 13:15:36 +0800 Subject: powerpc/QorIQ: fix network frame manager TBI PHY address settings TBI PHY address (TBIPA) register has been set in general frame manager phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c So remove the duplicate code on QorIQ frame manager Ethernet related platforms, which include Hydra board, P4080DS board and P2041rdb board. Signed-off-by: Roy Zang Cc: Andy Fleming Signed-off-by: Kumar Gala diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index a7a5e13..962f380 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -377,7 +377,6 @@ void fdt_fixup_board_enet(void *fdt) int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; @@ -387,13 +386,6 @@ int board_eth_init(bd_t *bis) initialize_lane_to_slot(); - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 7ff00d1..1f00c14 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -301,7 +301,6 @@ int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; int i; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; @@ -327,13 +326,6 @@ int board_eth_init(bd_t *bis) SLOT5, /* 17 - Bank 3:D */ }; - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 0a1dfa7..4b0d577 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -139,7 +139,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; @@ -149,13 +148,6 @@ int board_eth_init(bd_t *bis) initialize_lane_to_slot(); - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; -- cgit v0.10.2 From aada81de703e0fb26ae1a8dc8fc8d6a7a37fa3c9 Mon Sep 17 00:00:00 2001 From: chenhui zhao Date: Mon, 3 Oct 2011 08:38:50 -0500 Subject: powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129 Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early verion silicons. This workaround detects if the eTSEC Rx logic is properly initialized, and reinitialize the eTSEC Rx logic. Signed-off-by: Gong Chen Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index a09eb91..253bf08 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -103,6 +103,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 puts("Work-around for Erratum NMG_LBC103 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + puts("Work-around for Erratum NMG ETSEC129 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index c3d6ba9..981d639 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 +#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 78ffc95..160bc05 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -19,6 +19,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -43,6 +44,9 @@ static RTXBD rtx __attribute__ ((aligned(8))); #error "rtx must be 64-bit aligned" #endif +static int tsec_send(struct eth_device *dev, + volatile void *packet, int length); + /* Default initializations for TSEC controllers. */ static struct tsec_info_struct tsec_info[] = { @@ -236,6 +240,87 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); } +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 +/* + * When MACCFG1[Rx_EN] is enabled during system boot as part + * of the eTSEC port initialization sequence, + * the eTSEC Rx logic may not be properly initialized. + */ +void redundant_init(struct eth_device *dev) +{ + struct tsec_private *priv = dev->priv; + tsec_t *regs = priv->regs; + uint t, count = 0; + int fail = 1; + static const u8 pkt[] = { + 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25, + 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00, + 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01, + 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1, + 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00, + 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, + 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, + 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, + 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x71, 0x72}; + + /* Enable promiscuous mode */ + setbits_be32(®s->rctrl, 0x8); + /* Enable loopback mode */ + setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); + /* Enable transmit and receive */ + setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); + + /* Tell the DMA it is clear to go */ + setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); + out_be32(®s->tstat, TSTAT_CLEAR_THALT); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); + + do { + tsec_send(dev, (void *)pkt, sizeof(pkt)); + + /* Wait for buffer to be received */ + for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) { + if (t >= 10 * TOUT_LOOP) { + printf("%s: tsec: rx error\n", dev->name); + break; + } + } + + if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt))) + fail = 0; + + rtx.rxbd[rxIdx].length = 0; + rtx.rxbd[rxIdx].status = + RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + rxIdx = (rxIdx + 1) % PKTBUFSRX; + + if (in_be32(®s->ievent) & IEVENT_BSY) { + out_be32(®s->ievent, IEVENT_BSY); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + } + if (fail) { + printf("loopback recv packet error!\n"); + clrbits_be32(®s->maccfg1, MACCFG1_RX_EN); + udelay(1000); + setbits_be32(®s->maccfg1, MACCFG1_RX_EN); + } + } while ((count++ < 4) && (fail == 1)); + + if (fail) + panic("eTSEC init fail!\n"); + /* Disable promiscuous mode */ + clrbits_be32(®s->rctrl, 0x8); + /* Disable loopback mode */ + clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); +} +#endif + /* Set up the buffers and their descriptors, and bring up the * interface */ @@ -248,6 +333,9 @@ static void startup_tsec(struct eth_device *dev) /* reset the indices to zero */ rxIdx = 0; txIdx = 0; +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + uint svr; +#endif /* Point to the buffer descriptors */ out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx])); @@ -269,6 +357,11 @@ static void startup_tsec(struct eth_device *dev) } rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + svr = get_svr(); + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + redundant_init(dev); +#endif /* Enable Transmit and Receive */ setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); -- cgit v0.10.2 From d37012289df80f3907a54bb01ffc38a394fa0766 Mon Sep 17 00:00:00 2001 From: chenhui zhao Date: Tue, 6 Sep 2011 16:41:18 +0000 Subject: powerpc/mpc8548cds: Fix network initialization Add board_eth_init(). PCIe network card is also supported. Put RGMII init after tsec_eth_init(). Skip initializing eTSEC3 and eTSEC4 with Carrier boards prior to ver 1.3. Signed-off-by: Ebony Zhu Signed-off-by: Zhao Chenhui diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index a8d57cd..d33ef7e 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -33,6 +33,9 @@ #include #include #include +#include +#include +#include #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -287,7 +290,7 @@ void pci_init_board(void) fsl_pcie_init_board(first_free_busno); } -int last_stage_init(void) +void configure_rgmii(void) { unsigned short temp; @@ -295,29 +298,77 @@ int last_stage_init(void) /* This is needed to get the RGMII working for the 1.3+ * CDS cards */ if (get_board_version() == 0x13) { - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 29, 18); - miiphy_read(CONFIG_TSEC1_NAME, + miiphy_read(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, &temp); temp = (temp & 0xf03f); temp |= 2 << 9; /* 36 ohm */ temp |= 2 << 6; /* 39 ohm */ - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, temp); - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 29, 3); - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, 0x8000); } - return 0; + return; } +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif +#ifdef CONFIG_TSEC3 + /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */ + if (get_board_version() >= 0x13) { + SET_STD_TSEC_INFO(tsec_info[num], 3); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; + num++; + } +#endif +#ifdef CONFIG_TSEC4 + /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */ + if (get_board_version() >= 0x13) { + SET_STD_TSEC_INFO(tsec_info[num], 4); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; + num++; + } +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + configure_rgmii(); + + return pci_eth_init(bis); +} +#endif #if defined(CONFIG_OF_BOARD_SETUP) void ft_pci_setup(void *blob, bd_t *bd) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a99f8d5..1a6ba69 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -464,6 +464,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC +#define CONFIG_PHY_MARVELL + #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 -- cgit v0.10.2 From 5c4a3d431e57c6eb9a7663905f47724fbf1f04dd Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 31 Oct 2011 13:30:41 -0500 Subject: powerpc/85xx: fix definition of MAS register macros Some of the MAS register macros do not protect the parameter with parentheses, which could cause wrong values if the parameter includes operators. Also fix the definition of TSIZE_TO_BYTES() so that it actually uses the parameter. This hasn't caused any problems to date because the parameter was always been 'tsize'. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index ef5076b..209103e 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -392,17 +392,17 @@ extern void print_bats(void); */ #define MAS0_TLBSEL_MSK 0x30000000 -#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK) +#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK) #define MAS0_ESEL_MSK 0x0FFF0000 -#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK) +#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK) #define MAS0_NV(x) ((x) & 0x00000FFF) #define MAS1_VALID 0x80000000 #define MAS1_IPROT 0x40000000 -#define MAS1_TID(x) ((x << 16) & 0x3FFF0000) +#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) #define MAS1_TS 0x00001000 -#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) -#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10))) +#define MAS1_TSIZE(x) (((x) << 8) & 0x00000F00) +#define TSIZE_TO_BYTES(x) (1ULL << (((x) * 2) + 10)) #define MAS2_EPN 0xFFFFF000 #define MAS2_X0 0x00000040 -- cgit v0.10.2 From c2efa0aa1e484448d553b37df9738095b113a71c Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 31 Oct 2011 13:30:42 -0500 Subject: powerpc/85xx: fix some comments in the CCSR relocation code Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 5e0d78d..275accc 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -387,7 +387,7 @@ create_ccsr_new_tlb: tlbwe /* - * Create a TLB for the old location of CCSR. Register R9 is reserved + * Create a TLB for the current location of CCSR. Register R9 is reserved * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: @@ -446,7 +446,7 @@ create_temp_law: */ read_old_ccsrbar: lwz r0, 0(r9) /* CCSRBARH */ - lwz r0, 4(r9) /* CCSRBARH */ + lwz r0, 4(r9) /* CCSRBARL */ isync /* -- cgit v0.10.2 From 452ad61c3feeffbf2b5ff74f0a6797af3ba4882c Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 31 Oct 2011 13:30:43 -0500 Subject: powerpc/85xx: add some missing sync instructions in the CCSR relocation code Calls to tlbwe and tlbsx should be preceded with an isync/msync pair. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 275accc..e519f35 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -352,6 +352,8 @@ purge_old_ccsr_tlb: li r1, 0 mtspr MAS6, r1 /* Search the current address space and PID */ + isync + msync tlbsx 0, r8 mfspr r1, MAS1 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ @@ -359,6 +361,8 @@ purge_old_ccsr_tlb: rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ mtspr MAS1, r1 + isync + msync tlbwe 1: -- cgit v0.10.2 From 19e438412416c4cd4066dfa7aca679fe291f13e1 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 31 Oct 2011 13:30:44 -0500 Subject: powerpc/85xx: verify the current address of CCSR before relocating it Verify that CCSR is actually located where it is supposed to be before we relocate it. This is useful in detecting U-Boot configurations that are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT). If the current value is wrong, we enter an infinite loop, which is handy for debuggers. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index e519f35..d494528 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -411,6 +411,33 @@ create_ccsr_old_tlb: msync tlbwe + /* + * We have a TLB for what we think is the current (old) CCSR. Let's + * verify that, otherwise we won't be able to move it. + * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only + * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. + */ +verify_old_ccsr: + lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h + ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l +#ifdef CONFIG_FSL_CORENET + lwz r1, 4(r9) /* CCSRBARL */ +#else + lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ + slwi r1, r1, 12 +#endif + + cmpl 0, r0, r1 + + /* + * If the value we read from CCSRBARL is not what we expect, then + * enter an infinite loop. This will at least allow a debugger to + * halt execution and examine TLBs, etc. There's no point in going + * on. + */ +infinite_debug_loop: + bne infinite_debug_loop + #ifdef CONFIG_FSL_CORENET #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) -- cgit v0.10.2 From 72243c0194051f609fe3b24963465555c377eaaa Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 31 Oct 2011 13:30:45 -0500 Subject: powerpc/85xx: resize the boot page TLB before relocating CCSR On some Freescale systems (e.g. those booted from the on-chip ROM), the TLB that covers the boot page can also cover CCSR, which breaks the CCSR relocation code. To fix this, we resize the boot page TLB so that it only covers the 4KB boot page. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index d494528..7bd5cc0 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -319,6 +319,55 @@ l2_disabled: #endif /* CONFIG_MPC8569 */ /* + * Search for the TLB that covers the code we're executing, and shrink it + * so that it covers only this 4K page. That will ensure that any other + * TLB we create won't interfere with it. We assume that the TLB exists, + * which is why we don't check the Valid bit of MAS1. + * + * This is necessary, for example, when booting from the on-chip ROM, + * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. + * If we don't shrink this TLB now, then we'll accidentally delete it + * in "purge_old_ccsr_tlb" below. + */ + bl nexti /* Find our address */ +nexti: mflr r1 /* R1 = our PC */ + li r2, 0 + mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ + isync + msync + tlbsx 0, r1 /* This must succeed */ + + /* Set the size of the TLB to 4KB */ + mfspr r3, MAS1 + li r2, 0xF00 + andc r3, r3, r2 /* Clear the TSIZE bits */ + ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l + mtspr MAS1, r3 + + /* + * Set the base address of the TLB to our PC. We assume that + * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. + */ + lis r3, MAS2_EPN@h + ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ + + and r1, r1, r3 /* Our PC, rounded down to the nearest page */ + + mfspr r2, MAS2 + andc r2, r2, r3 + or r2, r2, r1 + mtspr MAS2, r2 /* Set the EPN to our PC base address */ + + mfspr r2, MAS3 + andc r2, r2, r3 + or r2, r2, r1 + mtspr MAS3, r2 /* Set the RPN to our PC base address */ + + isync + msync + tlbwe + +/* * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default * location is not where we want it. This typically happens on a 36-bit * system, where we want to move CCSR to near the top of 36-bit address space. -- cgit v0.10.2 From 4765fb7d739d0a46a466f96cf4ef0126d44ab5d0 Mon Sep 17 00:00:00 2001 From: Ramneek Mehresh Date: Tue, 8 Nov 2011 13:09:20 +0530 Subject: powerpc/85xx: Fix warning for USB device-fixup Fix USB device-fixup warning "node not found". This was occuring because of static nature of start_offset variable Static start_offset was storing offset of last node modified, and was becoming issue if node fixup is carried multiple times, resulting in "node not found" warning Signed-off-by: Ramneek Mehresh Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 112c603..d07ae1b 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -87,13 +87,12 @@ void ft_fixup_num_cores(void *blob) { #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ #ifdef CONFIG_HAS_FSL_DR_USB -static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, - const char *phy_type) +static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, + const char *phy_type, int start_offset) { const char *compat = "fsl-usb2-dr"; const char *prop_mode = "dr_mode"; const char *prop_type = "phy_type"; - static int start_offset = -1; int node_offset; int err; @@ -102,7 +101,7 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, if (node_offset < 0) { printf("WARNING: could not find compatible node %s: %s.\n", compat, fdt_strerror(node_offset)); - return; + return -1; } if (mode) { @@ -121,16 +120,18 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, prop_type, compat, fdt_strerror(err)); } - start_offset = node_offset; + return node_offset; } void fdt_fixup_dr_usb(void *blob, bd_t *bd) { const char *modes[] = { "host", "peripheral", "otg" }; - const char *phys[] = { "ulpi", "umti" }; + const char *phys[] = { "ulpi", "utmi" }; const char *mode = NULL; const char *phy_type = NULL; char usb1_defined = 0; + int usb_mode_off = -1; + int usb_phy_off = -1; char str[5]; int i, j; @@ -153,11 +154,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) } } if (mode_idx >= 0) - fdt_fixup_usb_mode_phy_type(blob, - modes[mode_idx], NULL); + usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, + modes[mode_idx], NULL, usb_mode_off); if (phy_idx >= 0) - fdt_fixup_usb_mode_phy_type(blob, - NULL, phys[phy_idx]); + usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, + NULL, phys[phy_idx], usb_phy_off); if (!strcmp(str, "usb1")) usb1_defined = 1; if (mode_idx < 0 && phy_idx < 0) @@ -165,11 +166,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) } } if (!usb1_defined) { + int usb_off = -1; mode = getenv("usb_dr_mode"); phy_type = getenv("usb_phy_type"); if (!mode && !phy_type) return; - fdt_fixup_usb_mode_phy_type(blob, mode, phy_type); + fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off); } } #endif /* CONFIG_HAS_FSL_DR_USB */ -- cgit v0.10.2 From a311db6941791617cb4b6bc3c67b47a8b1132e95 Mon Sep 17 00:00:00 2001 From: Ramneek Mehresh Date: Tue, 8 Nov 2011 10:21:28 +0530 Subject: powerpc/85xx: Make inclusion of USB device fixup conditional Include call to usb device-fixup only when CONFIG_HAS_FSL_DR_USB is defined for the platform - P1020RDB, P1010RDB, P1020-PC Signed-off-by: Ramneek Mehresh Signed-off-by: Kumar Gala diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 03e9da1..b9e66f7 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -275,7 +275,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif /* P1014 and it's derivatives don't support CAN and eTSEC3 */ if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 864b3ce..cfbae69 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -264,7 +264,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) /* Delete eLBC node as it is muxed with USB2 controller */ diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 4671128..a60c5a2 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -444,6 +444,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_board_fixup_qe_pins(blob); #endif #endif + +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif } #endif -- cgit v0.10.2 From 50cf3d17ce021fc6156d41abfbaa5490e8238c3b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 31 Oct 2011 22:13:26 -0500 Subject: powerpc/85xx: Add support for Book-E MMU Arch v2.0 A few of the config registers changed definition between MMU v1.0 and MMUv2.0. The new e6500 core from Freescale implements v2.0 of the architecture. Specifically, how we determine the size of TLB entries we support in the variable size (or TLBCAM/TLB1) array is specified in a new register (TLBnPS - TLB n Page size) instead of via TLBnCFG. Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 01a3561..80ad04a 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -252,16 +252,20 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) unsigned int tlb_size; unsigned int wimge = 0; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; - unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; + unsigned int max_cam; u64 size, memsize = (u64)memsize_in_meg << 20; #ifdef CONFIG_SYS_PPC_DDR_WIMGE wimge = CONFIG_SYS_PPC_DDR_WIMGE; #endif size = min(memsize, CONFIG_MAX_MEM_MAPPED); - - /* Convert (4^max) kB to (2^max) bytes */ - max_cam = max_cam * 2 + 10; + if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { + /* Convert (4^max) kB to (2^max) bytes */ + max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10; + } else { + /* Convert (2^max) kB to (2^max) bytes */ + max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10; + } for (i = 0; size && i < 8; i++) { int ram_tlb_index = find_free_tlbcam(); diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 1b96b84..4e32639 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -513,7 +513,13 @@ #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ +#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ +#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */ #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ +#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */ +#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ +#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ +#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ -- cgit v0.10.2 From cfee584eeadbd6141f6729b19b424448599e4e47 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Tue, 1 Nov 2011 18:58:20 +0530 Subject: fsl_ifc: Fixed a bug in the erratum handling code for IFC_A003399 Wrong pointer was being used to copy code into L2SRAM. Also removed the unreferenced variable l2srbar. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 4ef3c9a..091af7c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -71,7 +71,7 @@ void cpu_init_early_f(void) #endif #if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; - u32 *l2srbar, *dst, *src; + u32 *dst, *src; void (*setup_ifc_sram)(void); #endif @@ -137,7 +137,7 @@ void cpu_init_early_f(void) dst = (u32 *) SRAM_BASE_ADDR; src = (u32 *) setup_ifc; for (i = 0; i < 1024; i++) - *l2srbar++ = *src++; + *dst++ = *src++; setup_ifc_sram(); -- cgit v0.10.2 From e4382acb1ff1c0686d86f4cac4f2e12f89c534cf Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 8 Nov 2011 11:03:54 -0600 Subject: powerpc/85xx: Fix MPC8572DS NAND build Reduce NAND SPL build size by not include TLB entries that arent used by it. Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 575bdb5..6d60513 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_NAND_SPL /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -76,6 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), +#endif /* *I*G - NAND */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, -- cgit v0.10.2 From 8d22ddca3db2577b7f2bf1040972231279288847 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 09:10:49 -0600 Subject: powerpc/85xx: Fix NAND SPL support We cause CCSRBAR to be relocated in the SPL phase of NAND boot which isn't expected and breaks things. Fixing the board config.h to NOT relocate CCSR during the CONFIG_NAND_SPL phase. Signed-off-by: Kumar Gala diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index d4e3ef5..16db98f 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -131,7 +131,7 @@ #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_SPL) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 19d3271..ab27b98 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -108,7 +108,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_SPL) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index ffee8fc..d7910e1 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -115,7 +115,7 @@ #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_SPL) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 883d44e..00fa74d 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -151,7 +151,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_SPL) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index bcfb034..5a69902 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -221,7 +221,7 @@ /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k SPL code*/ -#if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_SPL) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif -- cgit v0.10.2 From 71775d3b54780f1901ff6eac7c5ae05676938107 Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Thu, 3 Nov 2011 15:18:06 +0800 Subject: powerpc/mpc85xx: Set SYSCLK to the required frequency For ICS307-02, there is one general expression to generate SYSCLK: CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) If we want the required frequency for SYSCLK, we must find one solution to generate this frequency, this solution includes VDW, RDW and OD. For OD, there are only eight option value: 10, 2, 8, 4, 5, 7, 3, 6. For RDW, the range is 1 to 127. For VDW, the range is 4 to 511. First, we use one OD, RDW and required SYSCLK to calculate the VDW, if VDW is in it's range, we will calculate the CLK1Frequency with the OD, RDW and VDW calculated, and we will check this percent (CLK1Frequency / required SYSCLK), and the precision is 1/1000. if the percent is less than 1/1000, we think the CLK1Frequency is we want. Otherwise, We will continue to calculate it with the next OD and RDW. Signed-off-by: Jerry Huang Signed-off-by: Kumar Gala diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index 89d8810..6acbc36 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -31,12 +31,81 @@ #include "pixis.h" #endif +/* define for SYS CLK or CLK1Frequency */ +#define TTL 1 +#define CLK2 0 +#define CRYSTAL 0 +#define MAX_VDW (511 + 8) +#define MAX_RDW (127 + 2) +#define MIN_VDW (4 + 8) +#define MIN_RDW (1 + 2) +#define NUM_OD_SETTING 8 +/* + * These defines cover the industrial temperature range part, + * for commercial, change below to 400000 and 55000, respectively + */ +#define MAX_VCO 360000 +#define MIN_VCO 60000 + /* decode S[0-2] to Output Divider (OD) */ static u8 ics307_s_to_od[] = { 10, 2, 8, 4, 5, 7, 3, 6 }; /* + * Find one solution to generate required frequency for SYSCLK + * out_freq: KHz, required frequency to the SYSCLK + * the result will be retuned with component RDW, VDW, OD, TTL, + * CLK2 and crystal + */ +unsigned long ics307_sysclk_calculator(unsigned long out_freq) +{ + const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; + unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; + unsigned long tmp_out, diff, result = 0; + int found = 0; + + for (odp = 0; odp < NUM_OD_SETTING; odp++) { + od = ics307_s_to_od[odp]; + if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO) + continue; + for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) { + /* Calculate the VDW */ + vdw = out_freq * 1000 * od * rdw / (input_freq * 2); + if (vdw > MAX_VDW) + vdw = MAX_VDW; + if (vdw < MIN_VDW) + continue; + /* Calculate the temp out frequency */ + tmp_out = input_freq * 2 * vdw / (rdw * od * 1000); + diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out); + /* + * calculate the percent, the precision is 1/1000 + * If greater than 1/1000, continue + * otherwise, we think the solution is we required + */ + if (diff * 1000 / out_freq > 1) + continue; + else { + s_vdw = vdw; + s_rdw = rdw; + s_odp = odp; + found = 1; + break; + } + } + } + + if (found) + result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 | + CLK2 << 19 | TTL << 21 | CRYSTAL << 22; + + debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8, + ics307_s_to_od[s_odp]); + return result; +} + +/* * Calculate frequency being generated by ICS307-02 clock chip based upon * the control bytes being programmed into it. */ diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h index db3dbc4..3757912 100644 --- a/board/freescale/common/ics307_clk.h +++ b/board/freescale/common/ics307_clk.h @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,8 +23,10 @@ #define __ICS_CLK_H_ 1 #ifndef __ASSEMBLY__ + extern unsigned long get_board_sys_clk(void); extern unsigned long get_board_ddr_clk(void); +extern unsigned long ics307_sysclk_calculator(unsigned long out_freq); #endif #endif /* __ICS_CLK_H_ */ diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c index 765f035..276ae3c 100644 --- a/board/freescale/common/ngpixis.c +++ b/board/freescale/common/ngpixis.c @@ -156,9 +156,29 @@ static void pixis_dump_regs(void) } #endif +void pixis_sysclk_set(unsigned long sysclk) +{ + unsigned long freq_word; + u8 sclk0, sclk1, sclk2; + + freq_word = ics307_sysclk_calculator(sysclk); + sclk2 = freq_word & 0xff; + sclk1 = (freq_word >> 8) & 0xff; + sclk0 = (freq_word >> 16) & 0xff; + + /* set SYSCLK enable bit */ + PIXIS_WRITE(vcfgen0, 0x01); + + /* SYSCLK to required frequency */ + PIXIS_WRITE(sclk[0], sclk0); + PIXIS_WRITE(sclk[1], sclk1); + PIXIS_WRITE(sclk[2], sclk2); +} + int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned int i; + unsigned long sysclk; char *p_altbank = NULL; #ifdef DEBUG char *p_dump = NULL; @@ -182,6 +202,12 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) continue; } #endif + if (strcmp(argv[i], "sysclk") == 0) { + sysclk = simple_strtoul(argv[i + 1], NULL, 0); + i += 1; + pixis_sysclk_set(sysclk); + continue; + } unknown_param = argv[i]; } @@ -219,4 +245,5 @@ U_BOOT_CMD( #ifdef DEBUG "pixis_reset dump - display the PIXIS registers\n" #endif + "pixis_reset sysclk - reset with SYSCLK frequency(KHz)\n" ); -- cgit v0.10.2 From 07b5edc20633b803ac047bddff569432dab7a917 Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Wed, 2 Nov 2011 09:16:44 +0800 Subject: powerpc/85xx: Set max alloc length to 10MB on P1022DS In order to support 1920x01080 resolution, we must increase the alloc length. Signed-off-by: Jerry Huang CC: Anatolij Gustschin Acked-by: Timur Tabi Signed-off-by: Kumar Gala diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 0077060..1158fec 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -173,7 +173,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) /* * Serial Port -- cgit v0.10.2 From c27ff9b623067549e937bd419adb98f2db2b15c7 Mon Sep 17 00:00:00 2001 From: Xie Xiaobo Date: Fri, 11 Nov 2011 17:19:41 +0800 Subject: phylib: Enable AR8021 phy support Enable AR8021 as it used on Freescale boards: P1020RDB-PC, P1021RDB-PC, P2020RDB-PC, P1020UTM-PC, and P1020MSBG-PC. Signed-off-by: Xie Xiaobo Signed-off-by: Kumar Gala diff --git a/include/config_phylib_all_drivers.h b/include/config_phylib_all_drivers.h index 903c7a7..1db7cec 100644 --- a/include/config_phylib_all_drivers.h +++ b/include/config_phylib_all_drivers.h @@ -22,6 +22,7 @@ #define CONFIG_PHY_REALTEK #define CONFIG_PHY_NATSEMI #define CONFIG_PHY_LXT +#define CONFIG_PHY_ATHEROS #ifdef CONFIG_PHYLIB_10G #define CONFIG_PHY_TERANETICS -- cgit v0.10.2 From e4c9a35d21ac8d27e90db9448cfd1a8a230c8388 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 09:56:41 -0600 Subject: arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warning Fix: cpu_init.c: In function 'cpu_init_r': cpu_init.c:320:7: warning: variable 'l2srbar' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 0a4ce53..b9a8193 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -317,7 +317,6 @@ int cpu_init_r(void) volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile uint cache_ctl; uint svr, ver; - uint l2srbar; u32 l2siz_field; svr = get_svr(); @@ -385,8 +384,8 @@ int cpu_init_r(void) if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { puts("already enabled"); - l2srbar = l2cache->l2srbar0; #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) + u32 l2srbar = l2cache->l2srbar0; if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE && l2srbar >= CONFIG_SYS_FLASH_BASE) { l2srbar = CONFIG_SYS_INIT_L2_ADDR; -- cgit v0.10.2 From 3d6d9c3116a93d49a764f65df6d3718aa356f436 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 09:59:32 -0600 Subject: arch/powerpc/cpu/mpc85xx/tlb.c: Fix GCC 4.6 build warning Fix: tlb.c: In function 'disable_tlb': tlb.c:175:34: warning: variable '_mas7' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 80ad04a..929f6a6 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -172,7 +172,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, void disable_tlb(u8 esel) { - u32 _mas0, _mas1, _mas2, _mas3, _mas7; + u32 _mas0, _mas1, _mas2, _mas3; free_tlb_cam(esel); @@ -180,14 +180,13 @@ void disable_tlb(u8 esel) _mas1 = 0; _mas2 = 0; _mas3 = 0; - _mas7 = 0; mtspr(MAS0, _mas0); mtspr(MAS1, _mas1); mtspr(MAS2, _mas2); mtspr(MAS3, _mas3); #ifdef CONFIG_ENABLE_36BIT_PHYS - mtspr(MAS7, _mas7); + mtspr(MAS7, 0); #endif asm volatile("isync;msync;tlbwe;isync"); -- cgit v0.10.2 From e55d637a5f0aff493d6fa2af96ff31cd193b2822 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:00:23 -0600 Subject: arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: Fix GCC 4.6 build warning Fix: fsl_lbc.c: In function 'upmconfig': fsl_lbc.c:110:9: warning: variable 'mdr' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index d78962f..587576b 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -107,7 +107,7 @@ void init_early_memctl_regs(void) void upmconfig(uint upm, uint *table, uint size) { fsl_lbc_t *lbc = LBC_BASE_ADDR; - int i, mdr, mad, old_mad = 0; + int i, mad, old_mad = 0; u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK); u32 msel = BR_UPMx_TO_MSEL(upm); u32 *mxmr = &lbc->mamr + upm; @@ -138,7 +138,7 @@ void upmconfig(uint upm, uint *table, uint size) for (i = 0; i < size; i++) { out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i); out_be32(&lbc->mdr, table[i]); - mdr = in_be32(&lbc->mdr); + (void)in_be32(&lbc->mdr); *dummy = 0; do { mad = in_be32(mxmr) & MxMR_MAD_MSK; -- cgit v0.10.2 From 67926c2a1d872deb12f21221e2a6d28ef575f956 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:01:06 -0600 Subject: board/freescale/common/cds_pci_ft.c: Fix GCC 4.6 build warning Fix: cds_pci_ft.c: In function 'cds_pci_fixup': cds_pci_ft.c:31:12: warning: variable 'tmp' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 6f221af..8a09f99 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -28,13 +28,12 @@ #if defined(CONFIG_OF_BOARD_SETUP) static void cds_pci_fixup(void *blob) { - int node, tmp[2]; + int node; const char *path; int len, slot, i; u32 *map = NULL; node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; if (node >= 0) { path = fdt_getprop(blob, node, "pci0", NULL); if (path) { -- cgit v0.10.2 From 8dbd4b746da3c3dec6c4d8c8dc959ffeb15865de Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:02:11 -0600 Subject: board/freescale/common/pixis.c: Fix GCC 4.6 build warning Fix: pixis.c: In function 'strfractoint': pixis.c:383:6: warning: variable 'intarr_len' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index a35b5cf..8d07061 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -380,7 +380,7 @@ static unsigned long strfractoint(char *strptr) { int i, j; int mulconst; - int intarr_len, no_dec = 0; + int no_dec = 0; unsigned long intval = 0, decval = 0; char intarr[3], decarr[3]; @@ -399,8 +399,6 @@ static unsigned long strfractoint(char *strptr) i++; } - /* Assign length of integer part to intarr_len. */ - intarr_len = i; intarr[i] = '\0'; if (no_dec) { -- cgit v0.10.2 From 945f43101ec79fa1c9ced8e7f3a6418b273ec55d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:02:40 -0600 Subject: board/freescale/mpc8548cds/mpc8548cds.c: Fix GCC 4.6 build warning Fix: mpc8548cds.c: In function 'local_bus_init': mpc8548cds.c:87:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable] mpc8548cds.c: In function 'lbc_sdram_init': mpc8548cds.c:121:7: warning: variable 'cpu_board_rev' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index d33ef7e..e5563f7 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -84,12 +84,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; if (clkdiv == 16) { @@ -118,7 +116,6 @@ void lbc_sdram_init(void) uint idx; volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint cpu_board_rev; uint lsdmr_common; puts("LBC SDRAM: "); @@ -140,7 +137,6 @@ void lbc_sdram_init(void) /* * MPC8548 uses "new" 15-16 style addressing. */ - cpu_board_rev = get_cpu_board_revision(); lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; lsdmr_common |= LSDMR_BSMA1516; -- cgit v0.10.2 From 502dd36b78b4b0d1b9e347609f53782f66b5edf3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:03:01 -0600 Subject: board/freescale/mpc8568mds/mpc8568mds.c: Fix GCC 4.6 build warning Fix: mpc8568mds.c: In function 'local_bus_init': mpc8568mds.c:150:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable] mpc8568mds.c: In function 'pib_init': mpc8568mds.c:271:11: warning: variable 'orig_i2c_bus' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 225c5d8..6e3945e 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -147,12 +147,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; if (clkdiv == 16) { @@ -302,6 +300,7 @@ pib_init(void) i2c_write(0x27, 0x3, 1, &val8, 1); asm("eieio"); + i2c_set_bus_num(orig_i2c_bus); } #ifdef CONFIG_PCI -- cgit v0.10.2 From e3779209ddd40f52874b27a7bca3c0a153c5ad90 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:03:12 -0600 Subject: board/freescale/mpc8569mds/mpc8569mds.c: Fix GCC 4.6 build warning mpc8569mds.c: In function 'local_bus_init': mpc8569mds.c:306:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 89557d2..d119c65 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -303,12 +303,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) -- cgit v0.10.2 From dbe128a9bd60cb5a292c7daeec3a7a13f5d142b8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:03:26 -0600 Subject: board/sbc8548/sbc8548.c: Fix GCC 4.6 build warning Fix: sbc8548.c: In function 'local_bus_init': sbc8548.c:80:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index e1a3ea3..26095a5 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -77,12 +77,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) { -- cgit v0.10.2 From ebba0d4bc5a0fd4eda2d19493a8a81f4f8a9497b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:03:43 -0600 Subject: board/sbc8560/sbc8560.c: Fix GCC 4.6 build warning Fix: sbc8560.c: In function 'ft_board_setup': sbc8560.c:351:12: warning: variable 'tmp' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index c5fe92e..98bc7df 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -348,7 +348,7 @@ phys_size_t fixed_sdram(void) void ft_board_setup(void *blob, bd_t *bd) { - int node, tmp[2]; + int node; #ifdef CONFIG_PCI const char *path; #endif @@ -356,7 +356,6 @@ ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; if (node >= 0) { #ifdef CONFIG_PCI path = fdt_getprop(blob, node, "pci0", NULL); -- cgit v0.10.2 From 9ccfed20dae7b2668a82087f40303d85771bb833 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:03:55 -0600 Subject: drivers/net/fm/fm.c: Fix GCC 4.6 build warning Fix: fm.c: In function 'fm_init_common': fm.c:398:6: warning: variable 'n' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 23ef14b..846c372 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -395,7 +395,6 @@ int fm_init_common(int index, struct ccsr_fman *reg) int dev = CONFIG_SYS_MMC_ENV_DEV; void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH); u32 cnt = CONFIG_SYS_FMAN_FW_LENGTH / 512; - u32 n; u32 blk = CONFIG_SYS_QE_FW_IN_MMC / 512; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); @@ -405,7 +404,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) printf("\nMMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); - n = mmc->block_dev.block_read(dev, blk, cnt, addr); + (void)mmc->block_dev.block_read(dev, blk, cnt, addr); /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); } -- cgit v0.10.2 From dd22f7cf2c247eacc18ca5845a44c412946bd992 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:04:15 -0600 Subject: drivers/usb/host/ehci-fsl.c: Fix GCC 4.6 build warning Fix: ehci-fsl.c: In function 'ehci_hcd_init': ehci-fsl.c:43:7: warning: variable 'usb_phy' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 5a65d92..b2d294e 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -40,11 +40,13 @@ int ehci_hcd_init(void) { struct usb_ehci *ehci; - char usb_phy[5]; const char *phy_type = NULL; size_t len; +#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY + char usb_phy[5]; usb_phy[0] = '\0'; +#endif ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); -- cgit v0.10.2 From 9cc971b90fd8ed221632da2ae2812f368a2a507d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:04:33 -0600 Subject: drivers/qe/uec.c: Fix GCC 4.6 build warning uec.c: In function 'uec_stop': uec.c:267:22: warning: variable 'uccf' set but not used [-Wunused-but-set-variable] uec.c: In function 'uec_set_mac_if_mode': uec.c:328:15: warning: variable 'uec_info' set but not used [-Wunused-but-set-variable] uec.c: In function 'adjust_link': uec.c:519:11: warning: variable 'uec_regs' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 1ecb137..3e46e35 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -264,13 +264,10 @@ static int uec_open(uec_private_t *uec, comm_dir_e mode) static int uec_stop(uec_private_t *uec, comm_dir_e mode) { - ucc_fast_private_t *uccf; - if (!uec || !uec->uccf) { printf("%s: No handle passed.\n", __FUNCTION__); return -EINVAL; } - uccf = uec->uccf; /* check if the UCC number is in range. */ if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { @@ -325,7 +322,6 @@ static int uec_set_mac_if_mode(uec_private_t *uec, phy_interface_t if_mode, int speed) { phy_interface_t enet_if_mode; - uec_info_t *uec_info; uec_t *uec_regs; u32 upsmr; u32 maccfg2; @@ -335,7 +331,6 @@ static int uec_set_mac_if_mode(uec_private_t *uec, return -EINVAL; } - uec_info = uec->uec_info; uec_regs = uec->uec_regs; enet_if_mode = if_mode; @@ -516,12 +511,10 @@ bus_fail: static void adjust_link(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv; - uec_t *uec_regs; struct uec_mii_info *mii_info = uec->mii_info; extern void change_phy_interface_mode(struct eth_device *dev, phy_interface_t mode, int speed); - uec_regs = uec->uec_regs; if (mii_info->link) { /* Now we make sure that we can be in full duplex mode. -- cgit v0.10.2 From 667bc17e07e0675164e0291c3bdbd7866de0248c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:05:21 -0600 Subject: arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning Fix: options.c: In function 'populate_memctl_options': options.c:486:28: warning: variable 'pdodt' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 4dc748b..00ec57b 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -483,7 +483,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, unsigned int i; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; +#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) const struct dynamic_odt *pdodt = odt_unknown; +#endif ulong ddr_freq; /* @@ -493,6 +495,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; +#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) /* Chip select options. */ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { switch (pdimm[0].n_ranks) { @@ -546,6 +549,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, break; } } +#endif /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { -- cgit v0.10.2 From c1ee16b8e02cd974d7ce9bfb9578e6a1557c2af2 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:05:01 -0600 Subject: arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warning Fix: fsl_corenet_serdes.c: In function 'fsl_serdes_init': fsl_corenet_serdes.c:511:8: warning: variable 'buf' set but not used [-Wunused-but-set-variable] fsl_corenet_serdes.c:498:18: warning: variable 'lane_prtcl' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 89ed5b4..4b52dad 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -495,7 +495,6 @@ void fsl_serdes_init(void) int cfg; serdes_corenet_t *srds_regs; int lane, bank, idx; - enum srds_prtcl lane_prtcl; int have_bank[SRDS_MAX_BANK] = {}; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 u32 serdes8_devdisr = 0; @@ -507,6 +506,7 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; @@ -516,6 +516,7 @@ void fsl_serdes_init(void) */ if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; +#endif /* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -617,7 +618,10 @@ void fsl_serdes_init(void) } } +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9) for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl; + idx = serdes_get_lane_idx(lane); lane_prtcl = serdes_get_prtcl(cfg, lane); @@ -729,6 +733,7 @@ void fsl_serdes_init(void) #endif } +#endif #ifdef DEBUG puts("\n"); -- cgit v0.10.2 From dea7f88726cb56ebb0fc1369182c37ebabe677a7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Nov 2011 10:05:10 -0600 Subject: arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning Fix: ctrl_regs.c: In function 'set_ddr_sdram_cfg_2': ctrl_regs.c:641:15: warning: variable 'rcw_en' set but not used [-Wunused-but-set-variable] ctrl_regs.c: In function 'compute_fsl_memctl_config_regs': ctrl_regs.c:951:31: warning: array subscript is above array bounds [-Warray-bounds] ctrl_regs.c:752:34: warning: array subscript is above array bounds [-Warray-bounds] Signed-off-by: Kumar Gala diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 15cd375..2067d53 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -672,7 +672,6 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, rcw_en = 1; ap_en = popts->ap_en; } else { - rcw_en = 0; ap_en = 0; } @@ -702,9 +701,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((obc_cfg & 0x1) << 6) | ((ap_en & 0x1) << 5) | ((d_init & 0x1) << 4) -#ifdef CONFIG_FSL_DDR3 | ((rcw_en & 0x1) << 2) -#endif | ((md_en & 0x1) << 0) ); debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); @@ -745,7 +742,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, #ifdef CONFIG_FSL_DDR3 if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < 4; i++) { + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (popts->rtt_override) rtt_wr = popts->rtt_wr_override_value; else @@ -944,7 +941,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < 4; i++) { + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (popts->rtt_override) rtt = popts->rtt_override_value; else -- cgit v0.10.2 From 4589728e214958a4e6e011a081a68d360c49d7a5 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Nov 2011 08:14:53 -0600 Subject: powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND Size grew a bit so nand-spl didn't fit in 4k, reduce done by removing LAW entries not needed during SPL phase. Signed-off-by: Kumar Gala diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 5ff6ea6..7968919 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -25,15 +25,17 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#ifndef CONFIG_NAND_SPL SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#endif #ifdef CONFIG_VSC7385_ENET SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif +#endif + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); -- cgit v0.10.2