From 8febd13c69cb68652577d1a9fcbde954bf784155 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 18 Jul 2008 16:52:23 +0200 Subject: Update Freescale 85xx boards to sys_eeprom.c The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID format, and so it obsoletes board/freescale/common/cds_eeprom.c. Freescale 86xx boards already use sys_eeprom.c, so this patch migrates the remaining Freescale 85xx boards to use it as well. cds_eeprom.c is deleted. Signed-off-by: Timur Tabi diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 8584374..02a824d 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -30,7 +30,6 @@ endif LIB = $(obj)lib$(VENDOR).a COBJS-${CONFIG_FSL_CADMUS} += cadmus.o -COBJS-${CONFIG_FSL_CDS_EEPROM} += cds_eeprom.o COBJS-${CONFIG_FSL_VIA} += cds_via.o COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o COBJS-${CONFIG_FSL_PIXIS} += pixis.o diff --git a/board/freescale/common/cds_eeprom.c b/board/freescale/common/cds_eeprom.c deleted file mode 100644 index 5034e0c..0000000 --- a/board/freescale/common/cds_eeprom.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -#include "eeprom.h" - - -typedef struct { - char idee_pcbid[4]; /* "CCID" for CDC v1.X */ - u8 idee_major; - u8 idee_minor; - char idee_serial[10]; - char idee_errata[2]; - char idee_date[8]; /* yyyymmdd */ - /* The rest of the EEPROM space is reserved */ -} id_eeprom_t; - - -unsigned int -get_cpu_board_revision(void) -{ - uint major = 0; - uint minor = 0; - - id_eeprom_t id_eeprom; - - i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, - (uchar *) &id_eeprom, sizeof(id_eeprom)); - - major = id_eeprom.idee_major; - minor = id_eeprom.idee_minor; - - if (major == 0xff && minor == 0xff) { - major = minor = 0; - } - - return MPC85XX_CPU_BOARD_REV(major,minor); -} diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 29dff32..bfd86f5 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -44,7 +44,6 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_VIA -#define CONFIG_FSL_CDS_EEPROM /* * When initializing flash, if we cannot find the manufacturer ID, @@ -328,11 +327,17 @@ extern unsigned long get_clock_freq(void); #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CFG_I2C_EEPROM_CCID +#define CFG_ID_EEPROM +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR_LEN 2 + /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index ec0b4ff..06965ed 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -50,7 +50,6 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_VIA -#define CONFIG_FSL_CDS_EEPROM /* * When initializing flash, if we cannot find the manufacturer ID, @@ -352,11 +351,17 @@ extern unsigned long get_clock_freq(void); #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CFG_I2C_EEPROM_CCID +#define CFG_ID_EEPROM +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR_LEN 2 + /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index c07a725..a92c0fe 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -43,7 +43,7 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_VIA -#define CONFIG_FSL_CDS_EEPROM + /* * When initializing flash, if we cannot find the manufacturer ID, @@ -325,11 +325,17 @@ extern unsigned long get_clock_freq(void); #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CFG_I2C_EEPROM_CCID +#define CFG_ID_EEPROM +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR_LEN 2 + /* * General PCI * Addresses are mapped 1-1. -- cgit v0.10.2 From 7a47753ddcaebbf2142809842f70c5f723bd9ddb Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Fri, 15 Aug 2008 15:42:12 +0200 Subject: 85xx: Socrates: Major code update. - Update the local bus ranges in the FDT for Linux for the various devices connected to the local bus via chip-select. - Set the LCRR_DBYP bit in the LCRR for local bus frequencies lower than 66 MHz and uses I/O accessor functions consequently. - UPM data update. - Update of default environment and configuration. Use I2C multibus as we do have two I2C buses. Also enable sdram and ext2 commands. Signed-off-by: Wolfgang Grandegger Signed-off-by: Sergei Poselenov Signed-off-by: Detlev Zundel diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index d791f11..63694a7 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -37,9 +37,8 @@ #include #include -#if defined(CFG_FPGA_BASE) #include "upm_table.h" -#endif + DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[]; /* FLASH chips info */ @@ -50,6 +49,7 @@ ulong flash_get_size (ulong base, int banknum); int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + char *src; int f; char *s = getenv("serial#"); @@ -79,10 +79,6 @@ int checkboard (void) * Initialize local bus. */ local_bus_init (); -#if defined(CFG_FPGA_BASE) - /* Init UPMA for FPGA access */ - upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); -#endif return 0; } @@ -149,15 +145,34 @@ int misc_init_r (void) */ void local_bus_init (void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + sys_info_t sysinfo; + uint clkdiv; + uint lbc_mhz; + uint lcrr = CFG_LBC_LCRR; + + get_sys_info (&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ + if (lbc_mhz >= 66) + lcrr &= ~LCRR_DBYP; /* DLL Enabled */ + else + lcrr |= LCRR_DBYP; /* DLL Bypass */ + + out_be32 (&lbc->lcrr, lcrr); + asm ("sync;isync;msync"); - lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ - lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ - ecm->eedr = 0xffffffff; /* Clear ecm errors */ - ecm->eeer = 0xffffffff; /* Enable ecm errors */ + out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ + out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ + out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ + out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ + /* Init UPMA for FPGA access */ + out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ + upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); } #if defined(CONFIG_PCI) @@ -197,9 +212,14 @@ void pci_init_board (void) #ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) { -#ifdef CONFIG_PS2MULT - ps2mult_early_init(); -#endif /* CONFIG_PS2MULT */ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + + /* set and reset the GPIO pin 2 which will reset the W83782G chip */ + out_8((unsigned char*)&gur->gpoutdr, 0x3F ); + out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */ + udelay(200); + out_8( (unsigned char*)&gur->gpoutdr, 0x1F ); + return (0); } #endif /* CONFIG_BOARD_EARLY_INIT_R */ @@ -208,31 +228,27 @@ int board_early_init_r (void) void ft_board_setup(void *blob, bd_t *bd) { - u32 val[4]; - int rc; + u32 val[12]; + int rc, i = 0; ft_cpu_setup(blob, bd); - /* Fixup NOR mapping */ - val[0] = 0; /* chip select number */ - val[1] = 0; /* always 0 */ - val[2] = gd->bd->bi_flashstart; - val[3] = gd->bd->bi_flashsize; + /* Fixup NOR FLASH mapping */ + val[i++] = 0; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = gd->bd->bi_flashstart; + val[i++] = gd->bd->bi_flashsize; - rc = fdt_find_and_setprop(blob, "/localbus", "ranges", - val, sizeof(val), 1); - if (rc) - printf("Unable to update property NOR mapping, err=%s\n", - fdt_strerror(rc)); + /* Fixup FPGA mapping */ + val[i++] = 3; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = CFG_FPGA_BASE; + val[i++] = CFG_FPGA_SIZE; -#if defined (CFG_FPGA_BASE) - memset(val, 0, sizeof(val)); - val[0] = CFG_FPGA_BASE; - rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg", - val, sizeof(val), 1); + rc = fdt_find_and_setprop(blob, "/localbus", "ranges", + val, i * sizeof(u32), 1); if (rc) - printf("Unable to update property \"fpga\", err=%s\n", + printf("Unable to update localbus ranges, err=%s\n", fdt_strerror(rc)); -#endif } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h index ea64a59..ed8f887 100644 --- a/board/socrates/upm_table.h +++ b/board/socrates/upm_table.h @@ -34,22 +34,22 @@ /* UPM Table Configuration Code for FPGA access */ static const unsigned int UPMTableA[] = { - 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, /* Words 0 to 3 */ - 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, /* Words 4 to 7 */ - 0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, /* Words 8 to 11 */ - 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, /* Words 12 to 15 */ - 0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, /* Words 16 to 19 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */ - 0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, /* Words 24 to 27 */ - 0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, /* Words 28 to 31 */ - 0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 32 to 35 */ - 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 36 to 39 */ - 0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */ - 0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */ + 0x00fcec00, 0x00fcec00, 0x00fcec00, 0x00fcec00, /* Words 0 to 3 */ + 0x00fcec00, 0x00fcfc00, 0x00fcfc00, 0x00fcec05, /* Words 4 to 7 */ + 0x00fcec00, 0x00fcec00, 0x00fcec04, 0x00fcec04, /* Words 8 to 11 */ + 0x00fcec04, 0x00fcec04, 0x00fcec04, 0x00fcec04, /* Words 12 to 15 */ + 0x00fcec04, 0x00fcec04, 0x0fffec00, 0xffffec00, /* Words 16 to 19 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 20 to 23 */ + 0x00ffec00, 0x00ffec00, 0x00f3ec00, 0x0fffec00, /* Words 24 to 27 */ + 0x0ffffc04, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 28 to 31 */ + 0x00ffec00, 0x00ffec00, 0x00f3ec04, 0x00f3ec04, /* Words 32 to 35 */ + 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, /* Words 36 to 39 */ + 0x00f3ec04, 0x00f3ec04, 0x0fffec00, 0xffffec00, /* Words 40 to 43 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 44 to 47 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 48 to 51 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 52 to 55 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 56 to 59 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01 /* Words 60 to 63 */ }; #endif diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 5cc4213..197ed78 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -45,6 +45,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ @@ -141,13 +142,12 @@ #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ #define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */ -#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */ +#define CFG_OR0_PRELIM 0xfe000030 /* 32MB Flash */ #define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */ -#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */ +#define CFG_OR1_PRELIM 0xfe000030 /* 32MB Flash */ #define CFG_FLASH_CFI /* flash is CFI compat. */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 256 /* sectors per device */ @@ -157,7 +157,7 @@ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ @@ -171,8 +171,20 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ +#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ + +/* FPGA and NAND */ +#define CFG_FPGA_BASE 0xc0000000 +#define CFG_FPGA_SIZE 0x00100000 /* 1 MB */ +#define CFG_HMI_BASE 0xc0010000 +#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ +#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ + +#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_CMD_NAND /* Serial Port */ @@ -204,11 +216,14 @@ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 102124 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C2_OFFSET 0x3100 + /* I2C RTC */ #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ #define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ @@ -302,18 +317,18 @@ #define CONFIG_CMD_DTT #undef CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C +#define CONFIG_CMD_SDRAM #define CONFIG_CMD_MII #define CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB - +#define CONFIG_CMD_EXT2 /* EXT2 Support */ #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif - #undef CONFIG_WATCHDOG /* watchdog disabled */ /* @@ -357,50 +372,69 @@ #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Welcome on the ABB Socrates Board;" \ "echo" #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootfile=$hostname/uImage\0" \ "netdev=eth0\0" \ "consdev=ttyS0\0" \ - "hostname=socrates\0" \ + "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ + "bootfile=/home/tftp/syscon3/uImage\0" \ + "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ + "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ + "uboot_addr=FFFA0000\0" \ + "kernel_addr=FE000000\0" \ + "fdt_addr=FE1E0000\0" \ + "ramdisk_addr=FE200000\0" \ + "fdt_addr_r=B00000\0" \ + "kernel_addr_r=200000\0" \ + "ramdisk_addr_r=400000\0" \ + "rootpath=/opt/eldk/ppc_85xxDP\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addcons=setenv bootargs $bootargs " \ + "console=$consdev,$baudrate\0" \ "addip=setenv bootargs $bootargs " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ ":$hostname:$netdev:off panic=1\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "flash_self=run ramargs addip addcons;" \ + "boot_nor=run ramargs addcons;" \ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ "tftp ${fdt_addr_r} ${fdt_file}; " \ "run nfsargs addip addcons;" \ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "fdt_file=$hostname/socrates.dtb\0" \ - "fdt_addr_r=B00000\0" \ - "fdt_addr=FC1E0000\0" \ - "rootpath=/opt/eldk/ppc_85xxDP\0" \ - "kernel_addr=FC000000\0" \ - "kernel_addr_r=200000\0" \ - "ramdisk_addr=FC200000\0" \ - "ramdisk_addr_r=400000\0" \ - "load=tftp 100000 $hostname/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ + "update_uboot=tftp 100000 ${uboot_file};" \ + "protect off fffa0000 ffffffff;" \ + "era fffa0000 ffffffff;" \ + "cp.b 100000 fffa0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "update_kernel=tftp 100000 ${bootfile};" \ + "era fe000000 fe1dffff;" \ + "cp.b 100000 fe000000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ + "update_fdt=tftp 100000 ${fdt_file};" \ + "era fe1e0000 fe1fffff;" \ + "cp.b 100000 fe1e0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "update_initrd=tftp 100000 ${initrd_file};" \ + "era fe200000 fe9fffff;" \ + "cp.b 100000 fe200000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "clean_data=era fea00000 fff5ffff\0" \ + "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ + "load_usb=usb start;" \ + "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ + "boot_usb=run load_usb usbargs addcons;" \ + "bootm ${kernel_addr_r} - ${fdt_addr};" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" +#define CONFIG_BOOTCOMMAND "run boot_nor" /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -417,14 +451,4 @@ #define CONFIG_DOS_PARTITION 1 #define CONFIG_USB_STORAGE 1 -/* FPGA and NAND */ -#define CFG_FPGA_BASE 0xc0000000 -#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ -#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ - -#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_CMD_NAND - #endif /* __CONFIG_H */ -- cgit v0.10.2 From 36241ca29d4804a1006fb3f26069effda5202581 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Fri, 15 Aug 2008 15:42:13 +0200 Subject: 85xx: socrates: Enable Lime support. This patch adds Lime GDC support together with support for the PWM backlight control through the w83782d chip. The reset pin of the latter is attached to GPIO, so we need to reset it in early_board_init_r. Signed-off-by: Anatolij Gustschin diff --git a/board/socrates/law.c b/board/socrates/law.c index 35c4a90..89b446f 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -36,6 +36,7 @@ * 0x0000_0000 0x2fff_ffff DDR 512M * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xc000_0000 0xc00f_ffff FPGA 1M + * 0xc800_0000 0xcbff_ffff LIME 64M * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xfc00_0000 0xffff_ffff FLASH 64M @@ -48,11 +49,12 @@ struct law_entry law_table[] = { SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), #if defined(CFG_FPGA_BASE) SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC), #endif + SET_LAW(CFG_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 63694a7..73a2d9d 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -173,6 +173,12 @@ void local_bus_init (void) /* Init UPMA for FPGA access */ out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); + + if (getenv("lime")) { + /* Init UPMB for Lime controller access */ + out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */ + upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int)); + } } #if defined(CONFIG_PCI) @@ -239,6 +245,14 @@ ft_board_setup(void *blob, bd_t *bd) val[i++] = gd->bd->bi_flashstart; val[i++] = gd->bd->bi_flashsize; + if (getenv("lime")) { + /* Fixup LIME mapping */ + val[i++] = 2; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = CFG_LIME_BASE; + val[i++] = CFG_LIME_SIZE; + } + /* Fixup FPGA mapping */ val[i++] = 3; /* chip select number */ val[i++] = 0; /* always 0 */ @@ -252,3 +266,187 @@ ft_board_setup(void *blob, bd_t *bd) fdt_strerror(rc)); } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#include +#include +#include + +#define CFG_LIME_SRST ((CFG_LIME_BASE) + 0x01FC002C) +#define CFG_LIME_CCF ((CFG_LIME_BASE) + 0x01FC0038) +#define CFG_LIME_MMR ((CFG_LIME_BASE) + 0x01FCFFFC) +/* Lime clock frequency */ +#define CFG_LIME_CLK_100MHZ 0x00000 +#define CFG_LIME_CLK_133MHZ 0x10000 +/* SDRAM parameter */ +#define CFG_LIME_MMR_VALUE 0x4157BA63 + +#define DISPLAY_WIDTH 800 +#define DISPLAY_HEIGHT 480 +#define DEFAULT_BRIGHTNESS 25 +#define BACKLIGHT_ENABLE (1 << 31) + +extern GraphicDevice mb862xx; + +static const gdc_regs init_regs [] = +{ + {0x0100, 0x00010f00}, + {0x0020, 0x801901df}, + {0x0024, 0x00000000}, + {0x0028, 0x00000000}, + {0x002c, 0x00000000}, + {0x0110, 0x00000000}, + {0x0114, 0x00000000}, + {0x0118, 0x01df0320}, + {0x0004, 0x041f0000}, + {0x0008, 0x031f031f}, + {0x000c, 0x017f0349}, + {0x0010, 0x020c0000}, + {0x0014, 0x01df01e9}, + {0x0018, 0x00000000}, + {0x001c, 0x01e00320}, + {0x0100, 0x80010f00}, + {0x0, 0x0} +}; + +const gdc_regs *board_get_regs (void) +{ + return init_regs; +} + +/* Returns Lime base address */ +unsigned int board_video_init (void) +{ + + if (!getenv("lime")) + return 0; + + /* + * Reset Lime controller + */ + out_be32((void *)CFG_LIME_SRST, 0x1); + udelay(200); + + /* Set Lime clock to 133MHz */ + out_be32((void *)CFG_LIME_CCF, CFG_LIME_CLK_133MHZ); + /* Delay required */ + udelay(300); + /* Set memory parameters */ + out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); + + mb862xx.winSizeX = DISPLAY_WIDTH; + mb862xx.winSizeY = DISPLAY_HEIGHT; + mb862xx.gdfIndex = GDF_15BIT_555RGB; + mb862xx.gdfBytesPP = 2; + + return CFG_LIME_BASE; +} + +#define W83782D_REG_CFG 0x40 +#define W83782D_REG_BANK_SEL 0x4e +#define W83782D_REG_ADCCLK 0x4b +#define W83782D_REG_BEEP_CTRL 0x4d +#define W83782D_REG_BEEP_CTRL2 0x57 +#define W83782D_REG_PWMOUT1 0x5b +#define W83782D_REG_VBAT 0x5d + +static int w83782d_hwmon_init(void) +{ + u8 buf; + + if (i2c_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) + return -1; + + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); + + buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, + buf | 0x80); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); + + buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, + (buf & 0xf4) | 0x01); + return 0; +} + +static void board_backlight_brightness(int br) +{ + u32 reg; + u8 buf; + u8 old_buf; + + /* Select bank 0 */ + if (i2c_read(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) + goto err; + else + buf = old_buf & 0xf8; + + if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) + goto err; + + if (br > 0) { + /* PWMOUT1 duty cycle ctrl */ + buf = 255 / (100 / br); + if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) + goto err; + + /* LEDs on */ + reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c)); + if (!(reg & BACKLIGHT_ENABLE)); + out_be32((void *)(CFG_FPGA_BASE + 0x0c), + reg | BACKLIGHT_ENABLE); + } else { + buf = 0; + if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) + goto err; + + /* LEDs off */ + reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c)); + reg &= ~BACKLIGHT_ENABLE; + out_be32((void *)(CFG_FPGA_BASE + 0x0c), reg); + } + /* Restore previous bank setting */ + if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) + goto err; + + return; +err: + printf("W83782G I2C access failed\n"); +} + +void board_backlight_switch (int flag) +{ + char * param; + int rc; + + if (w83782d_hwmon_init()) + printf ("hwmon IC init failed\n"); + + if (flag) { + param = getenv("brightness"); + rc = param ? simple_strtol(param, NULL, 10) : -1; + if (rc < 0) + rc = DEFAULT_BRIGHTNESS; + } else { + rc = 0; + } + board_backlight_brightness(rc); +} + +#if defined(CONFIG_CONSOLE_EXTRA_INFO) +/* + * Return text to be printed besides the logo. + */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { + strcpy (info, " Board: Socrates"); + } else { + info [0] = '\0'; + } +} +#endif diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index aea99ad..d255cea 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* - * TLB 0: 64M Non-cacheable, guarded + * TLB 1: 64M Non-cacheable, guarded * 0xfc000000 64M FLASH * Out of reset this entry is only 4K. */ @@ -81,6 +81,17 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* + * TLB 5: 64M Non-cacheable, guarded + * 0xc8000000 16M LIME GDC framebuffer + * 0xc9fc0000 256K LIME GDC MMIO + * (0xcbfc0000 256K LIME GDC MMIO) + * MMIO is relocatable and could be at 0xcbfc0000 + */ + SET_TLB_ENTRY(1, CFG_LIME_BASE, CFG_LIME_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* * TLB 6: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h index ed8f887..2a89c96 100644 --- a/board/socrates/upm_table.h +++ b/board/socrates/upm_table.h @@ -52,4 +52,24 @@ static const unsigned int UPMTableA[] = 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01 /* Words 60 to 63 */ }; +/* LIME UPM B Table Configuration Code */ +static unsigned int UPMTableB[] = +{ + 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ + 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffffc01, /* Words 4 to 7 */ + 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 8 to 11 */ + 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffcfc04, /* Words 12 to 15 */ + 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, /* Words 16 to 19 */ + 0x0ffcfc04, 0x0ffcfc04, 0x0ffffc00, 0xfffffc01, /* Words 20 to 23 */ + 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ + 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x0ffffc01, /* Words 28 to 31 */ + 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 32 to 35 */ + 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x00fffc04, /* Words 36 to 39 */ + 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x00fffc04, /* Words 40 to 43 */ + 0x00fffc04, 0x00fffc04, 0x0ffffc00, 0xfffffc01, /* Words 44 to 47 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */ +}; #endif diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index 6c14b0d..d47cb03 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -357,7 +357,8 @@ void *video_hw_init (void) board_disp_init(); #endif -#if defined(CONFIG_LWMON5) && !(CONFIG_POST & CFG_POST_SYSMON) +#if (defined(CONFIG_LWMON5) || \ + defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CFG_POST_SYSMON) /* Lamp on */ board_backlight_switch (1); #endif diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 197ed78..a981a8f 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -186,6 +186,26 @@ #define NAND_MAX_CHIPS 1 #define CONFIG_CMD_NAND +/* LIME GDC */ +#define CFG_LIME_BASE 0xc8000000 +#define CFG_LIME_SIZE 0x04000000 /* 64 MB */ +#define CFG_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ +#define CFG_OR2_PRELIM 0xfc000000 /* 64 MB */ + +#define CONFIG_VIDEO +#define CONFIG_VIDEO_MB862xx +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO +#define VIDEO_FB_16BPP_PIXEL_SWAP +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CFG_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_GZIP +#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ + /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -228,6 +248,9 @@ #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ #define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ +/* I2C W83782G HW-Monitoring IC */ +#define CFG_I2C_W83782G_ADDR 0x28 /* W83782G address */ + /* I2C temp sensor */ /* Socrates uses Maxim's DS75, which is compatible with LM75 */ #define CONFIG_DTT_LM75 1 @@ -324,6 +347,7 @@ #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB #define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_BMP #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI -- cgit v0.10.2 From 6cc64f9b5f69239c8b1969572b5a3a4aab7de5b9 Mon Sep 17 00:00:00 2001 From: Sergei Poselenov Date: Fri, 15 Aug 2008 15:42:11 +0200 Subject: Removed hardcoded MxMR loop value from upmconfig() for MPC85xx. Signed-off-by: Sergei Poselenov diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 7976cac..67e81c0 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -298,15 +298,14 @@ int dma_xfer(void *dest, uint count, void *src) { #endif /* - * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF) - * are hardcoded as "1"."size" is the number or entries, not a sizeof. + * Configures a UPM. The function requires the respective MxMR to be set + * before calling this function. "size" is the number or entries, not a sizeof. */ void upmconfig (uint upm, uint * table, uint size) { int i, mdr, mad, old_mad = 0; volatile u32 *mxmr; volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - int loopval = 0x00004440; volatile u32 *brp,*orp; volatile u8* dummy = NULL; int upmmask; @@ -334,8 +333,8 @@ void upmconfig (uint upm, uint * table, uint size) i++, brp += 2, orp += 2) { /* Look for a valid BR with selected UPM */ - if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) { - dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT); + if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { + dummy = (volatile u8*)(in_be32(brp) & BR_BA); break; } } @@ -347,7 +346,7 @@ void upmconfig (uint upm, uint * table, uint size) for (i = 0; i < size; i++) { /* 1 */ - out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */ + out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); /* 2 */ out_be32(&lbc->mdr, table[i]); /* 3 */ @@ -356,11 +355,11 @@ void upmconfig (uint upm, uint * table, uint size) *(volatile u8 *)dummy = 0; /* 5 */ do { - mad = in_be32(mxmr) & 0x3f; + mad = in_be32(mxmr) & MxMR_MAD_MSK; } while (mad <= old_mad && !(!mad && i == (size-1))); old_mad = mad; } - out_be32(mxmr, loopval); /* OP_NORMAL */ + out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); } -- cgit v0.10.2 From e0ff3d350d6b7960deb5a881dfc5acf3a63ef676 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 8 Sep 2008 08:51:29 -0500 Subject: 85xx: Ensure timebase is zero on secondary cores The e500um says the timebase is volatile out of reset. To ensure TB sync works we need to make sure its zero. Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 75676b5..ec5e4da 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -37,6 +37,11 @@ __secondary_start_page: li r3,0x201 mtspr SPRN_BUCSR,r3 + /* Ensure TB is 0 */ + li r3,0 + mttbl r3 + mttbu r3 + /* Enable/invalidate the I-Cache */ mfspr r0,SPRN_L1CSR1 ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE) -- cgit v0.10.2 From 5251469943895de4bb9a04d5053352cc22acb7d5 Mon Sep 17 00:00:00 2001 From: Andrew Klossner Date: Thu, 21 Aug 2008 07:12:26 -0700 Subject: Fix printf errors under -DDEBUG Fix printf format-string/arg mismatches under -DDEBUG. These warnings occur with DEBUG defined for a platform using cpu/mpc85xx. Users of other architectures can unearth similar problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right after "CFLAGS += $(call cc-option,-fno-stack-protector)". Signed-off-by: Andrew Klossner Signed-off-by: Andy Fleming diff --git a/common/image.c b/common/image.c index f7e8606..d7fcd1d 100644 --- a/common/image.c +++ b/common/image.c @@ -1563,7 +1563,7 @@ int boot_get_fdt (int flag, int argc, char *argv[], bootm_headers_t *images, *of_flat_tree = fdt_blob; *of_size = be32_to_cpu (fdt_totalsize (fdt_blob)); debug (" of_flat_tree at 0x%08lx size 0x%08lx\n", - *of_flat_tree, *of_size); + (ulong)*of_flat_tree, *of_size); return 0; diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index 06d4d8b..d702ca6 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -48,29 +48,29 @@ int interrupt_init_cpu(unsigned long *decrementer_count) #ifdef CONFIG_INTERRUPTS pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ - debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); + debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1); pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ - debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2); + debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2); pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ - debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3); + debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3); #ifdef CONFIG_PCI1 pic->iivpr8 = 0x810008; /* enable pci1 interrupts */ - debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8); + debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8); #endif #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) pic->iivpr9 = 0x810009; /* enable pci1 interrupts */ - debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9); + debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9); #endif #ifdef CONFIG_PCIE1 pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */ - debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10); + debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10); #endif #ifdef CONFIG_PCIE3 pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */ - debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11); + debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11); #endif pic->ctpr=0; /* 40080 clear current task priority register */ diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 03ea2d0..a74321d 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -516,7 +516,7 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect, retval = (flash_read16(addr) == cword.w); break; case FLASH_CFI_32BIT: - debug ("is= %8.8lx %8.8lx\n", flash_read32(addr), cword.l); + debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l); retval = (flash_read32(addr) == cword.l); break; case FLASH_CFI_64BIT: -- cgit v0.10.2