From 8eeb19be753da220819b0b3a95a746508455d149 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:55:30 +0000 Subject: mx31: Move EHCI definitions to ehci-fsl.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 8fd3d08..01a849d 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -896,32 +896,6 @@ struct esdc_regs { #define MX31_AIPS1_BASE_ADDR 0x43f00000 #define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) -/* USB portsc */ -/* values for portsc field */ -#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) -#define MXC_EHCI_FORCE_FS (1 << 24) -#define MXC_EHCI_UTMI_8BIT (0 << 28) -#define MXC_EHCI_UTMI_16BIT (1 << 28) -#define MXC_EHCI_SERIAL (1 << 29) -#define MXC_EHCI_MODE_UTMI (0 << 30) -#define MXC_EHCI_MODE_PHILIPS (1 << 30) -#define MXC_EHCI_MODE_ULPI (2 << 30) -#define MXC_EHCI_MODE_SERIAL (3 << 30) - -/* values for flags field */ -#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) -#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) -#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) -#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) -#define MXC_EHCI_INTERFACE_MASK (0xf) - -#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) -#define MXC_EHCI_TTL_ENABLED (1 << 6) - -#define MXC_EHCI_INTERNAL_PHY (1 << 7) -#define MXC_EHCI_IPPUE_DOWN (1 << 8) -#define MXC_EHCI_IPPUE_UP (1 << 9) - /* * CSPI register definitions */ diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index 2869302..4dee5b0 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -246,9 +246,31 @@ struct usb_ehci { /* * For MXC SOCs */ + +/* values for portsc field */ +#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) +#define MXC_EHCI_FORCE_FS (1 << 24) +#define MXC_EHCI_UTMI_8BIT (0 << 28) +#define MXC_EHCI_UTMI_16BIT (1 << 28) +#define MXC_EHCI_SERIAL (1 << 29) +#define MXC_EHCI_MODE_UTMI (0 << 30) +#define MXC_EHCI_MODE_PHILIPS (1 << 30) +#define MXC_EHCI_MODE_ULPI (2 << 30) +#define MXC_EHCI_MODE_SERIAL (3 << 30) + +/* values for flags field */ +#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) +#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) +#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) +#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) +#define MXC_EHCI_INTERFACE_MASK (0xf) + #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) #define MXC_EHCI_TTL_ENABLED (1 << 6) + #define MXC_EHCI_INTERNAL_PHY (1 << 7) +#define MXC_EHCI_IPPUE_DOWN (1 << 8) +#define MXC_EHCI_IPPUE_UP (1 << 9) /* Board-specific initialization */ int board_ehci_hcd_init(int port); -- cgit v0.10.2 From 164738e9403c3a6a84eca7a2c2b9b78a62a3f57c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:55:57 +0000 Subject: ehci-mxc: Clean up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clean up ehci-mxc: - Remove useless #if's. - Fix identation. - Issue a #error if used with an unsupported platform. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index a38bc9c..e21f2c5 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -28,14 +28,11 @@ #define USBCTRL_OTGBASE_OFFSET 0x600 -#ifdef CONFIG_MX25 #define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) #define MX25_USB_CTRL_HSTD_BIT (1<<5) #define MX25_USB_CTRL_USBTE_BIT (1<<4) #define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) -#endif -#ifdef CONFIG_MX31 #define MX31_OTG_SIC_SHIFT 29 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) #define MX31_OTG_PM_BIT (1 << 24) @@ -49,59 +46,56 @@ #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) #define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_DT_BIT (1 << 4) -#endif static int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; -#ifdef CONFIG_MX25 +#if defined(CONFIG_MX25) v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT | MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT; -#endif +#elif defined(CONFIG_MX31) + v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); -#ifdef CONFIG_MX31 - v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX31_OTG_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | - MX31_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX31_H1_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | - MX31_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) - << MX31_H2_SIC_SHIFT; - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H2_DT_BIT; - - break; - default: - return -EINVAL; - } -#endif + switch (port) { + case 0: /* OTG port */ + v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_OTG_PM_BIT; + + break; + case 1: /* H1 port */ + v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX31_H1_DT_BIT; + + break; + case 2: /* H2 port */ + v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_H2_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX31_H2_DT_BIT; + + break; + default: + return -EINVAL; + } +#else +#error MXC EHCI USB driver not supported on this platform +#endif writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); + return 0; } -- cgit v0.10.2 From bdc5202068ec778ae2eecb818559ce7c61057109 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:56:15 +0000 Subject: ehci-mx5: Clean up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clean up ehci-mx5: - Fix column alignments. - Fix comments. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 9a2c295..46973b0 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -29,9 +29,9 @@ #define MX5_USBOTHER_REGS_OFFSET 0x800 -#define MXC_OTG_OFFSET 0 -#define MXC_H1_OFFSET 0x200 -#define MXC_H2_OFFSET 0x400 +#define MXC_OTG_OFFSET 0 +#define MXC_H1_OFFSET 0x200 +#define MXC_H2_OFFSET 0x400 #define MXC_USBCTRL_OFFSET 0 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 @@ -40,23 +40,30 @@ #define MXC_USBH2CTRL_OFFSET 0x14 /* USB_CTRL */ -#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ -#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ -#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ -#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ -#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ +/* OTG wakeup intr enable */ +#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) +/* OTG power mask */ +#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) +/* Host1 ULPI interrupt enable */ +#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) +/* HOST1 wakeup intr enable */ +#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) +/* HOST1 power mask */ +#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* USB_PHY_CTRL_FUNC */ -#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ -#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ +/* OTG Disable Overcurrent Event */ +#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) +/* UH1 Disable Overcurrent Event */ +#define MXC_H1_OC_DIS_BIT (1 << 5) /* USBH2CTRL */ -#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) -#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) -#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) +#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) +#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) +#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) /* USB_CTRL_1 */ -#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) +#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) /* USB pin configuration */ #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ @@ -160,7 +167,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; - case 1: /* Host 1 Host ULPI */ + case 1: /* Host 1 ULPI */ #ifdef CONFIG_MX51 /* The clock for the USBH1 ULPI port will come externally from the PHY. */ @@ -171,9 +178,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags) v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */ + v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */ else - v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */ + v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */ __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); @@ -187,9 +194,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags) case 2: /* Host 2 ULPI */ v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */ + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */ else - v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */ + v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); break; -- cgit v0.10.2 From 7d42432d38af11f9d05398c3b6d29a54ab3322c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:56:30 +0000 Subject: ehci-mx5: Fix OC_DIS usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like MXC_H1_OC_DIS_BIT, not the opposite. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 46973b0..72cde1a 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -151,11 +151,11 @@ int mxc_set_usbcontrol(int port, unsigned int flags) v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); if (flags & MXC_EHCI_POWER_PINS_ENABLED) - /* OC/USBPWR is not used */ - v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; - else /* OC/USBPWR is used */ v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; + else + /* OC/USBPWR is not used */ + v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); -- cgit v0.10.2 From 394c00dcfc9751030cbd9eb87ab2492d234f9ace Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:56:44 +0000 Subject: ehci-mx5: Fix OPM usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like MXC_H1_UCTRL_H1PM_BIT and MXC_H2_UCTRL_H2PM_BIT, not the opposite. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 72cde1a..8c1b70a 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -161,9 +161,9 @@ int mxc_set_usbcontrol(int port, unsigned int flags) v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v |= MXC_OTG_UCTRL_OPM_BIT; - else v &= ~MXC_OTG_UCTRL_OPM_BIT; + else + v |= MXC_OTG_UCTRL_OPM_BIT; __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; -- cgit v0.10.2 From 661052f47622ce234e592622020f69b61f04c649 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:56:59 +0000 Subject: ehci-mx5: Fix *PM usage for i.MX53 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MXC_*_UCTRL_*PM_BIT bits are available only on i.MX51. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 8c1b70a..4f4b98a 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -160,10 +160,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags) MXC_USB_PHY_CTR_FUNC_OFFSET); v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); +#ifdef CONFIG_MX51 if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_OTG_UCTRL_OPM_BIT; else v |= MXC_OTG_UCTRL_OPM_BIT; +#endif __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; @@ -177,10 +179,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags) #endif v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); +#ifdef CONFIG_MX51 if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */ else v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */ +#endif __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); @@ -193,11 +197,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags) break; case 2: /* Host 2 ULPI */ v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); +#ifdef CONFIG_MX51 if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */ else v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ - +#endif __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); break; } -- cgit v0.10.2 From 2cfe0b8f132a04b2f1075355f062a4d05c95f096 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:57:14 +0000 Subject: ehci-mx5: Add missing OC_DIS for i.MX53 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 4f4b98a..6f7fe80 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -32,12 +32,14 @@ #define MXC_OTG_OFFSET 0 #define MXC_H1_OFFSET 0x200 #define MXC_H2_OFFSET 0x400 +#define MXC_H3_OFFSET 0x600 #define MXC_USBCTRL_OFFSET 0 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc #define MXC_USB_CTRL_1_OFFSET 0x10 #define MXC_USBH2CTRL_OFFSET 0x14 +#define MXC_USBH3CTRL_OFFSET 0x18 /* USB_CTRL */ /* OTG wakeup intr enable */ @@ -58,10 +60,16 @@ #define MXC_H1_OC_DIS_BIT (1 << 5) /* USBH2CTRL */ +#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) +/* USBH3CTRL */ +#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) +#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) +#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) + /* USB_CTRL_1 */ #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) @@ -203,8 +211,24 @@ int mxc_set_usbcontrol(int port, unsigned int flags) else v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ #endif +#ifdef CONFIG_MX53 + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */ + else + v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */ +#endif __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); break; +#ifdef CONFIG_MX53 + case 3: /* Host 3 ULPI */ + v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */ + else + v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */ + __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); + break; +#endif } return ret; -- cgit v0.10.2 From 31ac2d0c6af61b16ab8c3c6cefe61f53a06219d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:57:27 +0000 Subject: ehci-mxc: Make EHCI power/oc polarities configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make EHCI power and overcurrent polarities configurable. If not set, these new configurartions keep the default register values so that existing board files do not have to be changed. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 6f7fe80..7e60c3c 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -46,29 +46,43 @@ #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG power mask */ #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) +/* OTG power pin polarity */ +#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* Host1 ULPI interrupt enable */ #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* HOST1 wakeup intr enable */ #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 power mask */ #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) +/* HOST1 power pin polarity */ +#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* USB_PHY_CTRL_FUNC */ +/* OTG Polarity of Overcurrent */ +#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Disable Overcurrent Event */ #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) +/* UH1 Polarity of Overcurrent */ +#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Disable Overcurrent Event */ #define MXC_H1_OC_DIS_BIT (1 << 5) +/* OTG Power Pin Polarity */ +#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* USBH2CTRL */ +#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31) #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) +#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4) /* USBH3CTRL */ +#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31) #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) +#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4) /* USB_CTRL_1 */ #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) @@ -158,12 +172,22 @@ int mxc_set_usbcontrol(int port, unsigned int flags) if (flags & MXC_EHCI_INTERNAL_PHY) { v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) + v |= MXC_OTG_PHYCTRL_OC_POL_BIT; + else + v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) /* OC/USBPWR is used */ v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; else /* OC/USBPWR is not used */ v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; +#ifdef CONFIG_MX51 + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; + else + v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; +#endif __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); @@ -174,6 +198,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags) else v |= MXC_OTG_UCTRL_OPM_BIT; #endif +#ifdef CONFIG_MX53 + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_OTG_UCTRL_O_PWR_POL_BIT; + else + v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT; +#endif __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; @@ -193,9 +223,19 @@ int mxc_set_usbcontrol(int port, unsigned int flags) else v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */ #endif +#ifdef CONFIG_MX53 + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_H1_UCTRL_H1_PWR_POL_BIT; + else + v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT; +#endif __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) + v |= MXC_H1_OC_POL_BIT; + else + v &= ~MXC_H1_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ else @@ -212,20 +252,36 @@ int mxc_set_usbcontrol(int port, unsigned int flags) v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ #endif #ifdef CONFIG_MX53 + if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) + v |= MXC_H2_UCTRL_H2_OC_POL_BIT; + else + v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */ else v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */ + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_H2_UCTRL_H2_PWR_POL_BIT; + else + v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT; #endif __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); break; #ifdef CONFIG_MX53 case 3: /* Host 3 ULPI */ v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); + if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) + v |= MXC_H3_UCTRL_H3_OC_POL_BIT; + else + v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */ else v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */ + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_H3_UCTRL_H3_PWR_POL_BIT; + else + v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT; __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); break; #endif diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index 4dee5b0..a1438d6 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -266,11 +266,13 @@ struct usb_ehci { #define MXC_EHCI_INTERFACE_MASK (0xf) #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) -#define MXC_EHCI_TTL_ENABLED (1 << 6) +#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) +#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) +#define MXC_EHCI_TTL_ENABLED (1 << 8) -#define MXC_EHCI_INTERNAL_PHY (1 << 7) -#define MXC_EHCI_IPPUE_DOWN (1 << 8) -#define MXC_EHCI_IPPUE_UP (1 << 9) +#define MXC_EHCI_INTERNAL_PHY (1 << 9) +#define MXC_EHCI_IPPUE_DOWN (1 << 10) +#define MXC_EHCI_IPPUE_UP (1 << 11) /* Board-specific initialization */ int board_ehci_hcd_init(int port); -- cgit v0.10.2 From 9fa3d093d626b25c64c695e29d381dd2ae7bf8cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:57:48 +0000 Subject: ehci-mxc: Make i.MX25 EHCI configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use EHCI MXC configuration options for i.MX25. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic Cc: Matthias Weisser diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index e21f2c5..846aa3b 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -28,10 +28,21 @@ #define USBCTRL_OTGBASE_OFFSET 0x600 -#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) -#define MX25_USB_CTRL_HSTD_BIT (1<<5) -#define MX25_USB_CTRL_USBTE_BIT (1<<4) -#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) +#define MX25_OTG_SIC_SHIFT 29 +#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) +#define MX25_OTG_PM_BIT (1 << 24) +#define MX25_OTG_PP_BIT (1 << 11) +#define MX25_OTG_OCPOL_BIT (1 << 3) + +#define MX25_H1_SIC_SHIFT 21 +#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) +#define MX25_H1_PP_BIT (1 << 18) +#define MX25_H1_PM_BIT (1 << 8) +#define MX25_H1_IPPUE_UP_BIT (1 << 7) +#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) +#define MX25_H1_TLL_BIT (1 << 5) +#define MX25_H1_USBTE_BIT (1 << 4) +#define MX25_H1_OCPOL_BIT (1 << 2) #define MX31_OTG_SIC_SHIFT 29 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) @@ -51,12 +62,57 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; -#if defined(CONFIG_MX25) - v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT | - MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT; -#elif defined(CONFIG_MX31) v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); +#if defined(CONFIG_MX25) + switch (port) { + case 0: /* OTG port */ + v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | + MX25_OTG_OCPOL_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX25_OTG_PM_BIT; + + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MX25_OTG_PP_BIT; + + if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) + v |= MX25_OTG_OCPOL_BIT; + + break; + case 1: /* H1 port */ + v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | + MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | + MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | + MX25_H1_IPPUE_UP_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX25_H1_PM_BIT; + + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MX25_H1_PP_BIT; + + if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) + v |= MX25_H1_OCPOL_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX25_H1_TLL_BIT; + + if (flags & MXC_EHCI_INTERNAL_PHY) + v |= MX25_H1_USBTE_BIT; + + if (flags & MXC_EHCI_IPPUE_DOWN) + v |= MX25_H1_IPPUE_DOWN_BIT; + if (flags & MXC_EHCI_IPPUE_UP) + v |= MX25_H1_IPPUE_UP_BIT; + + break; + default: + return -EINVAL; + } +#elif defined(CONFIG_MX31) switch (port) { case 0: /* OTG port */ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 447683a..e9216d9 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -109,9 +109,9 @@ #define CONFIG_USB_EHCI /* Enable EHCI USB support */ #define CONFIG_USB_EHCI_MXC #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORT 2 -#define CONFIG_MXC_USB_PORTSC 0xC0000000 -#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL +#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION -- cgit v0.10.2 From 34d33b671a03da1c115d83a603fb36da0360b20a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:57:59 +0000 Subject: ehci-mxc: Define host offsets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at SoC level. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 738d411..5f4b543 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -241,6 +241,7 @@ struct aips_regs { #define IMX_RTIC_BASE (0x53FEC000) #define IMX_IIM_BASE (0x53FF0000) #define IMX_USB_BASE (0x53FF4000) +#define IMX_USB_PORT_OFFSET 0x200 #define IMX_CSI_BASE (0x53FF8000) #define IMX_DRYICE_BASE (0x53FFC000) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 01a849d..ae3658b 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -895,6 +895,7 @@ struct esdc_regs { #define MX31_AIPS1_BASE_ADDR 0x43f00000 #define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) +#define IMX_USB_PORT_OFFSET 0x200 /* * CSPI register definitions diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 846aa3b..6260a8c 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -169,7 +169,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) udelay(80); ehci = (struct usb_ehci *)(IMX_USB_BASE + - (0x200 * CONFIG_MXC_USB_PORT)); + IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT); *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); -- cgit v0.10.2 From 71a5c55bfa776b29d11b85e80945b89af06e6546 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:58:12 +0000 Subject: ehci-mxc: Add support for i.MX35 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index 7b6475a..18c6816 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -84,6 +84,8 @@ #define PWM_BASE_ADDR 0x53FE0000 #define RTIC_BASE_ADDR 0x53FEC000 #define IIM_BASE_ADDR 0x53FF0000 +#define IMX_USB_BASE 0x53FF4000 +#define IMX_USB_PORT_OFFSET 0x400 #define IMX_CCM_BASE CCM_BASE_ADDR diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 6260a8c..7c5f71c 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -58,6 +58,22 @@ #define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_DT_BIT (1 << 4) +#define MX35_OTG_SIC_SHIFT 29 +#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) +#define MX35_OTG_PM_BIT (1 << 24) +#define MX35_OTG_PP_BIT (1 << 11) +#define MX35_OTG_OCPOL_BIT (1 << 3) + +#define MX35_H1_SIC_SHIFT 21 +#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) +#define MX35_H1_PP_BIT (1 << 18) +#define MX35_H1_PM_BIT (1 << 8) +#define MX35_H1_IPPUE_UP_BIT (1 << 7) +#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) +#define MX35_H1_TLL_BIT (1 << 5) +#define MX35_H1_USBTE_BIT (1 << 4) +#define MX35_H1_OCPOL_BIT (1 << 2) + static int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; @@ -147,6 +163,55 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) default: return -EINVAL; } +#elif defined(CONFIG_MX35) + switch (port) { + case 0: /* OTG port */ + v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | + MX35_OTG_OCPOL_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_OTG_PM_BIT; + + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MX35_OTG_PP_BIT; + + if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) + v |= MX35_OTG_OCPOL_BIT; + + break; + case 1: /* H1 port */ + v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | + MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | + MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | + MX35_H1_IPPUE_UP_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; + + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_H1_PM_BIT; + + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MX35_H1_PP_BIT; + + if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) + v |= MX35_H1_OCPOL_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX35_H1_TLL_BIT; + + if (flags & MXC_EHCI_INTERNAL_PHY) + v |= MX35_H1_USBTE_BIT; + + if (flags & MXC_EHCI_IPPUE_DOWN) + v |= MX35_H1_IPPUE_DOWN_BIT; + + if (flags & MXC_EHCI_IPPUE_UP) + v |= MX35_H1_IPPUE_UP_BIT; + + break; + default: + return -EINVAL; + } #else #error MXC EHCI USB driver not supported on this platform #endif @@ -176,6 +241,10 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) setbits_le32(&ehci->usbmode, CM_HOST); __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); +#ifdef CONFIG_MX35 + /* Workaround for ENGcm11601 */ + __raw_writel(0, &ehci->sbuscfg); +#endif udelay(10000); -- cgit v0.10.2 From 961a762838d55dc9bae8fa7ea57bc3c51a9c7b57 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:58:25 +0000 Subject: mx35pdk: Add support for OTG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for the OTG port on the mx35pdk Personality board. Signed-off-by: Benoît Thébaudeau Tested-by: Stefano Babic Cc: Stefano Babic Cc: Marek Vasut diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S index 75bb958..da8b6f3 100644 --- a/board/freescale/mx35pdk/lowlevel_init.S +++ b/board/freescale/mx35pdk/lowlevel_init.S @@ -94,6 +94,10 @@ orr r1, r1, #0x00000C00 orr r1, r1, #0x00000003 str r1, [r0, #CLKCTL_CGR1] + + ldr r1, [r0, #CLKCTL_CGR2] + orr r1, r1, #0x00C00000 + str r1, [r0, #CLKCTL_CGR2] .endm .macro setup_sdram diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index a12531f..4d8f2f5 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -98,6 +98,26 @@ static void setup_iomux_spi(void) mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); } +static void setup_iomux_usbotg(void) +{ + int in_pad, out_pad; + + /* Set up pins for USBOTG. */ + mxc_request_iomux(MX35_PIN_USBOTG_PWR, + MUX_CONFIG_SION | MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_USBOTG_OC, + MUX_CONFIG_SION | MUX_CONFIG_FUNC); + + in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS | + PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW; + out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE | + PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW; + + mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad); + mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad); +} + static void setup_iomux_fec(void) { int pad; @@ -189,6 +209,7 @@ int board_early_init_f(void) __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); setup_iomux_i2c(); + setup_iomux_usbotg(); setup_iomux_fec(); setup_iomux_spi(); diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index d89db7a..00171a7 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -112,6 +112,8 @@ #define CONFIG_NET_RETRY_COUNT 100 #define CONFIG_CMD_DATE +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION @@ -244,6 +246,18 @@ #define CONFIG_MXC_NAND_HWECC #define CONFIG_SYS_NAND_LARGEPAGE +/* EHCI driver */ +#define CONFIG_USB_EHCI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_MXC +#define CONFIG_MXC_USB_PORT 0 +#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \ + MXC_EHCI_POWER_PINS_ENABLED | \ + MXC_EHCI_OC_PIN_ACTIVE_LOW) +#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI) + /* mmc driver */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -- cgit v0.10.2 From f22e4fae19c05ae66c83b846fee66a1b8fbc5a9b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 13 Nov 2012 09:58:35 +0000 Subject: ehci-mx5/6: Make board_ehci_hcd_init() optional MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A custom board_ehci_hcd_init() may be unneeded, so add a weak default implementation doing nothing. By the way, use simple __weak from linux/compiler.h for board_ehci_hcd_postinit() instead of weak alias with full attribute. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 7e60c3c..adbed5c 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -290,12 +290,14 @@ int mxc_set_usbcontrol(int port, unsigned int flags) return ret; } -void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) +int __weak board_ehci_hcd_init(int port) { + return 0; } -void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) - __attribute((weak, alias("__board_ehci_hcd_postinit"))); +void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) +{ +} int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 9ce25da..1b20e41 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -159,6 +159,11 @@ static void usbh1_oc_config(void) __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET); } +int __weak board_ehci_hcd_init(int port) +{ + return 0; +} + int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct usb_ehci *ehci; -- cgit v0.10.2 From d84f56f48f361df182060f702c20a49c12937504 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 15 Nov 2012 11:23:21 +0000 Subject: mx5: Align SPI CS naming with i.MX53 reference manual Align SPI chip select naming with i.MX53 reference manual. Signed-off-by: Fabio Estevam diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h index 122fbee..3457f6a 100644 --- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h +++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h @@ -802,22 +802,22 @@ typedef enum iomux_input_select { MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, MX53_CSPI_IPP_IND_MISO_SELECT_INPUT, MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT, MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, - MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT, MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT, MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT, MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT, MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT, - MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT, MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, + MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT, MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, - MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT, MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT, MX53_ESAI1_IPP_IND_FST_SELECT_INPUT, MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT, -- cgit v0.10.2 From 081237c1f7e7a177bb2e761ee5678d08c345865d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 15 Nov 2012 11:23:22 +0000 Subject: mx5: Print CSPI clock in 'clock' command Print CSPI clock in 'clock' command. Signed-off-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 1c9223f..76c2c52 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -928,7 +928,9 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); - +#ifdef CONFIG_MXC_SPI + printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); +#endif return 0; } -- cgit v0.10.2 From de5bf02cb1f61de0c65a539cd0083ac8ab07ec50 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 15 Nov 2012 11:23:23 +0000 Subject: spi: mxc_spi: Fix handling of chip select In decode_cs() function the polarity of the chip select must be taken into account. Also, for the case of low active chip select, the CS was activated too early. Signed-off-by: Fabio Estevam diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 13bebe8..b6bad98 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -387,7 +387,7 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) if (cs > 3) { mxcs->gpio = cs >> 8; cs &= 3; - ret = gpio_direction_output(mxcs->gpio, 0); + ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); if (ret) { printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); return -EINVAL; @@ -414,6 +414,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } + mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; + ret = decode_cs(mxcs, cs); if (ret < 0) { free(mxcs); @@ -425,7 +427,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mxcs->slave.bus = bus; mxcs->slave.cs = cs; mxcs->base = spi_bases[bus]; - mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); if (ret) { -- cgit v0.10.2 From 3cea335c3410f71524b50263b8af0e7eb69ebbe4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 15 Nov 2012 11:23:24 +0000 Subject: spi: mxc_spi: Fix spi clock glitch durant reset Measuring the spi clock line on a scope shows a 'glitch' during the reset of the spi. Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes always stable. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index b6bad98..859c43f 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -140,8 +140,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, reg_ctrl = reg_read(®s->ctrl); /* Reset spi */ - reg_write(®s->ctrl, 0); - reg_write(®s->ctrl, (reg_ctrl | 0x1)); + reg_write(®s->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN)); + reg_write(®s->ctrl, (reg_ctrl | MXC_CSPICTRL_EN)); /* * The following computation is taken directly from Freescale's code. -- cgit v0.10.2 From cc446726de6032688227548ef9d4b2eff331df83 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Nov 2012 01:30:10 +0000 Subject: mx6: clock: Only show CSPI clock if CSPI is enabled If a board does not enable CSPI, there is no need to show the CSPI clock frequency as part of the 'clock' command. Reported-by: Dirk Behme Signed-off-by: Fabio Estevam Acked-by: Dirk Behme diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index a01d96f..a50db70 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -404,7 +404,9 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("\n"); printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); +#ifdef CONFIG_MXC_SPI printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); +#endif printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); -- cgit v0.10.2 From ed0a6fcff92ec14947916291a33167188b4218d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Fri, 16 Nov 2012 01:42:49 +0000 Subject: ehci-mxc: Fix host power mask bit for i.MX35 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The correct bit for H1_PM is 16, not 8, which is the DP pull-up impedance selection bit. This issue has been reported by Michael Burkey and fixed by Christoph Fritz on Linux, from which these #define-s had been copied. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Marek Vasut Acked-by: Stefano Babic diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 7c5f71c..f2642a0 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -67,7 +67,7 @@ #define MX35_H1_SIC_SHIFT 21 #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) #define MX35_H1_PP_BIT (1 << 18) -#define MX35_H1_PM_BIT (1 << 8) +#define MX35_H1_PM_BIT (1 << 16) #define MX35_H1_IPPUE_UP_BIT (1 << 7) #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) #define MX35_H1_TLL_BIT (1 << 5) -- cgit v0.10.2 From 2785694381bcd114441c44c63362fb54a251230f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Nov 2012 05:09:03 +0000 Subject: mx28evk: Configure CONFIG_BOOTDELAY to one second One second is enough time for users to react in case they want to stop the booting process. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 2916c71..8b89b25 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -238,7 +238,7 @@ */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 1 #define CONFIG_BOOTFILE "uImage" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v0.10.2 From fbae0d108e4ee726df83130300d0305051d23caf Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Nov 2012 05:09:04 +0000 Subject: mx53loco: Configure CONFIG_BOOTDELAY to one second One second is enough time for users to react in case they want to stop the booting process. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index a62ea78..37f9d69 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -108,7 +108,7 @@ #undef CONFIG_CMD_IMLS -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 1 #define CONFIG_ETHPRIME "FEC0" -- cgit v0.10.2 From eb141bd36ca33e09eb86cdbc83bbe1b157c19aae Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Nov 2012 05:09:05 +0000 Subject: mx6qsabrelite: Configure CONFIG_BOOTDELAY to one second One second is enough time for users to react in case they want to stop the booting process. Signed-off-by: Fabio Estevam Acked-by: Jason Liu diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 318f857..759275a 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -144,7 +144,7 @@ #undef CONFIG_CMD_IMLS -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 1 #define CONFIG_PREBOOT "" -- cgit v0.10.2 From 072f26b1da7d25626c460f89d5e358e74d29008e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Nov 2012 05:09:06 +0000 Subject: mx6qsabre_common: Configure CONFIG_BOOTDELAY to one second One second is enough time for users to react in case they want to stop the booting process. Signed-off-by: Fabio Estevam Acked-by: Jason Liu diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h index 50f3b01..b8621b8 100644 --- a/include/configs/mx6qsabre_common.h +++ b/include/configs/mx6qsabre_common.h @@ -76,7 +76,7 @@ #define CONFIG_CMD_BOOTZ #undef CONFIG_CMD_IMLS -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 1 #define CONFIG_LOADADDR 0x10800000 #define CONFIG_SYS_TEXT_BASE 0x17800000 -- cgit v0.10.2 From bf5c6fbbf7f58084dc9a89c4bb31f909450f6e00 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Nov 2012 05:09:07 +0000 Subject: mx51evk: Configure CONFIG_BOOTDELAY to one second One second is enough time for users to react in case they want to stop the booting process. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 89feaed..e8c6618 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -149,7 +149,7 @@ #define CONFIG_CMD_DATE -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 1 #define CONFIG_ETHPRIME "FEC0" -- cgit v0.10.2 From d941e6b63e0dd3653b81841f7cf8238cccec8f56 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Nov 2012 05:09:08 +0000 Subject: mx25pdk: Configure CONFIG_BOOTDELAY to one second One second is enough time for users to react in case they want to stop the booting process. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index a4bd8b0..b5338a0 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -130,7 +130,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_NET -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 1 #define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v0.10.2 From 562e6c62b6754d95fd4696a74289a8292f779645 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Nov 2012 05:09:09 +0000 Subject: mx31pdk: Configure CONFIG_BOOTDELAY to one second One second is enough time for users to react in case they want to stop the booting process. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 223b5b0..6572676 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -106,7 +106,7 @@ #define CONFIG_BOARD_LATE_INIT -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ -- cgit v0.10.2 From ec7503bb0ec4c0df199129d0958413fb9d44baf0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Nov 2012 05:09:10 +0000 Subject: mx35pdk: Configure CONFIG_BOOTDELAY to one second One second is enough time for users to react in case they want to stop the booting process. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 00171a7..1c2f599 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -120,7 +120,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 1 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ -- cgit v0.10.2 From fa88ddb75f0abeee123dd1547f4e32ec3155d31f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Fri, 16 Nov 2012 06:46:24 +0000 Subject: ehci-mxc: Fix host power mask bit for i.MX25 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The correct bit for H1_PM is 16, not 8, which is the DP pull-up impedance selection bit. This issue has been reported by Eric Bénard and fixed by Christoph Fritz on Linux, from which these #define-s had been copied. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Marek Vasut diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index f2642a0..8633cab 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -37,7 +37,7 @@ #define MX25_H1_SIC_SHIFT 21 #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) #define MX25_H1_PP_BIT (1 << 18) -#define MX25_H1_PM_BIT (1 << 8) +#define MX25_H1_PM_BIT (1 << 16) #define MX25_H1_IPPUE_UP_BIT (1 << 7) #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) #define MX25_H1_TLL_BIT (1 << 5) -- cgit v0.10.2 From 39e8576164c3bef9d6cb9ad4567c09fc6a87b5fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Mon, 5 Nov 2012 10:07:04 +0000 Subject: mx5: Mark lowlevel_init board-specific code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Matt Sealey Acked-by: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 29ec957..6d9396a9 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -396,7 +396,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ -#if defined(CONFIG_MX51) +#if defined(CONFIG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 diff --git a/doc/README.imx5 b/doc/README.imx5 index f7eab7d..e08941e 100644 --- a/doc/README.imx5 +++ b/doc/README.imx5 @@ -15,3 +15,8 @@ i.MX5x SoCs. mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. + +1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. + This option should be enabled for boards having a SYS_ON_OFF_CTL signal + connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the + reference designs. diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h index ffe771f..a056566 100644 --- a/include/configs/mx51_efikamx.h +++ b/include/configs/mx51_efikamx.h @@ -261,5 +261,6 @@ #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 +#define CONFIG_SYS_MAIN_PWR_ON #endif diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index e8c6618..4e82355 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -235,6 +235,7 @@ #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 +#define CONFIG_SYS_MAIN_PWR_ON /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/vision2.h b/include/configs/vision2.h index 848df88..13c5702 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -196,6 +196,7 @@ /* 166 MHz DDR RAM */ #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100 +#define CONFIG_SYS_MAIN_PWR_ON #define CONFIG_SYS_NO_FLASH -- cgit v0.10.2 From 90a21030e330645d559a488f806c087809305eff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 21 Nov 2012 16:50:39 +0000 Subject: mx28: Fix typo in POWER_MINPWR_VBG_OFF The POWER_MINPWR_VBG_OFF bit in mx28 power supply block is not called POWER_MINPWR_FBG_OFF, but POWER_MINPWR_VBG_OFF. Correct the name in the header file. Signed-off-by: Marek Vasut Cc: Stefano Babic diff --git a/arch/arm/include/asm/arch-mxs/regs-power.h b/arch/arm/include/asm/arch-mxs/regs-power.h index a46a372..3c98cce 100644 --- a/arch/arm/include/asm/arch-mxs/regs-power.h +++ b/arch/arm/include/asm/arch-mxs/regs-power.h @@ -128,7 +128,7 @@ struct mxs_power_regs { #define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) #define POWER_MINPWR_ENABLE_OSC (1 << 9) #define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_FBG_OFF (1 << 7) +#define POWER_MINPWR_VBG_OFF (1 << 7) #define POWER_MINPWR_DOUBLE_FETS (1 << 6) #define POWER_MINPWR_HALFFETS (1 << 5) #define POWER_MINPWR_LESSANA_I (1 << 4) -- cgit v0.10.2 From 1d4fd0dc3b45de7b7a706285845ef5b527422014 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 21 Nov 2012 17:02:59 +0000 Subject: mx28: Fix typo in POWER_DCLIMITS_NEGLIMIT_OFFSET The POWER_DCLIMITS_NEGLIMIT_OFFSET bit in mx28 power supply block is not called POWER_DCLIMITS_NETLIMIT_OFFSET, but POWER_DCLIMITS_NEGLIMIT_OFFSET. Correct the name in the header file. Signed-off-by: Marek Vasut Cc: Stefano Babic diff --git a/arch/arm/include/asm/arch-mxs/regs-power.h b/arch/arm/include/asm/arch-mxs/regs-power.h index 3c98cce..257ee88 100644 --- a/arch/arm/include/asm/arch-mxs/regs-power.h +++ b/arch/arm/include/asm/arch-mxs/regs-power.h @@ -268,7 +268,7 @@ struct mxs_power_regs { #define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) #define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 #define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NETLIMIT_OFFSET 0 +#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 #define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) #define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -- cgit v0.10.2