From 2ef846e45cf0dbb9fb7d183266e4d57446592177 Mon Sep 17 00:00:00 2001
From: Qianyu Gong <qianyu.gong@nxp.com>
Date: Wed, 23 Mar 2016 19:11:36 +0800
Subject: armv8/ls1043aqds: dts: Set SPI mode for DSPI

Clock phase and polarity for DSPI flash need to be set.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 66efe67..2e9f1f9 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -28,8 +28,10 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "spi-flash";
-		reg = <0>;
 		spi-max-frequency = <1000000>; /* input clock */
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
 	};
 
 	dflash1: sst25wf040b {
@@ -37,6 +39,8 @@
 		#size-cells = <1>;
 		compatible = "spi-flash";
 		spi-max-frequency = <3500000>;
+		spi-cpol;
+		spi-cpha;
 		reg = <1>;
 	};
 
@@ -45,6 +49,8 @@
 		#size-cells = <1>;
 		compatible = "spi-flash";
 		spi-max-frequency = <3500000>;
+		spi-cpol;
+		spi-cpha;
 		reg = <2>;
 	};
 };
-- 
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