From 917d3565b5c6f064250fece1eebd7dc0f78a1fc0 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 7 Oct 2017 02:43:52 -0700 Subject: x86: minnowmax: Adjust VGA rom address Adjust VGA rom address to 0xfffb0000 so that u-boot.rom image can be built again. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index fc2564c..d1332d3 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -6,6 +6,7 @@ CONFIG_INTERNAL_UART=y CONFIG_DEBUG_UART=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y +CONFIG_VGA_BIOS_ADDR=0xfffb0000 CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y diff --git a/doc/README.x86 b/doc/README.x86 index c96a22c..92f4128 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -320,7 +320,7 @@ Offset Description Controlling config 6ef000 Environment CONFIG_ENV_OFFSET 6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE -790000 vga.bin CONFIG_VGA_BIOS_ADDR +7b0000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR 7f8000 (depends on size of fsp.bin) 7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16 -- cgit v0.10.2 From febdfaabc73473ca01e193e0a4be7e89e8f80cb4 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 12 Oct 2017 05:07:57 -0700 Subject: x86: baytrail: Fix unstable ACPI S3 resume It was observed that when booting a Ubuntu 16.04 kernel, doing ACPI S3 suspend/resume sometimes causes the Ubuntu kernel hang forever. The issue is however not reproduced with a kernel built from i386/ x86_64 defconfig configuration. The unstability is actually caused by unexpected interrupts being generated during the S3 resume. For some unknown reason, FSP (gold4) for BayTrail configures the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25). As this pin keeps generating interrupts during an S3 resume, and there is no IRQ requester in the kernel to handle it, the kernel seems to hang and does not continue resuming. Clear the mysterious interrupt bits for this pin. Reported-by: Stefan Roese Signed-off-by: Bin Meng Tested-by: Stefan Roese Reviewed-by: Stefan Roese diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index c58f6a8..9af1bda 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -10,6 +10,13 @@ #include #include #include +#include + +/* GPIO SUS */ +#define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) +#define GPIO_SUS_DFX5_CONF0 0x150 +#define BYT_TRIG_LVL BIT(24) +#define BYT_TRIG_POS BIT(25) #ifndef CONFIG_EFI_APP int arch_cpu_init(void) @@ -33,6 +40,21 @@ int arch_misc_init(void) mrccache_save(); #endif + /* + * For some unknown reason, FSP (gold4) for BayTrail configures + * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25). + * This does not cause any issue when Linux kernel runs w/ or w/o + * the pinctrl driver for BayTrail. However this causes unstable + * S3 resume if the pinctrl driver is included in the kernel build. + * As this pin keeps generating interrupts during an S3 resume, + * and there is no IRQ requester in the kernel to handle it, the + * kernel seems to hang and does not continue resuming. + * + * Clear the mysterious interrupt bits for this pin. + */ + clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0, + BYT_TRIG_LVL | BYT_TRIG_POS); + return 0; } -- cgit v0.10.2 From 3322a8e1a3dd9964b249673f5922a5093bfaf201 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 12 Oct 2017 05:07:58 -0700 Subject: x86: Turn off running VGA ROM during S3 resume This is only needed when graphics console is used. For kernel with native graphics driver, this can be turned off to speed up. Change this option's default to n in the Kconfig. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 38a6187..c869ae2 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -677,7 +677,6 @@ config HAVE_ACPI_RESUME config S3_VGA_ROM_RUN bool "Re-run VGA option ROMs on S3 resume" depends on HAVE_ACPI_RESUME - default y if HAVE_ACPI_RESUME help Execute VGA option ROMs in U-Boot when resuming from S3. Normally this is needed when graphics console is being used in the kernel. -- cgit v0.10.2 From abddcd52ab4979a57dc90ce1b90f8121b43d91b2 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 13 Oct 2017 01:30:04 -0700 Subject: x86: fsp: Consolidate Azalia header file So far there are two copies of Azalia struct defines with one in baytrail and the other one in braswell. This consolidates these two into one, put it in the common place, and remove the prefix pch_ to these structs to make their names more generic. This also corrects reset_wait_timer from us to ms. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 45f9bf9..926f26b 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -8,13 +8,12 @@ #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; /* ALC262 Verb Table - 10EC0262 */ -static const uint32_t verb_table_data13[] = { +static const u32 verb_table_data13[] = { /* Pin Complex (NID 0x11) */ 0x01171cf0, 0x01171d11, @@ -94,7 +93,7 @@ static const uint32_t verb_table_data13[] = { * Codec Address: CAd value (0/1/2) * Codec Vendor: 0x10EC0262 */ -static const struct pch_azalia_verb_table azalia_verb_table[] = { +static const struct azalia_verb_table azalia_verb_table[] = { { { 0x10ec0262, @@ -108,16 +107,16 @@ static const struct pch_azalia_verb_table azalia_verb_table[] = { } }; -const struct pch_azalia_config azalia_config = { +const struct azalia_config azalia_config = { .pme_enable = 1, .docking_supported = 1, .docking_attached = 0, .hdmi_codec_enable = 1, .azalia_v_ci_enable = 1, .rsvdbits = 0, - .azalia_verb_table_num = 1, - .azalia_verb_table = azalia_verb_table, - .reset_wait_timer_us = 300 + .verb_table_num = 1, + .verb_table = azalia_verb_table, + .reset_wait_timer_ms = 300 }; /** diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h deleted file mode 100644 index d96a20f..0000000 --- a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2015 Google, Inc - * - * SPDX-License-Identifier: Intel - */ - -#ifndef _FSP_AZALIA_H_ -#define _FSP_AZALIA_H_ - -struct __packed pch_azalia_verb_table_header { - uint32_t vendor_device_id; - uint16_t sub_system_id; - uint8_t revision_id; /* 0xff applies to all steppings */ - uint8_t front_panel_support; - uint16_t number_of_rear_jacks; - uint16_t number_of_front_jacks; -}; - -struct __packed pch_azalia_verb_table { - struct pch_azalia_verb_table_header verb_table_header; - const uint32_t *verb_table_data; -}; - -struct __packed pch_azalia_config { - uint8_t pme_enable:1; - uint8_t docking_supported:1; - uint8_t docking_attached:1; - uint8_t hdmi_codec_enable:1; - uint8_t azalia_v_ci_enable:1; - uint8_t rsvdbits:3; - /* number of verb tables provided by platform */ - uint8_t azalia_verb_table_num; - const struct pch_azalia_verb_table *azalia_verb_table; - /* delay timer after azalia reset */ - uint16_t reset_wait_timer_us; -}; - -#endif diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h index ecb01fa..99c4c0a 100644 --- a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h @@ -29,32 +29,6 @@ struct __packed memory_upd { u8 reserved[189]; /* Offset 0x0043 */ }; -struct __packed azalia_verb_table_header { - u32 vendor_device_id; - u16 sub_system_id; - u8 revision_id; - u8 front_panel_support; - u16 number_of_rear_jacks; - u16 number_of_front_jacks; -}; - -struct __packed azalia_verb_table { - struct azalia_verb_table_header header; - u32 *data; -}; - -struct __packed azalia_config { - u8 pme_enable:1; - u8 docking_supported:1; - u8 docking_attached:1; - u8 hdmi_codec_enable:1; - u8 azalia_v_ci_enable:1; - u8 reserved:3; - u8 verb_table_num; - struct azalia_verb_table *verb_table; - u16 reset_wait_timer_ms; -}; - struct gpio_family { u32 confg; u32 confg_changes; diff --git a/arch/x86/include/asm/fsp/fsp_azalia.h b/arch/x86/include/asm/fsp/fsp_azalia.h new file mode 100644 index 0000000..a1467bf --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_azalia.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: Intel + */ + +#ifndef _FSP_AZALIA_H_ +#define _FSP_AZALIA_H_ + +struct __packed azalia_verb_table_header { + u32 vendor_device_id; + u16 sub_system_id; + u8 revision_id; /* 0xff applies to all steppings */ + u8 front_panel_support; + u16 number_of_rear_jacks; + u16 number_of_front_jacks; +}; + +struct __packed azalia_verb_table { + struct azalia_verb_table_header header; + const u32 *data; +}; + +struct __packed azalia_config { + u8 pme_enable:1; + u8 docking_supported:1; + u8 docking_attached:1; + u8 hdmi_codec_enable:1; + u8 azalia_v_ci_enable:1; + u8 rsvdbits:3; + /* number of verb tables provided by platform */ + u8 verb_table_num; + const struct azalia_verb_table *verb_table; + /* delay timer after azalia reset */ + u16 reset_wait_timer_ms; +}; + +#endif diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 97a50b0..df3add0 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -15,6 +15,7 @@ #include "fsp_hob.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" +#include "fsp_azalia.h" #include #include -- cgit v0.10.2 From f6859558ca4e18d3a76fafb85924a50026be82fb Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 13 Oct 2017 01:30:05 -0700 Subject: x86: baytrail: fsp: Use a function to update the Azalia config pointer At present we directly pass the Azalia config pointer to the FSP UPD. This updates to use a function to do the stuff, like Braswell does. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 926f26b..3052fb6 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -120,6 +120,17 @@ const struct azalia_config azalia_config = { }; /** + * Override the FSP's Azalia configuration data + * + * @azalia: pointer to be updated to point to a ROM address where Azalia + * configuration data is stored + */ +static void update_fsp_azalia_configs(struct azalia_config **azalia) +{ + *azalia = (struct azalia_config *)&azalia_config; +} + +/** * Override the FSP's configuration data. * If the device tree does not specify an integer setting, use the default * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. @@ -137,8 +148,6 @@ void update_fsp_configs(struct fsp_config_data *config, rt_buf->common.boot_mode = config->common.boot_mode; rt_buf->common.upd_data = &config->fsp_upd; - fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config; - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); if (node < 0) { debug("%s: Cannot find FSP node\n", __func__); @@ -173,6 +182,8 @@ void update_fsp_configs(struct fsp_config_data *config, SATA_MODE_AHCI); fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, "fsp,enable-azalia"); + if (fsp_upd->enable_azalia) + update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr); fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode", LPE_MODE_PCI); diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h index 8c07b37..e2f0e39 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h @@ -45,7 +45,7 @@ struct __packed upd_region { uint8_t enable_sata; /* Offset 0x002d */ uint8_t sata_mode; /* Offset 0x002e */ uint8_t enable_azalia; /* Offset 0x002f */ - uint32_t azalia_config_ptr; /* Offset 0x0030 */ + struct azalia_config *azalia_cfg_ptr; /* Offset 0x0030 */ uint8_t enable_xhci; /* Offset 0x0034 */ uint8_t lpe_mode; /* Offset 0x0035 */ uint8_t lpss_sio_mode; /* Offset 0x0036 */ -- cgit v0.10.2 From 83262f99cd3619336b0d48257bc6595b7610a134 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 13 Oct 2017 01:30:06 -0700 Subject: x86: baytrail: fsp: Move Azalia update codes to board Azalia configuration may be different across boards, hence it's not appropriate to do that in the SoC level. Instead, let's make the SoC update_fsp_azalia_configs() routine as a weak version, and do the actual work in the board codes. So far it seems only som-db5800-som-6867 board enables the Azalia. Move the original codes into som-db5800-som-6867.c. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 3052fb6..6b762e5 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -12,122 +12,15 @@ DECLARE_GLOBAL_DATA_PTR; -/* ALC262 Verb Table - 10EC0262 */ -static const u32 verb_table_data13[] = { - /* Pin Complex (NID 0x11) */ - 0x01171cf0, - 0x01171d11, - 0x01171e11, - 0x01171f41, - /* Pin Complex (NID 0x12) */ - 0x01271cf0, - 0x01271d11, - 0x01271e11, - 0x01271f41, - /* Pin Complex (NID 0x14) */ - 0x01471c10, - 0x01471d40, - 0x01471e01, - 0x01471f01, - /* Pin Complex (NID 0x15) */ - 0x01571cf0, - 0x01571d11, - 0x01571e11, - 0x01571f41, - /* Pin Complex (NID 0x16) */ - 0x01671cf0, - 0x01671d11, - 0x01671e11, - 0x01671f41, - /* Pin Complex (NID 0x18) */ - 0x01871c20, - 0x01871d98, - 0x01871ea1, - 0x01871f01, - /* Pin Complex (NID 0x19) */ - 0x01971c21, - 0x01971d98, - 0x01971ea1, - 0x01971f02, - /* Pin Complex (NID 0x1A) */ - 0x01a71c2f, - 0x01a71d30, - 0x01a71e81, - 0x01a71f01, - /* Pin Complex */ - 0x01b71c1f, - 0x01b71d40, - 0x01b71e21, - 0x01b71f02, - /* Pin Complex */ - 0x01c71cf0, - 0x01c71d11, - 0x01c71e11, - 0x01c71f41, - /* Pin Complex */ - 0x01d71c01, - 0x01d71dc6, - 0x01d71e14, - 0x01d71f40, - /* Pin Complex */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, - /* Pin Complex */ - 0x01f71cf0, - 0x01f71d11, - 0x01f71e11, - 0x01f71f41, -}; - -/* - * This needs to be in ROM since if we put it in CAR, FSP init loses it when - * it drops CAR. - * - * TODO(sjg@chromium.org): Move to device tree when FSP allows it - * - * VerbTable: (RealTek ALC262) - * Revision ID = 0xFF, support all steps - * Codec Verb Table For AZALIA - * Codec Address: CAd value (0/1/2) - * Codec Vendor: 0x10EC0262 - */ -static const struct azalia_verb_table azalia_verb_table[] = { - { - { - 0x10ec0262, - 0x0000, - 0xff, - 0x01, - 0x000b, - 0x0002, - }, - verb_table_data13 - } -}; - -const struct azalia_config azalia_config = { - .pme_enable = 1, - .docking_supported = 1, - .docking_attached = 0, - .hdmi_codec_enable = 1, - .azalia_v_ci_enable = 1, - .rsvdbits = 0, - .verb_table_num = 1, - .verb_table = azalia_verb_table, - .reset_wait_timer_ms = 300 -}; - /** * Override the FSP's Azalia configuration data * * @azalia: pointer to be updated to point to a ROM address where Azalia * configuration data is stored */ -static void update_fsp_azalia_configs(struct azalia_config **azalia) +__weak void update_fsp_azalia_configs(struct azalia_config **azalia) { - *azalia = (struct azalia_config *)&azalia_config; + *azalia = NULL; } /** diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 6158795..202e9875 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -6,6 +6,117 @@ */ #include +#include + +/* ALC262 Verb Table - 10EC0262 */ +static const u32 verb_table_data13[] = { + /* Pin Complex (NID 0x11) */ + 0x01171cf0, + 0x01171d11, + 0x01171e11, + 0x01171f41, + /* Pin Complex (NID 0x12) */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin Complex (NID 0x14) */ + 0x01471c10, + 0x01471d40, + 0x01471e01, + 0x01471f01, + /* Pin Complex (NID 0x15) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin Complex (NID 0x16) */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin Complex (NID 0x18) */ + 0x01871c20, + 0x01871d98, + 0x01871ea1, + 0x01871f01, + /* Pin Complex (NID 0x19) */ + 0x01971c21, + 0x01971d98, + 0x01971ea1, + 0x01971f02, + /* Pin Complex (NID 0x1A) */ + 0x01a71c2f, + 0x01a71d30, + 0x01a71e81, + 0x01a71f01, + /* Pin Complex */ + 0x01b71c1f, + 0x01b71d40, + 0x01b71e21, + 0x01b71f02, + /* Pin Complex */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin Complex */ + 0x01d71c01, + 0x01d71dc6, + 0x01d71e14, + 0x01d71f40, + /* Pin Complex */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + /* Pin Complex */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +/* + * This needs to be in ROM since if we put it in CAR, FSP init loses it when + * it drops CAR. + * + * VerbTable: (RealTek ALC262) + * Revision ID = 0xFF, support all steps + * Codec Verb Table For AZALIA + * Codec Address: CAd value (0/1/2) + * Codec Vendor: 0x10EC0262 + */ +static const struct azalia_verb_table azalia_verb_table[] = { + { + { + 0x10ec0262, + 0x0000, + 0xff, + 0x01, + 0x000b, + 0x0002, + }, + verb_table_data13 + } +}; + +static const struct azalia_config azalia_config = { + .pme_enable = 1, + .docking_supported = 1, + .docking_attached = 0, + .hdmi_codec_enable = 1, + .azalia_v_ci_enable = 1, + .rsvdbits = 0, + .verb_table_num = 1, + .verb_table = azalia_verb_table, + .reset_wait_timer_ms = 300 +}; + +void update_fsp_azalia_configs(const struct azalia_config **azalia) +{ + *azalia = &azalia_config; +} int board_early_init_f(void) { -- cgit v0.10.2 From 871aa41d4c9ecf8d89b98491dc86d0097fdf80e5 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 16 Oct 2017 18:08:38 +0000 Subject: x86: provide CONFIG_BUILD_ROM Up to now we depended on an exported variable to build u-boot.rom. We should be able to specify it in the configuration file, too. With this patch this becomes possible using the new Kconfig option CONFIG_BUILD_ROM. This option depends on CONFIG_X86 and is selected in qemu-x86_defconfig and qemu-x86_64_defconfig. Cc: Simon Glass Cc: Bin Meng Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng diff --git a/Kconfig b/Kconfig index 73f820a..227fb17 100644 --- a/Kconfig +++ b/Kconfig @@ -158,6 +158,15 @@ config PHYS_64BIT This can be used not only for 64bit SoCs, but also for large physical address extention on 32bit SoCs. +config BUILD_ROM + bool "Build U-Boot as BIOS replacement" + depends on X86 + help + This option allows to build a ROM version of U-Boot. + The build process generally requires several binary blobs + which are not shipped in the U-Boot source tree. + Please, see doc/README.x86 for details. + endmenu # General setup menu "Boot images" diff --git a/Makefile b/Makefile index d074358..79150bb 100644 --- a/Makefile +++ b/Makefile @@ -796,7 +796,7 @@ ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf ALL-$(CONFIG_EFI_APP) += u-boot-app.efi ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi -ifneq ($(BUILD_ROM),) +ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),) ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom endif diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index fae4a9c..0cea369 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -14,6 +14,7 @@ CONFIG_SMP=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_BUILD_ROM=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTAGE=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index ffdb4c3..bf7fbc7 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -5,6 +5,7 @@ CONFIG_SMP=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_BUILD_ROM=y CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y diff --git a/doc/README.x86 b/doc/README.x86 index 92f4128..772e8d2 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -80,11 +80,15 @@ Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is not turned on by default in the U-Boot source tree. Firstly, you need turn it -on by enabling the ROM build: +on by enabling the ROM build either via an environment variable -$ export BUILD_ROM=y + $ export BUILD_ROM=y -This tells the Makefile to build u-boot.rom as a target. +or via configuration + + CONFIG_BUILD_ROM=y + +Both tell the Makefile to build u-boot.rom as a target. --- -- cgit v0.10.2 From 9af43acba6ea1fe6de29150b8bd3eb0126ba6a15 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 17 Oct 2017 08:09:14 +0200 Subject: x86: conga-qeval20-qa3-e3845-internal-uart_defconfig: Add ACPI resume support I've missed to add the ACPI resume support to this x86 build target. This patch adds the ACPI resume support enabling S3 suspend / resume. Signed-off-by: Stefan Roese Cc: Bin Meng Cc: Simon Glass Reviewed-by: Bin Meng diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 971cfc6..59bde05 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -9,6 +9,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y -- cgit v0.10.2