From a5fbe7422edcbf83a58d03263c4eed0f06283dab Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 24 Oct 2014 10:11:16 +0200 Subject: mpc85xx/kmp204x: raise u-boot size to 768KB Until now this defined to be 512KB and the total binary size actually was on the edge of this limit. Most of the powerpc boards have thus moved to 768KB. Since on the current kmp204x boards there is 1MB reserved for u-boot on the SPI boot flash, there is no problem to set the limit to 768KB as well to be on line with the other powerpc boards and to eventually configure in some additional features (and binary size) to u-boot. Signed-off-by: Valentin Longchamp Reviewed-by: York Sun diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index a0f9d29..c5c9dfc 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -11,7 +11,7 @@ #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P2041 -#define CONFIG_SYS_TEXT_BASE 0xfff80000 +#define CONFIG_SYS_TEXT_BASE 0xfff40000 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" @@ -235,7 +235,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Serial Port - controlled on board with jumper J8 -- cgit v0.10.2 From ff5fb2a36dff8a92d6483359167a6b1525359eaf Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Wed, 13 Aug 2014 18:32:19 +0800 Subject: Fman/mEMAC: mEMAC fix for 10G MAC and PHY 1. use Payload length check disable when enable MAC; 2. add XGMII support for setting MAC interface mode; 3. only enable auto negotiation for Non-XGMII mode; 4. return 0xffff if clause 22 is used to read 10G phy_id; Signed-off-by: Shaohui Xie Signed-off-by: Roy Zang Acked-By: Joe Hershberger Reviewed-by: York Sun diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h index 4640e33..f84c1a9 100644 --- a/arch/powerpc/include/asm/fsl_memac.h +++ b/arch/powerpc/include/asm/fsl_memac.h @@ -159,6 +159,7 @@ struct memac { #define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ #define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ #define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN) +#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */ /* HASHTABLE_CTRL - Hashtable control register */ #define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 9499290..60e898c 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -37,7 +37,8 @@ static void memac_enable_mac(struct fsl_enet_mac *mac) { struct memac *regs = mac->base; - setbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); + setbits_be32(®s->command_config, + MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK); } static void memac_disable_mac(struct fsl_enet_mac *mac) @@ -93,11 +94,16 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode &= ~IF_MODE_MASK; if_mode |= (IF_MODE_GMII); break; + case PHY_INTERFACE_MODE_XGMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= IF_MODE_XGMII; + break; default: break; } - /* Enable automatic speed selection */ - if_mode |= IF_MODE_EN_AUTO; + /* Enable automatic speed selection for Non-XGMII */ + if (type != PHY_INTERFACE_MODE_XGMII) + if_mode |= IF_MODE_EN_AUTO; if (type == PHY_INTERFACE_MODE_RGMII) { if_mode &= ~IF_MODE_EN_AUTO; diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 5f910c2..e432ae7 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -71,6 +71,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, u32 c45 = 1; if (dev_addr == MDIO_DEVAD_NONE) { + if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME)) + return 0xffff; c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); -- cgit v0.10.2 From ae6b45830637f7540d0c06280c886bfcb295d27b Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Wed, 13 Aug 2014 18:38:09 +0800 Subject: driver/net/fm/memac_phy: set NEG bit for external MDIOs NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure on XAUI PHY, so set this bit definitely to align with the RM. Signed-off-by: Shaohui Xie Acked-by: Joe Hershberger Reviewed-by: York Sun diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h index f84c1a9..bed2a40 100644 --- a/arch/powerpc/include/asm/fsl_memac.h +++ b/arch/powerpc/include/asm/fsl_memac.h @@ -244,6 +244,7 @@ struct memac_mdio_controller { #define MDIO_STAT_PRE (1 << 5) #define MDIO_STAT_ENC (1 << 6) #define MDIO_STAT_HOLD_15_CLK (7 << 2) +#define MDIO_STAT_NEG (1 << 23) #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index e432ae7..a155d89 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -139,9 +139,12 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) * is zero, so MDIO clock is disabled. * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to * be properly initialized. + * NEG bit default should be '1' as per FMAN-v3 RM, but on platform + * like T2080QDS, this bit default is '0', which leads to MDIO failure + * on XAUI PHY, so set this bit definitely. */ setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat, - MDIO_STAT_CLKDIV(258)); + MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG); return mdio_register(bus); } -- cgit v0.10.2 From 2bf4207b8a452476a591d733c6b8f09b337acc08 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Thu, 14 Aug 2014 10:42:52 -0400 Subject: sbc8548: enable and test CONFIG_SYS_GENERIC_BOARD Tested on the following baseline (note "dirty" since I enabled ALT_BOOT in the config in order to use the alternate boot bank.) Everything seems to work fine with no additional changes. The banner warning message is now gone. --- U-Boot 2014.10-rc1-00075-ge49f14af1349-dirty (Aug 14 2014 - 10:26:15) CPU: 8548E, Version: 2.1, (0x80390021) Core: e500, Version: 2.2, (0x80210022) Clock Configuration: CPU0:990 MHz, CCB:396 MHz, DDR:198 MHz (396 MT/s data rate), LBC:99 MHz L1: D-cache 32 KiB enabled I-cache 32 KiB enabled I2C: ready DRAM: Detected UDIMM SDRAM: 128 MiB 256 MiB (DDR2, 64-bit, CL=3, ECC off) Flash: 72 MiB L2: 512 KiB enabled *** Warning - bad CRC, using default environment PCI: Host, 64 bit, 66 MHz, sync, arbiter 00:01.0 - 8086:1026 - Network controller PCI1: Bus 00 - 00 PCIe1: Root Complex, x1 gen1, regs @ 0xe000a000 02:00.0 - 1148:9e00 - Network controller PCIe1: Bus 01 - 02 In: serial Out: serial Err: serial Net: eTSEC0 [PRIME], eTSEC1 Hit any key to stop autoboot: 0 => ver U-Boot 2014.10-rc1-00075-ge49f14af1349-dirty (Aug 14 2014 - 10:26:15) powerpc-linux-gcc (GCC) 4.5.2 GNU ld (GNU Binutils) 2.21 => --- Signed-off-by: Paul Gortmaker Reviewed-by: York Sun diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index f28f350..aee0d9e 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -13,6 +13,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Top level Makefile configuration choices */ -- cgit v0.10.2 From a53dd530013bba81ad6ba87a661ff19b12977c23 Mon Sep 17 00:00:00 2001 From: ramneek mehresh Date: Thu, 21 Aug 2014 17:52:17 +0530 Subject: 85xx/b4:Correct USB DR controller liodn entry LIODN entry for B4860/B4420 mentions USB controller as "mph" insread of "dr". This results in PAMU not permitting bus transactions for USB DR controller on B4860 resulting in USB function failure. Replacing "fsl-usb2-mph" with "fsl-usb2-dr" allows USB DR controller bus transactions Signed-off-by: Poonam Aggrwal Signed-off-by: Ramneek Mehresh Reviewed-by: Sethi Varun-B16395 Reviewed-by: Sun Yusong-R58495 diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 39b8e3e..1a30f1c 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -55,7 +55,7 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 552), - SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(1, "fsl-usb2-dr", 553), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), -- cgit v0.10.2 From ab06b236f76cfa42f264ee161be190b3e479298f Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Fri, 12 Sep 2014 14:47:09 +0800 Subject: powerpc/t4rdb: Add support of CPLD This support of CPLD includes - Files and register definitions - Command to switch alternate bank - Command to switch default bank Signed-off-by: Chunhe Lan Reviewed-by: York Sun diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index f7f7fc0..3886e3d 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -5,6 +5,7 @@ # obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-y += cpld.o obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c new file mode 100644 index 0000000..d5f3812 --- /dev/null +++ b/board/freescale/t4rdb/cpld.c @@ -0,0 +1,136 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CPLD register map + * + */ + +#include +#include +#include + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 val, curbank, altbank, override; + + val = CPLD_READ(vbank); + curbank = val & CPLD_BANK_SEL_MASK; + + switch (curbank) { + case CPLD_SELECT_BANK0: + altbank = CPLD_SELECT_BANK4; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + case CPLD_SELECT_BANK4: + altbank = CPLD_SELECT_BANK0; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + default: + printf("CPLD Altbank Fail: Invalid value!\n"); + return; + } +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 val; + + val = CPLD_DEFAULT_BANK; + + CPLD_WRITE(global_reset, val); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); + printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); + printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); + printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("software_on = 0x%02x\n", CPLD_READ(software_on)); + printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); + printf("res0 = 0x%02x\n", CPLD_READ(res0)); + printf("vbank = 0x%02x\n", CPLD_READ(vbank)); + printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk)); + printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status)); + printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status)); + printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status)); + printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); + printf("global_reset = 0x%02x\n", CPLD_READ(global_reset)); + printf("res1 = 0x%02x\n", CPLD_READ(res1)); + putc('\n'); +} +#endif + +#ifndef CONFIG_SPL_BUILD +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); +#endif diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h new file mode 100644 index 0000000..0180082 --- /dev/null +++ b/board/freescale/t4rdb/cpld.h @@ -0,0 +1,49 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ + u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ + u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ + u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ + u8 hw_ver; /* 0x04 - PCBA Version Register */ + u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ + u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ + u8 res0; /* 0x07 - not used */ + u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ + u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ + u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ + u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ + u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ + u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ + u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ + u8 res1; /* 0x0f - not used */ +}; + +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_EN 0x04 +#define CPLD_SYSTEM_RESET 0x01 +#define CPLD_SELECT_BANK0 0x00 +#define CPLD_SELECT_BANK4 0x04 +#define CPLD_DEFAULT_BANK 0x01 + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index 1f58768..39818fc 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -16,6 +16,9 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index afef7e9..2ff77b8 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -20,14 +20,26 @@ #include #include "t4rdb.h" +#include "cpld.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; + u8 sw; printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); + + sw = CPLD_READ(vbank); + sw = sw & CPLD_BANK_SEL_MASK; + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); puts("SERDES Reference Clocks:\n"); printf(" SERDES1=100MHz SERDES2=156.25MHz\n" diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 4b50bcd..474301e 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -106,6 +106,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 13f4bd3..e639e1d 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -514,6 +514,29 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_CSOR3 0x0 + +/* CPLD Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT #endif -- cgit v0.10.2 From 0921de67440ac5dfc3dbf687217cdecc6335f15e Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Wed, 17 Sep 2014 15:57:54 +0530 Subject: t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg -A_007662 states that for x1 link width, PCIe2 controller trains in Gen1 speed while configured for Gen2 speed. Workaround:Set the width to x1 and speed to Gen2 by writing to CCSR registers in PBI phase -A_008007 states that PVR register may show random value. Workaround: Reset PVR register using DCSR space in PBI phase Add PBI based software workaround for A_007662 and A_008007 in t104x_pbi.cfg. This is required for SPL-based bootloaders like NAND-boot, SD-boot, SPI-boot Signed-off-by: Priyanka Jain Reviewed-by: York Sun diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg index 7b9e9b0..b83b9b7 100644 --- a/board/freescale/t104xrdb/t104x_pbi.cfg +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -1,4 +1,14 @@ #PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 #Initialize CPC1 09010000 00200400 09138000 00000000 -- cgit v0.10.2 From aa5a3d8d4622fc5f0115aa7c4ac752ae60458a44 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 23 Sep 2014 10:57:12 +0530 Subject: powerpc/mpc85xx: Use IFC accessor function IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So use IFC acessor functions instead of in_be32(). Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 072387a..5ca9bf5 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -70,9 +70,9 @@ void setup_ifc(void) #endif /* Change flash's physical address */ - out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); - out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); - out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); + ifc_out32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); + ifc_out32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); + ifc_out32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); return ; } diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 3236f6a..8426b1a 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -430,7 +430,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #if defined(CONFIG_FSL_IFC) - ccr = in_be32(&ifc_regs->ifc_ccr); + ccr = ifc_in32(&ifc_regs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; sys_info->freq_localbus = sys_info->freq_systembus / ccr; -- cgit v0.10.2 From 42a9e2fe1be0f8879ad0928e05116e5a4c7cea1a Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Mon, 6 Oct 2014 18:24:56 +0530 Subject: powerpc/BSC9132QDS: Enable creation of dynamic partition for NAND and NOR * fdt_fixup_mtdparts is called from ft_board_setup * run "mtdparts default" to create NAND, NOR partition on uboot * Use mtdparts to create partitions dynamically rather than using static partitions in device tree Signed-off-by: Ashish Kumar Reviewed-by: York Sun diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 10580bc..c88838b 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -21,6 +21,9 @@ #include #include #include +#include +#include +#include #ifdef CONFIG_PCI #include @@ -354,6 +357,12 @@ void fdt_del_node_compat(void *blob, const char *compatible) } #if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +struct node_info nodes[] = { + { "cfi-flash", MTD_DEV_TYPE_NOR, }, + { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, +}; +#endif void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -369,6 +378,9 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 porbmsr = in_be32(&gur->porbmsr); diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 989363c..2722a32 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -637,6 +637,27 @@ combinations. this should be removed later #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," +#define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ + "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ + "8m(kernel),512k(dtb),-(fs)" +#endif +/* + * Override partitions in device tree using info + * in "mtdparts" environment variable + */ +#ifdef CONFIG_CMD_MTDPARTS +#define CONFIG_FDT_FIXUP_PARTITIONS +#endif + +/* * Environment Configuration */ -- cgit v0.10.2 From 7ac1a24a85b9e961f8f26a9c2a23a438a849f183 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Tue, 7 Oct 2014 18:02:23 +0530 Subject: powerpc/BSC9131RDB: Enable creation of dynamic partitions for NAND * fdt_fixup_mtdparts is called from ft_board_setup * Run "mtdparts default" to create NAND partition on uboot * Use mtdparts to create partitions dynamically rather than using static partitions in device tree Signed-off-by: Ashish Kumar Reviewed-by: York Sun diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c index 7fe4ae7..9146f49 100644 --- a/board/freescale/bsc9131rdb/bsc9131rdb.c +++ b/board/freescale/bsc9131rdb/bsc9131rdb.c @@ -15,6 +15,9 @@ #include #include #include +#include +#include +#include #include @@ -50,6 +53,11 @@ int checkboard(void) } #if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +struct node_info nodes[] = { + { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, +}; +#endif void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -61,6 +69,9 @@ void ft_board_setup(void *blob, bd_t *bd) size = getenv_bootm_size(); fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif fdt_fixup_dr_usb(blob, bd); } diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index bc5af52..adb8146 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -400,6 +400,23 @@ extern unsigned long get_sdram_size(void); #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=ff800000.flash," +#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \ + "8m(kernel),512k(dtb),-(fs)" +/* + * Override partitions in device tree using info + * in "mtdparts" environment variable + */ +#ifdef CONFIG_CMD_MTDPARTS +#define CONFIG_FDT_FIXUP_PARTITIONS +#endif + +/* * Environment Configuration */ -- cgit v0.10.2 From e83a7e9453295753e84ab51221d167e87cac67aa Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 3 Oct 2014 11:45:23 +0200 Subject: powerpc/mpc83xx: Zero boot_flags arg for calling board_init_f() The argument boot_flags of board_init_f() is not used at all in the powerpc specific board.c init sequence. Now with the generic init sequence, this boot_flags arg is used by board_init_f(). This patch sets the r3 register that is used to pass the boot_flags argument from the start.S board_init_f() call to 0 prior to the function call to avoid unknown content to end up in gd->flags. Signed-off-by: Valentin Longchamp Reviewed-by: York Sun diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index af75c63..9bd86d8 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -283,6 +283,7 @@ in_flash: bl cpu_init_f /* run 1st part of board init code (in Flash)*/ + li r3, 0 /* clear boot_flag for calling board_init_f */ bl board_init_f /* NOTREACHED - board_init_f() does not return */ -- cgit v0.10.2 From a0744285eeb90ecc72f75d2fc6901f9ce9db967c Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 3 Oct 2014 11:45:24 +0200 Subject: keymile/powerpc: move to the architecture-generic board system This converts all the Keymile powerpc boards to the generic board initialization. This includes the 3 Keymile powerpc subsystems: km82xx, km83xx, and kmp204x. Signed-off-by: Valentin Longchamp Reviewed-by: York Sun diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index ae6b6dc..940000e 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_KM83XX_H #define __CONFIG_KM83XX_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* include common defines/options for all Keymile boards */ #include "keymile-common.h" #include "km-powerpc.h" diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index c5c9dfc..864e5f1 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -21,6 +21,9 @@ #define CONFIG_NAND_ECC_BCH +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* common KM defines */ #include "keymile-common.h" diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h index 029c348..69ba66a 100644 --- a/include/configs/km82xx.h +++ b/include/configs/km82xx.h @@ -29,6 +29,9 @@ #error ("Board unsupported") #endif +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #define CONFIG_SYS_TEXT_BASE 0xFE000000 /* include common defines/options for all Keymile boards */ -- cgit v0.10.2 From 94b383e7d843efe2618535f01776921751dd756b Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 16 Oct 2014 10:58:55 +0800 Subject: powerpc/85xx: enable some P1/P2 boards mtdparts for nor flash Enable these boards mtdparts for nor flash: p1020rdb-pd, p1021rdb-pc, p1022ds, p1025twr, and p2020rdb-pc. Signed-off-by: Xie Xiaobo Signed-off-by: Yangbo Lu Cc: York Sun Cc: Scott Wood diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 54e2569..bd08090 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -616,6 +616,25 @@ #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fe8000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ + "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ + "512k(dtb),768k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=e8000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ + "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ + "512k(dtb),768k(u-boot)" +#endif + +/* * Environment */ #ifdef CONFIG_SPIFLASH diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9b58950..5f27c2a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -80,6 +80,16 @@ #define __SW_BOOT_NAND 0x44 #define __SW_BOOT_PCIE 0x74 #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ + "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" #endif #if defined(CONFIG_P1021RDB) @@ -98,6 +108,24 @@ #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" +#endif #endif #if defined(CONFIG_P1024RDB) @@ -145,6 +173,22 @@ #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 #define CONFIG_SYS_L2_SIZE (512 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +#endif #endif #ifdef CONFIG_SDCARD diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 911203d..681bc92 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -389,6 +389,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_TWR-P1025 */ /* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),5632k(kernel),57856k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" + +/* * Environment */ #ifdef CONFIG_SYS_RAMBOOT -- cgit v0.10.2