From 07806977878130dd27dfc926ef7002041f6cf288 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Dec 2015 04:00:09 +0100 Subject: arm: socfpga: Actually enable L2 cache The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index b110f5b..a54d2b9 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -54,14 +54,23 @@ void enable_caches(void) void v7_outer_cache_enable(void) { - /* disable the L2 cache */ - writel(0, &pl310->pl310_ctrl); + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } /* -- cgit v0.10.2 From 25af71c4bfcd54a88cc9098f23416fe9d1f7d80c Mon Sep 17 00:00:00 2001 From: Thomas Chou Date: Mon, 7 Dec 2015 20:53:29 +0800 Subject: net: eth_designware: select PHYLIB in Kconfig Select PHYLIB in drivers/net/Kconfig. And remove CONFIG_PHYLIB from legacy board header files. This fixed the warnings when both ALTERA_TSE and ETH_DESIGNWARE are selected. Signed-off-by: Thomas Chou Reported-by: Pavel Machek Acked-by: Chin Liang See Acked-by: Pavel Machek Tested-by: Pavel Machek Reviewed-by: Bin Meng diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index ae5e78d..de54ca8 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -88,6 +88,7 @@ config ETH_SANDBOX_RAW config ETH_DESIGNWARE bool "Synopsys Designware Ethernet MAC" + select PHYLIB help This MAC is present in SoCs from various vendors. It supports 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to diff --git a/drivers/net/designware.c b/drivers/net/designware.c index a6c39c3..3af43b4 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -22,10 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_PHYLIB) -# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" -#endif - static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { struct eth_mac_regs *mac_p = bus->priv; diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 650d97d..eeb2ae6 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -95,7 +95,6 @@ /* * Ethernet PHY configuration */ -#define CONFIG_PHYLIB #define CONFIG_MII #define CONFIG_PHY_GIGE diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 0e353b9..b5d4847 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -75,7 +75,6 @@ #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_MII #define CONFIG_MII -#define CONFIG_PHYLIB /* i2c Settings */ #define CONFIG_SYS_I2C diff --git a/include/configs/galileo.h b/include/configs/galileo.h index eb16a5e..14a42b1 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -45,7 +45,6 @@ /* 10/100M Ethernet support */ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_PHYLIB /* Environment configuration */ #define CONFIG_ENV_SECT_SIZE 0x1000 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 3a4df63..1da2ecf 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -109,7 +109,6 @@ #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) -#define CONFIG_PHYLIB #define CONFIG_PHY_GIGE #endif diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 1d69477..d2630f4 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,7 +17,6 @@ /* Ethernet driver configuration */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 14c6a9e..f421321 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -53,7 +53,6 @@ /* GMAC related configs */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_PHY_MICREL diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index da6ab61..46f7994 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -313,7 +313,6 @@ extern int soft_i2c_gpio_scl; #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ #define CONFIG_PHY_ADDR 1 #define CONFIG_MII /* MII PHY management */ -#define CONFIG_PHYLIB #endif #ifdef CONFIG_USB_EHCI_HCD diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 8660ed4..e06484f 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -42,7 +42,6 @@ /* * Ethernet PHY configuration */ -#define CONFIG_PHYLIB #define CONFIG_PHY_GIGE /* diff --git a/include/configs/x600.h b/include/configs/x600.h index 58f1aca..0263c50 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -77,7 +77,6 @@ /* Ethernet config options */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ -- cgit v0.10.2 From 4c9ae24fe8e171b87389cae596b07423e5a0ea73 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Dec 2015 03:59:41 +0100 Subject: net: designware: Zap CONFIG_DW_AUTONEG This symbol is not used anywhere, so remove it. For spear600, remove it from the board file, since the symbol is not defined for spear600 either. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Joe Hershberger diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index fc0918f..858a9ca 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -48,9 +48,6 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_ETH_DESIGNWARE) u32 interface = PHY_INTERFACE_MODE_MII; -#if defined(CONFIG_DW_AUTONEG) - interface = PHY_INTERFACE_MODE_GMII; -#endif if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif diff --git a/include/configs/axs101.h b/include/configs/axs101.h index eeb2ae6..ee2a9c0 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -99,11 +99,6 @@ #define CONFIG_PHY_GIGE /* - * Ethernet configuration - */ -#define CONFIG_DW_AUTONEG - -/* * Commands still not supported in Kconfig */ #define CONFIG_CMD_FAT diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 46f7994..921d912 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -309,7 +309,6 @@ extern int soft_i2c_gpio_scl; #endif #ifdef CONFIG_SUNXI_GMAC -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ #define CONFIG_PHY_ADDR 1 #define CONFIG_MII /* MII PHY management */ -- cgit v0.10.2 From 2b2610921920d841bbf0f6b7de2b170aa8cd9598 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Dec 2015 03:59:23 +0100 Subject: net: designware: Zap trailing backslash Trailing backslashes are necessary only in macros, not in the actual code, so remove them. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Joe Hershberger diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 3af43b4..04114a1 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -103,8 +103,8 @@ static void tx_descs_init(struct dw_eth_dev *priv) #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | - DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ - DESC_TXSTS_TXCHECKINSCTRL | \ + DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | + DESC_TXSTS_TXCHECKINSCTRL | DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; @@ -151,7 +151,7 @@ static void rx_descs_init(struct dw_eth_dev *priv) desc_p->dmamac_next = &desc_table_p[idx + 1]; desc_p->dmamac_cntl = - (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ + (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | DESC_RXCTRL_RXCHAIN; desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; @@ -317,14 +317,14 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; - desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ + desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & DESC_TXCTRL_SIZE1MASK; desc_p->txrx_status &= ~(DESC_TXSTS_MSK); desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; #else - desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ - DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ + desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & + DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | DESC_TXCTRL_TXFIRST; desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; @@ -364,7 +364,7 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) /* Check if the owner is the CPU */ if (!(status & DESC_RXSTS_OWNBYDMA)) { - length = (status & DESC_RXSTS_FRMLENMSK) >> \ + length = (status & DESC_RXSTS_FRMLENMSK) >> DESC_RXSTS_FRMLENSHFT; /* Invalidate received data */ -- cgit v0.10.2 From 79cc48e77c95768ac69ac5403bccda8234e82991 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 21 Dec 2015 21:02:45 +0800 Subject: arm: socfpga: Consolidate SDMMC environment Remove the duplication of SDMMC environment configuration from each boards' configuration header file into socfpga_common.h Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 1da2ecf..275aa6d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -270,6 +270,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE #define CONFIG_ENV_SIZE 4096 +/* Environment for SDMMC boot */ +#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ +#endif + /* * SPL * -- cgit v0.10.2 From 7d6bf079c47899ddf386b587bcfb78af742ba0e4 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 21 Dec 2015 21:02:46 +0800 Subject: arm: socfpga: cyclone5_socdk: Consolidate SDMMC environment Remove the duplication of SDMMC environment configuration from each boards' configuration header file into socfpga_common.h Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index d2efdda..3c2e2ae 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -52,8 +52,6 @@ #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2 From 8a08962a5b4d0b4f0cff504703818a4b2ff53fac Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 21 Dec 2015 21:02:47 +0800 Subject: arm: socfpga: arria5_socdk: Consolidate SDMMC environment Remove the duplication of SDMMC environment configuration from each boards' configuration header file into socfpga_common.h Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 3d5665d..af0f87f 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -52,8 +52,6 @@ #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2 From 617600bd61906fb800dac347d978343151ac2093 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 21 Dec 2015 21:02:48 +0800 Subject: arm: socfpga: de0_nano_soc: Consolidate SDMMC environment Remove the duplication of SDMMC environment configuration from each boards' configuration header file into socfpga_common.h Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 959e3af..cbc7396 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -48,8 +48,6 @@ #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2 From a4417affe12a3a0b9fbfdb1e290c4af4fe523a0c Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 21 Dec 2015 21:02:49 +0800 Subject: arm: socfpga: mcvevk: Consolidate SDMMC environment Remove the duplication of SDMMC environment configuration from each boards' configuration header file into socfpga_common.h Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index cd63faf..e7b5675 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -45,8 +45,6 @@ /* Environment is in MMC */ #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2 From 866da6e7796269684fb5dfe16087fbd6304d2e6d Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 21 Dec 2015 21:02:50 +0800 Subject: arm: socfpga: sockit: Consolidate SDMMC environment Remove the duplication of SDMMC environment configuration from each boards' configuration header file into socfpga_common.h Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 6cbe367..2356c74 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -48,8 +48,6 @@ #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2 From 520b9e0956bf7569bab4943a7f0da4881adaa25d Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 21 Dec 2015 21:02:51 +0800 Subject: arm: socfpga: socrates: Consolidate SDMMC environment Remove the duplication of SDMMC environment configuration from each boards' configuration header file into socfpga_common.h Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index 1d88f4f..c32a40a 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -48,8 +48,6 @@ #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2 From 55702fe275b9570418fd71f09c0cab08c02860d1 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 21 Dec 2015 23:01:51 +0800 Subject: arm: socfpga: Enabling MTD default partitions Enabling MTD default partitions if its not defined in board configuration file. The layout as below device nor0 , # parts = 6 #: name size offset mask_flags 0: u-boot 0x00100000 0x00000000 0 1: env1 0x00040000 0x00100000 0 2: env2 0x00040000 0x00140000 0 3: UBI 0x03e80000 0x00180000 0 4: boot 0x00e80000 0x00180000 0 5: rootfs 0x01000000 0x01000000 0 Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 275aa6d..6655152 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -196,7 +196,7 @@ unsigned int cm_get_l4_sp_clk_hz(void); #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nor0=ff705000.spi" +#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" #endif /* QSPI reference clock */ #ifndef __ASSEMBLY__ @@ -277,6 +277,29 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif /* + * mtd partitioning for serial NOR flash + * + * device nor0 , # parts = 6 + * #: name size offset mask_flags + * 0: u-boot 0x00100000 0x00000000 0 + * 1: env1 0x00040000 0x00100000 0 + * 2: env2 0x00040000 0x00140000 0 + * 3: UBI 0x03e80000 0x00180000 0 + * 4: boot 0x00e80000 0x00180000 0 + * 5: rootfs 0x01000000 0x01000000 0 + * + */ +#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) +#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ + "1m(u-boot)," \ + "256k(env1)," \ + "256k(env2)," \ + "14848k(boot)," \ + "16m(rootfs)," \ + "-@1536k(UBI)\0" +#endif + +/* * SPL * * SRAM Memory layout: -- cgit v0.10.2 From 68909e823eb4074a7e559e0c03d16533813c86cf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 22 Dec 2015 04:15:21 +0100 Subject: arm: socfpga: Make /soc available in pre-reloc This node must be available before relocation, otherwise the board will not find mmc and will thus not boot. Signed-off-by: Marek Vasut Cc: Dinh Nguyen diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 224928f..a202709 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -34,6 +34,10 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { -- cgit v0.10.2 From 574967c241301b924748ce205f29f494e32967fe Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 22 Dec 2015 04:16:01 +0100 Subject: arm: socfpga: Enable simple bus in SPL on all boards The simple bus support must be enabled in SPL, otherwise the boards will not be able to parse the DT and will fail to boot. Signed-off-by: Marek Vasut Cc: Dinh Nguyen diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 10eb91d..a9f9ea3 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 864358c..c9e39f1 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y -- cgit v0.10.2 From 6cdd465cbe884d51f566ac5f7f06cc2a82d5a18b Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:26 +0800 Subject: arm: socfpga: Enable ubi and ubifs support When QSPI and NAND is enabled, the ubi and ubifs support will be enabled too. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 6655152..35e4a75 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -299,6 +299,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "-@1536k(UBI)\0" #endif +/* UBI and UBIFS support */ +#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#endif + /* * SPL * -- cgit v0.10.2 From 6a6e6cf869637d34c5efac853d69bba7ef3728aa Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:27 +0800 Subject: arm: socfpga: cyclone5: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS for UBI and UBIFS support on serial NOR flash Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index c9e39f1..accee92 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -24,3 +24,4 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y CONFIG_USB=y CONFIG_DM_USB=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -- cgit v0.10.2 From aa2ba829257a29bb38e47b51b3e40ad68e92d773 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:28 +0800 Subject: arm: socfpga: arria5: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS for UBI and UBIFS support on serial NOR flash Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index a9f9ea3..68d12df 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -24,3 +24,4 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y CONFIG_USB=y CONFIG_DM_USB=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -- cgit v0.10.2 From 0645c773156c432c2fac579290d52e7962f815bc Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:30 +0800 Subject: arm: socfpga: sr1500: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS for UBI and UBIFS support on serial NOR flash Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 2c75bda..3d98a63 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -17,3 +17,4 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_DM_MMC=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -- cgit v0.10.2 From dc93280d3e557f92d86fd2913405e8e30318c2ec Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:31 +0800 Subject: arm: socfpga: cyclone5_socdk: Enable ubiload console command Enabling ubiload command to load kernel image and device tree from mtd part labeled "UBI". ubiload command will search the file from directory /boot. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 3c2e2ae..72a3cef 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -74,7 +74,10 @@ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* The rest of the configuration is shared */ #include -- cgit v0.10.2 From c26112a73de78b494436061f832874e7a521b067 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:32 +0800 Subject: arm: socfpga: arria5_socdk: Enable ubiload console command Enabling ubiload command to load kernel image and device tree from mtd part labeled "UBI". ubiload command will search the file from directory /boot. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index af0f87f..5c21aec 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -74,7 +74,10 @@ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* The rest of the configuration is shared */ #include -- cgit v0.10.2 From 3e8a075d6e56b6b2268a6a165aa344afe9447a40 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:33 +0800 Subject: arm: socfpga: sockit: Enable ubiload console command Enabling ubiload command to load kernel image and device tree from mtd part labeled "UBI". ubiload command will search the file from directory /boot. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 2356c74..c60dca4 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -66,6 +66,9 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* The rest of the configuration is shared */ #include -- cgit v0.10.2 From eb45022c4c798388c89bb2ca4735ae58e3f9d436 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:34 +0800 Subject: arm: socfpga: sr1500: Enable ubiload console command Enabling ubiload command to load kernel image and device tree from mtd part labeled "UBI". ubiload command will search the file from directory /boot. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index 5bd2956..f37d005 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -74,7 +74,10 @@ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* Environment */ #define CONFIG_ENV_IS_IN_SPI_FLASH -- cgit v0.10.2 From d9f2bd4096e6d63cb4fb62a32dd4e7d200c22b42 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:35 +0800 Subject: arm: socfpga: cyclone5_socdk: Enable qspiload console command Enabling qspiload command which will load the kernel image and dtb from UBIFS within MTD partition labeled UBI. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 72a3cef..0ed7f42 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -70,6 +70,7 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ "qspiroot=/dev/mtdblock0\0" \ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ -- cgit v0.10.2 From f8e08b8f2ea3e45c1dc906ea2a8a9791e2e8e07c Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:36 +0800 Subject: arm: socfpga: arria5_socdk: Enable qspiload console command Enabling qspiload command which will load the kernel image and dtb from UBIFS within MTD partition labeled UBI. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 5c21aec..d3009a4 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -70,6 +70,7 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ "qspiroot=/dev/mtdblock0\0" \ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ -- cgit v0.10.2 From 8ee0c6486597342011ef1c2ba95dce0b0cf01cb5 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:37 +0800 Subject: arm: socfpga: sockit: Enable qspiload console command Enabling qspiload command which will load the kernel image and dtb from UBIFS within MTD partition labeled UBI. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index c60dca4..39f0b09 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -66,6 +66,7 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ "ubiload=ubi part UBI && ubifsmount ubi0 && " \ "ubifsload ${loadaddr} /boot/${bootimage} && " \ "ubifsload ${fdt_addr} /boot/${fdtimage}\0" -- cgit v0.10.2 From b3bb1110cf8d2c43f15841151af0d560dc74c7b8 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:38 +0800 Subject: arm: socfpga: sr1500: Enable qspiload console command Enabling qspiload command which will load the kernel image and dtb from UBIFS within MTD partition labeled UBI. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index f37d005..0ebea13 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -70,6 +70,7 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ "qspiroot=/dev/mtdblock0\0" \ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ -- cgit v0.10.2 From 0f28b1a404651dbc51d8b7bb07a4bfe78e51f96c Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:39 +0800 Subject: arm: socfpga: cyclone5_socdk: Update qspiboot to use UBIFS Update the qspiboot console command to use UBIFS instead of old jffs2 file system. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 0ed7f42..c4c4ecb 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -71,11 +71,9 @@ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ "qspiload=sf probe && mtdparts default && run ubiload\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" \ + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ "ubiload=ubi part UBI && ubifsmount ubi0 && " \ "ubifsload ${loadaddr} /boot/${bootimage} && " \ "ubifsload ${fdt_addr} /boot/${fdtimage}\0" -- cgit v0.10.2 From d6d55cdeca49dc37e41b080e0a34431424925e88 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:40 +0800 Subject: arm: socfpga: arria5_socdk: Update qspiboot to use UBIFS Update the qspiboot console command to use UBIFS instead of old jffs2 file system. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index d3009a4..a0161bc 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -71,11 +71,9 @@ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ "qspiload=sf probe && mtdparts default && run ubiload\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" \ + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ "ubiload=ubi part UBI && ubifsmount ubi0 && " \ "ubifsload ${loadaddr} /boot/${bootimage} && " \ "ubifsload ${fdt_addr} /boot/${fdtimage}\0" -- cgit v0.10.2 From 5abbdfadbe8ded75e240de693794c96e214b561b Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:41 +0800 Subject: arm: socfpga: sockit: Update qspiboot to use UBIFS Update the qspiboot console command to use UBIFS instead of old jffs2 file system. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 39f0b09..95e7ba6 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -67,6 +67,9 @@ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ "qspiload=sf probe && mtdparts default && run ubiload\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ "ubiload=ubi part UBI && ubifsmount ubi0 && " \ "ubifsload ${loadaddr} /boot/${bootimage} && " \ "ubifsload ${fdt_addr} /boot/${fdtimage}\0" -- cgit v0.10.2 From 94f53a7ddfaf9af844121e3437031a07297c478e Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 22 Dec 2015 15:32:42 +0800 Subject: arm: socfpga: sr1500: Update qspiboot to use UBIFS Update the qspiboot console command to use UBIFS instead of old jffs2 file system. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index 0ebea13..fdf67ca 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -71,11 +71,9 @@ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ "qspiload=sf probe && mtdparts default && run ubiload\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" \ + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ "ubiload=ubi part UBI && ubifsmount ubi0 && " \ "ubifsload ${loadaddr} /boot/${bootimage} && " \ "ubifsload ${fdt_addr} /boot/${fdtimage}\0" -- cgit v0.10.2 From b0808b912d3f728597afcb97545d89b9f34dbc3f Mon Sep 17 00:00:00 2001 From: shengjiangwu Date: Tue, 22 Dec 2015 15:22:02 +0800 Subject: arm: socfpga: Fix emac1 doesn't work on socdk board Updated pinmux group MIXED1IO[0-13] for RGMII1. Updated EMAC1 clock. Signed-off-by: shengjiangwu Cc: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 33cf1fd..442b1e0 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO29 */ 0, /* GENERALIO30 */ 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 1, /* MIXED1IO1 */ - 1, /* MIXED1IO2 */ - 1, /* MIXED1IO3 */ - 1, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 1, /* MIXED1IO8 */ - 1, /* MIXED1IO9 */ - 1, /* MIXED1IO10 */ - 1, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ 1, /* MIXED1IO15 */ 1, /* MIXED1IO16 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 3d621ed..9e336e3 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -31,7 +31,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -- cgit v0.10.2 From caee45ecc32329294d0f42a54b5c47794ecbe750 Mon Sep 17 00:00:00 2001 From: shengjiangwu Date: Tue, 22 Dec 2015 17:18:09 +0800 Subject: arm: socfpga: Fix QSPI doesn't work on socdk board Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock. Signed-off-by: shengjiangwu Cc: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 442b1e0..06783dc 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = { 2, /* MIXED1IO12 */ 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ 0, /* MIXED1IO21 */ 0, /* MIXED2IO0 */ 0, /* MIXED2IO1 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 9e336e3..4abd2e0 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -14,7 +14,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -- cgit v0.10.2 From f2f3782eadc7a958b0d33e9746640b874b5eefcc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Dec 2015 04:00:41 +0100 Subject: arm: socfpga: Define NAND reset bit Define the NAND reset bit and fix the ordering of the macros. Signed-off-by: Marek Vasut Cc: Dinh Nguyen diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index e50fbd8..2f070f2 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -65,12 +65,13 @@ struct socfpga_reset_manager { */ #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) -- cgit v0.10.2 From ac242e16258c943f6d2e0dd10898e4cc6a6339ca Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Dec 2015 04:00:42 +0100 Subject: arm: socfpga: Unreset NAND in SPL If the system boots from NAND, make sure to de-assert the NAND IP reset, otherwise the system will get stuck. Signed-off-by: Marek Vasut Cc: Dinh Nguyen diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 775a827..98c16a0 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -40,6 +40,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ -- cgit v0.10.2 From 8f7ed08eb35e7c9660ee7c0bd3df5661ee9a2638 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Dec 2015 04:00:43 +0100 Subject: arm: socfpga: Unreset NAND in U-Boot Make sure the NAND reset is not asserted in full U-Boot. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index a54d2b9..9b43b92 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -359,6 +359,10 @@ int arch_early_init_r(void) socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); #endif +#ifdef CONFIG_NAND_DENALI + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); +#endif + return 0; } -- cgit v0.10.2 From 4197a0f45b655c00eae738ddecee2a1009e972a3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Dec 2015 04:00:44 +0100 Subject: arm: socfpga: Enable SPL MMC/SPI support only if DM_MMC/SPI is enabled It is not possible to compile MMC/SPI SPL if the respective DM_MMC/DM_SPI bits are not enabled. Secure the code with an ifdef to prevent compiler splat. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 35e4a75..ff7a300 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -330,8 +330,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_DM_MMC #define CONFIG_SPL_MMC_SUPPORT +#endif +#ifdef CONFIG_DM_SPI #define CONFIG_SPL_SPI_SUPPORT +#endif /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT -- cgit v0.10.2 From eba522a0f7e0bae819633977aa9ad905775a1b68 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Dec 2015 04:00:45 +0100 Subject: arm: socfpga: Enable DFU MMC support only if DM_MMC is enabled It is not possible to compile DFU MMC support if the MMC support is not compiled into U-Boot. Secure the code with an ifdef to prevent compiler splat. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index ff7a300..2d1765d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -248,7 +248,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_FUNCTION_DFU +#ifdef CONFIG_DM_MMC #define CONFIG_DFU_MMC +#endif #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) #define DFU_DEFAULT_POLL_TIMEOUT 300 -- cgit v0.10.2 From c339ea5bfe7129ac0e832df253df855c1e73cc84 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Dec 2015 04:00:46 +0100 Subject: arm: socfpga: Add support for Denali NAND controller Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 2d1765d..a09e906 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -161,6 +161,19 @@ #endif /* + * NAND Support + */ +#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_DENALI_ECC_SIZE 512 +#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS +#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) +#endif + +/* * I2C support */ #define CONFIG_SYS_I2C @@ -338,6 +351,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #ifdef CONFIG_DM_SPI #define CONFIG_SPL_SPI_SUPPORT #endif +#ifdef CONFIG_SPL_NAND_DENALI +#define CONFIG_SPL_NAND_SUPPORT +#endif /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT @@ -360,6 +376,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif +/* SPL NAND boot support */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#endif + /* * Stack setup */ -- cgit v0.10.2 From f464a631426a30ffcbf2d7f732e678df1b684be8 Mon Sep 17 00:00:00 2001 From: shengjiangwu Date: Wed, 23 Dec 2015 10:37:31 +0800 Subject: arm: socfpga: Fix USB doesn't work on socdk board Updated pinmux group EMACIO[1-8] and EMACIO[10-13] for USB. Signed-off-by: shengjiangwu Cc: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 06783dc..7819ad0 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -9,19 +9,19 @@ const u8 sys_mgr_init_table[] = { 3, /* EMACIO0 */ - 3, /* EMACIO1 */ - 3, /* EMACIO2 */ - 3, /* EMACIO3 */ - 3, /* EMACIO4 */ - 3, /* EMACIO5 */ - 3, /* EMACIO6 */ - 3, /* EMACIO7 */ - 3, /* EMACIO8 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ 3, /* EMACIO9 */ - 3, /* EMACIO10 */ - 3, /* EMACIO11 */ - 3, /* EMACIO12 */ - 3, /* EMACIO13 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ 0, /* EMACIO14 */ 0, /* EMACIO15 */ 0, /* EMACIO16 */ -- cgit v0.10.2 From e662573822d24dcdc079d29ff397cb8bacf97b27 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Wed, 23 Dec 2015 22:07:49 +0800 Subject: arm: socfpga: Fix i2c mux on cyclone5-socdk board Updated pinmux group GENERALIO[15-16] for i2c. Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Pavel Machek Cc: Marek Vasut Cc: Stefan Roese Cc: shengjiangwu diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 7819ad0..f1e6d2b 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -55,8 +55,8 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO12 */ 2, /* GENERALIO13 */ 2, /* GENERALIO14 */ - 0, /* GENERALIO15 */ - 0, /* GENERALIO16 */ + 3, /* GENERALIO15 */ + 3, /* GENERALIO16 */ 2, /* GENERALIO17 */ 2, /* GENERALIO18 */ 0, /* GENERALIO19 */ -- cgit v0.10.2