From 8318fbf8cc30418b621ea9f39b84b4c1a08f003a Mon Sep 17 00:00:00 2001
From: Marian Balakowicz <m8@semihalf.com>
Date: Mon, 23 Oct 2006 22:17:05 +0200
Subject: Fix sequoia separate object direcory building problems.


diff --git a/CHANGELOG b/CHANGELOG
index 727a7b6..ed6396d 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes for U-Boot 1.1.5:
 ======================================================================
 
+* Fix sequoia separate object direcory building problems.
+
 * Cleanup compile warnings. Prepare for release 1.1.5
 
 * Fix compile problem in include/configs/ep82xxm.h
diff --git a/Makefile b/Makefile
index 9203494..e6d044a 100644
--- a/Makefile
+++ b/Makefile
@@ -269,10 +269,10 @@ $(SUBDIRS):
 		$(MAKE) -C $@ all
 
 $(NAND_SPL):	version
-		$(MAKE) -C nand_spl all
+		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
 
 $(U_BOOT_NAND):	$(NAND_SPL) $(obj)u-boot.bin
-		cat nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
+		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
 
 version:
 		@echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
@@ -1146,19 +1146,22 @@ PPChameleonEVB_HI_33_config:	unconfig
 	@$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
 
 rainier_config:	unconfig
-	@echo "#define CONFIG_RAINIER" > include/config.h
+	@mkdir -p $(obj)include
+	@echo "#define CONFIG_RAINIER" > $(obj)include/config.h
 	@echo "Configuring for rainier board as subset of sequoia..."
 	@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
 
 rainier_nand_config:	unconfig
-	@echo "#define CONFIG_RAINIER" > include/config.h
+	@mkdir -p $(obj)include
+	@mkdir -p $(obj)nand_spl
+	@mkdir -p $(obj)board/amcc/sequoia
+	@echo "#define CONFIG_RAINIER" > $(obj)include/config.h
 	@echo "Configuring for rainier board as subset of sequoia..."
-	@ln -s board/amcc/sequoia/Makefile nand_spl/Makefile
-	@echo "#define CONFIG_NAND_U_BOOT" >> include/config.h
+	@echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h
 	@echo "Compile NAND boot image for sequoia"
 	@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
-	@echo "TEXT_BASE = 0x01000000" >board/amcc/sequoia/config.tmp
-	@echo "CONFIG_NAND_U_BOOT = y" >> include/config.mk
+	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
+	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
 
 sbc405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
@@ -1167,12 +1170,14 @@ sequoia_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx sequoia amcc
 
 sequoia_nand_config:	unconfig
-	@ln -s board/amcc/sequoia/Makefile nand_spl/Makefile
-	@echo "#define CONFIG_NAND_U_BOOT" >include/config.h
+	@mkdir -p $(obj)include
+	@mkdir -p $(obj)nand_spl
+	@mkdir -p $(obj)board/amcc/sequoia
+	@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
 	@echo "Compile NAND boot image for sequoia"
 	@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
-	@echo "TEXT_BASE = 0x01000000" >board/amcc/sequoia/config.tmp
-	@echo "CONFIG_NAND_U_BOOT = y" >> include/config.mk
+	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
+	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
 
 sycamore_config:	unconfig
 	@echo "Configuring for sycamore board as subset of walnut..."
@@ -2244,8 +2249,7 @@ clean:
 	rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
 	rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
 	rm -f $(obj)include/bmp_logo.h
-	find nand_spl -lname "*" -print | xargs rm -f
-	rm -f nand_spl/u-boot-spl nand_spl/u-boot-spl.map
+	rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
 
 clobber:	clean
 	find $(OBJTREE) -type f \( -name .depend \
@@ -2258,6 +2262,7 @@ clobber:	clean
 	rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c
 	rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
 	rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
+	[ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
 
 ifeq ($(OBJTREE),$(SRCTREE))
 mrproper \
diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile
index 9c1be0e..06ef7f9 100644
--- a/board/amcc/sequoia/Makefile
+++ b/board/amcc/sequoia/Makefile
@@ -22,7 +22,6 @@
 #
 
 include $(TOPDIR)/config.mk
-include $(TOPDIR)/include/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk
index 7713a72..e62b8d3 100644
--- a/board/amcc/sequoia/config.mk
+++ b/board/amcc/sequoia/config.mk
@@ -24,7 +24,7 @@
 # AMCC 440EPx Reference Platform (Sequoia) board
 #
 
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
 
 ifndef TEXT_BASE
 TEXT_BASE = 0xFFFA0000
diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile
index 897aa8b..a71f583 100644
--- a/nand_spl/board/amcc/sequoia/Makefile
+++ b/nand_spl/board/amcc/sequoia/Makefile
@@ -22,9 +22,9 @@
 #
 
 include $(TOPDIR)/config.mk
-include board/$(BOARDDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
 
-LDSCRIPT= board/$(BOARDDIR)/u-boot.lds
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
 LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
 AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
@@ -32,49 +32,65 @@ CFLAGS	+= -DCONFIG_NAND_SPL
 SOBJS	= start.o init.o resetvec.o
 COBJS	= nand_boot.o ndfc.o sdram.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
 
-ALL	= u-boot-spl u-boot-spl.bin u-boot-spl-16k.bin
+nandobj	:= $(OBJTREE)/nand_spl/
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
 
 all:	$(obj).depend $(ALL)
 
-u-boot-spl-16k.bin: u-boot-spl
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
 	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
 
-u-boot-spl.bin:	u-boot-spl
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
 	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
 
-u-boot-spl:	$(OBJS)
-	$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
-		-Map u-boot-spl.map -o u-boot-spl
+$(nandobj)u-boot-spl:	$(OBJS)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $(nandobj)u-boot-spl
 
 # create symbolic links for common files
 
 # from cpu directory
-ndfc.c:
-	@rm -f ndfc.c
-	ln -s ../cpu/ppc4xx/ndfc.c ndfc.c
+$(obj)ndfc.c:
+	@rm -f $(obj)ndfc.c
+	ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
 
-resetvec.S:
-	@rm -f resetvec.S
-	ln -s ../cpu/ppc4xx/resetvec.S resetvec.S
+$(obj)resetvec.S:
+	@rm -f $(obj)resetvec.S
+	ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
 
-start.S:
-	@rm -f start.S
-	ln -s ../cpu/ppc4xx/start.S start.S
+$(obj)start.S:
+	@rm -f $(obj)start.S
+	ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
 
 # from board directory
-init.S:
-	@rm -f init.S
-	ln -s ../board/amcc/sequoia/init.S init.S
+$(obj)init.S:
+	@rm -f $(obj)init.S
+	ln -s $(SRCTREE)/board/amcc/sequoia/init.S $(obj)init.S
+
+$(obj)sdram.c:
+	@rm -f $(obj)sdram.c
+	ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c
 
-sdram.c:
-	@rm -f sdram.c
-	ln -s ../board/amcc/sequoia/sdram.c sdram.c
+# from nand_spl directory
+$(obj)nand_boot.c:
+	@rm -f $(obj)nand_boot.c
+	ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
 
 #########################################################################
 
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
 # defines $(obj).depend target
 include $(SRCTREE)/rules.mk
 
-- 
cgit v0.10.2


From 965829872169c2996023840d98e1d85ad148d629 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue, 24 Oct 2006 13:55:18 +0200
Subject: Fix/workaround broken dependency handling with make 3.81 Based on
 patch by Haavard Skinnemoen, 29 Aug 2006 11:20:39 +0200


diff --git a/examples/Makefile b/examples/Makefile
index 8706ed4..680fe75 100644
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -59,51 +59,60 @@ endif
 
 include $(TOPDIR)/config.mk
 
+ELF	= hello_world
 SREC	= hello_world.srec
-BIN	= hello_world.bin hello_world
+BIN	= hello_world.bin
 
 ifeq ($(CPU),mpc8xx)
+ELF	= test_burst
 SREC	= test_burst.srec
-BIN	= test_burst.bin test_burst
+BIN	= test_burst.bin
 endif
 
 ifeq ($(ARCH),i386)
-SREC   += 82559_eeprom.srec
-BIN    += 82559_eeprom.bin 82559_eeprom
+ELF	+= 82559_eeprom
+SREC	+= 82559_eeprom.srec
+BIN	+= 82559_eeprom.bin
 endif
 
 ifeq ($(ARCH),ppc)
-SREC   += sched.srec
-BIN    += sched.bin sched
+ELF	+= sched
+SREC	+= sched.srec
+BIN	+= sched.bin
 endif
 
 ifeq ($(ARCH),blackfin)
+ELF	+= smc91111_eeprom
 SREC	+= smc91111_eeprom.srec
-BIN 	+= smc91111_eeprom.bin smc91111_eeprom
+BIN 	+= smc91111_eeprom.bin
 endif
 
 # The following example is pretty 8xx specific...
 ifeq ($(CPU),mpc8xx)
-SREC   += timer.srec
-BIN    += timer.bin timer
+ELF	+= timer
+SREC	+= timer.srec
+BIN	+= timer.bin
 endif
 
 # The following example is 8260 specific...
 ifeq ($(CPU),mpc8260)
-SREC   += mem_to_mem_idma2intr.srec
-BIN    += mem_to_mem_idma2intr.bin mem_to_mem_idma2intr
+ELF	+= mem_to_mem_idma2intr
+SREC	+= mem_to_mem_idma2intr.srec
+BIN	+= mem_to_mem_idma2intr.bin
 endif
 
 # Demo for 52xx IRQs
 ifeq ($(CPU),mpc5xxx)
-SREC   += interrupt.srec
-BIN    += interrupt.bin interrupt
+ELF	+= interrupt
+SREC	+= interrupt.srec
+BIN	+= interrupt.bin
 endif
 
 # Utility for resetting i82559 EEPROM
 ifeq ($(BOARD),oxc)
-SREC   += eepro100_eeprom.srec
-BIN    += eepro100_eeprom.bin eepro100_eeprom
+ELF	+= eepro100_eeprom
+SREC	+= eepro100_eeprom.srec
+BIN	+= eepro100_eeprom.bin
 endif
 
 ifeq ($(BIG_ENDIAN),y)
@@ -126,6 +135,7 @@ LIBOBJS	= $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS))
 
 SRCS	:= $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(if $(LIBAOBJS),$(LIBAOBJS:.o=.S))
 OBJS	:= $(addprefix $(obj),$(COBJS))
+ELF	:= $(addprefix $(obj),$(ELF))
 BIN	:= $(addprefix $(obj),$(BIN))
 SREC	:= $(addprefix $(obj),$(SREC))
 
@@ -134,19 +144,23 @@ clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`)
 
 CPPFLAGS += -I..
 
-all:	$(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN)
+all:	$(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF)
 
 #########################################################################
 $(LIB):	$(obj).depend $(LIBOBJS)
 		$(AR) $(ARFLAGS) $@ $(LIBOBJS)
 
+$(ELF):
 $(obj)%:	$(obj)%.o $(LIB)
 		$(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \
 			-o $@ -e $(notdir $(<:.o=)) $< $(LIB) \
 			-L$(gcclibdir) -lgcc
+
+$(SREC):
 $(obj)%.srec:	$(obj)%
 		$(OBJCOPY) -O srec $< $@ 2>/dev/null
 
+$(BIN):
 $(obj)%.bin:	$(obj)%
 		$(OBJCOPY) -O binary $< $@ 2>/dev/null
 
-- 
cgit v0.10.2


From 2da2d9a4766063b9848f3a35ad6025499cf87265 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue, 24 Oct 2006 13:57:33 +0200
Subject: Use -g instead of -gstabs in AFLAGS_DEBUG Patch by Haavard
 Skinnemoen, 30 Aug 2006

In config.mk, -Wa,-gstabs is unconditionally appended to AFLAGS no
matter what the target's preferred debugging format is. This patch
simply replaces -gstabs with -g, so that the default debugging format
for the architecture is used.

diff --git a/config.mk b/config.mk
index d32f51e..46e956f 100644
--- a/config.mk
+++ b/config.mk
@@ -169,7 +169,7 @@ CFLAGS := $(CPPFLAGS) -Wall -Wno-trigraphs
 endif
 endif
 
-AFLAGS_DEBUG := -Wa,-gstabs
+AFLAGS_DEBUG := -Wa,-g
 
 # turn jbsr into jsr for m68k
 ifeq ($(ARCH),m68k)
-- 
cgit v0.10.2


From 7b64fef33c66be648826c0ff9758298ef13d0604 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue, 24 Oct 2006 14:21:16 +0200
Subject: Add AVR32 architecture support Patch by Haavard Skinnemoen, 6 Sep
 2006 16:23:02 +0200

This patch adds common infrastructure code for the Atmel AVR32
architecture. See doc/README.AVR32 for details.

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 4262719..d7ef203 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -555,5 +555,12 @@ Zachary P. Landau <zachary.landau@labxtechnologies.com>
 	r5200			mcf52x2
 
 #########################################################################
+# AVR32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+#########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/Makefile b/Makefile
index 9203494..5260a61 100644
--- a/Makefile
+++ b/Makefile
@@ -152,6 +152,9 @@ endif
 ifeq ($(ARCH),blackfin)
 CROSS_COMPILE = bfin-elf-
 endif
+ifeq ($(ARCH),avr32)
+CROSS_COMPILE = avr32-
+endif
 endif
 endif
 
@@ -2099,6 +2102,10 @@ pb1000_config		: 	unconfig
 	@echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h
 	@$(MKCONFIG) -a pb1x00 mips mips pb1x00
 
+#========================================================================
+# AVR32
+#========================================================================
+
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################
diff --git a/README b/README
index a0949f0..8405a9b 100644
--- a/README
+++ b/README
@@ -156,6 +156,7 @@ Directory Hierarchy:
 - examples	Example code for standalone applications, etc.
 - include	Header Files
 - lib_arm	Files generic to ARM	 architecture
+- lib_avr32	Files generic to AVR32	 architecture
 - lib_generic	Files generic to all	 architectures
 - lib_i386	Files generic to i386	 architecture
 - lib_m68k	Files generic to m68k	 architecture
@@ -2722,9 +2723,9 @@ defines the following image properties:
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
   LynxOS, pSOS, QNX, RTEMS, ARTOS;
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS).
-* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
+* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
   IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, Intel x86, MIPS, NIOS, PowerPC).
+  Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
diff --git a/avr32_config.mk b/avr32_config.mk
new file mode 100644
index 0000000..0b92053
--- /dev/null
+++ b/avr32_config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS	+= -ffixed-r5 -mno-pic -mrelax
+PLATFORM_LDFLAGS	+= --relax
diff --git a/doc/README.AVR32 b/doc/README.AVR32
new file mode 100644
index 0000000..abec872
--- /dev/null
+++ b/doc/README.AVR32
@@ -0,0 +1,33 @@
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Wed, 30 Aug 2006 17:01:46 +0200
+Subject: [PATCH] AVR32 architecture support
+
+This patch adds common infrastructure code for the Atmel AVR32
+architecture.
+
+AVR32 is a new high-performance 32-bit RISC microprocessor core,
+designed for cost-sensitive embedded applications, with particular
+emphasis on low power consumption and high code density. The AVR32
+architecture is not binary compatible with earlier 8-bit AVR
+architectures.
+
+The AVR32 architecture, including the instruction set, is described
+by the AVR32 Architecture Manual, available from
+
+http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
+
+A GNU toolchain with support for AVR32 is included with the ATSTK1000
+BSP, which can be downloaded as an ISO image from
+
+http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918
+
+Alternatively, you can build it yourself by following the
+Getting Started guide at avr32linux.org, which also provides links
+to the necessary sources and patches you need to download:
+
+http://avr32linux.org/twiki/bin/view/Main/GettingStarted
+
+The AVR32 ports of u-boot, the Linux kernel, the GNU toolchain and
+other associated software are actively supported by Atmel Corporation.
+
+Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
diff --git a/examples/Makefile b/examples/Makefile
index 680fe75..423a79b 100644
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -57,6 +57,10 @@ ifeq ($(ARCH),blackfin)
 LOAD_ADDR = 0x1000
 endif
 
+ifeq ($(ARCH),avr32)
+LOAD_ADDR = 0x00000000
+endif
+
 include $(TOPDIR)/config.mk
 
 ELF	= hello_world
diff --git a/examples/stubs.c b/examples/stubs.c
index 1caa575..ffd314e 100644
--- a/examples/stubs.c
+++ b/examples/stubs.c
@@ -138,6 +138,19 @@ gd_t *global_data;
 "	P0 = [P0 + %1]\n"		\
 "	JUMP (P0)\n"			\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0");
+#elif defined(CONFIG_AVR32)
+/*
+ * r6 holds the pointer to the global_data. r8 is call clobbered.
+ */
+#define EXPORT_FUNC(x)					\
+	asm volatile(					\
+		"	.globl\t" #x "\n"		\
+		#x ":\n"				\
+		"	ld.w	r8, r6[%0]\n"		\
+		"	ld.w	pc, r8[%1]\n"		\
+		:					\
+		: "i"(offsetof(gd_t, jt)), "i"(XF_ ##x)	\
+		: "r8");
 #else
 #error stubs definition missing for this architecture
 #endif
diff --git a/include/asm-avr32/addrspace.h b/include/asm-avr32/addrspace.h
new file mode 100644
index 0000000..b2ba1ee
--- /dev/null
+++ b/include/asm-avr32/addrspace.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ADDRSPACE_H
+#define __ASM_AVR32_ADDRSPACE_H
+
+/* Memory segments when segmentation is enabled */
+#define P0SEG		0x00000000
+#define P1SEG		0x80000000
+#define P2SEG		0xa0000000
+#define P3SEG		0xc0000000
+#define P4SEG		0xe0000000
+
+/* Returns the privileged segment base of a given address */
+#define PXSEG(a)	(((unsigned long)(a)) & 0xe0000000)
+
+/* Returns the physical address of a PnSEG (n=1,2) address */
+#define PHYSADDR(a)	(((unsigned long)(a)) & 0x1fffffff)
+
+/*
+ * Map an address to a certain privileged segment
+ */
+#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
+#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
+#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
+#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
+
+#endif /* __ASM_AVR32_ADDRSPACE_H */
diff --git a/include/asm-avr32/bitops.h b/include/asm-avr32/bitops.h
new file mode 100644
index 0000000..f15fd46
--- /dev/null
+++ b/include/asm-avr32/bitops.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_BITOPS_H
+#define __ASM_AVR32_BITOPS_H
+
+#endif /* __ASM_AVR32_BITOPS_H */
diff --git a/include/asm-avr32/byteorder.h b/include/asm-avr32/byteorder.h
new file mode 100644
index 0000000..2fe867e
--- /dev/null
+++ b/include/asm-avr32/byteorder.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_BYTEORDER_H
+#define __ASM_AVR32_BYTEORDER_H
+
+#include <asm/types.h>
+
+#define __arch__swab32(x) __builtin_bswap_32(x)
+#define __arch__swab16(x) __builtin_bswap_16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* __ASM_AVR32_BYTEORDER_H */
diff --git a/include/asm-avr32/cacheflush.h b/include/asm-avr32/cacheflush.h
new file mode 100644
index 0000000..929f68e
--- /dev/null
+++ b/include/asm-avr32/cacheflush.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_CACHEFLUSH_H
+#define __ASM_AVR32_CACHEFLUSH_H
+
+/*
+ * Invalidate any cacheline containing virtual address vaddr without
+ * writing anything back to memory.
+ *
+ * Note that this function may corrupt unrelated data structures when
+ * applied on buffers that are not cacheline aligned in both ends.
+ */
+static inline void dcache_invalidate_line(volatile void *vaddr)
+{
+	asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Make sure any cacheline containing virtual address vaddr is written
+ * to memory.
+ */
+static inline void dcache_clean_line(volatile void *vaddr)
+{
+	asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Make sure any cacheline containing virtual address vaddr is written
+ * to memory and then invalidate it.
+ */
+static inline void dcache_flush_line(volatile void *vaddr)
+{
+	asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Invalidate any instruction cacheline containing virtual address
+ * vaddr.
+ */
+static inline void icache_invalidate_line(volatile void *vaddr)
+{
+	asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Applies the above functions on all lines that are touched by the
+ * specified virtual address range.
+ */
+void dcache_invalidate_range(volatile void *start, size_t len);
+void dcache_clean_range(volatile void *start, size_t len);
+void dcache_flush_range(volatile void *start, size_t len);
+void icache_invalidate_range(volatile void *start, size_t len);
+
+static inline void dcache_flush_unlocked(void)
+{
+	asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory");
+}
+
+/*
+ * Make sure any pending writes are completed before continuing.
+ */
+#define sync_write_buffer() asm volatile("sync 0" : : : "memory")
+
+#endif /* __ASM_AVR32_CACHEFLUSH_H */
diff --git a/include/asm-avr32/div64.h b/include/asm-avr32/div64.h
new file mode 100644
index 0000000..2e0ba83
--- /dev/null
+++ b/include/asm-avr32/div64.h
@@ -0,0 +1,39 @@
+#ifndef _ASM_GENERIC_DIV64_H
+#define _ASM_GENERIC_DIV64_H
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ * 	uint32_t remainder = *n % base;
+ * 	*n = *n / base;
+ * 	return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ *       beware of side effects!
+ */
+
+#include <linux/types.h>
+
+extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
+
+/* The unnecessary pointer compare is there
+ * to check for type safety (n must be 64bit)
+ */
+# define do_div(n,base) ({				\
+	uint32_t __base = (base);			\
+	uint32_t __rem;					\
+	(void)(((typeof((n)) *)0) == ((uint64_t *)0));	\
+	if (((n) >> 32) == 0) {			\
+		__rem = (uint32_t)(n) % __base;		\
+		(n) = (uint32_t)(n) / __base;		\
+	} else 						\
+		__rem = __div64_32(&(n), __base);	\
+	__rem;						\
+ })
+
+#endif /* _ASM_GENERIC_DIV64_H */
diff --git a/include/asm-avr32/dma-mapping.h b/include/asm-avr32/dma-mapping.h
new file mode 100644
index 0000000..3b46fa3
--- /dev/null
+++ b/include/asm-avr32/dma-mapping.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_DMA_MAPPING_H
+#define __ASM_AVR32_DMA_MAPPING_H
+
+#include <asm/io.h>
+#include <asm/cacheflush.h>
+
+enum dma_data_direction {
+	DMA_BIDIRECTIONAL	= 0,
+	DMA_TO_DEVICE		= 1,
+	DMA_FROM_DEVICE		= 2,
+};
+extern void *dma_alloc_coherent(size_t len, unsigned long *handle);
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+					   enum dma_data_direction dir)
+{
+	extern void __bad_dma_data_direction(void);
+
+	switch (dir) {
+	case DMA_BIDIRECTIONAL:
+		dcache_flush_range(vaddr, len);
+		break;
+	case DMA_TO_DEVICE:
+		dcache_clean_range(vaddr, len);
+		break;
+	case DMA_FROM_DEVICE:
+		dcache_invalidate_range(vaddr, len);
+		break;
+	default:
+		/* This will cause a linker error */
+		__bad_dma_data_direction();
+	}
+
+	return virt_to_phys(vaddr);
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+				    unsigned long paddr)
+{
+
+}
+
+#endif /* __ASM_AVR32_DMA_MAPPING_H */
diff --git a/include/asm-avr32/errno.h b/include/asm-avr32/errno.h
new file mode 100644
index 0000000..ea3506f
--- /dev/null
+++ b/include/asm-avr32/errno.h
@@ -0,0 +1,132 @@
+#ifndef _ASM_AVR32_ERRNO_H
+#define _ASM_AVR32_ERRNO_H
+
+#define	EPERM		 1	/* Operation not permitted */
+#define	ENOENT		 2	/* No such file or directory */
+#define	ESRCH		 3	/* No such process */
+#define	EINTR		 4	/* Interrupted system call */
+#define	EIO		 5	/* I/O error */
+#define	ENXIO		 6	/* No such device or address */
+#define	E2BIG		 7	/* Argument list too long */
+#define	ENOEXEC		 8	/* Exec format error */
+#define	EBADF		 9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+
+#define	EDEADLOCK	EDEADLK
+
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+#endif /* _ASM_AVR32_ERRNO_H */
diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h
new file mode 100644
index 0000000..01d836c
--- /dev/null
+++ b/include/asm-avr32/global_data.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_GLOBAL_DATA_H__
+#define __ASM_GLOBAL_DATA_H__
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct	global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	const struct device	*console_uart;
+	const struct device	*sm;
+	unsigned long	baudrate;
+	unsigned long	sdram_size;
+	unsigned long	have_console;	/* serial_init() was called */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address of env struct */
+	unsigned long	env_valid;	/* Checksum of env valid? */
+	unsigned long	cpu_hz;		/* cpu core clock frequency */
+	void		**jt;		/* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define GD_FLG_RELOC	0x00001		/* Code was relocated to RAM	 */
+#define GD_FLG_DEVINIT	0x00002		/* Devices have been initialized */
+#define GD_FLG_SILENT	0x00004		/* Silent mode			 */
+
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
+
+#endif /* __ASM_GLOBAL_DATA_H__ */
diff --git a/include/asm-avr32/initcalls.h b/include/asm-avr32/initcalls.h
new file mode 100644
index 0000000..7ba25cd
--- /dev/null
+++ b/include/asm-avr32/initcalls.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2005, 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_INITCALLS_H__
+#define __ASM_AVR32_INITCALLS_H__
+
+#include <config.h>
+
+extern int cpu_init(void);
+extern int timer_init(void);
+extern void board_init_memories(void);
+extern void board_init_pio(void);
+extern void board_init_info(void);
+
+#endif /* __ASM_AVR32_INITCALLS_H__ */
diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h
new file mode 100644
index 0000000..e86c456
--- /dev/null
+++ b/include/asm-avr32/io.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_IO_H
+#define __ASM_AVR32_IO_H
+
+#ifdef __KERNEL__
+
+/*
+ * Generic IO read/write.  These perform native-endian accesses.  Note
+ * that some architectures will want to re-define __raw_{read,write}w.
+ */
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v,a)       (*(volatile unsigned char  *)(a) = (v))
+#define __raw_writew(v,a)       (*(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a)       (*(volatile unsigned int   *)(a) = (v))
+
+#define __raw_readb(a)          (*(volatile unsigned char  *)(a))
+#define __raw_readw(a)          (*(volatile unsigned short *)(a))
+#define __raw_readl(a)          (*(volatile unsigned int   *)(a))
+
+/* As long as I/O is only performed in P4 (or possibly P3), we're safe */
+#define writeb(v,a)		__raw_writeb(v,a)
+#define writew(v,a)		__raw_writew(v,a)
+#define writel(v,a)		__raw_writel(v,a)
+
+#define readb(a)		__raw_readb(a)
+#define readw(a)		__raw_readw(a)
+#define readl(a)		__raw_readl(a)
+
+/*
+ * Bad read/write accesses...
+ */
+extern void __readwrite_bug(const char *fn);
+
+#define IO_SPACE_LIMIT	0xffffffff
+
+/*
+ * All I/O is memory mapped, so these macros doesn't make very much sense
+ */
+#define outb(v,p)		__raw_writeb(v, p)
+#define outw(v,p)		__raw_writew(cpu_to_le16(v),p)
+#define outl(v,p)		__raw_writel(cpu_to_le32(v),p)
+
+#define inb(p)	({ unsigned int __v = __raw_readb(p); __v; })
+#define inw(p)	({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
+#define inl(p)	({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
+
+#include <asm/addrspace.h>
+
+/* virt_to_phys will only work when address is in P1 or P2 */
+static __inline__ unsigned long virt_to_phys(volatile void *address)
+{
+	return PHYSADDR(address);
+}
+
+static __inline__ void * phys_to_virt(unsigned long address)
+{
+	return (void *)P1SEGADDR(address);
+}
+
+#define cached(addr) ((void *)P1SEGADDR(addr))
+#define uncached(addr) ((void *)P2SEGADDR(addr))
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_AVR32_IO_H */
diff --git a/include/asm-avr32/posix_types.h b/include/asm-avr32/posix_types.h
new file mode 100644
index 0000000..edf1bc1
--- /dev/null
+++ b/include/asm-avr32/posix_types.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_POSIX_TYPES_H
+#define __ASM_AVR32_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned short	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned int	__kernel_uid_t;
+typedef unsigned int	__kernel_gid_t;
+typedef unsigned long	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_timer_t;
+typedef int		__kernel_clockid_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+typedef unsigned short	__kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef  __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef  __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef  __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef  __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+	unsigned long *__tmp = __p->fds_bits;
+	int __i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+		case 16:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			__tmp[ 8] = 0; __tmp[ 9] = 0;
+			__tmp[10] = 0; __tmp[11] = 0;
+			__tmp[12] = 0; __tmp[13] = 0;
+			__tmp[14] = 0; __tmp[15] = 0;
+			return;
+
+		case 8:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			return;
+
+		case 4:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			return;
+		}
+	}
+	__i = __FDSET_LONGS;
+	while (__i) {
+		__i--;
+		*__tmp = 0;
+		__tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* __ASM_AVR32_POSIX_TYPES_H */
diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h
new file mode 100644
index 0000000..cc59dfa
--- /dev/null
+++ b/include/asm-avr32/processor.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PROCESSOR_H
+#define __ASM_AVR32_PROCESSOR_H
+
+#ifndef __ASSEMBLY__
+
+#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; })
+
+struct avr32_cpuinfo {
+	unsigned long loops_per_jiffy;
+};
+
+extern struct avr32_cpuinfo boot_cpu_data;
+
+#ifdef CONFIG_SMP
+extern struct avr32_cpuinfo cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+#else
+#define cpu_data (&boot_cpu_data)
+#define current_cpu_data boot_cpu_data
+#endif
+
+/* TODO: Make configurable (2GB will serve as a reasonable default) */
+#define TASK_SIZE	0x80000000
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's
+ */
+#define TASK_UNMAPPED_BASE	(TASK_SIZE / 3)
+
+#define cpu_relax()		barrier()
+#define cpu_sync_pipeline()	asm volatile("sub pc, -2" : : : "memory")
+
+/* This struct contains the CPU context as stored by switch_to() */
+struct thread_struct {
+	unsigned long pc;
+	unsigned long ksp;	/* Kernel stack pointer */
+	unsigned long r7;
+	unsigned long r6;
+	unsigned long r5;
+	unsigned long r4;
+	unsigned long r3;
+	unsigned long r2;
+	unsigned long r1;
+	unsigned long r0;
+};
+
+#define INIT_THREAD {						\
+	.ksp = sizeof(init_stack) + (long)&init_stack,		\
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+#define start_thread(regs, new_pc, new_sp)	 \
+	set_fs(USER_DS);			 \
+	regs->sr = 0;		/* User mode. */ \
+	regs->gr[REG_PC] = new_pc;		 \
+	regs->gr[REG_SP] = new_sp
+
+struct task_struct;
+
+/* Free all resources held by a thread */
+extern void release_thread(struct task_struct *);
+
+/* Create a kernel thread without removing it from tasklists */
+extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk) do { } while(0)
+
+/* Return saved PC of a blocked thread */
+#define thread_saved_pc(tsk)    (tsk->thread.pc)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_PROCESSOR_H */
diff --git a/include/asm-avr32/ptrace.h b/include/asm-avr32/ptrace.h
new file mode 100644
index 0000000..c770ba0
--- /dev/null
+++ b/include/asm-avr32/ptrace.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PTRACE_H
+#define __ASM_AVR32_PTRACE_H
+
+/*
+ * Status Register bits
+ */
+#define SR_H		0x40000000
+#define SR_R		0x20000000
+#define SR_J		0x10000000
+#define SR_DM		0x08000000
+#define SR_D		0x04000000
+#define MODE_NMI	0x01c00000
+#define MODE_EXCEPTION	0x01800000
+#define MODE_INT3	0x01400000
+#define MODE_INT2	0x01000000
+#define MODE_INT1	0x00c00000
+#define MODE_INT0	0x00800000
+#define MODE_SUPERVISOR	0x00400000
+#define MODE_USER	0x00000000
+#define MODE_MASK	0x01c00000
+#define SR_EM		0x00200000
+#define SR_I3M		0x00100000
+#define SR_I2M		0x00080000
+#define SR_I1M		0x00040000
+#define SR_I0M		0x00020000
+#define SR_GM		0x00010000
+
+#define MODE_SHIFT	22
+#define SR_EM_BIT	21
+#define SR_I3M_BIT	20
+#define SR_I2M_BIT	19
+#define SR_I1M_BIT	18
+#define SR_I0M_BIT	17
+#define SR_GM_BIT	16
+
+/* The user-visible part */
+#define SR_Q		0x00000010
+#define SR_V		0x00000008
+#define SR_N		0x00000004
+#define SR_Z		0x00000002
+#define SR_C		0x00000001
+
+/*
+ * The order is defined by the stdsp instruction. r0 is stored first, so it
+ * gets the highest address.
+ *
+ * Registers 0-12 are general-purpose registers (r12 is normally used for
+ * the function return value).
+ * Register 13 is the stack pointer
+ * Register 14 is the link register
+ * Register 15 is the program counter
+ */
+#define FRAME_SIZE_FULL 72
+#define REG_R12_ORIG	68
+#define REG_R0		64
+#define REG_R1		60
+#define REG_R2		56
+#define REG_R3		52
+#define REG_R4		48
+#define REG_R5		44
+#define REG_R6		40
+#define REG_R7		36
+#define REG_R8		32
+#define REG_R9		28
+#define REG_R10		34
+#define REG_R11		20
+#define REG_R12		16
+#define REG_SP		12
+#define REG_LR		 8
+
+#define FRAME_SIZE_MIN	 8
+#define REG_PC		 4
+#define REG_SR		 0
+
+#ifndef __ASSEMBLY__
+struct pt_regs {
+	/* These are always saved */
+	unsigned long sr;
+	unsigned long pc;
+
+	/* These are sometimes saved */
+	unsigned long lr;
+	unsigned long sp;
+	unsigned long r12;
+	unsigned long r11;
+	unsigned long r10;
+	unsigned long r9;
+	unsigned long r8;
+	unsigned long r7;
+	unsigned long r6;
+	unsigned long r5;
+	unsigned long r4;
+	unsigned long r3;
+	unsigned long r2;
+	unsigned long r1;
+	unsigned long r0;
+
+	/* Only saved on system call */
+	unsigned long r12_orig;
+};
+
+#ifdef __KERNEL__
+# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
+# define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs (struct pt_regs *);
+
+static __inline__ int valid_user_regs(struct pt_regs *regs)
+{
+	/*
+	 * Some of the Java bits might be acceptable if/when we
+	 * implement some support for that stuff...
+	 */
+	if ((regs->sr & 0xffff0000) == 0)
+		return 1;
+
+	/*
+	 * Force status register flags to be sane and report this
+	 * illegal behaviour...
+	 */
+	regs->sr &= 0x0000ffff;
+	return 0;
+}
+#endif
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_PTRACE_H */
diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h
new file mode 100644
index 0000000..5057eef
--- /dev/null
+++ b/include/asm-avr32/sdram.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SDRAM_H
+#define __ASM_AVR32_SDRAM_H
+
+struct sdram_info {
+	unsigned long phys_addr;
+	unsigned int row_bits, col_bits, bank_bits;
+	unsigned int cas, twr, trc, trp, trcd, tras, txsr;
+};
+
+extern unsigned long sdram_init(const struct sdram_info *info);
+
+#endif /* __ASM_AVR32_SDRAM_H */
diff --git a/include/asm-avr32/sections.h b/include/asm-avr32/sections.h
new file mode 100644
index 0000000..75373ab
--- /dev/null
+++ b/include/asm-avr32/sections.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SECTIONS_H
+#define __ASM_AVR32_SECTIONS_H
+
+/* References to section boundaries */
+
+extern char _text[], _etext[];
+extern char __flashprog_start[], __flashprog_end[];
+extern char _data[], __data_lma[], _edata[], __edata_lma[];
+extern char __got_start[], __got_lma[], __got_end[];
+extern char _end[];
+
+/*
+ * Everything in .flashprog will be locked in the icache so it doesn't
+ * get disturbed when executing flash commands.
+ */
+#define __flashprog __attribute__((section(".flashprog"), __noinline__))
+
+#endif /* __ASM_AVR32_SECTIONS_H */
diff --git a/include/asm-avr32/setup.h b/include/asm-avr32/setup.h
new file mode 100644
index 0000000..e6ef8d6
--- /dev/null
+++ b/include/asm-avr32/setup.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * Based on linux/include/asm-arm/setup.h
+ *   Copyright (C) 1997-1999 Russel King
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SETUP_H__
+#define __ASM_AVR32_SETUP_H__
+
+#define COMMAND_LINE_SIZE 256
+
+/* Magic number indicating that a tag table is present */
+#define ATAG_MAGIC	0xa2a25441
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Generic memory range, used by several tags.
+ *
+ *   addr is always physical.
+ *   size is measured in bytes.
+ *   next is for use by the OS, e.g. for grouping regions into
+ *	  linked lists.
+ */
+struct tag_mem_range {
+	u32			addr;
+	u32			size;
+	struct tag_mem_range *	next;
+};
+
+/* The list ends with an ATAG_NONE node. */
+#define ATAG_NONE	0x00000000
+
+struct tag_header {
+	u32 size;
+	u32 tag;
+};
+
+/* The list must start with an ATAG_CORE node */
+#define ATAG_CORE	0x54410001
+
+struct tag_core {
+	u32 flags;
+	u32 pagesize;
+	u32 rootdev;
+};
+
+/* it is allowed to have multiple ATAG_MEM nodes */
+#define ATAG_MEM	0x54410002
+/* ATAG_MEM uses tag_mem_range */
+
+/* command line: \0 terminated string */
+#define ATAG_CMDLINE	0x54410003
+
+struct tag_cmdline {
+	char	cmdline[1];	/* this is the minimum size */
+};
+
+/* Ramdisk image (may be compressed) */
+#define ATAG_RDIMG	0x54410004
+/* ATAG_RDIMG uses tag_mem_range */
+
+/* Information about various clocks present in the system */
+#define ATAG_CLOCK	0x54410005
+
+struct tag_clock {
+	u32	clock_id;	/* Which clock are we talking about? */
+	u32	clock_flags;	/* Special features */
+	u64	clock_hz;	/* Clock speed in Hz */
+};
+
+/* The clock types we know about */
+#define ACLOCK_BOOTCPU	0	/* The CPU we're booting from */
+#define ACLOCK_HSB	1	/* Deprecated */
+
+/* Memory reserved for the system (e.g. the bootloader) */
+#define ATAG_RSVD_MEM	0x54410006
+/* ATAG_RSVD_MEM uses tag_mem_range */
+
+/* Ethernet information */
+
+#define ATAG_ETHERNET	0x54410007
+
+struct tag_ethernet {
+	u8	mac_index;
+	u8	mii_phy_addr;
+	u8	hw_address[6];
+};
+
+#define AETH_INVALID_PHY	0xff
+
+struct tag {
+	struct tag_header hdr;
+	union {
+		struct tag_core core;
+		struct tag_mem_range mem_range;
+		struct tag_cmdline cmdline;
+		struct tag_clock clock;
+		struct tag_ethernet ethernet;
+	} u;
+};
+
+struct tagtable {
+	u32	tag;
+	int	(*parse)(struct tag *);
+};
+
+#define __tag __attribute_used__ __attribute__((__section__(".taglist")))
+#define __tagtable(tag, fn)						\
+	static struct tagtable __tagtable_##fn __tag = { tag, fn }
+
+#define tag_member_present(tag,member)					\
+	((unsigned long)(&((struct tag *)0L)->member + 1)		\
+	 <= (tag)->hdr.size * 4)
+
+#define tag_next(t)	((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_size(type)	((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
+
+#define for_each_tag(t,base)						\
+	for (t = base; t->hdr.size; t = tag_next(t))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_SETUP_H__ */
diff --git a/include/asm-avr32/string.h b/include/asm-avr32/string.h
new file mode 100644
index 0000000..8b05d1a
--- /dev/null
+++ b/include/asm-avr32/string.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_STRING_H
+#define __ASM_AVR32_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *s, int c, size_t n);
+
+#endif /* __ASM_AVR32_STRING_H */
diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h
new file mode 100644
index 0000000..72ad49e
--- /dev/null
+++ b/include/asm-avr32/sysreg.h
@@ -0,0 +1,279 @@
+/*
+ * System registers for AVR32
+ */
+#ifndef __ASM_AVR32_SYSREG_H__
+#define __ASM_AVR32_SYSREG_H__
+
+/* system register offsets */
+#define SYSREG_SR			0x0000
+#define SYSREG_EVBA			0x0004
+#define SYSREG_ACBA			0x0008
+#define SYSREG_CPUCR			0x000c
+#define SYSREG_ECR			0x0010
+#define SYSREG_RSR_SUP			0x0014
+#define SYSREG_RSR_INT0			0x0018
+#define SYSREG_RSR_INT1			0x001c
+#define SYSREG_RSR_INT2			0x0020
+#define SYSREG_RSR_INT3			0x0024
+#define SYSREG_RSR_EX			0x0028
+#define SYSREG_RSR_NMI			0x002c
+#define SYSREG_RSR_DBG			0x0030
+#define SYSREG_RAR_SUP			0x0034
+#define SYSREG_RAR_INT0			0x0038
+#define SYSREG_RAR_INT1			0x003c
+#define SYSREG_RAR_INT2			0x0040
+#define SYSREG_RAR_INT3			0x0044
+#define SYSREG_RAR_EX			0x0048
+#define SYSREG_RAR_NMI			0x004c
+#define SYSREG_RAR_DBG			0x0050
+#define SYSREG_JECR			0x0054
+#define SYSREG_JOSP			0x0058
+#define SYSREG_JAVA_LV0			0x005c
+#define SYSREG_JAVA_LV1			0x0060
+#define SYSREG_JAVA_LV2			0x0064
+#define SYSREG_JAVA_LV3			0x0068
+#define SYSREG_JAVA_LV4			0x006c
+#define SYSREG_JAVA_LV5			0x0070
+#define SYSREG_JAVA_LV6			0x0074
+#define SYSREG_JAVA_LV7			0x0078
+#define SYSREG_JTBA			0x007c
+#define SYSREG_JBCR			0x0080
+#define SYSREG_CONFIG0			0x0100
+#define SYSREG_CONFIG1			0x0104
+#define SYSREG_COUNT			0x0108
+#define SYSREG_COMPARE			0x010c
+#define SYSREG_TLBEHI			0x0110
+#define SYSREG_TLBELO			0x0114
+#define SYSREG_PTBR			0x0118
+#define SYSREG_TLBEAR			0x011c
+#define SYSREG_MMUCR			0x0120
+#define SYSREG_TLBARLO			0x0124
+#define SYSREG_TLBARHI			0x0128
+#define SYSREG_PCCNT			0x012c
+#define SYSREG_PCNT0			0x0130
+#define SYSREG_PCNT1			0x0134
+#define SYSREG_PCCR			0x0138
+#define SYSREG_BEAR			0x013c
+#define SYSREG_SABAL			0x0300
+#define SYSREG_SABAH			0x0304
+#define SYSREG_SABD			0x0308
+
+/* Bitfields in SR */
+#define SYSREG_SR_C_OFFSET		0
+#define SYSREG_SR_C_SIZE		1
+#define SYSREG_Z_OFFSET			1
+#define SYSREG_Z_SIZE			1
+#define SYSREG_SR_N_OFFSET		2
+#define SYSREG_SR_N_SIZE		1
+#define SYSREG_SR_V_OFFSET		3
+#define SYSREG_SR_V_SIZE		1
+#define SYSREG_Q_OFFSET			4
+#define SYSREG_Q_SIZE			1
+#define SYSREG_L_OFFSET			5
+#define SYSREG_L_SIZE			1
+#define SYSREG_T_OFFSET			14
+#define SYSREG_T_SIZE			1
+#define SYSREG_SR_R_OFFSET		15
+#define SYSREG_SR_R_SIZE		1
+#define SYSREG_GM_OFFSET		16
+#define SYSREG_GM_SIZE			1
+#define SYSREG_I0M_OFFSET		17
+#define SYSREG_I0M_SIZE			1
+#define SYSREG_I1M_OFFSET		18
+#define SYSREG_I1M_SIZE			1
+#define SYSREG_I2M_OFFSET		19
+#define SYSREG_I2M_SIZE			1
+#define SYSREG_I3M_OFFSET		20
+#define SYSREG_I3M_SIZE			1
+#define SYSREG_EM_OFFSET		21
+#define SYSREG_EM_SIZE			1
+#define SYSREG_M0_OFFSET		22
+#define SYSREG_M0_SIZE			1
+#define SYSREG_M1_OFFSET		23
+#define SYSREG_M1_SIZE			1
+#define SYSREG_M2_OFFSET		24
+#define SYSREG_M2_SIZE			1
+#define SYSREG_SR_D_OFFSET		26
+#define SYSREG_SR_D_SIZE		1
+#define SYSREG_DM_OFFSET		27
+#define SYSREG_DM_SIZE			1
+#define SYSREG_SR_J_OFFSET		28
+#define SYSREG_SR_J_SIZE		1
+#define SYSREG_H_OFFSET			29
+#define SYSREG_H_SIZE			1
+
+/* Bitfields in CPUCR */
+#define SYSREG_BI_OFFSET		0
+#define SYSREG_BI_SIZE			1
+#define SYSREG_BE_OFFSET		1
+#define SYSREG_BE_SIZE			1
+#define SYSREG_FE_OFFSET		2
+#define SYSREG_FE_SIZE			1
+#define SYSREG_RE_OFFSET		3
+#define SYSREG_RE_SIZE			1
+#define SYSREG_IBE_OFFSET		4
+#define SYSREG_IBE_SIZE			1
+#define SYSREG_IEE_OFFSET		5
+#define SYSREG_IEE_SIZE			1
+
+/* Bitfields in ECR */
+#define SYSREG_ECR_OFFSET		0
+#define SYSREG_ECR_SIZE			32
+
+/* Bitfields in CONFIG0 */
+#define SYSREG_CONFIG0_R_OFFSET		0
+#define SYSREG_CONFIG0_R_SIZE		1
+#define SYSREG_CONFIG0_D_OFFSET		1
+#define SYSREG_CONFIG0_D_SIZE		1
+#define SYSREG_CONFIG0_S_OFFSET		2
+#define SYSREG_CONFIG0_S_SIZE		1
+#define SYSREG_O_OFFSET			3
+#define SYSREG_O_SIZE			1
+#define SYSREG_P_OFFSET			4
+#define SYSREG_P_SIZE			1
+#define SYSREG_CONFIG0_J_OFFSET		5
+#define SYSREG_CONFIG0_J_SIZE		1
+#define SYSREG_F_OFFSET			6
+#define SYSREG_F_SIZE			1
+#define SYSREG_MMUT_OFFSET		7
+#define SYSREG_MMUT_SIZE		3
+#define SYSREG_AR_OFFSET		10
+#define SYSREG_AR_SIZE			3
+#define SYSREG_AT_OFFSET		13
+#define SYSREG_AT_SIZE			3
+#define SYSREG_PROCESSORREVISION_OFFSET	16
+#define SYSREG_PROCESSORREVISION_SIZE	8
+#define SYSREG_PROCESSORID_OFFSET	24
+#define SYSREG_PROCESSORID_SIZE		8
+
+/* Bitfields in CONFIG1 */
+#define SYSREG_DASS_OFFSET		0
+#define SYSREG_DASS_SIZE		3
+#define SYSREG_DLSZ_OFFSET		3
+#define SYSREG_DLSZ_SIZE		3
+#define SYSREG_DSET_OFFSET		6
+#define SYSREG_DSET_SIZE		4
+#define SYSREG_IASS_OFFSET		10
+#define SYSREG_IASS_SIZE		3
+#define SYSREG_ILSZ_OFFSET		13
+#define SYSREG_ILSZ_SIZE		3
+#define SYSREG_ISET_OFFSET		16
+#define SYSREG_ISET_SIZE		4
+#define SYSREG_DMMUSZ_OFFSET		20
+#define SYSREG_DMMUSZ_SIZE		6
+#define SYSREG_IMMUSZ_OFFSET		26
+#define SYSREG_IMMUSZ_SIZE		6
+
+/* Bitfields in TLBEHI */
+#define SYSREG_ASID_OFFSET		0
+#define SYSREG_ASID_SIZE		8
+#define SYSREG_TLBEHI_I_OFFSET		8
+#define SYSREG_TLBEHI_I_SIZE		1
+#define SYSREG_TLBEHI_V_OFFSET		9
+#define SYSREG_TLBEHI_V_SIZE		1
+#define SYSREG_VPN_OFFSET		10
+#define SYSREG_VPN_SIZE			22
+
+/* Bitfields in TLBELO */
+#define SYSREG_W_OFFSET			0
+#define SYSREG_W_SIZE			1
+#define SYSREG_TLBELO_D_OFFSET		1
+#define SYSREG_TLBELO_D_SIZE		1
+#define SYSREG_SZ_OFFSET		2
+#define SYSREG_SZ_SIZE			2
+#define SYSREG_AP_OFFSET		4
+#define SYSREG_AP_SIZE			3
+#define SYSREG_B_OFFSET			7
+#define SYSREG_B_SIZE			1
+#define SYSREG_G_OFFSET			8
+#define SYSREG_G_SIZE			1
+#define SYSREG_TLBELO_C_OFFSET		9
+#define SYSREG_TLBELO_C_SIZE		1
+#define SYSREG_PFN_OFFSET		10
+#define SYSREG_PFN_SIZE			22
+
+/* Bitfields in MMUCR */
+#define SYSREG_E_OFFSET			0
+#define SYSREG_E_SIZE			1
+#define SYSREG_M_OFFSET			1
+#define SYSREG_M_SIZE			1
+#define SYSREG_MMUCR_I_OFFSET		2
+#define SYSREG_MMUCR_I_SIZE		1
+#define SYSREG_MMUCR_N_OFFSET		3
+#define SYSREG_MMUCR_N_SIZE		1
+#define SYSREG_MMUCR_S_OFFSET		4
+#define SYSREG_MMUCR_S_SIZE		1
+#define SYSREG_DLA_OFFSET		8
+#define SYSREG_DLA_SIZE			6
+#define SYSREG_DRP_OFFSET		14
+#define SYSREG_DRP_SIZE			6
+#define SYSREG_ILA_OFFSET		20
+#define SYSREG_ILA_SIZE			6
+#define SYSREG_IRP_OFFSET		26
+#define SYSREG_IRP_SIZE			6
+
+/* Bitfields in PCCR */
+#define SYSREG_PCCR_R_OFFSET		1
+#define SYSREG_PCCR_R_SIZE		1
+#define SYSREG_PCCR_C_OFFSET		2
+#define SYSREG_PCCR_C_SIZE		1
+#define SYSREG_PCCR_S_OFFSET		3
+#define SYSREG_PCCR_S_SIZE		1
+#define SYSREG_IEC_OFFSET		4
+#define SYSREG_IEC_SIZE			1
+#define SYSREG_IE0_OFFSET		5
+#define SYSREG_IE0_SIZE			1
+#define SYSREG_IE1_OFFSET		6
+#define SYSREG_IE1_SIZE			1
+#define SYSREG_FC_OFFSET		8
+#define SYSREG_FC_SIZE			1
+#define SYSREG_F0_OFFSET		9
+#define SYSREG_F0_SIZE			1
+#define SYSREG_F1_OFFSET		10
+#define SYSREG_F1_SIZE			1
+#define SYSREG_CONF0_OFFSET		12
+#define SYSREG_CONF0_SIZE		6
+#define SYSREG_CONF1_OFFSET		18
+#define SYSREG_CONF1_SIZE		6
+
+/* Constants for ECR */
+#define ECR_UNRECOVERABLE		0
+#define ECR_TLB_MULTIPLE		1
+#define ECR_BUS_ERROR_WRITE		2
+#define ECR_BUS_ERROR_READ		3
+#define ECR_NMI				4
+#define ECR_ADDR_ALIGN_X		5
+#define ECR_PROTECTION_X		6
+#define ECR_DEBUG			7
+#define ECR_ILLEGAL_OPCODE		8
+#define ECR_UNIMPL_INSTRUCTION		9
+#define ECR_PRIVILEGE_VIOLATION		10
+#define ECR_FPE				11
+#define ECR_COPROC_ABSENT		12
+#define ECR_ADDR_ALIGN_R		13
+#define ECR_ADDR_ALIGN_W		14
+#define ECR_PROTECTION_R		15
+#define ECR_PROTECTION_W		16
+#define ECR_DTLB_MODIFIED		17
+#define ECR_TLB_MISS_X			20
+#define ECR_TLB_MISS_R			24
+#define ECR_TLB_MISS_W			28
+
+/* Bit manipulation macros */
+#define SYSREG_BIT(name)		(1 << SYSREG_##name##_OFFSET)
+#define SYSREG_BF(name,value)				\
+	(((value) & ((1 << SYSREG_##name##_SIZE) - 1))	\
+	 << SYSREG_##name##_OFFSET)
+#define SYSREG_BFEXT(name,value)			\
+	(((value) >> SYSREG_##name##_OFFSET)		\
+	 & ((1 << SYSREG_##name##_SIZE) - 1))
+#define SYSREG_BFINS(name,value,old)			\
+	(((old) & ~(((1 << SYSREG_##name##_SIZE) - 1)	\
+		    << SYSREG_##name##_OFFSET))		\
+	 | SYSREG_BF(name,value))
+
+/* Register access macros */
+#define sysreg_read(reg)		__builtin_mfsr(SYSREG_##reg)
+#define sysreg_write(reg, value)	__builtin_mtsr(SYSREG_##reg, value)
+
+#endif /* __ASM_AVR32_SYSREG_H__ */
diff --git a/include/asm-avr32/types.h b/include/asm-avr32/types.h
new file mode 100644
index 0000000..e6c65d9
--- /dev/null
+++ b/include/asm-avr32/types.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_TYPES_H
+#define __ASM_AVR32_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef __signed__ char s8;
+typedef unsigned char u8;
+
+typedef __signed__ short s16;
+typedef unsigned short u16;
+
+typedef __signed__ int s32;
+typedef unsigned int u32;
+
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+#ifdef CONFIG_LBD
+typedef u64 sector_t;
+#define HAVE_SECTOR_T
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+
+#endif /* __ASM_AVR32_TYPES_H */
diff --git a/include/asm-avr32/u-boot.h b/include/asm-avr32/u-boot.h
new file mode 100644
index 0000000..71dfcaf
--- /dev/null
+++ b/include/asm-avr32/u-boot.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_U_BOOT_H__
+#define __ASM_U_BOOT_H__ 1
+
+typedef struct bd_info {
+	unsigned long		bi_baudrate;
+	unsigned long		bi_ip_addr;
+	unsigned char		bi_enetaddr[6];
+	unsigned char		bi_phy_id[4];
+	struct environment_s	*bi_env;
+	unsigned long		bi_board_number;
+	void			*bi_boot_params;
+	struct {
+		unsigned long	start;
+		unsigned long	size;
+	}			bi_dram[CONFIG_NR_DRAM_BANKS];
+	unsigned long		bi_flashstart;
+	unsigned long		bi_flashsize;
+	unsigned long		bi_flashoffset;
+} bd_t;
+
+#define bi_memstart bi_dram[0].start
+#define bi_memsize bi_dram[0].size
+
+/**
+ *  container_of - cast a member of a structure out to the containing structure
+ *
+ *    @ptr:        the pointer to the member.
+ *    @type:       the type of the container struct this is embedded in.
+ *    @member:     the name of the member within the struct.
+ */
+#define container_of(ptr, type, member) ({                      \
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* __ASM_U_BOOT_H__ */
diff --git a/lib_avr32/Makefile b/lib_avr32/Makefile
new file mode 100644
index 0000000..5b6300b
--- /dev/null
+++ b/lib_avr32/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).a
+
+SOBJS	= memset.o
+
+COBJS	= board.o interrupts.o avr32_linux.o div64.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/lib_avr32/avr32_linux.c b/lib_avr32/avr32_linux.c
new file mode 100644
index 0000000..d128dfb
--- /dev/null
+++ b/lib_avr32/avr32_linux.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <zlib.h>
+#include <asm/byteorder.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/arch/platform.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* CPU-specific hook to allow flushing of caches, etc. */
+extern void prepare_to_boot(void);
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+extern image_header_t header;		/* from cmd_bootm.c */
+
+static struct tag *setup_start_tag(struct tag *params)
+{
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 4096;
+	params->u.core.rootdev = 0;
+
+	return tag_next(params);
+}
+
+static struct tag *setup_memory_tags(struct tag *params)
+{
+	bd_t *bd = gd->bd;
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem_range);
+
+		params->u.mem_range.addr = bd->bi_dram[i].start;
+		params->u.mem_range.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+
+	return params;
+}
+
+static struct tag *setup_commandline_tag(struct tag *params, char *cmdline)
+{
+	if (!cmdline)
+		return params;
+
+	/* eat leading white space */
+	while (*cmdline == ' ') cmdline++;
+
+	/*
+	 * Don't include tags for empty command lines; let the kernel
+	 * use its default command line.
+	 */
+	if (*cmdline == '\0')
+		return params;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof (struct tag_header) + strlen(cmdline) + 1 + 3) >> 2;
+	strcpy(params->u.cmdline.cmdline, cmdline);
+
+	return tag_next(params);
+}
+
+static struct tag *setup_ramdisk_tag(struct tag *params,
+				     unsigned long rd_start,
+				     unsigned long rd_end)
+{
+	if (rd_start == rd_end)
+		return params;
+
+	params->hdr.tag = ATAG_RDIMG;
+	params->hdr.size = tag_size(tag_mem_range);
+
+	params->u.mem_range.addr = rd_start;
+	params->u.mem_range.size = rd_end - rd_start;
+
+	return tag_next(params);
+}
+
+static struct tag *setup_clock_tags(struct tag *params)
+{
+	params->hdr.tag = ATAG_CLOCK;
+	params->hdr.size = tag_size(tag_clock);
+	params->u.clock.clock_id = ACLOCK_BOOTCPU;
+	params->u.clock.clock_flags = 0;
+	params->u.clock.clock_hz = gd->cpu_hz;
+
+#ifdef CONFIG_AT32AP7000
+	/*
+	 * New kernels don't need this, but we should be backwards
+	 * compatible for a while...
+	 */
+	params = tag_next(params);
+
+	params->hdr.tag = ATAG_CLOCK;
+	params->hdr.size = tag_size(tag_clock);
+	params->u.clock.clock_id = ACLOCK_HSB;
+	params->u.clock.clock_flags = 0;
+	params->u.clock.clock_hz = pm_get_clock_freq(CLOCK_HSB);
+#endif
+
+	return tag_next(params);
+}
+
+static struct tag *setup_ethernet_tag(struct tag *params,
+				      char *addr, int index)
+{
+	char *s, *e;
+	int i;
+
+	params->hdr.tag = ATAG_ETHERNET;
+	params->hdr.size = tag_size(tag_ethernet);
+
+	params->u.ethernet.mac_index = index;
+	params->u.ethernet.mii_phy_addr = gd->bd->bi_phy_id[index];
+
+	s = addr;
+	for (i = 0; i < 6; i++) {
+		params->u.ethernet.hw_address[i] = simple_strtoul(s, &e, 16);
+		s = e + 1;
+	}
+
+	return tag_next(params);
+}
+
+static struct tag *setup_ethernet_tags(struct tag *params)
+{
+	char name[16] = "ethaddr";
+	char *addr;
+	int i = 0;
+
+	do {
+		addr = getenv(name);
+		if (addr)
+			params = setup_ethernet_tag(params, addr, i);
+		sprintf(name, "eth%daddr", ++i);
+	} while (i < 4);
+
+	return params;
+}
+
+static void setup_end_tag(struct tag *params)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
+		    unsigned long addr, unsigned long *len_ptr, int verify)
+{
+	unsigned long data, len = 0;
+	unsigned long initrd_start, initrd_end;
+	unsigned long image_start, image_end;
+	unsigned long checksum;
+	void (*theKernel)(int magic, void *tagtable);
+	image_header_t *hdr;
+	struct tag *params, *params_start;
+	char *commandline = getenv("bootargs");
+
+	hdr = (image_header_t *)addr;
+	image_start = addr;
+	image_end = addr + hdr->ih_size;
+
+	theKernel = (void *)ntohl(hdr->ih_ep);
+
+	/*
+	 * Check if there is an initrd image
+	 */
+	if (argc >= 3) {
+		SHOW_BOOT_PROGRESS(9);
+
+		addr = simple_strtoul(argv[2], NULL, 16);
+
+		printf("## Loading RAMDISK image at %08lx ...\n", addr);
+
+		memcpy(&header, (char *)addr, sizeof(header));
+		hdr = &header;
+
+		if (ntohl(hdr->ih_magic) != IH_MAGIC) {
+			puts("Bad Magic Number\n");
+			SHOW_BOOT_PROGRESS(-10);
+			do_reset(cmdtp, flag, argc, argv);
+		}
+
+		data = (unsigned long)hdr;
+		len = sizeof(*hdr);
+		checksum = ntohl(hdr->ih_hcrc);
+		hdr->ih_hcrc = 0;
+
+		if (crc32(0, (unsigned char *)data, len) != checksum) {
+			puts("Bad Header Checksum\n");
+			SHOW_BOOT_PROGRESS(-11);
+			do_reset(cmdtp, flag, argc, argv);
+		}
+
+		SHOW_BOOT_PROGRESS(10);
+
+		print_image_hdr(hdr);
+
+		data = addr + sizeof(header);
+		len = ntohl(hdr->ih_size);
+
+		if (verify) {
+			unsigned long csum = 0;
+
+			puts("   Verifying Checksum ... ");
+			csum = crc32(0, (unsigned char *)data, len);
+			if (csum != ntohl(hdr->ih_dcrc)) {
+				puts("Bad Data CRC\n");
+				SHOW_BOOT_PROGRESS(-12);
+				do_reset(cmdtp, flag, argc, argv);
+			}
+			puts("OK\n");
+		}
+
+		SHOW_BOOT_PROGRESS(11);
+
+		if ((hdr->ih_os != IH_OS_LINUX) ||
+		    (hdr->ih_arch != IH_CPU_AVR32) ||
+		    (hdr->ih_type != IH_TYPE_RAMDISK)) {
+			puts("Not a Linux/AVR32 RAMDISK image\n");
+			SHOW_BOOT_PROGRESS(-13);
+			do_reset(cmdtp, flag, argc, argv);
+		}
+	} else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) {
+		ulong tail = ntohl (len_ptr[0]) % 4;
+		int i;
+
+		SHOW_BOOT_PROGRESS (13);
+
+		/* skip kernel length and terminator */
+		data = (ulong) (&len_ptr[2]);
+		/* skip any additional image length fields */
+		for (i = 1; len_ptr[i]; ++i)
+			data += 4;
+		/* add kernel length, and align */
+		data += ntohl (len_ptr[0]);
+		if (tail) {
+			data += 4 - tail;
+		}
+
+		len = ntohl (len_ptr[1]);
+	} else {
+		/* no initrd image */
+		SHOW_BOOT_PROGRESS(14);
+		len = data = 0;
+	}
+
+	if (data) {
+		initrd_start = data;
+		initrd_end = initrd_start + len;
+	} else {
+		initrd_start = 0;
+		initrd_end = 0;
+	}
+
+	SHOW_BOOT_PROGRESS(15);
+
+	params = params_start = (struct tag *)gd->bd->bi_boot_params;
+	params = setup_start_tag(params);
+	params = setup_memory_tags(params);
+	if (initrd_start) {
+		params = setup_ramdisk_tag(params,
+					   PHYSADDR(initrd_start),
+					   PHYSADDR(initrd_end));
+	}
+	params = setup_commandline_tag(params, commandline);
+	params = setup_clock_tags(params);
+	params = setup_ethernet_tags(params);
+	setup_end_tag(params);
+
+	printf("\nStarting kernel at %p (params at %p)...\n\n",
+	       theKernel, params_start);
+
+	prepare_to_boot();
+
+	theKernel(ATAG_MAGIC, params_start);
+}
diff --git a/lib_avr32/board.c b/lib_avr32/board.c
new file mode 100644
index 0000000..02c106b
--- /dev/null
+++ b/lib_avr32/board.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <devices.h>
+#include <version.h>
+#include <net.h>
+
+#include <asm/initcalls.h>
+#include <asm/sections.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const char version_string[] =
+	U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ") " CONFIG_IDENT_STRING;
+
+unsigned long monitor_flash_len;
+
+/*
+ * Begin and end of memory area for malloc(), and current "brk"
+ */
+static unsigned long mem_malloc_start = 0;
+static unsigned long mem_malloc_end = 0;
+static unsigned long mem_malloc_brk = 0;
+
+/* The malloc area is wherever the board wants it to be */
+static void mem_malloc_init(void)
+{
+	mem_malloc_start = CFG_MALLOC_START;
+	mem_malloc_end = CFG_MALLOC_END;
+	mem_malloc_brk = mem_malloc_start;
+
+	printf("malloc: Using memory from 0x%08lx to 0x%08lx\n",
+	       mem_malloc_start, mem_malloc_end);
+
+	memset ((void *)mem_malloc_start, 0,
+		mem_malloc_end - mem_malloc_start);
+}
+
+void *sbrk(ptrdiff_t increment)
+{
+	unsigned long old = mem_malloc_brk;
+	unsigned long new = old + increment;
+
+	if ((new < mem_malloc_start) || (new > mem_malloc_end))
+		return NULL;
+
+	mem_malloc_brk = new;
+	return ((void *)old);
+}
+
+static int init_baudrate(void)
+{
+	char tmp[64];
+	int i;
+
+	i = getenv_r("baudrate", tmp, sizeof(tmp));
+	if (i > 0) {
+		gd->baudrate = simple_strtoul(tmp, NULL, 10);
+	} else {
+		gd->baudrate = CONFIG_BAUDRATE;
+	}
+	return 0;
+}
+
+
+static int display_banner (void)
+{
+	printf ("\n\n%s\n\n", version_string);
+	printf ("U-Boot code: %p -> %p  data: %p -> %p\n",
+		_text, _etext, _data, _end);
+	return 0;
+}
+
+void hang(void)
+{
+	for (;;) ;
+}
+
+static int display_dram_config (void)
+{
+	int i;
+
+	puts ("DRAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size (gd->bd->bi_dram[i].size, "\n");
+	}
+
+	return 0;
+}
+
+static void display_flash_config (void)
+{
+	puts ("Flash: ");
+	print_size(gd->bd->bi_flashsize, " ");
+	printf("at address 0x%08lx\n", gd->bd->bi_flashstart);
+}
+
+void start_u_boot (void)
+{
+	gd_t gd_data;
+
+	/* Initialize the global data pointer */
+	memset(&gd_data, 0, sizeof(gd_data));
+	gd = &gd_data;
+
+	monitor_flash_len = _edata - _text;
+
+	/* Perform initialization sequence */
+	cpu_init();
+	timer_init();
+	env_init();
+	init_baudrate();
+	serial_init();
+	console_init_f();
+	display_banner();
+
+	board_init_memories();
+	mem_malloc_init();
+
+	gd->bd = malloc(sizeof(bd_t));
+	memset(gd->bd, 0, sizeof(bd_t));
+	gd->bd->bi_baudrate = gd->baudrate;
+	gd->bd->bi_dram[0].start = CFG_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->sdram_size;
+
+	board_init_info();
+	flash_init();
+
+	if (gd->bd->bi_flashsize)
+		display_flash_config();
+	if (gd->bd->bi_dram[0].size)
+		display_dram_config();
+
+	gd->bd->bi_boot_params = malloc(CFG_BOOTPARAMS_LEN);
+	if (!gd->bd->bi_boot_params)
+		puts("WARNING: Cannot allocate space for boot parameters\n");
+
+	/* initialize environment */
+	env_relocate();
+
+	devices_init();
+	jumptable_init();
+	console_init_r();
+
+	for (;;) {
+		main_loop();
+	}
+}
diff --git a/lib_avr32/div64.c b/lib_avr32/div64.c
new file mode 100644
index 0000000..99726e3
--- /dev/null
+++ b/lib_avr32/div64.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ *
+ * Based on former do_div() implementation from asm-parisc/div64.h:
+ *	Copyright (C) 1999 Hewlett-Packard Co
+ *	Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ *
+ * Generic C version of 64bit/32bit division and modulo, with
+ * 64bit result and 32bit remainder.
+ *
+ * The fast case for (n>>32 == 0) is handled inline by do_div().
+ *
+ * Code generated for this function might be very inefficient
+ * for some CPUs. __div64_32() can be overridden by linking arch-specific
+ * assembly versions such as arch/ppc/lib/div64.S and arch/sh/lib/div64.S.
+ */
+
+#include <linux/types.h>
+
+#include <asm/div64.h>
+
+uint32_t __div64_32(uint64_t *n, uint32_t base)
+{
+	uint64_t rem = *n;
+	uint64_t b = base;
+	uint64_t res, d = 1;
+	uint32_t high = rem >> 32;
+
+	/* Reduce the thing a bit first */
+	res = 0;
+	if (high >= base) {
+		high /= base;
+		res = (uint64_t) high << 32;
+		rem -= (uint64_t) (high*base) << 32;
+	}
+
+	while ((int64_t)b > 0 && b < rem) {
+		b = b+b;
+		d = d+d;
+	}
+
+	do {
+		if (rem >= b) {
+			rem -= b;
+			res += d;
+		}
+		b >>= 1;
+		d >>= 1;
+	} while (d);
+
+	*n = res;
+	return rem;
+}
diff --git a/lib_avr32/interrupts.c b/lib_avr32/interrupts.c
new file mode 100644
index 0000000..ce538f3
--- /dev/null
+++ b/lib_avr32/interrupts.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/sysreg.h>
+
+void enable_interrupts(void)
+{
+	asm volatile("csrf	%0" : : "n"(SYSREG_GM_OFFSET));
+}
+
+int disable_interrupts(void)
+{
+	unsigned long sr;
+
+	sr = sysreg_read(SR);
+	asm volatile("ssrf	%0" : : "n"(SYSREG_GM_OFFSET));
+
+	return SYSREG_BFEXT(GM, sr);
+}
diff --git a/lib_avr32/memset.S b/lib_avr32/memset.S
new file mode 100644
index 0000000..dc3b09b
--- /dev/null
+++ b/lib_avr32/memset.S
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+	/*
+	 * r12:	void *b
+	 * r11:	int c
+	 * r10:	size_t len
+	 *
+	 * Returns b in r12
+	 */
+	.text
+
+	.global	memset
+	.type	memset, @function
+	.align	2
+memset:
+	mov	r9, r12
+	mov	r8, r12
+	or	r11, r11, r11 << 8
+	andl	r9, 3, COH
+	brne	1f
+
+2:	or	r11, r11, r11 << 16
+	sub	r10, 4
+	brlt	5f
+
+	/* Let's do some real work */
+4:	st.w	r8++, r11
+	sub	r10, 4
+	brge	4b
+
+	/*
+	 * When we get here, we've got less than 4 bytes to set. r10
+	 * might be negative.
+	 */
+5:	sub	r10, -4
+	reteq	r12
+
+	/* Fastpath ends here, exactly 32 bytes from memset */
+
+	/* Handle unaligned count or pointer */
+	bld	r10, 1
+	brcc	6f
+	st.b	r8++, r11
+	st.b	r8++, r11
+	bld	r10, 0
+	retcc	r12
+6:	st.b	r8++, r11
+	mov	pc, lr
+
+	/* Handle unaligned pointer */
+1:	sub	r10, 4
+	brlt	5b
+	add	r10, r9
+	lsl	r9, 1
+	add	pc, r9
+	st.b	r8++, r11
+	st.b	r8++, r11
+	st.b	r8++, r11
+	rjmp	2b
+
+	.size	memset, . - memset
-- 
cgit v0.10.2


From 72a087e04705c26cad982879ebd06b5281bf825a Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue, 24 Oct 2006 14:27:35 +0200
Subject: Add AT32AP CPU and AT32AP7000 SoC support Patch by Haavard
 Skinnemoen, 06 Sep 2006

This patch adds support for the AT32AP CPU family and the AT32AP7000
chip, which is the first chip implementing the AVR32 architecture.

The AT32AP CPU core is a high-performance implementation featuring a
7-stage pipeline, separate instruction- and data caches, and a MMU.
For more information, please see the "AVR32 AP Technical Reference":

http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf

In addition to this, the AT32AP7000 chip comes with a large set of
integrated peripherals, many of which are shared with the AT91 series
of ARM-based microcontrollers from Atmel. Full data sheet is
available here:

http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>

diff --git a/Makefile b/Makefile
index 5260a61..2f3e886 100644
--- a/Makefile
+++ b/Makefile
@@ -2105,6 +2105,9 @@ pb1000_config		: 	unconfig
 #========================================================================
 # AVR32
 #========================================================================
+#########################################################################
+## AT32AP7xxx
+#########################################################################
 
 #########################################################################
 ## MIPS64 5Kc
diff --git a/README b/README
index 8405a9b..69af79a 100644
--- a/README
+++ b/README
@@ -132,6 +132,7 @@ Directory Hierarchy:
   - arm925t	Files specific to ARM 925 CPUs
   - arm926ejs	Files specific to ARM 926 CPUs
   - arm1136	Files specific to ARM 1136 CPUs
+  - at32ap	Files specific to Atmel AVR32 AP CPUs
   - i386	Files specific to i386 CPUs
   - ixp		Files specific to Intel XScale IXP CPUs
   - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
@@ -257,6 +258,9 @@ The following options need to be configured:
 		----------------------
 		CONFIG_NIOS2
 
+		AVR32 based CPUs:
+		----------------------
+		CONFIG_AT32AP
 
 - Board Type:	Define exactly one of
 
diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile
new file mode 100644
index 0000000..8ce79e9
--- /dev/null
+++ b/cpu/at32ap/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2005-2006 Atmel Corporation.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(CPU).a
+
+START	:= start.o
+SOBJS	:= entry.o
+COBJS	:= cpu.o hsdramc.o exception.o cache.o
+COBJS	+= interrupts.o device.o pm.o pio.o
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+	$(AR) crv $@ $^
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/at32ap/at32ap7000/Makefile b/cpu/at32ap/at32ap7000/Makefile
new file mode 100644
index 0000000..1cd9444
--- /dev/null
+++ b/cpu/at32ap/at32ap7000/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(SOC).a
+
+COBJS	:= hebi.o devices.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+	$(AR) crv $@ $^
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/at32ap/at32ap7000/devices.c b/cpu/at32ap/at32ap7000/devices.c
new file mode 100644
index 0000000..8b216e9
--- /dev/null
+++ b/cpu/at32ap/at32ap7000/devices.c
@@ -0,0 +1,448 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+#include "../sm.h"
+
+#define ARRAY_SIZE(x)	(sizeof(x) / sizeof((x)[0]))
+
+const struct clock_domain chip_clock[] = {
+	[CLOCK_CPU] = {
+		.reg	= SM_PM_CPU_MASK,
+		.id	= CLOCK_CPU,
+		.bridge	= NO_DEVICE,
+	},
+	[CLOCK_HSB] = {
+		.reg	= SM_PM_HSB_MASK,
+		.id	= CLOCK_HSB,
+		.bridge	= NO_DEVICE,
+	},
+	[CLOCK_PBA] = {
+		.reg	= SM_PM_PBA_MASK,
+		.id	= CLOCK_PBA,
+		.bridge	= DEVICE_PBA_BRIDGE,
+	},
+	[CLOCK_PBB] = {
+		.reg	= SM_PM_PBB_MASK,
+		.id	= CLOCK_PBB,
+		.bridge	= DEVICE_PBB_BRIDGE,
+	},
+};
+
+static const struct resource hebi_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_HSB, 0 },
+		},
+	}, {
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBB, 13 },
+		},
+	}, {
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBB, 14 },
+		},
+	}, {
+		.type	= RESOURCE_GPIO,
+		.u	= {
+			.gpio	= { 27, DEVICE_PIOE, GPIO_FUNC_A, 0 },
+		},
+	},
+};
+static const struct resource pba_bridge_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_HSB, 1 },
+		}
+	}, {
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			/* HSB-HSB Bridge */
+			.clock	= { CLOCK_HSB, 4 },
+		},
+	},
+};
+static const struct resource pbb_bridge_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_HSB, 2 },
+		},
+	},
+};
+static const struct resource hramc_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_HSB, 3 },
+		},
+	},
+};
+static const struct resource pioa_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBA, 10 },
+		},
+	},
+};
+static const struct resource piob_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBA, 11 },
+		},
+	},
+};
+static const struct resource pioc_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBA, 12 },
+		},
+	},
+};
+static const struct resource piod_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBA, 13 },
+		},
+	},
+};
+static const struct resource pioe_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBA, 14 },
+		},
+	},
+};
+static const struct resource sm_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBB, 0 },
+		},
+	},
+};
+static const struct resource intc_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock = { CLOCK_PBB, 1 },
+		},
+	},
+};
+static const struct resource hmatrix_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock = { CLOCK_PBB, 2 },
+		},
+	},
+};
+#if defined(CFG_HPDC)
+static const struct resource hpdc_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBA, 16 },
+		},
+	},
+};
+#endif
+#if defined(CFG_MACB0)
+static const struct resource macb0_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_HSB, 8 },
+		},
+	}, {
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBB, 6 },
+		},
+	}, {
+		.type	= RESOURCE_GPIO,
+		.u	= {
+			.gpio	= { 19, DEVICE_PIOC, GPIO_FUNC_A, 0 },
+		},
+	},
+};
+#endif
+#if defined(CFG_MACB1)
+static const struct resource macb1_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_HSB, 9 },
+		},
+	}, {
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBB, 7 },
+		},
+	}, {
+		.type	= RESOURCE_GPIO,
+		.u	= {
+			.gpio	= { 12, DEVICE_PIOC, GPIO_FUNC_B, 19 },
+		},
+	}, {
+		.type	= RESOURCE_GPIO,
+		.u	= {
+			.gpio	= { 14, DEVICE_PIOD, GPIO_FUNC_B, 2 },
+		},
+	},
+};
+#endif
+#if defined(CFG_LCDC)
+static const struct resource lcdc_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_HSB, 7 },
+		},
+	},
+};
+#endif
+#if defined(CFG_USART0)
+static const struct resource usart0_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBA, 3 },
+		},
+	}, {
+		.type	= RESOURCE_GPIO,
+		.u	= {
+			.gpio = { 2, DEVICE_PIOA, GPIO_FUNC_B, 8 },
+		},
+	},
+};
+#endif
+#if defined(CFG_USART1)
+static const struct resource usart1_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBA, 4 },
+		},
+	}, {
+		.type	= RESOURCE_GPIO,
+		.u	= {
+			.gpio = { 2, DEVICE_PIOA, GPIO_FUNC_A, 17 },
+		},
+	},
+};
+#endif
+#if defined(CFG_USART2)
+static const struct resource usart2_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBA, 5 },
+		},
+	}, {
+		.type	= RESOURCE_GPIO,
+		.u	= {
+			.gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 26 },
+		},
+	},
+};
+#endif
+#if defined(CFG_USART3)
+static const struct resource usart3_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBA, 6 },
+		},
+	}, {
+		.type	= RESOURCE_GPIO,
+		.u	= {
+			.gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 17 },
+		},
+	},
+};
+#endif
+#if defined(CFG_MMCI)
+static const struct resource mmci_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_PBB, 9 },
+		},
+	}, {
+		.type	= RESOURCE_GPIO,
+		.u	= {
+			.gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 10 },
+		},
+	},
+};
+#endif
+#if defined(CFG_DMAC)
+static const struct resource dmac_resource[] = {
+	{
+		.type	= RESOURCE_CLOCK,
+		.u	= {
+			.clock	= { CLOCK_HSB, 10 },
+		},
+	},
+};
+#endif
+
+const struct device chip_device[] = {
+	[DEVICE_HEBI] = {
+		.regs		= (void *)HSMC_BASE,
+		.nr_resources	= ARRAY_SIZE(hebi_resource),
+		.resource	= hebi_resource,
+	},
+	[DEVICE_PBA_BRIDGE] = {
+		.nr_resources	= ARRAY_SIZE(pba_bridge_resource),
+		.resource	= pba_bridge_resource,
+	},
+	[DEVICE_PBB_BRIDGE] = {
+		.nr_resources	= ARRAY_SIZE(pbb_bridge_resource),
+		.resource	= pbb_bridge_resource,
+	},
+	[DEVICE_HRAMC] = {
+		.nr_resources	= ARRAY_SIZE(hramc_resource),
+		.resource	= hramc_resource,
+	},
+	[DEVICE_PIOA] = {
+		.regs		= (void *)PIOA_BASE,
+		.nr_resources	= ARRAY_SIZE(pioa_resource),
+		.resource	= pioa_resource,
+	},
+	[DEVICE_PIOB] = {
+		.regs		= (void *)PIOB_BASE,
+		.nr_resources	= ARRAY_SIZE(piob_resource),
+		.resource	= piob_resource,
+	},
+	[DEVICE_PIOC] = {
+		.regs		= (void *)PIOC_BASE,
+		.nr_resources	= ARRAY_SIZE(pioc_resource),
+		.resource	= pioc_resource,
+	},
+	[DEVICE_PIOD] = {
+		.regs		= (void *)PIOD_BASE,
+		.nr_resources	= ARRAY_SIZE(piod_resource),
+		.resource	= piod_resource,
+	},
+	[DEVICE_PIOE] = {
+		.regs		= (void *)PIOE_BASE,
+		.nr_resources	= ARRAY_SIZE(pioe_resource),
+		.resource	= pioe_resource,
+	},
+	[DEVICE_SM] = {
+		.regs		= (void *)SM_BASE,
+		.nr_resources	= ARRAY_SIZE(sm_resource),
+		.resource	= sm_resource,
+	},
+	[DEVICE_INTC] = {
+		.regs		= (void *)INTC_BASE,
+		.nr_resources	= ARRAY_SIZE(intc_resource),
+		.resource	= intc_resource,
+	},
+	[DEVICE_HMATRIX] = {
+		.regs		= (void *)HMATRIX_BASE,
+		.nr_resources	= ARRAY_SIZE(hmatrix_resource),
+		.resource	= hmatrix_resource,
+	},
+#if defined(CFG_HPDC)
+	[DEVICE_HPDC] = {
+		.nr_resources	= ARRAY_SIZE(hpdc_resource),
+		.resource	= hpdc_resource,
+	},
+#endif
+#if defined(CFG_MACB0)
+	[DEVICE_MACB0] = {
+		.regs		= (void *)MACB0_BASE,
+		.nr_resources	= ARRAY_SIZE(macb0_resource),
+		.resource	= macb0_resource,
+	},
+#endif
+#if defined(CFG_MACB1)
+	[DEVICE_MACB1] = {
+		.regs		= (void *)MACB1_BASE,
+		.nr_resources	= ARRAY_SIZE(macb1_resource),
+		.resource	= macb1_resource,
+	},
+#endif
+#if defined(CFG_LCDC)
+	[DEVICE_LCDC] = {
+		.nr_resources	= ARRAY_SIZE(lcdc_resource),
+		.resource	= lcdc_resource,
+	},
+#endif
+#if defined(CFG_USART0)
+	[DEVICE_USART0] = {
+		.regs		= (void *)USART0_BASE,
+		.nr_resources	= ARRAY_SIZE(usart0_resource),
+		.resource	= usart0_resource,
+	},
+#endif
+#if defined(CFG_USART1)
+	[DEVICE_USART1] = {
+		.regs		= (void *)USART1_BASE,
+		.nr_resources	= ARRAY_SIZE(usart1_resource),
+		.resource	= usart1_resource,
+	},
+#endif
+#if defined(CFG_USART2)
+	[DEVICE_USART2] = {
+		.regs		= (void *)USART2_BASE,
+		.nr_resources	= ARRAY_SIZE(usart2_resource),
+		.resource	= usart2_resource,
+	},
+#endif
+#if defined(CFG_USART3)
+	[DEVICE_USART3] = {
+		.regs		= (void *)USART3_BASE,
+		.nr_resources	= ARRAY_SIZE(usart3_resource),
+		.resource	= usart3_resource,
+	},
+#endif
+#if defined(CFG_MMCI)
+	[DEVICE_MMCI] = {
+		.regs		= (void *)MMCI_BASE,
+		.nr_resources	= ARRAY_SIZE(mmci_resource),
+		.resource	= mmci_resource,
+	},
+#endif
+#if defined(CFG_DMAC)
+	[DEVICE_DMAC] = {
+		.regs		= (void *)DMAC_BASE,
+		.nr_resources	= ARRAY_SIZE(dmac_resource),
+		.resource	= dmac_resource,
+	},
+#endif
+};
diff --git a/cpu/at32ap/at32ap7000/hebi.c b/cpu/at32ap/at32ap7000/hebi.c
new file mode 100644
index 0000000..3b32adf
--- /dev/null
+++ b/cpu/at32ap/at32ap7000/hebi.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/hmatrix2.h>
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+void cpu_enable_sdram(void)
+{
+	const struct device *hmatrix;
+
+	hmatrix = get_device(DEVICE_HMATRIX);
+
+	/* Set the SDRAM_ENABLE bit in the HEBI SFR */
+	hmatrix2_writel(hmatrix, SFR4, 1 << 1);
+}
diff --git a/cpu/at32ap/cache.c b/cpu/at32ap/cache.c
new file mode 100644
index 0000000..41fb5aa
--- /dev/null
+++ b/cpu/at32ap/cache.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/cacheflush.h>
+
+void dcache_clean_range(volatile void *start, size_t size)
+{
+	unsigned long v, begin, end, linesz;
+
+	linesz = CFG_DCACHE_LINESZ;
+
+	/* You asked for it, you got it */
+	begin = (unsigned long)start & ~(linesz - 1);
+	end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+	for (v = begin; v < end; v += linesz)
+		dcache_clean_line((void *)v);
+
+	sync_write_buffer();
+}
+
+void dcache_invalidate_range(volatile void *start, size_t size)
+{
+	unsigned long v, begin, end, linesz;
+
+	linesz = CFG_DCACHE_LINESZ;
+
+	/* You asked for it, you got it */
+	begin = (unsigned long)start & ~(linesz - 1);
+	end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+	for (v = begin; v < end; v += linesz)
+		dcache_invalidate_line((void *)v);
+}
+
+void dcache_flush_range(volatile void *start, size_t size)
+{
+	unsigned long v, begin, end, linesz;
+
+	linesz = CFG_DCACHE_LINESZ;
+
+	/* You asked for it, you got it */
+	begin = (unsigned long)start & ~(linesz - 1);
+	end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+	for (v = begin; v < end; v += linesz)
+		dcache_flush_line((void *)v);
+
+	sync_write_buffer();
+}
+
+void icache_invalidate_range(volatile void *start, size_t size)
+{
+	unsigned long v, begin, end, linesz;
+
+	linesz = CFG_ICACHE_LINESZ;
+
+	/* You asked for it, you got it */
+	begin = (unsigned long)start & ~(linesz - 1);
+	end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+	for (v = begin; v < end; v += linesz)
+		icache_invalidate_line((void *)v);
+}
+
+/*
+ * This is called after loading something into memory.  We need to
+ * make sure that everything that was loaded is actually written to
+ * RAM, and that the icache will look for it. Cleaning the dcache and
+ * invalidating the icache will do the trick.
+ */
+void  flush_cache (unsigned long start_addr, unsigned long size)
+{
+	dcache_clean_range((void *)start_addr, size);
+	icache_invalidate_range((void *)start_addr, size);
+}
diff --git a/cpu/at32ap/config.mk b/cpu/at32ap/config.mk
new file mode 100644
index 0000000..1c12169
--- /dev/null
+++ b/cpu/at32ap/config.mk
@@ -0,0 +1,22 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS       += -mcpu=ap7000
diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c
new file mode 100644
index 0000000..37e3ea0
--- /dev/null
+++ b/cpu/at32ap/cpu.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+
+#include <asm/io.h>
+#include <asm/sections.h>
+#include <asm/sysreg.h>
+
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+#include "hsmc3.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cpu_init(void)
+{
+	const struct device *hebi;
+	extern void _evba(void);
+	char *p;
+
+	gd->cpu_hz = CFG_OSC0_HZ;
+
+	/* fff03400: 00010001 04030402 00050005 10011103 */
+	hebi = get_device(DEVICE_HEBI);
+	hsmc3_writel(hebi, MODE0, 0x00031103);
+	hsmc3_writel(hebi, CYCLE0, 0x000c000d);
+	hsmc3_writel(hebi, PULSE0, 0x0b0a0906);
+	hsmc3_writel(hebi, SETUP0, 0x00010002);
+
+	pm_init();
+
+	sysreg_write(EVBA, (unsigned long)&_evba);
+	asm volatile("csrf	%0" : : "i"(SYSREG_EM_OFFSET));
+	gd->console_uart = get_device(CFG_CONSOLE_UART_DEV);
+
+	/* Lock everything that mess with the flash in the icache */
+	for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);
+	     p += CFG_ICACHE_LINESZ)
+		asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
+
+	return 0;
+}
+
+void prepare_to_boot(void)
+{
+	/* Flush both caches and the write buffer */
+	asm volatile("cache  %0[4], 010\n\t"
+		     "cache  %0[0], 000\n\t"
+		     "sync   0" : : "r"(0) : "memory");
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	/* This will reset the CPU core, caches, MMU and all internal busses */
+	__builtin_mtdr(8, 1 << 13);	/* set DC:DBE */
+	__builtin_mtdr(8, 1 << 30);	/* set DC:RES */
+
+	/* Flush the pipeline before we declare it a failure */
+	asm volatile("sub   pc, pc, -4");
+
+	return -1;
+}
diff --git a/cpu/at32ap/device.c b/cpu/at32ap/device.c
new file mode 100644
index 0000000..89914b6
--- /dev/null
+++ b/cpu/at32ap/device.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/arch/platform.h>
+
+#include "sm.h"
+
+struct device_state {
+	int refcount;
+};
+
+static struct device_state device_state[NR_DEVICES];
+
+static int claim_resource(const struct resource *res)
+{
+	int ret = 0;
+
+	switch (res->type) {
+	case RESOURCE_GPIO:
+		ret = gpio_set_func(res->u.gpio.gpio_dev,
+				    res->u.gpio.start,
+				    res->u.gpio.nr_pins,
+				    res->u.gpio.func);
+		break;
+	case RESOURCE_CLOCK:
+		ret = pm_enable_clock(res->u.clock.id, res->u.clock.index);
+		break;
+	}
+
+	return ret;
+}
+
+static void free_resource(const struct resource *res)
+{
+	switch (res->type) {
+	case RESOURCE_GPIO:
+		gpio_free(res->u.gpio.gpio_dev, res->u.gpio.start,
+			  res->u.gpio.nr_pins);
+		break;
+	case RESOURCE_CLOCK:
+		pm_disable_clock(res->u.clock.id, res->u.clock.index);
+		break;
+	}
+}
+
+static int init_dev(const struct device *dev)
+{
+	unsigned int i;
+	int ret = 0;
+
+	for (i = 0; i < dev->nr_resources; i++) {
+		ret = claim_resource(&dev->resource[i]);
+		if (ret)
+			goto cleanup;
+	}
+
+	return 0;
+
+cleanup:
+	while (i--)
+		free_resource(&dev->resource[i]);
+
+	return ret;
+}
+
+const struct device *get_device(enum device_id devid)
+{
+	struct device_state *devstate;
+	const struct device *dev;
+	unsigned long flags;
+	int initialized = 0;
+	int ret = 0;
+
+	devstate = &device_state[devid];
+	dev = &chip_device[devid];
+
+	flags = disable_interrupts();
+	if (devstate->refcount++)
+		initialized = 1;
+	if (flags)
+		enable_interrupts();
+
+	if (!initialized)
+		ret = init_dev(dev);
+
+	return ret ? NULL : dev;
+}
+
+void put_device(const struct device *dev)
+{
+	struct device_state *devstate;
+	unsigned long devid, flags;
+
+	devid = (unsigned long)(dev - chip_device) / sizeof(struct device);
+	devstate = &device_state[devid];
+
+	flags = disable_interrupts();
+	devstate--;
+	if (!devstate) {
+		unsigned int i;
+		for (i = 0; i < dev->nr_resources; i++)
+			free_resource(&dev->resource[i]);
+	}
+	if (flags)
+		enable_interrupts();
+}
diff --git a/cpu/at32ap/entry.S b/cpu/at32ap/entry.S
new file mode 100644
index 0000000..b52d798
--- /dev/null
+++ b/cpu/at32ap/entry.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/sysreg.h>
+#include <asm/ptrace.h>
+
+	.section .text.exception,"ax"
+	.global	_evba
+	.type	_evba,@function
+	.align	10
+_evba:
+	.irp	x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
+	.align	2
+	rjmp	unknown_exception
+	.endr
+
+	.global	timer_interrupt_handler
+	.type	timer_interrupt_handler,@function
+	.align	2
+timer_interrupt_handler:
+	/*
+	 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
+	 *
+	 * We're running at interrupt level 3, so we don't need to save
+	 * r8-r12 or lr to the stack.
+	 */
+	mov	r8, lo(timer_overflow)
+	orh	r8, hi(timer_overflow)
+	ld.w	r9, r8[0]
+	mov	r10, -1
+	mtsr	SYSREG_COMPARE, r10
+	sub	r9, -1
+	st.w	r8[0], r9
+	rete
+
+	.type	unknown_exception, @function
+unknown_exception:
+	pushm	r0-r12
+	sub	r8, sp, REG_R12 - REG_R0 - 4
+	mov	r9, lr
+	mfsr	r10, SYSREG_RAR_EX
+	mfsr	r11, SYSREG_RSR_EX
+	pushm	r8-r11
+	mfsr	r12, SYSREG_ECR
+	mov	r11, sp
+	rcall	do_unknown_exception
+1:	rjmp	1b
diff --git a/cpu/at32ap/exception.c b/cpu/at32ap/exception.c
new file mode 100644
index 0000000..4123c44
--- /dev/null
+++ b/cpu/at32ap/exception.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/sysreg.h>
+#include <asm/ptrace.h>
+
+static const char * const cpu_modes[8] = {
+	"Application", "Supervisor", "Interrupt level 0", "Interrupt level 1",
+	"Interrupt level 2", "Interrupt level 3", "Exception", "NMI"
+};
+
+static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
+{
+	unsigned long p;
+	int i;
+
+	printf("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
+
+	for (p = bottom & ~31; p < top; ) {
+		printf("%04lx: ", p & 0xffff);
+
+		for (i = 0; i < 8; i++, p += 4) {
+			unsigned int val;
+
+			if (p < bottom || p >= top)
+				printf("         ");
+			else {
+				val = *(unsigned long *)p;
+				printf("%08x ", val);
+			}
+		}
+		printf("\n");
+	}
+}
+
+void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
+{
+	unsigned int mode;
+
+	printf("\n *** Unhandled exception %u at PC=0x%08lx\n", ecr, regs->pc);
+
+	switch (ecr) {
+	case ECR_BUS_ERROR_WRITE:
+	case ECR_BUS_ERROR_READ:
+		printf("Bus error at address 0x%08lx\n",
+		       sysreg_read(BEAR));
+		break;
+	case ECR_TLB_MULTIPLE:
+	case ECR_ADDR_ALIGN_X:
+	case ECR_PROTECTION_X:
+	case ECR_ADDR_ALIGN_R:
+	case ECR_ADDR_ALIGN_W:
+	case ECR_PROTECTION_R:
+	case ECR_PROTECTION_W:
+	case ECR_DTLB_MODIFIED:
+	case ECR_TLB_MISS_X:
+	case ECR_TLB_MISS_R:
+	case ECR_TLB_MISS_W:
+		printf("MMU exception at address 0x%08lx\n",
+		       sysreg_read(TLBEAR));
+		break;
+	}
+
+	printf("   pc: %08lx    lr: %08lx    sp: %08lx   r12: %08lx\n",
+	       regs->pc, regs->lr, regs->sp, regs->r12);
+	printf("  r11: %08lx   r10: %08lx    r9: %08lx    r8: %08lx\n",
+	       regs->r11, regs->r10, regs->r9, regs->r8);
+	printf("   r7: %08lx    r6: %08lx    r5: %08lx    r4: %08lx\n",
+	       regs->r7, regs->r6, regs->r5, regs->r4);
+	printf("   r3: %08lx    r2: %08lx    r1: %08lx    r0: %08lx\n",
+	       regs->r3, regs->r2, regs->r1, regs->r0);
+	printf("Flags: %c%c%c%c%c\n",
+	       regs->sr & SR_Q ? 'Q' : 'q',
+	       regs->sr & SR_V ? 'V' : 'v',
+	       regs->sr & SR_N ? 'N' : 'n',
+	       regs->sr & SR_Z ? 'Z' : 'z',
+	       regs->sr & SR_C ? 'C' : 'c');
+	printf("Mode bits: %c%c%c%c%c%c%c%c%c\n",
+	       regs->sr & SR_H ? 'H' : 'h',
+	       regs->sr & SR_R ? 'R' : 'r',
+	       regs->sr & SR_J ? 'J' : 'j',
+	       regs->sr & SR_EM ? 'E' : 'e',
+	       regs->sr & SR_I3M ? '3' : '.',
+	       regs->sr & SR_I2M ? '2' : '.',
+	       regs->sr & SR_I1M ? '1' : '.',
+	       regs->sr & SR_I0M ? '0' : '.',
+	       regs->sr & SR_GM ? 'G' : 'g');
+	mode = (regs->sr >> SYSREG_M0_OFFSET) & 7;
+	printf("CPU Mode: %s\n", cpu_modes[mode]);
+
+	/* Avoid exception loops */
+	if (regs->sp >= CFG_INIT_SP_ADDR
+	    || regs->sp < (CFG_INIT_SP_ADDR - CONFIG_STACKSIZE))
+		printf("\nStack pointer seems bogus, won't do stack dump\n");
+	else
+		dump_mem("\nStack: ", regs->sp, CFG_INIT_SP_ADDR);
+
+	panic("Unhandled exception\n");
+}
diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c
new file mode 100644
index 0000000..f36da35
--- /dev/null
+++ b/cpu/at32ap/hsdramc.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CFG_HSDRAMC
+#include <asm/io.h>
+#include <asm/sdram.h>
+
+#include <asm/arch/platform.h>
+
+#include "hsdramc1.h"
+
+struct hsdramc {
+	const struct device *hebi;
+	void *regs;
+};
+
+static struct hsdramc hsdramc;
+
+unsigned long sdram_init(const struct sdram_info *info)
+{
+	unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
+	unsigned long sdram_size;
+	unsigned long tmp;
+	unsigned long bus_hz;
+	unsigned int i;
+
+	hsdramc.hebi = get_device(DEVICE_HEBI);
+	if (!hsdramc.hebi)
+		return 0;
+
+	/* FIXME: Both of these lines are complete hacks */
+	hsdramc.regs = hsdramc.hebi->regs + 0x400;
+	bus_hz = pm_get_clock_freq(hsdramc.hebi->resource[0].u.clock.id);
+
+	cpu_enable_sdram();
+
+	tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
+	       | HSDRAMC1_BF(NR, info->row_bits - 11)
+	       | HSDRAMC1_BF(NB, info->bank_bits - 1)
+	       | HSDRAMC1_BF(CAS, info->cas)
+	       | HSDRAMC1_BF(TWR, info->twr)
+	       | HSDRAMC1_BF(TRC, info->trc)
+	       | HSDRAMC1_BF(TRP, info->trp)
+	       | HSDRAMC1_BF(TRCD, info->trcd)
+	       | HSDRAMC1_BF(TRAS, info->tras)
+	       | HSDRAMC1_BF(TXSR, info->txsr));
+
+#ifdef CFG_SDRAM_16BIT
+	tmp |= HSDRAMC1_BIT(DBW);
+	sdram_size = 1 << (info->row_bits + info->col_bits
+			   + info->bank_bits + 1);
+#else
+	sdram_size = 1 << (info->row_bits + info->col_bits
+			   + info->bank_bits + 2);
+#endif
+
+	hsdramc1_writel(&hsdramc, CR, tmp);
+
+	/*
+	 * Initialization sequence for SDRAM, from the data sheet:
+	 *
+	 * 1. A minimum pause of 200 us is provided to precede any
+	 *    signal toggle.
+	 */
+	udelay(200);
+
+	/*
+	 * 2. A Precharge All command is issued to the SDRAM
+	 */
+	hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
+	hsdramc1_readl(&hsdramc, MR);
+	writel(0, sdram);
+
+	/*
+	 * 3. Eight auto-refresh (CBR) cycles are provided
+	 */
+	hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_AUTO_REFRESH);
+	hsdramc1_readl(&hsdramc, MR);
+	for (i = 0; i < 8; i++)
+		writel(0, sdram);
+
+	/*
+	 * 4. A mode register set (MRS) cycle is issued to program
+	 *    SDRAM parameters, in particular CAS latency and burst
+	 *    length.
+	 *
+	 * CAS from info struct, burst length 1, serial burst type
+	 */
+	hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_LOAD_MODE);
+	hsdramc1_readl(&hsdramc, MR);
+	writel(0, sdram + (info->cas << 4));
+
+	/*
+	 * 5. A Normal Mode command is provided, 3 clocks after tMRD
+	 *    is met.
+	 *
+	 * From the timing diagram, it looks like tMRD is 3
+	 * cycles...try a dummy read from the peripheral bus.
+	 */
+	hsdramc1_readl(&hsdramc, MR);
+	hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_NORMAL);
+	hsdramc1_readl(&hsdramc, MR);
+	writel(0, sdram);
+
+	/*
+	 * 6. Write refresh rate into SDRAMC refresh timer count
+	 *    register (refresh rate = timing between refresh cycles).
+	 *
+	 * 15.6 us is a typical value for a burst of length one
+	 */
+	hsdramc1_writel(&hsdramc, TR, (156 * (bus_hz / 1000)) / 10000);
+
+	printf("SDRAM: %u MB at address 0x%08lx\n",
+	       sdram_size >> 20, info->phys_addr);
+
+	printf("Testing SDRAM...");
+	for (i = 0; i < sdram_size / 4; i++)
+		sdram[i] = i;
+
+	for (i = 0; i < sdram_size / 4; i++) {
+		tmp = sdram[i];
+		if (tmp != i) {
+			printf("FAILED at address 0x%08lx\n",
+			       info->phys_addr + i * 4);
+			printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
+			return 0;
+		}
+	}
+
+	puts("OK\n");
+
+	return sdram_size;
+}
+
+#endif /* CFG_HSDRAMC */
diff --git a/cpu/at32ap/hsdramc1.h b/cpu/at32ap/hsdramc1.h
new file mode 100644
index 0000000..ce229bc
--- /dev/null
+++ b/cpu/at32ap/hsdramc1.h
@@ -0,0 +1,143 @@
+/*
+ * Register definitions for SDRAM Controller
+ */
+#ifndef __ASM_AVR32_HSDRAMC1_H__
+#define __ASM_AVR32_HSDRAMC1_H__
+
+/* HSDRAMC1 register offsets */
+#define HSDRAMC1_MR				0x0000
+#define HSDRAMC1_TR				0x0004
+#define HSDRAMC1_CR				0x0008
+#define HSDRAMC1_HSR				0x000c
+#define HSDRAMC1_LPR				0x0010
+#define HSDRAMC1_IER				0x0014
+#define HSDRAMC1_IDR				0x0018
+#define HSDRAMC1_IMR				0x001c
+#define HSDRAMC1_ISR				0x0020
+#define HSDRAMC1_MDR				0x0024
+#define HSDRAMC1_VERSION			0x00fc
+
+/* Bitfields in MR */
+#define HSDRAMC1_MODE_OFFSET			0
+#define HSDRAMC1_MODE_SIZE			3
+
+/* Bitfields in TR */
+#define HSDRAMC1_COUNT_OFFSET			0
+#define HSDRAMC1_COUNT_SIZE			12
+
+/* Bitfields in CR */
+#define HSDRAMC1_NC_OFFSET			0
+#define HSDRAMC1_NC_SIZE			2
+#define HSDRAMC1_NR_OFFSET			2
+#define HSDRAMC1_NR_SIZE			2
+#define HSDRAMC1_NB_OFFSET			4
+#define HSDRAMC1_NB_SIZE			1
+#define HSDRAMC1_CAS_OFFSET			5
+#define HSDRAMC1_CAS_SIZE			2
+#define HSDRAMC1_DBW_OFFSET			7
+#define HSDRAMC1_DBW_SIZE			1
+#define HSDRAMC1_TWR_OFFSET			8
+#define HSDRAMC1_TWR_SIZE			4
+#define HSDRAMC1_TRC_OFFSET			12
+#define HSDRAMC1_TRC_SIZE			4
+#define HSDRAMC1_TRP_OFFSET			16
+#define HSDRAMC1_TRP_SIZE			4
+#define HSDRAMC1_TRCD_OFFSET			20
+#define HSDRAMC1_TRCD_SIZE			4
+#define HSDRAMC1_TRAS_OFFSET			24
+#define HSDRAMC1_TRAS_SIZE			4
+#define HSDRAMC1_TXSR_OFFSET			28
+#define HSDRAMC1_TXSR_SIZE			4
+
+/* Bitfields in HSR */
+#define HSDRAMC1_DA_OFFSET			0
+#define HSDRAMC1_DA_SIZE			1
+
+/* Bitfields in LPR */
+#define HSDRAMC1_LPCB_OFFSET			0
+#define HSDRAMC1_LPCB_SIZE			2
+#define HSDRAMC1_PASR_OFFSET			4
+#define HSDRAMC1_PASR_SIZE			3
+#define HSDRAMC1_TCSR_OFFSET			8
+#define HSDRAMC1_TCSR_SIZE			2
+#define HSDRAMC1_DS_OFFSET			10
+#define HSDRAMC1_DS_SIZE			2
+#define HSDRAMC1_TIMEOUT_OFFSET			12
+#define HSDRAMC1_TIMEOUT_SIZE			2
+
+/* Bitfields in IDR */
+#define HSDRAMC1_RES_OFFSET			0
+#define HSDRAMC1_RES_SIZE			1
+
+/* Bitfields in MDR */
+#define HSDRAMC1_MD_OFFSET			0
+#define HSDRAMC1_MD_SIZE			2
+
+/* Bitfields in VERSION */
+#define HSDRAMC1_VERSION_OFFSET			0
+#define HSDRAMC1_VERSION_SIZE			12
+#define HSDRAMC1_MFN_OFFSET			16
+#define HSDRAMC1_MFN_SIZE			3
+
+/* Constants for MODE */
+#define HSDRAMC1_MODE_NORMAL			0
+#define HSDRAMC1_MODE_NOP			1
+#define HSDRAMC1_MODE_BANKS_PRECHARGE		2
+#define HSDRAMC1_MODE_LOAD_MODE			3
+#define HSDRAMC1_MODE_AUTO_REFRESH		4
+#define HSDRAMC1_MODE_EXT_LOAD_MODE		5
+#define HSDRAMC1_MODE_POWER_DOWN		6
+
+/* Constants for NC */
+#define HSDRAMC1_NC_8_COLUMN_BITS		0
+#define HSDRAMC1_NC_9_COLUMN_BITS		1
+#define HSDRAMC1_NC_10_COLUMN_BITS		2
+#define HSDRAMC1_NC_11_COLUMN_BITS		3
+
+/* Constants for NR */
+#define HSDRAMC1_NR_11_ROW_BITS			0
+#define HSDRAMC1_NR_12_ROW_BITS			1
+#define HSDRAMC1_NR_13_ROW_BITS			2
+
+/* Constants for NB */
+#define HSDRAMC1_NB_TWO_BANKS			0
+#define HSDRAMC1_NB_FOUR_BANKS			1
+
+/* Constants for CAS */
+#define HSDRAMC1_CAS_ONE_CYCLE			1
+#define HSDRAMC1_CAS_TWO_CYCLES			2
+
+/* Constants for DBW */
+#define HSDRAMC1_DBW_32_BITS			0
+#define HSDRAMC1_DBW_16_BITS			1
+
+/* Constants for TIMEOUT */
+#define HSDRAMC1_TIMEOUT_AFTER_END		0
+#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END	1
+#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END	2
+
+/* Constants for MD */
+#define HSDRAMC1_MD_SDRAM			0
+#define HSDRAMC1_MD_LOW_POWER_SDRAM		1
+
+/* Bit manipulation macros */
+#define HSDRAMC1_BIT(name)					\
+	(1 << HSDRAMC1_##name##_OFFSET)
+#define HSDRAMC1_BF(name,value)					\
+	(((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1))	\
+	 << HSDRAMC1_##name##_OFFSET)
+#define HSDRAMC1_BFEXT(name,value)				\
+	(((value) >> HSDRAMC1_##name##_OFFSET)			\
+	 & ((1 << HSDRAMC1_##name##_SIZE) - 1))
+#define HSDRAMC1_BFINS(name,value,old)				\
+	(((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1)		\
+		    << HSDRAMC1_##name##_OFFSET))		\
+	 | HSDRAMC1_BF(name,value))
+
+/* Register access macros */
+#define hsdramc1_readl(port,reg)				\
+	readl((port)->regs + HSDRAMC1_##reg)
+#define hsdramc1_writel(port,reg,value)				\
+	writel((value), (port)->regs + HSDRAMC1_##reg)
+
+#endif /* __ASM_AVR32_HSDRAMC1_H__ */
diff --git a/cpu/at32ap/hsmc3.h b/cpu/at32ap/hsmc3.h
new file mode 100644
index 0000000..ec78cee
--- /dev/null
+++ b/cpu/at32ap/hsmc3.h
@@ -0,0 +1,126 @@
+/*
+ * Register definitions for Static Memory Controller
+ */
+#ifndef __CPU_AT32AP_HSMC3_H__
+#define __CPU_AT32AP_HSMC3_H__
+
+/* HSMC3 register offsets */
+#define HSMC3_SETUP0				0x0000
+#define HSMC3_PULSE0				0x0004
+#define HSMC3_CYCLE0				0x0008
+#define HSMC3_MODE0				0x000c
+#define HSMC3_SETUP1				0x0010
+#define HSMC3_PULSE1				0x0014
+#define HSMC3_CYCLE1				0x0018
+#define HSMC3_MODE1				0x001c
+#define HSMC3_SETUP2				0x0020
+#define HSMC3_PULSE2				0x0024
+#define HSMC3_CYCLE2				0x0028
+#define HSMC3_MODE2				0x002c
+#define HSMC3_SETUP3				0x0030
+#define HSMC3_PULSE3				0x0034
+#define HSMC3_CYCLE3				0x0038
+#define HSMC3_MODE3				0x003c
+#define HSMC3_SETUP4				0x0040
+#define HSMC3_PULSE4				0x0044
+#define HSMC3_CYCLE4				0x0048
+#define HSMC3_MODE4				0x004c
+#define HSMC3_SETUP5				0x0050
+#define HSMC3_PULSE5				0x0054
+#define HSMC3_CYCLE5				0x0058
+#define HSMC3_MODE5				0x005c
+
+/* Bitfields in SETUP0 */
+#define HSMC3_NWE_SETUP_OFFSET			0
+#define HSMC3_NWE_SETUP_SIZE			6
+#define HSMC3_NCS_WR_SETUP_OFFSET		8
+#define HSMC3_NCS_WR_SETUP_SIZE			6
+#define HSMC3_NRD_SETUP_OFFSET			16
+#define HSMC3_NRD_SETUP_SIZE			6
+#define HSMC3_NCS_RD_SETUP_OFFSET		24
+#define HSMC3_NCS_RD_SETUP_SIZE			6
+
+/* Bitfields in PULSE0 */
+#define HSMC3_NWE_PULSE_OFFSET			0
+#define HSMC3_NWE_PULSE_SIZE			7
+#define HSMC3_NCS_WR_PULSE_OFFSET		8
+#define HSMC3_NCS_WR_PULSE_SIZE			7
+#define HSMC3_NRD_PULSE_OFFSET			16
+#define HSMC3_NRD_PULSE_SIZE			7
+#define HSMC3_NCS_RD_PULSE_OFFSET		24
+#define HSMC3_NCS_RD_PULSE_SIZE			7
+
+/* Bitfields in CYCLE0 */
+#define HSMC3_NWE_CYCLE_OFFSET			0
+#define HSMC3_NWE_CYCLE_SIZE			9
+#define HSMC3_NRD_CYCLE_OFFSET			16
+#define HSMC3_NRD_CYCLE_SIZE			9
+
+/* Bitfields in MODE0 */
+#define HSMC3_READ_MODE_OFFSET			0
+#define HSMC3_READ_MODE_SIZE			1
+#define HSMC3_WRITE_MODE_OFFSET			1
+#define HSMC3_WRITE_MODE_SIZE			1
+#define HSMC3_EXNW_MODE_OFFSET			4
+#define HSMC3_EXNW_MODE_SIZE			2
+#define HSMC3_BAT_OFFSET			8
+#define HSMC3_BAT_SIZE				1
+#define HSMC3_DBW_OFFSET			12
+#define HSMC3_DBW_SIZE				2
+#define HSMC3_TDF_CYCLES_OFFSET			16
+#define HSMC3_TDF_CYCLES_SIZE			4
+#define HSMC3_TDF_MODE_OFFSET			20
+#define HSMC3_TDF_MODE_SIZE			1
+#define HSMC3_PMEN_OFFSET			24
+#define HSMC3_PMEN_SIZE				1
+#define HSMC3_PS_OFFSET				28
+#define HSMC3_PS_SIZE				2
+
+/* Bitfields in MODE1 */
+#define HSMC3_PD_OFFSET				28
+#define HSMC3_PD_SIZE				2
+
+/* Constants for READ_MODE */
+#define HSMC3_READ_MODE_NCS_CONTROLLED		0
+#define HSMC3_READ_MODE_NRD_CONTROLLED		1
+
+/* Constants for WRITE_MODE */
+#define HSMC3_WRITE_MODE_NCS_CONTROLLED		0
+#define HSMC3_WRITE_MODE_NWE_CONTROLLED		1
+
+/* Constants for EXNW_MODE */
+#define HSMC3_EXNW_MODE_DISABLED		0
+#define HSMC3_EXNW_MODE_RESERVED		1
+#define HSMC3_EXNW_MODE_FROZEN			2
+#define HSMC3_EXNW_MODE_READY			3
+
+/* Constants for BAT */
+#define HSMC3_BAT_BYTE_SELECT			0
+#define HSMC3_BAT_BYTE_WRITE			1
+
+/* Constants for DBW */
+#define HSMC3_DBW_8_BITS			0
+#define HSMC3_DBW_16_BITS			1
+#define HSMC3_DBW_32_BITS			2
+
+/* Bit manipulation macros */
+#define HSMC3_BIT(name)						\
+	(1 << HSMC3_##name##_OFFSET)
+#define HSMC3_BF(name,value)					\
+	(((value) & ((1 << HSMC3_##name##_SIZE) - 1))		\
+	 << HSMC3_##name##_OFFSET)
+#define HSMC3_BFEXT(name,value)					\
+	(((value) >> HSMC3_##name##_OFFSET)			\
+	 & ((1 << HSMC3_##name##_SIZE) - 1))
+#define HSMC3_BFINS(name,value,old)\
+	(((old) & ~(((1 << HSMC3_##name##_SIZE) - 1)		\
+		    << HSMC3_##name##_OFFSET))			\
+	 | HSMC3_BF(name,value))
+
+/* Register access macros */
+#define hsmc3_readl(port,reg)					\
+	readl((port)->regs + HSMC3_##reg)
+#define hsmc3_writel(port,reg,value)				\
+	writel((value), (port)->regs + HSMC3_##reg)
+
+#endif /* __CPU_AT32AP_HSMC3_H__ */
diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c
new file mode 100644
index 0000000..d720cfa
--- /dev/null
+++ b/cpu/at32ap/interrupts.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/div64.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/sysreg.h>
+
+#include <asm/arch/platform.h>
+
+#define HANDLER_MASK	0x00ffffff
+#define INTLEV_SHIFT	30
+#define INTLEV_MASK	0x00000003
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Incremented whenever COUNT reaches 0xffffffff by timer_interrupt_handler */
+volatile unsigned long timer_overflow;
+
+/*
+ * Instead of dividing by get_tbclk(), multiply by this constant and
+ * right-shift the result by 32 bits.
+ */
+static unsigned long tb_factor;
+
+static const struct device *intc_dev;
+
+unsigned long get_tbclk(void)
+{
+	return gd->cpu_hz;
+}
+
+unsigned long long get_ticks(void)
+{
+	unsigned long lo, hi_now, hi_prev;
+
+	do {
+		hi_prev = timer_overflow;
+		lo = sysreg_read(COUNT);
+		hi_now = timer_overflow;
+	} while (hi_prev != hi_now);
+
+	return ((unsigned long long)hi_now << 32) | lo;
+}
+
+void reset_timer(void)
+{
+	sysreg_write(COUNT, 0);
+	cpu_sync_pipeline();	/* process any pending interrupts */
+	timer_overflow = 0;
+}
+
+unsigned long get_timer(unsigned long base)
+{
+	u64 now = get_ticks();
+
+	now *= tb_factor;
+	return (unsigned long)(now >> 32) - base;
+}
+
+void set_timer(unsigned long t)
+{
+	unsigned long long ticks = t;
+	unsigned long lo, hi, hi_new;
+
+	ticks = (ticks * get_tbclk()) / CFG_HZ;
+	hi = ticks >> 32;
+	lo = ticks & 0xffffffffUL;
+
+	do {
+		timer_overflow = hi;
+		sysreg_write(COUNT, lo);
+		hi_new = timer_overflow;
+	} while (hi_new != hi);
+}
+
+/*
+ * For short delays only. It will overflow after a few seconds.
+ */
+void udelay(unsigned long usec)
+{
+	unsigned long now, end;
+
+	now = sysreg_read(COUNT);
+
+	end = ((usec * (get_tbclk() / 10000)) + 50) / 100;
+	end += now;
+
+	while (now > end)
+		now = sysreg_read(COUNT);
+
+	while (now < end)
+		now = sysreg_read(COUNT);
+}
+
+static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
+				 unsigned int priority)
+{
+	unsigned long intpr;
+	unsigned long handler_addr = (unsigned long)handler;
+
+	if ((handler_addr & HANDLER_MASK) != handler_addr
+	    || (priority & INTLEV_MASK) != priority)
+		return -EINVAL;
+
+	intpr = (handler_addr & HANDLER_MASK);
+	intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT;
+	writel(intpr, intc_dev->regs + 4 * nr);
+
+	return 0;
+}
+
+void timer_init(void)
+{
+	extern void timer_interrupt_handler(void);
+	u64 tmp;
+
+	sysreg_write(COUNT, 0);
+
+	tmp = (u64)CFG_HZ << 32;
+	tmp += gd->cpu_hz / 2;
+	do_div(tmp, gd->cpu_hz);
+	tb_factor = (u32)tmp;
+
+	intc_dev = get_device(DEVICE_INTC);
+
+	if (!intc_dev
+	    || set_interrupt_handler(0, &timer_interrupt_handler, 3))
+		return;
+
+	/* For all practical purposes, this gives us an overflow interrupt */
+	sysreg_write(COMPARE, 0xffffffff);
+}
diff --git a/cpu/at32ap/pio.c b/cpu/at32ap/pio.c
new file mode 100644
index 0000000..8b6c3a3
--- /dev/null
+++ b/cpu/at32ap/pio.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+
+#include "pio2.h"
+
+struct pio_state {
+	const struct device *dev;
+	u32 alloc_mask;
+};
+
+static struct pio_state pio_state[CFG_NR_PIOS];
+
+int gpio_set_func(enum device_id gpio_devid, unsigned int start,
+		  unsigned int nr_pins, enum gpio_func func)
+{
+	const struct device *gpio;
+	struct pio_state *state;
+	u32 mask;
+
+	state = &pio_state[gpio_devid - DEVICE_PIOA];
+
+	gpio = get_device(gpio_devid);
+	if (!gpio)
+		return -EBUSY;
+
+	state->dev = gpio;
+	mask = ((1 << nr_pins) - 1) << start;
+
+	if (mask & state->alloc_mask) {
+		put_device(gpio);
+		return -EBUSY;
+	}
+	state->alloc_mask |= mask;
+
+	switch (func) {
+	case GPIO_FUNC_GPIO:
+		/* TODO */
+		return -EINVAL;
+	case GPIO_FUNC_A:
+		pio2_writel(gpio, ASR, mask);
+		pio2_writel(gpio, PDR, mask);
+		pio2_writel(gpio, PUDR, mask);
+		break;
+	case GPIO_FUNC_B:
+		pio2_writel(gpio, BSR, mask);
+		pio2_writel(gpio, PDR, mask);
+		pio2_writel(gpio, PUDR, mask);
+		break;
+	}
+
+	return 0;
+}
+
+void gpio_free(enum device_id gpio_devid, unsigned int start,
+	       unsigned int nr_pins)
+{
+	const struct device *gpio;
+	struct pio_state *state;
+	u32 mask;
+
+	state = &pio_state[gpio_devid - DEVICE_PIOA];
+	gpio = state->dev;
+	mask = ((1 << nr_pins) - 1) << start;
+
+	pio2_writel(gpio, ODR, mask);
+	pio2_writel(gpio, PER, mask);
+
+	state->alloc_mask &= ~mask;
+	put_device(gpio);
+}
diff --git a/cpu/at32ap/pio2.h b/cpu/at32ap/pio2.h
new file mode 100644
index 0000000..6b79de3
--- /dev/null
+++ b/cpu/at32ap/pio2.h
@@ -0,0 +1,44 @@
+/*
+ * Register definitions for Parallel Input/Output Controller
+ */
+#ifndef __CPU_AT32AP_PIO2_H__
+#define __CPU_AT32AP_PIO2_H__
+
+/* PIO2 register offsets */
+#define PIO2_PER				0x0000
+#define PIO2_PDR				0x0004
+#define PIO2_PSR				0x0008
+#define PIO2_OER				0x0010
+#define PIO2_ODR				0x0014
+#define PIO2_OSR				0x0018
+#define PIO2_IFER				0x0020
+#define PIO2_IFDR				0x0024
+#define PIO2_ISFR				0x0028
+#define PIO2_SODR				0x0030
+#define PIO2_CODR				0x0034
+#define PIO2_ODSR				0x0038
+#define PIO2_PDSR				0x003c
+#define PIO2_IER				0x0040
+#define PIO2_IDR				0x0044
+#define PIO2_IMR				0x0048
+#define PIO2_ISR				0x004c
+#define PIO2_MDER				0x0050
+#define PIO2_MDDR				0x0054
+#define PIO2_MDSR				0x0058
+#define PIO2_PUDR				0x0060
+#define PIO2_PUER				0x0064
+#define PIO2_PUSR				0x0068
+#define PIO2_ASR				0x0070
+#define PIO2_BSR				0x0074
+#define PIO2_ABSR				0x0078
+#define PIO2_OWER				0x00a0
+#define PIO2_OWDR				0x00a4
+#define PIO2_OWSR				0x00a8
+
+/* Register access macros */
+#define pio2_readl(port,reg)				\
+	readl((port)->regs + PIO2_##reg)
+#define pio2_writel(port,reg,value)			\
+	writel((value), (port)->regs + PIO2_##reg)
+
+#endif /* __CPU_AT32AP_PIO2_H__ */
diff --git a/cpu/at32ap/pm.c b/cpu/at32ap/pm.c
new file mode 100644
index 0000000..01ac325
--- /dev/null
+++ b/cpu/at32ap/pm.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CFG_POWER_MANAGER
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+#include "sm.h"
+
+/* Sanity checks */
+#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB)		\
+	|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA)	\
+	|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
+# error Constraint fCPU >= fHSB >= fPB{A,B} violated
+#endif
+#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
+# error Invalid PLL multiplier and/or divider
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clock_domain_state {
+	const struct device *bridge;
+	unsigned long freq;
+	u32 mask;
+};
+static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS];
+
+int pm_enable_clock(enum clock_domain_id id, unsigned int index)
+{
+	const struct clock_domain *ckd = &chip_clock[id];
+	struct clock_domain_state *state = &ckd_state[id];
+
+	if (ckd->bridge != NO_DEVICE) {
+		state->bridge = get_device(ckd->bridge);
+		if (!state->bridge)
+			return -EBUSY;
+	}
+
+	state->mask |= 1 << index;
+	if (gd->sm)
+		writel(state->mask, gd->sm->regs + ckd->reg);
+
+	return 0;
+}
+
+void pm_disable_clock(enum clock_domain_id id, unsigned int index)
+{
+	const struct clock_domain *ckd = &chip_clock[id];
+	struct clock_domain_state *state = &ckd_state[id];
+
+	state->mask &= ~(1 << index);
+	if (gd->sm)
+		writel(state->mask, gd->sm->regs + ckd->reg);
+
+	if (ckd->bridge)
+		put_device(state->bridge);
+}
+
+unsigned long pm_get_clock_freq(enum clock_domain_id domain)
+{
+	return ckd_state[domain].freq;
+}
+
+void pm_init(void)
+{
+	uint32_t cksel = 0;
+	unsigned long main_clock;
+
+	/* Make sure we don't disable any device we're already using */
+	get_device(DEVICE_HRAMC);
+	get_device(DEVICE_HEBI);
+
+	/* Enable the PICO as well */
+	ckd_state[CLOCK_CPU].mask |= 1;
+
+	gd->sm = get_device(DEVICE_SM);
+	if (!gd->sm)
+		panic("Unable to claim system manager device!\n");
+
+	/* Disable any devices that haven't been explicitly claimed */
+	sm_writel(gd->sm, PM_PBB_MASK, ckd_state[CLOCK_PBB].mask);
+	sm_writel(gd->sm, PM_PBA_MASK, ckd_state[CLOCK_PBA].mask);
+	sm_writel(gd->sm, PM_HSB_MASK, ckd_state[CLOCK_HSB].mask);
+	sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask);
+
+#ifdef CONFIG_PLL
+	/* Initialize the PLL */
+	main_clock = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL;
+
+	sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
+				    | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
+				    | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
+				    | SM_BF(PLLOPT, CFG_PLL0_OPT)
+				    | SM_BF(PLLOSC, 0)
+				    | SM_BIT(PLLEN)));
+
+	/* Wait for lock */
+	while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ;
+#else
+	main_clock = CFG_OSC0_HZ;
+#endif
+
+	/* Set up clocks for the CPU and all peripheral buses */
+	if (CFG_CLKDIV_CPU) {
+		cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
+		ckd_state[CLOCK_CPU].freq = main_clock / (1 << CFG_CLKDIV_CPU);
+	} else {
+		ckd_state[CLOCK_CPU].freq = main_clock;
+	}
+	if (CFG_CLKDIV_HSB) {
+		cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
+		ckd_state[CLOCK_HSB].freq = main_clock / (1 << CFG_CLKDIV_HSB);
+	} else {
+		ckd_state[CLOCK_HSB].freq = main_clock;
+	}
+	if (CFG_CLKDIV_PBA) {
+		cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
+		ckd_state[CLOCK_PBA].freq = main_clock / (1 << CFG_CLKDIV_PBA);
+	} else {
+		ckd_state[CLOCK_PBA].freq = main_clock;
+	}
+	if (CFG_CLKDIV_PBB) {
+		cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
+		ckd_state[CLOCK_PBB].freq = main_clock / (1 << CFG_CLKDIV_PBB);
+	} else {
+		ckd_state[CLOCK_PBB].freq = main_clock;
+	}
+	sm_writel(gd->sm, PM_CKSEL, cksel);
+
+	/* CFG_HZ currently depends on cpu_hz */
+	gd->cpu_hz = ckd_state[CLOCK_CPU].freq;
+
+#ifdef CONFIG_PLL
+	/* Use PLL0 as main clock */
+	sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL));
+#endif
+}
+
+#endif /* CFG_POWER_MANAGER */
diff --git a/cpu/at32ap/sm.h b/cpu/at32ap/sm.h
new file mode 100644
index 0000000..ce81ef0
--- /dev/null
+++ b/cpu/at32ap/sm.h
@@ -0,0 +1,204 @@
+/*
+ * Register definitions for System Manager
+ */
+#ifndef __CPU_AT32AP_SM_H__
+#define __CPU_AT32AP_SM_H__
+
+/* SM register offsets */
+#define SM_PM_MCCTRL				0x0000
+#define SM_PM_CKSEL				0x0004
+#define SM_PM_CPU_MASK				0x0008
+#define SM_PM_HSB_MASK				0x000c
+#define SM_PM_PBA_MASK				0x0010
+#define SM_PM_PBB_MASK				0x0014
+#define SM_PM_PLL0				0x0020
+#define SM_PM_PLL1				0x0024
+#define SM_PM_VCTRL				0x0030
+#define SM_PM_VMREF				0x0034
+#define SM_PM_VMV				0x0038
+#define SM_PM_IER				0x0040
+#define SM_PM_IDR				0x0044
+#define SM_PM_IMR				0x0048
+#define SM_PM_ISR				0x004c
+#define SM_PM_ICR				0x0050
+#define SM_PM_GCCTRL				0x0060
+#define SM_RTC_CTRL				0x0080
+#define SM_RTC_VAL				0x0084
+#define SM_RTC_TOP				0x0088
+#define SM_RTC_IER				0x0090
+#define SM_RTC_IDR				0x0094
+#define SM_RTC_IMR				0x0098
+#define SM_RTC_ISR				0x009c
+#define SM_RTC_ICR				0x00a0
+#define SM_WDT_CTRL				0x00b0
+#define SM_WDT_CLR				0x00b4
+#define SM_WDT_EXT				0x00b8
+#define SM_RC_RCAUSE				0x00c0
+#define SM_EIM_IER				0x0100
+#define SM_EIM_IDR				0x0104
+#define SM_EIM_IMR				0x0108
+#define SM_EIM_ISR				0x010c
+#define SM_EIM_ICR				0x0110
+#define SM_EIM_MODE				0x0114
+#define SM_EIM_EDGE				0x0118
+#define SM_EIM_LEVEL				0x011c
+#define SM_EIM_TEST				0x0120
+#define SM_EIM_NMIC				0x0124
+
+/* Bitfields in PM_CKSEL */
+#define SM_CPUSEL_OFFSET			0
+#define SM_CPUSEL_SIZE				3
+#define SM_CPUDIV_OFFSET			7
+#define SM_CPUDIV_SIZE				1
+#define SM_HSBSEL_OFFSET			8
+#define SM_HSBSEL_SIZE				3
+#define SM_HSBDIV_OFFSET			15
+#define SM_HSBDIV_SIZE				1
+#define SM_PBASEL_OFFSET			16
+#define SM_PBASEL_SIZE				3
+#define SM_PBADIV_OFFSET			23
+#define SM_PBADIV_SIZE				1
+#define SM_PBBSEL_OFFSET			24
+#define SM_PBBSEL_SIZE				3
+#define SM_PBBDIV_OFFSET			31
+#define SM_PBBDIV_SIZE				1
+
+/* Bitfields in PM_PLL0 */
+#define SM_PLLEN_OFFSET				0
+#define SM_PLLEN_SIZE				1
+#define SM_PLLOSC_OFFSET			1
+#define SM_PLLOSC_SIZE				1
+#define SM_PLLOPT_OFFSET			2
+#define SM_PLLOPT_SIZE				3
+#define SM_PLLDIV_OFFSET			8
+#define SM_PLLDIV_SIZE				8
+#define SM_PLLMUL_OFFSET			16
+#define SM_PLLMUL_SIZE				8
+#define SM_PLLCOUNT_OFFSET			24
+#define SM_PLLCOUNT_SIZE			6
+#define SM_PLLTEST_OFFSET			31
+#define SM_PLLTEST_SIZE				1
+
+/* Bitfields in PM_VCTRL */
+#define SM_VAUTO_OFFSET				0
+#define SM_VAUTO_SIZE				1
+#define SM_PM_VCTRL_VAL_OFFSET			8
+#define SM_PM_VCTRL_VAL_SIZE			7
+
+/* Bitfields in PM_VMREF */
+#define SM_REFSEL_OFFSET			0
+#define SM_REFSEL_SIZE				4
+
+/* Bitfields in PM_VMV */
+#define SM_PM_VMV_VAL_OFFSET			0
+#define SM_PM_VMV_VAL_SIZE			8
+
+/* Bitfields in PM_ICR */
+#define SM_LOCK0_OFFSET				0
+#define SM_LOCK0_SIZE				1
+#define SM_LOCK1_OFFSET				1
+#define SM_LOCK1_SIZE				1
+#define SM_WAKE_OFFSET				2
+#define SM_WAKE_SIZE				1
+#define SM_VOK_OFFSET				3
+#define SM_VOK_SIZE				1
+#define SM_VMRDY_OFFSET				4
+#define SM_VMRDY_SIZE				1
+#define SM_CKRDY_OFFSET				5
+#define SM_CKRDY_SIZE				1
+
+/* Bitfields in PM_GCCTRL */
+#define SM_OSCSEL_OFFSET			0
+#define SM_OSCSEL_SIZE				1
+#define SM_PLLSEL_OFFSET			1
+#define SM_PLLSEL_SIZE				1
+#define SM_CEN_OFFSET				2
+#define SM_CEN_SIZE				1
+#define SM_CPC_OFFSET				3
+#define SM_CPC_SIZE				1
+#define SM_DIVEN_OFFSET				4
+#define SM_DIVEN_SIZE				1
+#define SM_DIV_OFFSET				8
+#define SM_DIV_SIZE				8
+
+/* Bitfields in RTC_CTRL */
+#define SM_PCLR_OFFSET				1
+#define SM_PCLR_SIZE				1
+#define SM_TOPEN_OFFSET				2
+#define SM_TOPEN_SIZE				1
+#define SM_CLKEN_OFFSET				3
+#define SM_CLKEN_SIZE				1
+#define SM_PSEL_OFFSET				8
+#define SM_PSEL_SIZE				16
+
+/* Bitfields in RTC_VAL */
+#define SM_RTC_VAL_VAL_OFFSET			0
+#define SM_RTC_VAL_VAL_SIZE			31
+
+/* Bitfields in RTC_TOP */
+#define SM_RTC_TOP_VAL_OFFSET			0
+#define SM_RTC_TOP_VAL_SIZE			32
+
+/* Bitfields in RTC_ICR */
+#define SM_TOPI_OFFSET				0
+#define SM_TOPI_SIZE				1
+
+/* Bitfields in WDT_CTRL */
+#define SM_KEY_OFFSET				24
+#define SM_KEY_SIZE				8
+
+/* Bitfields in RC_RCAUSE */
+#define SM_POR_OFFSET				0
+#define SM_POR_SIZE				1
+#define SM_BOD_OFFSET				1
+#define SM_BOD_SIZE				1
+#define SM_EXT_OFFSET				2
+#define SM_EXT_SIZE				1
+#define SM_WDT_OFFSET				3
+#define SM_WDT_SIZE				1
+#define SM_NTAE_OFFSET				4
+#define SM_NTAE_SIZE				1
+#define SM_SERP_OFFSET				5
+#define SM_SERP_SIZE				1
+
+/* Bitfields in EIM_EDGE */
+#define SM_INT0_OFFSET				0
+#define SM_INT0_SIZE				1
+#define SM_INT1_OFFSET				1
+#define SM_INT1_SIZE				1
+#define SM_INT2_OFFSET				2
+#define SM_INT2_SIZE				1
+#define SM_INT3_OFFSET				3
+#define SM_INT3_SIZE				1
+
+/* Bitfields in EIM_LEVEL */
+
+/* Bitfields in EIM_TEST */
+#define SM_TESTEN_OFFSET			31
+#define SM_TESTEN_SIZE				1
+
+/* Bitfields in EIM_NMIC */
+#define SM_EN_OFFSET				0
+#define SM_EN_SIZE				1
+
+/* Bit manipulation macros */
+#define SM_BIT(name)					\
+	(1 << SM_##name##_OFFSET)
+#define SM_BF(name,value)				\
+	(((value) & ((1 << SM_##name##_SIZE) - 1))	\
+	 << SM_##name##_OFFSET)
+#define SM_BFEXT(name,value)				\
+	(((value) >> SM_##name##_OFFSET)		\
+	 & ((1 << SM_##name##_SIZE) - 1))
+#define SM_BFINS(name,value,old)			\
+	(((old) & ~(((1 << SM_##name##_SIZE) - 1)	\
+		    << SM_##name##_OFFSET))		\
+	 | SM_BF(name,value))
+
+/* Register access macros */
+#define sm_readl(port,reg)				\
+	readl((port)->regs + SM_##reg)
+#define sm_writel(port,reg,value)			\
+	writel((value), (port)->regs + SM_##reg)
+
+#endif /* __CPU_AT32AP_SM_H__ */
diff --git a/cpu/at32ap/start.S b/cpu/at32ap/start.S
new file mode 100644
index 0000000..79ee33b
--- /dev/null
+++ b/cpu/at32ap/start.S
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <asm/sysreg.h>
+
+#ifndef PART_SPECIFIC_BOOTSTRAP
+# define PART_SPECIFIC_BOOTSTRAP
+#endif
+
+#define SYSREG_MMUCR_I_OFFSET	2
+#define SYSREG_MMUCR_S_OFFSET	4
+
+#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
+#define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE)		\
+		    | SYSREG_BIT(FE) | SYSREG_BIT(RE)		\
+		    | SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
+
+	.text
+	.global	_start
+_start:
+	PART_SPECIFIC_BOOTSTRAP
+
+	/* Reset the Status Register */
+	mov	r0, lo(SR_INIT)
+	orh	r0, hi(SR_INIT)
+	mtsr	SYSREG_SR, r0
+
+	/* Reset CPUCR and invalidate the BTB */
+	mov	r2, CPUCR_INIT
+	mtsr	SYSREG_CPUCR, r2
+
+	/* Flush the caches */
+	mov	r1, 0
+	cache	r1[4], 8
+	cache	r1[0], 0
+	sync	0
+
+	/* Reset the MMU to default settings */
+	mov	r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
+	mtsr	SYSREG_MMUCR, r0
+
+	/* Internal RAM should not need any initialization.  We might
+	   have to initialize external RAM here if the part doesn't
+	   have internal RAM (or we may use the data cache) */
+
+	/* Jump to cacheable segment */
+	lddpc	pc, 1f
+
+	.align	2
+1:	.long	2f
+
+2:	lddpc	sp, sp_init
+
+	/*
+	 * Relocate the data section and initialize .bss.  Everything
+	 * is guaranteed to be at least doubleword aligned by the
+	 * linker script.
+	 */
+	lddpc	r12, .Ldata_vma
+	lddpc	r11, .Ldata_lma
+	lddpc	r10, .Ldata_end
+	sub	r10, r12
+4:	ld.d	r8, r11++
+	sub	r10, 8
+	st.d	r12++, r8
+	brne	4b
+
+	mov	r8, 0
+	mov	r9, 0
+	lddpc	r10, .Lbss_end
+	sub	r10, r12
+4:	sub	r10, 8
+	st.d	r12++, r8
+	brne	4b
+
+	/* Initialize the GOT pointer */
+	lddpc	r6, got_init
+3:	rsub	r6, pc
+	ld.w	pc, r6[start_u_boot@got]
+
+	.align	2
+	.type	sp_init,@object
+sp_init:
+	.long	CFG_INIT_SP_ADDR
+got_init:
+	.long	3b - _GLOBAL_OFFSET_TABLE_
+.Ldata_lma:
+	.long	__data_lma
+.Ldata_vma:
+	.long	_data
+.Ldata_end:
+	.long	_edata
+.Lbss_end:
+	.long	_end
diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h
new file mode 100644
index 0000000..e6df4b7
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/hmatrix2.h
@@ -0,0 +1,232 @@
+/*
+ * Register definition for the High-speed Bus Matrix
+ */
+#ifndef __ASM_AVR32_HMATRIX2_H__
+#define __ASM_AVR32_HMATRIX2_H__
+
+/* HMATRIX2 register offsets */
+#define HMATRIX2_MCFG0				0x0000
+#define HMATRIX2_MCFG1				0x0004
+#define HMATRIX2_MCFG2				0x0008
+#define HMATRIX2_MCFG3				0x000c
+#define HMATRIX2_MCFG4				0x0010
+#define HMATRIX2_MCFG5				0x0014
+#define HMATRIX2_MCFG6				0x0018
+#define HMATRIX2_MCFG7				0x001c
+#define HMATRIX2_MCFG8				0x0020
+#define HMATRIX2_MCFG9				0x0024
+#define HMATRIX2_MCFG10				0x0028
+#define HMATRIX2_MCFG11				0x002c
+#define HMATRIX2_MCFG12				0x0030
+#define HMATRIX2_MCFG13				0x0034
+#define HMATRIX2_MCFG14				0x0038
+#define HMATRIX2_MCFG15				0x003c
+#define HMATRIX2_SCFG0				0x0040
+#define HMATRIX2_SCFG1				0x0044
+#define HMATRIX2_SCFG2				0x0048
+#define HMATRIX2_SCFG3				0x004c
+#define HMATRIX2_SCFG4				0x0050
+#define HMATRIX2_SCFG5				0x0054
+#define HMATRIX2_SCFG6				0x0058
+#define HMATRIX2_SCFG7				0x005c
+#define HMATRIX2_SCFG8				0x0060
+#define HMATRIX2_SCFG9				0x0064
+#define HMATRIX2_SCFG10				0x0068
+#define HMATRIX2_SCFG11				0x006c
+#define HMATRIX2_SCFG12				0x0070
+#define HMATRIX2_SCFG13				0x0074
+#define HMATRIX2_SCFG14				0x0078
+#define HMATRIX2_SCFG15				0x007c
+#define HMATRIX2_PRAS0				0x0080
+#define HMATRIX2_PRBS0				0x0084
+#define HMATRIX2_PRAS1				0x0088
+#define HMATRIX2_PRBS1				0x008c
+#define HMATRIX2_PRAS2				0x0090
+#define HMATRIX2_PRBS2				0x0094
+#define HMATRIX2_PRAS3				0x0098
+#define HMATRIX2_PRBS3				0x009c
+#define HMATRIX2_PRAS4				0x00a0
+#define HMATRIX2_PRBS4				0x00a4
+#define HMATRIX2_PRAS5				0x00a8
+#define HMATRIX2_PRBS5				0x00ac
+#define HMATRIX2_PRAS6				0x00b0
+#define HMATRIX2_PRBS6				0x00b4
+#define HMATRIX2_PRAS7				0x00b8
+#define HMATRIX2_PRBS7				0x00bc
+#define HMATRIX2_PRAS8				0x00c0
+#define HMATRIX2_PRBS8				0x00c4
+#define HMATRIX2_PRAS9				0x00c8
+#define HMATRIX2_PRBS9				0x00cc
+#define HMATRIX2_PRAS10				0x00d0
+#define HMATRIX2_PRBS10				0x00d4
+#define HMATRIX2_PRAS11				0x00d8
+#define HMATRIX2_PRBS11				0x00dc
+#define HMATRIX2_PRAS12				0x00e0
+#define HMATRIX2_PRBS12				0x00e4
+#define HMATRIX2_PRAS13				0x00e8
+#define HMATRIX2_PRBS13				0x00ec
+#define HMATRIX2_PRAS14				0x00f0
+#define HMATRIX2_PRBS14				0x00f4
+#define HMATRIX2_PRAS15				0x00f8
+#define HMATRIX2_PRBS15				0x00fc
+#define HMATRIX2_MRCR				0x0100
+#define HMATRIX2_SFR0				0x0110
+#define HMATRIX2_SFR1				0x0114
+#define HMATRIX2_SFR2				0x0118
+#define HMATRIX2_SFR3				0x011c
+#define HMATRIX2_SFR4				0x0120
+#define HMATRIX2_SFR5				0x0124
+#define HMATRIX2_SFR6				0x0128
+#define HMATRIX2_SFR7				0x012c
+#define HMATRIX2_SFR8				0x0130
+#define HMATRIX2_SFR9				0x0134
+#define HMATRIX2_SFR10				0x0138
+#define HMATRIX2_SFR11				0x013c
+#define HMATRIX2_SFR12				0x0140
+#define HMATRIX2_SFR13				0x0144
+#define HMATRIX2_SFR14				0x0148
+#define HMATRIX2_SFR15				0x014c
+#define HMATRIX2_VERSION			0x01fc
+
+/* Bitfields in MCFG0 */
+#define HMATRIX2_ULBT_OFFSET			0
+#define HMATRIX2_ULBT_SIZE			3
+
+/* Bitfields in SCFG0 */
+#define HMATRIX2_SLOT_CYCLE_OFFSET		0
+#define HMATRIX2_SLOT_CYCLE_SIZE		8
+#define HMATRIX2_DEFMSTR_TYPE_OFFSET		16
+#define HMATRIX2_DEFMSTR_TYPE_SIZE		2
+#define HMATRIX2_FIXED_DEFMSTR_OFFSET		18
+#define HMATRIX2_FIXED_DEFMSTR_SIZE		4
+#define HMATRIX2_ARBT_OFFSET			24
+#define HMATRIX2_ARBT_SIZE			2
+
+/* Bitfields in PRAS0 */
+#define HMATRIX2_M0PR_OFFSET			0
+#define HMATRIX2_M0PR_SIZE			4
+#define HMATRIX2_M1PR_OFFSET			4
+#define HMATRIX2_M1PR_SIZE			4
+#define HMATRIX2_M2PR_OFFSET			8
+#define HMATRIX2_M2PR_SIZE			4
+#define HMATRIX2_M3PR_OFFSET			12
+#define HMATRIX2_M3PR_SIZE			4
+#define HMATRIX2_M4PR_OFFSET			16
+#define HMATRIX2_M4PR_SIZE			4
+#define HMATRIX2_M5PR_OFFSET			20
+#define HMATRIX2_M5PR_SIZE			4
+#define HMATRIX2_M6PR_OFFSET			24
+#define HMATRIX2_M6PR_SIZE			4
+#define HMATRIX2_M7PR_OFFSET			28
+#define HMATRIX2_M7PR_SIZE			4
+
+/* Bitfields in PRBS0 */
+#define HMATRIX2_M8PR_OFFSET			0
+#define HMATRIX2_M8PR_SIZE			4
+#define HMATRIX2_M9PR_OFFSET			4
+#define HMATRIX2_M9PR_SIZE			4
+#define HMATRIX2_M10PR_OFFSET			8
+#define HMATRIX2_M10PR_SIZE			4
+#define HMATRIX2_M11PR_OFFSET			12
+#define HMATRIX2_M11PR_SIZE			4
+#define HMATRIX2_M12PR_OFFSET			16
+#define HMATRIX2_M12PR_SIZE			4
+#define HMATRIX2_M13PR_OFFSET			20
+#define HMATRIX2_M13PR_SIZE			4
+#define HMATRIX2_M14PR_OFFSET			24
+#define HMATRIX2_M14PR_SIZE			4
+#define HMATRIX2_M15PR_OFFSET			28
+#define HMATRIX2_M15PR_SIZE			4
+
+/* Bitfields in MRCR */
+#define HMATRIX2_RBC0_OFFSET			0
+#define HMATRIX2_RBC0_SIZE			1
+#define HMATRIX2_RBC1_OFFSET			1
+#define HMATRIX2_RBC1_SIZE			1
+#define HMATRIX2_RBC2_OFFSET			2
+#define HMATRIX2_RBC2_SIZE			1
+#define HMATRIX2_RBC3_OFFSET			3
+#define HMATRIX2_RBC3_SIZE			1
+#define HMATRIX2_RBC4_OFFSET			4
+#define HMATRIX2_RBC4_SIZE			1
+#define HMATRIX2_RBC5_OFFSET			5
+#define HMATRIX2_RBC5_SIZE			1
+#define HMATRIX2_RBC6_OFFSET			6
+#define HMATRIX2_RBC6_SIZE			1
+#define HMATRIX2_RBC7_OFFSET			7
+#define HMATRIX2_RBC7_SIZE			1
+#define HMATRIX2_RBC8_OFFSET			8
+#define HMATRIX2_RBC8_SIZE			1
+#define HMATRIX2_RBC9_OFFSET			9
+#define HMATRIX2_RBC9_SIZE			1
+#define HMATRIX2_RBC10_OFFSET			10
+#define HMATRIX2_RBC10_SIZE			1
+#define HMATRIX2_RBC11_OFFSET			11
+#define HMATRIX2_RBC11_SIZE			1
+#define HMATRIX2_RBC12_OFFSET			12
+#define HMATRIX2_RBC12_SIZE			1
+#define HMATRIX2_RBC13_OFFSET			13
+#define HMATRIX2_RBC13_SIZE			1
+#define HMATRIX2_RBC14_OFFSET			14
+#define HMATRIX2_RBC14_SIZE			1
+#define HMATRIX2_RBC15_OFFSET			15
+#define HMATRIX2_RBC15_SIZE			1
+
+/* Bitfields in SFR0 */
+#define HMATRIX2_SFR_OFFSET			0
+#define HMATRIX2_SFR_SIZE			32
+
+/* Bitfields in SFR4 */
+#define HMATRIX2_CS1A_OFFSET			1
+#define HMATRIX2_CS1A_SIZE			1
+#define HMATRIX2_CS3A_OFFSET			3
+#define HMATRIX2_CS3A_SIZE			1
+#define HMATRIX2_CS4A_OFFSET			4
+#define HMATRIX2_CS4A_SIZE			1
+#define HMATRIX2_CS5A_OFFSET			5
+#define HMATRIX2_CS5A_SIZE			1
+#define HMATRIX2_DBPUC_OFFSET			8
+#define HMATRIX2_DBPUC_SIZE			1
+
+/* Bitfields in VERSION */
+#define HMATRIX2_VERSION_OFFSET			0
+#define HMATRIX2_VERSION_SIZE			12
+#define HMATRIX2_MFN_OFFSET			16
+#define HMATRIX2_MFN_SIZE			3
+
+/* Constants for ULBT */
+#define HMATRIX2_ULBT_INFINITE			0
+#define HMATRIX2_ULBT_SINGLE			1
+#define HMATRIX2_ULBT_FOUR_BEAT			2
+#define HMATRIX2_ULBT_SIXTEEN_BEAT		4
+
+/* Constants for DEFMSTR_TYPE */
+#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT	0
+#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT	1
+#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT	2
+
+/* Constants for ARBT */
+#define HMATRIX2_ARBT_ROUND_ROBIN		0
+#define HMATRIX2_ARBT_FIXED_PRIORITY		1
+
+/* Bit manipulation macros */
+#define HMATRIX2_BIT(name)					\
+	(1 << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BF(name,value)					\
+	(((value) & ((1 << HMATRIX2_##name##_SIZE) - 1))	\
+	 << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BFEXT(name,value)				\
+	(((value) >> HMATRIX2_##name##_OFFSET)			\
+	 & ((1 << HMATRIX2_##name##_SIZE) - 1))
+#define HMATRIX2_BFINS(name,value,old)				\
+	(((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1)		\
+		    << HMATRIX2_##name##_OFFSET))		\
+	 | HMATRIX2_BF(name,value))
+
+/* Register access macros */
+#define hmatrix2_readl(port,reg)				\
+	readl((port)->regs + HMATRIX2_##reg)
+#define hmatrix2_writel(port,reg,value)				\
+	writel((value), (port)->regs + HMATRIX2_##reg)
+
+#endif /* __ASM_AVR32_HMATRIX2_H__ */
diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h
new file mode 100644
index 0000000..8ffe851
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/memory-map.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__
+#define __ASM_AVR32_PART_MEMORY_MAP_H__
+
+#define AUDIOC_BASE                             0xFFF02800
+#define DAC_BASE                                0xFFF02000
+#define DMAC_BASE                               0xFF200000
+#define ECC_BASE                                0xFFF03C00
+#define HISI_BASE                               0xFFF02C00
+#define HMATRIX_BASE                            0xFFF00800
+#define HSDRAMC_BASE                            0xFFF03800
+#define HSMC_BASE                               0xFFF03400
+#define LCDC_BASE                               0xFF000000
+#define MACB0_BASE                              0xFFF01800
+#define MACB1_BASE                              0xFFF01C00
+#define MMCI_BASE                               0xFFF02400
+#define PIOA_BASE                               0xFFE02800
+#define PIOB_BASE                               0xFFE02C00
+#define PIOC_BASE                               0xFFE03000
+#define PIOD_BASE                               0xFFE03400
+#define PIOE_BASE                               0xFFE03800
+#define PSIF_BASE                               0xFFE03C00
+#define PWM_BASE                                0xFFF01400
+#define SM_BASE                                 0xFFF00000
+#define INTC_BASE				0XFFF00400
+#define SPI0_BASE                               0xFFE00000
+#define SPI1_BASE                               0xFFE00400
+#define SSC0_BASE                               0xFFE01C00
+#define SSC1_BASE                               0xFFE02000
+#define SSC2_BASE                               0xFFE02400
+#define TIMER0_BASE                             0xFFF00C00
+#define TIMER1_BASE                             0xFFF01000
+#define TWI_BASE                                0xFFE00800
+#define USART0_BASE                             0xFFE00C00
+#define USART1_BASE                             0xFFE01000
+#define USART2_BASE                             0xFFE01400
+#define USART3_BASE                             0xFFE01800
+#define USB_FIFO                                0xFF300000
+#define USB_BASE                                0xFFF03000
+
+#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */
diff --git a/include/asm-avr32/arch-at32ap7000/platform.h b/include/asm-avr32/arch-at32ap7000/platform.h
new file mode 100644
index 0000000..7590501
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/platform.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_AVR32_ARCH_PM_H
+#define _ASM_AVR32_ARCH_PM_H
+
+#include <config.h>
+
+enum clock_domain_id {
+	CLOCK_CPU,
+	CLOCK_HSB,
+	CLOCK_PBA,
+	CLOCK_PBB,
+	NR_CLOCK_DOMAINS,
+};
+
+enum resource_type {
+	RESOURCE_GPIO,
+	RESOURCE_CLOCK,
+};
+
+enum gpio_func {
+	GPIO_FUNC_GPIO,
+	GPIO_FUNC_A,
+	GPIO_FUNC_B,
+};
+
+enum device_id {
+	DEVICE_HEBI,
+	DEVICE_PBA_BRIDGE,
+	DEVICE_PBB_BRIDGE,
+	DEVICE_HRAMC,
+	/* GPIO controllers must be kept together */
+	DEVICE_PIOA,
+	DEVICE_PIOB,
+	DEVICE_PIOC,
+	DEVICE_PIOD,
+	DEVICE_PIOE,
+	DEVICE_SM,
+	DEVICE_INTC,
+	DEVICE_HMATRIX,
+#if defined(CFG_HPDC)
+	DEVICE_HPDC,
+#endif
+#if defined(CFG_MACB0)
+	DEVICE_MACB0,
+#endif
+#if defined(CFG_MACB1)
+	DEVICE_MACB1,
+#endif
+#if defined(CFG_LCDC)
+	DEVICE_LCDC,
+#endif
+#if defined(CFG_USART0)
+	DEVICE_USART0,
+#endif
+#if defined(CFG_USART1)
+	DEVICE_USART1,
+#endif
+#if defined(CFG_USART2)
+	DEVICE_USART2,
+#endif
+#if defined(CFG_USART3)
+	DEVICE_USART3,
+#endif
+#if defined(CFG_MMCI)
+	DEVICE_MMCI,
+#endif
+#if defined(CFG_DMAC)
+	DEVICE_DMAC,
+#endif
+	NR_DEVICES,
+	NO_DEVICE = -1,
+};
+
+struct resource {
+	enum resource_type type;
+	union {
+		struct {
+			unsigned long base;
+		} iomem;
+		struct {
+			unsigned char nr_pins;
+			enum device_id gpio_dev;
+			enum gpio_func func;
+			unsigned short start;
+		} gpio;
+		struct {
+			enum clock_domain_id id;
+			unsigned char index;
+		} clock;
+	} u;
+};
+
+struct device {
+	void *regs;
+	unsigned int nr_resources;
+	const struct resource *resource;
+};
+
+struct clock_domain {
+	unsigned short reg;
+	enum clock_domain_id id;
+	enum device_id bridge;
+};
+
+extern const struct device chip_device[NR_DEVICES];
+extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS];
+
+/**
+ * Set up PIO, clock management and I/O memory for a device.
+ */
+const struct device *get_device(enum device_id devid);
+void put_device(const struct device *dev);
+
+int gpio_set_func(enum device_id gpio_devid, unsigned int start,
+		  unsigned int nr_pins, enum gpio_func func);
+void gpio_free(enum device_id gpio_devid, unsigned int start,
+	       unsigned int nr_pins);
+
+void pm_init(void);
+int pm_enable_clock(enum clock_domain_id id, unsigned int index);
+void pm_disable_clock(enum clock_domain_id id, unsigned int index);
+unsigned long pm_get_clock_freq(enum clock_domain_id domain);
+
+void cpu_enable_sdram(void);
+
+#endif /* _ASM_AVR32_ARCH_PM_H */
-- 
cgit v0.10.2


From f93ae788c3640fcde5db383471d45548ff4060d0 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue, 24 Oct 2006 14:31:24 +0200
Subject: Add common serial driver for Atmel AT32 and AT91 chips Patch by
 Haavard Skinnemoen, 06 Sep 2006

This is a first attempt at creating a common serial driver for Atmel
chips. For now, it supports the AT32AP7000 AVR32 chip, but it should
be possible to support AT91RM9200 and other ARM-based chips with some
minor modifications.

There's nothing fundamentally AVR32-specific in this driver, but it
does use some features which are currently only defined for the
AT32AP CPU port:
  * pm_get_clock_freq: Obtain the clock frequency of a given domain
  * gd->console_uart: A "struct device" containing information about
    register mappings, gpio resources and clocks associated with the
    UART device.

For more information about these features, please see the "AT32AP
CPU" patch.

diff --git a/drivers/Makefile b/drivers/Makefile
index 5a7ab71..7628f56 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)libdrivers.a
 
-COBJS	= 3c589.o 5701rls.o ali512x.o \
+COBJS	= 3c589.o 5701rls.o ali512x.o atmel_usart.o \
 	  bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
 	  cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
 	  e1000.o eepro100.o \
diff --git a/drivers/atmel_usart.c b/drivers/atmel_usart.c
new file mode 100644
index 0000000..41c3768
--- /dev/null
+++ b/drivers/atmel_usart.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_ATMEL_USART
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+
+#include "atmel_usart.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void serial_setbrg(void)
+{
+	unsigned long divisor;
+	unsigned long usart_hz;
+
+	/*
+	 *              Master Clock
+	 * Baud Rate = --------------
+	 *                16 * CD
+	 */
+	usart_hz = pm_get_clock_freq(gd->console_uart->resource[0].u.clock.id);
+	divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
+	usart3_writel(gd->console_uart, BRGR, USART3_BF(CD, divisor));
+}
+
+int serial_init(void)
+{
+	usart3_writel(gd->console_uart, CR,
+		      USART3_BIT(RSTRX) | USART3_BIT(RSTTX));
+
+	serial_setbrg();
+
+	usart3_writel(gd->console_uart, CR,
+		      USART3_BIT(RXEN) | USART3_BIT(TXEN));
+	usart3_writel(gd->console_uart, MR,
+		      USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
+		      | USART3_BF(USCLKS, USART3_USCLKS_MCK)
+		      | USART3_BF(CHRL, USART3_CHRL_8)
+		      | USART3_BF(PAR, USART3_PAR_NONE)
+		      | USART3_BF(NBSTOP, USART3_NBSTOP_1));
+
+	return 0;
+}
+
+void serial_putc(char c)
+{
+	if (c == '\n')
+		serial_putc('\r');
+
+	while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(TXRDY))) ;
+	usart3_writel(gd->console_uart, THR, c);
+}
+
+void serial_puts(const char *s)
+{
+	while (*s)
+		serial_putc(*s++);
+}
+
+int serial_getc(void)
+{
+	while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY))) ;
+	return usart3_readl(gd->console_uart, RHR);
+}
+
+int serial_tstc(void)
+{
+	return (usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY)) != 0;
+}
+
+#endif /* CONFIG_ATMEL_USART */
diff --git a/drivers/atmel_usart.h b/drivers/atmel_usart.h
new file mode 100644
index 0000000..fad90a8
--- /dev/null
+++ b/drivers/atmel_usart.h
@@ -0,0 +1,314 @@
+/*
+ * Register definitions for the Atmel USART3 module.
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __DRIVERS_ATMEL_USART_H__
+#define __DRIVERS_ATMEL_USART_H__
+
+/* USART3 register offsets */
+#define USART3_CR				0x0000
+#define USART3_MR				0x0004
+#define USART3_IER				0x0008
+#define USART3_IDR				0x000c
+#define USART3_IMR				0x0010
+#define USART3_CSR				0x0014
+#define USART3_RHR				0x0018
+#define USART3_THR				0x001c
+#define USART3_BRGR				0x0020
+#define USART3_RTOR				0x0024
+#define USART3_TTGR				0x0028
+#define USART3_FIDI				0x0040
+#define USART3_NER				0x0044
+#define USART3_XXR				0x0048
+#define USART3_IFR				0x004c
+#define USART3_RPR				0x0100
+#define USART3_RCR				0x0104
+#define USART3_TPR				0x0108
+#define USART3_TCR				0x010c
+#define USART3_RNPR				0x0110
+#define USART3_RNCR				0x0114
+#define USART3_TNPR				0x0118
+#define USART3_TNCR				0x011c
+#define USART3_PTCR				0x0120
+#define USART3_PTSR				0x0124
+
+/* Bitfields in CR */
+#define USART3_RSTRX_OFFSET			2
+#define USART3_RSTRX_SIZE			1
+#define USART3_RSTTX_OFFSET			3
+#define USART3_RSTTX_SIZE			1
+#define USART3_RXEN_OFFSET			4
+#define USART3_RXEN_SIZE			1
+#define USART3_RXDIS_OFFSET			5
+#define USART3_RXDIS_SIZE			1
+#define USART3_TXEN_OFFSET			6
+#define USART3_TXEN_SIZE			1
+#define USART3_TXDIS_OFFSET			7
+#define USART3_TXDIS_SIZE			1
+#define USART3_RSTSTA_OFFSET			8
+#define USART3_RSTSTA_SIZE			1
+#define USART3_STTBRK_OFFSET			9
+#define USART3_STTBRK_SIZE			1
+#define USART3_STPBRK_OFFSET			10
+#define USART3_STPBRK_SIZE			1
+#define USART3_STTTO_OFFSET			11
+#define USART3_STTTO_SIZE			1
+#define USART3_SENDA_OFFSET			12
+#define USART3_SENDA_SIZE			1
+#define USART3_RSTIT_OFFSET			13
+#define USART3_RSTIT_SIZE			1
+#define USART3_RSTNACK_OFFSET			14
+#define USART3_RSTNACK_SIZE			1
+#define USART3_RETTO_OFFSET			15
+#define USART3_RETTO_SIZE			1
+#define USART3_DTREN_OFFSET			16
+#define USART3_DTREN_SIZE			1
+#define USART3_DTRDIS_OFFSET			17
+#define USART3_DTRDIS_SIZE			1
+#define USART3_RTSEN_OFFSET			18
+#define USART3_RTSEN_SIZE			1
+#define USART3_RTSDIS_OFFSET			19
+#define USART3_RTSDIS_SIZE			1
+#define USART3_COMM_TX_OFFSET			30
+#define USART3_COMM_TX_SIZE			1
+#define USART3_COMM_RX_OFFSET			31
+#define USART3_COMM_RX_SIZE			1
+
+/* Bitfields in MR */
+#define USART3_USART_MODE_OFFSET		0
+#define USART3_USART_MODE_SIZE			4
+#define USART3_USCLKS_OFFSET			4
+#define USART3_USCLKS_SIZE			2
+#define USART3_CHRL_OFFSET			6
+#define USART3_CHRL_SIZE			2
+#define USART3_SYNC_OFFSET			8
+#define USART3_SYNC_SIZE			1
+#define USART3_PAR_OFFSET			9
+#define USART3_PAR_SIZE				3
+#define USART3_NBSTOP_OFFSET			12
+#define USART3_NBSTOP_SIZE			2
+#define USART3_CHMODE_OFFSET			14
+#define USART3_CHMODE_SIZE			2
+#define USART3_MSBF_OFFSET			16
+#define USART3_MSBF_SIZE			1
+#define USART3_MODE9_OFFSET			17
+#define USART3_MODE9_SIZE			1
+#define USART3_CLKO_OFFSET			18
+#define USART3_CLKO_SIZE			1
+#define USART3_OVER_OFFSET			19
+#define USART3_OVER_SIZE			1
+#define USART3_INACK_OFFSET			20
+#define USART3_INACK_SIZE			1
+#define USART3_DSNACK_OFFSET			21
+#define USART3_DSNACK_SIZE			1
+#define USART3_MAX_ITERATION_OFFSET		24
+#define USART3_MAX_ITERATION_SIZE		3
+#define USART3_FILTER_OFFSET			28
+#define USART3_FILTER_SIZE			1
+
+/* Bitfields in CSR */
+#define USART3_RXRDY_OFFSET			0
+#define USART3_RXRDY_SIZE			1
+#define USART3_TXRDY_OFFSET			1
+#define USART3_TXRDY_SIZE			1
+#define USART3_RXBRK_OFFSET			2
+#define USART3_RXBRK_SIZE			1
+#define USART3_ENDRX_OFFSET			3
+#define USART3_ENDRX_SIZE			1
+#define USART3_ENDTX_OFFSET			4
+#define USART3_ENDTX_SIZE			1
+#define USART3_OVRE_OFFSET			5
+#define USART3_OVRE_SIZE			1
+#define USART3_FRAME_OFFSET			6
+#define USART3_FRAME_SIZE			1
+#define USART3_PARE_OFFSET			7
+#define USART3_PARE_SIZE			1
+#define USART3_TIMEOUT_OFFSET			8
+#define USART3_TIMEOUT_SIZE			1
+#define USART3_TXEMPTY_OFFSET			9
+#define USART3_TXEMPTY_SIZE			1
+#define USART3_ITERATION_OFFSET			10
+#define USART3_ITERATION_SIZE			1
+#define USART3_TXBUFE_OFFSET			11
+#define USART3_TXBUFE_SIZE			1
+#define USART3_RXBUFF_OFFSET			12
+#define USART3_RXBUFF_SIZE			1
+#define USART3_NACK_OFFSET			13
+#define USART3_NACK_SIZE			1
+#define USART3_RIIC_OFFSET			16
+#define USART3_RIIC_SIZE			1
+#define USART3_DSRIC_OFFSET			17
+#define USART3_DSRIC_SIZE			1
+#define USART3_DCDIC_OFFSET			18
+#define USART3_DCDIC_SIZE			1
+#define USART3_CTSIC_OFFSET			19
+#define USART3_CTSIC_SIZE			1
+#define USART3_RI_OFFSET			20
+#define USART3_RI_SIZE				1
+#define USART3_DSR_OFFSET			21
+#define USART3_DSR_SIZE				1
+#define USART3_DCD_OFFSET			22
+#define USART3_DCD_SIZE				1
+#define USART3_CTS_OFFSET			23
+#define USART3_CTS_SIZE				1
+
+/* Bitfields in RHR */
+#define USART3_RXCHR_OFFSET			0
+#define USART3_RXCHR_SIZE			9
+
+/* Bitfields in THR */
+#define USART3_TXCHR_OFFSET			0
+#define USART3_TXCHR_SIZE			9
+
+/* Bitfields in BRGR */
+#define USART3_CD_OFFSET			0
+#define USART3_CD_SIZE				16
+
+/* Bitfields in RTOR */
+#define USART3_TO_OFFSET			0
+#define USART3_TO_SIZE				16
+
+/* Bitfields in TTGR */
+#define USART3_TG_OFFSET			0
+#define USART3_TG_SIZE				8
+
+/* Bitfields in FIDI */
+#define USART3_FI_DI_RATIO_OFFSET		0
+#define USART3_FI_DI_RATIO_SIZE			11
+
+/* Bitfields in NER */
+#define USART3_NB_ERRORS_OFFSET			0
+#define USART3_NB_ERRORS_SIZE			8
+
+/* Bitfields in XXR */
+#define USART3_XOFF_OFFSET			0
+#define USART3_XOFF_SIZE			8
+#define USART3_XON_OFFSET			8
+#define USART3_XON_SIZE				8
+
+/* Bitfields in IFR */
+#define USART3_IRDA_FILTER_OFFSET		0
+#define USART3_IRDA_FILTER_SIZE			8
+
+/* Bitfields in RCR */
+#define USART3_RXCTR_OFFSET			0
+#define USART3_RXCTR_SIZE			16
+
+/* Bitfields in TCR */
+#define USART3_TXCTR_OFFSET			0
+#define USART3_TXCTR_SIZE			16
+
+/* Bitfields in RNCR */
+#define USART3_RXNCR_OFFSET			0
+#define USART3_RXNCR_SIZE			16
+
+/* Bitfields in TNCR */
+#define USART3_TXNCR_OFFSET			0
+#define USART3_TXNCR_SIZE			16
+
+/* Bitfields in PTCR */
+#define USART3_RXTEN_OFFSET			0
+#define USART3_RXTEN_SIZE			1
+#define USART3_RXTDIS_OFFSET			1
+#define USART3_RXTDIS_SIZE			1
+#define USART3_TXTEN_OFFSET			8
+#define USART3_TXTEN_SIZE			1
+#define USART3_TXTDIS_OFFSET			9
+#define USART3_TXTDIS_SIZE			1
+
+/* Constants for USART_MODE */
+#define USART3_USART_MODE_NORMAL		0
+#define USART3_USART_MODE_RS485			1
+#define USART3_USART_MODE_HARDWARE		2
+#define USART3_USART_MODE_MODEM			3
+#define USART3_USART_MODE_ISO7816_T0		4
+#define USART3_USART_MODE_ISO7816_T1		6
+#define USART3_USART_MODE_IRDA			8
+
+/* Constants for USCLKS */
+#define USART3_USCLKS_MCK			0
+#define USART3_USCLKS_MCK_DIV			1
+#define USART3_USCLKS_SCK			3
+
+/* Constants for CHRL */
+#define USART3_CHRL_5				0
+#define USART3_CHRL_6				1
+#define USART3_CHRL_7				2
+#define USART3_CHRL_8				3
+
+/* Constants for PAR */
+#define USART3_PAR_EVEN				0
+#define USART3_PAR_ODD				1
+#define USART3_PAR_SPACE			2
+#define USART3_PAR_MARK				3
+#define USART3_PAR_NONE				4
+#define USART3_PAR_MULTI			6
+
+/* Constants for NBSTOP */
+#define USART3_NBSTOP_1				0
+#define USART3_NBSTOP_1_5			1
+#define USART3_NBSTOP_2				2
+
+/* Constants for CHMODE */
+#define USART3_CHMODE_NORMAL			0
+#define USART3_CHMODE_ECHO			1
+#define USART3_CHMODE_LOCAL_LOOP		2
+#define USART3_CHMODE_REMOTE_LOOP		3
+
+/* Constants for MSBF */
+#define USART3_MSBF_LSBF			0
+#define USART3_MSBF_MSBF			1
+
+/* Constants for OVER */
+#define USART3_OVER_X16				0
+#define USART3_OVER_X8				1
+
+/* Constants for CD */
+#define USART3_CD_DISABLE			0
+#define USART3_CD_BYPASS			1
+
+/* Constants for TO */
+#define USART3_TO_DISABLE			0
+
+/* Constants for TG */
+#define USART3_TG_DISABLE			0
+
+/* Constants for FI_DI_RATIO */
+#define USART3_FI_DI_RATIO_DISABLE		0
+
+/* Bit manipulation macros */
+#define USART3_BIT(name)				\
+	(1 << USART3_##name##_OFFSET)
+#define USART3_BF(name,value)				\
+	(((value) & ((1 << USART3_##name##_SIZE) - 1))	\
+	 << USART3_##name##_OFFSET)
+#define USART3_BFEXT(name,value)			\
+	(((value) >> USART3_##name##_OFFSET)		\
+	 & ((1 << USART3_##name##_SIZE) - 1))
+#define USART3_BFINS(name,value,old)			\
+	(((old) & ~(((1 << USART3_##name##_SIZE) - 1)	\
+		    << USART3_##name##_OFFSET))		\
+	 | USART3_BF(name,value))
+
+/* Register access macros */
+#define usart3_readl(port,reg)				\
+	readl((port)->regs + USART3_##reg)
+#define usart3_writel(port,reg,value)			\
+	writel((value), (port)->regs + USART3_##reg)
+
+#endif /* __DRIVERS_ATMEL_USART_H__ */
-- 
cgit v0.10.2


From 6ccec4492e77428fd6eafd3dfe94fbdf08e91d37 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue, 24 Oct 2006 14:42:37 +0200
Subject: Add ATSTK1000 and ATSTK1002 board support Patch by Haavard
 Skinnemoen, 06 Sep 2006

This patch adds support for the ATSTK1000 with the ATSTK1002 CPU
daughterboard.

ATSTK1000 is a full-featured development board for AT32AP CPUs. It
has two ethernet ports, a high quality QVGA LCD panel, a loudspeaker,
and connectors for USART, PS/2, VGA, USB, MMC/SD cards and
CompactFlash cards. For more information, please see this page:

http://www.atmel.com/dyn/products/tools.asp?family_id=682

The ATSTK1002 is a daughterboard for the ATSTK1000 supporting the
AT32AP7000 chip.

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index d7ef203..cff3957 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -561,6 +561,10 @@ Zachary P. Landau <zachary.landau@labxtechnologies.com>
 #	Board			CPU					#
 #########################################################################
 
+Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+	ATSTK1000		AT32AP7000
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 4409f2b..879a17f 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -302,6 +302,12 @@ LIST_coldfire="	\
 	r5200		M5271EVB					\
 "
 
+#########################################################################
+## AVR32 Systems
+#########################################################################
+
+LIST_avr32="atstk1002"
+
 #-----------------------------------------------------------------------
 
 #----- for now, just run PPC by default -----
@@ -334,7 +340,8 @@ do
 	mips|mips_el| \
 	nios|nios2| \
 	x86|I486| \
-	coldfire)
+	coldfire| \
+	avr32)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}
diff --git a/README b/README
index 69af79a..f83d774 100644
--- a/README
+++ b/README
@@ -330,6 +330,15 @@ The following options need to be configured:
 		CONFIG_PCI5441 CONFIG_PK1C20
 		CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40
 
+		AVR32 based boards:
+		-------------------
+
+		CONFIG_ATSTK1000
+
+- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
+		Define exactly one of
+		CONFIG_ATSTK1002
+
 
 - CPU Module Type: (if CONFIG_COGENT is defined)
 		Define exactly one of
diff --git a/board/atstk1000/Makefile b/board/atstk1000/Makefile
new file mode 100644
index 0000000..22ac02a
--- /dev/null
+++ b/board/atstk1000/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/atstk1000/atstk1000.c b/board/atstk1000/atstk1000.c
new file mode 100644
index 0000000..4d737d2
--- /dev/null
+++ b/board/atstk1000/atstk1000.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct sdram_info sdram = {
+	.phys_addr	= CFG_SDRAM_BASE,
+	.row_bits	= 11,
+	.col_bits	= 8,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 5,
+};
+
+void board_init_memories(void)
+{
+	gd->sdram_size = sdram_init(&sdram);
+}
+
+void board_init_info(void)
+{
+	gd->bd->bi_phy_id[0] = 0x10;
+	gd->bd->bi_phy_id[1] = 0x11;
+}
diff --git a/board/atstk1000/config.mk b/board/atstk1000/config.mk
new file mode 100644
index 0000000..a72c80e
--- /dev/null
+++ b/board/atstk1000/config.mk
@@ -0,0 +1,4 @@
+PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS	+= --gc-sections
+TEXT_BASE		= 0x00000000
+LDSCRIPT		= $(obj)board/atstk1000/u-boot.lds
diff --git a/board/atstk1000/flash.c b/board/atstk1000/flash.c
new file mode 100644
index 0000000..3aebf66
--- /dev/null
+++ b/board/atstk1000/flash.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_ATSTK1000_EXT_FLASH
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+flash_info_t flash_info[1];
+
+static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info)
+{
+	unsigned long flags;
+
+	flags = disable_interrupts();
+
+	dcache_flush_unlocked();
+
+	writew(0xaa, flash + 0x555);
+	writew(0x55, flash + 0xaaa);
+	writew(0x90, flash + 0x555);
+	info->flash_id = readl(flash);
+	writew(0xff, flash);
+
+	readw(flash);
+
+	if (flags)
+		enable_interrupts();
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long addr;
+	unsigned int i;
+
+	gd->bd->bi_flashstart = CFG_FLASH_BASE;
+	gd->bd->bi_flashsize = CFG_FLASH_SIZE;
+	gd->bd->bi_flashoffset = __edata_lma - _text;
+
+	flash_info[0].size = CFG_FLASH_SIZE;
+	flash_info[0].sector_count = 135;
+
+	flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]);
+
+	for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
+		flash_info[0].start[i] = addr;
+	for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
+		flash_info[0].start[i] = addr;
+
+	return CFG_FLASH_SIZE;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n",
+	       info->flash_id >> 16, info->flash_id & 0xffff);
+	printf("Size: %ld MB in %d sectors\n",
+	       info->size >> 10, info->sector_count);
+}
+
+int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long flags;
+	unsigned long start_time;
+	uint16_t *fb, *sb;
+	unsigned int i;
+	int ret;
+	uint16_t status;
+
+	if ((s_first < 0) || (s_first > s_last)
+	    || (s_last >= info->sector_count)) {
+		puts("Error: first and/or last sector out of range\n");
+		return ERR_INVAL;
+	}
+
+	for (i = s_first; i < s_last; i++)
+		if (info->protect[i]) {
+			printf("Error: sector %d is protected\n", i);
+			return ERR_PROTECTED;
+		}
+
+	fb = (uint16_t *)uncached(info->start[0]);
+
+	dcache_flush_unlocked();
+
+	for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
+		printf("Erasing sector %3d...", i);
+
+		sb = (uint16_t *)uncached(info->start[i]);
+
+		flags = disable_interrupts();
+
+		start_time = get_timer(0);
+
+		/* Unlock sector */
+		writew(0xaa, fb + 0x555);
+		writew(0x70, sb);
+
+		/* Erase sector */
+		writew(0xaa, fb + 0x555);
+		writew(0x55, fb + 0xaaa);
+		writew(0x80, fb + 0x555);
+		writew(0xaa, fb + 0x555);
+		writew(0x55, fb + 0xaaa);
+		writew(0x30, sb);
+
+		/* Wait for completion */
+		ret = ERR_OK;
+		do {
+			/* TODO: Timeout */
+			status = readw(sb);
+		} while ((status != 0xffff) && !(status & 0x28));
+
+		writew(0xf0, fb);
+
+		/*
+		 * Make sure the command actually makes it to the bus
+		 * before we re-enable interrupts.
+		 */
+		readw(fb);
+
+		if (flags)
+			enable_interrupts();
+
+		if (status != 0xffff) {
+			printf("Flash erase error at address 0x%p: 0x%02x\n",
+			       sb, status);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+	}
+
+	if (ctrlc())
+		printf("User interrupt!\n");
+
+	return ERR_OK;
+}
+
+int __flashprog write_buff(flash_info_t *info, uchar *src,
+			   ulong addr, ulong count)
+{
+	unsigned long flags;
+	uint16_t *base, *p, *s, *end;
+	uint16_t word, status;
+	int ret = ERR_OK;
+
+	if (addr < info->start[0]
+	    || (addr + count) > (info->start[0] + info->size)
+	    || (addr + count) < addr) {
+		puts("Error: invalid address range\n");
+		return ERR_INVAL;
+	}
+
+	if (addr & 1 || count & 1 || (unsigned int)src & 1) {
+		puts("Error: misaligned source, destination or count\n");
+		return ERR_ALIGN;
+	}
+
+	base = (uint16_t *)uncached(info->start[0]);
+	end = (uint16_t *)uncached(addr + count);
+
+	flags = disable_interrupts();
+
+	dcache_flush_unlocked();
+	sync_write_buffer();
+
+	for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
+	     p < end && !ctrlc(); p++, s++) {
+		word = *s;
+
+		writew(0xaa, base + 0x555);
+		writew(0x55, base + 0xaaa);
+		writew(0xa0, base + 0x555);
+		writew(word, p);
+
+		sync_write_buffer();
+
+		/* Wait for completion */
+		do {
+			/* TODO: Timeout */
+			status = readw(p);
+		} while ((status != word) && !(status & 0x28));
+
+		writew(0xf0, base);
+		readw(base);
+
+		if (status != word) {
+			printf("Flash write error at address 0x%p: 0x%02x\n",
+			       p, status);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+	}
+
+	if (flags)
+		enable_interrupts();
+
+	return ret;
+}
+
+#endif /* CONFIG_ATSTK1000_EXT_FLASH */
diff --git a/board/atstk1000/u-boot.lds.S b/board/atstk1000/u-boot.lds.S
new file mode 100644
index 0000000..d46b82c
--- /dev/null
+++ b/board/atstk1000/u-boot.lds.S
@@ -0,0 +1,79 @@
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = CFG_FLASH_BASE;
+	_text = .;
+	.text : {
+		*(.text)
+		*(.text.*)
+	}
+
+	. = ALIGN(CFG_ICACHE_LINESZ);
+	__flashprog_start = .;
+	.flashprog : {
+		*(.flashprog)
+	}
+	. = ALIGN(CFG_ICACHE_LINESZ);
+	__flashprog_end = .;
+
+	. = ALIGN(8);
+	.rodata : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	_etext = .;
+
+	__data_lma = ALIGN(8);
+	. = CFG_INTRAM_BASE;
+	_data = .;
+	.data : AT(__data_lma) {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	__u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data);
+	.u_boot_cmd : AT(__u_boot_cmd_lma) {
+		KEEP(*(.u_boot_cmd))
+	}
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(8);
+	_edata = .;
+	__edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start);
+
+	.bss : AT(__edata_lma) {
+		*(.bss)
+		*(.bss.*)
+	}
+	. = ALIGN(8);
+	_end = .;
+}
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
new file mode 100644
index 0000000..458ebab
--- /dev/null
+++ b/include/configs/atstk1002.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1002 CPU daughterboard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AVR32			1
+#define CONFIG_AT32AP			1
+#define CONFIG_AT32AP7000		1
+#define CONFIG_ATSTK1002		1
+#define CONFIG_ATSTK1000		1
+
+#define CONFIG_ATSTK1000_EXT_FLASH	1
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CFG_HZ				1000
+
+/*
+ * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
+ * frequency and the peripherals to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL			1
+#define CFG_POWER_MANAGER		1
+#define CFG_OSC0_HZ			20000000
+#define CFG_PLL0_DIV			1
+#define CFG_PLL0_MUL			7
+#define CFG_PLL0_SUPPRESS_CYCLES	16
+#define CFG_CLKDIV_CPU			0
+#define CFG_CLKDIV_HSB			1
+#define CFG_CLKDIV_PBA			2
+#define CFG_CLKDIV_PBB			1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT			0x04
+
+#define CFG_USART1			1
+
+#define CFG_CONSOLE_UART_DEV		DEVICE_USART1
+
+/* User serviceable stuff */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyUS0 root=/dev/mtdblock1 fbmem=600k"
+
+#define CONFIG_COMMANDS			(CFG_CMD_BDI			\
+					 | CFG_CMD_LOADS		\
+					 | CFG_CMD_LOADB		\
+					 /* | CFG_CMD_IMI */		\
+					 /* | CFG_CMD_CACHE */		\
+					 | CFG_CMD_FLASH		\
+					 | CFG_CMD_MEMORY		\
+					 /* | CFG_CMD_NET */		\
+					 | CFG_CMD_ENV			\
+					 /* | CFG_CMD_IRQ */		\
+					 | CFG_CMD_BOOTD		\
+					 | CFG_CMD_CONSOLE		\
+					 /* | CFG_CMD_EEPROM */		\
+					 | CFG_CMD_ASKENV		\
+					 | CFG_CMD_RUN			\
+					 | CFG_CMD_ECHO			\
+					 /* | CFG_CMD_I2C */		\
+					 | CFG_CMD_REGINFO		\
+					 /* | CFG_CMD_DATE */		\
+					 /* | CFG_CMD_DHCP */		\
+					 /* | CFG_CMD_AUTOSCRIPT */	\
+					 /* | CFG_CMD_MII */		\
+					 | CFG_CMD_MISC			\
+					 /* | CFG_CMD_SDRAM */		\
+					 /* | CFG_CMD_DIAG */		\
+					 /* | CFG_CMD_HWFLOW */		\
+					 /* | CFG_CMD_SAVES */		\
+					 /* | CFG_CMD_SPI */		\
+					 /* | CFG_CMD_PING */		\
+					 /* | CFG_CMD_MMC */		\
+					 /* | CFG_CMD_FAT */		\
+					 /* | CFG_CMD_IMLS */		\
+					 /* | CFG_CMD_ITEST */		\
+					 /* | CFG_CMD_EXT2 */		\
+		)
+
+#include <cmd_confdefs.h>
+
+#define CONFIG_ATMEL_USART		1
+#define CONFIG_PIO2			1
+#define CFG_NR_PIOS			5
+#define CFG_HSDRAMC			1
+
+#define CFG_DCACHE_LINESZ		32
+#define CFG_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+/* External flash on STK1000 */
+#if 0
+#define CFG_FLASH_CFI			1
+#define CFG_FLASH_CFI_DRIVER		1
+#endif
+
+#define CFG_FLASH_BASE			0x00000000
+#define CFG_FLASH_SIZE			0x800000
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		135
+
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE			0x24000000
+#define CFG_INTRAM_SIZE			0x8000
+
+#define CFG_SDRAM_BASE			0x10000000
+
+#define CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_SIZE			65536
+#define CFG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN			(256*1024)
+#define CFG_MALLOC_END							\
+	({								\
+		DECLARE_GLOBAL_DATA_PTR;				\
+		CFG_SDRAM_BASE + gd->sdram_size;			\
+	})
+#define CFG_MALLOC_START		(CFG_MALLOC_END - CFG_MALLOC_LEN)
+
+#define CFG_DMA_ALLOC_LEN		(16384)
+#define CFG_DMA_ALLOC_END		(CFG_MALLOC_START)
+#define CFG_DMA_ALLOC_START		(CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
+/* Allow 2MB for the kernel run-time image */
+#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00200000)
+#define CFG_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT			"Uboot> "
+#define CFG_CBSIZE			256
+#define CFG_MAXARGS			8
+#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP			1
+
+#define CFG_MEMTEST_START						\
+	({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
+#define CFG_MEMTEST_END							\
+	({								\
+		DECLARE_GLOBAL_DATA_PTR;				\
+		gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;	\
+	})
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
-- 
cgit v0.10.2


From 3a78e3e75b633ecb6413114ffd11e2f000c4f11e Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue, 24 Oct 2006 14:51:36 +0200
Subject: Move atstk1000 files into vendor specific directory. Patch by Haavard
 Skinnemoen, 12 Sep 2006


diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile
new file mode 100644
index 0000000..22ac02a
--- /dev/null
+++ b/board/atmel/atstk1000/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c
new file mode 100644
index 0000000..4d737d2
--- /dev/null
+++ b/board/atmel/atstk1000/atstk1000.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct sdram_info sdram = {
+	.phys_addr	= CFG_SDRAM_BASE,
+	.row_bits	= 11,
+	.col_bits	= 8,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 5,
+};
+
+void board_init_memories(void)
+{
+	gd->sdram_size = sdram_init(&sdram);
+}
+
+void board_init_info(void)
+{
+	gd->bd->bi_phy_id[0] = 0x10;
+	gd->bd->bi_phy_id[1] = 0x11;
+}
diff --git a/board/atmel/atstk1000/config.mk b/board/atmel/atstk1000/config.mk
new file mode 100644
index 0000000..ec3618d
--- /dev/null
+++ b/board/atmel/atstk1000/config.mk
@@ -0,0 +1,4 @@
+PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS	+= --gc-sections
+TEXT_BASE		= 0x00000000
+LDSCRIPT		= $(obj)board/atmel/atstk1000/u-boot.lds
diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c
new file mode 100644
index 0000000..3aebf66
--- /dev/null
+++ b/board/atmel/atstk1000/flash.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_ATSTK1000_EXT_FLASH
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+flash_info_t flash_info[1];
+
+static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info)
+{
+	unsigned long flags;
+
+	flags = disable_interrupts();
+
+	dcache_flush_unlocked();
+
+	writew(0xaa, flash + 0x555);
+	writew(0x55, flash + 0xaaa);
+	writew(0x90, flash + 0x555);
+	info->flash_id = readl(flash);
+	writew(0xff, flash);
+
+	readw(flash);
+
+	if (flags)
+		enable_interrupts();
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long addr;
+	unsigned int i;
+
+	gd->bd->bi_flashstart = CFG_FLASH_BASE;
+	gd->bd->bi_flashsize = CFG_FLASH_SIZE;
+	gd->bd->bi_flashoffset = __edata_lma - _text;
+
+	flash_info[0].size = CFG_FLASH_SIZE;
+	flash_info[0].sector_count = 135;
+
+	flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]);
+
+	for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
+		flash_info[0].start[i] = addr;
+	for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
+		flash_info[0].start[i] = addr;
+
+	return CFG_FLASH_SIZE;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n",
+	       info->flash_id >> 16, info->flash_id & 0xffff);
+	printf("Size: %ld MB in %d sectors\n",
+	       info->size >> 10, info->sector_count);
+}
+
+int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long flags;
+	unsigned long start_time;
+	uint16_t *fb, *sb;
+	unsigned int i;
+	int ret;
+	uint16_t status;
+
+	if ((s_first < 0) || (s_first > s_last)
+	    || (s_last >= info->sector_count)) {
+		puts("Error: first and/or last sector out of range\n");
+		return ERR_INVAL;
+	}
+
+	for (i = s_first; i < s_last; i++)
+		if (info->protect[i]) {
+			printf("Error: sector %d is protected\n", i);
+			return ERR_PROTECTED;
+		}
+
+	fb = (uint16_t *)uncached(info->start[0]);
+
+	dcache_flush_unlocked();
+
+	for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
+		printf("Erasing sector %3d...", i);
+
+		sb = (uint16_t *)uncached(info->start[i]);
+
+		flags = disable_interrupts();
+
+		start_time = get_timer(0);
+
+		/* Unlock sector */
+		writew(0xaa, fb + 0x555);
+		writew(0x70, sb);
+
+		/* Erase sector */
+		writew(0xaa, fb + 0x555);
+		writew(0x55, fb + 0xaaa);
+		writew(0x80, fb + 0x555);
+		writew(0xaa, fb + 0x555);
+		writew(0x55, fb + 0xaaa);
+		writew(0x30, sb);
+
+		/* Wait for completion */
+		ret = ERR_OK;
+		do {
+			/* TODO: Timeout */
+			status = readw(sb);
+		} while ((status != 0xffff) && !(status & 0x28));
+
+		writew(0xf0, fb);
+
+		/*
+		 * Make sure the command actually makes it to the bus
+		 * before we re-enable interrupts.
+		 */
+		readw(fb);
+
+		if (flags)
+			enable_interrupts();
+
+		if (status != 0xffff) {
+			printf("Flash erase error at address 0x%p: 0x%02x\n",
+			       sb, status);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+	}
+
+	if (ctrlc())
+		printf("User interrupt!\n");
+
+	return ERR_OK;
+}
+
+int __flashprog write_buff(flash_info_t *info, uchar *src,
+			   ulong addr, ulong count)
+{
+	unsigned long flags;
+	uint16_t *base, *p, *s, *end;
+	uint16_t word, status;
+	int ret = ERR_OK;
+
+	if (addr < info->start[0]
+	    || (addr + count) > (info->start[0] + info->size)
+	    || (addr + count) < addr) {
+		puts("Error: invalid address range\n");
+		return ERR_INVAL;
+	}
+
+	if (addr & 1 || count & 1 || (unsigned int)src & 1) {
+		puts("Error: misaligned source, destination or count\n");
+		return ERR_ALIGN;
+	}
+
+	base = (uint16_t *)uncached(info->start[0]);
+	end = (uint16_t *)uncached(addr + count);
+
+	flags = disable_interrupts();
+
+	dcache_flush_unlocked();
+	sync_write_buffer();
+
+	for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
+	     p < end && !ctrlc(); p++, s++) {
+		word = *s;
+
+		writew(0xaa, base + 0x555);
+		writew(0x55, base + 0xaaa);
+		writew(0xa0, base + 0x555);
+		writew(word, p);
+
+		sync_write_buffer();
+
+		/* Wait for completion */
+		do {
+			/* TODO: Timeout */
+			status = readw(p);
+		} while ((status != word) && !(status & 0x28));
+
+		writew(0xf0, base);
+		readw(base);
+
+		if (status != word) {
+			printf("Flash write error at address 0x%p: 0x%02x\n",
+			       p, status);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+	}
+
+	if (flags)
+		enable_interrupts();
+
+	return ret;
+}
+
+#endif /* CONFIG_ATSTK1000_EXT_FLASH */
diff --git a/board/atmel/atstk1000/u-boot.lds.S b/board/atmel/atstk1000/u-boot.lds.S
new file mode 100644
index 0000000..d46b82c
--- /dev/null
+++ b/board/atmel/atstk1000/u-boot.lds.S
@@ -0,0 +1,79 @@
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = CFG_FLASH_BASE;
+	_text = .;
+	.text : {
+		*(.text)
+		*(.text.*)
+	}
+
+	. = ALIGN(CFG_ICACHE_LINESZ);
+	__flashprog_start = .;
+	.flashprog : {
+		*(.flashprog)
+	}
+	. = ALIGN(CFG_ICACHE_LINESZ);
+	__flashprog_end = .;
+
+	. = ALIGN(8);
+	.rodata : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+	_etext = .;
+
+	__data_lma = ALIGN(8);
+	. = CFG_INTRAM_BASE;
+	_data = .;
+	.data : AT(__data_lma) {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	__u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data);
+	.u_boot_cmd : AT(__u_boot_cmd_lma) {
+		KEEP(*(.u_boot_cmd))
+	}
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(8);
+	_edata = .;
+	__edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start);
+
+	.bss : AT(__edata_lma) {
+		*(.bss)
+		*(.bss.*)
+	}
+	. = ALIGN(8);
+	_end = .;
+}
diff --git a/board/atstk1000/Makefile b/board/atstk1000/Makefile
deleted file mode 100644
index 22ac02a..0000000
--- a/board/atstk1000/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(BOARD).a
-
-COBJS	:= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-$(LIB): $(obj).depend $(OBJS)
-	$(AR) crv $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/atstk1000/atstk1000.c b/board/atstk1000/atstk1000.c
deleted file mode 100644
index 4d737d2..0000000
--- a/board/atstk1000/atstk1000.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct sdram_info sdram = {
-	.phys_addr	= CFG_SDRAM_BASE,
-	.row_bits	= 11,
-	.col_bits	= 8,
-	.bank_bits	= 2,
-	.cas		= 3,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 5,
-	.txsr		= 5,
-};
-
-void board_init_memories(void)
-{
-	gd->sdram_size = sdram_init(&sdram);
-}
-
-void board_init_info(void)
-{
-	gd->bd->bi_phy_id[0] = 0x10;
-	gd->bd->bi_phy_id[1] = 0x11;
-}
diff --git a/board/atstk1000/config.mk b/board/atstk1000/config.mk
deleted file mode 100644
index a72c80e..0000000
--- a/board/atstk1000/config.mk
+++ /dev/null
@@ -1,4 +0,0 @@
-PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
-PLATFORM_LDFLAGS	+= --gc-sections
-TEXT_BASE		= 0x00000000
-LDSCRIPT		= $(obj)board/atstk1000/u-boot.lds
diff --git a/board/atstk1000/flash.c b/board/atstk1000/flash.c
deleted file mode 100644
index 3aebf66..0000000
--- a/board/atstk1000/flash.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-
-#ifdef CONFIG_ATSTK1000_EXT_FLASH
-#include <asm/cacheflush.h>
-#include <asm/io.h>
-#include <asm/sections.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-flash_info_t flash_info[1];
-
-static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info)
-{
-	unsigned long flags;
-
-	flags = disable_interrupts();
-
-	dcache_flush_unlocked();
-
-	writew(0xaa, flash + 0x555);
-	writew(0x55, flash + 0xaaa);
-	writew(0x90, flash + 0x555);
-	info->flash_id = readl(flash);
-	writew(0xff, flash);
-
-	readw(flash);
-
-	if (flags)
-		enable_interrupts();
-}
-
-unsigned long flash_init(void)
-{
-	unsigned long addr;
-	unsigned int i;
-
-	gd->bd->bi_flashstart = CFG_FLASH_BASE;
-	gd->bd->bi_flashsize = CFG_FLASH_SIZE;
-	gd->bd->bi_flashoffset = __edata_lma - _text;
-
-	flash_info[0].size = CFG_FLASH_SIZE;
-	flash_info[0].sector_count = 135;
-
-	flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]);
-
-	for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
-		flash_info[0].start[i] = addr;
-	for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
-		flash_info[0].start[i] = addr;
-
-	return CFG_FLASH_SIZE;
-}
-
-void flash_print_info(flash_info_t *info)
-{
-	printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n",
-	       info->flash_id >> 16, info->flash_id & 0xffff);
-	printf("Size: %ld MB in %d sectors\n",
-	       info->size >> 10, info->sector_count);
-}
-
-int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
-{
-	unsigned long flags;
-	unsigned long start_time;
-	uint16_t *fb, *sb;
-	unsigned int i;
-	int ret;
-	uint16_t status;
-
-	if ((s_first < 0) || (s_first > s_last)
-	    || (s_last >= info->sector_count)) {
-		puts("Error: first and/or last sector out of range\n");
-		return ERR_INVAL;
-	}
-
-	for (i = s_first; i < s_last; i++)
-		if (info->protect[i]) {
-			printf("Error: sector %d is protected\n", i);
-			return ERR_PROTECTED;
-		}
-
-	fb = (uint16_t *)uncached(info->start[0]);
-
-	dcache_flush_unlocked();
-
-	for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
-		printf("Erasing sector %3d...", i);
-
-		sb = (uint16_t *)uncached(info->start[i]);
-
-		flags = disable_interrupts();
-
-		start_time = get_timer(0);
-
-		/* Unlock sector */
-		writew(0xaa, fb + 0x555);
-		writew(0x70, sb);
-
-		/* Erase sector */
-		writew(0xaa, fb + 0x555);
-		writew(0x55, fb + 0xaaa);
-		writew(0x80, fb + 0x555);
-		writew(0xaa, fb + 0x555);
-		writew(0x55, fb + 0xaaa);
-		writew(0x30, sb);
-
-		/* Wait for completion */
-		ret = ERR_OK;
-		do {
-			/* TODO: Timeout */
-			status = readw(sb);
-		} while ((status != 0xffff) && !(status & 0x28));
-
-		writew(0xf0, fb);
-
-		/*
-		 * Make sure the command actually makes it to the bus
-		 * before we re-enable interrupts.
-		 */
-		readw(fb);
-
-		if (flags)
-			enable_interrupts();
-
-		if (status != 0xffff) {
-			printf("Flash erase error at address 0x%p: 0x%02x\n",
-			       sb, status);
-			ret = ERR_PROG_ERROR;
-			break;
-		}
-	}
-
-	if (ctrlc())
-		printf("User interrupt!\n");
-
-	return ERR_OK;
-}
-
-int __flashprog write_buff(flash_info_t *info, uchar *src,
-			   ulong addr, ulong count)
-{
-	unsigned long flags;
-	uint16_t *base, *p, *s, *end;
-	uint16_t word, status;
-	int ret = ERR_OK;
-
-	if (addr < info->start[0]
-	    || (addr + count) > (info->start[0] + info->size)
-	    || (addr + count) < addr) {
-		puts("Error: invalid address range\n");
-		return ERR_INVAL;
-	}
-
-	if (addr & 1 || count & 1 || (unsigned int)src & 1) {
-		puts("Error: misaligned source, destination or count\n");
-		return ERR_ALIGN;
-	}
-
-	base = (uint16_t *)uncached(info->start[0]);
-	end = (uint16_t *)uncached(addr + count);
-
-	flags = disable_interrupts();
-
-	dcache_flush_unlocked();
-	sync_write_buffer();
-
-	for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
-	     p < end && !ctrlc(); p++, s++) {
-		word = *s;
-
-		writew(0xaa, base + 0x555);
-		writew(0x55, base + 0xaaa);
-		writew(0xa0, base + 0x555);
-		writew(word, p);
-
-		sync_write_buffer();
-
-		/* Wait for completion */
-		do {
-			/* TODO: Timeout */
-			status = readw(p);
-		} while ((status != word) && !(status & 0x28));
-
-		writew(0xf0, base);
-		readw(base);
-
-		if (status != word) {
-			printf("Flash write error at address 0x%p: 0x%02x\n",
-			       p, status);
-			ret = ERR_PROG_ERROR;
-			break;
-		}
-	}
-
-	if (flags)
-		enable_interrupts();
-
-	return ret;
-}
-
-#endif /* CONFIG_ATSTK1000_EXT_FLASH */
diff --git a/board/atstk1000/u-boot.lds.S b/board/atstk1000/u-boot.lds.S
deleted file mode 100644
index d46b82c..0000000
--- a/board/atstk1000/u-boot.lds.S
+++ /dev/null
@@ -1,79 +0,0 @@
-/* -*- Fundamental -*-
- *
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <config.h>
-
-OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
-OUTPUT_ARCH(avr32)
-ENTRY(_start)
-
-SECTIONS
-{
-	. = CFG_FLASH_BASE;
-	_text = .;
-	.text : {
-		*(.text)
-		*(.text.*)
-	}
-
-	. = ALIGN(CFG_ICACHE_LINESZ);
-	__flashprog_start = .;
-	.flashprog : {
-		*(.flashprog)
-	}
-	. = ALIGN(CFG_ICACHE_LINESZ);
-	__flashprog_end = .;
-
-	. = ALIGN(8);
-	.rodata : {
-		*(.rodata)
-		*(.rodata.*)
-	}
-	_etext = .;
-
-	__data_lma = ALIGN(8);
-	. = CFG_INTRAM_BASE;
-	_data = .;
-	.data : AT(__data_lma) {
-		*(.data)
-		*(.data.*)
-	}
-
-	. = ALIGN(4);
-	__u_boot_cmd_start = .;
-	__u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data);
-	.u_boot_cmd : AT(__u_boot_cmd_lma) {
-		KEEP(*(.u_boot_cmd))
-	}
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(8);
-	_edata = .;
-	__edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start);
-
-	.bss : AT(__edata_lma) {
-		*(.bss)
-		*(.bss.*)
-	}
-	. = ALIGN(8);
-	_end = .;
-}
-- 
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