From 51efabac487d832632f9797a94ed2ba6fe98e718 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Wed, 30 Nov 2016 10:08:58 -0200 Subject: Revert "ARM: mx6: add MMC2 boot device detection support in SPL" Commit 54e4fcfa3c749a78 ("ARM: mx6: add MMC2 boot device detection support in SPL") prevents UDOO neo board to boot: Trying to boot from MMC2 port 1 MMC Device 1 not found spl: could not find mmc device. error: -19 SPL: failed to boot from all boot devices This reverts commit 54e4fcfa3c749a789192e83740a53234182f4ca3. Signed-off-by: Breno Lima diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c index 325ba26..bdcda7d 100644 --- a/arch/arm/imx-common/spl.c +++ b/arch/arm/imx-common/spl.c @@ -14,9 +14,6 @@ #include #if defined(CONFIG_MX6) -#define MX6_MMC_PORT_MASK GENMASK(12, 11) -#define MX6_MMC_PORT_2 BIT(11) - /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */ u32 spl_boot_device(void) { @@ -58,11 +55,10 @@ u32 spl_boot_device(void) /* SD/eSD: 8.5.3, Table 8-15 */ case 0x4: case 0x5: + return BOOT_DEVICE_MMC1; /* MMC/eMMC: 8.5.3 */ case 0x6: case 0x7: - if ((reg & MX6_MMC_PORT_MASK) == MX6_MMC_PORT_2) - return BOOT_DEVICE_MMC2; return BOOT_DEVICE_MMC1; /* NAND Flash: 8.5.2 */ case 0x8 ... 0xf: -- cgit v0.10.2 From beaf40688ba7303e9db50558b3852c79437eecad Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 Nov 2016 13:41:52 -0800 Subject: toradex: fix USB Download gadget fixup callback Use the proper config option to guard the USB Download Function fixup callback. Signed-off-by: Stefan Agner diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index f1ab794..d418055 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -108,7 +108,7 @@ int show_board_info(void) return 0; } -#ifdef CONFIG_USBDOWNLOAD_GADGET +#ifdef CONFIG_USB_GADGET_DOWNLOAD int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) { unsigned short usb_pid; @@ -118,7 +118,7 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) return 0; } -#endif /* CONFIG_USBDOWNLOAD_GADGET */ +#endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) -- cgit v0.10.2 From 37fa41256bd756f3652e7479b976982092a4f9bc Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 Nov 2016 13:41:53 -0800 Subject: toradex: allow custom fdt board setup in board file The config block support currently uses the ft_board_setup function to patch the device tree with config block information. However, this does not allow to patch the device tree with board specific information. Rename the common setup function to ft_common_board_setup and use the call it from the board files directly. Signed-off-by: Stefan Agner diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 3d83491..827eefd 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -14,6 +14,7 @@ #include #include #include +#include "../common/tdx-common.h" #include "pinmux-config-apalis_t30.h" @@ -39,6 +40,13 @@ int checkboard(void) return 0; } +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + /* * Routine: pinmux_init * Description: Do individual peripheral pinmux configs diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index c64e31e..e1340c3 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -24,6 +24,7 @@ #include #include #include +#include "../common/tdx-common.h" DECLARE_GLOBAL_DATA_PTR; @@ -387,6 +388,13 @@ int checkboard(void) return 0; } +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + #ifdef CONFIG_USB_EHCI_MX7 static iomux_v3_cfg_t const usb_otg2_pads[] = { MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c index 932b900..8e94854 100644 --- a/board/toradex/colibri_pxa270/colibri_pxa270.c +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -18,6 +18,7 @@ #include #include #include +#include "../common/tdx-common.h" DECLARE_GLOBAL_DATA_PTR; @@ -43,6 +44,13 @@ int checkboard(void) return 0; } +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + int dram_init(void) { pxa2xx_dram_init(); diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 01b55be..4d298e6 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -15,6 +15,7 @@ #include #include #include +#include "../common/tdx-common.h" DECLARE_GLOBAL_DATA_PTR; @@ -74,6 +75,13 @@ int checkboard(void) return 0; } +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + #ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 707d07e..b68d3ca 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -14,6 +14,7 @@ #include #include #include "pinmux-config-colibri_t30.h" +#include "../common/tdx-common.h" int arch_misc_init(void) { @@ -31,6 +32,13 @@ int checkboard(void) return 0; } +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + /* * Routine: pinmux_init * Description: Do individual peripheral pinmux configs diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index e65d9c3..86f52c5 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -22,6 +22,7 @@ #include #include #include +#include "../common/tdx-common.h" DECLARE_GLOBAL_DATA_PTR; @@ -528,6 +529,13 @@ int checkboard(void) return 0; } +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + #ifdef CONFIG_USB_EHCI_VF int board_ehci_hcd_init(int port) { diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index d418055..2c6fc40 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -120,8 +120,8 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) } #endif -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_LIBFDT) +int ft_common_board_setup(void *blob, bd_t *bd) { if (tdx_serial) { fdt_setprop(blob, 0, "serial-number", tdx_serial_str, @@ -158,11 +158,9 @@ u32 get_board_serial(void) } #endif /* CONFIG_SERIAL_TAG */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) +int ft_common_board_setup(void *blob, bd_t *bd) { return 0; } -#endif #endif /* CONFIG_TDX_CFG_BLOCK */ diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h index f308ebd..f8d78f0 100644 --- a/board/toradex/common/tdx-common.h +++ b/board/toradex/common/tdx-common.h @@ -10,4 +10,6 @@ #define TORADEX_USB_PRODUCT_NUM_OFFSET 0x4000 #define TDX_USB_VID 0x1B67 +int ft_common_board_setup(void *blob, bd_t *bd); + #endif /* _TDX_COMMON_H */ -- cgit v0.10.2 From 6119b0f764eb8b68d6148d4c017cbd343408c2d8 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 Nov 2016 13:41:54 -0800 Subject: colibri_vf: use device-tree for MTD partitions Use device-tree fixup to communicate the MTD partitions to the kernel. U-Boot's mtdparts environment variable will be used as partition source for the device-tree based partition table too. Signed-off-by: Stefan Agner diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 86f52c5..0f8b440 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -15,8 +15,11 @@ #include #include #include +#include #include +#include #include +#include #include #include #include @@ -532,6 +535,16 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + static struct node_info nodes[] = { + { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + }; + + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + return ft_common_board_setup(blob, bd); } #endif -- cgit v0.10.2 From 9e73c1b7d11611d51f0026d375731f0316dd26e8 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 Nov 2016 13:41:55 -0800 Subject: colibri_vf: cleanup USB clock initialization Use the same preprocessor define to enable clocks as we use to enable the driver. Make sure that the necessary PLL's are on (they get enabled by boot ROM by default, so this is more for completness). Signed-off-by: Stefan Agner diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 0f8b440..15f263c 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -368,12 +368,18 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, CCM_CCGR10_NFC_CTRL_MASK); -#ifdef CONFIG_CI_UDC +#ifdef CONFIG_USB_EHCI_VF setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK); -#endif - -#ifdef CONFIG_USB_EHCI setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK); + + clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS | + ANADIG_PLL3_CTRL_POWERDOWN | + ANADIG_PLL3_CTRL_DIV_SELECT, + ANADIG_PLL3_CTRL_ENABLE); + clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS | + ANADIG_PLL7_CTRL_POWERDOWN | + ANADIG_PLL7_CTRL_DIV_SELECT, + ANADIG_PLL7_CTRL_ENABLE); #endif clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | -- cgit v0.10.2 From 0eba4c41ca18f8f009126dcacc647927accaa63d Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 Nov 2016 13:41:56 -0800 Subject: colibri_vf: use same NAND clock as Linux uses Currently a divider of 6 has been used, leading to following NAND Flash Controller (NFC) clocks: VF61: 27.7 MHz (166.7MHz bus clock) VF50: 22 MHz (132MHz bus clock) The NAND Flash Memory used on VF50 allows to use clock speed of up to 33MHz, while the Flash Memory of VF61 allows 50MHz. We can use the same divider of 4 on both modules to configure the maximal possible clock speeds: VF61: 41.7 MHz VF50: 33 MHz Signed-off-by: Stefan Agner diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 15f263c..7b74eb7 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -428,7 +428,7 @@ static void clock_init(void) CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | CCM_CSCDR2_NFC_EN); clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, - CCM_CSCDR3_NFC_PRE_DIV(5)); + CCM_CSCDR3_NFC_PRE_DIV(3)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(2)); } -- cgit v0.10.2 From 19271138fff79419b0c25e3570ed58046dba1780 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 Nov 2016 13:41:57 -0800 Subject: ARM: dts: vf: Fix warning about missing reg property Add proper reg values for the two AIPS bus nodes. This avoids this two warnings: Node /soc/aips-bus@40000000 has a unit name, but no reg property Node /soc/aips-bus@40080000 has a unit name, but no reg property Signed-off-by: Stefan Agner diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi index 000aff2..477d8de 100644 --- a/arch/arm/dts/vf.dtsi +++ b/arch/arm/dts/vf.dtsi @@ -35,6 +35,7 @@ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; + reg = <0x40000000 0x00070000>; ranges; uart0: serial@40027000 { @@ -130,6 +131,7 @@ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; + reg = <0x40080000 0x0007f000>; ranges; uart4: serial@400a9000 { -- cgit v0.10.2 From 592f4aed6db765172e21f228800b49f9a27ff201 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 30 Nov 2016 19:43:08 +0100 Subject: arm: imx: initial support for apalis imx6 This adds board support for the Toradex module family Apalis iMX6. The familiy consists of a module with i.MX6 Dual, i.MX6 Quad with commercial and industrial temperature range. Signed-off-by: Max Krummenacher diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 8c96ba3..279a0ba 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -51,6 +51,13 @@ config TARGET_ADVANTECH_DMS_BA16 bool "Advantech dms-ba16" select MX6Q +config TARGET_APALIS_IMX6 + bool "Toradex Apalis iMX6 board" + select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_THERMAL + config TARGET_ARISTAINETOS bool "aristainetos" @@ -271,6 +278,7 @@ source "board/solidrun/mx6cuboxi/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" +source "board/toradex/apalis_imx6/Kconfig" source "board/udoo/Kconfig" source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" diff --git a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg new file mode 100644 index 0000000..5cfda26 --- /dev/null +++ b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014-2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7954 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09555050 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x432A0338 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03260324 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43340344 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x031E027C + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37 + +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4336453F + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg new file mode 100644 index 0000000..3707910 --- /dev/null +++ b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014-2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E78f5 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xff328f64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x02888032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03300338 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03240324 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x03440350 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x032C0308 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46 + +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x403E463E +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/apalis_imx6/Kconfig b/board/toradex/apalis_imx6/Kconfig new file mode 100644 index 0000000..14f8c10 --- /dev/null +++ b/board/toradex/apalis_imx6/Kconfig @@ -0,0 +1,55 @@ +if TARGET_APALIS_IMX6 + +config SYS_BOARD + default "apalis_imx6" + +config SYS_CONFIG_NAME + default "apalis_imx6" + +config SYS_CPU + default "armv7" + +config SYS_SOC + default "mx6" + +config SYS_VENDOR + default "toradex" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CMD_IMX_MFGR + bool "Enable factory testing commands for Toradex iMX 6 modules" + help + This adds the commands + pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 + If executed on already fused modules it doesn't change any fuse setting. + default y + +config TDX_APALIS_IMX6_V1_0 + bool "Apalis iMX6 V1.0 HW" + help + Apalis iMX6 V1.0 HW has a different pinout for the UART. + The UARTs must be used in DCE mode, RTS/CTS are swapped and + thus unusable on standard carrier boards. + This option configures DCE mode unconditionally. Whithout this + option the config block stating V1.0 HW selects DCE mode, + otherwise the UARTs are configuered in DTE mode. + default n + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS new file mode 100644 index 0000000..2c70ab4 --- /dev/null +++ b/board/toradex/apalis_imx6/MAINTAINERS @@ -0,0 +1,9 @@ +Apalis iMX6 +M: Max Krummenacher +W: http://developer.toradex.com/software/linux/linux-software +S: Maintained +F: board/toradex/apalis_imx6/ +F: include/configs/apalis_imx6.h +F: configs/apalis_imx6_defconfig +F: configs/apalis_imx6_nospl_com_defconfig +F: configs/apalis_imx6_nospl_it_defconfig diff --git a/board/toradex/apalis_imx6/Makefile b/board/toradex/apalis_imx6/Makefile new file mode 100644 index 0000000..128f179 --- /dev/null +++ b/board/toradex/apalis_imx6/Makefile @@ -0,0 +1,5 @@ +# Copyright (c) 2012-2014 Toradex, Inc. +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := apalis_imx6.o do_fuse.o +obj-$(CONFIG_TDX_CMD_IMX_MFGR) += pf0100.o diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c new file mode 100644 index 0000000..09bebeb --- /dev/null +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -0,0 +1,1292 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013, Boundary Devices + * Copyright (C) 2014-2016, Toradex AG + * copied from nitrogen6x + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tdx-cfg-block.h" +#ifdef CONFIG_TDX_CMD_IMX_MFGR +#include "pf0100.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define NO_PULLUP ( \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +#define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED) + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + /* use the DDR controllers configured size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + (ulong)imx_ddr_size()); + + return 0; +} + +/* Apalis UART1 */ +iomux_v3_cfg_t const uart1_pads_dce[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; +iomux_v3_cfg_t const uart1_pads_dte[] = { + MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* Apalis I2C1 */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +/* Apalis local, PMIC, SGTL5000, STMPE811 */ +struct i2c_pads_info i2c_pad_info_loc = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* Apalis I2C3 / CAM */ +struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +/* Apalis I2C2 / DDC */ +struct i2c_pads_info i2c_pad_info_ddc = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, + .gp = IMX_GPIO_NR(3, 16) + } +}; + +/* Apalis MMC1 */ +iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +# define GPIO_MMC_CD IMX_GPIO_NR(4, 20) +}; + +/* Apalis SD1 */ +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +# define GPIO_SD_CD IMX_GPIO_NR(6, 14) +}; + +/* eMMC */ +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), +}; + +int mx6_rgmii_rework(struct phy_device *phydev) +{ + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); + return 0; +} + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* KSZ9031 PHY Reset */ + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), +# define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25) +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + +static int reset_enet_phy(struct mii_dev *bus) +{ + /* Reset KSZ9031 PHY */ + gpio_direction_output(GPIO_ENET_PHY_RESET, 0); + mdelay(10); + gpio_set_value(GPIO_ENET_PHY_RESET, 1); + + return 0; +} + +/* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */ +iomux_v3_cfg_t const gpio_pads[] = { + /* Apalis GPIO1 - GPIO8 */ + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN), + MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), +}; + +static void setup_iomux_gpio(void) +{ + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); +} + +iomux_v3_cfg_t const usb_pads[] = { + /* USBH_EN */ + MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +# define GPIO_USBH_EN IMX_GPIO_NR(1, 0) + /* USB_VBUS_DET */ + MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), +# define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28) + /* USBO1_ID */ + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), + /* USBO1_EN */ + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +# define GPIO_USBO_EN IMX_GPIO_NR(3, 22) +}; + +/* + * UARTs are used in DTE mode, switch the mode on all UARTs before + * any pinmuxing connects a (DCE) output to a transceiver output. + */ +#define UFCR 0x90 /* FIFO Control Register */ +#define UFCR_DCEDTE (1<<6) /* DCE=0 */ + +static void setup_dtemode_uart(void) +{ + setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); + setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); + setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE); + setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE); +} +static void setup_dcemode_uart(void) +{ + clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); + clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); + clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE); + clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE); +} + +static void setup_iomux_dte_uart(void) +{ + setup_dtemode_uart(); + imx_iomux_v3_setup_multiple_pads(uart1_pads_dte, + ARRAY_SIZE(uart1_pads_dte)); +} + +static void setup_iomux_dce_uart(void) +{ + setup_dcemode_uart(); + imx_iomux_v3_setup_multiple_pads(uart1_pads_dce, + ARRAY_SIZE(uart1_pads_dce)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + /* control OTG power */ + gpio_direction_output(GPIO_USBO_EN, on); + mdelay(100); + break; + case 1: + /* Control MXM USBH */ + gpio_direction_output(GPIO_USBH_EN, on); + mdelay(2); + /* Control onboard USB Hub VBUS */ + gpio_direction_output(GPIO_USB_VBUS_DET, on); + mdelay(100); + break; + default: + break; + } + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +/* use the following sequence: eMMC, MMC, SD */ +struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC3_BASE_ADDR}, + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = true; /* default: assume inserted */ + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + gpio_direction_input(GPIO_MMC_CD); + ret = !gpio_get_value(GPIO_MMC_CD); + break; + case USDHC2_BASE_ADDR: + gpio_direction_input(GPIO_SD_CD); + ret = !gpio_get_value(GPIO_SD_CD); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + s32 status = 0; + u32 index = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + usdhc_cfg[0].max_bus_width = 8; + usdhc_cfg[1].max_bus_width = 8; + usdhc_cfg[2].max_bus_width = 4; + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +#else + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + default: + puts("MMC boot device not available"); + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + bus->reset = reset_enet_phy; + /* scan PHY 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + free(bus); + puts("no PHY found\n"); + return 0; + } + printf("using PHY at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + +static iomux_v3_cfg_t const pwr_intb_pads[] = { + /* + * the bootrom sets the iomux to vselect, potentially connecting + * two outputs. Set this back to GPIO + */ + MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +#if defined(CONFIG_VIDEO_IPUV3) + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight on RGB connector: J15 */ + MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13) + /* additional CPU pin on BKL_PWM, keep in tristate */ + MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE), + /* Backlight PWM, used as GPIO in U-Boot */ + MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10) + /* buffer output enable 0: buffer enabled */ + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), +#define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2) + /* PSAVE# integrated VDAC */ + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31) +}; + +static iomux_v3_cfg_t const rgb_pads[] = { + MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB), +}; + +static iomux_v3_cfg_t const vga_pads[] = { +#ifdef FOR_DL_SOLO + /* DualLite/Solo doesn't have IPU2 */ + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, +#else + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03, + MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU2_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU2_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU2_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15, +#endif +}; + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return (0 == i2c_set_bus_num(dev->bus)) && + (0 == i2c_probe(dev->addr)); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); + gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); + gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0); +} + +static void enable_rgb(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + rgb_pads, + ARRAY_SIZE(rgb_pads)); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); + gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); + gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0); +} + +static int detect_default(struct display_info_t const *dev) +{ + (void) dev; + return 1; +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .di = 1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_default, + .enable = enable_rgb, + .mode = { + .name = "vga-rgb", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 33000, + .left_margin = 48, + .right_margin = 16, + .upper_margin = 31, + .lower_margin = 11, + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .di = 1, + .pixfmt = IPU_PIX_FMT_RGB24, + .enable = enable_rgb, + .mode = { + .name = "wvga-rgb", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 25000, + .left_margin = 40, + .right_margin = 88, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 128, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "wsvga-lvds", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK + |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <gpr[3]); + + /* backlight unconditionally on for now */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + /* use 0 for EDT 7", use 1 for LG fullHD panel */ + gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); + gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); +} +#endif /* defined(CONFIG_VIDEO_IPUV3) */ + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(pwr_intb_pads, + ARRAY_SIZE(pwr_intb_pads)); +#ifndef CONFIG_TDX_APALIS_IMX6_V1_0 + setup_iomux_dte_uart(); +#else + setup_iomux_dce_uart(); +#endif + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); + +#ifdef CONFIG_TDX_CMD_IMX_MFGR + (void) pmic_init(); +#endif + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + setup_iomux_gpio(); + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#if defined(CONFIG_REVISION_TAG) && \ + defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) + char env_str[256]; + u32 rev; + + rev = get_board_rev(); + snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); + setenv("board_rev", env_str); + +#ifndef CONFIG_TDX_APALIS_IMX6_V1_0 + if ((rev & 0xfff0) == 0x0100) { + char *fdt_env; + + /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */ + setup_iomux_dce_uart(); + + /* if using the default device tree, use version for V1.0 HW */ + fdt_env = getenv("fdt_file"); + if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) { + setenv("fdt_file", FDT_FILE_V1_0); + printf("patching fdt_file to " FDT_FILE_V1_0 "\n"); +#ifndef CONFIG_ENV_IS_NOWHERE + saveenv(); +#endif + } + } +#endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */ +#endif /* CONFIG_REVISION_TAG */ + + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP) +int ft_system_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int checkboard(void) +{ + char it[] = " IT"; + int minc, maxc; + + switch (get_cpu_temp_grade(&minc, &maxc)) { + case TEMP_AUTOMOTIVE: + case TEMP_INDUSTRIAL: + break; + case TEMP_EXTCOMMERCIAL: + default: + it[0] = 0; + }; + printf("Model: Toradex Apalis iMX6 %s %s%s\n", + is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad", + (gd->ram_size == 0x80000000) ? "2GB" : + (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it); + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4-bit bus width */ + {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +/* TODO, use external pmic, for now always ldo_enable */ +void ldo_mode_set(int ldo_bypass) +{ + return; +} +#endif + +#ifdef CONFIG_SPL_BUILD +#include +#include +#include "asm/arch/mx6q-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +static int mx6_com_dcd_table[] = { +/* ddr-setup.cfg */ +MX6_IOM_DRAM_SDQS0, 0x00000030, +MX6_IOM_DRAM_SDQS1, 0x00000030, +MX6_IOM_DRAM_SDQS2, 0x00000030, +MX6_IOM_DRAM_SDQS3, 0x00000030, +MX6_IOM_DRAM_SDQS4, 0x00000030, +MX6_IOM_DRAM_SDQS5, 0x00000030, +MX6_IOM_DRAM_SDQS6, 0x00000030, +MX6_IOM_DRAM_SDQS7, 0x00000030, + +MX6_IOM_GRP_B0DS, 0x00000030, +MX6_IOM_GRP_B1DS, 0x00000030, +MX6_IOM_GRP_B2DS, 0x00000030, +MX6_IOM_GRP_B3DS, 0x00000030, +MX6_IOM_GRP_B4DS, 0x00000030, +MX6_IOM_GRP_B5DS, 0x00000030, +MX6_IOM_GRP_B6DS, 0x00000030, +MX6_IOM_GRP_B7DS, 0x00000030, +MX6_IOM_GRP_ADDDS, 0x00000030, +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +MX6_IOM_GRP_CTLDS, 0x00000030, + +MX6_IOM_DRAM_DQM0, 0x00020030, +MX6_IOM_DRAM_DQM1, 0x00020030, +MX6_IOM_DRAM_DQM2, 0x00020030, +MX6_IOM_DRAM_DQM3, 0x00020030, +MX6_IOM_DRAM_DQM4, 0x00020030, +MX6_IOM_DRAM_DQM5, 0x00020030, +MX6_IOM_DRAM_DQM6, 0x00020030, +MX6_IOM_DRAM_DQM7, 0x00020030, + +MX6_IOM_DRAM_CAS, 0x00020030, +MX6_IOM_DRAM_RAS, 0x00020030, +MX6_IOM_DRAM_SDCLK_0, 0x00020030, +MX6_IOM_DRAM_SDCLK_1, 0x00020030, + +MX6_IOM_DRAM_RESET, 0x00020030, +MX6_IOM_DRAM_SDCKE0, 0x00003000, +MX6_IOM_DRAM_SDCKE1, 0x00003000, + +MX6_IOM_DRAM_SDODT0, 0x00003030, +MX6_IOM_DRAM_SDODT1, 0x00003030, + +/* (differential input) */ +MX6_IOM_DDRMODE_CTL, 0x00020000, +/* (differential input) */ +MX6_IOM_GRP_DDRMODE, 0x00020000, +/* disable ddr pullups */ +MX6_IOM_GRP_DDRPKE, 0x00000000, +MX6_IOM_DRAM_SDBA2, 0x00000000, +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +MX6_IOM_GRP_DDR_TYPE, 0x000C0000, + +/* Read data DQ Byte0-3 delay */ +MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +MX6_MMDC_P0_MDMISC, 0x00081740, + +/* + * MDSCR con_req + */ +MX6_MMDC_P0_MDSCR, 0x00008000, + +/* 1066mhz_4x128mx16.cfg */ + +MX6_MMDC_P0_MDPDC, 0x00020036, +MX6_MMDC_P0_MDCFG0, 0x555A7954, +MX6_MMDC_P0_MDCFG1, 0xDB328F64, +MX6_MMDC_P0_MDCFG2, 0x01FF00DB, +MX6_MMDC_P0_MDRWD, 0x000026D2, +MX6_MMDC_P0_MDOR, 0x005A1023, +MX6_MMDC_P0_MDOTC, 0x09555050, +MX6_MMDC_P0_MDPDC, 0x00025576, +MX6_MMDC_P0_MDASP, 0x00000027, +MX6_MMDC_P0_MDCTL, 0x831A0000, +MX6_MMDC_P0_MDSCR, 0x04088032, +MX6_MMDC_P0_MDSCR, 0x00008033, +MX6_MMDC_P0_MDSCR, 0x00428031, +MX6_MMDC_P0_MDSCR, 0x19308030, +MX6_MMDC_P0_MDSCR, 0x04008040, +MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, +MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, +MX6_MMDC_P0_MDREF, 0x00005800, +MX6_MMDC_P0_MPODTCTRL, 0x00000000, +MX6_MMDC_P1_MPODTCTRL, 0x00000000, + +MX6_MMDC_P0_MPDGCTRL0, 0x432A0338, +MX6_MMDC_P0_MPDGCTRL1, 0x03260324, +MX6_MMDC_P1_MPDGCTRL0, 0x43340344, +MX6_MMDC_P1_MPDGCTRL1, 0x031E027C, + +MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E, +MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37, + +MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C, +MX6_MMDC_P1_MPWRDLCTL, 0x4336453F, + +MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E, +MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B, +MX6_MMDC_P1_MPWLDECTRL0, 0x00060015, +MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E, + +MX6_MMDC_P0_MPMUR0, 0x00000800, +MX6_MMDC_P1_MPMUR0, 0x00000800, +MX6_MMDC_P0_MDSCR, 0x00000000, +MX6_MMDC_P0_MAPSR, 0x00011006, +}; + +static int mx6_it_dcd_table[] = { +/* ddr-setup.cfg */ +MX6_IOM_DRAM_SDQS0, 0x00000030, +MX6_IOM_DRAM_SDQS1, 0x00000030, +MX6_IOM_DRAM_SDQS2, 0x00000030, +MX6_IOM_DRAM_SDQS3, 0x00000030, +MX6_IOM_DRAM_SDQS4, 0x00000030, +MX6_IOM_DRAM_SDQS5, 0x00000030, +MX6_IOM_DRAM_SDQS6, 0x00000030, +MX6_IOM_DRAM_SDQS7, 0x00000030, + +MX6_IOM_GRP_B0DS, 0x00000030, +MX6_IOM_GRP_B1DS, 0x00000030, +MX6_IOM_GRP_B2DS, 0x00000030, +MX6_IOM_GRP_B3DS, 0x00000030, +MX6_IOM_GRP_B4DS, 0x00000030, +MX6_IOM_GRP_B5DS, 0x00000030, +MX6_IOM_GRP_B6DS, 0x00000030, +MX6_IOM_GRP_B7DS, 0x00000030, +MX6_IOM_GRP_ADDDS, 0x00000030, +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +MX6_IOM_GRP_CTLDS, 0x00000030, + +MX6_IOM_DRAM_DQM0, 0x00020030, +MX6_IOM_DRAM_DQM1, 0x00020030, +MX6_IOM_DRAM_DQM2, 0x00020030, +MX6_IOM_DRAM_DQM3, 0x00020030, +MX6_IOM_DRAM_DQM4, 0x00020030, +MX6_IOM_DRAM_DQM5, 0x00020030, +MX6_IOM_DRAM_DQM6, 0x00020030, +MX6_IOM_DRAM_DQM7, 0x00020030, + +MX6_IOM_DRAM_CAS, 0x00020030, +MX6_IOM_DRAM_RAS, 0x00020030, +MX6_IOM_DRAM_SDCLK_0, 0x00020030, +MX6_IOM_DRAM_SDCLK_1, 0x00020030, + +MX6_IOM_DRAM_RESET, 0x00020030, +MX6_IOM_DRAM_SDCKE0, 0x00003000, +MX6_IOM_DRAM_SDCKE1, 0x00003000, + +MX6_IOM_DRAM_SDODT0, 0x00003030, +MX6_IOM_DRAM_SDODT1, 0x00003030, + +/* (differential input) */ +MX6_IOM_DDRMODE_CTL, 0x00020000, +/* (differential input) */ +MX6_IOM_GRP_DDRMODE, 0x00020000, +/* disable ddr pullups */ +MX6_IOM_GRP_DDRPKE, 0x00000000, +MX6_IOM_DRAM_SDBA2, 0x00000000, +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +MX6_IOM_GRP_DDR_TYPE, 0x000C0000, + +/* Read data DQ Byte0-3 delay */ +MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +MX6_MMDC_P0_MDMISC, 0x00081740, + +/* + * MDSCR con_req + */ +MX6_MMDC_P0_MDSCR, 0x00008000, + +/* 1066mhz_4x256mx16.cfg */ + +MX6_MMDC_P0_MDPDC, 0x00020036, +MX6_MMDC_P0_MDCFG0, 0x898E78f5, +MX6_MMDC_P0_MDCFG1, 0xff328f64, +MX6_MMDC_P0_MDCFG2, 0x01FF00DB, +MX6_MMDC_P0_MDRWD, 0x000026D2, +MX6_MMDC_P0_MDOR, 0x008E1023, +MX6_MMDC_P0_MDOTC, 0x09444040, +MX6_MMDC_P0_MDPDC, 0x00025576, +MX6_MMDC_P0_MDASP, 0x00000047, +MX6_MMDC_P0_MDCTL, 0x841A0000, +MX6_MMDC_P0_MDSCR, 0x02888032, +MX6_MMDC_P0_MDSCR, 0x00008033, +MX6_MMDC_P0_MDSCR, 0x00048031, +MX6_MMDC_P0_MDSCR, 0x19408030, +MX6_MMDC_P0_MDSCR, 0x04008040, +MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, +MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, +MX6_MMDC_P0_MDREF, 0x00007800, +MX6_MMDC_P0_MPODTCTRL, 0x00022227, +MX6_MMDC_P1_MPODTCTRL, 0x00022227, + +MX6_MMDC_P0_MPDGCTRL0, 0x03300338, +MX6_MMDC_P0_MPDGCTRL1, 0x03240324, +MX6_MMDC_P1_MPDGCTRL0, 0x03440350, +MX6_MMDC_P1_MPDGCTRL1, 0x032C0308, + +MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E, +MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46, + +MX6_MMDC_P0_MPWRDLCTL, 0x403E463E, +MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46, + +MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E, +MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B, +MX6_MMDC_P1_MPWLDECTRL0, 0x00060015, +MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E, + +MX6_MMDC_P0_MPMUR0, 0x00000800, +MX6_MMDC_P1_MPMUR0, 0x00000800, +MX6_MMDC_P0_MDSCR, 0x00000000, +MX6_MMDC_P0_MAPSR, 0x00011006, +}; + + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFFFF3, &ccm->CCGR2); + writel(0x3FF0300F, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000F3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ + writel(0x000000FB, &ccm->ccosr); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +static void ddr_init(int *table, int size) +{ + int i; + + for (i = 0; i < size / 2 ; i++) + writel(table[2 * i + 1], table[2 * i]); +} + +static void spl_dram_init(void) +{ + int minc, maxc; + + switch (get_cpu_temp_grade(&minc, &maxc)) { + case TEMP_COMMERCIAL: + case TEMP_EXTCOMMERCIAL: + puts("Commercial temperature grade DDR3 timings.\n"); + ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table)); + break; + case TEMP_INDUSTRIAL: + case TEMP_AUTOMOTIVE: + default: + puts("Industrial temperature grade DDR3 timings.\n"); + ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table)); + break; + }; + udelay(100); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + +#ifndef CONFIG_TDX_APALIS_IMX6_V1_0 + /* Make sure we use dte mode */ + setup_dtemode_uart(); +#endif + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} + +#endif + +static struct mxc_serial_platdata mxc_serial_plat = { + .reg = (struct mxc_uart *)UART1_BASE, + .use_dte = true, +}; + +U_BOOT_DEVICE(mxc_serial) = { + .name = "serial_mxc", + .platdata = &mxc_serial_plat, +}; diff --git a/board/toradex/apalis_imx6/apalis_imx6q.cfg b/board/toradex/apalis_imx6/apalis_imx6q.cfg new file mode 100644 index 0000000..b775010 --- /dev/null +++ b/board/toradex/apalis_imx6/apalis_imx6q.cfg @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#if CONFIG_DDR_MB == 2048 +#include "1066mhz_4x256mx16.cfg" +#else +#include "1066mhz_4x128mx16.cfg" +#endif +#include "clocks.cfg" diff --git a/board/toradex/apalis_imx6/clocks.cfg b/board/toradex/apalis_imx6/clocks.cfg new file mode 100644 index 0000000..be96094 --- /dev/null +++ b/board/toradex/apalis_imx6/clocks.cfg @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/toradex/apalis_imx6/ddr-setup.cfg b/board/toradex/apalis_imx6/ddr-setup.cfg new file mode 100644 index 0000000..de7cdd6 --- /dev/null +++ b/board/toradex/apalis_imx6/ddr-setup.cfg @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +/* + * MDSCR con_req + */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c new file mode 100644 index 0000000..cff07e9 --- /dev/null +++ b/board/toradex/apalis_imx6/do_fuse.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Helpers for i.MX OTP fusing during module production +*/ + +#include +#ifndef CONFIG_SPL_BUILD +#include +#include + +static int mfgr_fuse(void) +{ + unsigned val, val6; + + fuse_sense(0, 5, &val); + printf("Fuse 0, 5: %8x\n", val); + fuse_sense(0, 6, &val6); + printf("Fuse 0, 6: %8x\n", val6); + fuse_sense(4, 3, &val); + printf("Fuse 4, 3: %8x\n", val); + fuse_sense(4, 2, &val); + printf("Fuse 4, 2: %8x\n", val); + if (val6 & 0x10) { + puts("BT_FUSE_SEL already fused, will do nothing\n"); + return CMD_RET_FAILURE; + } + /* boot cfg */ + fuse_prog(0, 5, 0x00005072); + /* BT_FUSE_SEL */ + fuse_prog(0, 6, 0x00000010); + return CMD_RET_SUCCESS; +} + +int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ret; + puts("Fusing...\n"); + ret = mfgr_fuse(); + if (ret == CMD_RET_SUCCESS) + puts("done.\n"); + else + puts("failed.\n"); + return ret; +} + +int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned val; + int ret; + int confirmed = argc >= 1 && !strcmp(argv[1], "-y"); + + /* can be used in scripts for command availability check */ + if (argc >= 1 && !strcmp(argv[1], "-n")) + return CMD_RET_SUCCESS; + + /* boot cfg */ + fuse_sense(0, 5, &val); + printf("Fuse 0, 5: %8x\n", val); + if (val & 0x10) { + puts("Fast boot mode already fused, no need to fuse\n"); + return CMD_RET_SUCCESS; + } + if (!confirmed) { + puts("Warning: Programming fuses is an irreversible operation!\n" + " Updating to fast boot mode prevents easy\n" + " downgrading to previous BSP versions.\n" + "\nReally perform this fuse programming? \n"); + if (!confirm_yesno()) + return CMD_RET_FAILURE; + } + puts("Fusing fast boot mode...\n"); + ret = fuse_prog(0, 5, 0x00005072); + if (ret == CMD_RET_SUCCESS) + puts("done.\n"); + else + puts("failed.\n"); + return ret; +} + +U_BOOT_CMD( + mfgr_fuse, 1, 0, do_mfgr_fuse, + "OTP fusing during module production", + "" +); + +U_BOOT_CMD( + updt_fuse, 2, 0, do_updt_fuse, + "OTP fusing during module update", + "updt_fuse [-n] [-y] - boot cfg fast boot mode fusing" +); +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c new file mode 100644 index 0000000..0b42438 --- /dev/null +++ b/board/toradex/apalis_imx6/pf0100.c @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Helpers for Freescale PMIC PF0100 +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include "pf0100_otp.inc" +#include "pf0100.h" + +/* define for PMIC register dump */ +/*#define DEBUG */ + +/* use Apalis GPIO1 to switch on VPGM, ON: 1 */ +static iomux_v3_cfg_t const pmic_prog_pads[] = { + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 4) +}; + +unsigned pmic_init(void) +{ + unsigned programmed = 0; + uchar bus = 1; + uchar devid, revid, val; + + puts("PMIC: "); + if (!((0 == i2c_set_bus_num(bus)) && + (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { + puts("i2c bus failed\n"); + return 0; + } + /* get device ident */ + if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) { + puts("i2c pmic devid read failed\n"); + return 0; + } + if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) { + puts("i2c pmic revid read failed\n"); + return 0; + } + printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid); + +#ifdef DEBUG + { + unsigned i, j; + + for (i = 0; i < 16; i++) + printf("\t%x", i); + for (j = 0; j < 0x80; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\nEXT Page 1"); + + val = PFUZE100_PAGE_REGISTER_PAGE1; + if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, + &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + + for (j = 0x80; j < 0x100; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\nEXT Page 2"); + + val = PFUZE100_PAGE_REGISTER_PAGE2; + if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, + &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + + for (j = 0x80; j < 0x100; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\n"); + } +#endif + /* get device programmed state */ + val = PFUZE100_PAGE_REGISTER_PAGE1; + if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return 0; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return programmed; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return programmed; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + switch (programmed) { + case 0: + printf("PMIC: not programmed\n"); + break; + case 3: + printf("PMIC: programmed\n"); + break; + default: + printf("PMIC: undefined programming state\n"); + break; + } + + /* The following is needed during production */ + if (programmed != 3) { + /* set VGEN1 to 1.2V */ + val = PFUZE100_VGEN1_VAL; + if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1, + &val, 1)) { + puts("i2c write failed\n"); + return programmed; + } + + /* set SWBST to 5.0V */ + val = PFUZE100_SWBST_VAL; + if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1, + &val, 1)) { + puts("i2c write failed\n"); + } + } + return programmed; +} + +int pf0100_prog(void) +{ + unsigned char bus = 1; + unsigned char val; + unsigned int i; + + if (pmic_init() == 3) { + puts("PMIC already programmed, exiting\n"); + return CMD_RET_FAILURE; + } + /* set up gpio to manipulate vprog, initially off */ + imx_iomux_v3_setup_multiple_pads(pmic_prog_pads, + ARRAY_SIZE(pmic_prog_pads)); + gpio_direction_output(PMIC_PROG_VOLTAGE, 0); + + if (!((0 == i2c_set_bus_num(bus)) && + (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { + puts("i2c bus failed\n"); + return CMD_RET_FAILURE; + } + + for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) { + switch (pmic_otp_prog[i].cmd) { + case pmic_i2c: + val = (unsigned char) (pmic_otp_prog[i].value & 0xff); + if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg, + 1, &val, 1)) { + printf("i2c write failed, reg 0x%2x, value 0x%2x\n", + pmic_otp_prog[i].reg, val); + return CMD_RET_FAILURE; + } + break; + case pmic_delay: + udelay(pmic_otp_prog[i].value * 1000); + break; + case pmic_vpgm: + gpio_direction_output(PMIC_PROG_VOLTAGE, + pmic_otp_prog[i].value); + break; + case pmic_pwr: + /* TODO */ + break; + } + } + return CMD_RET_SUCCESS; +} + +int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ret; + puts("Programming PMIC OTP..."); + ret = pf0100_prog(); + if (ret == CMD_RET_SUCCESS) + puts("done.\n"); + else + puts("failed.\n"); + return ret; +} + +U_BOOT_CMD( + pf0100_otp_prog, 1, 0, do_pf0100_prog, + "Program the OTP fuses on the PMIC PF0100", + "" +); diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h new file mode 100644 index 0000000..c84cab8 --- /dev/null +++ b/board/toradex/apalis_imx6/pf0100.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Helpers for Freescale PMIC PF0100 +*/ + +#ifndef PF0100_H_ +#define PF0100_H_ + +/* 7-bit I2C bus slave address */ +#define PFUZE100_I2C_ADDR (0x08) +/* Register Addresses */ +#define PFUZE100_DEVICEID (0x0) +#define PFUZE100_REVID (0x3) +#define PFUZE100_SW1AMODE (0x23) +#define PFUZE100_SW1ACON 36 +#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ +#define PFUZE100_SW1ACON_SPEED_M (0x3<<6) +#define PFUZE100_SW1CCON 49 +#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */ +#define PFUZE100_SW1CCON_SPEED_M (0x3<<6) +#define PFUZE100_SW1AVOL 32 +#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0) +#define PFUZE100_SW1CVOL 46 +#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0) +#define PFUZE100_VGEN1CTL (0x6c) +#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */ +#define PFUZE100_SWBSTCTL (0x66) +/* Always ON, Auto Switching Mode, 5.0V */ +#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00) + +/* chooses the extended page (registers 0x80..0xff) */ +#define PFUZE100_PAGE_REGISTER 0x7f +#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0) +#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M) +#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M) + +/* extended page 1 */ +#define PFUZE100_FUSE_POR1 0xe4 +#define PFUZE100_FUSE_POR2 0xe5 +#define PFUZE100_FUSE_POR3 0xe6 +#define PFUZE100_FUSE_POR_M (0x1 << 1) + + +/* output some informational messages, return the number FUSE_POR=1 */ +/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */ +unsigned pmic_init(void); + +/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */ +int pf0100_prog(void); + +#endif /* PF0100_H_ */ diff --git a/board/toradex/apalis_imx6/pf0100_otp.inc b/board/toradex/apalis_imx6/pf0100_otp.inc new file mode 100644 index 0000000..59e0587 --- /dev/null +++ b/board/toradex/apalis_imx6/pf0100_otp.inc @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +// Register Output for PF0100 programmer +// Customer: Toradex AG +// Program: Apalis iMX6 +// Sample marking: +// Date: 12.02.2014 +// Time: 17:16:41 +// Generated from Spreadsheet Revision: P1.8 + +/* sed commands to get from programmer script to struct */ +/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc + sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc + sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */ + +enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr }; +struct pmic_otp_prog_t{ + unsigned char cmd; + unsigned char reg; + unsigned short value; +}; + +struct pmic_otp_prog_t pmic_otp_prog[] = { +{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1 +{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94 +{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95 +{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96 +{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102 +{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103 +{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104 +{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106 +{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108 +{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110 +{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111 +{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112 +{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114 +{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115 +{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116 +{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118 +{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120 +{pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123 +{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126 +{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130 +{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134 +{pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135 +{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138 +{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139 +{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142 +{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143 +{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147 +{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150 +{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151 +{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154 +{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155 +{pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158 + +#if 0 /* TBB mode */ +{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1 +{pmic_delay, 0, 10}, +#else +// Write OTP +{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1 +{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1 +{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1 +{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register +{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register +{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2 +{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register +{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST +//VPGM:DOWN:n +//VPGM:UP:n +{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up +//----------------------------------------------------------------------------------- +// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10) +//----------------------------------------------------------------------------------- +// BANK 1 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN +{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 2 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN +{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 3 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN +{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 4 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN +{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 5 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN +{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 6 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN +{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 7 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN +{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 8 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN +{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 9 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN +{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 10 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN +{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +{pmic_vpgm, 0, 0}, // Turn off 8V SWBST +{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off +{pmic_i2c, 0xD0, 0x00}, // Clear +{pmic_i2c, 0xD1, 0x00}, // Clear +{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data +{pmic_delay, 0, 500}, +{pmic_pwr, 0, 1}, +#endif +}; \ No newline at end of file diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig new file mode 100644 index 0000000..80c69ea --- /dev/null +++ b/configs/apalis_imx6_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_APALIS_IMX6=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_SPL_DMA_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Apalis iMX6 # " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Toradex" +CONFIG_G_DNL_VENDOR_NUM=0x1b67 +CONFIG_G_DNL_PRODUCT_NUM=0x4020 +CONFIG_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig new file mode 100644 index 0000000..4276c6a --- /dev/null +++ b/configs/apalis_imx6_nospl_com_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_APALIS_IMX6=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024" +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Apalis iMX6 # " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Toradex" +CONFIG_G_DNL_VENDOR_NUM=0x1b67 +CONFIG_G_DNL_PRODUCT_NUM=0x4020 +CONFIG_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig new file mode 100644 index 0000000..d246722 --- /dev/null +++ b/configs/apalis_imx6_nospl_it_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_APALIS_IMX6=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048" +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Apalis iMX6 # " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Toradex" +CONFIG_G_DNL_VENDOR_NUM=0x1b67 +CONFIG_G_DNL_PRODUCT_NUM=0x4020 +CONFIG_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h new file mode 100644 index 0000000..80a76a8 --- /dev/null +++ b/include/configs/apalis_imx6.h @@ -0,0 +1,342 @@ +/* + * Copyright 2013-2015 Toradex, Inc. + * + * Configuration settings for the Toradex Apalis iMX6 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#define CONFIG_SYS_THUMB_BUILD +/* These are not provided in SPL and result in a linker error */ +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_USE_ARCH_MEMSET +#endif + +#undef CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ + +#define CONFIG_MACH_TYPE 4886 + +#define CONFIG_SYS_GENERIC_BOARD + +#include +#include + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#define CONFIG_SPL_PAD_TO 0x11000 /* 4k IVT/DCD, 64k SPL */ +#endif + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MISC_INIT_R + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* Make the HW version stuff available in U-Boot env */ +#define CONFIG_VERSION_VARIABLE /* ver environment variable */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* OCOTP Configs */ +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FAT_WRITE +#define CONFIG_DOS_PARTITION + +#ifdef CONFIG_MX6Q +#define CONFIG_CMD_SATA +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +/* Network */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_TFTP_TSIZE + +/* USB Configs */ +/* Host */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL +#endif /* CONFIG_USB_KEYBOARD */ +/* Client */ +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_USBD_HS + +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_G_DNL_MANUFACTURER "Toradex" +/* USB DFU */ +#define CONFIG_DFU_MMC + +/* Miscellaneous commands */ +#define CONFIG_CMD_BMODE +#define CONFIG_MXC_GPIO + +/* Framebuffer and LCD */ +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_CMD_BMP + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FLASH + +#undef CONFIG_IPADDR +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#undef CONFIG_SERVERIP +#define CONFIG_SERVERIP 192.168.10.1 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#ifdef CONFIG_CMD_SATA +#define CONFIG_DRIVE_SATA "sata " +#else +#define CONFIG_DRIVE_SATA +#endif + +#ifdef CONFIG_CMD_MMC +#define CONFIG_DRIVE_MMC "mmc " +#else +#define CONFIG_DRIVE_MMC +#endif + +#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC + +#define DFU_ALT_EMMC_INFO \ + "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "uImage fat 0 1;" \ + "imx6q-colibri-eval-v3.dtb fat 0 1;" \ + "imx6q-colibri-cam-eval-v3.dtb fat 0 1" + +#define EMMC_BOOTCMD \ + "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \ + "rootwait\0" \ + "emmcboot=run setup; " \ + "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ + "${vidargs}; echo Booting from internal eMMC chip...; " \ + "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \ + "${boot_file} && run fdt_fixup && " \ + "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \ + "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x12000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x11000000\0" \ + "ramdisk_addr_r=0x12100000\0" + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ + "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ + "run nfsdtbload; dhcp ${kernel_addr_r} " \ + "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \ + "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ + "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define SD_BOOTCMD \ + "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \ + "rootwait\0" \ + "sdboot=run setup; " \ + "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ + "${vidargs}; echo Booting from SD card; " \ + "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \ + "${boot_file} && run fdt_fixup && " \ + "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \ + "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define USB_BOOTCMD \ + "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \ + "rootwait\0" \ + "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \ + "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ + "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \ + "${boot_file} && run fdt_fixup && " \ + "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \ + "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#ifndef CONFIG_TDX_APALIS_IMX6_V1_0 +#define FDT_FILE "imx6q-apalis-eval.dtb" +#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb" +#else +#define FDT_FILE "imx6q-apalis_v1_0-eval.dtb" +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \ + "run nfsboot ; echo ; echo nfsboot failed ; " \ + "usb start ;" \ + "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ + "boot_file=uImage\0" \ + "console=ttymxc0\0" \ + "defargs=enable_wait_mode=off vmalloc=400M\0" \ + "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ + EMMC_BOOTCMD \ + "fdt_file=" FDT_FILE "\0" \ + "fdt_fixup=;\0" \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + SD_BOOTCMD \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ + "flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \ + "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setup=setenv setupargs fec_mac=${ethaddr} " \ + "consoleblank=0 no_console_suspend=1 console=tty1 " \ + "console=${console},${baudrate}n8\0 " \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "splashpos=m,m\0" \ + "vidargs=mxc_hdmi.only_cea=1 " \ + "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \ + "video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \ + "fbmem=32M\0 " + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 48 + +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC + +#if defined(CONFIG_ENV_IS_IN_MMC) +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ + CONFIG_TDX_CFG_BLOCK_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 +#endif + +#define CONFIG_OF_SYSTEM_SETUP + +#define CONFIG_CMD_TIME + +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_CRC32_VERIFY + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From a02d517b0182f83771565eba1329fb323674ec58 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 30 Nov 2016 19:43:09 +0100 Subject: arm: imx: initial support for colibri imx6 This adds board support for the Toradex module family Colibri iMX6. The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both with a version for commercial and industrial temperature range. Signed-off-by: Max Krummenacher diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 279a0ba..5a8c7bf 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -80,6 +80,13 @@ config TARGET_CM_FX6 select DM_SERIAL select DM_GPIO +config TARGET_COLIBRI_IMX6 + bool "Toradex Colibri iMX6 board" + select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_THERMAL + config TARGET_EMBESTMX6BOARDS bool "embestmx6boards" @@ -279,6 +286,7 @@ source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" +source "board/toradex/colibri_imx6/Kconfig" source "board/udoo/Kconfig" source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg new file mode 100644 index 0000000..660f9d3 --- /dev/null +++ b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +/* DDR3 DATA BUS SIZE: 64BIT */ +/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */ +/* DDR3 DATA BUS SIZE: 32BIT */ +DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 + +/* Write commands to DDR */ +/* Load Mode Registers */ +/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ +/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +/* ZQ calibration */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 + +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 + +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg new file mode 100644 index 0000000..3bd8576 --- /dev/null +++ b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +/* DDR3 DATA BUS SIZE: 64BIT */ +DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 +/* DDR3 DATA BUS SIZE: 32BIT */ +/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */ + +/* Write commands to DDR */ +/* Load Mode Registers */ +/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ +/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +/* ZQ calibration */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 + +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 + +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/colibri_imx6/Kconfig b/board/toradex/colibri_imx6/Kconfig new file mode 100644 index 0000000..d2ad1ce --- /dev/null +++ b/board/toradex/colibri_imx6/Kconfig @@ -0,0 +1,44 @@ +if TARGET_COLIBRI_IMX6 + +config SYS_BOARD + default "colibri_imx6" + +config SYS_CONFIG_NAME + default "colibri_imx6" + +config SYS_CPU + default "armv7" + +config SYS_SOC + default "mx6" + +config SYS_VENDOR + default "toradex" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CMD_IMX_MFGR + bool "Enable factory testing commands for Toradex iMX 6 modules" + help + This adds the commands + pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 + If executed on already fused modules it doesn't change any fuse setting. + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS new file mode 100644 index 0000000..1cc7ef2 --- /dev/null +++ b/board/toradex/colibri_imx6/MAINTAINERS @@ -0,0 +1,8 @@ +Colibri iMX6 +M: Max Krummenacher +W: http://developer.toradex.com/software/linux/linux-software +S: Maintained +F: board/toradex/colibri_imx6/ +F: include/configs/colibri_imx6.h +F: configs/colibri_imx6_defconfig +F: configs/colibri_imx6_nospl_defconfig diff --git a/board/toradex/colibri_imx6/Makefile b/board/toradex/colibri_imx6/Makefile new file mode 100644 index 0000000..c81bc2d --- /dev/null +++ b/board/toradex/colibri_imx6/Makefile @@ -0,0 +1,5 @@ +# Copyright (c) 2012-2014 Toradex, Inc. +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := colibri_imx6.o do_fuse.o +obj-$(CONFIG_TDX_CMD_IMX_MFGR) += pf0100.o diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg new file mode 100644 index 0000000..be96094 --- /dev/null +++ b/board/toradex/colibri_imx6/clocks.cfg @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c new file mode 100644 index 0000000..d070677 --- /dev/null +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -0,0 +1,1130 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013, Boundary Devices + * Copyright (C) 2014-2016, Toradex AG + * copied from nitrogen6x + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tdx-cfg-block.h" +#ifdef CONFIG_TDX_CMD_IMX_MFGR +#include "pf0100.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define NO_PULLUP ( \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + /* use the DDR controllers configured size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + (ulong)imx_ddr_size()); + + return 0; +} + +/* Colibri UARTA */ +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* Colibri I2C */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +/* Colibri local, PMIC, SGTL5000, STMPE811 */ +struct i2c_pads_info i2c_pad_info_loc = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, + .gp = IMX_GPIO_NR(3, 16) + } +}; + +/* Apalis MMC */ +iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +# define GPIO_MMC_CD IMX_GPIO_NR(2, 5) +}; + +/* eMMC */ +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + +/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */ +iomux_v3_cfg_t const gpio_pads[] = { + /* ADDRESS[17:18] [25] used as GPIO */ + MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), + /* ADDRESS[19:24] used as GPIO */ + MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), + /* DATA[16:29] [31] used as GPIO */ + MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), + /* DQM[0:3] used as GPIO */ + MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), + /* RDY used as GPIO */ + MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), + /* ADDRESS[16] DATA[30] used as GPIO */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN), + MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + /* CSI pins used as GPIO */ + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN), + MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), + /* GPIO */ + MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + /* USBH_OC */ + MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP), + /* USBC_ID */ + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), + /* USBC_DET */ + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), +}; + +static void setup_iomux_gpio(void) +{ + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); +} + +iomux_v3_cfg_t const usb_pads[] = { + /* USB_PE */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), +# define GPIO_USBH_EN IMX_GPIO_NR(3, 31) +}; + +/* + * UARTs are used in DTE mode, switch the mode on all UARTs before + * any pinmuxing connects a (DCE) output to a transceiver output. + */ +#define UFCR 0x90 /* FIFO Control Register */ +#define UFCR_DCEDTE (1<<6) /* DCE=0 */ + +static void setup_dtemode_uart(void) +{ + setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); + setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); + setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE); +} + +static void setup_iomux_uart(void) +{ + setup_dtemode_uart(); + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + /* control OTG power */ + /* No special PE for USBC, always on when ID pin signals + host mode */ + break; + case 1: + /* Control MXM USBH */ + /* Set MXM USBH power enable, '0' means on */ + gpio_direction_output(GPIO_USBH_EN, !on); + mdelay(100); + break; + default: + break; + } + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +/* use the following sequence: eMMC, MMC */ +struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC3_BASE_ADDR}, + {USDHC1_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = true; /* default: assume inserted */ + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + gpio_direction_input(GPIO_MMC_CD); + ret = !gpio_get_value(GPIO_MMC_CD); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + s32 status = 0; + u32 index = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + usdhc_cfg[0].max_bus_width = 8; + usdhc_cfg[1].max_bus_width = 4; + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +#else + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + default: + puts("MMC boot device not available"); + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + /* provide the PHY clock from the i.MX 6 */ + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + /* set gpr1[ENET_CLK_SEL] */ + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan PHY 1..7 */ + phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII); + if (!phydev) { + free(bus); + puts("no PHY found\n"); + return 0; + } + phy_reset(phydev); + printf("using PHY at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + +static iomux_v3_cfg_t const pwr_intb_pads[] = { + /* + * the bootrom sets the iomux to vselect, potentially connecting + * two outputs. Set this back to GPIO + */ + MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +#if defined(CONFIG_VIDEO_IPUV3) + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight On */ + MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26) + /* Backlight PWM, used as GPIO in U-Boot */ + MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP), + MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9) +}; + +static iomux_v3_cfg_t const rgb_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB), + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB), +}; + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static void enable_rgb(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + rgb_pads, + ARRAY_SIZE(rgb_pads)); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); + gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); +} + +static int detect_default(struct display_info_t const *dev) +{ + (void) dev; + return 1; +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_default, + .enable = enable_rgb, + .mode = { + .name = "vga-rgb", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 33000, + .left_margin = 48, + .right_margin = 16, + .upper_margin = 31, + .lower_margin = 11, + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .enable = enable_rgb, + .mode = { + .name = "wvga-rgb", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 25000, + .left_margin = 40, + .right_margin = 88, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 128, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK + |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <gpr[3]); + + /* backlight unconditionally on for now */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + /* use 0 for EDT 7", use 1 for LG fullHD panel */ + gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); +} +#endif /* defined(CONFIG_VIDEO_IPUV3) */ + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(pwr_intb_pads, + ARRAY_SIZE(pwr_intb_pads)); + setup_iomux_uart(); + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); + +#ifdef CONFIG_TDX_CMD_IMX_MFGR + (void) pmic_init(); +#endif + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + setup_iomux_gpio(); + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#if defined(CONFIG_REVISION_TAG) && \ + defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) + char env_str[256]; + u32 rev; + + rev = get_board_rev(); + snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); + setenv("board_rev", env_str); +#endif + + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP) +int ft_system_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int checkboard(void) +{ + char it[] = " IT"; + int minc, maxc; + + switch (get_cpu_temp_grade(&minc, &maxc)) { + case TEMP_AUTOMOTIVE: + case TEMP_INDUSTRIAL: + break; + case TEMP_EXTCOMMERCIAL: + default: + it[0] = 0; + }; + printf("Model: Toradex Colibri iMX6 %s %sMB%s\n", + is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo", + (gd->ram_size == 0x20000000) ? "512" : "256", it); + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +/* TODO, use external pmic, for now always ldo_enable */ +void ldo_mode_set(int ldo_bypass) +{ + return; +} +#endif + +#ifdef CONFIG_SPL_BUILD +#include +#include +#include "asm/arch/mx6dl-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +static int mx6s_dcd_table[] = { +/* ddr-setup.cfg */ + +MX6_IOM_DRAM_SDQS0, 0x00000030, +MX6_IOM_DRAM_SDQS1, 0x00000030, +MX6_IOM_DRAM_SDQS2, 0x00000030, +MX6_IOM_DRAM_SDQS3, 0x00000030, +MX6_IOM_DRAM_SDQS4, 0x00000030, +MX6_IOM_DRAM_SDQS5, 0x00000030, +MX6_IOM_DRAM_SDQS6, 0x00000030, +MX6_IOM_DRAM_SDQS7, 0x00000030, + +MX6_IOM_GRP_B0DS, 0x00000030, +MX6_IOM_GRP_B1DS, 0x00000030, +MX6_IOM_GRP_B2DS, 0x00000030, +MX6_IOM_GRP_B3DS, 0x00000030, +MX6_IOM_GRP_B4DS, 0x00000030, +MX6_IOM_GRP_B5DS, 0x00000030, +MX6_IOM_GRP_B6DS, 0x00000030, +MX6_IOM_GRP_B7DS, 0x00000030, +MX6_IOM_GRP_ADDDS, 0x00000030, +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +MX6_IOM_GRP_CTLDS, 0x00000030, + +MX6_IOM_DRAM_DQM0, 0x00020030, +MX6_IOM_DRAM_DQM1, 0x00020030, +MX6_IOM_DRAM_DQM2, 0x00020030, +MX6_IOM_DRAM_DQM3, 0x00020030, +MX6_IOM_DRAM_DQM4, 0x00020030, +MX6_IOM_DRAM_DQM5, 0x00020030, +MX6_IOM_DRAM_DQM6, 0x00020030, +MX6_IOM_DRAM_DQM7, 0x00020030, + +MX6_IOM_DRAM_CAS, 0x00020030, +MX6_IOM_DRAM_RAS, 0x00020030, +MX6_IOM_DRAM_SDCLK_0, 0x00020030, +MX6_IOM_DRAM_SDCLK_1, 0x00020030, + +MX6_IOM_DRAM_RESET, 0x00020030, +MX6_IOM_DRAM_SDCKE0, 0x00003000, +MX6_IOM_DRAM_SDCKE1, 0x00003000, + +MX6_IOM_DRAM_SDODT0, 0x00003030, +MX6_IOM_DRAM_SDODT1, 0x00003030, + +/* (differential input) */ +MX6_IOM_DDRMODE_CTL, 0x00020000, +/* (differential input) */ +MX6_IOM_GRP_DDRMODE, 0x00020000, +/* disable ddr pullups */ +MX6_IOM_GRP_DDRPKE, 0x00000000, +MX6_IOM_DRAM_SDBA2, 0x00000000, +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +MX6_IOM_GRP_DDR_TYPE, 0x000C0000, + +/* Read data DQ Byte0-3 delay */ +MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +/* TODO: check what the RALAT field does */ +MX6_MMDC_P0_MDMISC, 0x00081740, + +/* + * MDSCR con_req + */ +MX6_MMDC_P0_MDSCR, 0x00008000, + + +/* 800mhz_2x64mx16.cfg */ + +MX6_MMDC_P0_MDPDC, 0x0002002D, +MX6_MMDC_P0_MDCFG0, 0x2C305503, +MX6_MMDC_P0_MDCFG1, 0xB66D8D63, +MX6_MMDC_P0_MDCFG2, 0x01FF00DB, +MX6_MMDC_P0_MDRWD, 0x000026D2, +MX6_MMDC_P0_MDOR, 0x00301023, +MX6_MMDC_P0_MDOTC, 0x00333030, +MX6_MMDC_P0_MDPDC, 0x0002556D, +/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */ +MX6_MMDC_P0_MDASP, 0x00000017, +/* DDR3 DATA BUS SIZE: 64BIT */ +/* MX6_MMDC_P0_MDCTL, 0x821A0000, */ +/* DDR3 DATA BUS SIZE: 32BIT */ +MX6_MMDC_P0_MDCTL, 0x82190000, + +/* Write commands to DDR */ +/* Load Mode Registers */ +/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ +/* MX6_MMDC_P0_MDSCR, 0x04408032, */ +MX6_MMDC_P0_MDSCR, 0x04008032, +MX6_MMDC_P0_MDSCR, 0x00008033, +MX6_MMDC_P0_MDSCR, 0x00048031, +MX6_MMDC_P0_MDSCR, 0x13208030, +/* ZQ calibration */ +MX6_MMDC_P0_MDSCR, 0x04008040, + +MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, +MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, +MX6_MMDC_P0_MDREF, 0x00005800, + +MX6_MMDC_P0_MPODTCTRL, 0x00000000, +MX6_MMDC_P1_MPODTCTRL, 0x00000000, + +MX6_MMDC_P0_MPDGCTRL0, 0x42360232, +MX6_MMDC_P0_MPDGCTRL1, 0x021F022A, +MX6_MMDC_P1_MPDGCTRL0, 0x421E0224, +MX6_MMDC_P1_MPDGCTRL1, 0x02110218, + +MX6_MMDC_P0_MPRDDLCTL, 0x41434344, +MX6_MMDC_P1_MPRDDLCTL, 0x4345423E, +MX6_MMDC_P0_MPWRDLCTL, 0x39383339, +MX6_MMDC_P1_MPWRDLCTL, 0x3E363930, + +MX6_MMDC_P0_MPWLDECTRL0, 0x00340039, +MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D, +MX6_MMDC_P1_MPWLDECTRL0, 0x00120019, +MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D, + +MX6_MMDC_P0_MPMUR0, 0x00000800, +MX6_MMDC_P1_MPMUR0, 0x00000800, +MX6_MMDC_P0_MDSCR, 0x00000000, +MX6_MMDC_P0_MAPSR, 0x00011006, +}; + +static int mx6dl_dcd_table[] = { +/* ddr-setup.cfg */ + +MX6_IOM_DRAM_SDQS0, 0x00000030, +MX6_IOM_DRAM_SDQS1, 0x00000030, +MX6_IOM_DRAM_SDQS2, 0x00000030, +MX6_IOM_DRAM_SDQS3, 0x00000030, +MX6_IOM_DRAM_SDQS4, 0x00000030, +MX6_IOM_DRAM_SDQS5, 0x00000030, +MX6_IOM_DRAM_SDQS6, 0x00000030, +MX6_IOM_DRAM_SDQS7, 0x00000030, + +MX6_IOM_GRP_B0DS, 0x00000030, +MX6_IOM_GRP_B1DS, 0x00000030, +MX6_IOM_GRP_B2DS, 0x00000030, +MX6_IOM_GRP_B3DS, 0x00000030, +MX6_IOM_GRP_B4DS, 0x00000030, +MX6_IOM_GRP_B5DS, 0x00000030, +MX6_IOM_GRP_B6DS, 0x00000030, +MX6_IOM_GRP_B7DS, 0x00000030, +MX6_IOM_GRP_ADDDS, 0x00000030, +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +MX6_IOM_GRP_CTLDS, 0x00000030, + +MX6_IOM_DRAM_DQM0, 0x00020030, +MX6_IOM_DRAM_DQM1, 0x00020030, +MX6_IOM_DRAM_DQM2, 0x00020030, +MX6_IOM_DRAM_DQM3, 0x00020030, +MX6_IOM_DRAM_DQM4, 0x00020030, +MX6_IOM_DRAM_DQM5, 0x00020030, +MX6_IOM_DRAM_DQM6, 0x00020030, +MX6_IOM_DRAM_DQM7, 0x00020030, + +MX6_IOM_DRAM_CAS, 0x00020030, +MX6_IOM_DRAM_RAS, 0x00020030, +MX6_IOM_DRAM_SDCLK_0, 0x00020030, +MX6_IOM_DRAM_SDCLK_1, 0x00020030, + +MX6_IOM_DRAM_RESET, 0x00020030, +MX6_IOM_DRAM_SDCKE0, 0x00003000, +MX6_IOM_DRAM_SDCKE1, 0x00003000, + +MX6_IOM_DRAM_SDODT0, 0x00003030, +MX6_IOM_DRAM_SDODT1, 0x00003030, + +/* (differential input) */ +MX6_IOM_DDRMODE_CTL, 0x00020000, +/* (differential input) */ +MX6_IOM_GRP_DDRMODE, 0x00020000, +/* disable ddr pullups */ +MX6_IOM_GRP_DDRPKE, 0x00000000, +MX6_IOM_DRAM_SDBA2, 0x00000000, +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +MX6_IOM_GRP_DDR_TYPE, 0x000C0000, + +/* Read data DQ Byte0-3 delay */ +MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, +MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, +MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +/* TODO: check what the RALAT field does */ +MX6_MMDC_P0_MDMISC, 0x00081740, + +/* + * MDSCR con_req + */ +MX6_MMDC_P0_MDSCR, 0x00008000, + + +/* 800mhz_2x64mx16.cfg */ + +MX6_MMDC_P0_MDPDC, 0x0002002D, +MX6_MMDC_P0_MDCFG0, 0x2C305503, +MX6_MMDC_P0_MDCFG1, 0xB66D8D63, +MX6_MMDC_P0_MDCFG2, 0x01FF00DB, +MX6_MMDC_P0_MDRWD, 0x000026D2, +MX6_MMDC_P0_MDOR, 0x00301023, +MX6_MMDC_P0_MDOTC, 0x00333030, +MX6_MMDC_P0_MDPDC, 0x0002556D, +/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */ +MX6_MMDC_P0_MDASP, 0x00000017, +/* DDR3 DATA BUS SIZE: 64BIT */ +MX6_MMDC_P0_MDCTL, 0x821A0000, +/* DDR3 DATA BUS SIZE: 32BIT */ +/* MX6_MMDC_P0_MDCTL, 0x82190000, */ + +/* Write commands to DDR */ +/* Load Mode Registers */ +/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ +/* MX6_MMDC_P0_MDSCR, 0x04408032, */ +MX6_MMDC_P0_MDSCR, 0x04008032, +MX6_MMDC_P0_MDSCR, 0x00008033, +MX6_MMDC_P0_MDSCR, 0x00048031, +MX6_MMDC_P0_MDSCR, 0x13208030, +/* ZQ calibration */ +MX6_MMDC_P0_MDSCR, 0x04008040, + +MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, +MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, +MX6_MMDC_P0_MDREF, 0x00005800, + +MX6_MMDC_P0_MPODTCTRL, 0x00000000, +MX6_MMDC_P1_MPODTCTRL, 0x00000000, + +MX6_MMDC_P0_MPDGCTRL0, 0x42360232, +MX6_MMDC_P0_MPDGCTRL1, 0x021F022A, +MX6_MMDC_P1_MPDGCTRL0, 0x421E0224, +MX6_MMDC_P1_MPDGCTRL1, 0x02110218, + +MX6_MMDC_P0_MPRDDLCTL, 0x41434344, +MX6_MMDC_P1_MPRDDLCTL, 0x4345423E, +MX6_MMDC_P0_MPWRDLCTL, 0x39383339, +MX6_MMDC_P1_MPWRDLCTL, 0x3E363930, + +MX6_MMDC_P0_MPWLDECTRL0, 0x00340039, +MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D, +MX6_MMDC_P1_MPWLDECTRL0, 0x00120019, +MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D, + +MX6_MMDC_P0_MPMUR0, 0x00000800, +MX6_MMDC_P1_MPMUR0, 0x00000800, +MX6_MMDC_P0_MDSCR, 0x00000000, +MX6_MMDC_P0_MAPSR, 0x00011006, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFFFF3, &ccm->CCGR2); + writel(0x3FF0300F, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000F3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ + writel(0x000000FB, &ccm->ccosr); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +static void ddr_init(int *table, int size) +{ + int i; + + for (i = 0; i < size / 2 ; i++) + writel(table[2 * i + 1], table[2 * i]); +} + +static void spl_dram_init(void) +{ + int minc, maxc; + + switch (get_cpu_temp_grade(&minc, &maxc)) { + case TEMP_COMMERCIAL: + case TEMP_EXTCOMMERCIAL: + if (is_cpu_type(MXC_CPU_MX6DL)) { + puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n"); + ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); + } else { + puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n"); + ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); + } + break; + case TEMP_INDUSTRIAL: + case TEMP_AUTOMOTIVE: + default: + if (is_cpu_type(MXC_CPU_MX6DL)) { + ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); + } else { + puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); + ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); + } + break; + }; + udelay(100); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Make sure we use dte mode */ + setup_dtemode_uart(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} + +#endif + +static struct mxc_serial_platdata mxc_serial_plat = { + .reg = (struct mxc_uart *)UART1_BASE, + .use_dte = true, +}; + +U_BOOT_DEVICE(mxc_serial) = { + .name = "serial_mxc", + .platdata = &mxc_serial_plat, +}; diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg new file mode 100644 index 0000000..e7886de --- /dev/null +++ b/board/toradex/colibri_imx6/colibri_imx6.cfg @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" + +#if CONFIG_DDR_MB == 256 +#include "800mhz_2x64mx16.cfg" +#elif CONFIG_DDR_MB == 512 +#include "800mhz_4x64mx16.cfg" +#else +#error "unknown DDR size" +#endif + +#include "clocks.cfg" diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg new file mode 100644 index 0000000..f46ae55 --- /dev/null +++ b/board/toradex/colibri_imx6/ddr-setup.cfg @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +/* TODO: check what the RALAT field does */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +/* + * MDSCR con_req + */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c new file mode 100644 index 0000000..cff07e9 --- /dev/null +++ b/board/toradex/colibri_imx6/do_fuse.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Helpers for i.MX OTP fusing during module production +*/ + +#include +#ifndef CONFIG_SPL_BUILD +#include +#include + +static int mfgr_fuse(void) +{ + unsigned val, val6; + + fuse_sense(0, 5, &val); + printf("Fuse 0, 5: %8x\n", val); + fuse_sense(0, 6, &val6); + printf("Fuse 0, 6: %8x\n", val6); + fuse_sense(4, 3, &val); + printf("Fuse 4, 3: %8x\n", val); + fuse_sense(4, 2, &val); + printf("Fuse 4, 2: %8x\n", val); + if (val6 & 0x10) { + puts("BT_FUSE_SEL already fused, will do nothing\n"); + return CMD_RET_FAILURE; + } + /* boot cfg */ + fuse_prog(0, 5, 0x00005072); + /* BT_FUSE_SEL */ + fuse_prog(0, 6, 0x00000010); + return CMD_RET_SUCCESS; +} + +int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ret; + puts("Fusing...\n"); + ret = mfgr_fuse(); + if (ret == CMD_RET_SUCCESS) + puts("done.\n"); + else + puts("failed.\n"); + return ret; +} + +int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned val; + int ret; + int confirmed = argc >= 1 && !strcmp(argv[1], "-y"); + + /* can be used in scripts for command availability check */ + if (argc >= 1 && !strcmp(argv[1], "-n")) + return CMD_RET_SUCCESS; + + /* boot cfg */ + fuse_sense(0, 5, &val); + printf("Fuse 0, 5: %8x\n", val); + if (val & 0x10) { + puts("Fast boot mode already fused, no need to fuse\n"); + return CMD_RET_SUCCESS; + } + if (!confirmed) { + puts("Warning: Programming fuses is an irreversible operation!\n" + " Updating to fast boot mode prevents easy\n" + " downgrading to previous BSP versions.\n" + "\nReally perform this fuse programming? \n"); + if (!confirm_yesno()) + return CMD_RET_FAILURE; + } + puts("Fusing fast boot mode...\n"); + ret = fuse_prog(0, 5, 0x00005072); + if (ret == CMD_RET_SUCCESS) + puts("done.\n"); + else + puts("failed.\n"); + return ret; +} + +U_BOOT_CMD( + mfgr_fuse, 1, 0, do_mfgr_fuse, + "OTP fusing during module production", + "" +); + +U_BOOT_CMD( + updt_fuse, 2, 0, do_updt_fuse, + "OTP fusing during module update", + "updt_fuse [-n] [-y] - boot cfg fast boot mode fusing" +); +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c new file mode 100644 index 0000000..618c571 --- /dev/null +++ b/board/toradex/colibri_imx6/pf0100.c @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Helpers for Freescale PMIC PF0100 +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include "pf0100_otp.inc" +#include "pf0100.h" + +/* define for PMIC register dump */ +/*#define DEBUG */ + +/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */ +static iomux_v3_cfg_t const pmic_prog_pads[] = { + MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), +# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3) +}; + +unsigned pmic_init(void) +{ + unsigned programmed = 0; + uchar bus = 1; + uchar devid, revid, val; + + puts("PMIC: "); + if (!((0 == i2c_set_bus_num(bus)) && + (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { + puts("i2c bus failed\n"); + return 0; + } + /* get device ident */ + if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) { + puts("i2c pmic devid read failed\n"); + return 0; + } + if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) { + puts("i2c pmic revid read failed\n"); + return 0; + } + printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid); + +#ifdef DEBUG + { + unsigned i, j; + + for (i = 0; i < 16; i++) + printf("\t%x", i); + for (j = 0; j < 0x80; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\nEXT Page 1"); + + val = PFUZE100_PAGE_REGISTER_PAGE1; + if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, + &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + + for (j = 0x80; j < 0x100; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\nEXT Page 2"); + + val = PFUZE100_PAGE_REGISTER_PAGE2; + if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, + &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + + for (j = 0x80; j < 0x100; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\n"); + } +#endif + /* get device programmed state */ + val = PFUZE100_PAGE_REGISTER_PAGE1; + if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return 0; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return programmed; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return programmed; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + switch (programmed) { + case 0: + printf("PMIC: not programmed\n"); + break; + case 3: + printf("PMIC: programmed\n"); + break; + default: + printf("PMIC: undefined programming state\n"); + break; + } + + return programmed; +} + +int pf0100_prog(void) +{ + unsigned char bus = 1; + unsigned char val; + unsigned int i; + + if (pmic_init() == 3) { + puts("PMIC already programmed, exiting\n"); + return CMD_RET_FAILURE; + } + /* set up gpio to manipulate vprog, initially off */ + imx_iomux_v3_setup_multiple_pads(pmic_prog_pads, + ARRAY_SIZE(pmic_prog_pads)); + gpio_direction_output(PMIC_PROG_VOLTAGE, 0); + + if (!((0 == i2c_set_bus_num(bus)) && + (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { + puts("i2c bus failed\n"); + return CMD_RET_FAILURE; + } + + for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) { + switch (pmic_otp_prog[i].cmd) { + case pmic_i2c: + val = (unsigned char) (pmic_otp_prog[i].value & 0xff); + if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg, + 1, &val, 1)) { + printf("i2c write failed, reg 0x%2x, value 0x%2x\n", + pmic_otp_prog[i].reg, val); + return CMD_RET_FAILURE; + } + break; + case pmic_delay: + udelay(pmic_otp_prog[i].value * 1000); + break; + case pmic_vpgm: + gpio_direction_output(PMIC_PROG_VOLTAGE, + pmic_otp_prog[i].value); + break; + case pmic_pwr: + /* TODO */ + break; + } + } + return CMD_RET_SUCCESS; +} + +int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ret; + puts("Programming PMIC OTP..."); + ret = pf0100_prog(); + if (ret == CMD_RET_SUCCESS) + puts("done.\n"); + else + puts("failed.\n"); + return ret; +} + +U_BOOT_CMD( + pf0100_otp_prog, 1, 0, do_pf0100_prog, + "Program the OTP fuses on the PMIC PF0100", + "" +); diff --git a/board/toradex/colibri_imx6/pf0100.h b/board/toradex/colibri_imx6/pf0100.h new file mode 100644 index 0000000..c84cab8 --- /dev/null +++ b/board/toradex/colibri_imx6/pf0100.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Helpers for Freescale PMIC PF0100 +*/ + +#ifndef PF0100_H_ +#define PF0100_H_ + +/* 7-bit I2C bus slave address */ +#define PFUZE100_I2C_ADDR (0x08) +/* Register Addresses */ +#define PFUZE100_DEVICEID (0x0) +#define PFUZE100_REVID (0x3) +#define PFUZE100_SW1AMODE (0x23) +#define PFUZE100_SW1ACON 36 +#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ +#define PFUZE100_SW1ACON_SPEED_M (0x3<<6) +#define PFUZE100_SW1CCON 49 +#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */ +#define PFUZE100_SW1CCON_SPEED_M (0x3<<6) +#define PFUZE100_SW1AVOL 32 +#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0) +#define PFUZE100_SW1CVOL 46 +#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0) +#define PFUZE100_VGEN1CTL (0x6c) +#define PFUZE100_VGEN1_VAL (0x30 + 0x08) /* Always ON, 1.2V */ +#define PFUZE100_SWBSTCTL (0x66) +/* Always ON, Auto Switching Mode, 5.0V */ +#define PFUZE100_SWBST_VAL (0x40 + 0x08 + 0x00) + +/* chooses the extended page (registers 0x80..0xff) */ +#define PFUZE100_PAGE_REGISTER 0x7f +#define PFUZE100_PAGE_REGISTER_PAGE_M (0x1f << 0) +#define PFUZE100_PAGE_REGISTER_PAGE1 (0x01 & PFUZE100_PAGE_REGISTER_PAGE_M) +#define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M) + +/* extended page 1 */ +#define PFUZE100_FUSE_POR1 0xe4 +#define PFUZE100_FUSE_POR2 0xe5 +#define PFUZE100_FUSE_POR3 0xe6 +#define PFUZE100_FUSE_POR_M (0x1 << 1) + + +/* output some informational messages, return the number FUSE_POR=1 */ +/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */ +unsigned pmic_init(void); + +/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */ +int pf0100_prog(void); + +#endif /* PF0100_H_ */ diff --git a/board/toradex/colibri_imx6/pf0100_otp.inc b/board/toradex/colibri_imx6/pf0100_otp.inc new file mode 100644 index 0000000..255392b --- /dev/null +++ b/board/toradex/colibri_imx6/pf0100_otp.inc @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2014-2016, Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +// Register Output for PF0100 programmer +// Customer: Toradex AG +// Program: Colibri iMX6 +// Sample marking: +// Date: 24.07.2015 +// Time: 10:52:58 +// Generated from Spreadsheet Revision: P1.8 + +/* sed commands to get from programmer script to struct */ +/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc + sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc + sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */ + +enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr }; +struct pmic_otp_prog_t{ + unsigned char cmd; + unsigned char reg; + unsigned short value; +}; + +struct pmic_otp_prog_t pmic_otp_prog[] = { +{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1 +{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94 +{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95 +{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96 +{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102 +{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103 +{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104 +{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106 +{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108 +{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110 +{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111 +{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112 +{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114 +{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115 +{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116 +{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118 +{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120 +{pmic_i2c, 0xBD, 0x0E}, // Auto gen from Row123 +{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126 +{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130 +{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134 +{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138 +{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139 +{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142 +{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147 +{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150 +{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151 +{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154 +{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155 +{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158 + +#if 0 /* TBB mode */ +{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1 +{pmic_delay, 0, 10}, +#else +// Write OTP +{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1 +{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1 +{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1 +{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register +{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register +{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2 +{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register +{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST +//VPGM:DOWN:n +//VPGM:UP:n +{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up +//----------------------------------------------------------------------------------- +// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10) +//----------------------------------------------------------------------------------- +// BANK 1 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN +{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 2 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN +{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 3 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN +{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 4 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN +{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 5 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN +{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 6 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN +{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 7 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN +{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 8 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN +{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 9 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN +{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +// BANK 10 +//----------------------------------------------------------------------------------- +{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN +{pmic_delay, 0, 10}, // Allow time for bank programming to complete +{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN +{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits +//----------------------------------------------------------------------------------- +{pmic_vpgm, 0, 0}, // Turn off 8V SWBST +{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off +{pmic_i2c, 0xD0, 0x00}, // Clear +{pmic_i2c, 0xD1, 0x00}, // Clear +{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data +{pmic_delay, 0, 500}, +{pmic_pwr, 0, 1}, +#endif +}; \ No newline at end of file diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig new file mode 100644 index 0000000..f14f701 --- /dev/null +++ b/configs/colibri_imx6_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_COLIBRI_IMX6=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL" +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_SPL_DMA_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Colibri iMX6 # " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Toradex" +CONFIG_G_DNL_VENDOR_NUM=0x1b67 +CONFIG_G_DNL_PRODUCT_NUM=0x4020 +CONFIG_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig new file mode 100644 index 0000000..a5cf60b --- /dev/null +++ b/configs/colibri_imx6_nospl_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_COLIBRI_IMX6=y +CONFIG_VIDEO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256" +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Colibri iMX6 # " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Toradex" +CONFIG_G_DNL_VENDOR_NUM=0x1b67 +CONFIG_G_DNL_PRODUCT_NUM=0x4020 +CONFIG_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h new file mode 100644 index 0000000..4ed94fe --- /dev/null +++ b/include/configs/colibri_imx6.h @@ -0,0 +1,310 @@ +/* + * Copyright 2013-2015 Toradex, Inc. + * + * Configuration settings for the Toradex Colibri iMX6 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#define CONFIG_SYS_THUMB_BUILD +/* These are not provided in SPL and result in a linker error */ +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_USE_ARCH_MEMSET +#endif + +#undef CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ + +#define CONFIG_SYS_GENERIC_BOARD + +#include +#include + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#define CONFIG_SPL_PAD_TO 0x11000 /* 4k IVT/DCD, 64k SPL */ +#endif + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MISC_INIT_R + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* Make the HW version stuff available in U-Boot env */ +#define CONFIG_VERSION_VARIABLE /* ver environment variable */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* OCOTP Configs */ +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FAT_WRITE +#define CONFIG_DOS_PARTITION + +/* Network */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 16352 +#define CONFIG_TFTP_TSIZE + +/* USB Configs */ +/* Host */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL +#endif /* CONFIG_USB_KEYBOARD */ +/* Client */ +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_USBD_HS + +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_G_DNL_MANUFACTURER "Toradex" +/* USB DFU */ +#define CONFIG_DFU_MMC + +/* Miscellaneous commands */ +#define CONFIG_CMD_BMODE +#define CONFIG_MXC_GPIO + +/* Framebuffer and LCD */ +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_CMD_BMP + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FLASH + +#undef CONFIG_IPADDR +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#undef CONFIG_SERVERIP +#define CONFIG_SERVERIP 192.168.10.1 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#ifdef CONFIG_CMD_MMC +#define CONFIG_DRIVE_MMC "mmc " +#else +#define CONFIG_DRIVE_MMC +#endif + +#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC + +#define DFU_ALT_EMMC_INFO \ + "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "uImage fat 0 1;" \ + "imx6q-colibri-eval-v3.dtb fat 0 1;" \ + "imx6q-colibri-cam-eval-v3.dtb fat 0 1" + +#define EMMC_BOOTCMD \ + "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \ + "rootwait\0" \ + "emmcboot=run setup; " \ + "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ + "${vidargs}; echo Booting from internal eMMC chip...; " \ + "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \ + "${boot_file} && run fdt_fixup && " \ + "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \ + "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x12000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x11000000\0" \ + "ramdisk_addr_r=0x12100000\0" + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ + "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ + "run nfsdtbload; dhcp ${kernel_addr_r} " \ + "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \ + "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ + "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define SD_BOOTCMD \ + "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \ + "rootwait\0" \ + "sdboot=run setup; " \ + "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ + "${vidargs}; echo Booting from SD card; " \ + "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \ + "${boot_file} && run fdt_fixup && " \ + "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \ + "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define USB_BOOTCMD \ + "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \ + "rootwait\0" \ + "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \ + "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ + "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \ + "${boot_file} && run fdt_fixup && " \ + "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \ + "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" + +#define FDT_FILE "imx6dl-colibri-eval-v3.dtb" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \ + "run nfsboot ; echo ; echo nfsboot failed ; " \ + "usb start ;" \ + "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ + "boot_file=uImage\0" \ + "console=ttymxc0\0" \ + "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ + "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ + EMMC_BOOTCMD \ + "fdt_file=" FDT_FILE "\0" \ + "fdt_fixup=;\0" \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + SD_BOOTCMD \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ + "flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \ + "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setup=setenv setupargs fec_mac=${ethaddr} " \ + "consoleblank=0 no_console_suspend=1 console=tty1 " \ + "console=${console},${baudrate}n8\0 " \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "splashpos=m,m\0" \ + "vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \ + "video=mxcfb1:off fbmem=8M\0 " + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 48 + +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC + +#if defined(CONFIG_ENV_IS_IN_MMC) +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ + CONFIG_TDX_CFG_BLOCK_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 +#endif + +#define CONFIG_OF_SYSTEM_SETUP + +#define CONFIG_CMD_TIME + +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_CRC32_VERIFY + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From c94981efa20cc5861caad6a53e589121bf978fb1 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 1 Dec 2016 16:37:36 -0200 Subject: udoo_neo: Remove USDHC3 support It's not necessary to support USDHC3 in U-Boot as it's being used for the WLAN. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index 7f17469..efe8605 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -81,16 +81,6 @@ static iomux_v3_cfg_t const board_recognition_pads[] = { MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG, }; -static iomux_v3_cfg_t const usdhc3_pads[] = { - /* Configured for WLAN */ - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_b_pad = { MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -171,91 +161,19 @@ static struct fsl_esdhc_cfg usdhc_cfg[2] = { int board_mmc_getcd(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - } - - return ret; + return !gpio_get_value(USDHC2_CD_GPIO); } int board_mmc_init(bd_t *bis) { -#ifndef CONFIG_SPL_BUILD - int i, ret; - - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 USDHC2 - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - gpio_direction_input(USDHC2_CD_GPIO); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers\ - (%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) { - printf("Warning:\ - failed to initialize mmc dev %d\n", i); - return ret; - } - } - - return 0; -#else - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - u32 val; - u32 port; - - val = readl(&src_regs->sbmr1); - - if ((val & 0xc0) != 0x40) { - printf("Not boot from USDHC!\n"); - return -EINVAL; - } - - port = (val >> 11) & 0x3; - printf("port %d\n", port); - switch (port) { - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - gpio_direction_input(USDHC2_CD_GPIO); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; - break; - } + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif } char *board_string(void) diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 81e0481..cf75186 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -27,7 +27,6 @@ /* Command definition */ #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/ /* Linux only */ -- cgit v0.10.2 From 4a056c4504d078356fa3afcaed963d31d5e901c7 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 1 Dec 2016 16:37:37 -0200 Subject: udoo_neo: Move MX6SX configuration to Kconfig It's not necessary to define the processor in the defconfig file. The preferred method to select the SoC is via Kconfig file. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 5a8c7bf..cca8a87 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -217,6 +217,7 @@ config TARGET_UDOO config TARGET_UDOO_NEO bool "UDOO Neo" select SUPPORT_SPL + select MX6SX config TARGET_SAMTEC_VINING_2000 bool "samtec VIN|ING 2000" diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 3304afb..f88820c 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -11,7 +11,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set -- cgit v0.10.2 From 72d900bdbc8bf58d9dfb646ecfcc0882031034ae Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 1 Dec 2016 16:37:38 -0200 Subject: udoo_neo: Staticize board_string() Change board_string() function to static because it's being used locally. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index efe8605..cfeed6f 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -176,7 +176,7 @@ int board_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); } -char *board_string(void) +static char *board_string(void) { switch (get_board_value()) { case UDOO_NEO_TYPE_BASIC: -- cgit v0.10.2 From b3f276cb6f753a3c1ed66c713500d56713e981b3 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 1 Dec 2016 16:37:39 -0200 Subject: udoo_neo: Remove mmcautodetect option It's not necessary to define the mmcautodetect as it is not used anywhere. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index cf75186..164980f 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -40,7 +40,6 @@ "ip_dyn=yes\0" \ "mmcdev=0\0" \ "mmcrootfstype=ext4\0" \ - "mmcautodetect=no\0" \ "findfdt="\ "if test $board_name = BASIC; then " \ "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ -- cgit v0.10.2 From 6cc8d4da8d1d6f007ee6b396cb50dd4e12457e3c Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 1 Dec 2016 16:37:40 -0200 Subject: udoo_neo: Remove console option It's not necessary to define the console option as we use the distro config. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 164980f..1b7a03f 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -32,7 +32,6 @@ /* Linux only */ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=undefined\0" \ -- cgit v0.10.2 From 0719b16f1990fcf911d81cb842508d1ff4580ff4 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Thu, 1 Dec 2016 16:37:41 -0200 Subject: udoo_neo: Add thermal support Add thermal support on the Kconfig file. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index cca8a87..c682484 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -218,6 +218,8 @@ config TARGET_UDOO_NEO bool "UDOO Neo" select SUPPORT_SPL select MX6SX + select DM + select DM_THERMAL config TARGET_SAMTEC_VINING_2000 bool "samtec VIN|ING 2000" diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 1b7a03f..0357631 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -88,4 +88,6 @@ #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_IMX_THERMAL + #endif /* __CONFIG_H */ -- cgit v0.10.2 From 894a4b4da7e295a95741c8b0f969e43f8ee239af Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Tue, 6 Dec 2016 15:38:24 -0200 Subject: power: pmic: Add Voltage configuration macro Add pfuze3000 voltage configuration macro for SW1AB, SW3 and VLDO1/2 according to tables 53, 57 and 62 on PF3000 datasheet. Signed-off-by: Breno Lima diff --git a/include/power/pfuze3000_pmic.h b/include/power/pfuze3000_pmic.h index e8b892b..7d66ba4 100644 --- a/include/power/pfuze3000_pmic.h +++ b/include/power/pfuze3000_pmic.h @@ -75,4 +75,9 @@ enum { int power_pfuze3000_init(unsigned char bus); +/* Voltage Configuration */ +#define PFUZE3000_SW1AB_SETP(x) ((x - 7000) / 250) +#define PFUZE3000_SW3_SETP(x) ((x - 9000) / 500) +#define PFUZE3000_VLDO_SETP(x) ((x - 8000) / 500) + #endif -- cgit v0.10.2 From 21729bcdbdcd102cdb15535331d7e4b7b204a0b4 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Tue, 6 Dec 2016 15:38:25 -0200 Subject: udoo_neo: Add PFUZE300 PMIC support UDOO Neo boards has a PFUZE300 connected to I2C1 bus. Tested on a UDOO Neo Full with "pmic PFUZE3000 dump" command. Signed-off-by: Breno Lima diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index cfeed6f..ad7452c 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -19,10 +19,14 @@ #include #include #include +#include #include #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +45,11 @@ enum { PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm) @@ -56,6 +65,136 @@ int dram_init(void) return 0; } +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; +#endif + +#ifdef CONFIG_POWER +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(PFUZE3000_I2C_BUS); + if (ret) + return ret; + + p = pmic_get("PFUZE3000"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE3000_DEVICEID, ®); + pmic_reg_read(p, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); + if (ret) + return ret; + + ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc); + if (ret) + return ret; + + ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc); + if (ret) + return ret; + + ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc); + if (ret) + return ret; + + ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc); + if (ret) + return ret; + + /* set SW1A standby voltage 0.975V */ + pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®); + reg &= ~0x3f; + reg |= PFUZE3000_SW1AB_SETP(9750); + ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); + if (ret) + return ret; + + /* set SW1B standby voltage 0.975V */ + pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE3000_SW1AB_SETP(9750); + ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); + if (ret) + return ret; + + /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE3000_SW1ACONF, ®); + reg &= ~0xc0; + reg |= 0x40; + ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg); + if (ret) + return ret; + + /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE3000_SW1BCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg); + if (ret) + return ret; + + /* set VDD_ARM_IN to 1.350V */ + pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®); + reg &= ~0x3f; + reg |= PFUZE3000_SW1AB_SETP(13500); + ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg); + if (ret) + return ret; + + /* set VDD_SOC_IN to 1.350V */ + pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); + reg &= ~0x3f; + reg |= PFUZE3000_SW1AB_SETP(13500); + ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); + if (ret) + return ret; + + /* set DDR_1_5V to 1.350V */ + pmic_reg_read(p, PFUZE3000_SW3VOLT, ®); + reg &= ~0x0f; + reg |= PFUZE3000_SW3_SETP(13500); + ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg); + if (ret) + return ret; + + /* set VGEN2_1V5 to 1.5V */ + pmic_reg_read(p, PFUZE3000_VLDO2CTL, ®); + reg &= ~0x0f; + reg |= PFUZE3000_VLDO_SETP(15000); + /* enable */ + reg |= 0x10; + ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg); + if (ret) + return ret; + + return 0; +} +#endif + static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -115,6 +254,10 @@ int board_init(void) /* Active high for ncp692 */ gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); + #ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + #endif + return 0; } diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 0357631..0c59068 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -90,4 +90,17 @@ #define CONFIG_IMX_THERMAL +/* I2C configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#define PFUZE3000_I2C_BUS 0 + #endif /* __CONFIG_H */ -- cgit v0.10.2 From a11e30f8c877ea9aaeef0e9e762b811a08d65bd1 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Tue, 6 Dec 2016 15:38:26 -0200 Subject: udoo_neo: Add Ethernet support UDOO Neo boards has one FEC port connected to KSZ8091, add support for it. Tested on a UDOO Neo Full with "dhcp zImage" command. Signed-off-by: Breno Lima diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index ad7452c..688b522 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -25,8 +26,11 @@ #include #include #include +#include +#include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +54,16 @@ enum { PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) + #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm) @@ -213,6 +227,27 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const phy_control_pads[] = { + /* 25MHz Ethernet PHY Clock */ + MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | + MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), +}; + static iomux_v3_cfg_t const board_recognition_pads[] = { /*Connected to R184*/ MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG, @@ -233,6 +268,66 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +static int setup_fec(int fec_id) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg; + + imx_iomux_v3_setup_multiple_pads(phy_control_pads, + ARRAY_SIZE(phy_control_pads)); + + /* Reset PHY */ + gpio_direction_output(IMX_GPIO_NR(2, 1) , 0); + udelay(10000); + gpio_set_value(IMX_GPIO_NR(2, 1), 1); + udelay(100); + + reg = readl(&anatop->pll_enet); + reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; + writel(reg, &anatop->pll_enet); + + return enable_fec_anatop_clock(fec_id, ENET_25MHZ); +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + + setup_fec(CONFIG_FEC_ENET_DEV); + + bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV); + if (!bus) + return -EINVAL; + + phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR), + PHY_INTERFACE_MODE_RMII); + if (!phydev) { + free(bus); + return -EINVAL; + } + + ret = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev); + if (ret) { + free(bus); + free(phydev); + return ret; + } + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + int board_init(void) { /* Address of boot parameters */ diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index f88820c..5df4ef9 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -19,7 +19,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_MMC=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_DHCP=y +CONFIG_CMD_DHCP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 0c59068..aec39db 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -58,7 +58,8 @@ BOOTENV #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) #define CONFIG_BOOTCOMMAND \ "run findfdt; " \ @@ -103,4 +104,18 @@ #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #define PFUZE3000_I2C_BUS 0 +/* Network */ +#define CONFIG_FEC_MXC +#define CONFIG_MII + +#define CONFIG_FEC_ENET_DEV 0 +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 + +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC0" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + #endif /* __CONFIG_H */ -- cgit v0.10.2 From 727feafebbdfe23d86b8517aedcb4501d4c49ba9 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Wed, 7 Dec 2016 16:46:32 +0100 Subject: ARM: imx6ul: Add support for liteSOM liteSOM is a System On Module (http://grinn-global.com/litesom/). It can't exists on its own, but will be used as part of other boards. Hardware specification: * NXP i.MX6UL processor * 256M or 512M DDR3 memory * optional eMMC (uSDHC2) Here we treat SOM similar to SOC, so we place it inside arch/arm/mach-* directory and make it possible to reuse initialization code (i.e. DDR, eMMC init) for all boards that use it. Signed-off-by: Marcin Niestroj diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 714dd8b..c655963 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -900,6 +900,8 @@ source "arch/arm/mach-keystone/Kconfig" source "arch/arm/mach-kirkwood/Kconfig" +source "arch/arm/mach-litesom/Kconfig" + source "arch/arm/mach-mvebu/Kconfig" source "arch/arm/cpu/armv7/ls102xa/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 236debb..ef4f69d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -58,6 +58,7 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_KEYSTONE) += keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood +machine-$(CONFIG_LITESOM) += litesom machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA diff --git a/arch/arm/mach-litesom/Kconfig b/arch/arm/mach-litesom/Kconfig new file mode 100644 index 0000000..9b7f36d --- /dev/null +++ b/arch/arm/mach-litesom/Kconfig @@ -0,0 +1,6 @@ +config LITESOM + bool + select MX6UL + select DM + select DM_THERMAL + select SUPPORT_SPL diff --git a/arch/arm/mach-litesom/Makefile b/arch/arm/mach-litesom/Makefile new file mode 100644 index 0000000..b15eb64 --- /dev/null +++ b/arch/arm/mach-litesom/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Grinn +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := litesom.o diff --git a/arch/arm/mach-litesom/include/mach/litesom.h b/arch/arm/mach-litesom/include/mach/litesom.h new file mode 100644 index 0000000..6833949 --- /dev/null +++ b/arch/arm/mach-litesom/include/mach/litesom.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2016 Grinn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_ARM_MACH_LITESOM_SOM_H__ +#define __ARCH_ARM_MACH_LITESOM_SOM_H__ + +int litesom_mmc_init(bd_t *bis); + +#ifdef CONFIG_SPL_BUILD +void litesom_init_f(void); +#endif + +#endif diff --git a/arch/arm/mach-litesom/litesom.c b/arch/arm/mach-litesom/litesom.c new file mode 100644 index 0000000..ac2eccf --- /dev/null +++ b/arch/arm/mach-litesom/litesom.c @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright (C) 2016 Grinn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const emmc_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* RST_B */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8}; + +#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10) + +int litesom_mmc_init(bd_t *bis) +{ + int ret; + + /* eMMC */ + imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads)); + gpio_direction_output(EMMC_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(EMMC_PWR_GPIO, 1); + emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + ret = fsl_esdhc_initialize(bis, &emmc_cfg); + if (ret) { + printf("Warning: failed to initialize mmc dev 1 (eMMC)\n"); + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +#include +#include +#include + + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41570155, + .p0_mprddlctl = 0x4040474A, + .p0_mpwrdlctl = 0x40405550, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 0, /* Refresh cycles at 64KHz */ + .refr = 1, /* 2 refresh commands per refresh cycle */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + unsigned long ram_size; + + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); + + /* + * Get actual RAM size, so we can adjust DDR row size for <512M + * memories + */ + ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M); + if (ram_size < SZ_512M) { + mem_ddr.rowaddr = 14; + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); + } +} + +void litesom_init_f(void) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + +#ifdef CONFIG_BOARD_EARLY_INIT_F + board_early_init_f(); +#endif + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} +#endif -- cgit v0.10.2 From c9e40e65e1dcf19f518fa3811bb6de2bf407360f Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Wed, 7 Dec 2016 16:46:33 +0100 Subject: board/liteboard: Add support for liteBoard liteBoard is a development board which uses liteSOM as its base. Hardware specification: * liteSOM (i.MX6UL, DRAM, eMMC) * Ethernet PHY (id 0) * USB host (usb_otg1) * MicroSD slot (uSDHC1) Signed-off-by: Marcin Niestroj diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index c682484..87978a3 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -186,6 +186,10 @@ config TARGET_PICO_IMX6UL bool "PICO-IMX6UL-EMMC" select MX6UL +config TARGET_LITEBOARD + bool "Grinn liteBoard (i.MX6UL)" + select LITESOM + config TARGET_PLATINUM_PICON bool "platinum-picon" select SUPPORT_SPL @@ -279,6 +283,7 @@ source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ullevk/Kconfig" +source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" diff --git a/board/grinn/liteboard/Kconfig b/board/grinn/liteboard/Kconfig new file mode 100644 index 0000000..e035872 --- /dev/null +++ b/board/grinn/liteboard/Kconfig @@ -0,0 +1,12 @@ +if TARGET_LITEBOARD + +config SYS_BOARD + default "liteboard" + +config SYS_VENDOR + default "grinn" + +config SYS_CONFIG_NAME + default "liteboard" + +endif diff --git a/board/grinn/liteboard/MAINTAINERS b/board/grinn/liteboard/MAINTAINERS new file mode 100644 index 0000000..b4474f1 --- /dev/null +++ b/board/grinn/liteboard/MAINTAINERS @@ -0,0 +1,6 @@ +LITEBOARD +M: Marcin Niestroj +S: Maintained +F: board/grinn/liteboard/ +F: include/configs/liteboard.h +F: configs/liteboard_defconfig diff --git a/board/grinn/liteboard/Makefile b/board/grinn/liteboard/Makefile new file mode 100644 index 0000000..e2492d6 --- /dev/null +++ b/board/grinn/liteboard/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Grinn +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/grinn/liteboard/README b/board/grinn/liteboard/README new file mode 100644 index 0000000..bee0394 --- /dev/null +++ b/board/grinn/liteboard/README @@ -0,0 +1,31 @@ +How to use U-Boot on Grinn's liteBoard +-------------------------------------- + +- Build U-Boot for liteBoard: + +$ make mrproper +$ make liteboard_defconfig +$ make + +This will generate the SPL image called SPL and the u-boot.img. + +- Flash the SPL image into the micro SD card: + +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + +- Flash the u-boot.img image into the micro SD card: + +sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Jumper settings: + +S1: 0 1 0 1 1 1 + +where 0 means bottom position and 1 means top position (from the +switch label numbers reference). + +- Insert the micro SD card in the board. + +- Connect USB cable between liteBoard and the PC for the power and console. + +- U-Boot messages should come up. diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c new file mode 100644 index 0000000..13dd0a6 --- /dev/null +++ b/board/grinn/liteboard/board.c @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright (C) 2016 Grinn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const sd_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4}; + +#define SD_CD_GPIO IMX_GPIO_NR(1, 19) + +static int mmc_get_env_devno(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + int dev_no; + u32 bootsel; + + bootsel = (soc_sbmr & 0x000000FF) >> 6; + + /* If not boot from sd/mmc, use default value */ + if (bootsel != 1) + return CONFIG_SYS_MMC_ENV_DEV; + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + dev_no = (soc_sbmr & 0x00001800) >> 11; + + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(SD_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + ret = 1; + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* SD */ + imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads)); + gpio_direction_input(SD_CD_GPIO); + sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + ret = fsl_esdhc_initialize(bis, &sd_cfg); + if (ret) { + printf("Warning: failed to initialize mmc dev 0 (SD)\n"); + return ret; + } + + return litesom_mmc_init(bis); +} + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = getenv("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_devno(); + + if (!check_mmc_autodetect()) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + dev_no); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + setup_iomux_fec(); + + return fecmxc_initialize(bis); +} + +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], + set gpr1[17]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +int board_usb_phy_mode(int port) +{ + return USB_INIT_HOST; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: Grinn liteBoard\n"); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void board_boot_order(u32 *spl_boot_list) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28); + unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1); + unsigned port = (reg >> 11) & 0x1; + + if (port == 0) { + spl_boot_list[0] = BOOT_DEVICE_MMC1; + spl_boot_list[1] = BOOT_DEVICE_MMC2; + } else { + spl_boot_list[0] = BOOT_DEVICE_MMC2; + spl_boot_list[1] = BOOT_DEVICE_MMC1; + } +} + +void board_init_f(ulong dummy) +{ + litesom_init_f(); +} +#endif diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig new file mode 100644 index 0000000..11c5b35 --- /dev/null +++ b/configs/liteboard_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_LITEBOARD=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg" +CONFIG_BOOTDELAY=1 +CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb" +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h new file mode 100644 index 0000000..a55d767 --- /dev/null +++ b/include/configs/liteboard.h @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2016 Grinn + * + * Configuration settings for the Grinn liteBoard (i.MX6UL). + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __LITEBOARD_CONFIG_H +#define __LITEBOARD_CONFIG_H + +#include +#include +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SUPPORT_EMMC_BOOT +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" + +#define CONFIG_CMD_BMODE + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 0 + +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC +#endif + +#define CONFIG_IMX_THERMAL + +#endif -- cgit v0.10.2 From faf1e62bf04b01dc7110a459f558aaf414bfcac0 Mon Sep 17 00:00:00 2001 From: Sanchayan Maity Date: Fri, 2 Dec 2016 14:28:27 +0530 Subject: configs: colibri_vf: Add fdt_fixup environment variable u-boot allows modifying a device tree after it is loaded into memory. Add fdt_fixup hook in u-boot environment which can facilitate such modifications. Signed-off-by: Sanchayan Maity diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index d58145e..be28324 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -99,7 +99,7 @@ "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \ "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \ - "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ #define NFS_BOOTCMD \ "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ @@ -108,7 +108,7 @@ "${setupargs} ${vidargs}; echo Booting from NFS...;" \ "dhcp ${kernel_addr_r} && " \ "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ - "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ #define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ @@ -119,7 +119,7 @@ "ubi part ubi && " \ "ubi read ${kernel_addr_r} kernel && " \ "ubi read ${fdt_addr_r} dtb && " \ - "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ #define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" @@ -131,6 +131,7 @@ "kernel_file=zImage\0" \ "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \ "fdt_board=eval-v3\0" \ + "fdt_fixup=;\0" \ "defargs=\0" \ "console=ttyLP0\0" \ "setup=setenv setupargs " \ -- cgit v0.10.2 From 7ce6d3c868407044703f93e315ea3b56fa80f7ff Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:20 +0800 Subject: imx: add i.MX 6SLL CPU type Add i.MX6SLL cpu type. MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A. Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 632faca..40fe813 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -155,6 +155,8 @@ const char *get_imx_type(u32 imxtype) return "6SOLO"; /* Solo version of the mx6 */ case MXC_CPU_MX6SL: return "6SL"; /* Solo-Lite version of the mx6 */ + case MXC_CPU_MX6SLL: + return "6SLL"; /* SLL version of the mx6 */ case MXC_CPU_MX6SX: return "6SX"; /* SoloX version of the mx6 */ case MXC_CPU_MX6UL: diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 667115b0..8bd1421 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -19,7 +19,8 @@ #define MXC_CPU_MX6UL 0x64 #define MXC_CPU_MX6ULL 0x65 #define MXC_CPU_MX6SOLO 0x66 /* dummy */ -#define MXC_CPU_MX6D 0x67 +#define MXC_CPU_MX6SLL 0x67 +#define MXC_CPU_MX6D 0x6A #define MXC_CPU_MX6DP 0x68 #define MXC_CPU_MX6QP 0x69 #define MXC_CPU_MX7S 0x71 /* dummy ID */ diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h index 005435a..539d34b 100644 --- a/arch/arm/include/asm/imx-common/sys_proto.h +++ b/arch/arm/include/asm/imx-common/sys_proto.h @@ -36,6 +36,7 @@ #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) +#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) u32 get_nr_cpus(void); u32 get_cpu_rev(void); -- cgit v0.10.2 From 36e40142f4f424575f0bf194097b6c0e0827b582 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:21 +0800 Subject: imx: mx6sll: add pinmux header files Add i.MX6SLL pinmux header files Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h index b9cd670..2934b12 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h @@ -33,6 +33,8 @@ enum { MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), #include "mx6dl_pins.h" }; +#elif defined(CONFIG_MX6SLL) +#include "mx6sll_pins.h" #elif defined(CONFIG_MX6SL) #include "mx6sl_pins.h" #elif defined(CONFIG_MX6SX) diff --git a/arch/arm/include/asm/arch-mx6/mx6sll_pins.h b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h new file mode 100644 index 0000000..1ecb7ce --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h @@ -0,0 +1,1019 @@ +/* + * Copyright (C) 2014 - 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX6SLL_PINS_H__ +#define __ASM_ARCH_IMX6SLL_PINS_H__ + +#include + +enum { + MX6_PAD_WDOG_B__WDOG1_B = IOMUX_PAD(0x02DC, 0x0014, 0, 0x0000, 0, 0), + MX6_PAD_WDOG_B__WDOG1_RESET_B_DEB = IOMUX_PAD(0x02DC, 0x0014, 1, 0x0000, 0, 0), + MX6_PAD_WDOG_B__UART5_RI_B = IOMUX_PAD(0x02DC, 0x0014, 2, 0x0000, 0, 0), + MX6_PAD_WDOG_B__GPIO3_IO18 = IOMUX_PAD(0x02DC, 0x0014, 5, 0x0000, 0, 0), + + MX6_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x02E0, 0x0018, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_24M__I2C3_SCL = IOMUX_PAD(0x02E0, 0x0018, IOMUX_CONFIG_SION | 1, 0x068C, 0, 0), + MX6_PAD_REF_CLK_24M__PWM3_OUT = IOMUX_PAD(0x02E0, 0x0018, 2, 0x0000, 0, 0), + MX6_PAD_REF_CLK_24M__USB_OTG2_ID = IOMUX_PAD(0x02E0, 0x0018, 3, 0x0560, 0, 0), + MX6_PAD_REF_CLK_24M__CCM_PMIC_READY = IOMUX_PAD(0x02E0, 0x0018, 4, 0x05AC, 0, 0), + MX6_PAD_REF_CLK_24M__GPIO3_IO21 = IOMUX_PAD(0x02E0, 0x0018, 5, 0x0000, 0, 0), + MX6_PAD_REF_CLK_24M__SD3_WP = IOMUX_PAD(0x02E0, 0x0018, 6, 0x0794, 0, 0), + + MX6_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x02E4, 0x001C, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__I2C3_SDA = IOMUX_PAD(0x02E4, 0x001C, IOMUX_CONFIG_SION | 1, 0x0690, 0, 0), + MX6_PAD_REF_CLK_32K__PWM4_OUT = IOMUX_PAD(0x02E4, 0x001C, 2, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__USB_OTG1_ID = IOMUX_PAD(0x02E4, 0x001C, 3, 0x055C, 0, 0), + MX6_PAD_REF_CLK_32K__SD1_LCTL = IOMUX_PAD(0x02E4, 0x001C, 4, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__GPIO3_IO22 = IOMUX_PAD(0x02E4, 0x001C, 5, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__SD3_CD_B = IOMUX_PAD(0x02E4, 0x001C, 6, 0x0780, 0, 0), + + MX6_PAD_PWM1__PWM1_OUT = IOMUX_PAD(0x02E8, 0x0020, 0, 0x0000, 0, 0), + MX6_PAD_PWM1__CCM_CLKO = IOMUX_PAD(0x02E8, 0x0020, 1, 0x0000, 0, 0), + MX6_PAD_PWM1__AUDIO_CLK_OUT = IOMUX_PAD(0x02E8, 0x0020, 2, 0x0000, 0, 0), + MX6_PAD_PWM1__CSI_MCLK = IOMUX_PAD(0x02E8, 0x0020, 4, 0x0000, 0, 0), + MX6_PAD_PWM1__GPIO3_IO23 = IOMUX_PAD(0x02E8, 0x0020, 5, 0x0000, 0, 0), + MX6_PAD_PWM1__EPIT1_OUT = IOMUX_PAD(0x02E8, 0x0020, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x02EC, 0x0024, 0, 0x06A0, 0, 0), + MX6_PAD_KEY_COL0__I2C2_SCL = IOMUX_PAD(0x02EC, 0x0024, IOMUX_CONFIG_SION | 1, 0x0684, 0, 0), + MX6_PAD_KEY_COL0__LCD_DATA00 = IOMUX_PAD(0x02EC, 0x0024, 2, 0x06D8, 0, 0), + MX6_PAD_KEY_COL0__SD1_CD_B = IOMUX_PAD(0x02EC, 0x0024, 4, 0x0770, 1, 0), + MX6_PAD_KEY_COL0__GPIO3_IO24 = IOMUX_PAD(0x02EC, 0x0024, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x02F0, 0x0028, 0, 0x06C0, 0, 0), + MX6_PAD_KEY_ROW0__I2C2_SDA = IOMUX_PAD(0x02F0, 0x0028, IOMUX_CONFIG_SION | 1, 0x0688, 0, 0), + MX6_PAD_KEY_ROW0__LCD_DATA01 = IOMUX_PAD(0x02F0, 0x0028, 2, 0x06DC, 0, 0), + MX6_PAD_KEY_ROW0__SD1_WP = IOMUX_PAD(0x02F0, 0x0028, 4, 0x0774, 1, 0), + MX6_PAD_KEY_ROW0__GPIO3_IO25 = IOMUX_PAD(0x02F0, 0x0028, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x02F4, 0x002C, 0, 0x06A4, 0, 0), + MX6_PAD_KEY_COL1__ECSPI4_MOSI = IOMUX_PAD(0x02F4, 0x002C, 1, 0x0658, 1, 0), + MX6_PAD_KEY_COL1__LCD_DATA02 = IOMUX_PAD(0x02F4, 0x002C, 2, 0x06E0, 0, 0), + MX6_PAD_KEY_COL1__SD3_DATA4 = IOMUX_PAD(0x02F4, 0x002C, 4, 0x0784, 0, 0), + MX6_PAD_KEY_COL1__GPIO3_IO26 = IOMUX_PAD(0x02F4, 0x002C, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x02F8, 0x0030, 0, 0x06C4, 0, 0), + MX6_PAD_KEY_ROW1__ECSPI4_MISO = IOMUX_PAD(0x02F8, 0x0030, 1, 0x0654, 1, 0), + MX6_PAD_KEY_ROW1__LCD_DATA03 = IOMUX_PAD(0x02F8, 0x0030, 2, 0x06E4, 0, 0), + MX6_PAD_KEY_ROW1__CSI_FIELD = IOMUX_PAD(0x02F8, 0x0030, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__SD3_DATA5 = IOMUX_PAD(0x02F8, 0x0030, 4, 0x0788, 0, 0), + MX6_PAD_KEY_ROW1__GPIO3_IO27 = IOMUX_PAD(0x02F8, 0x0030, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x02FC, 0x0034, 0, 0x06A8, 0, 0), + MX6_PAD_KEY_COL2__ECSPI4_SS0 = IOMUX_PAD(0x02FC, 0x0034, 1, 0x065C, 1, 0), + MX6_PAD_KEY_COL2__LCD_DATA04 = IOMUX_PAD(0x02FC, 0x0034, 2, 0x06E8, 0, 0), + MX6_PAD_KEY_COL2__CSI_DATA12 = IOMUX_PAD(0x02FC, 0x0034, 3, 0x05B8, 1, 0), + MX6_PAD_KEY_COL2__SD3_DATA6 = IOMUX_PAD(0x02FC, 0x0034, 4, 0x078C, 0, 0), + MX6_PAD_KEY_COL2__GPIO3_IO28 = IOMUX_PAD(0x02FC, 0x0034, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x0300, 0x0038, 0, 0x06C8, 0, 0), + MX6_PAD_KEY_ROW2__ECSPI4_SCLK = IOMUX_PAD(0x0300, 0x0038, 1, 0x0650, 1, 0), + MX6_PAD_KEY_ROW2__LCD_DATA05 = IOMUX_PAD(0x0300, 0x0038, 2, 0x06EC, 0, 0), + MX6_PAD_KEY_ROW2__CSI_DATA13 = IOMUX_PAD(0x0300, 0x0038, 3, 0x05BC, 1, 0), + MX6_PAD_KEY_ROW2__SD3_DATA7 = IOMUX_PAD(0x0300, 0x0038, 4, 0x0790, 0, 0), + MX6_PAD_KEY_ROW2__GPIO3_IO29 = IOMUX_PAD(0x0300, 0x0038, 5, 0x0000, 0, 0), + + MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x0304, 0x003C, 0, 0x06AC, 0, 0), + MX6_PAD_KEY_COL3__AUD6_RXFS = IOMUX_PAD(0x0304, 0x003C, 1, 0x05A0, 1, 0), + MX6_PAD_KEY_COL3__LCD_DATA06 = IOMUX_PAD(0x0304, 0x003C, 2, 0x06F0, 0, 0), + MX6_PAD_KEY_COL3__CSI_DATA14 = IOMUX_PAD(0x0304, 0x003C, 3, 0x05C0, 1, 0), + MX6_PAD_KEY_COL3__GPIO3_IO30 = IOMUX_PAD(0x0304, 0x003C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__SD1_RESET = IOMUX_PAD(0x0304, 0x003C, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x0308, 0x0040, 0, 0x06CC, 1, 0), + MX6_PAD_KEY_ROW3__AUD6_RXC = IOMUX_PAD(0x0308, 0x0040, 1, 0x059C, 1, 0), + MX6_PAD_KEY_ROW3__LCD_DATA07 = IOMUX_PAD(0x0308, 0x0040, 2, 0x06F4, 1, 0), + MX6_PAD_KEY_ROW3__CSI_DATA15 = IOMUX_PAD(0x0308, 0x0040, 3, 0x05C4, 2, 0), + MX6_PAD_KEY_ROW3__GPIO3_IO31 = IOMUX_PAD(0x0308, 0x0040, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x0308, 0x0040, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x030C, 0x0044, 0, 0x06B0, 1, 0), + MX6_PAD_KEY_COL4__AUD6_RXD = IOMUX_PAD(0x030C, 0x0044, 1, 0x0594, 1, 0), + MX6_PAD_KEY_COL4__LCD_DATA08 = IOMUX_PAD(0x030C, 0x0044, 2, 0x06F8, 1, 0), + MX6_PAD_KEY_COL4__CSI_DATA16 = IOMUX_PAD(0x030C, 0x0044, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__GPIO4_IO00 = IOMUX_PAD(0x030C, 0x0044, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__USB_OTG1_PWR = IOMUX_PAD(0x030C, 0x0044, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x0310, 0x0048, 0, 0x06D0, 1, 0), + MX6_PAD_KEY_ROW4__AUD6_TXC = IOMUX_PAD(0x0310, 0x0048, 1, 0x05A4, 1, 0), + MX6_PAD_KEY_ROW4__LCD_DATA09 = IOMUX_PAD(0x0310, 0x0048, 2, 0x06FC, 1, 0), + MX6_PAD_KEY_ROW4__CSI_DATA17 = IOMUX_PAD(0x0310, 0x0048, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__GPIO4_IO01 = IOMUX_PAD(0x0310, 0x0048, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USB_OTG1_OC = IOMUX_PAD(0x0310, 0x0048, 6, 0x076C, 2, 0), + + MX6_PAD_KEY_COL5__KEY_COL5 = IOMUX_PAD(0x0314, 0x004C, 0, 0x0694, 1, 0), + MX6_PAD_KEY_COL5__AUD6_TXFS = IOMUX_PAD(0x0314, 0x004C, 1, 0x05A8, 1, 0), + MX6_PAD_KEY_COL5__LCD_DATA10 = IOMUX_PAD(0x0314, 0x004C, 2, 0x0700, 0, 0), + MX6_PAD_KEY_COL5__CSI_DATA18 = IOMUX_PAD(0x0314, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__GPIO4_IO02 = IOMUX_PAD(0x0314, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__USB_OTG2_PWR = IOMUX_PAD(0x0314, 0x004C, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW5__KEY_ROW5 = IOMUX_PAD(0x0318, 0x0050, 0, 0x06B4, 2, 0), + MX6_PAD_KEY_ROW5__AUD6_TXD = IOMUX_PAD(0x0318, 0x0050, 1, 0x0598, 1, 0), + MX6_PAD_KEY_ROW5__LCD_DATA11 = IOMUX_PAD(0x0318, 0x0050, 2, 0x0704, 1, 0), + MX6_PAD_KEY_ROW5__CSI_DATA19 = IOMUX_PAD(0x0318, 0x0050, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW5__GPIO4_IO03 = IOMUX_PAD(0x0318, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW5__USB_OTG2_OC = IOMUX_PAD(0x0318, 0x0050, 6, 0x0768, 3, 0), + + MX6_PAD_KEY_COL6__KEY_COL6 = IOMUX_PAD(0x031C, 0x0054, 0, 0x0698, 2, 0), + MX6_PAD_KEY_COL6__UART4_DCE_RX = IOMUX_PAD(0x031C, 0x0054, 1, 0x075C, 2, 0), + MX6_PAD_KEY_COL6__UART4_DTE_TX = IOMUX_PAD(0x031C, 0x0054, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__LCD_DATA12 = IOMUX_PAD(0x031C, 0x0054, 2, 0x0708, 1, 0), + MX6_PAD_KEY_COL6__CSI_DATA20 = IOMUX_PAD(0x031C, 0x0054, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__GPIO4_IO04 = IOMUX_PAD(0x031C, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__SD3_RESET = IOMUX_PAD(0x031C, 0x0054, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_ROW6__KEY_ROW6 = IOMUX_PAD(0x0320, 0x0058, 0, 0x06B8, 2, 0), + MX6_PAD_KEY_ROW6__UART4_DCE_TX = IOMUX_PAD(0x0320, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__UART4_DTE_RX = IOMUX_PAD(0x0320, 0x0058, 1, 0x075C, 3, 0), + MX6_PAD_KEY_ROW6__LCD_DATA13 = IOMUX_PAD(0x0320, 0x0058, 2, 0x070C, 1, 0), + MX6_PAD_KEY_ROW6__CSI_DATA21 = IOMUX_PAD(0x0320, 0x0058, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__GPIO4_IO05 = IOMUX_PAD(0x0320, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__SD3_VSELECT = IOMUX_PAD(0x0320, 0x0058, 6, 0x0000, 0, 0), + + MX6_PAD_KEY_COL7__KEY_COL7 = IOMUX_PAD(0x0324, 0x005C, 0, 0x069C, 2, 0), + MX6_PAD_KEY_COL7__UART4_DCE_RTS = IOMUX_PAD(0x0324, 0x005C, 1, 0x0758, 2, 0), + MX6_PAD_KEY_COL7__UART4_DTE_CTS = IOMUX_PAD(0x0324, 0x005C, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL7__LCD_DATA14 = IOMUX_PAD(0x0324, 0x005C, 2, 0x0710, 1, 0), + MX6_PAD_KEY_COL7__CSI_DATA22 = IOMUX_PAD(0x0324, 0x005C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL7__GPIO4_IO06 = IOMUX_PAD(0x0324, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL7__SD1_WP = IOMUX_PAD(0x0324, 0x005C, 6, 0x0774, 3, 0), + + MX6_PAD_KEY_ROW7__KEY_ROW7 = IOMUX_PAD(0x0328, 0x0060, 0, 0x06BC, 2, 0), + MX6_PAD_KEY_ROW7__UART4_DCE_CTS = IOMUX_PAD(0x0328, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__UART4_DTE_RTS = IOMUX_PAD(0x0328, 0x0060, 1, 0x0758, 3, 0), + MX6_PAD_KEY_ROW7__LCD_DATA15 = IOMUX_PAD(0x0328, 0x0060, 2, 0x0714, 1, 0), + MX6_PAD_KEY_ROW7__CSI_DATA23 = IOMUX_PAD(0x0328, 0x0060, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__GPIO4_IO07 = IOMUX_PAD(0x0328, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__SD1_CD_B = IOMUX_PAD(0x0328, 0x0060, 6, 0x0770, 3, 0), + + MX6_PAD_EPDC_DATA00__EPDC_DATA00 = IOMUX_PAD(0x032C, 0x0064, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA00__ECSPI4_MOSI = IOMUX_PAD(0x032C, 0x0064, 1, 0x0658, 2, 0), + MX6_PAD_EPDC_DATA00__LCD_DATA24 = IOMUX_PAD(0x032C, 0x0064, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA00__CSI_DATA00 = IOMUX_PAD(0x032C, 0x0064, 3, 0x05C8, 2, 0), + MX6_PAD_EPDC_DATA00__GPIO1_IO07 = IOMUX_PAD(0x032C, 0x0064, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA01__EPDC_DATA01 = IOMUX_PAD(0x0330, 0x0068, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA01__ECSPI4_MISO = IOMUX_PAD(0x0330, 0x0068, 1, 0x0654, 2, 0), + MX6_PAD_EPDC_DATA01__LCD_DATA25 = IOMUX_PAD(0x0330, 0x0068, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA01__CSI_DATA01 = IOMUX_PAD(0x0330, 0x0068, 3, 0x05CC, 2, 0), + MX6_PAD_EPDC_DATA01__GPIO1_IO08 = IOMUX_PAD(0x0330, 0x0068, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA02__EPDC_DATA02 = IOMUX_PAD(0x0334, 0x006C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA02__ECSPI4_SS0 = IOMUX_PAD(0x0334, 0x006C, 1, 0x065C, 2, 0), + MX6_PAD_EPDC_DATA02__LCD_DATA26 = IOMUX_PAD(0x0334, 0x006C, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA02__CSI_DATA02 = IOMUX_PAD(0x0334, 0x006C, 3, 0x05D0, 2, 0), + MX6_PAD_EPDC_DATA02__GPIO1_IO09 = IOMUX_PAD(0x0334, 0x006C, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA03__EPDC_DATA03 = IOMUX_PAD(0x0338, 0x0070, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA03__ECSPI4_SCLK = IOMUX_PAD(0x0338, 0x0070, 1, 0x0650, 2, 0), + MX6_PAD_EPDC_DATA03__LCD_DATA27 = IOMUX_PAD(0x0338, 0x0070, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA03__CSI_DATA03 = IOMUX_PAD(0x0338, 0x0070, 3, 0x05D4, 2, 0), + MX6_PAD_EPDC_DATA03__GPIO1_IO10 = IOMUX_PAD(0x0338, 0x0070, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA04__EPDC_DATA04 = IOMUX_PAD(0x033C, 0x0074, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA04__ECSPI4_SS1 = IOMUX_PAD(0x033C, 0x0074, 1, 0x0660, 1, 0), + MX6_PAD_EPDC_DATA04__LCD_DATA28 = IOMUX_PAD(0x033C, 0x0074, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA04__CSI_DATA04 = IOMUX_PAD(0x033C, 0x0074, 3, 0x05D8, 2, 0), + MX6_PAD_EPDC_DATA04__GPIO1_IO11 = IOMUX_PAD(0x033C, 0x0074, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA05__EPDC_DATA05 = IOMUX_PAD(0x0340, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA05__ECSPI4_SS2 = IOMUX_PAD(0x0340, 0x0078, 1, 0x0664, 1, 0), + MX6_PAD_EPDC_DATA05__LCD_DATA29 = IOMUX_PAD(0x0340, 0x0078, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA05__CSI_DATA05 = IOMUX_PAD(0x0340, 0x0078, 3, 0x05DC, 2, 0), + MX6_PAD_EPDC_DATA05__GPIO1_IO12 = IOMUX_PAD(0x0340, 0x0078, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA06__EPDC_DATA06 = IOMUX_PAD(0x0344, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA06__ECSPI4_SS3 = IOMUX_PAD(0x0344, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA06__LCD_DATA30 = IOMUX_PAD(0x0344, 0x007C, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA06__CSI_DATA06 = IOMUX_PAD(0x0344, 0x007C, 3, 0x05E0, 2, 0), + MX6_PAD_EPDC_DATA06__GPIO1_IO13 = IOMUX_PAD(0x0344, 0x007C, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA07__EPDC_DATA07 = IOMUX_PAD(0x0348, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA07__ECSPI4_RDY = IOMUX_PAD(0x0348, 0x0080, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA07__LCD_DATA31 = IOMUX_PAD(0x0348, 0x0080, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA07__CSI_DATA07 = IOMUX_PAD(0x0348, 0x0080, 3, 0x05E4, 2, 0), + MX6_PAD_EPDC_DATA07__GPIO1_IO14 = IOMUX_PAD(0x0348, 0x0080, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA08__EPDC_DATA08 = IOMUX_PAD(0x034C, 0x0084, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA08__ECSPI3_MOSI = IOMUX_PAD(0x034C, 0x0084, 1, 0x063C, 2, 0), + MX6_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 = IOMUX_PAD(0x034C, 0x0084, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA08__GPIO1_IO15 = IOMUX_PAD(0x034C, 0x0084, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA09__EPDC_DATA09 = IOMUX_PAD(0x0350, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA09__ECSPI3_MISO = IOMUX_PAD(0x0350, 0x0088, 1, 0x0638, 2, 0), + MX6_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 = IOMUX_PAD(0x0350, 0x0088, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA09__GPIO1_IO16 = IOMUX_PAD(0x0350, 0x0088, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x0354, 0x008C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA10__ECSPI3_SS0 = IOMUX_PAD(0x0354, 0x008C, 1, 0x0648, 2, 0), + MX6_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 = IOMUX_PAD(0x0354, 0x008C, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA10__GPIO1_IO17 = IOMUX_PAD(0x0354, 0x008C, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x0358, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA11__ECSPI3_SCLK = IOMUX_PAD(0x0358, 0x0090, 1, 0x0630, 2, 0), + MX6_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 = IOMUX_PAD(0x0358, 0x0090, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA11__GPIO1_IO18 = IOMUX_PAD(0x0358, 0x0090, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x035C, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA12__UART2_DCE_RX = IOMUX_PAD(0x035C, 0x0094, 1, 0x074C, 4, 0), + MX6_PAD_EPDC_DATA12__UART2_DTE_TX = IOMUX_PAD(0x035C, 0x0094, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA12__EPDC_PWR_COM = IOMUX_PAD(0x035C, 0x0094, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA12__GPIO1_IO19 = IOMUX_PAD(0x035C, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA12__ECSPI3_SS1 = IOMUX_PAD(0x035C, 0x0094, 6, 0x064C, 1, 0), + + MX6_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x0360, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA13__UART2_DCE_TX = IOMUX_PAD(0x0360, 0x0098, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA13__UART2_DTE_RX = IOMUX_PAD(0x0360, 0x0098, 1, 0x074C, 5, 0), + MX6_PAD_EPDC_DATA13__EPDC_PWR_IRQ = IOMUX_PAD(0x0360, 0x0098, 2, 0x0668, 0, 0), + MX6_PAD_EPDC_DATA13__GPIO1_IO20 = IOMUX_PAD(0x0360, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA13__ECSPI3_SS2 = IOMUX_PAD(0x0360, 0x0098, 6, 0x0640, 1, 0), + + MX6_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x0364, 0x009C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA14__UART2_DCE_RTS = IOMUX_PAD(0x0364, 0x009C, 1, 0x0748, 4, 0), + MX6_PAD_EPDC_DATA14__UART2_DTE_CTS = IOMUX_PAD(0x0364, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA14__EPDC_PWR_STAT = IOMUX_PAD(0x0364, 0x009C, 2, 0x066C, 0, 0), + MX6_PAD_EPDC_DATA14__GPIO1_IO21 = IOMUX_PAD(0x0364, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA14__ECSPI3_SS3 = IOMUX_PAD(0x0364, 0x009C, 6, 0x0644, 1, 0), + + MX6_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x0368, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA15__UART2_DCE_CTS = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA15__UART2_DTE_RTS = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0748, 5, 0), + MX6_PAD_EPDC_DATA15__EPDC_PWR_WAKE = IOMUX_PAD(0x0368, 0x00A0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA15__GPIO1_IO22 = IOMUX_PAD(0x0368, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_DATA15__ECSPI3_RDY = IOMUX_PAD(0x0368, 0x00A0, 6, 0x0634, 1, 0), + + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P = IOMUX_PAD(0x036C, 0x00A4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__ECSPI2_MOSI = IOMUX_PAD(0x036C, 0x00A4, 1, 0x0624, 2, 0), + MX6_PAD_EPDC_SDCLK__I2C2_SCL = IOMUX_PAD(0x036C, 0x00A4, IOMUX_CONFIG_SION | 2, 0x0684, 2, 0), + MX6_PAD_EPDC_SDCLK__CSI_DATA08 = IOMUX_PAD(0x036C, 0x00A4, 3, 0x05E8, 2, 0), + MX6_PAD_EPDC_SDCLK__GPIO1_IO23 = IOMUX_PAD(0x036C, 0x00A4, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x0370, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__ECSPI2_MISO = IOMUX_PAD(0x0370, 0x00A8, 1, 0x0620, 2, 0), + MX6_PAD_EPDC_SDLE__I2C2_SDA = IOMUX_PAD(0x0370, 0x00A8, IOMUX_CONFIG_SION | 2, 0x0688, 2, 0), + MX6_PAD_EPDC_SDLE__CSI_DATA09 = IOMUX_PAD(0x0370, 0x00A8, 3, 0x05EC, 2, 0), + MX6_PAD_EPDC_SDLE__GPIO1_IO24 = IOMUX_PAD(0x0370, 0x00A8, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x0374, 0x00AC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__ECSPI2_SS0 = IOMUX_PAD(0x0374, 0x00AC, 1, 0x0628, 1, 0), + MX6_PAD_EPDC_SDOE__CSI_DATA10 = IOMUX_PAD(0x0374, 0x00AC, 3, 0x05B0, 2, 0), + MX6_PAD_EPDC_SDOE__GPIO1_IO25 = IOMUX_PAD(0x0374, 0x00AC, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x0378, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__ECSPI2_SCLK = IOMUX_PAD(0x0378, 0x00B0, 1, 0x061C, 2, 0), + MX6_PAD_EPDC_SDSHR__EPDC_SDCE4 = IOMUX_PAD(0x0378, 0x00B0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__CSI_DATA11 = IOMUX_PAD(0x0378, 0x00B0, 3, 0x05B4, 2, 0), + MX6_PAD_EPDC_SDSHR__GPIO1_IO26 = IOMUX_PAD(0x0378, 0x00B0, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x037C, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__ECSPI2_SS1 = IOMUX_PAD(0x037C, 0x00B4, 1, 0x062C, 1, 0), + MX6_PAD_EPDC_SDCE0__PWM3_OUT = IOMUX_PAD(0x037C, 0x00B4, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__GPIO1_IO27 = IOMUX_PAD(0x037C, 0x00B4, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x0380, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__WDOG2_B = IOMUX_PAD(0x0380, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__PWM4_OUT = IOMUX_PAD(0x0380, 0x00B8, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__GPIO1_IO28 = IOMUX_PAD(0x0380, 0x00B8, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x0384, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__I2C3_SCL = IOMUX_PAD(0x0384, 0x00BC, IOMUX_CONFIG_SION | 1, 0x068C, 2, 0), + MX6_PAD_EPDC_SDCE2__PWM1_OUT = IOMUX_PAD(0x0384, 0x00BC, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__GPIO1_IO29 = IOMUX_PAD(0x0384, 0x00BC, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0388, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__I2C3_SDA = IOMUX_PAD(0x0388, 0x00C0, IOMUX_CONFIG_SION | 1, 0x0690, 2, 0), + MX6_PAD_EPDC_SDCE3__PWM2_OUT = IOMUX_PAD(0x0388, 0x00C0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__GPIO1_IO30 = IOMUX_PAD(0x0388, 0x00C0, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x038C, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__ECSPI2_SS2 = IOMUX_PAD(0x038C, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__CSI_PIXCLK = IOMUX_PAD(0x038C, 0x00C4, 3, 0x05F4, 2, 0), + MX6_PAD_EPDC_GDCLK__GPIO1_IO31 = IOMUX_PAD(0x038C, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__SD2_RESET = IOMUX_PAD(0x038C, 0x00C4, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0390, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__ECSPI2_SS3 = IOMUX_PAD(0x0390, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__CSI_HSYNC = IOMUX_PAD(0x0390, 0x00C8, 3, 0x05F0, 2, 0), + MX6_PAD_EPDC_GDOE__GPIO2_IO00 = IOMUX_PAD(0x0390, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__SD2_VSELECT = IOMUX_PAD(0x0390, 0x00C8, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x0394, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__CSI_MCLK = IOMUX_PAD(0x0394, 0x00CC, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__GPIO2_IO01 = IOMUX_PAD(0x0394, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__SD2_WP = IOMUX_PAD(0x0394, 0x00CC, 6, 0x077C, 2, 0), + + MX6_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0398, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__PWM4_OUT = IOMUX_PAD(0x0398, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__CSI_VSYNC = IOMUX_PAD(0x0398, 0x00D0, 3, 0x05F8, 2, 0), + MX6_PAD_EPDC_GDSP__GPIO2_IO02 = IOMUX_PAD(0x0398, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__SD2_CD_B = IOMUX_PAD(0x0398, 0x00D0, 6, 0x0778, 2, 0), + + MX6_PAD_EPDC_VCOM0__EPDC_VCOM0 = IOMUX_PAD(0x039C, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__AUD5_RXFS = IOMUX_PAD(0x039C, 0x00D4, 1, 0x0588, 1, 0), + MX6_PAD_EPDC_VCOM0__UART3_DCE_RX = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0754, 4, 0), + MX6_PAD_EPDC_VCOM0__UART3_DTE_TX = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__GPIO2_IO03 = IOMUX_PAD(0x039C, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__EPDC_SDCE5 = IOMUX_PAD(0x039C, 0x00D4, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_VCOM1__EPDC_VCOM1 = IOMUX_PAD(0x03A0, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__AUD5_RXD = IOMUX_PAD(0x03A0, 0x00D8, 1, 0x057C, 1, 0), + MX6_PAD_EPDC_VCOM1__UART3_DCE_TX = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__UART3_DTE_RX = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0754, 5, 0), + MX6_PAD_EPDC_VCOM1__GPIO2_IO04 = IOMUX_PAD(0x03A0, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__EPDC_SDCE6 = IOMUX_PAD(0x03A0, 0x00D8, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x03A4, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__UART3_DCE_RTS = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0750, 2, 0), + MX6_PAD_EPDC_BDR0__UART3_DTE_CTS = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__GPIO2_IO05 = IOMUX_PAD(0x03A4, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__EPDC_SDCE7 = IOMUX_PAD(0x03A4, 0x00DC, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x03A8, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__UART3_DCE_CTS = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__UART3_DTE_RTS = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0750, 3, 0), + MX6_PAD_EPDC_BDR1__GPIO2_IO06 = IOMUX_PAD(0x03A8, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__EPDC_SDCE8 = IOMUX_PAD(0x03A8, 0x00E0, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03AC, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_CTRL0__AUD5_RXC = IOMUX_PAD(0x03AC, 0x00E4, 1, 0x0584, 1, 0), + MX6_PAD_EPDC_PWR_CTRL0__LCD_DATA16 = IOMUX_PAD(0x03AC, 0x00E4, 2, 0x0718, 1, 0), + MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 = IOMUX_PAD(0x03AC, 0x00E4, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03B0, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_CTRL1__AUD5_TXFS = IOMUX_PAD(0x03B0, 0x00E8, 1, 0x0590, 1, 0), + MX6_PAD_EPDC_PWR_CTRL1__LCD_DATA17 = IOMUX_PAD(0x03B0, 0x00E8, 2, 0x071C, 1, 0), + MX6_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 = IOMUX_PAD(0x03B0, 0x00E8, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03B4, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_CTRL2__AUD5_TXD = IOMUX_PAD(0x03B4, 0x00EC, 1, 0x0580, 1, 0), + MX6_PAD_EPDC_PWR_CTRL2__LCD_DATA18 = IOMUX_PAD(0x03B4, 0x00EC, 2, 0x0720, 1, 0), + MX6_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 = IOMUX_PAD(0x03B4, 0x00EC, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03B8, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_CTRL3__AUD5_TXC = IOMUX_PAD(0x03B8, 0x00F0, 1, 0x058C, 1, 0), + MX6_PAD_EPDC_PWR_CTRL3__LCD_DATA19 = IOMUX_PAD(0x03B8, 0x00F0, 2, 0x0724, 1, 0), + MX6_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 = IOMUX_PAD(0x03B8, 0x00F0, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x03BC, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_COM__LCD_DATA20 = IOMUX_PAD(0x03BC, 0x00F4, 2, 0x0728, 1, 0), + MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID = IOMUX_PAD(0x03BC, 0x00F4, 4, 0x055C, 4, 0), + MX6_PAD_EPDC_PWR_COM__GPIO2_IO11 = IOMUX_PAD(0x03BC, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_COM__SD3_RESET = IOMUX_PAD(0x03BC, 0x00F4, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ = IOMUX_PAD(0x03C0, 0x00F8, 0, 0x0668, 1, 0), + MX6_PAD_EPDC_PWR_IRQ__LCD_DATA21 = IOMUX_PAD(0x03C0, 0x00F8, 2, 0x072C, 1, 0), + MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID = IOMUX_PAD(0x03C0, 0x00F8, 4, 0x0560, 3, 0), + MX6_PAD_EPDC_PWR_IRQ__GPIO2_IO12 = IOMUX_PAD(0x03C0, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_IRQ__SD3_VSELECT = IOMUX_PAD(0x03C0, 0x00F8, 6, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x03C4, 0x00FC, 0, 0x066C, 1, 0), + MX6_PAD_EPDC_PWR_STAT__LCD_DATA22 = IOMUX_PAD(0x03C4, 0x00FC, 2, 0x0730, 1, 0), + MX6_PAD_EPDC_PWR_STAT__ARM_EVENTI = IOMUX_PAD(0x03C4, 0x00FC, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 = IOMUX_PAD(0x03C4, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_STAT__SD3_WP = IOMUX_PAD(0x03C4, 0x00FC, 6, 0x0794, 2, 0), + + MX6_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE = IOMUX_PAD(0x03C8, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_WAKE__LCD_DATA23 = IOMUX_PAD(0x03C8, 0x0100, 2, 0x0734, 1, 0), + MX6_PAD_EPDC_PWR_WAKE__ARM_EVENTO = IOMUX_PAD(0x03C8, 0x0100, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 = IOMUX_PAD(0x03C8, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWR_WAKE__SD3_CD_B = IOMUX_PAD(0x03C8, 0x0100, 6, 0x0780, 2, 0), + + MX6_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x03CC, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__LCD_WR_RWN = IOMUX_PAD(0x03CC, 0x0104, 2, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__PWM4_OUT = IOMUX_PAD(0x03CC, 0x0104, 4, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__GPIO2_IO15 = IOMUX_PAD(0x03CC, 0x0104, 5, 0x0000, 0, 0), + + MX6_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x03D0, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__LCD_RD_E = IOMUX_PAD(0x03D0, 0x0108, 2, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART2_DCE_RX = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART2_DTE_TX = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__GPIO2_IO16 = IOMUX_PAD(0x03D0, 0x0108, 5, 0x0000, 0, 0), + + MX6_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x03D4, 0x010C, 0, 0x06D4, 0, 0), + MX6_PAD_LCD_HSYNC__LCD_CS = IOMUX_PAD(0x03D4, 0x010C, 2, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART2_DCE_TX = IOMUX_PAD(0x03D4, 0x010C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART2_DTE_RX = IOMUX_PAD(0x03D4, 0x010C, 4, 0x074C, 1, 0), + MX6_PAD_LCD_HSYNC__GPIO2_IO17 = IOMUX_PAD(0x03D4, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__ARM_TRACE_CLK = IOMUX_PAD(0x03D4, 0x010C, 6, 0x0000, 0, 0), + + MX6_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x03D8, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__LCD_RS = IOMUX_PAD(0x03D8, 0x0110, 2, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__UART2_DCE_RTS = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0748, 0, 0), + MX6_PAD_LCD_VSYNC__UART2_DTE_CTS = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__GPIO2_IO18 = IOMUX_PAD(0x03D8, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__ARM_TRACE_CTL = IOMUX_PAD(0x03D8, 0x0110, 6, 0x0000, 0, 0), + + MX6_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x03DC, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__LCD_BUSY = IOMUX_PAD(0x03DC, 0x0114, 2, 0x06D4, 1, 0), + MX6_PAD_LCD_RESET__UART2_DCE_CTS = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__UART2_DTE_RTS = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0748, 1, 0), + MX6_PAD_LCD_RESET__GPIO2_IO19 = IOMUX_PAD(0x03DC, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__CCM_PMIC_READY = IOMUX_PAD(0x03DC, 0x0114, 6, 0x05AC, 2, 0), + + MX6_PAD_LCD_DATA00__LCD_DATA00 = IOMUX_PAD(0x03E0, 0x0118, 0, 0x06D8, 1, 0), + MX6_PAD_LCD_DATA00__ECSPI1_MOSI = IOMUX_PAD(0x03E0, 0x0118, 1, 0x0608, 0, 0), + MX6_PAD_LCD_DATA00__USB_OTG2_ID = IOMUX_PAD(0x03E0, 0x0118, 2, 0x0560, 2, 0), + MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03E0, 0x0118, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__UART5_DTR_B = IOMUX_PAD(0x03E0, 0x0118, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__GPIO2_IO20 = IOMUX_PAD(0x03E0, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__ARM_TRACE00 = IOMUX_PAD(0x03E0, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SRC_BOOT_CFG00 = IOMUX_PAD(0x03E0, 0x0118, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA01__LCD_DATA01 = IOMUX_PAD(0x03E4, 0x011C, 0, 0x06DC, 1, 0), + MX6_PAD_LCD_DATA01__ECSPI1_MISO = IOMUX_PAD(0x03E4, 0x011C, 1, 0x0604, 0, 0), + MX6_PAD_LCD_DATA01__USB_OTG1_ID = IOMUX_PAD(0x03E4, 0x011C, 2, 0x055C, 3, 0), + MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03E4, 0x011C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__AUD4_RXFS = IOMUX_PAD(0x03E4, 0x011C, 4, 0x0570, 0, 0), + MX6_PAD_LCD_DATA01__GPIO2_IO21 = IOMUX_PAD(0x03E4, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__ARM_TRACE01 = IOMUX_PAD(0x03E4, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SRC_BOOT_CFG01 = IOMUX_PAD(0x03E4, 0x011C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA02__LCD_DATA02 = IOMUX_PAD(0x03E8, 0x0120, 0, 0x06E0, 1, 0), + MX6_PAD_LCD_DATA02__ECSPI1_SS0 = IOMUX_PAD(0x03E8, 0x0120, 1, 0x0614, 0, 0), + MX6_PAD_LCD_DATA02__EPIT2_OUT = IOMUX_PAD(0x03E8, 0x0120, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03E8, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__AUD4_RXC = IOMUX_PAD(0x03E8, 0x0120, 4, 0x056C, 0, 0), + MX6_PAD_LCD_DATA02__GPIO2_IO22 = IOMUX_PAD(0x03E8, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__ARM_TRACE02 = IOMUX_PAD(0x03E8, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SRC_BOOT_CFG02 = IOMUX_PAD(0x03E8, 0x0120, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA03__LCD_DATA03 = IOMUX_PAD(0x03EC, 0x0124, 0, 0x06E4, 1, 0), + MX6_PAD_LCD_DATA03__ECSPI1_SCLK = IOMUX_PAD(0x03EC, 0x0124, 1, 0x05FC, 0, 0), + MX6_PAD_LCD_DATA03__UART5_DSR_B = IOMUX_PAD(0x03EC, 0x0124, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03EC, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__AUD4_RXD = IOMUX_PAD(0x03EC, 0x0124, 4, 0x0564, 0, 0), + MX6_PAD_LCD_DATA03__GPIO2_IO23 = IOMUX_PAD(0x03EC, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__ARM_TRACE03 = IOMUX_PAD(0x03EC, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SRC_BOOT_CFG03 = IOMUX_PAD(0x03EC, 0x0124, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA04__LCD_DATA04 = IOMUX_PAD(0x03F0, 0x0128, 0, 0x06E8, 1, 0), + MX6_PAD_LCD_DATA04__ECSPI1_SS1 = IOMUX_PAD(0x03F0, 0x0128, 1, 0x060C, 1, 0), + MX6_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x03F0, 0x0128, 2, 0x05F8, 0, 0), + MX6_PAD_LCD_DATA04__WDOG2_RESET_B_DEB = IOMUX_PAD(0x03F0, 0x0128, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__AUD4_TXC = IOMUX_PAD(0x03F0, 0x0128, 4, 0x0574, 0, 0), + MX6_PAD_LCD_DATA04__GPIO2_IO24 = IOMUX_PAD(0x03F0, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__ARM_TRACE04 = IOMUX_PAD(0x03F0, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SRC_BOOT_CFG04 = IOMUX_PAD(0x03F0, 0x0128, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA05__LCD_DATA05 = IOMUX_PAD(0x03F4, 0x012C, 0, 0x06EC, 1, 0), + MX6_PAD_LCD_DATA05__ECSPI1_SS2 = IOMUX_PAD(0x03F4, 0x012C, 1, 0x0610, 1, 0), + MX6_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x03F4, 0x012C, 2, 0x05F0, 0, 0), + MX6_PAD_LCD_DATA05__AUD4_TXFS = IOMUX_PAD(0x03F4, 0x012C, 4, 0x0578, 0, 0), + MX6_PAD_LCD_DATA05__GPIO2_IO25 = IOMUX_PAD(0x03F4, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ARM_TRACE05 = IOMUX_PAD(0x03F4, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SRC_BOOT_CFG05 = IOMUX_PAD(0x03F4, 0x012C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA06__LCD_DATA06 = IOMUX_PAD(0x03F8, 0x0130, 0, 0x06F0, 1, 0), + MX6_PAD_LCD_DATA06__ECSPI1_SS3 = IOMUX_PAD(0x03F8, 0x0130, 1, 0x0618, 0, 0), + MX6_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x03F8, 0x0130, 2, 0x05F4, 0, 0), + MX6_PAD_LCD_DATA06__AUD4_TXD = IOMUX_PAD(0x03F8, 0x0130, 4, 0x0568, 0, 0), + MX6_PAD_LCD_DATA06__GPIO2_IO26 = IOMUX_PAD(0x03F8, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__ARM_TRACE06 = IOMUX_PAD(0x03F8, 0x0130, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SRC_BOOT_CFG06 = IOMUX_PAD(0x03F8, 0x0130, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA07__LCD_DATA07 = IOMUX_PAD(0x03FC, 0x0134, 0, 0x06F4, 0, 0), + MX6_PAD_LCD_DATA07__ECSPI1_RDY = IOMUX_PAD(0x03FC, 0x0134, 1, 0x0600, 0, 0), + MX6_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x03FC, 0x0134, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__AUDIO_CLK_OUT = IOMUX_PAD(0x03FC, 0x0134, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__GPIO2_IO27 = IOMUX_PAD(0x03FC, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ARM_TRACE07 = IOMUX_PAD(0x03FC, 0x0134, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SRC_BOOT_CFG07 = IOMUX_PAD(0x03FC, 0x0134, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA08__LCD_DATA08 = IOMUX_PAD(0x0400, 0x0138, 0, 0x06F8, 0, 0), + MX6_PAD_LCD_DATA08__KEY_COL0 = IOMUX_PAD(0x0400, 0x0138, 1, 0x06A0, 1, 0), + MX6_PAD_LCD_DATA08__CSI_DATA09 = IOMUX_PAD(0x0400, 0x0138, 2, 0x05EC, 0, 0), + MX6_PAD_LCD_DATA08__ECSPI2_SCLK = IOMUX_PAD(0x0400, 0x0138, 4, 0x061C, 0, 0), + MX6_PAD_LCD_DATA08__GPIO2_IO28 = IOMUX_PAD(0x0400, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__ARM_TRACE08 = IOMUX_PAD(0x0400, 0x0138, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SRC_BOOT_CFG08 = IOMUX_PAD(0x0400, 0x0138, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA09__LCD_DATA09 = IOMUX_PAD(0x0404, 0x013C, 0, 0x06FC, 0, 0), + MX6_PAD_LCD_DATA09__KEY_ROW0 = IOMUX_PAD(0x0404, 0x013C, 1, 0x06C0, 1, 0), + MX6_PAD_LCD_DATA09__CSI_DATA08 = IOMUX_PAD(0x0404, 0x013C, 2, 0x05E8, 0, 0), + MX6_PAD_LCD_DATA09__ECSPI2_MOSI = IOMUX_PAD(0x0404, 0x013C, 4, 0x0624, 0, 0), + MX6_PAD_LCD_DATA09__GPIO2_IO29 = IOMUX_PAD(0x0404, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__ARM_TRACE09 = IOMUX_PAD(0x0404, 0x013C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SRC_BOOT_CFG09 = IOMUX_PAD(0x0404, 0x013C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0408, 0x0140, 0, 0x0700, 1, 0), + MX6_PAD_LCD_DATA10__KEY_COL1 = IOMUX_PAD(0x0408, 0x0140, 1, 0x06A4, 1, 0), + MX6_PAD_LCD_DATA10__CSI_DATA07 = IOMUX_PAD(0x0408, 0x0140, 2, 0x05E4, 0, 0), + MX6_PAD_LCD_DATA10__ECSPI2_MISO = IOMUX_PAD(0x0408, 0x0140, 4, 0x0620, 0, 0), + MX6_PAD_LCD_DATA10__GPIO2_IO30 = IOMUX_PAD(0x0408, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__ARM_TRACE10 = IOMUX_PAD(0x0408, 0x0140, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0408, 0x0140, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x040C, 0x0144, 0, 0x0704, 0, 0), + MX6_PAD_LCD_DATA11__KEY_ROW1 = IOMUX_PAD(0x040C, 0x0144, 1, 0x06C4, 1, 0), + MX6_PAD_LCD_DATA11__CSI_DATA06 = IOMUX_PAD(0x040C, 0x0144, 2, 0x05E0, 0, 0), + MX6_PAD_LCD_DATA11__ECSPI2_SS1 = IOMUX_PAD(0x040C, 0x0144, 4, 0x062C, 0, 0), + MX6_PAD_LCD_DATA11__GPIO2_IO31 = IOMUX_PAD(0x040C, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__ARM_TRACE11 = IOMUX_PAD(0x040C, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x040C, 0x0144, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0410, 0x0148, 0, 0x0708, 0, 0), + MX6_PAD_LCD_DATA12__KEY_COL2 = IOMUX_PAD(0x0410, 0x0148, 1, 0x06A8, 1, 0), + MX6_PAD_LCD_DATA12__CSI_DATA05 = IOMUX_PAD(0x0410, 0x0148, 2, 0x05DC, 0, 0), + MX6_PAD_LCD_DATA12__UART5_DCE_RTS = IOMUX_PAD(0x0410, 0x0148, 4, 0x0760, 0, 0), + MX6_PAD_LCD_DATA12__UART5_DTE_CTS = IOMUX_PAD(0x0410, 0x0148, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__GPIO3_IO00 = IOMUX_PAD(0x0410, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__ARM_TRACE12 = IOMUX_PAD(0x0410, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0410, 0x0148, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x0414, 0x014C, 0, 0x070C, 0, 0), + MX6_PAD_LCD_DATA13__KEY_ROW2 = IOMUX_PAD(0x0414, 0x014C, 1, 0x06C8, 1, 0), + MX6_PAD_LCD_DATA13__CSI_DATA04 = IOMUX_PAD(0x0414, 0x014C, 2, 0x05D8, 0, 0), + MX6_PAD_LCD_DATA13__UART5_DCE_CTS = IOMUX_PAD(0x0414, 0x014C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__UART5_DTE_RTS = IOMUX_PAD(0x0414, 0x014C, 4, 0x0760, 1, 0), + MX6_PAD_LCD_DATA13__GPIO3_IO01 = IOMUX_PAD(0x0414, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__ARM_TRACE13 = IOMUX_PAD(0x0414, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0414, 0x014C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0418, 0x0150, 0, 0x0710, 0, 0), + MX6_PAD_LCD_DATA14__KEY_COL3 = IOMUX_PAD(0x0418, 0x0150, 1, 0x06AC, 1, 0), + MX6_PAD_LCD_DATA14__CSI_DATA03 = IOMUX_PAD(0x0418, 0x0150, 2, 0x05D4, 0, 0), + MX6_PAD_LCD_DATA14__UART5_DCE_RX = IOMUX_PAD(0x0418, 0x0150, 4, 0x0764, 0, 0), + MX6_PAD_LCD_DATA14__UART5_DTE_TX = IOMUX_PAD(0x0418, 0x0150, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__GPIO3_IO02 = IOMUX_PAD(0x0418, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__ARM_TRACE14 = IOMUX_PAD(0x0418, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0418, 0x0150, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x041C, 0x0154, 0, 0x0714, 0, 0), + MX6_PAD_LCD_DATA15__KEY_ROW3 = IOMUX_PAD(0x041C, 0x0154, 1, 0x06CC, 0, 0), + MX6_PAD_LCD_DATA15__CSI_DATA02 = IOMUX_PAD(0x041C, 0x0154, 2, 0x05D0, 0, 0), + MX6_PAD_LCD_DATA15__UART5_DCE_TX = IOMUX_PAD(0x041C, 0x0154, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__UART5_DTE_RX = IOMUX_PAD(0x041C, 0x0154, 4, 0x0764, 1, 0), + MX6_PAD_LCD_DATA15__GPIO3_IO03 = IOMUX_PAD(0x041C, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__ARM_TRACE15 = IOMUX_PAD(0x041C, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x041C, 0x0154, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0420, 0x0158, 0, 0x0718, 0, 0), + MX6_PAD_LCD_DATA16__KEY_COL4 = IOMUX_PAD(0x0420, 0x0158, 1, 0x06B0, 0, 0), + MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x0420, 0x0158, 2, 0x05CC, 0, 0), + MX6_PAD_LCD_DATA16__I2C2_SCL = IOMUX_PAD(0x0420, 0x0158, IOMUX_CONFIG_SION | 4, 0x0684, 1, 0), + MX6_PAD_LCD_DATA16__GPIO3_IO04 = IOMUX_PAD(0x0420, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__SRC_BOOT_CFG24 = IOMUX_PAD(0x0420, 0x0158, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x0424, 0x015C, 0, 0x071C, 0, 0), + MX6_PAD_LCD_DATA17__KEY_ROW4 = IOMUX_PAD(0x0424, 0x015C, 1, 0x06D0, 0, 0), + MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x0424, 0x015C, 2, 0x05C8, 0, 0), + MX6_PAD_LCD_DATA17__I2C2_SDA = IOMUX_PAD(0x0424, 0x015C, IOMUX_CONFIG_SION | 4, 0x0688, 1, 0), + MX6_PAD_LCD_DATA17__GPIO3_IO05 = IOMUX_PAD(0x0424, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__SRC_BOOT_CFG25 = IOMUX_PAD(0x0424, 0x015C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0428, 0x0160, 0, 0x0720, 0, 0), + MX6_PAD_LCD_DATA18__KEY_COL5 = IOMUX_PAD(0x0428, 0x0160, 1, 0x0694, 2, 0), + MX6_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0428, 0x0160, 2, 0x05C4, 1, 0), + MX6_PAD_LCD_DATA18__GPT_CAPTURE1 = IOMUX_PAD(0x0428, 0x0160, 4, 0x0670, 1, 0), + MX6_PAD_LCD_DATA18__GPIO3_IO06 = IOMUX_PAD(0x0428, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__SRC_BOOT_CFG26 = IOMUX_PAD(0x0428, 0x0160, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x042C, 0x0164, 0, 0x0724, 0, 0), + MX6_PAD_LCD_DATA19__KEY_ROW5 = IOMUX_PAD(0x042C, 0x0164, 1, 0x06B4, 1, 0), + MX6_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x042C, 0x0164, 2, 0x05C0, 2, 0), + MX6_PAD_LCD_DATA19__GPT_CAPTURE2 = IOMUX_PAD(0x042C, 0x0164, 4, 0x0674, 1, 0), + MX6_PAD_LCD_DATA19__GPIO3_IO07 = IOMUX_PAD(0x042C, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__SRC_BOOT_CFG27 = IOMUX_PAD(0x042C, 0x0164, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0430, 0x0168, 0, 0x0728, 0, 0), + MX6_PAD_LCD_DATA20__KEY_COL6 = IOMUX_PAD(0x0430, 0x0168, 1, 0x0698, 1, 0), + MX6_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0430, 0x0168, 2, 0x05BC, 2, 0), + MX6_PAD_LCD_DATA20__GPT_COMPARE1 = IOMUX_PAD(0x0430, 0x0168, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__GPIO3_IO08 = IOMUX_PAD(0x0430, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__SRC_BOOT_CFG28 = IOMUX_PAD(0x0430, 0x0168, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x0434, 0x016C, 0, 0x072C, 0, 0), + MX6_PAD_LCD_DATA21__KEY_ROW6 = IOMUX_PAD(0x0434, 0x016C, 1, 0x06B8, 1, 0), + MX6_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x0434, 0x016C, 2, 0x05B8, 2, 0), + MX6_PAD_LCD_DATA21__GPT_COMPARE2 = IOMUX_PAD(0x0434, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__GPIO3_IO09 = IOMUX_PAD(0x0434, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__SRC_BOOT_CFG29 = IOMUX_PAD(0x0434, 0x016C, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0438, 0x0170, 0, 0x0730, 0, 0), + MX6_PAD_LCD_DATA22__KEY_COL7 = IOMUX_PAD(0x0438, 0x0170, 1, 0x069C, 1, 0), + MX6_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0438, 0x0170, 2, 0x05B4, 1, 0), + MX6_PAD_LCD_DATA22__GPT_COMPARE3 = IOMUX_PAD(0x0438, 0x0170, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__GPIO3_IO10 = IOMUX_PAD(0x0438, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__SRC_BOOT_CFG30 = IOMUX_PAD(0x0438, 0x0170, 7, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x043C, 0x0174, 0, 0x0734, 0, 0), + MX6_PAD_LCD_DATA23__KEY_ROW7 = IOMUX_PAD(0x043C, 0x0174, 1, 0x06BC, 1, 0), + MX6_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x043C, 0x0174, 2, 0x05B0, 1, 0), + MX6_PAD_LCD_DATA23__GPT_CLKIN = IOMUX_PAD(0x043C, 0x0174, 4, 0x0678, 1, 0), + MX6_PAD_LCD_DATA23__GPIO3_IO11 = IOMUX_PAD(0x043C, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__SRC_BOOT_CFG31 = IOMUX_PAD(0x043C, 0x0174, 7, 0x0000, 0, 0), + + MX6_PAD_AUD_RXFS__AUD3_RXFS = IOMUX_PAD(0x0440, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_AUD_RXFS__I2C1_SCL = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 1, 0x067C, 1, 0), + MX6_PAD_AUD_RXFS__UART3_DCE_RX = IOMUX_PAD(0x0440, 0x0178, 2, 0x0754, 0, 0), + MX6_PAD_AUD_RXFS__UART3_DTE_TX = IOMUX_PAD(0x0440, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_AUD_RXFS__I2C3_SCL = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 4, 0x068C, 1, 0), + MX6_PAD_AUD_RXFS__GPIO1_IO00 = IOMUX_PAD(0x0440, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_AUD_RXFS__ECSPI3_SS0 = IOMUX_PAD(0x0440, 0x0178, 6, 0x0648, 0, 0), + MX6_PAD_AUD_RXFS__MBIST_BEND = IOMUX_PAD(0x0440, 0x0178, 7, 0x0000, 0, 0), + + MX6_PAD_AUD_RXC__AUD3_RXC = IOMUX_PAD(0x0444, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_AUD_RXC__I2C1_SDA = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 1, 0x0680, 1, 0), + MX6_PAD_AUD_RXC__UART3_DCE_TX = IOMUX_PAD(0x0444, 0x017C, 2, 0x0000, 0, 0), + MX6_PAD_AUD_RXC__UART3_DTE_RX = IOMUX_PAD(0x0444, 0x017C, 2, 0x0754, 1, 0), + MX6_PAD_AUD_RXC__I2C3_SDA = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 4, 0x0690, 1, 0), + MX6_PAD_AUD_RXC__GPIO1_IO01 = IOMUX_PAD(0x0444, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_AUD_RXC__ECSPI3_SS1 = IOMUX_PAD(0x0444, 0x017C, 6, 0x064C, 0, 0), + + MX6_PAD_AUD_RXD__AUD3_RXD = IOMUX_PAD(0x0448, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__ECSPI3_MOSI = IOMUX_PAD(0x0448, 0x0180, 1, 0x063C, 0, 0), + MX6_PAD_AUD_RXD__UART4_DCE_RX = IOMUX_PAD(0x0448, 0x0180, 2, 0x075C, 0, 0), + MX6_PAD_AUD_RXD__UART4_DTE_TX = IOMUX_PAD(0x0448, 0x0180, 2, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__SD1_LCTL = IOMUX_PAD(0x0448, 0x0180, 4, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__GPIO1_IO02 = IOMUX_PAD(0x0448, 0x0180, 5, 0x0000, 0, 0), + + MX6_PAD_AUD_TXC__AUD3_TXC = IOMUX_PAD(0x044C, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__ECSPI3_MISO = IOMUX_PAD(0x044C, 0x0184, 1, 0x0638, 0, 0), + MX6_PAD_AUD_TXC__UART4_DCE_TX = IOMUX_PAD(0x044C, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__UART4_DTE_RX = IOMUX_PAD(0x044C, 0x0184, 2, 0x075C, 1, 0), + MX6_PAD_AUD_TXC__SD2_LCTL = IOMUX_PAD(0x044C, 0x0184, 4, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__GPIO1_IO03 = IOMUX_PAD(0x044C, 0x0184, 5, 0x0000, 0, 0), + + MX6_PAD_AUD_TXFS__AUD3_TXFS = IOMUX_PAD(0x0450, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__PWM3_OUT = IOMUX_PAD(0x0450, 0x0188, 1, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__UART4_DCE_RTS = IOMUX_PAD(0x0450, 0x0188, 2, 0x0758, 0, 0), + MX6_PAD_AUD_TXFS__UART4_DTE_CTS = IOMUX_PAD(0x0450, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__SD3_LCTL = IOMUX_PAD(0x0450, 0x0188, 4, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__GPIO1_IO04 = IOMUX_PAD(0x0450, 0x0188, 5, 0x0000, 0, 0), + + MX6_PAD_AUD_TXD__AUD3_TXD = IOMUX_PAD(0x0454, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__ECSPI3_SCLK = IOMUX_PAD(0x0454, 0x018C, 1, 0x0630, 0, 0), + MX6_PAD_AUD_TXD__UART4_DCE_CTS = IOMUX_PAD(0x0454, 0x018C, 2, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__UART4_DTE_RTS = IOMUX_PAD(0x0454, 0x018C, 2, 0x0758, 1, 0), + MX6_PAD_AUD_TXD__GPIO1_IO05 = IOMUX_PAD(0x0454, 0x018C, 5, 0x0000, 0, 0), + + MX6_PAD_AUD_MCLK__AUDIO_CLK_OUT = IOMUX_PAD(0x0458, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__PWM4_OUT = IOMUX_PAD(0x0458, 0x0190, 1, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__ECSPI3_RDY = IOMUX_PAD(0x0458, 0x0190, 2, 0x0634, 0, 0), + MX6_PAD_AUD_MCLK__WDOG2_RESET_B_DEB = IOMUX_PAD(0x0458, 0x0190, 4, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__GPIO1_IO06 = IOMUX_PAD(0x0458, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__SPDIF_EXT_CLK = IOMUX_PAD(0x0458, 0x0190, 6, 0x073C, 1, 0), + + MX6_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 0, 0x0744, 0, 0), + + MX6_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__PWM1_OUT = IOMUX_PAD(0x045C, 0x0194, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__UART4_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 2, 0x075C, 4, 0), + MX6_PAD_UART1_RXD__UART4_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 2, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__UART5_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 4, 0x0764, 6, 0), + MX6_PAD_UART1_RXD__UART5_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 4, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__GPIO3_IO16 = IOMUX_PAD(0x045C, 0x0194, 5, 0x0000, 0, 0), + + MX6_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 0, 0x0744, 1, 0), + MX6_PAD_UART1_TXD__PWM2_OUT = IOMUX_PAD(0x0460, 0x0198, 1, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART4_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 2, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART4_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 2, 0x075C, 5, 0), + MX6_PAD_UART1_TXD__UART5_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 4, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART5_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 4, 0x0764, 7, 0), + MX6_PAD_UART1_TXD__GPIO3_IO17 = IOMUX_PAD(0x0460, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART5_DCD_B = IOMUX_PAD(0x0460, 0x0198, 7, 0x0000, 0, 0), + + MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0464, 0x019C, IOMUX_CONFIG_SION | 0, 0x067C, 0, 0), + MX6_PAD_I2C1_SCL__UART1_DCE_RTS = IOMUX_PAD(0x0464, 0x019C, 1, 0x0740, 0, 0), + MX6_PAD_I2C1_SCL__UART1_DTE_CTS = IOMUX_PAD(0x0464, 0x019C, 1, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__ECSPI3_SS2 = IOMUX_PAD(0x0464, 0x019C, 2, 0x0640, 0, 0), + MX6_PAD_I2C1_SCL__SD3_RESET = IOMUX_PAD(0x0464, 0x019C, 4, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__GPIO3_IO12 = IOMUX_PAD(0x0464, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__ECSPI1_SS1 = IOMUX_PAD(0x0464, 0x019C, 6, 0x060C, 0, 0), + + MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0468, 0x01A0, IOMUX_CONFIG_SION | 0, 0x0680, 0, 0), + MX6_PAD_I2C1_SDA__UART1_DCE_CTS = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__UART1_DTE_RTS = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0740, 1, 0), + MX6_PAD_I2C1_SDA__ECSPI3_SS3 = IOMUX_PAD(0x0468, 0x01A0, 2, 0x0644, 0, 0), + MX6_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x0468, 0x01A0, 4, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__GPIO3_IO13 = IOMUX_PAD(0x0468, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__ECSPI1_SS2 = IOMUX_PAD(0x0468, 0x01A0, 6, 0x0610, 0, 0), + + MX6_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x046C, 0x01A4, IOMUX_CONFIG_SION | 0, 0x0684, 3, 0), + MX6_PAD_I2C2_SCL__AUD4_RXFS = IOMUX_PAD(0x046C, 0x01A4, 1, 0x0570, 2, 0), + MX6_PAD_I2C2_SCL__SPDIF_IN = IOMUX_PAD(0x046C, 0x01A4, 2, 0x0738, 2, 0), + MX6_PAD_I2C2_SCL__SD3_WP = IOMUX_PAD(0x046C, 0x01A4, 4, 0x0794, 3, 0), + MX6_PAD_I2C2_SCL__GPIO3_IO14 = IOMUX_PAD(0x046C, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_I2C2_SCL__ECSPI1_RDY = IOMUX_PAD(0x046C, 0x01A4, 6, 0x0600, 1, 0), + + MX6_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0470, 0x01A8, IOMUX_CONFIG_SION | 0, 0x0688, 3, 0), + MX6_PAD_I2C2_SDA__AUD4_RXC = IOMUX_PAD(0x0470, 0x01A8, 1, 0x056C, 2, 0), + MX6_PAD_I2C2_SDA__SPDIF_OUT = IOMUX_PAD(0x0470, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_I2C2_SDA__SD3_CD_B = IOMUX_PAD(0x0470, 0x01A8, 4, 0x0780, 3, 0), + MX6_PAD_I2C2_SDA__GPIO3_IO15 = IOMUX_PAD(0x0470, 0x01A8, 5, 0x0000, 0, 0), + + MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0474, 0x01AC, 0, 0x05FC, 1, 0), + MX6_PAD_ECSPI1_SCLK__AUD4_TXD = IOMUX_PAD(0x0474, 0x01AC, 1, 0x0568, 1, 0), + MX6_PAD_ECSPI1_SCLK__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0764, 2, 0), + MX6_PAD_ECSPI1_SCLK__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__EPDC_VCOM0 = IOMUX_PAD(0x0474, 0x01AC, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__SD2_RESET = IOMUX_PAD(0x0474, 0x01AC, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 = IOMUX_PAD(0x0474, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__USB_OTG2_OC = IOMUX_PAD(0x0474, 0x01AC, 6, 0x0768, 1, 0), + + MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0478, 0x01B0, 0, 0x0608, 1, 0), + MX6_PAD_ECSPI1_MOSI__AUD4_TXC = IOMUX_PAD(0x0478, 0x01B0, 1, 0x0574, 1, 0), + MX6_PAD_ECSPI1_MOSI__UART5_DCE_TX = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__UART5_DTE_RX = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0764, 3, 0), + MX6_PAD_ECSPI1_MOSI__EPDC_VCOM1 = IOMUX_PAD(0x0478, 0x01B0, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__SD2_VSELECT = IOMUX_PAD(0x0478, 0x01B0, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__GPIO4_IO09 = IOMUX_PAD(0x0478, 0x01B0, 5, 0x0000, 0, 0), + + MX6_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x047C, 0x01B4, 0, 0x0604, 1, 0), + MX6_PAD_ECSPI1_MISO__AUD4_TXFS = IOMUX_PAD(0x047C, 0x01B4, 1, 0x0578, 1, 0), + MX6_PAD_ECSPI1_MISO__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0760, 2, 0), + MX6_PAD_ECSPI1_MISO__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MISO__EPDC_BDR0 = IOMUX_PAD(0x047C, 0x01B4, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MISO__SD2_WP = IOMUX_PAD(0x047C, 0x01B4, 4, 0x077C, 0, 0), + MX6_PAD_ECSPI1_MISO__GPIO4_IO10 = IOMUX_PAD(0x047C, 0x01B4, 5, 0x0000, 0, 0), + + MX6_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0480, 0x01B8, 0, 0x0614, 1, 0), + MX6_PAD_ECSPI1_SS0__AUD4_RXD = IOMUX_PAD(0x0480, 0x01B8, 1, 0x0564, 1, 0), + MX6_PAD_ECSPI1_SS0__UART5_DCE_CTS = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__UART5_DTE_RTS = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0760, 3, 0), + MX6_PAD_ECSPI1_SS0__EPDC_BDR1 = IOMUX_PAD(0x0480, 0x01B8, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__SD2_CD_B = IOMUX_PAD(0x0480, 0x01B8, 4, 0x0778, 0, 0), + MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0480, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__USB_OTG2_PWR = IOMUX_PAD(0x0480, 0x01B8, 6, 0x0000, 0, 0), + + MX6_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0484, 0x01BC, 0, 0x061C, 1, 0), + MX6_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK = IOMUX_PAD(0x0484, 0x01BC, 1, 0x073C, 2, 0), + MX6_PAD_ECSPI2_SCLK__UART3_DCE_RX = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0754, 2, 0), + MX6_PAD_ECSPI2_SCLK__UART3_DTE_TX = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SCLK__CSI_PIXCLK = IOMUX_PAD(0x0484, 0x01BC, 3, 0x05F4, 1, 0), + MX6_PAD_ECSPI2_SCLK__SD1_RESET = IOMUX_PAD(0x0484, 0x01BC, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SCLK__GPIO4_IO12 = IOMUX_PAD(0x0484, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC = IOMUX_PAD(0x0484, 0x01BC, 6, 0x0768, 2, 0), + + MX6_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0488, 0x01C0, 0, 0x0624, 1, 0), + MX6_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0488, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0754, 3, 0), + MX6_PAD_ECSPI2_MOSI__CSI_HSYNC = IOMUX_PAD(0x0488, 0x01C0, 3, 0x05F0, 1, 0), + MX6_PAD_ECSPI2_MOSI__SD1_VSELECT = IOMUX_PAD(0x0488, 0x01C0, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__GPIO4_IO13 = IOMUX_PAD(0x0488, 0x01C0, 5, 0x0000, 0, 0), + + MX6_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x048C, 0x01C4, 0, 0x0620, 1, 0), + MX6_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 = IOMUX_PAD(0x048C, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__UART3_DCE_RTS = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0750, 0, 0), + MX6_PAD_ECSPI2_MISO__UART3_DTE_CTS = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__CSI_MCLK = IOMUX_PAD(0x048C, 0x01C4, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__SD1_WP = IOMUX_PAD(0x048C, 0x01C4, 4, 0x0774, 2, 0), + MX6_PAD_ECSPI2_MISO__GPIO4_IO14 = IOMUX_PAD(0x048C, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__USB_OTG1_OC = IOMUX_PAD(0x048C, 0x01C4, 6, 0x076C, 1, 0), + + MX6_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0490, 0x01C8, 0, 0x0628, 0, 0), + MX6_PAD_ECSPI2_SS0__ECSPI1_SS3 = IOMUX_PAD(0x0490, 0x01C8, 1, 0x0618, 1, 0), + MX6_PAD_ECSPI2_SS0__UART3_DCE_CTS = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SS0__UART3_DTE_RTS = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0750, 1, 0), + MX6_PAD_ECSPI2_SS0__CSI_VSYNC = IOMUX_PAD(0x0490, 0x01C8, 3, 0x05F8, 1, 0), + MX6_PAD_ECSPI2_SS0__SD1_CD_B = IOMUX_PAD(0x0490, 0x01C8, 4, 0x0770, 2, 0), + MX6_PAD_ECSPI2_SS0__GPIO4_IO15 = IOMUX_PAD(0x0490, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SS0__USB_OTG1_PWR = IOMUX_PAD(0x0490, 0x01C8, 6, 0x0000, 0, 0), + + MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0494, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__KEY_COL0 = IOMUX_PAD(0x0494, 0x01CC, 2, 0x06A0, 2, 0), + MX6_PAD_SD1_CLK__EPDC_SDCE4 = IOMUX_PAD(0x0494, 0x01CC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO5_IO15 = IOMUX_PAD(0x0494, 0x01CC, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0498, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__KEY_ROW0 = IOMUX_PAD(0x0498, 0x01D0, 2, 0x06C0, 2, 0), + MX6_PAD_SD1_CMD__EPDC_SDCE5 = IOMUX_PAD(0x0498, 0x01D0, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO5_IO14 = IOMUX_PAD(0x0498, 0x01D0, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x049C, 0x01D4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__KEY_COL1 = IOMUX_PAD(0x049C, 0x01D4, 2, 0x06A4, 2, 0), + MX6_PAD_SD1_DATA0__EPDC_SDCE6 = IOMUX_PAD(0x049C, 0x01D4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPIO5_IO11 = IOMUX_PAD(0x049C, 0x01D4, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x04A0, 0x01D8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__KEY_ROW1 = IOMUX_PAD(0x04A0, 0x01D8, 2, 0x06C4, 2, 0), + MX6_PAD_SD1_DATA1__EPDC_SDCE7 = IOMUX_PAD(0x04A0, 0x01D8, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPIO5_IO08 = IOMUX_PAD(0x04A0, 0x01D8, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x04A4, 0x01DC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__KEY_COL2 = IOMUX_PAD(0x04A4, 0x01DC, 2, 0x06A8, 2, 0), + MX6_PAD_SD1_DATA2__EPDC_SDCE8 = IOMUX_PAD(0x04A4, 0x01DC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPIO5_IO13 = IOMUX_PAD(0x04A4, 0x01DC, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x04A8, 0x01E0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__KEY_ROW2 = IOMUX_PAD(0x04A8, 0x01E0, 2, 0x06C8, 2, 0), + MX6_PAD_SD1_DATA3__EPDC_SDCE9 = IOMUX_PAD(0x04A8, 0x01E0, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPIO5_IO06 = IOMUX_PAD(0x04A8, 0x01E0, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA4__SD1_DATA4 = IOMUX_PAD(0x04AC, 0x01E4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA4__KEY_COL3 = IOMUX_PAD(0x04AC, 0x01E4, 2, 0x06AC, 2, 0), + MX6_PAD_SD1_DATA4__EPDC_SDCLK_N = IOMUX_PAD(0x04AC, 0x01E4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA4__UART4_DCE_RX = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x075C, 6, 0), + MX6_PAD_SD1_DATA4__UART4_DTE_TX = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA4__GPIO5_IO12 = IOMUX_PAD(0x04AC, 0x01E4, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA5__SD1_DATA5 = IOMUX_PAD(0x04B0, 0x01E8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA5__KEY_ROW3 = IOMUX_PAD(0x04B0, 0x01E8, 2, 0x06CC, 2, 0), + MX6_PAD_SD1_DATA5__EPDC_SDOED = IOMUX_PAD(0x04B0, 0x01E8, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA5__UART4_DCE_TX = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA5__UART4_DTE_RX = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x075C, 7, 0), + MX6_PAD_SD1_DATA5__GPIO5_IO09 = IOMUX_PAD(0x04B0, 0x01E8, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA6__SD1_DATA6 = IOMUX_PAD(0x04B4, 0x01EC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA6__KEY_COL4 = IOMUX_PAD(0x04B4, 0x01EC, 2, 0x06B0, 2, 0), + MX6_PAD_SD1_DATA6__EPDC_SDOEZ = IOMUX_PAD(0x04B4, 0x01EC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA6__UART4_DCE_RTS = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0758, 4, 0), + MX6_PAD_SD1_DATA6__UART4_DTE_CTS = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA6__GPIO5_IO07 = IOMUX_PAD(0x04B4, 0x01EC, 5, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA7__SD1_DATA7 = IOMUX_PAD(0x04B8, 0x01F0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA7__KEY_ROW4 = IOMUX_PAD(0x04B8, 0x01F0, 2, 0x06D0, 2, 0), + MX6_PAD_SD1_DATA7__CCM_PMIC_READY = IOMUX_PAD(0x04B8, 0x01F0, 3, 0x05AC, 3, 0), + MX6_PAD_SD1_DATA7__UART4_DCE_CTS = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA7__UART4_DTE_RTS = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0758, 5, 0), + MX6_PAD_SD1_DATA7__GPIO5_IO10 = IOMUX_PAD(0x04B8, 0x01F0, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_RESET__SD2_RESET = IOMUX_PAD(0x04BC, 0x01F4, 0, 0x0000, 0, 0), + MX6_PAD_SD2_RESET__WDOG2_B = IOMUX_PAD(0x04BC, 0x01F4, 2, 0x0000, 0, 0), + MX6_PAD_SD2_RESET__SPDIF_OUT = IOMUX_PAD(0x04BC, 0x01F4, 3, 0x0000, 0, 0), + MX6_PAD_SD2_RESET__CSI_MCLK = IOMUX_PAD(0x04BC, 0x01F4, 4, 0x0000, 0, 0), + MX6_PAD_SD2_RESET__GPIO4_IO27 = IOMUX_PAD(0x04BC, 0x01F4, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x04C0, 0x01F8, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x04C0, 0x01F8, 1, 0x0570, 1, 0), + MX6_PAD_SD2_CLK__ECSPI3_SCLK = IOMUX_PAD(0x04C0, 0x01F8, 2, 0x0630, 1, 0), + MX6_PAD_SD2_CLK__CSI_DATA00 = IOMUX_PAD(0x04C0, 0x01F8, 3, 0x05C8, 1, 0), + MX6_PAD_SD2_CLK__GPIO5_IO05 = IOMUX_PAD(0x04C0, 0x01F8, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x04C4, 0x01FC, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x04C4, 0x01FC, 1, 0x056C, 1, 0), + MX6_PAD_SD2_CMD__ECSPI3_SS0 = IOMUX_PAD(0x04C4, 0x01FC, 2, 0x0648, 1, 0), + MX6_PAD_SD2_CMD__CSI_DATA01 = IOMUX_PAD(0x04C4, 0x01FC, 3, 0x05CC, 1, 0), + MX6_PAD_SD2_CMD__EPIT1_OUT = IOMUX_PAD(0x04C4, 0x01FC, 4, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__GPIO5_IO04 = IOMUX_PAD(0x04C4, 0x01FC, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x04C8, 0x0200, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__AUD4_RXD = IOMUX_PAD(0x04C8, 0x0200, 1, 0x0564, 2, 0), + MX6_PAD_SD2_DATA0__ECSPI3_MOSI = IOMUX_PAD(0x04C8, 0x0200, 2, 0x063C, 1, 0), + MX6_PAD_SD2_DATA0__CSI_DATA02 = IOMUX_PAD(0x04C8, 0x0200, 3, 0x05D0, 1, 0), + MX6_PAD_SD2_DATA0__UART5_DCE_RTS = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0760, 4, 0), + MX6_PAD_SD2_DATA0__UART5_DTE_CTS = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DATA0__GPIO5_IO01 = IOMUX_PAD(0x04C8, 0x0200, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x04CC, 0x0204, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__AUD4_TXC = IOMUX_PAD(0x04CC, 0x0204, 1, 0x0574, 2, 0), + MX6_PAD_SD2_DATA1__ECSPI3_MISO = IOMUX_PAD(0x04CC, 0x0204, 2, 0x0638, 1, 0), + MX6_PAD_SD2_DATA1__CSI_DATA03 = IOMUX_PAD(0x04CC, 0x0204, 3, 0x05D4, 1, 0), + MX6_PAD_SD2_DATA1__UART5_DCE_CTS = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DATA1__UART5_DTE_RTS = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0760, 5, 0), + MX6_PAD_SD2_DATA1__GPIO4_IO30 = IOMUX_PAD(0x04CC, 0x0204, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x04D0, 0x0208, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__AUD4_TXFS = IOMUX_PAD(0x04D0, 0x0208, 1, 0x0578, 2, 0), + MX6_PAD_SD2_DATA2__CSI_DATA04 = IOMUX_PAD(0x04D0, 0x0208, 3, 0x05D8, 1, 0), + MX6_PAD_SD2_DATA2__UART5_DCE_RX = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0764, 4, 0), + MX6_PAD_SD2_DATA2__UART5_DTE_TX = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DATA2__GPIO5_IO03 = IOMUX_PAD(0x04D0, 0x0208, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x04D4, 0x020C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA3__AUD4_TXD = IOMUX_PAD(0x04D4, 0x020C, 1, 0x0568, 2, 0), + MX6_PAD_SD2_DATA3__CSI_DATA05 = IOMUX_PAD(0x04D4, 0x020C, 3, 0x05DC, 1, 0), + MX6_PAD_SD2_DATA3__UART5_DCE_TX = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DATA3__UART5_DTE_RX = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0764, 5, 0), + MX6_PAD_SD2_DATA3__GPIO4_IO28 = IOMUX_PAD(0x04D4, 0x020C, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA4__SD2_DATA4 = IOMUX_PAD(0x04D8, 0x0210, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA4__SD3_DATA4 = IOMUX_PAD(0x04D8, 0x0210, 1, 0x0784, 1, 0), + MX6_PAD_SD2_DATA4__UART2_DCE_RX = IOMUX_PAD(0x04D8, 0x0210, 2, 0x074C, 2, 0), + MX6_PAD_SD2_DATA4__UART2_DTE_TX = IOMUX_PAD(0x04D8, 0x0210, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DATA4__CSI_DATA06 = IOMUX_PAD(0x04D8, 0x0210, 3, 0x05E0, 1, 0), + MX6_PAD_SD2_DATA4__SPDIF_OUT = IOMUX_PAD(0x04D8, 0x0210, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DATA4__GPIO5_IO02 = IOMUX_PAD(0x04D8, 0x0210, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA5__SD2_DATA5 = IOMUX_PAD(0x04DC, 0x0214, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA5__SD3_DATA5 = IOMUX_PAD(0x04DC, 0x0214, 1, 0x0788, 1, 0), + MX6_PAD_SD2_DATA5__UART2_DCE_TX = IOMUX_PAD(0x04DC, 0x0214, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DATA5__UART2_DTE_RX = IOMUX_PAD(0x04DC, 0x0214, 2, 0x074C, 3, 0), + MX6_PAD_SD2_DATA5__CSI_DATA07 = IOMUX_PAD(0x04DC, 0x0214, 3, 0x05E4, 1, 0), + MX6_PAD_SD2_DATA5__SPDIF_IN = IOMUX_PAD(0x04DC, 0x0214, 4, 0x0738, 1, 0), + MX6_PAD_SD2_DATA5__GPIO4_IO31 = IOMUX_PAD(0x04DC, 0x0214, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA6__SD2_DATA6 = IOMUX_PAD(0x04E0, 0x0218, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA6__SD3_DATA6 = IOMUX_PAD(0x04E0, 0x0218, 1, 0x078C, 1, 0), + MX6_PAD_SD2_DATA6__UART2_DCE_RTS = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0748, 2, 0), + MX6_PAD_SD2_DATA6__UART2_DTE_CTS = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DATA6__CSI_DATA08 = IOMUX_PAD(0x04E0, 0x0218, 3, 0x05E8, 1, 0), + MX6_PAD_SD2_DATA6__SD2_WP = IOMUX_PAD(0x04E0, 0x0218, 4, 0x077C, 1, 0), + MX6_PAD_SD2_DATA6__GPIO4_IO29 = IOMUX_PAD(0x04E0, 0x0218, 5, 0x0000, 0, 0), + + MX6_PAD_SD2_DATA7__SD2_DATA7 = IOMUX_PAD(0x04E4, 0x021C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DATA7__SD3_DATA7 = IOMUX_PAD(0x04E4, 0x021C, 1, 0x0790, 1, 0), + MX6_PAD_SD2_DATA7__UART2_DCE_CTS = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DATA7__UART2_DTE_RTS = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0748, 3, 0), + MX6_PAD_SD2_DATA7__CSI_DATA09 = IOMUX_PAD(0x04E4, 0x021C, 3, 0x05EC, 1, 0), + MX6_PAD_SD2_DATA7__SD2_CD_B = IOMUX_PAD(0x04E4, 0x021C, 4, 0x0778, 1, 0), + MX6_PAD_SD2_DATA7__GPIO5_IO00 = IOMUX_PAD(0x04E4, 0x021C, 5, 0x0000, 0, 0), + + MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x04E8, 0x0220, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__AUD5_RXFS = IOMUX_PAD(0x04E8, 0x0220, 1, 0x0588, 0, 0), + MX6_PAD_SD3_CLK__KEY_COL5 = IOMUX_PAD(0x04E8, 0x0220, 2, 0x0694, 0, 0), + MX6_PAD_SD3_CLK__CSI_DATA10 = IOMUX_PAD(0x04E8, 0x0220, 3, 0x05B0, 0, 0), + MX6_PAD_SD3_CLK__WDOG1_RESET_B_DEB = IOMUX_PAD(0x04E8, 0x0220, 4, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__GPIO5_IO18 = IOMUX_PAD(0x04E8, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USB_OTG1_PWR = IOMUX_PAD(0x04E8, 0x0220, 6, 0x0000, 0, 0), + + MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x04EC, 0x0224, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__AUD5_RXC = IOMUX_PAD(0x04EC, 0x0224, 1, 0x0584, 0, 0), + MX6_PAD_SD3_CMD__KEY_ROW5 = IOMUX_PAD(0x04EC, 0x0224, 2, 0x06B4, 0, 0), + MX6_PAD_SD3_CMD__CSI_DATA11 = IOMUX_PAD(0x04EC, 0x0224, 3, 0x05B4, 0, 0), + MX6_PAD_SD3_CMD__USB_OTG2_ID = IOMUX_PAD(0x04EC, 0x0224, 4, 0x0560, 1, 0), + MX6_PAD_SD3_CMD__GPIO5_IO21 = IOMUX_PAD(0x04EC, 0x0224, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USB_OTG2_PWR = IOMUX_PAD(0x04EC, 0x0224, 6, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x04F0, 0x0228, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA0__AUD5_RXD = IOMUX_PAD(0x04F0, 0x0228, 1, 0x057C, 0, 0), + MX6_PAD_SD3_DATA0__KEY_COL6 = IOMUX_PAD(0x04F0, 0x0228, 2, 0x0698, 0, 0), + MX6_PAD_SD3_DATA0__CSI_DATA12 = IOMUX_PAD(0x04F0, 0x0228, 3, 0x05B8, 0, 0), + MX6_PAD_SD3_DATA0__USB_OTG1_ID = IOMUX_PAD(0x04F0, 0x0228, 4, 0x055C, 1, 0), + MX6_PAD_SD3_DATA0__GPIO5_IO19 = IOMUX_PAD(0x04F0, 0x0228, 5, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x04F4, 0x022C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__AUD5_TXC = IOMUX_PAD(0x04F4, 0x022C, 1, 0x058C, 0, 0), + MX6_PAD_SD3_DATA1__KEY_ROW6 = IOMUX_PAD(0x04F4, 0x022C, 2, 0x06B8, 0, 0), + MX6_PAD_SD3_DATA1__CSI_DATA13 = IOMUX_PAD(0x04F4, 0x022C, 3, 0x05BC, 0, 0), + MX6_PAD_SD3_DATA1__SD1_VSELECT = IOMUX_PAD(0x04F4, 0x022C, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__GPIO5_IO20 = IOMUX_PAD(0x04F4, 0x022C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA1__JTAG_DE_B = IOMUX_PAD(0x04F4, 0x022C, 6, 0x0000, 0, 0), + + MX6_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x04F8, 0x0230, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__AUD5_TXFS = IOMUX_PAD(0x04F8, 0x0230, 1, 0x0590, 0, 0), + MX6_PAD_SD3_DATA2__KEY_COL7 = IOMUX_PAD(0x04F8, 0x0230, 2, 0x069C, 0, 0), + MX6_PAD_SD3_DATA2__CSI_DATA14 = IOMUX_PAD(0x04F8, 0x0230, 3, 0x05C0, 0, 0), + MX6_PAD_SD3_DATA2__EPIT1_OUT = IOMUX_PAD(0x04F8, 0x0230, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__GPIO5_IO16 = IOMUX_PAD(0x04F8, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA2__USB_OTG2_OC = IOMUX_PAD(0x04F8, 0x0230, 6, 0x0768, 0, 0), + + MX6_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x04FC, 0x0234, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__AUD5_TXD = IOMUX_PAD(0x04FC, 0x0234, 1, 0x0580, 0, 0), + MX6_PAD_SD3_DATA3__KEY_ROW7 = IOMUX_PAD(0x04FC, 0x0234, 2, 0x06BC, 0, 0), + MX6_PAD_SD3_DATA3__CSI_DATA15 = IOMUX_PAD(0x04FC, 0x0234, 3, 0x05C4, 0, 0), + MX6_PAD_SD3_DATA3__EPIT2_OUT = IOMUX_PAD(0x04FC, 0x0234, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__GPIO5_IO17 = IOMUX_PAD(0x04FC, 0x0234, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DATA3__USB_OTG1_OC = IOMUX_PAD(0x04FC, 0x0234, 6, 0x076C, 0, 0), + + MX6_PAD_GPIO4_IO20__SD1_STROBE = IOMUX_PAD(0x0500, 0x0238, 0, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO20__AUD6_RXFS = IOMUX_PAD(0x0500, 0x0238, 2, 0x05A0, 0, 0), + MX6_PAD_GPIO4_IO20__ECSPI4_SS0 = IOMUX_PAD(0x0500, 0x0238, 3, 0x065C, 0, 0), + MX6_PAD_GPIO4_IO20__GPT_CAPTURE1 = IOMUX_PAD(0x0500, 0x0238, 4, 0x0670, 0, 0), + MX6_PAD_GPIO4_IO20__GPIO4_IO20 = IOMUX_PAD(0x0500, 0x0238, 5, 0x0000, 0, 0), + + MX6_PAD_GPIO4_IO21__SD2_STROBE = IOMUX_PAD(0x0504, 0x023C, 0, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO21__AUD6_RXC = IOMUX_PAD(0x0504, 0x023C, 2, 0x059C, 0, 0), + MX6_PAD_GPIO4_IO21__ECSPI4_SCLK = IOMUX_PAD(0x0504, 0x023C, 3, 0x0650, 0, 0), + MX6_PAD_GPIO4_IO21__GPT_CAPTURE2 = IOMUX_PAD(0x0504, 0x023C, 4, 0x0674, 0, 0), + MX6_PAD_GPIO4_IO21__GPIO4_IO21 = IOMUX_PAD(0x0504, 0x023C, 5, 0x0000, 0, 0), + + MX6_PAD_GPIO4_IO19__SD3_STROBE = IOMUX_PAD(0x0508, 0x0240, 0, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO19__AUD6_RXD = IOMUX_PAD(0x0508, 0x0240, 2, 0x0594, 0, 0), + MX6_PAD_GPIO4_IO19__ECSPI4_MOSI = IOMUX_PAD(0x0508, 0x0240, 3, 0x0658, 0, 0), + MX6_PAD_GPIO4_IO19__GPT_COMPARE1 = IOMUX_PAD(0x0508, 0x0240, 4, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO19__GPIO4_IO19 = IOMUX_PAD(0x0508, 0x0240, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO25__AUD6_TXC = IOMUX_PAD(0x050C, 0x0244, 2, 0x05A4, 0, 0), + MX6_PAD_GPIO4_IO25__ECSPI4_MISO = IOMUX_PAD(0x050C, 0x0244, 3, 0x0654, 0, 0), + MX6_PAD_GPIO4_IO25__GPT_COMPARE2 = IOMUX_PAD(0x050C, 0x0244, 4, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO25__GPIO4_IO25 = IOMUX_PAD(0x050C, 0x0244, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO18__AUD6_TXFS = IOMUX_PAD(0x0510, 0x0248, 2, 0x05A8, 0, 0), + MX6_PAD_GPIO4_IO18__ECSPI4_SS1 = IOMUX_PAD(0x0510, 0x0248, 3, 0x0660, 0, 0), + MX6_PAD_GPIO4_IO18__GPT_COMPARE3 = IOMUX_PAD(0x0510, 0x0248, 4, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO18__GPIO4_IO18 = IOMUX_PAD(0x0510, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO24__AUD6_TXD = IOMUX_PAD(0x0514, 0x024C, 2, 0x0598, 0, 0), + MX6_PAD_GPIO4_IO24__ECSPI4_SS2 = IOMUX_PAD(0x0514, 0x024C, 3, 0x0664, 0, 0), + MX6_PAD_GPIO4_IO24__GPT_CLKIN = IOMUX_PAD(0x0514, 0x024C, 4, 0x0678, 0, 0), + MX6_PAD_GPIO4_IO24__GPIO4_IO24 = IOMUX_PAD(0x0514, 0x024C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO23__AUDIO_CLK_OUT = IOMUX_PAD(0x0518, 0x0250, 2, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO23__SD1_RESET = IOMUX_PAD(0x0518, 0x0250, 3, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO23__SD3_RESET = IOMUX_PAD(0x0518, 0x0250, 4, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO23__GPIO4_IO23 = IOMUX_PAD(0x0518, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO17__USB_OTG1_ID = IOMUX_PAD(0x051C, 0x0254, 2, 0x055C, 2, 0), + MX6_PAD_GPIO4_IO17__SD1_VSELECT = IOMUX_PAD(0x051C, 0x0254, 3, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO17__SD3_VSELECT = IOMUX_PAD(0x051C, 0x0254, 4, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO17__GPIO4_IO17 = IOMUX_PAD(0x051C, 0x0254, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO22__SPDIF_IN = IOMUX_PAD(0x0520, 0x0258, 2, 0x0738, 0, 0), + MX6_PAD_GPIO4_IO22__SD1_WP = IOMUX_PAD(0x0520, 0x0258, 3, 0x0774, 0, 0), + MX6_PAD_GPIO4_IO22__SD3_WP = IOMUX_PAD(0x0520, 0x0258, 4, 0x0794, 1, 0), + MX6_PAD_GPIO4_IO22__GPIO4_IO22 = IOMUX_PAD(0x0520, 0x0258, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO16__SPDIF_OUT = IOMUX_PAD(0x0524, 0x025C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO16__SD1_CD_B = IOMUX_PAD(0x0524, 0x025C, 3, 0x0770, 0, 0), + MX6_PAD_GPIO4_IO16__SD3_CD_B = IOMUX_PAD(0x0524, 0x025C, 4, 0x0780, 1, 0), + MX6_PAD_GPIO4_IO16__GPIO4_IO16 = IOMUX_PAD(0x0524, 0x025C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO26__WDOG1_B = IOMUX_PAD(0x0528, 0x0260, 2, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO26__PWM4_OUT = IOMUX_PAD(0x0528, 0x0260, 3, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO26__CCM_PMIC_READY = IOMUX_PAD(0x0528, 0x0260, 4, 0x05AC, 1, 0), + MX6_PAD_GPIO4_IO26__GPIO4_IO26 = IOMUX_PAD(0x0528, 0x0260, 5, 0x0000, 0, 0), + MX6_PAD_GPIO4_IO26__SPDIF_EXT_CLK = IOMUX_PAD(0x0528, 0x0260, 6, 0x073C, 0, 0), +}; +#endif /* __ASM_ARCH_IMX6SLL_PINS_H__ */ -- cgit v0.10.2 From 56612bf6c6c3e8415758b09eff1e288a384dead9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:22 +0800 Subject: imx: mx6sll: update register address Update register address for i.MX6 SLL Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 8bb36eb..6727c56 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -26,7 +26,7 @@ #define APBH_DMA_ARB_END_ADDR 0x0180BFFF #define M4_BOOTROM_BASE_ADDR 0x007F8000 -#else +#elif !defined(CONFIG_MX6SLL) #define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_END_ADDR 0x00103FFF #define APBH_DMA_ARB_BASE_ADDR 0x00110000 @@ -46,13 +46,9 @@ #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) /* GPV - PL301 configuration ports */ -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)) #define GPV2_BASE_ADDR 0x00D00000 -#else -#define GPV2_BASE_ADDR 0x00200000 -#endif - -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #define GPV3_BASE_ADDR 0x00E00000 #define GPV4_BASE_ADDR 0x00F00000 #define GPV5_BASE_ADDR 0x01000000 @@ -61,6 +57,7 @@ #define PCIE_ARB_END_ADDR 0x08FFFFFF #else +#define GPV2_BASE_ADDR 0x00200000 #define GPV3_BASE_ADDR 0x00300000 #define GPV4_BASE_ADDR 0x00800000 #define PCIE_ARB_BASE_ADDR 0x01000000 @@ -96,7 +93,7 @@ #define WEIM_ARB_END_ADDR 0x57FFFFFF #define QSPI0_AMBA_BASE 0x60000000 #define QSPI0_AMBA_END 0x6FFFFFFF -#else +#elif !defined(CONFIG_MX6SLL) #define SATA_ARB_BASE_ADDR 0x02200000 #define SATA_ARB_END_ADDR 0x02203FFF #define OPENVG_ARB_BASE_ADDR 0x02204000 @@ -111,7 +108,8 @@ #define WEIM_ARB_END_ADDR 0x0FFFFFFF #endif -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) +#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ + defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #define MMDC0_ARB_BASE_ADDR 0x80000000 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF #define MMDC1_ARB_BASE_ADDR 0xC0000000 @@ -141,19 +139,21 @@ #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) -#ifdef CONFIG_MX6SL -#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) -#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) -#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) -#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) -#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) -#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) -#else + +#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) +#define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) +#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) + #ifndef CONFIG_MX6SX #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) #endif +#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) @@ -161,7 +161,6 @@ #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) -#endif #ifndef CONFIG_MX6SX #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) @@ -176,6 +175,8 @@ #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) +/* QOSC on i.MX6SLL */ +#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) @@ -198,11 +199,18 @@ #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) -#ifdef CONFIG_MX6SL +#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) +#ifdef CONFIG_MX6SLL +#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) +#elif defined(CONFIG_MX6SL) #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#elif CONFIG_MX6SX +#elif defined(CONFIG_MX6SX) #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) @@ -215,6 +223,9 @@ #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) #endif +#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) + #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) @@ -249,7 +260,7 @@ #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) -/* i.MX6SL */ +/* i.MX6SL/SLL */ #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) #ifdef CONFIG_MX6UL #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) @@ -263,6 +274,10 @@ #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) +#ifdef CONFIG_MX6SLL +#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) +#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#endif #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) @@ -296,6 +311,8 @@ #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +/* i.MX6SLL */ +#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #ifdef CONFIG_MX6SX #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) @@ -334,7 +351,8 @@ #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) +#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ + defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)) #define IRAM_SIZE 0x00040000 #else #define IRAM_SIZE 0x00020000 @@ -348,10 +366,14 @@ /* only for i.MX6SX/UL */ #define WDOG3_BASE_ADDR ((is_mx6ul() ? \ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) -#define LCDIF1_BASE_ADDR ((is_mx6ul()) ? \ +#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \ + MX6SLL_LCDIF_BASE_ADDR : \ + (is_cpu_type(MXC_CPU_MX6SL)) ? \ + MX6SL_LCDIF_BASE_ADDR : \ + ((is_cpu_type(MXC_CPU_MX6UL)) ? \ MX6UL_LCDIF1_BASE_ADDR : \ ((is_mx6ull()) ? \ - MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)) + MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); @@ -672,7 +694,8 @@ struct cspi_regs { #define MXC_CSPICON_POL 4 /* SCLK polarity */ #define MXC_CSPICON_SSPOL 12 /* SS polarity */ #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ -#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) +#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \ + defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ ECSPI2_BASE_ADDR, \ -- cgit v0.10.2 From fddac8056a4ea5ef446cd278b73bae625b42a16c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:23 +0800 Subject: imx-common: timer: add i.MX6SLL support Add i.MX6 SLL GPT timer support. Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index 1f7c671..ee6eff2 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -45,7 +45,7 @@ static inline int gpt_has_clk_source_osc(void) #if defined(CONFIG_MX6) if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() || - is_mx6ull()) + is_mx6ull() || is_mx6sll()) return 1; return 0; @@ -84,8 +84,12 @@ int timer_init(void) if (gpt_has_clk_source_osc()) { i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; - /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler */ - if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) { + /* + * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC + * Enable bit and prescaler + */ + if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() || + is_mx6sll()) { i |= GPTCR_24MEN; /* Produce 3Mhz clock */ -- cgit v0.10.2 From 40913fb595d1f909acbe098b3cbb076c8a635dda Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:24 +0800 Subject: imx: mx6sll: add iomux settings Add iomux settings for i.MX6 SLL Signed-off-by: Peng Fan Signed-off-by: Ye.Li Cc: Stefano Babic diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 392f4bc..c9a3bf2 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -31,7 +31,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; -#if defined CONFIG_MX6SL +#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) /* Check whether LVE bit needs to be set */ if (pad_ctrl & PAD_CTL_LVE) { pad_ctrl &= ~PAD_CTL_LVE; @@ -51,7 +51,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS; } #else - if (is_mx6ull()) { + if (is_mx6ull() || is_mx6sll()) { if (lpsr == IOMUX_CONFIG_LPSR) { base = (void *)IOMUXC_SNVS_BASE_ADDR; mux_mode &= ~IOMUX_CONFIG_LPSR; @@ -60,7 +60,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #endif #endif - if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs) + if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); if (sel_input_ofs) @@ -73,6 +73,10 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #else if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); +#if defined(CONFIG_MX6SLL) + else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) + clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT); +#endif #endif #ifdef CONFIG_IOMUX_LPSR diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index b3af696..7587cbb 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -144,10 +144,12 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 << 3) #define PAD_CTL_DSE_34ohm (7 << 3) -#if defined CONFIG_MX6SL +/* i.MX6SL/SLL */ #define PAD_CTL_LVE (1 << 1) #define PAD_CTL_LVE_BIT (1 << 22) -#endif + +/* i.MX6SLL */ +#define PAD_CTL_IPD_BIT (1 << 27) #elif defined(CONFIG_VF610) -- cgit v0.10.2 From 0e81982de08fc93118c3dc49cc81def0d3801445 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:25 +0800 Subject: imx: mx6: fix mmdc ch0 clk for 6SL >From RM, per_periph2_clk_sel option3 is: "derive clock from 198MHz clock (divided 392MHz PLL2 PFD)." So fix it. Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 2995628..88f68f1 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -514,6 +514,11 @@ static u32 get_mmdc_ch0_clk(void) freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: + if (is_mx6sl()) { + freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1; + break; + } + pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2)); switch (pmu_misc2_audio_div) { case 0: -- cgit v0.10.2 From 70ac169723003ecc8e3f5f0abcf7bc4c59b487d9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:26 +0800 Subject: imx: mx6: lcdif: gate clock before changing mux The mux for the lcd clock is not glitchless, so need to first gate the clock before changing the mux. Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 88f68f1..2092260 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -771,6 +771,16 @@ int enable_lcdif_clock(u32 base_addr) return 0; } + /* Gate LCDIF clock first */ + reg = readl(&imx_ccm->CCGR3); + reg &= ~lcdif_ccgr3_mask; + writel(reg, &imx_ccm->CCGR3); + + reg = readl(&imx_ccm->CCGR2); + reg &= ~MXC_CCM_CCGR2_LCD_MASK; + writel(reg, &imx_ccm->CCGR2); + + /* Select pre-mux */ reg = readl(&imx_ccm->cscdr2); reg &= ~lcdif_clk_sel_mask; writel(reg, &imx_ccm->cscdr2); -- cgit v0.10.2 From e332623b0328f91c76d99c356c350fc04b1fc8dc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:27 +0800 Subject: imx: mx6sl: add lcdif clock support Add lcdif clock support for i.MX6SL. Signed-off-by: Peng Fan diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 2092260..007c135 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -625,16 +625,18 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) debug("mxs_set_lcdclk, freq = %dKHz\n", freq); - if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) { + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) { debug("This chip not support lcd!\n"); return; } - if (base_addr == LCDIF1_BASE_ADDR) { - reg = readl(&imx_ccm->cscdr2); - /* Can't change clocks when clock not from pre-mux */ - if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0) - return; + if (!is_mx6sl()) { + if (base_addr == LCDIF1_BASE_ADDR) { + reg = readl(&imx_ccm->cscdr2); + /* Can't change clocks when clock not from pre-mux */ + if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0) + return; + } } if (is_mx6sx()) { @@ -705,19 +707,35 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) return; - /* Select pre-lcd clock to PLL5 and set pre divider */ - clrsetbits_le32(&imx_ccm->cscdr2, - MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK | - MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK, - (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) | - ((pred - 1) << - MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET)); - - /* Set the post divider */ - clrsetbits_le32(&imx_ccm->cbcmr, - MXC_CCM_CBCMR_LCDIF1_PODF_MASK, - ((postd - 1) << - MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET)); + if (!is_mx6sl()) { + /* Select pre-lcd clock to PLL5 and set pre divider */ + clrsetbits_le32(&imx_ccm->cscdr2, + MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK | + MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK, + (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) | + ((pred - 1) << + MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET)); + + /* Set the post divider */ + clrsetbits_le32(&imx_ccm->cbcmr, + MXC_CCM_CBCMR_LCDIF1_PODF_MASK, + ((postd - 1) << + MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET)); + } else { + /* Select pre-lcd clock to PLL5 and set pre divider */ + clrsetbits_le32(&imx_ccm->cscdr2, + MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK | + MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK, + (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) | + ((pred - 1) << + MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET)); + + /* Set the post divider */ + clrsetbits_le32(&imx_ccm->cscmr1, + MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK, + (((postd - 1)^0x6) << + MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET)); + } } else if (is_mx6sx()) { /* Setting LCDIF2 for i.MX6SX */ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) @@ -767,6 +785,28 @@ int enable_lcdif_clock(u32 base_addr) /* Set to pre-mux clock at default */ lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK; lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK; + } else if (is_mx6sl()) { + if (base_addr != LCDIF1_BASE_ADDR) { + puts("Wrong LCD interface!\n"); + return -EINVAL; + } + + reg = readl(&imx_ccm->CCGR3); + reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK | + MXC_CCM_CCGR3_LCDIF_PIX_MASK); + writel(reg, &imx_ccm->CCGR3); + + reg = readl(&imx_ccm->cscdr3); + reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK; + reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET; + writel(reg, &imx_ccm->cscdr3); + + reg = readl(&imx_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK | + MXC_CCM_CCGR3_LCDIF_PIX_MASK; + writel(reg, &imx_ccm->CCGR3); + + return 0; } else { return 0; } diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 29674ce..74ed912 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -307,6 +307,9 @@ struct mxc_ccm_reg { /* LCFIF2_PODF on i.MX6SX */ #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 +/* LCDIF_PIX_PODF on i.MX6SL */ +#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK (0x7 << 20) +#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET 20 /* ACLK_EMI on i.MX6DQ/SDL/DQP */ #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 @@ -529,6 +532,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0 +/*LCD on i.MX6SL */ +#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET 6 +#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK (0x7 << 3) +#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET 3 + /* All IPU2_DI1 are LCDIF1 on MX6SX */ #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 @@ -554,6 +563,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 +/* For i.MX6SL */ +#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET 16 +#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET 14 + /* Define the bits in register CDHIPR */ #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) @@ -783,6 +798,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_QSPI_OFFSET 14 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) +/* i.MX6SL */ +#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6 +#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8 +#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET) + #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 -- cgit v0.10.2 From 708f69275329d4e23ed2f927cee7674ca25c1544 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:28 +0800 Subject: imx: clock: gate clk before changing pix clk mux The LCDIF Pixel clock mux is not glitchless, so need to gate before changing mux. Also change enable_lcdif_clock prototype with a new input parameter to indicate disable or enable. Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 007c135..de3665f 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -707,6 +707,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) return; + enable_lcdif_clock(base_addr, 0); if (!is_mx6sl()) { /* Select pre-lcd clock to PLL5 and set pre divider */ clrsetbits_le32(&imx_ccm->cscdr2, @@ -736,11 +737,14 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) (((postd - 1)^0x6) << MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET)); } + + enable_lcdif_clock(base_addr, 1); } else if (is_mx6sx()) { /* Setting LCDIF2 for i.MX6SX */ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) return; + enable_lcdif_clock(base_addr, 0); /* Select pre-lcd clock to PLL5 and set pre divider */ clrsetbits_le32(&imx_ccm->cscdr2, MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK | @@ -754,10 +758,12 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) MXC_CCM_CSCMR1_LCDIF2_PODF_MASK, ((postd - 1) << MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET)); + + enable_lcdif_clock(base_addr, 1); } } -int enable_lcdif_clock(u32 base_addr) +int enable_lcdif_clock(u32 base_addr, bool enable) { u32 reg = 0; u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask; @@ -796,15 +802,17 @@ int enable_lcdif_clock(u32 base_addr) MXC_CCM_CCGR3_LCDIF_PIX_MASK); writel(reg, &imx_ccm->CCGR3); - reg = readl(&imx_ccm->cscdr3); - reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK; - reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET; - writel(reg, &imx_ccm->cscdr3); + if (enable) { + reg = readl(&imx_ccm->cscdr3); + reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK; + reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET; + writel(reg, &imx_ccm->cscdr3); - reg = readl(&imx_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK | - MXC_CCM_CCGR3_LCDIF_PIX_MASK; - writel(reg, &imx_ccm->CCGR3); + reg = readl(&imx_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK | + MXC_CCM_CCGR3_LCDIF_PIX_MASK; + writel(reg, &imx_ccm->CCGR3); + } return 0; } else { @@ -820,19 +828,21 @@ int enable_lcdif_clock(u32 base_addr) reg &= ~MXC_CCM_CCGR2_LCD_MASK; writel(reg, &imx_ccm->CCGR2); - /* Select pre-mux */ - reg = readl(&imx_ccm->cscdr2); - reg &= ~lcdif_clk_sel_mask; - writel(reg, &imx_ccm->cscdr2); + if (enable) { + /* Select pre-mux */ + reg = readl(&imx_ccm->cscdr2); + reg &= ~lcdif_clk_sel_mask; + writel(reg, &imx_ccm->cscdr2); - /* Enable the LCDIF pix clock */ - reg = readl(&imx_ccm->CCGR3); - reg |= lcdif_ccgr3_mask; - writel(reg, &imx_ccm->CCGR3); + /* Enable the LCDIF pix clock */ + reg = readl(&imx_ccm->CCGR3); + reg |= lcdif_ccgr3_mask; + writel(reg, &imx_ccm->CCGR3); - reg = readl(&imx_ccm->CCGR2); - reg |= MXC_CCM_CCGR2_LCD_MASK; - writel(reg, &imx_ccm->CCGR2); + reg = readl(&imx_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_LCD_MASK; + writel(reg, &imx_ccm->CCGR2); + } return 0; } diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index ed1433e..2d9c45e 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -74,7 +74,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); -int enable_lcdif_clock(u32 base_addr); +int enable_lcdif_clock(u32 base_addr, bool enable); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); void mxs_set_lcdclk(u32 base_addr, u32 freq); diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 965e511..0460cd9 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -504,7 +504,7 @@ static iomux_v3_cfg_t const lcd_pads[] = { static int setup_lcd(void) { - enable_lcdif_clock(LCDIF1_BASE_ADDR); + enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 399bad2..b28ce10 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -600,7 +600,7 @@ static iomux_v3_cfg_t const lcd_pads[] = { static int setup_lcd(void) { - enable_lcdif_clock(LCDIF1_BASE_ADDR); + enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); -- cgit v0.10.2 From dfca246f4cbc46b5bb714b611dcbd3f5eae3b1e6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:29 +0800 Subject: imx: mx6sll: add clock support Add clock support for i.MX6SLL. Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index de3665f..fa54c95 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -171,6 +171,8 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) reg &= ~mask; __raw_writel(reg, &imx_ccm->CCGR2); } else { + if (is_mx6sll()) + return -EINVAL; if (is_mx6sx() || is_mx6ul() || is_mx6ull()) { mask = MXC_CCM_CCGR6_I2C4_MASK; addr = &imx_ccm->CCGR6; @@ -382,7 +384,7 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf; reg = __raw_readl(&imx_ccm->cscmr1); - if (is_mx6sl() || is_mx6sx() || + if (is_mx6sll() || is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() || is_mx6ull()) { if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) return MXC_HCLK; /* OSC 24Mhz */ @@ -400,7 +402,7 @@ static u32 get_uart_clk(void) reg = __raw_readl(&imx_ccm->cscdr1); if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() || - is_mx6ull()) { + is_mx6sll() || is_mx6ull()) { if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) freq = MXC_HCLK; } @@ -420,7 +422,7 @@ static u32 get_cspi_clk(void) MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() || - is_mx6ull()) { + is_mx6sll() || is_mx6ull()) { if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) return MXC_HCLK / (cspi_podf + 1); } @@ -482,7 +484,8 @@ static u32 get_mmdc_ch0_clk(void) u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div; - if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) { + if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || + is_mx6sll()) { podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { @@ -625,7 +628,8 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) debug("mxs_set_lcdclk, freq = %dKHz\n", freq); - if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) { + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() && + !is_mx6sll()) { debug("This chip not support lcd!\n"); return; } @@ -783,7 +787,7 @@ int enable_lcdif_clock(u32 base_addr, bool enable) MXC_CCM_CCGR3_DISP_AXI_MASK) : (MXC_CCM_CCGR3_LCDIF1_PIX_MASK | MXC_CCM_CCGR3_DISP_AXI_MASK); - } else if (is_mx6ul() || is_mx6ull()) { + } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) { if (base_addr != LCDIF1_BASE_ADDR) { puts("Wrong LCD interface!\n"); return -EINVAL; @@ -981,6 +985,16 @@ static u32 get_usdhc_clk(u32 port) u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1); u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1); + if (is_mx6ul() || is_mx6ull()) { + if (port > 1) + return 0; + } + + if (is_mx6sll()) { + if (port > 2) + return 0; + } + switch (port) { case 0: usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> @@ -1144,7 +1158,7 @@ void hab_caam_clock_enable(unsigned char enable) { u32 reg; - if (is_mx6ull()) { + if (is_mx6ull() || is_mx6sll()) { /* CG5, DCP clock */ reg = __raw_readl(&imx_ccm->CCGR0); if (enable) -- cgit v0.10.2 From a472e9bd6a51d67de38ca8fe65e1df344d19849e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:30 +0800 Subject: imx-common: cache: configure L2 Cache for i.MX6SLL If L2 cache configured as OCRAM, reset it. Switch to use runtime check. Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c index b775488..1c4a9a2 100644 --- a/arch/arm/imx-common/cache.c +++ b/arch/arm/imx-common/cache.c @@ -8,6 +8,7 @@ #include #include #include +#include #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) @@ -39,6 +40,7 @@ void enable_caches(void) void v7_outer_cache_enable(void) { struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; unsigned int val; @@ -55,15 +57,14 @@ void v7_outer_cache_enable(void) */ setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); -#if defined CONFIG_MX6SL - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - val = readl(&iomux->gpr[11]); - if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { - /* L2 cache configured as OCRAM, reset it */ - val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; - writel(val, &iomux->gpr[11]); + if (is_mx6sl() || is_mx6sll()) { + val = readl(&iomux->gpr[11]); + if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { + /* L2 cache configured as OCRAM, reset it */ + val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; + writel(val, &iomux->gpr[11]); + } } -#endif writel(0x132, &pl310->pl310_tag_latency_ctrl); writel(0x132, &pl310->pl310_data_latency_ctrl); -- cgit v0.10.2 From 2cc021697b2eebca161b0f18e4acf3f5a2d209d9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:31 +0800 Subject: imx: mx6sll: add Kconfig entry for i.MX6SLL add Kconfig entry for i.MX6SLL Signed-off-by: Peng Fan diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 87978a3..ba33d4c 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -26,6 +26,10 @@ config MX6SX select ROM_UNIFIED_SECTIONS bool +config MX6SLL + select ROM_UNIFIED_SECTIONS + bool + config MX6UL select SYS_L2CACHE_OFF select ROM_UNIFIED_SECTIONS -- cgit v0.10.2 From 0114011986547af14a9c4141e058c5ce30424f88 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:32 +0800 Subject: mx6_common: correct loadaddr and text base for i.MX6SLL Correct loadaddr and text base for i.MX6SLL Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index d28654b..e79ec21 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -44,7 +44,8 @@ #define CONFIG_REVISION_TAG /* Boot options */ -#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL)) +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL)) #define CONFIG_LOADADDR 0x82000000 #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x87800000 -- cgit v0.10.2 From b2ebdd85d9a865d2baf6664e09e32ad583d739aa Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:33 +0800 Subject: OCOTP: Update OCOTP driver to support i.MX6SLL Add the i.MX6SLL support to OCOTP driver. The i.MX6SLL reuses the i.MX6ULL fuse, bank 7 and bank8 have 4 words each, and there is a hole between bank 5 and bank 6. Signed-off-by: Ye Li Signed-off-by: Peng Fan diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 8a100c1..0b1c050 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -62,7 +62,7 @@ #define FUSE_BANK_SIZE 0x80 #ifdef CONFIG_MX6SL #define FUSE_BANKS 8 -#elif defined(CONFIG_MX6ULL) +#elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) #define FUSE_BANKS 9 #else #define FUSE_BANKS 16 @@ -79,7 +79,7 @@ /* * There is a hole in shadow registers address map of size 0x100 * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX, - * iMX6UL and i.MX6ULL. + * iMX6UL, i.MX6ULL and i.MX6SLL. * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, * we should account for this hole in address space. * @@ -100,8 +100,8 @@ u32 fuse_bank_physical(int index) if (is_mx6sl()) { phy_index = index; - } else if (is_mx6ul() || is_mx6ull()) { - if (is_mx6ull() && index == 8) + } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) { + if ((is_mx6ull() || is_mx6sll()) && index == 8) index = 7; if (index >= 6) @@ -121,7 +121,7 @@ u32 fuse_bank_physical(int index) u32 fuse_word_physical(u32 bank, u32 word_index) { - if (is_mx6ull()) { + if (is_mx6ull() || is_mx6sll()) { if (bank == 8) word_index = word_index + 4; } @@ -164,10 +164,10 @@ static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, return -EINVAL; } - if (is_mx6ull()) { + if (is_mx6ull() || is_mx6sll()) { if ((bank == 7 || bank == 8) && word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) { - printf("mxc_ocotp %s(): Invalid argument on 6ULL\n", caller); + printf("mxc_ocotp %s(): Invalid argument\n", caller); return -EINVAL; } } @@ -271,7 +271,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, #else u32 addr; /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */ - if ((is_mx6ull()) && (bank > 7)) { + if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) { bank = bank - 1; word += 4; } -- cgit v0.10.2 From 003db98ba6bd7cc833bbd79ba28ca1f25e9f3d0e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:34 +0800 Subject: imx-common: lcdif: update lcdif regs for i.MX6SL/SLL Update lcdif regs for i.MX6SL/SLL Signed-off-by: Ye.Li Signed-off-by: Peng Fan diff --git a/arch/arm/include/asm/imx-common/regs-lcdif.h b/arch/arm/include/asm/imx-common/regs-lcdif.h index 5a4f61f..ab147b5 100644 --- a/arch/arm/include/asm/imx-common/regs-lcdif.h +++ b/arch/arm/include/asm/imx-common/regs-lcdif.h @@ -20,7 +20,7 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX7) + defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -56,7 +56,7 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX7) + defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ @@ -64,7 +64,8 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */ mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */ mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */ -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) mxs_reg_32(hw_lcdif_thres) mxs_reg_32(hw_lcdif_as_ctrl) mxs_reg_32(hw_lcdif_as_buf) -- cgit v0.10.2 From ef0afaa083867f0d0ab2e6440c90161da8633f40 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:35 +0800 Subject: pinctrl: imx6: support i.MX6SLL There two iomuxc for i.MX6SLL. One is normal IOMUXC, the other is for IOMUXC_SNVS. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Simon Glass Reviewed-by: Simon Glass diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c index 32b4754..4488b16 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx6.c +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -28,6 +28,8 @@ static const struct udevice_id imx6_pinctrl_match[] = { { .compatible = "fsl,imx6q-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, { .compatible = "fsl,imx6dl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, { .compatible = "fsl,imx6sl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, + { .compatible = "fsl,imx6sll-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info }, + { .compatible = "fsl,imx6sll-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, { .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, { .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info }, -- cgit v0.10.2 From 3445373691bae4f2000b26df091a406f395df01d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:36 +0800 Subject: arm: dts: add i.MX6SLL device tree Add i.MX6SLL device tree. Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/dts/imx6sll-pinfunc.h b/arch/arm/dts/imx6sll-pinfunc.h new file mode 100644 index 0000000..5a3700b --- /dev/null +++ b/arch/arm/dts/imx6sll-pinfunc.h @@ -0,0 +1,882 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX6SLL_PINFUNC_H +#define __DTS_IMX6SLL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0 +#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0 +#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0 +#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0 +#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0 +#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0 +#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1 +#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1 +#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0 +#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1 +#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0 +#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0 +#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1 +#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1 +#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0 +#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1 +#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0 +#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1 +#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1 +#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2 +#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1 +#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1 +#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1 +#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2 +#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1 +#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1 +#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0 +#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3 +#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1 +#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1 +#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3 +#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3 +#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1 +#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0 +#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2 +#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5 +#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3 +#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4 +#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3 +#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2 +#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2 +#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1 +#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1 +#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1 +#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2 +#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3 +#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2 +#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1 +#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1 +#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0 +#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1 +#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1 +#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1 +#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0 +#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1 +#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1 +#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0 +#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1 +#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4 +#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6 +#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1 +#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5 +#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7 +#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0 +#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0 +#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0 +#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1 +#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0 +#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0 +#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3 +#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2 +#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2 +#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3 +#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1 +#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3 +#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2 +#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0 +#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3 +#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2 +#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3 +#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2 +#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2 +#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6 +#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7 +#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4 +#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3 +#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5 +#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1 +#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1 +#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1 +#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1 +#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1 +#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1 +#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0 +#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0 +#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0 +#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0 +#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0 +#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1 +#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1 +#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0 +#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2 +#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0 + +#endif /* __DTS_IMX6SLL_PINFUNC_H */ diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi new file mode 100644 index 0000000..349c47a --- /dev/null +++ b/arch/arm/dts/imx6sll.dtsi @@ -0,0 +1,859 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include "imx6sll-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1225000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1225000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + fsl,low-power-run; + clocks = <&clks IMX6SLL_CLK_ARM>, + <&clks IMX6SLL_CLK_PLL2_PFD2>, + <&clks IMX6SLL_CLK_STEP>, + <&clks IMX6SLL_CLK_PLL1_SW>, + <&clks IMX6SLL_CLK_PLL1_SYS>, + <&clks IMX6SLL_CLK_PLL1>, + <&clks IMX6SLL_PLL1_BYPASS>, + <&clks IMX6SLL_PLL1_BYPASS_SRC>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock@3 { + compatible = "fixed-clock"; + reg = <3>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>, + <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>, + <&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>, + <&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>, + <&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>, + <&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>, + <&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>, + <&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>, + <&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>, + <&clks IMX6SLL_CLK_PLL1>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + }; + + ocram: sram@00905000 { + compatible = "mmio-sram"; + reg = <0x00905000 0x1B000>; + }; + + L2: l2-cache@00a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + }; + + aips1: aips-bus@02000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba: spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@02004000 { + compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = ; + dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, + <&clks IMX6SLL_CLK_OSC>, + <&clks IMX6SLL_CLK_SPDIF>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_IPG>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "dma"; + status = "disabled"; + }; + + ecspi1: ecspi@02008000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = ; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI1>, + <&clks IMX6SLL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@0200c000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = ; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI2>, + <&clks IMX6SLL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@02010000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = ; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI3>, + <&clks IMX6SLL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: ecspi@02014000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = ; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI4>, + <&clks IMX6SLL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@02018000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts =; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART4_IPG>, + <&clks IMX6SLL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@02020000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART1_IPG>, + <&clks IMX6SLL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@02024000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02024000 0x4000>; + interrupts = ; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART2_IPG>, + <&clks IMX6SLL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi1: ssi@02028000 { + compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi"; + reg = <0x02028000 0x4000>; + interrupts = ; + dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, + <&clks IMX6SLL_CLK_SSI1>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi2: ssi2@0202c000 { + compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = ; + dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, + <&clks IMX6SLL_CLK_SSI2>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi3: ssi@02030000 { + compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi"; + reg = <0x02030000 0x4000>; + interrupts = ; + dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, + <&clks IMX6SLL_CLK_SSI3>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + uart3: serial@02034000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02034000 0x4000>; + interrupts = ; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-name = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART3_IPG>, + <&clks IMX6SLL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + pwm1: pwm@02080000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM1>, + <&clks IMX6SLL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm2: pwm@02084000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM2>, + <&clks IMX6SLL_CLK_PWM2>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm3: pwm@02088000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM3>, + <&clks IMX6SLL_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm4: pwm@0208c000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM4>, + <&clks IMX6SLL_CLK_PWM4>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + gpt1: gpt@02098000 { + compatible = "fsl,imx6sll-gpt"; + reg = <0x02098000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_GPT_BUS>, + <&clks IMX6SLL_CLK_GPT_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@020b0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: kpp@020b8000 { + compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_KPP>; + status = "disabled"; + }; + + wdog1: wdog@020bc000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_WDOG1>; + }; + + wdog2: wdog@020c0000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: ccm@020c4000 { + compatible = "fsl,imx6sll-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; + + anatop: anatop@020c8000 { + compatible = "fsl,imx6sll-anatop", + "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x4000>; + interrupts = , + , + ; + + reg_3p0: regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + }; + + tempmon: tempmon { + compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; + interrupts = ; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; + status = "disabled"; + }; + + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY2>; + phy-reg_3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , ; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x61>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup; + }; + }; + + epit1: epit@020d0000 { + reg = <0x020d0000 0x4000>; + interrupts = ; + }; + + epit2: epit@020d4000 { + reg = <0x020d4000 0x4000>; + interrupts = ; + }; + + src: src@020d8000 { + compatible = "fsl,imx6sll-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = , + ; + #reset-cells = <1>; + }; + + gpc: gpc@020dc000 { + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6sll-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@020e4000 { + compatible = "fsl,imx6sll-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + csi: csi@020e8000 { + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; + reg = <0x020e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_CSI>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + sdma: sdma@020ec000 { + compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_SDMA>, + <&clks IMX6SLL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + iram = <&ocram>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + pxp: pxp@020f0000 { + compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; + reg = <0x020f0000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_PXP>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + epdc: epdc@020f4000 { + compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc"; + reg = <0x020f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, <&clks IMX6SLL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; + status = "disabled"; + }; + + lcdif: lcdif@020f8000 { + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; + reg = <0x020f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, + <&clks IMX6SLL_CLK_LCDIF_APB>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + dcp: dcp@020fc000 { + compatible = "fsl,imx6sl-dcp"; + reg = <0x020fc000 0x4000>; + interrupts = , + , + ; + clocks = <&clks IMX6SLL_CLK_DCP>; + clock-names = "dcp"; + }; + }; + + aips2: aips-bus@02100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@02184000 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@02184200 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + usdhc1: usdhc@02190000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc2: usdhc@02194000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc3: usdhc@02198000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + i2c1: i2c@021a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@021a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@021a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C3>; + status = "disabled"; + }; + + romcp@021ac000 { + compatible = "fsl,imx6sll-romcp", "syscon"; + reg = <0x021ac000 0x4000>; + }; + + mmdc: mmdc@021b0000 { + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + rngb: rngb@021b4000 { + compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng"; + reg = <0x021b4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_DUMMY>; + }; + + ocotp: ocotp-ctrl@021bc000 { + compatible = "fsl,imx6sll-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SLL_CLK_OCOTP>; + }; + + csu: csu@021c0000 { + compatible = "fsl,imx6sll-csu"; + reg = <0x021c0000 0x4000>; + interrupts = ; + status = "disabled"; + }; + + snvs_gpr: snvs-gpr@0x021c4000 { + compatible = "fsl, imx6sll-snvs-gpr"; + reg = <0x021c4000 0x10000>; + }; + + iomuxc_snvs: iomuxc-snvs@021c8000 { + compatible = "fsl,imx6sll-iomuxc-snvs"; + reg = <0x021c80000 0x10000>; + }; + + audmux: audmux@021d8000 { + compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + + uart5: serial@021f4000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts =; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART5_IPG>, + <&clks IMX6SLL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h new file mode 100644 index 0000000..39c2567 --- /dev/null +++ b/include/dt-bindings/clock/imx6sll-clock.h @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H +#define __DT_BINDINGS_CLOCK_IMX6SLL_H + +#define IMX6SLL_CLK_DUMMY 0 +#define IMX6SLL_CLK_CKIL 1 +#define IMX6SLL_CLK_OSC 2 +#define IMX6SLL_PLL1_BYPASS_SRC 3 +#define IMX6SLL_PLL2_BYPASS_SRC 4 +#define IMX6SLL_PLL3_BYPASS_SRC 5 +#define IMX6SLL_PLL4_BYPASS_SRC 6 +#define IMX6SLL_PLL5_BYPASS_SRC 7 +#define IMX6SLL_PLL6_BYPASS_SRC 8 +#define IMX6SLL_PLL7_BYPASS_SRC 9 +#define IMX6SLL_CLK_PLL1 10 +#define IMX6SLL_CLK_PLL2 11 +#define IMX6SLL_CLK_PLL3 12 +#define IMX6SLL_CLK_PLL4 13 +#define IMX6SLL_CLK_PLL5 14 +#define IMX6SLL_CLK_PLL6 15 +#define IMX6SLL_CLK_PLL7 16 +#define IMX6SLL_PLL1_BYPASS 17 +#define IMX6SLL_PLL2_BYPASS 18 +#define IMX6SLL_PLL3_BYPASS 19 +#define IMX6SLL_PLL4_BYPASS 20 +#define IMX6SLL_PLL5_BYPASS 21 +#define IMX6SLL_PLL6_BYPASS 22 +#define IMX6SLL_PLL7_BYPASS 23 +#define IMX6SLL_CLK_PLL1_SYS 24 +#define IMX6SLL_CLK_PLL2_BUS 25 +#define IMX6SLL_CLK_PLL3_USB_OTG 26 +#define IMX6SLL_CLK_PLL4_AUDIO 27 +#define IMX6SLL_CLK_PLL5_VIDEO 28 +#define IMX6SLL_CLK_PLL6_ENET 29 +#define IMX6SLL_CLK_PLL7_USB_HOST 30 +#define IMX6SLL_CLK_USBPHY1 31 +#define IMX6SLL_CLK_USBPHY2 32 +#define IMX6SLL_CLK_USBPHY1_GATE 33 +#define IMX6SLL_CLK_USBPHY2_GATE 34 +#define IMX6SLL_CLK_PLL2_PFD0 35 +#define IMX6SLL_CLK_PLL2_PFD1 36 +#define IMX6SLL_CLK_PLL2_PFD2 37 +#define IMX6SLL_CLK_PLL2_PFD3 38 +#define IMX6SLL_CLK_PLL3_PFD0 39 +#define IMX6SLL_CLK_PLL3_PFD1 40 +#define IMX6SLL_CLK_PLL3_PFD2 41 +#define IMX6SLL_CLK_PLL3_PFD3 42 +#define IMX6SLL_CLK_PLL4_POST_DIV 43 +#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 +#define IMX6SLL_CLK_PLL5_POST_DIV 45 +#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 +#define IMX6SLL_CLK_PLL2_198M 47 +#define IMX6SLL_CLK_PLL3_120M 48 +#define IMX6SLL_CLK_PLL3_80M 49 +#define IMX6SLL_CLK_PLL3_60M 50 +#define IMX6SLL_CLK_STEP 51 +#define IMX6SLL_CLK_PLL1_SW 52 +#define IMX6SLL_CLK_AXI_ALT_SEL 53 +#define IMX6SLL_CLK_AXI_SEL 54 +#define IMX6SLL_CLK_PERIPH_PRE 55 +#define IMX6SLL_CLK_PERIPH2_PRE 56 +#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 +#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 +#define IMX6SLL_CLK_PERCLK_SEL 59 +#define IMX6SLL_CLK_USDHC1_SEL 60 +#define IMX6SLL_CLK_USDHC2_SEL 61 +#define IMX6SLL_CLK_USDHC3_SEL 62 +#define IMX6SLL_CLK_SSI1_SEL 63 +#define IMX6SLL_CLK_SSI2_SEL 64 +#define IMX6SLL_CLK_SSI3_SEL 65 +#define IMX6SLL_CLK_PXP_SEL 66 +#define IMX6SLL_CLK_LCDIF_PRE_SEL 67 +#define IMX6SLL_CLK_LCDIF_SEL 68 +#define IMX6SLL_CLK_EPDC_PRE_SEL 69 +#define IMX6SLL_CLK_SPDIF_SEL 70 +#define IMX6SLL_CLK_ECSPI_SEL 71 +#define IMX6SLL_CLK_UART_SEL 72 +#define IMX6SLL_CLK_ARM 73 +#define IMX6SLL_CLK_PERIPH 74 +#define IMX6SLL_CLK_PERIPH2 75 +#define IMX6SLL_CLK_PERIPH2_CLK2 76 +#define IMX6SLL_CLK_PERIPH_CLK2 77 +#define IMX6SLL_CLK_MMDC_PODF 78 +#define IMX6SLL_CLK_AXI_PODF 79 +#define IMX6SLL_CLK_AHB 80 +#define IMX6SLL_CLK_IPG 81 +#define IMX6SLL_CLK_PERCLK 82 +#define IMX6SLL_CLK_USDHC1_PODF 83 +#define IMX6SLL_CLK_USDHC2_PODF 84 +#define IMX6SLL_CLK_USDHC3_PODF 85 +#define IMX6SLL_CLK_SSI1_PRED 86 +#define IMX6SLL_CLK_SSI2_PRED 87 +#define IMX6SLL_CLK_SSI3_PRED 88 +#define IMX6SLL_CLK_SSI1_PODF 89 +#define IMX6SLL_CLK_SSI2_PODF 90 +#define IMX6SLL_CLK_SSI3_PODF 91 +#define IMX6SLL_CLK_PXP_PODF 92 +#define IMX6SLL_CLK_LCDIF_PRED 93 +#define IMX6SLL_CLK_LCDIF_PODF 94 +#define IMX6SLL_CLK_EPDC_SEL 95 +#define IMX6SLL_CLK_EPDC_PODF 96 +#define IMX6SLL_CLK_SPDIF_PRED 97 +#define IMX6SLL_CLK_SPDIF_PODF 98 +#define IMX6SLL_CLK_ECSPI_PODF 99 +#define IMX6SLL_CLK_UART_PODF 100 + +/* CCGR 0 */ +#define IMX6SLL_CLK_AIPSTZ1 101 +#define IMX6SLL_CLK_AIPSTZ2 102 +#define IMX6SLL_CLK_DCP 103 +#define IMX6SLL_CLK_UART2_IPG 104 +#define IMX6SLL_CLK_UART2_SERIAL 105 + +/* CCGR 1 */ +#define IMX6SLL_CLK_ECSPI1 106 +#define IMX6SLL_CLK_ECSPI2 107 +#define IMX6SLL_CLK_ECSPI3 108 +#define IMX6SLL_CLK_ECSPI4 109 +#define IMX6SLL_CLK_UART3_IPG 110 +#define IMX6SLL_CLK_UART3_SERIAL 111 +#define IMX6SLL_CLK_UART4_IPG 112 +#define IMX6SLL_CLK_UART4_SERIAL 113 +#define IMX6SLL_CLK_EPIT1 114 +#define IMX6SLL_CLK_EPIT2 115 +#define IMX6SLL_CLK_GPT_BUS 116 +#define IMX6SLL_CLK_GPT_SERIAL 117 + +/* CCGR2 */ +#define IMX6SLL_CLK_CSI 118 +#define IMX6SLL_CLK_I2C1 119 +#define IMX6SLL_CLK_I2C2 120 +#define IMX6SLL_CLK_I2C3 121 +#define IMX6SLL_CLK_OCOTP 122 +#define IMX6SLL_CLK_LCDIF_APB 123 +#define IMX6SLL_CLK_PXP 124 + +/* CCGR3 */ +#define IMX6SLL_CLK_UART5_IPG 125 +#define IMX6SLL_CLK_UART5_SERIAL 126 +#define IMX6SLL_CLK_EPDC_AXI 127 +#define IMX6SLL_CLK_EPDC_PIX 128 +#define IMX6SLL_CLK_LCDIF_PIX 129 +#define IMX6SLL_CLK_WDOG1 130 +#define IMX6SLL_CLK_MMDC_P0_FAST 131 +#define IMX6SLL_CLK_MMDC_P0_IPG 132 +#define IMX6SLL_CLK_OCRAM 133 + +/* CCGR4 */ +#define IMX6SLL_CLK_PWM1 134 +#define IMX6SLL_CLK_PWM2 135 +#define IMX6SLL_CLK_PWM3 136 +#define IMX6SLL_CLK_PWM4 137 + +/* CCGR 5 */ +#define IMX6SLL_CLK_ROM 138 +#define IMX6SLL_CLK_SDMA 139 +#define IMX6SLL_CLK_KPP 140 +#define IMX6SLL_CLK_WDOG2 141 +#define IMX6SLL_CLK_SPBA 142 +#define IMX6SLL_CLK_SPDIF 143 +#define IMX6SLL_CLK_SPDIF_GCLK 144 +#define IMX6SLL_CLK_SSI1 145 +#define IMX6SLL_CLK_SSI1_IPG 146 +#define IMX6SLL_CLK_SSI2 147 +#define IMX6SLL_CLK_SSI2_IPG 148 +#define IMX6SLL_CLK_SSI3 149 +#define IMX6SLL_CLK_SSI3_IPG 150 +#define IMX6SLL_CLK_UART1_IPG 151 +#define IMX6SLL_CLK_UART1_SERIAL 152 + +/* CCGR 6 */ +#define IMX6SLL_CLK_USBOH3 153 +#define IMX6SLL_CLK_USDHC1 154 +#define IMX6SLL_CLK_USDHC2 155 +#define IMX6SLL_CLK_USDHC3 156 + +#define IMX6SLL_CLK_IPP_DI0 157 +#define IMX6SLL_CLK_IPP_DI1 158 +#define IMX6SLL_CLK_LDB_DI0_SEL 159 +#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 +#define IMX6SLL_CLK_LDB_DI0_DIV_7 161 +#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 +#define IMX6SLL_CLK_LDB_DI0 163 +#define IMX6SLL_CLK_LDB_DI1_SEL 164 +#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 +#define IMX6SLL_CLK_LDB_DI1_DIV_7 166 +#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 +#define IMX6SLL_CLK_LDB_DI1 168 +#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 +#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 +#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 +#define IMX6SLL_CLK_EXTERN_AUDIO 172 + +#define IMX6SLL_CLK_END 173 + +#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ -- cgit v0.10.2 From 47f73504d8a826a7a0c54aed974ff5457aa4c8b8 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:37 +0800 Subject: arm: imx: add i.MX6SLL EVK board support Add i.MX6SLL EVK board support. 1. Add imx6sll-evk device tree. 2. Enable SDHC/I2C/UART. 3. Enable REGULATOR/PMIC/I2C/GPIO/SDHC/PINCTRL driver. Boot Log: U-Boot 2016.11-00127-gc635871-dirty (Nov 24 2016 - 13:28:19 +0800) CPU: Freescale i.MX6SLL rev1.0 at 792MHz CPU: Commercial temperature grade (0C to 95C)Reset cause: POR Model: Freescale i.MX6SLL EVK Board Board: MX6SLL EVK DRAM: 2 GiB i2c bus 0 at 35258368, no gpio pinctrl state. PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index ba33d4c..eefe629 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -146,6 +146,12 @@ config TARGET_MX6SLEVK bool "mx6slevk" select SUPPORT_SPL +config TARGET_MX6SLLEVK + bool "mx6sll evk" + select MX6SLL + select DM + select DM_THERMAL + config TARGET_MX6SXSABRESD bool "mx6sxsabresd" select MX6SX @@ -283,6 +289,7 @@ source "board/freescale/mx6qarm2/Kconfig" source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" +source "board/freescale/mx6sllevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f437469..fde1232 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -294,6 +294,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ bk4r1.dtb dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ + imx6sll-evk.dtb \ imx6dl-icore.dtb \ imx6q-icore.dtb diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts new file mode 100644 index 0000000..b4af007 --- /dev/null +++ b/arch/arm/dts/imx6sll-evk.dts @@ -0,0 +1,801 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" + +/ { + model = "Freescale i.MX6SLL EVK Board"; + compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + + memory { + reg = <0x80000000 0x80000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio4 13 1>; + uok_input = <&gpio4 13 1>; + chg_input = <&gpio4 15 1>; + flt_input = <&gpio4 14 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,adc_disable; + status = "okay"; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_aud3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; + + reg_lcd: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-pwr"; + gpio = <&gpio4 8 0>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC-VCCQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + reg_sd3_vmmc: sd3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD3_WIFI"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; + + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio4 24 1>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <393216000>; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "okay"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* 2's-compliment, -4325000 */ + regulator-min-microvolt = <0xffbe0178>; + /* 2's-compliment, -500000 */ + regulator-max-microvolt = <0xfff85ee0>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + amic-mono; + }; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6sll-evk { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 + MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059 + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 + /* + * Must set the LVE of pad SD2_RESET, otherwise current + * leakage through eMMC chip will pull high the VCCQ to + * 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch. + */ + MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059 + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */ + MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */ + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ + /* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */ + MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088 + MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088 + MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088 + MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088 + MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088 + MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088 + MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088 + MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088 + MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088 + MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088 + MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088 + MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088 + MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1 + MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1 + MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1 + MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1 + MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1 + MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1 + MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1 + MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1 + MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1 + MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1 + MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1 + MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1 + MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1 + MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1 + MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1 + MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1 + MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1 + MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1 + MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1 + MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1 + MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1 + MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1 + MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1 + MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1 + MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 + MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 + MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 + MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 + MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 + MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 + MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 + MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 + MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 + MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 + MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 + MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 + MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */ + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */ + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */ + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */ + MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */ + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x4130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1 /* bt reg on */ + MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1 + MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1 + MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1 + MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13059 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 + MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + lcd-supply = <®_lcd>; + display = <&display>; + status = "okay"; + + display: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pxp { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vqmmc-supply = <®_sd2_vmmc>; + bus-width = <8>; + no-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; diff --git a/board/freescale/mx6sllevk/Kconfig b/board/freescale/mx6sllevk/Kconfig new file mode 100644 index 0000000..4ba9bbf --- /dev/null +++ b/board/freescale/mx6sllevk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6SLLEVK + +config SYS_BOARD + default "mx6sllevk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6sllevk" + +endif diff --git a/board/freescale/mx6sllevk/Makefile b/board/freescale/mx6sllevk/Makefile new file mode 100644 index 0000000..667fcb0 --- /dev/null +++ b/board/freescale/mx6sllevk/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sllevk.o diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg new file mode 100644 index 0000000..53fb74f --- /dev/null +++ b/board/freescale/mx6sllevk/imximage.cfg @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E0550 0x00080000 +DATA 4 0x020E0534 0x00000000 +DATA 4 0x020E02AC 0x00000030 +DATA 4 0x020E0548 0x00000030 +DATA 4 0x020E052C 0x00000030 +DATA 4 0x020E0530 0x00020000 +DATA 4 0x020E02B0 0x00003030 +DATA 4 0x020E02B4 0x00003030 +DATA 4 0x020E02B8 0x00003030 +DATA 4 0x020E02BC 0x00003030 +DATA 4 0x020E0540 0x00020000 +DATA 4 0x020E0544 0x00000030 +DATA 4 0x020E054C 0x00000030 +DATA 4 0x020E0554 0x00000030 +DATA 4 0x020E0558 0x00000030 +DATA 4 0x020E0294 0x00000030 +DATA 4 0x020E0298 0x00000030 +DATA 4 0x020E029C 0x00000030 +DATA 4 0x020E02A0 0x00000030 +DATA 4 0x020E02C0 0x00082030 + +DATA 4 0x021B001C 0x00008000 + +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B085c 0x084700C7 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B0848 0x3F393B3C +DATA 4 0x021B0850 0x262C3826 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B0824 0x33333333 +DATA 4 0x021B0828 0x33333333 + +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B0834 0xf3333333 +DATA 4 0x021B0838 0xf3333333 +DATA 4 0x021B08C0 0x24922492 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B000C 0x53574333 +DATA 4 0x021B0010 0x00100B22 +DATA 4 0x021B0038 0x00170778 +DATA 4 0x021B0014 0x00C700DB +DATA 4 0x021B0018 0x00201718 +DATA 4 0x021B002C 0x0F9F26D2 +DATA 4 0x021B0030 0x009F0E10 +DATA 4 0x021B0040 0x0000005F +DATA 4 0x021B0000 0xC4190000 + +DATA 4 0x021B083C 0x20000000 + +DATA 4 0x021B001C 0x00008050 +DATA 4 0x021B001C 0x00008058 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0x003F8038 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0xFF0A8038 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x04028038 +DATA 4 0x021B001C 0x83018030 +DATA 4 0x021B001C 0x83018038 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B001C 0x01038038 + +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c new file mode 100644 index 0000000..74a27a3 --- /dev/null +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_DM_PMIC_PFUZE100 +int power_init_board(void) +{ + struct udevice *dev; + int ret; + u32 dev_id, rev_id, i; + u32 switch_num = 6; + u32 offset = PFUZE100_SW1CMODE; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return 0; + + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + + /* Init mode to APS_PFM */ + pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); + + for (i = 0; i < switch_num - 1; i++) + pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); + + /* set SW1AB staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); + + /* set SW1C staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6SLL EVK\n"); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno; +} diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig new file mode 100644 index 0000000..8ae049e --- /dev/null +++ b/configs/mx6sllevk_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLLEVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h new file mode 100644 index 0000000..b9f25cf --- /dev/null +++ b/include/configs/mx6sllevk.h @@ -0,0 +1,152 @@ +/* + * Copyright 2013-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SL EVK board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* I2C Configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "epdc_waveform=epdc_splash.bin\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6sll-evk.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "usb start; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M) + +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_2G + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#define CONFIG_ENV_OFFSET (12 * SZ_64K) +#define CONFIG_ENV_IS_IN_MMC + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ + +#define CONFIG_IMX_THERMAL + +#define CONFIG_IOMUX_LPSR + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 8e1d92fdbc09a6a31bd2a6571d915b1c38307320 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Dec 2016 19:24:38 +0800 Subject: imx: mx6sllevk: add plugin support Add plugin support for mx6sllevk board. Signed-off-by: Peng Fan Cc: Stefano Babic diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg index 53fb74f..7d8b323 100644 --- a/board/freescale/mx6sllevk/imximage.cfg +++ b/board/freescale/mx6sllevk/imximage.cfg @@ -23,6 +23,11 @@ IMAGE_VERSION 2 BOOT_FROM sd +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sllevk/plugin.bin 0x00907000 +#else + #ifdef CONFIG_SECURE_BOOT CSF CONFIG_CSF_SIZE #endif @@ -119,3 +124,4 @@ DATA 4 0x021B0800 0xA1390003 DATA 4 0x021B0004 0x00020052 DATA 4 0x021B0404 0x00011006 DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6sllevk/plugin.S b/board/freescale/mx6sllevk/plugin.S new file mode 100644 index 0000000..f9ef35a --- /dev/null +++ b/board/freescale/mx6sllevk/plugin.S @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sll_evk_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x550] + ldr r1, =0x00000000 + str r1, [r0, #0x534] + ldr r1, =0x00000030 + str r1, [r0, #0x2AC] + str r1, [r0, #0x548] + str r1, [r0, #0x52C] + ldr r1, =0x00020000 + str r1, [r0, #0x530] + ldr r1, =0x00003030 + str r1, [r0, #0x2B0] + str r1, [r0, #0x2B4] + str r1, [r0, #0x2B8] + str r1, [r0, #0x2BC] + + ldr r1, =0x00020000 + str r1, [r0, #0x540] + ldr r1, =0x00000030 + str r1, [r0, #0x544] + str r1, [r0, #0x54C] + str r1, [r0, #0x554] + str r1, [r0, #0x558] + str r1, [r0, #0x294] + str r1, [r0, #0x298] + str r1, [r0, #0x29C] + str r1, [r0, #0x2A0] + + ldr r1, =0x00082030 + str r1, [r0, #0x2C0] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x084700C7 + str r1, [r0, #0x85C] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x3F393B3C + str r1, [r0, #0x848] + ldr r1, =0x262C3826 + str r1, [r0, #0x850] + + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + str r1, [r0, #0x824] + str r1, [r0, #0x828] + + ldr r1, =0xf3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + str r1, [r0, #0x834] + str r1, [r0, #0x838] + + ldr r1, =0x24922492 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x53574333 + str r1, [r0, #0x00C] + ldr r1, =0x00100B22 + str r1, [r0, #0x010] + ldr r1, =0x00170778 + str r1, [r0, #0x038] + ldr r1, =0x00C700DB + str r1, [r0, #0x014] + ldr r1, =0x00201718 + str r1, [r0, #0x018] + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x02C] + ldr r1, =0x009F0E10 + str r1, [r0, #0x030] + ldr r1, =0x0000005F + str r1, [r0, #0x040] + ldr r1, =0xC4190000 + str r1, [r0, #0x000] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + + ldr r1, =0x00008050 + str r1, [r0, #0x01C] + ldr r1, =0x00008058 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0x003F8038 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x04028038 + str r1, [r0, #0x01C] + ldr r1, =0x83018030 + str r1, [r0, #0x01C] + ldr r1, =0x83018038 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x01038038 + str r1, [r0, #0x01C] + + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6sll_evk_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig new file mode 100644 index 0000000..e6be979 --- /dev/null +++ b/configs/mx6sllevk_plugin_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLLEVK=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y -- cgit v0.10.2 From 98d62e618bb9475eee799b7095803285ecf3a5ae Mon Sep 17 00:00:00 2001 From: Patrick Bruenn Date: Fri, 4 Nov 2016 11:57:02 +0100 Subject: arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn diff --git a/arch/arm/cpu/armv7/mx5/Kconfig b/arch/arm/cpu/armv7/mx5/Kconfig index 9f250c6..5fb5513 100644 --- a/arch/arm/cpu/armv7/mx5/Kconfig +++ b/arch/arm/cpu/armv7/mx5/Kconfig @@ -18,11 +18,19 @@ config TARGET_USBARMORY bool "Support USB armory" select CPU_V7 +config TARGET_MX53CX9020 + bool "Support CX9020" + select CPU_V7 + select MX53 + select DM + select DM_SERIAL + endchoice config SYS_SOC default "mx5" +source "board/beckhoff/mx53cx9020/Kconfig" source "board/inversepath/usbarmory/Kconfig" endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fde1232..b8e1342 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -293,6 +293,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ pcm052.dtb \ bk4r1.dtb +dtb-$(CONFIG_MX53) += imx53-cx9020.dtb + dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6sll-evk.dtb \ imx6dl-icore.dtb \ diff --git a/arch/arm/dts/imx53-cx9020.dts b/arch/arm/dts/imx53-cx9020.dts new file mode 100644 index 0000000..9610301 --- /dev/null +++ b/arch/arm/dts/imx53-cx9020.dts @@ -0,0 +1,190 @@ +/* + * Copyright 2016 Beckhoff Automation + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/dts-v1/; +#include "imx53.dtsi" + +#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 +#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 +#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 +#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 + +/ { + model = "Beckhoff CX9020-0100 i.MX53"; + compatible = "fsl,imx53-qsb", "fsl,imx53"; + + chosen { + stdout-path = &uart2; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-qsb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 + MX53_PAD_GPIO_8__GPIO1_8 0x80000000 + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 + MX53_PAD_GPIO_1__GPIO1_1 0x80000000 + MX53_PAD_GPIO_4__GPIO1_4 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 + MX53_PAD_GPIO_16__GPIO7_11 0x80000000 + + MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 + MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x80000000 + MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x80000000 + MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 + MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x80000000 + MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x80000000 + MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x80000000 + MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x80000000 + MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x80000000 + MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 + MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x80000000 + MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x80000000 + MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x80000000 + MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x80000000 + MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x80000000 + MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x80000000 + MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x80000000 + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 + MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 + MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0xa4 + MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0xa4 + MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0xa4 + MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0xa4 + MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0xa4 + MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0xa4 + MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0xa4 + MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0xa4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0xa4 + MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0xa4 + MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0xa4 + MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0xa4 + MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0xa4 + MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0xa4 + MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0xa4 + MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0xa4 + MX53_PAD_NANDF_CLE__GPIO6_7 0x00000001 + MX53_PAD_NANDF_WP_B__GPIO6_9 0x00000001 + MX53_PAD_NANDF_ALE__GPIO6_8 0x00000001 + + MX53_PAD_EIM_D23__GPIO3_23 0x80000000 + + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + + MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec + MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec + + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 + MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4 + MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4 + MX53_PAD_EIM_D28__UART2_RTS 0x1e4 + MX53_PAD_EIM_D29__UART2_CTS 0x1e4 + >; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + uart-has-rtscts; + fsl,dte-mode; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx53-pinfunc.h b/arch/arm/dts/imx53-pinfunc.h new file mode 100644 index 0000000..aec406b --- /dev/null +++ b/arch/arm/dts/imx53-pinfunc.h @@ -0,0 +1,1189 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX53_PINFUNC_H +#define __DTS_IMX53_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 +#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 +#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 +#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 +#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 +#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 +#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 +#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0 +#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0 +#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0 +#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0 +#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1 +#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0 +#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0 +#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0 +#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0 +#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0 +#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0 +#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1 +#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0 +#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0 +#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0 +#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0 +#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0 +#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0 +#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0 +#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0 +#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0 +#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0 +#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 +#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0 +#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0 +#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0 +#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 +#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0 +#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0 +#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0 +#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0 +#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 +#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0 +#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0 +#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0 +#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 +#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0 +#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0 +#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0 +#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0 +#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0 +#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0 +#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0 +#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0 +#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 +#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0 +#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0 +#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0 +#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0 +#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0 +#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0 +#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0 +#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0 +#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0 +#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1 +#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0 +#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0 +#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1 +#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0 +#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0 +#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1 +#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0 +#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0 +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1 +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0 +#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0 +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1 +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0 +#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1 +#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0 +#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1 +#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0 +#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1 +#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0 +#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1 +#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0 +#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0 +#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0 +#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0 +#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0 +#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0 +#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0 +#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0 +#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0 +#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0 +#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0 +#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0 +#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0 +#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0 +#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0 +#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0 +#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1 +#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2 +#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0 +#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2 +#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0 +#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2 +#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0 +#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2 +#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0 +#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1 +#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0 +#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0 +#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1 +#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0 +#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1 +#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1 +#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1 +#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3 +#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3 +#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0 +#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2 +#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0 +#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0 +#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0 +#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0 +#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0 +#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1 +#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0 +#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0 +#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3 +#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1 +#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0 +#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0 +#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0 +#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0 +#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3 +#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1 +#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0 +#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0 +#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0 +#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0 +#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3 +#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0 +#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0 +#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0 +#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0 +#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1 +#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3 +#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0 +#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0 +#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0 +#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2 +#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0 +#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0 +#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0 +#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0 +#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0 +#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0 +#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1 +#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0 +#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1 +#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0 +#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0 +#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0 +#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0 +#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0 +#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1 +#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1 +#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1 +#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0 +#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0 +#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0 +#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0 +#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1 +#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0 +#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0 +#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0 +#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0 +#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1 +#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0 +#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0 +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0 +#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0 +#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0 +#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0 +#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1 +#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1 +#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1 +#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0 +#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0 +#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0 +#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0 +#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1 +#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1 +#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1 +#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1 +#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0 +#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0 +#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0 +#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0 +#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0 +#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0 +#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0 +#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0 +#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1 +#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0 +#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0 +#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0 +#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0 +#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0 +#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0 +#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0 +#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0 +#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1 +#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1 +#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1 +#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0 +#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0 +#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0 +#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0 +#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1 +#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0 +#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2 +#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0 +#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0 +#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0 +#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0 +#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0 +#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0 +#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1 +#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0 +#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0 +#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3 +#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0 +#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0 +#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0 +#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0 +#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0 +#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0 +#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0 +#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0 +#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0 +#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0 +#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0 +#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0 +#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0 +#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0 +#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0 +#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0 +#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0 +#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0 +#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0 +#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0 +#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0 +#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0 +#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0 +#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0 +#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0 +#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0 +#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0 +#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0 +#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0 +#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0 +#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0 +#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0 +#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0 +#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0 +#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0 +#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0 +#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0 +#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0 +#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0 +#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0 +#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0 +#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0 +#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0 +#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0 +#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0 +#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0 +#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0 +#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0 +#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0 +#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0 +#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0 +#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0 +#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0 +#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0 +#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2 +#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0 +#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0 +#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0 +#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2 +#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0 +#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0 +#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0 +#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2 +#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0 +#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0 +#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0 +#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0 +#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2 +#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0 +#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0 +#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0 +#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0 +#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1 +#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0 +#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0 +#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0 +#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0 +#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1 +#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1 +#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1 +#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1 +#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0 +#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0 +#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0 +#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0 +#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0 +#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0 +#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0 +#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0 +#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0 +#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0 +#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0 +#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0 +#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0 +#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0 +#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0 +#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0 +#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0 +#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0 +#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0 +#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0 +#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0 +#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0 +#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0 +#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0 +#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0 +#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0 +#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0 +#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0 +#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0 +#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0 +#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0 +#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0 +#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0 +#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0 +#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1 +#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0 +#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0 +#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1 +#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0 +#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0 +#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0 +#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0 +#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0 +#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0 +#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0 +#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0 +#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0 +#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0 +#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0 +#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1 +#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0 +#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0 +#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0 +#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0 +#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0 +#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0 +#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0 +#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1 +#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0 +#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0 +#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0 +#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0 +#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0 +#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0 +#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0 +#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0 +#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0 +#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0 +#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0 +#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1 +#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0 +#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0 +#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0 +#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0 +#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0 +#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0 +#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0 +#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0 +#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1 +#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0 +#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0 +#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0 +#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0 +#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0 +#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0 +#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0 +#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0 +#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3 +#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0 +#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0 +#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0 +#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0 +#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0 +#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0 +#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0 +#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0 +#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3 +#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0 +#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0 +#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0 +#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0 +#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0 +#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0 +#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0 +#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0 +#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0 +#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0 +#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3 +#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1 +#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0 +#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0 +#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0 +#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0 +#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0 +#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0 +#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0 +#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0 +#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0 +#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0 +#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3 +#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1 +#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0 +#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0 +#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0 +#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0 +#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0 +#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0 +#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0 +#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0 +#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0 +#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0 +#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0 +#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0 +#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0 +#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0 +#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5 +#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0 +#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0 +#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0 +#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0 +#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0 +#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0 +#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0 +#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3 +#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0 +#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0 +#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0 +#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2 +#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0 +#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3 +#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1 +#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0 +#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0 +#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0 +#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2 +#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0 +#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0 +#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0 +#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2 +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0 +#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0 +#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0 +#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0 +#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0 +#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0 +#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2 +#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0 +#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0 +#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0 +#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2 +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0 +#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0 +#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0 +#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0 +#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2 +#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1 +#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3 +#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0 +#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0 +#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0 +#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1 +#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1 +#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3 +#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1 +#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1 +#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3 +#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1 +#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1 +#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3 +#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1 +#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1 +#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4 +#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1 +#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1 +#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3 +#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0 +#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0 +#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3 +#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0 +#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0 +#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0 +#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1 +#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0 +#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2 +#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0 +#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0 +#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0 +#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0 +#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0 +#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1 +#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0 +#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2 +#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0 +#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0 +#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0 +#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1 +#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0 +#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1 +#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0 +#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1 +#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0 +#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0 +#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0 +#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1 +#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2 +#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1 +#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1 +#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0 +#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0 +#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2 +#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1 +#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0 +#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2 +#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0 +#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0 +#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0 +#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0 +#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2 +#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1 +#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0 +#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2 +#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0 +#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0 +#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0 +#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0 +#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0 +#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1 +#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0 +#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2 +#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0 +#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0 +#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0 +#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2 +#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1 +#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1 +#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0 +#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0 +#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1 +#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1 +#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1 +#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0 +#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0 +#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2 +#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5 +#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0 +#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0 +#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1 +#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1 +#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0 +#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0 +#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0 +#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1 +#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2 +#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0 +#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1 +#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0 +#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1 +#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1 +#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0 +#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0 +#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0 +#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0 +#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1 +#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1 +#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1 +#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1 +#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0 + +#endif /* __DTS_IMX53_PINFUNC_H */ diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi new file mode 100644 index 0000000..1bdf066 --- /dev/null +++ b/arch/arm/dts/imx53.dtsi @@ -0,0 +1,110 @@ +/* + * Copyright 2016 Beckhoff Automation + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "skeleton.dtsi" +#include "imx53-pinfunc.h" +#include +#include +#include +#include + +/ { + aliases { + serial1 = &uart2; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aips@50000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x10000000>; + ranges; + + iomuxc: iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + }; + + gpr: iomuxc-gpr@53fa8000 { + compatible = "fsl,imx53-iomuxc-gpr", "syscon"; + reg = <0x53fa8000 0xc>; + }; + + uart2: serial@53fc0000 { + compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + clks: ccm@53fd4000{ + compatible = "fsl,imx53-ccm"; + reg = <0x53fd4000 0x4000>; + interrupts = <0 71 0x04 0 72 0x04>; + #clock-cells = <1>; + }; + + gpio7: gpio@53fe4000 { + compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; + reg = <0x53fe4000 0x4000>; + interrupts = <107 108>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + aips@60000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x60000000 0x10000000>; + ranges; + + sdma: sdma@63fb0000 { + compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; + reg = <0x63fb0000 0x4000>; + interrupts = <6>; + clocks = <&clks IMX5_CLK_SDMA_GATE>, + <&clks IMX5_CLK_SDMA_GATE>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + + + fec: ethernet@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + }; + }; +}; diff --git a/board/beckhoff/mx53cx9020/Kconfig b/board/beckhoff/mx53cx9020/Kconfig new file mode 100644 index 0000000..dcdafb6 --- /dev/null +++ b/board/beckhoff/mx53cx9020/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX53CX9020 + +config SYS_BOARD + default "mx53cx9020" + +config SYS_VENDOR + default "beckhoff" + +config SYS_CONFIG_NAME + default "mx53cx9020" + +endif diff --git a/board/beckhoff/mx53cx9020/MAINTAINERS b/board/beckhoff/mx53cx9020/MAINTAINERS new file mode 100644 index 0000000..f84413e --- /dev/null +++ b/board/beckhoff/mx53cx9020/MAINTAINERS @@ -0,0 +1,6 @@ +MX53 CX9020 +M: Patrick Bruenn +S: Maintained +F: board/beckhoff/mx53cx9020/ +F: include/configs/mx53cx9020.h +F: configs/mx53cx9020_defconfig diff --git a/board/beckhoff/mx53cx9020/Makefile b/board/beckhoff/mx53cx9020/Makefile new file mode 100644 index 0000000..a01c0f1 --- /dev/null +++ b/board/beckhoff/mx53cx9020/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG +# Patrick Bruenn +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += mx53cx9020.o +obj-$(CONFIG_VIDEO) += mx53cx9020_video.o diff --git a/board/beckhoff/mx53cx9020/imximage.cfg b/board/beckhoff/mx53cx9020/imximage.cfg new file mode 100644 index 0000000..a11d04c --- /dev/null +++ b/board/beckhoff/mx53cx9020/imximage.cfg @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2015 Beckhoff Automation GmbH + * Patrick Bruenn + * + * Based on /board/freescale/mx53loco/imximage.cfg + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x53fa8554 0x00300000 +DATA 4 0x53fa8558 0x00300040 +DATA 4 0x53fa8560 0x00300000 +DATA 4 0x53fa8564 0x00300040 +DATA 4 0x53fa8568 0x00300040 +DATA 4 0x53fa8570 0x00300000 +DATA 4 0x53fa8574 0x00300000 +DATA 4 0x53fa8578 0x00300000 +DATA 4 0x53fa857c 0x00300040 +DATA 4 0x53fa8580 0x00300040 +DATA 4 0x53fa8584 0x00300000 +DATA 4 0x53fa8588 0x00300000 +DATA 4 0x53fa8590 0x00300040 +DATA 4 0x53fa8594 0x00300000 +DATA 4 0x53fa86f0 0x00300000 +DATA 4 0x53fa86f4 0x00000000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8718 0x00300000 +DATA 4 0x53fa871c 0x00300000 +DATA 4 0x53fa8720 0x00300000 +DATA 4 0x53fa8724 0x00000000 +DATA 4 0x53fa8728 0x00300000 +DATA 4 0x53fa872c 0x00300000 +DATA 4 0x63fd9088 0x35343535 +DATA 4 0x63fd9090 0x4d444c44 +DATA 4 0x63fd907c 0x01370138 +DATA 4 0x63fd9080 0x013b013c +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0x83190000 +DATA 4 0x63fd900c 0x40425333 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x052080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x05208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00005800 +DATA 4 0x63fd9040 0x05380003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c new file mode 100644 index 0000000..9b3ac22 --- /dev/null +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG + * Patrick Bruenn + * + * Based on /board/freescale/mx53loco/mx53loco.c + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum LED_GPIOS { + GPIO_SD1_CD = IMX_GPIO_NR(1, 1), + GPIO_SD2_CD = IMX_GPIO_NR(1, 4), + GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16), + GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17), + GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18), + GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19), + GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20), + GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21), + GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22), + GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23), + GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24), + GPIO_SUPS_INT = IMX_GPIO_NR(3, 31), + GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8), + GPIO_C3_STATUS = IMX_GPIO_NR(6, 7), + GPIO_C3_DONE = IMX_GPIO_NR(6, 9), +}; + +#define CCAT_BASE_ADDR ((void *)0xf0000000) +#define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32)) +#define CCAT_SIZE 1191788 +#define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12) +static const char CCAT_SIGNATURE[] = "CCAT"; + +static const u32 CCAT_MODE_CONFIG = 0x0024DC81; +static const u32 CCAT_MODE_RUN = 0x0033DC8F; + +DECLARE_GLOBAL_DATA_PTR; + +static uint32_t mx53_dram_size[2]; + +phys_size_t get_effective_memsize(void) +{ + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return mx53_dram_size[0]; +} + +int dram_init(void) +{ + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); + + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; +} + +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + int rev = readl(&fuse->gp[6]); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +/* + * Set CCAT mode + * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN + */ +void weim_cs0_settings(u32 mode) +{ + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; + + writel(0x0, &weim_regs->cs0gcr1); + writel(mode, &weim_regs->cs0gcr1); + writel(0x00001002, &weim_regs->cs0gcr2); + + writel(0x04000000, &weim_regs->cs0rcr1); + writel(0x00000000, &weim_regs->cs0rcr2); + + writel(0x04000000, &weim_regs->cs0wcr1); + writel(0x00000000, &weim_regs->cs0wcr2); +} + +static void setup_gpio_eim(void) +{ + gpio_direction_input(GPIO_C3_STATUS); + gpio_direction_input(GPIO_C3_DONE); + gpio_direction_output(GPIO_C3_CONFIG, 1); + + weim_cs0_settings(CCAT_MODE_RUN); +} + +static void setup_gpio_sups(void) +{ + gpio_direction_input(GPIO_SUPS_INT); + + static const int BLINK_INTERVALL = 50000; + int status = 1; + while (gpio_get_value(GPIO_SUPS_INT)) { + /* signal "CX SUPS power fail" */ + gpio_set_value(GPIO_LED_PWR_R, + (++status / BLINK_INTERVALL) % 2); + } + + /* signal "CX power up" */ + gpio_set_value(GPIO_LED_PWR_R, 1); +} + +static void setup_gpio_leds(void) +{ + gpio_direction_output(GPIO_LED_SD2_R, 0); + gpio_direction_output(GPIO_LED_SD2_B, 0); + gpio_direction_output(GPIO_LED_SD2_G, 0); + gpio_direction_output(GPIO_LED_SD1_R, 0); + gpio_direction_output(GPIO_LED_SD1_B, 0); + gpio_direction_output(GPIO_LED_SD1_G, 0); + gpio_direction_output(GPIO_LED_PWR_R, 0); + gpio_direction_output(GPIO_LED_PWR_B, 0); + gpio_direction_output(GPIO_LED_PWR_G, 0); +} + +#ifdef CONFIG_USB_EHCI_MX5 +int board_ehci_hcd_init(int port) +{ + /* request VBUS power enable pin, GPIO7_8 */ + gpio_direction_output(IMX_GPIO_NR(7, 8), 1); + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR}, + {MMC_SDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + gpio_direction_input(GPIO_SD1_CD); + gpio_direction_input(GPIO_SD2_CD); + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + ret = !gpio_get_value(GPIO_SD1_CD); + else + ret = !gpio_get_value(GPIO_SD2_CD); + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + u32 index; + int ret; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { + switch (index) { + case 0: + break; + case 1: + break; + default: + printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return -EINVAL; + } + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; +} +#endif + +static int power_init(void) +{ + /* nothing to do on CX9020 */ + return 0; +} + +static void clock_1GHz(void) +{ + int ret; + u32 ref_clk = MXC_HCLK; + /* + * After increasing voltage to 1.25V, we can switch + * CPU clock to 1GHz and DDR to 400MHz safely + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to 400MHz failed\n"); +} + +int board_early_init_f(void) +{ + setup_gpio_leds(); + setup_gpio_sups(); + setup_gpio_eim(); + setup_iomux_lcd(); + + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + mxc_set_sata_internal_clock(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: Beckhoff CX9020\n"); + + return 0; +} + +static int ccat_config_fn(int assert_config, int flush, int cookie) +{ + /* prepare FPGA for programming */ + weim_cs0_settings(CCAT_MODE_CONFIG); + gpio_set_value(GPIO_C3_CONFIG, 0); + udelay(1); + gpio_set_value(GPIO_C3_CONFIG, 1); + udelay(230); + + return FPGA_SUCCESS; +} + +static int ccat_status_fn(int cookie) +{ + return FPGA_FAIL; +} + +static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie) +{ + const uint8_t *const buffer = buf; + + /* program CCAT */ + int i; + for (i = 0; i < buf_len; ++i) + writeb(buffer[i], CCAT_BASE_ADDR); + + writeb(0xff, CCAT_BASE_ADDR); + writeb(0xff, CCAT_BASE_ADDR); + + return FPGA_SUCCESS; +} + +static int ccat_done_fn(int cookie) +{ + /* programming complete? */ + return gpio_get_value(GPIO_C3_DONE); +} + +static int ccat_post_fn(int cookie) +{ + /* switch to FPGA run mode */ + weim_cs0_settings(CCAT_MODE_RUN); + invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR); + + if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) { + printf("Verifing CCAT firmware failed, signature not found\n"); + return FPGA_FAIL; + } + + /* signal "CX booting OS" */ + gpio_set_value(GPIO_LED_PWR_R, 1); + gpio_set_value(GPIO_LED_PWR_G, 1); + gpio_set_value(GPIO_LED_PWR_B, 0); + return FPGA_SUCCESS; +} + +static Altera_CYC2_Passive_Serial_fns ccat_fns = { + .config = ccat_config_fn, + .status = ccat_status_fn, + .done = ccat_done_fn, + .write = ccat_write_fn, + .abort = ccat_post_fn, + .post = ccat_post_fn, +}; + +static Altera_desc ccat_fpga = { + .family = Altera_CYC2, + .iface = passive_serial, + .size = CCAT_SIZE, + .iface_fns = &ccat_fns, + .base = CCAT_BASE_ADDR, +}; + +int board_late_init(void) +{ + if (!power_init()) + clock_1GHz(); + + fpga_init(); + fpga_add(fpga_altera, &ccat_fpga); + + return 0; +} diff --git a/board/beckhoff/mx53cx9020/mx53cx9020_video.c b/board/beckhoff/mx53cx9020/mx53cx9020_video.c new file mode 100644 index 0000000..4da83da --- /dev/null +++ b/board/beckhoff/mx53cx9020/mx53cx9020_video.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG + * Patrick Bruenn + * + * Based on /board/freescale/mx53loco/mx53loco_video.c + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define CX9020_DVI_PWD IMX_GPIO_NR(6, 1) + +static struct fb_videomode const vga_640x480 = { + .name = "VESA_VGA_640x480", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39721, /* picosecond (25.175 MHz) */ + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +}; + +void setup_iomux_lcd(void) +{ + /* Turn on DVI_PWD */ + imx_iomux_v3_setup_pad(MX53_PAD_CSI0_DAT15__GPIO6_1); + gpio_direction_output(CX9020_DVI_PWD, 1); +} + +int board_video_skip(void) +{ + const int ret = ipuv3_fb_init(&vga_640x480, 0, IPU_PIX_FMT_RGB24); + if (ret) + printf("VESA VG 640x480 cannot be configured: %d\n", ret); + return ret; +} diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig new file mode 100644 index 0000000..6954cf5 --- /dev/null +++ b/configs/mx53cx9020_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX5=y +CONFIG_TARGET_MX53CX9020=y +CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg" +CONFIG_BOOTDELAY=1 +CONFIG_HUSH_PARSER=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +#CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_VIDEO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_MXC_UART=y +CONFIG_OF_CONTROL=y +CONFIG_FPGA_ALTERA=y +CONFIG_FPGA_CYCLON2=y +CONFIG_CMD_FPGA=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX5=y +# CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CFB_CONSOLE=y +CONFIG_VGA_AS_SINGLE_DEVICE=y +CONFIG_SYS_CONSOLE_BG_COL=0x00 +CONFIG_SYS_CONSOLE_FG_COL=0xa0 diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index f3f6bf7..a760944 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -3,6 +3,26 @@ menu "FPGA support" config FPGA bool +config FPGA_ALTERA + bool "Enable Altera FPGA drivers" + select FPGA + help + Say Y here to enable the Altera FPGA driver + + This provides basic infrastructure to support Altera FPGA devices. + Enable Altera FPGA specific functions which includes bitstream + (in BIT format), fpga and device validation. + +config FPGA_CYCLON2 + bool "Enable Altera FPGA driver for Cyclone II" + depends on FPGA_ALTERA + help + Say Y here to enable the Altera Cyclone II FPGA specific driver + + This provides common functionality for Altera Cyclone II devices. + Enable FPGA driver for loading bitstream in BIT and BIN format + on Altera Cyclone II device. + config FPGA_XILINX bool "Enable Xilinx FPGA drivers" select FPGA diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f25d3ff..929b9e2 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -142,7 +142,7 @@ config ETHOC config FEC_MXC bool "FEC Ethernet controller" - depends on MX6 + depends on MX5 || MX6 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 35640f0..238f77d 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -1,6 +1,20 @@ config PINCTRL_IMX bool +config PINCTRL_IMX5 + bool "IMX5 pinctrl driver" + depends on ARCH_MX5 && PINCTRL_FULL + select DEVRES + select PINCTRL_IMX + help + Say Y here to enable the imx5 pinctrl driver + + This provides a simple pinctrl driver for i.MX 53SoC familiy, + i.MX53. This feature depends on device tree + configuration. This driver is different from the linux one, + this is a simple implementation, only parses the 'fsl,pins' + property and configure related registers. + config PINCTRL_IMX6 bool "IMX6 pinctrl driver" depends on ARCH_MX6 && PINCTRL_FULL diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index 0ee7f2f..e0f7325 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o +obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx5.c b/drivers/pinctrl/nxp/pinctrl-imx5.c new file mode 100644 index 0000000..6942f39 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx5.c @@ -0,0 +1,44 @@ + +/* + * Copyright (C) 2016 Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info imx5_pinctrl_soc_info; + +static int imx5_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id imx5_pinctrl_match[] = { + { + .compatible = "fsl,imx53-iomuxc", + .data = (ulong)&imx5_pinctrl_soc_info + }, + { + .compatible = "fsl,imx53-iomuxc-gpr", + .data = (ulong)&imx5_pinctrl_soc_info + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx5_pinctrl) = { + .name = "imx5-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx5_pinctrl_match), + .probe = imx5_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 620dd82..b26ada3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -325,7 +325,7 @@ config MVEBU_A3700_UART config MXC_UART bool "IMX serial port support" - depends on MX6 + depends on MX5 || MX6 help If you have a machine based on a Motorola IMX CPU you can enable its onboard serial port by enabling this option. diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h new file mode 100644 index 0000000..87c75d4 --- /dev/null +++ b/include/configs/mx53cx9020.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG + * Patrick Bruenn + * + * Configuration settings for Beckhoff CX9020. + * + * Based on Freescale's Linux i.MX mx53loco.h file: + * Copyright (C) 2010-2011 Freescale Semiconductor. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_FSL_CLK + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO +#define CONFIG_REVISION_TAG + +#define CONFIG_MXC_UART_BASE UART2_BASE + +#define CONFIG_FPGA_COUNT 1 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC + +/* bootz: zImage/initrd.img support */ +#define CONFIG_DOS_PARTITION + +/* Eth Configs */ +#define CONFIG_MII +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +/* USB Configs */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX5 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ +#define CONFIG_SYS_TEXT_BASE 0x77800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr=0x71ff0000\0" \ + "rdaddr=0x72000000\0" \ + "console=ttymxc1,115200\0" \ + "uenv=/boot/uEnv.txt\0" \ + "optargs=\0" \ + "cmdline=\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcrootfstype=ext4 rootwait fixrtc\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \ + "rootfstype=${mmcrootfstype} " \ + "${cmdline}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadrd=load mmc ${bootpart} ${rdaddr} ${bootdir}/${rdfile};" \ + "setenv rdsize ${filesize}\0" \ + "loadfdt=echo loading ${fdt_path} ...;" \ + "load mmc ${bootpart} ${fdt_addr} ${fdt_path}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "echo Checking for: ${uenv} ...;" \ + "setenv bootpart ${mmcdev}:${mmcpart};" \ + "if test -e mmc ${bootpart} ${uenv}; then " \ + "load mmc ${bootpart} ${loadaddr} ${uenv};" \ + "env import -t ${loadaddr} ${filesize};" \ + "echo Loaded environment from ${uenv};" \ + "if test -n ${dtb}; then " \ + "setenv fdt_file ${dtb};" \ + "echo Using: dtb=${fdt_file} ...;" \ + "fi;" \ + "echo Checking for uname_r in ${uenv}...;" \ + "if test -n ${uname_r}; then " \ + "echo Running uname_boot ...;" \ + "run uname_boot;" \ + "fi;" \ + "fi;" \ + "fi;\0" \ + "uname_boot="\ + "setenv bootdir /boot; " \ + "setenv bootfile vmlinuz-${uname_r}; " \ + "setenv ccatfile /boot/ccat.rbf; " \ + "echo loading CCAT firmware from ${ccatfile}; " \ + "load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \ + "fpga load 0 ${loadaddr} ${filesize}; " \ + "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \ + "echo loading ${bootdir}/${bootfile} ...; " \ + "run loadimage;" \ + "setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \ + "if test -e mmc ${bootpart} ${fdt_path}; then " \ + "run loadfdt;" \ + "else " \ + "echo; echo unable to find ${fdt_file} ...;" \ + "echo booting legacy ...;"\ + "run mmcargs;" \ + "echo debug: [${bootargs}] ... ;" \ + "echo debug: [bootz ${loadaddr}] ... ;" \ + "bootz ${loadaddr}; " \ + "fi;" \ + "run mmcargs;" \ + "echo debug: [${bootargs}] ... ;" \ + "echo debug: [bootz ${loadaddr} - ${fdt_addr}] ... ;" \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot;" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +/* Framebuffer and LCD */ +#define CONFIG_PREBOOT +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 200000000 + +#endif /* __CONFIG_H */ diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h new file mode 100644 index 0000000..d382fc7 --- /dev/null +++ b/include/dt-bindings/clock/imx5-clock.h @@ -0,0 +1,219 @@ +/* + * Copyright 2013 Lucas Stach, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX5_H +#define __DT_BINDINGS_CLOCK_IMX5_H + +#define IMX5_CLK_DUMMY 0 +#define IMX5_CLK_CKIL 1 +#define IMX5_CLK_OSC 2 +#define IMX5_CLK_CKIH1 3 +#define IMX5_CLK_CKIH2 4 +#define IMX5_CLK_AHB 5 +#define IMX5_CLK_IPG 6 +#define IMX5_CLK_AXI_A 7 +#define IMX5_CLK_AXI_B 8 +#define IMX5_CLK_UART_PRED 9 +#define IMX5_CLK_UART_ROOT 10 +#define IMX5_CLK_ESDHC_A_PRED 11 +#define IMX5_CLK_ESDHC_B_PRED 12 +#define IMX5_CLK_ESDHC_C_SEL 13 +#define IMX5_CLK_ESDHC_D_SEL 14 +#define IMX5_CLK_EMI_SEL 15 +#define IMX5_CLK_EMI_SLOW_PODF 16 +#define IMX5_CLK_NFC_PODF 17 +#define IMX5_CLK_ECSPI_PRED 18 +#define IMX5_CLK_ECSPI_PODF 19 +#define IMX5_CLK_USBOH3_PRED 20 +#define IMX5_CLK_USBOH3_PODF 21 +#define IMX5_CLK_USB_PHY_PRED 22 +#define IMX5_CLK_USB_PHY_PODF 23 +#define IMX5_CLK_CPU_PODF 24 +#define IMX5_CLK_DI_PRED 25 +#define IMX5_CLK_TVE_SEL 27 +#define IMX5_CLK_UART1_IPG_GATE 28 +#define IMX5_CLK_UART1_PER_GATE 29 +#define IMX5_CLK_UART2_IPG_GATE 30 +#define IMX5_CLK_UART2_PER_GATE 31 +#define IMX5_CLK_UART3_IPG_GATE 32 +#define IMX5_CLK_UART3_PER_GATE 33 +#define IMX5_CLK_I2C1_GATE 34 +#define IMX5_CLK_I2C2_GATE 35 +#define IMX5_CLK_GPT_IPG_GATE 36 +#define IMX5_CLK_PWM1_IPG_GATE 37 +#define IMX5_CLK_PWM1_HF_GATE 38 +#define IMX5_CLK_PWM2_IPG_GATE 39 +#define IMX5_CLK_PWM2_HF_GATE 40 +#define IMX5_CLK_GPT_HF_GATE 41 +#define IMX5_CLK_FEC_GATE 42 +#define IMX5_CLK_USBOH3_PER_GATE 43 +#define IMX5_CLK_ESDHC1_IPG_GATE 44 +#define IMX5_CLK_ESDHC2_IPG_GATE 45 +#define IMX5_CLK_ESDHC3_IPG_GATE 46 +#define IMX5_CLK_ESDHC4_IPG_GATE 47 +#define IMX5_CLK_SSI1_IPG_GATE 48 +#define IMX5_CLK_SSI2_IPG_GATE 49 +#define IMX5_CLK_SSI3_IPG_GATE 50 +#define IMX5_CLK_ECSPI1_IPG_GATE 51 +#define IMX5_CLK_ECSPI1_PER_GATE 52 +#define IMX5_CLK_ECSPI2_IPG_GATE 53 +#define IMX5_CLK_ECSPI2_PER_GATE 54 +#define IMX5_CLK_CSPI_IPG_GATE 55 +#define IMX5_CLK_SDMA_GATE 56 +#define IMX5_CLK_EMI_SLOW_GATE 57 +#define IMX5_CLK_IPU_SEL 58 +#define IMX5_CLK_IPU_GATE 59 +#define IMX5_CLK_NFC_GATE 60 +#define IMX5_CLK_IPU_DI1_GATE 61 +#define IMX5_CLK_VPU_SEL 62 +#define IMX5_CLK_VPU_GATE 63 +#define IMX5_CLK_VPU_REFERENCE_GATE 64 +#define IMX5_CLK_UART4_IPG_GATE 65 +#define IMX5_CLK_UART4_PER_GATE 66 +#define IMX5_CLK_UART5_IPG_GATE 67 +#define IMX5_CLK_UART5_PER_GATE 68 +#define IMX5_CLK_TVE_GATE 69 +#define IMX5_CLK_TVE_PRED 70 +#define IMX5_CLK_ESDHC1_PER_GATE 71 +#define IMX5_CLK_ESDHC2_PER_GATE 72 +#define IMX5_CLK_ESDHC3_PER_GATE 73 +#define IMX5_CLK_ESDHC4_PER_GATE 74 +#define IMX5_CLK_USB_PHY_GATE 75 +#define IMX5_CLK_HSI2C_GATE 76 +#define IMX5_CLK_MIPI_HSC1_GATE 77 +#define IMX5_CLK_MIPI_HSC2_GATE 78 +#define IMX5_CLK_MIPI_ESC_GATE 79 +#define IMX5_CLK_MIPI_HSP_GATE 80 +#define IMX5_CLK_LDB_DI1_DIV_3_5 81 +#define IMX5_CLK_LDB_DI1_DIV 82 +#define IMX5_CLK_LDB_DI0_DIV_3_5 83 +#define IMX5_CLK_LDB_DI0_DIV 84 +#define IMX5_CLK_LDB_DI1_GATE 85 +#define IMX5_CLK_CAN2_SERIAL_GATE 86 +#define IMX5_CLK_CAN2_IPG_GATE 87 +#define IMX5_CLK_I2C3_GATE 88 +#define IMX5_CLK_LP_APM 89 +#define IMX5_CLK_PERIPH_APM 90 +#define IMX5_CLK_MAIN_BUS 91 +#define IMX5_CLK_AHB_MAX 92 +#define IMX5_CLK_AIPS_TZ1 93 +#define IMX5_CLK_AIPS_TZ2 94 +#define IMX5_CLK_TMAX1 95 +#define IMX5_CLK_TMAX2 96 +#define IMX5_CLK_TMAX3 97 +#define IMX5_CLK_SPBA 98 +#define IMX5_CLK_UART_SEL 99 +#define IMX5_CLK_ESDHC_A_SEL 100 +#define IMX5_CLK_ESDHC_B_SEL 101 +#define IMX5_CLK_ESDHC_A_PODF 102 +#define IMX5_CLK_ESDHC_B_PODF 103 +#define IMX5_CLK_ECSPI_SEL 104 +#define IMX5_CLK_USBOH3_SEL 105 +#define IMX5_CLK_USB_PHY_SEL 106 +#define IMX5_CLK_IIM_GATE 107 +#define IMX5_CLK_USBOH3_GATE 108 +#define IMX5_CLK_EMI_FAST_GATE 109 +#define IMX5_CLK_IPU_DI0_GATE 110 +#define IMX5_CLK_GPC_DVFS 111 +#define IMX5_CLK_PLL1_SW 112 +#define IMX5_CLK_PLL2_SW 113 +#define IMX5_CLK_PLL3_SW 114 +#define IMX5_CLK_IPU_DI0_SEL 115 +#define IMX5_CLK_IPU_DI1_SEL 116 +#define IMX5_CLK_TVE_EXT_SEL 117 +#define IMX5_CLK_MX51_MIPI 118 +#define IMX5_CLK_PLL4_SW 119 +#define IMX5_CLK_LDB_DI1_SEL 120 +#define IMX5_CLK_DI_PLL4_PODF 121 +#define IMX5_CLK_LDB_DI0_SEL 122 +#define IMX5_CLK_LDB_DI0_GATE 123 +#define IMX5_CLK_USB_PHY1_GATE 124 +#define IMX5_CLK_USB_PHY2_GATE 125 +#define IMX5_CLK_PER_LP_APM 126 +#define IMX5_CLK_PER_PRED1 127 +#define IMX5_CLK_PER_PRED2 128 +#define IMX5_CLK_PER_PODF 129 +#define IMX5_CLK_PER_ROOT 130 +#define IMX5_CLK_SSI_APM 131 +#define IMX5_CLK_SSI1_ROOT_SEL 132 +#define IMX5_CLK_SSI2_ROOT_SEL 133 +#define IMX5_CLK_SSI3_ROOT_SEL 134 +#define IMX5_CLK_SSI_EXT1_SEL 135 +#define IMX5_CLK_SSI_EXT2_SEL 136 +#define IMX5_CLK_SSI_EXT1_COM_SEL 137 +#define IMX5_CLK_SSI_EXT2_COM_SEL 138 +#define IMX5_CLK_SSI1_ROOT_PRED 139 +#define IMX5_CLK_SSI1_ROOT_PODF 140 +#define IMX5_CLK_SSI2_ROOT_PRED 141 +#define IMX5_CLK_SSI2_ROOT_PODF 142 +#define IMX5_CLK_SSI_EXT1_PRED 143 +#define IMX5_CLK_SSI_EXT1_PODF 144 +#define IMX5_CLK_SSI_EXT2_PRED 145 +#define IMX5_CLK_SSI_EXT2_PODF 146 +#define IMX5_CLK_SSI1_ROOT_GATE 147 +#define IMX5_CLK_SSI2_ROOT_GATE 148 +#define IMX5_CLK_SSI3_ROOT_GATE 149 +#define IMX5_CLK_SSI_EXT1_GATE 150 +#define IMX5_CLK_SSI_EXT2_GATE 151 +#define IMX5_CLK_EPIT1_IPG_GATE 152 +#define IMX5_CLK_EPIT1_HF_GATE 153 +#define IMX5_CLK_EPIT2_IPG_GATE 154 +#define IMX5_CLK_EPIT2_HF_GATE 155 +#define IMX5_CLK_CAN_SEL 156 +#define IMX5_CLK_CAN1_SERIAL_GATE 157 +#define IMX5_CLK_CAN1_IPG_GATE 158 +#define IMX5_CLK_OWIRE_GATE 159 +#define IMX5_CLK_GPU3D_SEL 160 +#define IMX5_CLK_GPU2D_SEL 161 +#define IMX5_CLK_GPU3D_GATE 162 +#define IMX5_CLK_GPU2D_GATE 163 +#define IMX5_CLK_GARB_GATE 164 +#define IMX5_CLK_CKO1_SEL 165 +#define IMX5_CLK_CKO1_PODF 166 +#define IMX5_CLK_CKO1 167 +#define IMX5_CLK_CKO2_SEL 168 +#define IMX5_CLK_CKO2_PODF 169 +#define IMX5_CLK_CKO2 170 +#define IMX5_CLK_SRTC_GATE 171 +#define IMX5_CLK_PATA_GATE 172 +#define IMX5_CLK_SATA_GATE 173 +#define IMX5_CLK_SPDIF_XTAL_SEL 174 +#define IMX5_CLK_SPDIF0_SEL 175 +#define IMX5_CLK_SPDIF1_SEL 176 +#define IMX5_CLK_SPDIF0_PRED 177 +#define IMX5_CLK_SPDIF0_PODF 178 +#define IMX5_CLK_SPDIF1_PRED 179 +#define IMX5_CLK_SPDIF1_PODF 180 +#define IMX5_CLK_SPDIF0_COM_SEL 181 +#define IMX5_CLK_SPDIF1_COM_SEL 182 +#define IMX5_CLK_SPDIF0_GATE 183 +#define IMX5_CLK_SPDIF1_GATE 184 +#define IMX5_CLK_SPDIF_IPG_GATE 185 +#define IMX5_CLK_OCRAM 186 +#define IMX5_CLK_SAHARA_IPG_GATE 187 +#define IMX5_CLK_SATA_REF 188 +#define IMX5_CLK_STEP_SEL 189 +#define IMX5_CLK_CPU_PODF_SEL 190 +#define IMX5_CLK_ARM 191 +#define IMX5_CLK_FIRI_PRED 192 +#define IMX5_CLK_FIRI_SEL 193 +#define IMX5_CLK_FIRI_PODF 194 +#define IMX5_CLK_FIRI_SERIAL_GATE 195 +#define IMX5_CLK_FIRI_IPG_GATE 196 +#define IMX5_CLK_CSI0_MCLK1_PRED 197 +#define IMX5_CLK_CSI0_MCLK1_SEL 198 +#define IMX5_CLK_CSI0_MCLK1_PODF 199 +#define IMX5_CLK_CSI0_MCLK1_GATE 200 +#define IMX5_CLK_IEEE1588_PRED 201 +#define IMX5_CLK_IEEE1588_SEL 202 +#define IMX5_CLK_IEEE1588_PODF 203 +#define IMX5_CLK_IEEE1588_GATE 204 +#define IMX5_CLK_END 205 + +#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ -- cgit v0.10.2 From f54183e65dbf70195b1e02d9ac80110b08625cf3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:48 +0100 Subject: net: fec_mxc: Remove unneeded eth_device arg from fec_get_hwaddr fec_get_hwaddr never used eth_device argument, hence removed. Cc: Simon Glass Cc: Peng Fan Cc: Stefano Babic Cc: Michael Trimarchi Acked-by: Joe Hershberger Signed-off-by: Jagan Teki diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 84021ea..b642770 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -362,8 +362,7 @@ static void fec_rbd_clean(int last, struct fec_bd *pRbd) writew(0, &pRbd->data_length); } -static int fec_get_hwaddr(struct eth_device *dev, int dev_id, - unsigned char *mac) +static int fec_get_hwaddr(int dev_id, unsigned char *mac) { imx_get_mac_from_fuse(dev_id, mac); return !is_valid_ethaddr(mac); @@ -1045,7 +1044,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, #endif eth_register(edev); - if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { + if (fec_get_hwaddr(dev_id, ethaddr) == 0) { debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); memcpy(edev->enetaddr, ethaddr, 6); if (!getenv("ethaddr")) -- cgit v0.10.2 From 60752ca86afdb0eaf2482aee9dafbdea84cb75f1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:49 +0100 Subject: net: fec_mxc: Convert into driver model This patch add driver model support for fec_mxc driver. Cc: Simon Glass Cc: Joe Hershberger Cc: Peng Fan Cc: Stefano Babic Cc: Michael Trimarchi Signed-off-by: Jagan Teki Acked-by: Joe Hershberger diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index b642770..fd96c43 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -368,10 +369,20 @@ static int fec_get_hwaddr(int dev_id, unsigned char *mac) return !is_valid_ethaddr(mac); } +#ifdef CONFIG_DM_ETH +static int fecmxc_set_hwaddr(struct udevice *dev) +#else static int fec_set_hwaddr(struct eth_device *dev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + uchar *mac = pdata->enetaddr; +#else uchar *mac = dev->enetaddr; struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif writel(0, &fec->eth->iaddr1); writel(0, &fec->eth->iaddr2); @@ -426,9 +437,17 @@ static void fec_reg_setup(struct fec_priv *fec) * Start the FEC engine * @param[in] dev Our device to handle */ +#ifdef CONFIG_DM_ETH +static int fec_open(struct udevice *dev) +#else static int fec_open(struct eth_device *edev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)edev->priv; +#endif int speed; uint32_t addr, size; int i; @@ -534,14 +553,26 @@ static int fec_open(struct eth_device *edev) return 0; } +#ifdef CONFIG_DM_ETH +static int fecmxc_init(struct udevice *dev) +#else static int fec_init(struct eth_device *dev, bd_t* bd) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; int i; /* Initialize MAC address */ +#ifdef CONFIG_DM_ETH + fecmxc_set_hwaddr(dev); +#else fec_set_hwaddr(dev); +#endif /* * Setup transmit descriptors, there are two in total. @@ -595,9 +626,17 @@ static int fec_init(struct eth_device *dev, bd_t* bd) * Halt the FEC engine * @param[in] dev Our device to handle */ +#ifdef CONFIG_DM_ETH +static void fecmxc_halt(struct udevice *dev) +#else static void fec_halt(struct eth_device *dev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif int counter = 0xffff; /* @@ -637,7 +676,11 @@ static void fec_halt(struct eth_device *dev) * @param[in] length Data count in bytes * @return 0 on success */ +#ifdef CONFIG_DM_ETH +static int fecmxc_send(struct udevice *dev, void *packet, int length) +#else static int fec_send(struct eth_device *dev, void *packet, int length) +#endif { unsigned int status; uint32_t size, end; @@ -649,7 +692,11 @@ static int fec_send(struct eth_device *dev, void *packet, int length) * This routine transmits one frame. This routine only accepts * 6-byte Ethernet addresses. */ +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif /* * Check for valid length of data. @@ -782,9 +829,17 @@ out: * @param[in] dev Our ethernet device to handle * @return Length of packet read */ +#ifdef CONFIG_DM_ETH +static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) +#else static int fec_recv(struct eth_device *dev) +#endif { +#ifdef CONFIG_DM_ETH + struct fec_priv *fec = dev_get_priv(dev); +#else struct fec_priv *fec = (struct fec_priv *)dev->priv; +#endif struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; unsigned long ievent; int frame_length, len = 0; @@ -800,8 +855,13 @@ static int fec_recv(struct eth_device *dev) writel(ievent, &fec->eth->ievent); debug("fec_recv: ievent 0x%lx\n", ievent); if (ievent & FEC_IEVENT_BABR) { +#ifdef CONFIG_DM_ETH + fecmxc_halt(dev); + fecmxc_init(dev); +#else fec_halt(dev); fec_init(dev, fec->bd); +#endif printf("some error: 0x%08lx\n", ievent); return 0; } @@ -813,10 +873,18 @@ static int fec_recv(struct eth_device *dev) if (ievent & FEC_IEVENT_GRA) { /* Graceful stop complete */ if (readl(&fec->eth->x_cntrl) & 0x00000001) { +#ifdef CONFIG_DM_ETH + fecmxc_halt(dev); +#else fec_halt(dev); +#endif writel(~0x00000001 & readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl); +#ifdef CONFIG_DM_ETH + fecmxc_init(dev); +#else fec_init(dev, fec->bd); +#endif } } @@ -970,6 +1038,33 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); } +struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) +{ + struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; + struct mii_dev *bus; + int ret; + + bus = mdio_alloc(); + if (!bus) { + printf("mdio_alloc failed\n"); + return NULL; + } + bus->read = fec_phy_read; + bus->write = fec_phy_write; + bus->priv = eth; + fec_set_dev_name(bus->name, dev_id); + + ret = mdio_register(bus); + if (ret) { + printf("mdio_register failed\n"); + free(bus); + return NULL; + } + fec_mii_setspeed(eth); + return bus; +} + +#ifndef CONFIG_DM_ETH #ifdef CONFIG_PHYLIB int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, struct mii_dev *bus, struct phy_device *phydev) @@ -1061,32 +1156,6 @@ err1: return ret; } -struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) -{ - struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; - struct mii_dev *bus; - int ret; - - bus = mdio_alloc(); - if (!bus) { - printf("mdio_alloc failed\n"); - return NULL; - } - bus->read = fec_phy_read; - bus->write = fec_phy_write; - bus->priv = eth; - fec_set_dev_name(bus->name, dev_id); - - ret = mdio_register(bus); - if (ret) { - printf("mdio_register failed\n"); - free(bus); - return NULL; - } - fec_mii_setspeed(eth); - return bus; -} - int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) { uint32_t base_mii; @@ -1146,3 +1215,150 @@ int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) return 0; } #endif + +#else + +static const struct eth_ops fecmxc_ops = { + .start = fecmxc_init, + .send = fecmxc_send, + .recv = fecmxc_recv, + .stop = fecmxc_halt, + .write_hwaddr = fecmxc_set_hwaddr, +}; + +static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) +{ + struct phy_device *phydev; + int mask = 0xffffffff; + +#ifdef CONFIG_PHYLIB + mask = 1 << CONFIG_FEC_MXC_PHYADDR; +#endif + + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +static int fecmxc_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct fec_priv *priv = dev_get_priv(dev); + struct mii_dev *bus = NULL; + int dev_id = -1; + unsigned char ethaddr[6]; + uint32_t start; + int ret; + + ret = fec_alloc_descs(priv); + if (ret) + return ret; + + bus = fec_get_miibus((uint32_t)priv->eth, dev_id); + if (!bus) + goto err_mii; + + priv->bus = bus; + priv->xcv_type = CONFIG_FEC_XCV_TYPE; + priv->interface = pdata->phy_interface; + ret = fec_phy_init(priv, dev); + if (ret) + goto err_phy; + + /* Reset chip. */ + writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, &priv->eth->ecntrl); + start = get_timer(0); + while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { + if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { + printf("FEC MXC: Timeout reseting chip\n"); + goto err_timeout; + } + udelay(10); + } + + fec_reg_setup(priv); + fec_set_dev_name((char *)dev->name, dev_id); + priv->dev_id = (dev_id == -1) ? 0 : dev_id; + + ret = fec_get_hwaddr(dev_id, ethaddr); + if (!ret) { + debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); + memcpy(pdata->enetaddr, ethaddr, 6); + if (!getenv("ethaddr")) + eth_setenv_enetaddr("ethaddr", ethaddr); + } + + return 0; + +err_timeout: + free(priv->phydev); +err_phy: + mdio_unregister(bus); + free(bus); +err_mii: + fec_free_descs(priv); + return ret; +} + +static int fecmxc_remove(struct udevice *dev) +{ + struct fec_priv *priv = dev_get_priv(dev); + + free(priv->phydev); + fec_free_descs(priv); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +static int fecmxc_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct fec_priv *priv = dev_get_priv(dev); + const char *phy_mode; + + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + priv->eth = (struct ethernet_regs *)pdata->iobase; + + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + /* TODO + * Need to get the reset-gpio and related properties from DT + * and implemet the enet reset code on .probe call + */ + + return 0; +} + +static const struct udevice_id fecmxc_ids[] = { + { .compatible = "fsl,imx6q-fec" }, + { } +}; + +U_BOOT_DRIVER(fecmxc_gem) = { + .name = "fecmxc", + .id = UCLASS_ETH, + .of_match = fecmxc_ids, + .ofdata_to_platdata = fecmxc_ofdata_to_platdata, + .probe = fecmxc_probe, + .remove = fecmxc_remove, + .ops = &fecmxc_ops, + .priv_auto_alloc_size = sizeof(struct fec_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; +#endif diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 0717cc6..9fc6153 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -264,6 +264,10 @@ struct fec_priv { int phy_id; int (*mii_postcall)(int); #endif + +#ifdef CONFIG_DM_ETH + u32 interface; +#endif }; /** -- cgit v0.10.2 From 567173a610107ced9174f03290851f272b4cbfc2 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:50 +0100 Subject: net: fec_mxc: Driver cleanups - Remove exctra space - Add space - Add tab space - Fix single line comments quotes - Fix 'CHECK: Avoid CamelCase' - Fix 'CHECK: Alignment should match open parenthesis' - Fix 'WARNING: line over 80 characters' - Re-arrage header include files Cc: Simon Glass Cc: Peng Fan Cc: Stefano Babic Cc: Michael Trimarchi Acked-by: Joe Hershberger Signed-off-by: Jagan Teki diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index fd96c43..2c4be96 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -12,18 +12,19 @@ #include #include #include +#include #include #include -#include #include "fec_mxc.h" -#include -#include -#include #include #include #include +#include +#include +#include + DECLARE_GLOBAL_DATA_PTR; /* @@ -80,11 +81,9 @@ static void swap_packet(uint32_t *packet, int length) } #endif -/* - * MII-interface related functions - */ -static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, - uint8_t regAddr) +/* MII-interface related functions */ +static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr, + uint8_t regaddr) { uint32_t reg; /* convenient holder for the PHY register */ uint32_t phy; /* convenient holder for the PHY */ @@ -96,15 +95,13 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, * programming the FEC's MII data register. */ writel(FEC_IEVENT_MII, ð->ievent); - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + reg = regaddr << FEC_MII_DATA_RA_SHIFT; + phy = phyaddr << FEC_MII_DATA_PA_SHIFT; writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg, ð->mii_data); - /* - * wait for the related interrupt - */ + /* wait for the related interrupt */ start = get_timer(0); while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { @@ -113,17 +110,13 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, } } - /* - * clear mii interrupt bit - */ + /* clear mii interrupt bit */ writel(FEC_IEVENT_MII, ð->ievent); - /* - * it's now safe to read the PHY's register - */ + /* it's now safe to read the PHY's register */ val = (unsigned short)readl(ð->mii_data); - debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, - regAddr, val); + debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, + regaddr, val); return val; } @@ -154,22 +147,20 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); } -static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, - uint8_t regAddr, uint16_t data) +static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr, + uint8_t regaddr, uint16_t data) { uint32_t reg; /* convenient holder for the PHY register */ uint32_t phy; /* convenient holder for the PHY */ uint32_t start; - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + reg = regaddr << FEC_MII_DATA_RA_SHIFT; + phy = phyaddr << FEC_MII_DATA_PA_SHIFT; writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); - /* - * wait for the MII interrupt - */ + /* wait for the MII interrupt */ start = get_timer(0); while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { @@ -178,26 +169,24 @@ static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, } } - /* - * clear MII interrupt bit - */ + /* clear MII interrupt bit */ writel(FEC_IEVENT_MII, ð->ievent); - debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, - regAddr, data); + debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, + regaddr, data); return 0; } -static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, - int regAddr) +static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr, + int regaddr) { - return fec_mdio_read(bus->priv, phyAddr, regAddr); + return fec_mdio_read(bus->priv, phyaddr, regaddr); } -static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, - int regAddr, u16 data) +static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr, + int regaddr, u16 data) { - return fec_mdio_write(bus->priv, phyAddr, regAddr, data); + return fec_mdio_write(bus->priv, phyaddr, regaddr, data); } #ifndef CONFIG_PHYLIB @@ -218,14 +207,12 @@ static int miiphy_restart_aneg(struct eth_device *dev) fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); udelay(1000); - /* - * Set the auto-negotiation advertisement register bits - */ + /* Set the auto-negotiation advertisement register bits */ fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, - LPA_100FULL | LPA_100HALF | LPA_10FULL | - LPA_10HALF | PHY_ANLPAR_PSB_802_3); + LPA_100FULL | LPA_100HALF | LPA_10FULL | + LPA_10HALF | PHY_ANLPAR_PSB_802_3); fec_mdio_write(eth, fec->phy_id, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); + BMCR_ANENABLE | BMCR_ANRESTART); if (fec->mii_postcall) ret = fec->mii_postcall(fec->phy_id); @@ -242,9 +229,7 @@ static int miiphy_wait_aneg(struct eth_device *dev) struct fec_priv *fec = (struct fec_priv *)dev->priv; struct ethernet_regs *eth = fec->bus->priv; - /* - * Wait for AN completion - */ + /* Wait for AN completion */ start = get_timer(0); do { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { @@ -255,7 +240,7 @@ static int miiphy_wait_aneg(struct eth_device *dev) status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); if (status < 0) { printf("%s: Autonegotiation failed. status: %d\n", - dev->name, status); + dev->name, status); return -1; } } while (!(status & BMSR_LSTATUS)); @@ -352,15 +337,15 @@ static void fec_tbd_init(struct fec_priv *fec) /** * Mark the given read buffer descriptor as free * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 - * @param[in] pRbd buffer descriptor to mark free again + * @param[in] prbd buffer descriptor to mark free again */ -static void fec_rbd_clean(int last, struct fec_bd *pRbd) +static void fec_rbd_clean(int last, struct fec_bd *prbd) { unsigned short flags = FEC_RBD_EMPTY; if (last) flags |= FEC_RBD_WRAP; - writew(flags, &pRbd->status); - writew(0, &pRbd->data_length); + writew(flags, &prbd->status); + writew(0, &prbd->data_length); } static int fec_get_hwaddr(int dev_id, unsigned char *mac) @@ -389,37 +374,26 @@ static int fec_set_hwaddr(struct eth_device *dev) writel(0, &fec->eth->gaddr1); writel(0, &fec->eth->gaddr2); - /* - * Set physical address - */ + /* Set physical address */ writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], - &fec->eth->paddr1); + &fec->eth->paddr1); writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); return 0; } -/* - * Do initial configuration of the FEC registers - */ +/* Do initial configuration of the FEC registers */ static void fec_reg_setup(struct fec_priv *fec) { uint32_t rcntrl; - /* - * Set interrupt mask register - */ + /* Set interrupt mask register */ writel(0x00000000, &fec->eth->imask); - /* - * Clear FEC-Lite interrupt event register(IEVENT) - */ + /* Clear FEC-Lite interrupt event register(IEVENT) */ writel(0xffffffff, &fec->eth->ievent); - - /* - * Set FEC-Lite receive control register(R_CNTRL): - */ + /* Set FEC-Lite receive control register(R_CNTRL): */ /* Start with frame length = 1518, common for all modes. */ rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; @@ -471,22 +445,19 @@ static int fec_open(struct eth_device *edev) #ifdef FEC_QUIRK_ENET_MAC /* Enable ENET HW endian SWAP */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, - &fec->eth->ecntrl); + &fec->eth->ecntrl); /* Enable ENET store and forward mode */ writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, - &fec->eth->x_wmrk); + &fec->eth->x_wmrk); #endif - /* - * Enable FEC-Lite controller - */ + /* Enable FEC-Lite controller */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, - &fec->eth->ecntrl); + &fec->eth->ecntrl); + #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) udelay(100); - /* - * setup the MII gasket for RMII mode - */ + /* setup the MII gasket for RMII mode */ /* disable the gasket */ writew(0, &fec->eth->miigsk_enr); @@ -544,9 +515,7 @@ static int fec_open(struct eth_device *edev) #endif debug("%s:Speed=%i\n", __func__, speed); - /* - * Enable SmartDMA receive task - */ + /* Enable SmartDMA receive task */ fec_rx_task_enable(fec); udelay(100000); @@ -556,7 +525,7 @@ static int fec_open(struct eth_device *edev) #ifdef CONFIG_DM_ETH static int fecmxc_init(struct udevice *dev) #else -static int fec_init(struct eth_device *dev, bd_t* bd) +static int fec_init(struct eth_device *dev, bd_t *bd) #endif { #ifdef CONFIG_DM_ETH @@ -574,9 +543,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd) fec_set_hwaddr(dev); #endif - /* - * Setup transmit descriptors, there are two in total. - */ + /* Setup transmit descriptors, there are two in total. */ fec_tbd_init(fec); /* Setup receive descriptors. */ @@ -587,18 +554,14 @@ static int fec_init(struct eth_device *dev, bd_t* bd) if (fec->xcv_type != SEVENWIRE) fec_mii_setspeed(fec->bus->priv); - /* - * Set Opcode/Pause Duration Register - */ + /* Set Opcode/Pause Duration Register */ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ writel(0x2, &fec->eth->x_wmrk); - /* - * Set multicast address filter - */ + + /* Set multicast address filter */ writel(0x00000000, &fec->eth->gaddr1); writel(0x00000000, &fec->eth->gaddr2); - /* Do not access reserved register for i.MX6UL */ if (!is_mx6ul()) { /* clear MIB RAM */ @@ -639,22 +602,16 @@ static void fec_halt(struct eth_device *dev) #endif int counter = 0xffff; - /* - * issue graceful stop command to the FEC transmitter if necessary - */ + /* issue graceful stop command to the FEC transmitter if necessary */ writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), - &fec->eth->x_cntrl); + &fec->eth->x_cntrl); debug("eth_halt: wait for stop regs\n"); - /* - * wait for graceful stop to register - */ + /* wait for graceful stop to register */ while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) udelay(1); - /* - * Disable SmartDMA tasks - */ + /* Disable SmartDMA tasks */ fec_tx_task_disable(fec); fec_rx_task_disable(fec); @@ -663,7 +620,7 @@ static void fec_halt(struct eth_device *dev) * Note: this will also reset the BD index counter! */ writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, - &fec->eth->ecntrl); + &fec->eth->ecntrl); fec->rbd_index = 0; fec->tbd_index = 0; debug("eth_halt: done\n"); @@ -766,9 +723,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length) */ readl(addr + size - 4); - /* - * Enable SmartDMA transmit task - */ + /* Enable SmartDMA transmit task */ fec_tx_task_enable(fec); /* @@ -813,8 +768,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length) out: debug("fec_send: status 0x%x index %d ret %i\n", - readw(&fec->tbd_base[fec->tbd_index].status), - fec->tbd_index, ret); + readw(&fec->tbd_base[fec->tbd_index].status), + fec->tbd_index, ret); /* for next transmission use the other buffer */ if (fec->tbd_index) fec->tbd_index = 0; @@ -848,9 +803,7 @@ static int fec_recv(struct eth_device *dev) int i; ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); - /* - * Check if any critical events have happened - */ + /* Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); writel(ievent, &fec->eth->ievent); debug("fec_recv: ievent 0x%lx\n", ievent); @@ -868,7 +821,7 @@ static int fec_recv(struct eth_device *dev) if (ievent & FEC_IEVENT_HBERR) { /* Heartbeat error */ writel(0x00000001 | readl(&fec->eth->x_cntrl), - &fec->eth->x_cntrl); + &fec->eth->x_cntrl); } if (ievent & FEC_IEVENT_GRA) { /* Graceful stop complete */ @@ -879,7 +832,7 @@ static int fec_recv(struct eth_device *dev) fec_halt(dev); #endif writel(~0x00000001 & readl(&fec->eth->x_cntrl), - &fec->eth->x_cntrl); + &fec->eth->x_cntrl); #ifdef CONFIG_DM_ETH fecmxc_init(dev); #else @@ -911,22 +864,16 @@ static int fec_recv(struct eth_device *dev) if (!(bd_status & FEC_RBD_EMPTY)) { if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && - ((readw(&rbd->data_length) - 4) > 14)) { - /* - * Get buffer address and size - */ + ((readw(&rbd->data_length) - 4) > 14)) { + /* Get buffer address and size */ addr = readl(&rbd->data_pointer); frame_length = readw(&rbd->data_length) - 4; - /* - * Invalidate data cache over the buffer - */ + /* Invalidate data cache over the buffer */ end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); addr &= ~(ARCH_DMA_MINALIGN - 1); invalidate_dcache_range(addr, end); - /* - * Fill the buffer and pass it to upper layers - */ + /* Fill the buffer and pass it to upper layers */ #ifdef CONFIG_FEC_MXC_SWAP_PACKET swap_packet((uint32_t *)addr, frame_length); #endif @@ -954,7 +901,7 @@ static int fec_recv(struct eth_device *dev) &fec->rbd_base[i]); } flush_dcache_range(addr, - addr + ARCH_DMA_MINALIGN); + addr + ARCH_DMA_MINALIGN); } fec_rx_task_enable(fec); @@ -1273,7 +1220,8 @@ static int fecmxc_probe(struct udevice *dev) goto err_phy; /* Reset chip. */ - writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, &priv->eth->ecntrl); + writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, + &priv->eth->ecntrl); start = get_timer(0); while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 9fc6153..43a7d7b 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -14,21 +14,14 @@ * SPDX-License-Identifier: GPL-2.0+ */ - #ifndef __FEC_MXC_H #define __FEC_MXC_H -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); - -/** - * Layout description of the FEC - */ +/* Layout description of the FEC */ struct ethernet_regs { + /* [10:2]addr = 00 */ -/* [10:2]addr = 00 */ - -/* Control and status Registers (offset 000-1FF) */ - + /* Control and status Registers (offset 000-1FF) */ uint32_t res0[1]; /* MBAR_ETH + 0x000 */ uint32_t ievent; /* MBAR_ETH + 0x004 */ uint32_t imask; /* MBAR_ETH + 0x008 */ @@ -71,8 +64,7 @@ struct ethernet_regs { uint32_t emrbr; /* MBAR_ETH + 0x188 */ uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */ -/* MIB COUNTERS (Offset 200-2FF) */ - + /* MIB COUNTERS (Offset 200-2FF) */ uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */ uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */ uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ @@ -174,7 +166,6 @@ struct ethernet_regs { #define FEC_IMASKT_RL 0x00100000 #define FEC_IMASK_UN 0x00080000 - #define FEC_RCNTRL_MAX_FL_SHIFT 16 #define FEC_RCNTRL_LOOP 0x00000001 #define FEC_RCNTRL_DRT 0x00000002 @@ -233,9 +224,7 @@ struct fec_bd { uint32_t data_pointer; /* payload's buffer address */ }; -/** - * Supported phy types on this platform - */ +/* Supported phy types on this platform */ enum xceiver_type { SEVENWIRE, /* 7-wire */ MII10, /* MII 10Mbps */ @@ -244,9 +233,7 @@ enum xceiver_type { RGMII, /* RGMII */ }; -/** - * @brief i.MX27-FEC private structure - */ +/* @brief i.MX27-FEC private structure */ struct fec_priv { struct ethernet_regs *eth; /* pointer to register'S base */ enum xceiver_type xcv_type; /* transceiver type */ @@ -270,6 +257,8 @@ struct fec_priv { #endif }; +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); + /** * @brief Numbers of buffer descriptors for receiving * -- cgit v0.10.2 From 1ed2570f7eebd78b6ee698fa327a0d92a478d0bc Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:51 +0100 Subject: dm: net: fec: Add .read_rom_hwaddr Add .read_rom_hwaddr on dm eth_ops. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Acked-by: Joe Hershberger Signed-off-by: Jagan Teki diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 2c4be96..3304fddc 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1165,12 +1165,21 @@ int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) #else +static int fecmxc_read_rom_hwaddr(struct udevice *dev) +{ + struct fec_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + + return fec_get_hwaddr(priv->dev_id, pdata->enetaddr); +} + static const struct eth_ops fecmxc_ops = { .start = fecmxc_init, .send = fecmxc_send, .recv = fecmxc_recv, .stop = fecmxc_halt, .write_hwaddr = fecmxc_set_hwaddr, + .read_rom_hwaddr = fecmxc_read_rom_hwaddr, }; static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) @@ -1200,7 +1209,6 @@ static int fecmxc_probe(struct udevice *dev) struct fec_priv *priv = dev_get_priv(dev); struct mii_dev *bus = NULL; int dev_id = -1; - unsigned char ethaddr[6]; uint32_t start; int ret; @@ -1235,14 +1243,6 @@ static int fecmxc_probe(struct udevice *dev) fec_set_dev_name((char *)dev->name, dev_id); priv->dev_id = (dev_id == -1) ? 0 : dev_id; - ret = fec_get_hwaddr(dev_id, ethaddr); - if (!ret) { - debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); - memcpy(pdata->enetaddr, ethaddr, 6); - if (!getenv("ethaddr")) - eth_setenv_enetaddr("ethaddr", ethaddr); - } - return 0; err_timeout: -- cgit v0.10.2 From 65613cada2be42392ec7b0d9be94d38b9a17ba9f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:52 +0100 Subject: ARM: dts: imx6qdl-icore: Add FEC support Add FEC dts support for Engicam i.CoreM6 dql modules. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Acked-by: Joe Hershberger Signed-off-by: Jagan Teki diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi index f424cd5..a485c3e 100644 --- a/arch/arm/dts/imx6qdl-icore.dtsi +++ b/arch/arm/dts/imx6qdl-icore.dtsi @@ -75,6 +75,14 @@ assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; }; +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + phy-mode = "rmii"; + status = "okay"; +}; + &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -118,6 +126,22 @@ }; &iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 -- cgit v0.10.2 From e920f607793a0846b3837924e8ea5e95f2adc29b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:53 +0100 Subject: icorem6: Use CONFIG_DM_ETH support Use CONFIG_DM_ETH and remove board_eth_init code from board files. Cc: Joe Hershberger Cc: Peng Fan Cc: Stefano Babic Cc: Michael Trimarchi Acked-by: Joe Hershberger Signed-off-by: Jagan Teki diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index eefe629..544f9af 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -126,6 +126,7 @@ config TARGET_MX6Q_ICORE select MX6QDL select OF_CONTROL select DM + select DM_ETH select DM_GPIO select DM_MMC select DM_THERMAL diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index c152007..587775e 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -7,8 +7,6 @@ */ #include -#include -#include #include #include @@ -27,80 +25,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - static iomux_v3_cfg_t const uart4_pads[] = { IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL | PAD_CTL_SRE_FAST)), - IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -#ifdef CONFIG_FEC_MXC -#define ENET_PHY_RST IMX_GPIO_NR(7, 12) -static int setup_fec(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - s32 timeout = 100000; - u32 reg = 0; - int ret; - - /* Enable fec clock */ - setbits_le32(&ccm->CCGR1, MXC_CCM_CCGR1_ENET_MASK); - - /* use 50MHz */ - ret = enable_fec_anatop_clock(0, ENET_50MHZ); - if (ret) - return ret; - - /* Enable PLLs */ - reg = readl(&anatop->pll_enet); - reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; - writel(reg, &anatop->pll_enet); - reg = readl(&anatop->pll_enet); - reg |= BM_ANADIG_PLL_SYS_ENABLE; - while (timeout--) { - if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_SYS_LOCK) - break; - } - if (timeout <= 0) - return -EIO; - reg &= ~BM_ANADIG_PLL_SYS_BYPASS; - writel(reg, &anatop->pll_enet); - - /* reset the phy */ - gpio_direction_output(ENET_PHY_RST, 0); - udelay(10000); - gpio_set_value(ENET_PHY_RST, 1); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int ret; - - SETUP_IOMUX_PADS(enet_pads); - setup_fec(); - - return ret = cpu_eth_init(bis); -} -#endif - #ifdef CONFIG_NAND_MXS #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index fcf4934..31f40b4 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -30,7 +30,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_LIBFDT=y CONFIG_FEC_MXC=y CONFIG_MXC_UART=y -CONFIG_NETDEVICES=y CONFIG_IMX_THERMAL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 4919d44..3410e4c 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -24,7 +24,6 @@ CONFIG_OF_LIBFDT=y CONFIG_FEC_MXC=y CONFIG_MXC_UART=y CONFIG_NAND_MXS=y -CONFIG_NETDEVICES=y CONFIG_IMX_THERMAL=y # CONFIG_BLK is not set # CONFIG_DM_MMC_OPS is not set -- cgit v0.10.2 From 7db7455b53ee727010ba1ad431df85dd058a75d5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:54 +0100 Subject: video: Kconfig: Add VIDEO_IPV3 entry Added kconfig entry for CONFIG_VIDEO_IPV3 driver. Cc: Anatolij Gustschin Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 577e6d7..2069576 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -443,6 +443,13 @@ config VIDEO model. Video drivers typically provide a colour text console and cursor. +config VIDEO_IPUV3 + bool "i.MX IPUv3 Core video support" + depends on VIDEO && MX6 + help + This enables framebuffer driver for i.MX processors working + on the IPUv3(Image Processing Unit) internal graphic processor. + config CFB_CONSOLE bool "Enable colour frame buffer console" depends on VIDEO -- cgit v0.10.2 From ca7463c9d795d7c43621c8c5ac1faf870deec47c Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:55 +0100 Subject: imx6: icorem6: Add framebuffer support Add IPUv3 framebuffer support for Engicam i.CoreM6 qdl board. Cc: Anatolij Gustschin Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index 587775e..171ec45 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -18,6 +18,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -90,6 +91,113 @@ static void setup_gpmi_nand(void) } #endif +#if defined(CONFIG_VIDEO_IPUV3) +static iomux_v3_cfg_t const rgb_pads[] = { + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), + IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), + IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), + IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), + IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), + IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), + IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), + IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), + IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), + IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), + IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), + IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), + IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), + IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), + IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), + IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), + IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), + IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), + IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), + IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), +}; + +static void enable_rgb(struct display_info_t const *dev) +{ + SETUP_IOMUX_PADS(rgb_pads); +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "Amp-WD", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30000, + .left_margin = 30, + .right_margin = 30, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 64, + .vsync_len = 20, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } + }, +}; + +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | + IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + int board_early_init_f(void) { SETUP_IOMUX_PADS(uart4_pads); @@ -105,6 +213,11 @@ int board_init(void) #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif + +#ifdef CONFIG_VIDEO_IPUV3 + setup_display(); +#endif + return 0; } diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 31f40b4..6fa85de 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -33,6 +33,9 @@ CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 3410e4c..b32eea9 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -29,6 +29,9 @@ CONFIG_IMX_THERMAL=y # CONFIG_DM_MMC_OPS is not set CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index f8a1263..70e74ba 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -149,6 +149,18 @@ # define CONFIG_PHY_SMSC #endif +/* Framebuffer */ +#ifdef CONFIG_VIDEO_IPUV3 +# define CONFIG_IPUV3_CLK 260000000 +# define CONFIG_IMX_VIDEO_SKIP + +# define CONFIG_SPLASH_SCREEN +# define CONFIG_BMP_16BPP +# define CONFIG_VIDEO_BMP_RLE8 +# define CONFIG_VIDEO_LOGO +# define CONFIG_VIDEO_BMP_LOGO +#endif + /* SPL */ #ifdef CONFIG_SPL # ifdef CONFIG_NAND_MXS -- cgit v0.10.2 From 3713571cb748964dcba87675fe202036127da5de Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:56 +0100 Subject: imx6: icorem6: Add custom splashscreen support Add custom splashscreen, engicam.bmp support for Engicam i.CoreM6 qdl board. Cc: Anatolij Gustschin Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index 70e74ba..204e96e 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -37,6 +37,7 @@ /* Default environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ + "splashpos=m,m\0" \ "image=zImage\0" \ "console=ttymxc3\0" \ "fdt_high=0xffffffff\0" \ @@ -155,6 +156,7 @@ # define CONFIG_IMX_VIDEO_SKIP # define CONFIG_SPLASH_SCREEN +# define CONFIG_SPLASH_SCREEN_ALIGN # define CONFIG_BMP_16BPP # define CONFIG_VIDEO_BMP_RLE8 # define CONFIG_VIDEO_LOGO diff --git a/tools/logos/engicam.bmp b/tools/logos/engicam.bmp new file mode 100755 index 0000000..f6c60fb Binary files /dev/null and b/tools/logos/engicam.bmp differ -- cgit v0.10.2 From 72c8c10b7357b9edf344fb06fa4bc968edfa4156 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:57 +0100 Subject: i2c: Kconfig: Add SYS_I2C_MXC entry Added kconfig for SYS_I2C_MXC driver. Cc: Stefano Babic Cc: Heiko Schocher Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 1537b67..051f911 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -109,6 +109,14 @@ config SYS_I2C_INTEL the I2C API meaning that any I2C operations will immediately fail for now. +config SYS_I2C_MXC + bool "NXP i.MX I2C driver" + depends on MX6 + help + Add support for the NXP i.MX I2C driver. This supports upto for bus + channels and operating on standard mode upto 100 kbits/s and fast + mode upto 400 kbits/s. + config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" depends on DM_I2C -- cgit v0.10.2 From 65c92e4f39d1e61b7c5f6b086f1fdf5fac72d6e0 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:58 +0100 Subject: i2c: mxc: Print hex instead of decimal for bus address Better to print the hex value for bus address instead of decimal, for more readbility on bus addressing. Before: ------ U-Boot> i2c dev 1 Setting bus to 1 i2c bus 1 at 35274752, no gpio pinctrl state. After: ------ U-Boot> i2c dev 1 Setting bus to 1 i2c bus 1 at 0x21a4000, no gpio pinctrl state. Cc: Simon Glass Cc: Heiko Schocher Cc: Peng Fan Cc: Michael Trimarchi Signed-off-by: Jagan Teki Acked-by: Heiko Schocher diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 6247d33..03a5ce9 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -775,7 +775,7 @@ static int mxc_i2c_probe(struct udevice *bus) */ ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio"); if (ret < 0) { - dev_info(dev, "i2c bus %d at %lu, no gpio pinctrl state.\n", bus->seq, i2c_bus->base); + dev_info(dev, "i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base); } else { ret = gpio_request_by_name_nodev(fdt, node, "scl-gpios", 0, &i2c_bus->scl_gpio, -- cgit v0.10.2 From 2da24fe551122fcae523c1b117009c0be1dddb90 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:00:59 +0100 Subject: i2c: mxc: Make 'no gpio pinctrl state' print as debug Some I2C bus devicetree nodes, doesn't require to have gpio pinctrl so replace the dev_info to debug so the print never comes on the console and for bus that uses gpio pinctrl anyway have dev_err. Before: ------ U-Boot> i2c dev 1 Setting bus to 1 i2c bus 1 at 0x21a4000, no gpio pinctrl state. After: ------ U-Boot> i2c dev 1 Setting bus to 1 Cc: Simon Glass Cc: Heiko Schocher Cc: Peng Fan Cc: Michael Trimarchi Signed-off-by: Jagan Teki Acked-by: Heiko Schocher diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 03a5ce9..94d9027 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -775,7 +775,7 @@ static int mxc_i2c_probe(struct udevice *bus) */ ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio"); if (ret < 0) { - dev_info(dev, "i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base); + debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base); } else { ret = gpio_request_by_name_nodev(fdt, node, "scl-gpios", 0, &i2c_bus->scl_gpio, -- cgit v0.10.2 From d90384e834a551ef7b69b05f3be1bd103af87d38 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 6 Dec 2016 00:01:00 +0100 Subject: imx6: icorem6: Add I2C support Add I2C support for Engicam i.CoreM6 qdl board. icorem6qdl> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl> i2c dev 2 Setting bus to 2 icorem6qdl> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl> i2c probe Valid chip addresses: 2C icorem6qdl> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Stefano Babic Cc: Heiko Schocher Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki Acked-by: Heiko Schocher diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 544f9af..df745cc 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -128,6 +128,7 @@ config TARGET_MX6Q_ICORE select DM select DM_ETH select DM_GPIO + select DM_I2C select DM_MMC select DM_THERMAL select SUPPORT_SPL diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 6fa85de..5f09425 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_DM_MMC_OPS is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_MEMTEST=y @@ -33,6 +34,7 @@ CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y CONFIG_VIDEO=y CONFIG_VIDEO_IPUV3=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -40,7 +42,6 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index b32eea9..af3a9f8 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_IMLS is not set CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_MEMTEST=y @@ -29,13 +30,13 @@ CONFIG_IMX_THERMAL=y # CONFIG_DM_MMC_OPS is not set CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y CONFIG_VIDEO=y CONFIG_VIDEO_IPUV3=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_DMA_SUPPORT=y -- cgit v0.10.2 From b8ad70f70655d4a53c4014e768a25194c8a4b219 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:56:51 +0100 Subject: arm: dts: Add devicetree for i.MX6UL Add i.MX6UL dtsi support from Linux. Here is the last commit: "ARM: dts: add gpio-ranges property to iMX GPIO controllers" (sha1: bb728d662bed0fe91b152550e640cb3f6caa972c) Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi new file mode 100644 index 0000000..c5c05fd --- /dev/null +++ b/arch/arm/dts/imx6ul.dtsi @@ -0,0 +1,942 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include "imx6ul-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + sai1 = &sai1; + sai2 = &sai2; + sai3 = &sai3; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-latency = <61036>; /* two CLK32 periods */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + clocks = <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL2_BUS>, + <&clks IMX6UL_CLK_PLL2_PFD2>, + <&clks IMX6UL_CA7_SECONDARY_SEL>, + <&clks IMX6UL_CLK_STEP>, + <&clks IMX6UL_CLK_PLL1_SW>, + <&clks IMX6UL_CLK_PLL1_SYS>, + <&clks IMX6UL_PLL1_BYPASS>, + <&clks IMX6UL_CLK_PLL1>, + <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_CLK_OSC>; + clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", + "secondary_sel", "step", "pll1_sw", + "pll1_sys", "pll1_bypass", "pll1", + "pll1_bypass_src", "osc"; + arm-supply = <®_arm>; + soc-supply = <®_soc>; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a02000 0x1000>, + <0x00a04000 0x2000>, + <0x00a06000 0x2000>; + }; + + ckil: clock-cli { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + status = "disabled"; + }; + + ocram: sram@00900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + }; + + dma_apbh: dma-apbh@01804000 { + compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x01804000 0x2000>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX6UL_CLK_APBHDMA>; + }; + + gpmi: gpmi-nand@01806000 { + compatible = "fsl,imx6q-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01806000 0x2000>, <0x01808000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clks IMX6UL_CLK_GPMI_IO>, + <&clks IMX6UL_CLK_GPMI_APB>, + <&clks IMX6UL_CLK_GPMI_BCH>, + <&clks IMX6UL_CLK_GPMI_BCH_APB>, + <&clks IMX6UL_CLK_PER_BCH>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + aips1: aips-bus@02000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + ecspi1: ecspi@02008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI1>, + <&clks IMX6UL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@0200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI2>, + <&clks IMX6UL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@02010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI3>, + <&clks IMX6UL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: ecspi@02014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ECSPI4>, + <&clks IMX6UL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart7: serial@02018000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02018000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART7_IPG>, + <&clks IMX6UL_CLK_UART7_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@02020000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART1_IPG>, + <&clks IMX6UL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart8: serial@02024000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x02024000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART8_IPG>, + <&clks IMX6UL_CLK_UART8_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + sai1: sai@02028000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; + reg = <0x02028000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SAI1_IPG>, + <&clks IMX6UL_CLK_SAI1>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma 35 24 0>, + <&sdma 36 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai2: sai@0202c000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; + reg = <0x0202c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SAI2_IPG>, + <&clks IMX6UL_CLK_SAI2>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma 37 24 0>, + <&sdma 38 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@02030000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; + reg = <0x02030000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SAI3_IPG>, + <&clks IMX6UL_CLK_SAI3>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma 39 24 0>, + <&sdma 40 24 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + tsc: tsc@02040000 { + compatible = "fsl,imx6ul-tsc"; + reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_ADC2>; + clock-names = "tsc", "adc"; + status = "disabled"; + }; + + pwm1: pwm@02080000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM1>, + <&clks IMX6UL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@02084000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM2>, + <&clks IMX6UL_CLK_PWM2>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@02088000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM3>, + <&clks IMX6UL_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@0208c000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM4>, + <&clks IMX6UL_CLK_PWM4>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + can1: flexcan@02090000 { + compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02090000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CAN1_IPG>, + <&clks IMX6UL_CLK_CAN1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can2: flexcan@02094000 { + compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02094000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_CAN2_IPG>, + <&clks IMX6UL_CLK_CAN2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt1: gpt@02098000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; + reg = <0x02098000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_GPT1_BUS>, + <&clks IMX6UL_CLK_GPT1_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, + <&iomuxc 16 33 16>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 65 29>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; + }; + + fec2: ethernet@020b4000 { + compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; + reg = <0x020b4000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_ENET>, + <&clks IMX6UL_CLK_ENET_AHB>, + <&clks IMX6UL_CLK_ENET_PTP>, + <&clks IMX6UL_CLK_ENET2_REF_125M>, + <&clks IMX6UL_CLK_ENET2_REF_125M>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<1>; + fsl,num-rx-queues=<1>; + status = "disabled"; + }; + + kpp: kpp@020b8000 { + compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_KPP>; + status = "disabled"; + }; + + wdog1: wdog@020bc000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_WDOG1>; + }; + + wdog2: wdog@020c0000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: ccm@020c4000 { + compatible = "fsl,imx6ul-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; + + anatop: anatop@020c8000 { + compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x1000>; + interrupts = , + , + ; + + reg_3p0: regulator-3p0 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + }; + + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , + ; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x60>; + status = "disabled"; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + }; + + epit1: epit@020d0000 { + reg = <0x020d0000 0x4000>; + interrupts = ; + }; + + epit2: epit@020d4000 { + reg = <0x020d4000 0x4000>; + interrupts = ; + }; + + src: src@020d8000 { + compatible = "fsl,imx6ul-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = , + ; + #reset-cells = <1>; + }; + + gpc: gpc@020dc000 { + compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + interrupt-parent = <&intc>; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6ul-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@020e4000 { + compatible = "fsl,imx6ul-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + gpt2: gpt@020e8000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; + reg = <0x020e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_GPT2_BUS>, + <&clks IMX6UL_CLK_GPT2_SERIAL>; + clock-names = "ipg", "per"; + }; + + sdma: sdma@020ec000 { + compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", + "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_SDMA>, + <&clks IMX6UL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + pwm5: pwm@020f0000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM5>, + <&clks IMX6UL_CLK_PWM5>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@020f4000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM6>, + <&clks IMX6UL_CLK_PWM6>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm7: pwm@020f8000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM7>, + <&clks IMX6UL_CLK_PWM7>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm8: pwm@020fc000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020fc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_PWM8>, + <&clks IMX6UL_CLK_PWM8>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; + + aips2: aips-bus@02100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@02184000 { + compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@02184200 { + compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + fec1: ethernet@02188000 { + compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupts = , + ; + clocks = <&clks IMX6UL_CLK_ENET>, + <&clks IMX6UL_CLK_ENET_AHB>, + <&clks IMX6UL_CLK_ENET_PTP>, + <&clks IMX6UL_CLK_ENET_REF>, + <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<1>; + fsl,num-rx-queues=<1>; + status = "disabled"; + }; + + usdhc1: usdhc@02190000 { + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@02194000 { + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + adc1: adc@02198000 { + compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; + reg = <0x02198000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_ADC1>; + num-channels = <2>; + clock-names = "adc"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; + status = "disabled"; + }; + + i2c1: i2c@021a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@021a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@021a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C3>; + status = "disabled"; + }; + + mmdc: mmdc@021b0000 { + compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + lcdif: lcdif@021c8000 { + compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; + reg = <0x021c8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, + <&clks IMX6UL_CLK_LCDIF_APB>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + qspi: qspi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; + reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX6UL_CLK_QSPI>, + <&clks IMX6UL_CLK_QSPI>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + uart2: serial@021e8000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART2_IPG>, + <&clks IMX6UL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@021ec000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART3_IPG>, + <&clks IMX6UL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@021f0000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021f0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART4_IPG>, + <&clks IMX6UL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@021f4000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021f4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART5_IPG>, + <&clks IMX6UL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c4: i2c@021f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_I2C4>; + status = "disabled"; + }; + + uart6: serial@021fc000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart"; + reg = <0x021fc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6UL_CLK_UART6_IPG>, + <&clks IMX6UL_CLK_UART6_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index 18de070..4623f17 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -234,6 +234,7 @@ #define IMX6UL_CLK_CSI_SEL 221 #define IMX6UL_CLK_CSI_PODF 222 #define IMX6UL_CLK_PLL3_120M 223 +#define IMX6UL_CLK_KPP 224 /* For i.MX6ULL */ #define IMX6UL_CLK_ESAI_SEL 224 #define IMX6UL_CLK_ESAI_PRED 225 -- cgit v0.10.2 From a5b9f8c8f07f2a901354a77c6131cb0429881bf8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:56:52 +0100 Subject: arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial support Boot Log: -------- U-Boot SPL 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30) Trying to boot from MMC1 U-Boot 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30 +0530) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 43C Reset cause: POR Model: Engicam GEAM6UL DRAM: 128 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 geam6ul> Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index df745cc..f225431 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -181,6 +181,16 @@ config TARGET_MX6UL_14X14_EVK select DM_THERMAL select SUPPORT_SPL +config TARGET_MX6UL_GEAM + bool "Support Engicam GEAM6UL" + select MX6UL + select OF_CONTROL + select DM + select DM_GPIO + select DM_MMC + select DM_THERMAL + select SUPPORT_SPL + config TARGET_MX6ULL_14X14_EVK bool "Support mx6ull_14x14_evk" select MX6ULL @@ -286,6 +296,7 @@ source "board/compulab/cm_fx6/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig" source "board/el/el6x/Kconfig" source "board/embest/mx6boards/Kconfig" +source "board/engicam/geam6ul/Kconfig" source "board/engicam/icorem6/Kconfig" source "board/freescale/mx6qarm2/Kconfig" source "board/freescale/mx6qsabreauto/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b8e1342..79c2d76 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -298,7 +298,8 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6sll-evk.dtb \ imx6dl-icore.dtb \ - imx6q-icore.dtb + imx6q-icore.dtb \ + imx6ul-geam-kit.dtb dtb-$(CONFIG_MX7) += imx7-colibri.dtb diff --git a/arch/arm/dts/imx6ul-geam-kit.dts b/arch/arm/dts/imx6ul-geam-kit.dts new file mode 100644 index 0000000..a039b6d --- /dev/null +++ b/arch/arm/dts/imx6ul-geam-kit.dts @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include +#include "imx6ul.dtsi" + +/ { + model = "Engicam GEAM6UL"; + compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; + + memory { + reg = <0x80000000 0x08000000>; + }; + + chosen { + stdout-path = &uart1; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; +}; diff --git a/board/engicam/geam6ul/Kconfig b/board/engicam/geam6ul/Kconfig new file mode 100644 index 0000000..8753d15 --- /dev/null +++ b/board/engicam/geam6ul/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6UL_GEAM + +config SYS_BOARD + default "geam6ul" + +config SYS_VENDOR + default "engicam" + +config SYS_CONFIG_NAME + default "imx6ul_geam" + +endif diff --git a/board/engicam/geam6ul/MAINTAINERS b/board/engicam/geam6ul/MAINTAINERS new file mode 100644 index 0000000..6691450 --- /dev/null +++ b/board/engicam/geam6ul/MAINTAINERS @@ -0,0 +1,6 @@ +GEAM6UL BOARD +M: Jagan Teki +S: Maintained +F: board/engicam/geam6ul +F: include/configs/imx6ul_geam.h +F: configs/imx6ul_geam_mmc_defconfig diff --git a/board/engicam/geam6ul/Makefile b/board/engicam/geam6ul/Makefile new file mode 100644 index 0000000..0e367e2 --- /dev/null +++ b/board/engicam/geam6ul/Makefile @@ -0,0 +1,6 @@ +# Copyright (C) 2016 Amarula Solutions B.V. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := geam6ul.o diff --git a/board/engicam/geam6ul/README b/board/engicam/geam6ul/README new file mode 100644 index 0000000..0df6ae4 --- /dev/null +++ b/board/engicam/geam6ul/README @@ -0,0 +1,28 @@ +How to use U-Boot on Engicam GEAM6UL Starter Kit: +------------------------------------------------- + +- Configure U-Boot for Engicam GEAM6UL: + +$ make mrproper +$ make imx6ul_geam_mmc_defconfig +$ make + +This will generate the SPL image called SPL and the u-boot-dtb.img. + +- Flash the SPL image into the micro SD card: + +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + +- Flash the u-boot-dtb.img image into the micro SD card: + +sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Jumper settings: + +MMC Boot: JM3 Closed + +- Connect the Serial cable between the Starter Kit and the PC for the console. +(J28 is the Linux Serial console connector) + +- Insert the micro SD card in the board, power it up and U-Boot messages should +come up. diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c new file mode 100644 index 0000000..8530845 --- /dev/null +++ b/board/engicam/geam6ul/geam6ul.c @@ -0,0 +1,246 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * Author: Jagan Teki + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include +#include + +#include +#include + +/* MMC board initialization is needed till adding DM support in SPL */ +#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) +#include +#include + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) + +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} +#endif /* CONFIG_FSL_ESDHC */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00070007, + .p0_mpdgctrl0 = 0x41490145, + .p0_mprddlctl = 0x40404546, + .p0_mpwrdlctl = 0x4040524D, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 13, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig new file mode 100644 index 0000000..24f3fd6 --- /dev/null +++ b/configs/imx6ul_geam_mmc_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_GEAM=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" +CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb" +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit" +CONFIG_SYS_PROMPT="geam6ul> " +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTO_COMPLETE=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_IMLS is not set +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_EXT_SUPPORT=y diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h new file mode 100644 index 0000000..794a656 --- /dev/null +++ b/include/configs/imx6ul_geam.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * Configuration settings for the Engicam GEAM6UL Starter Kits. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX6UL_GEAM_CONFIG_H +#define __IMX6UL_GEAM_CONFIG_H + +#include +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE SZ_128K + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Environment */ +#ifndef CONFIG_ENV_IS_NOWHERE +/* Environment in MMC */ +# if defined(CONFIG_ENV_IS_IN_MMC) +# define CONFIG_ENV_OFFSET 0x100000 +# endif +#endif + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x87800000\0" \ + "boot_fdt=try\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_SP_OFFSET) + +/* UART */ +#ifdef CONFIG_MXC_UART +# define CONFIG_MXC_UART_BASE UART1_BASE +#endif + +/* MMC */ +#ifdef CONFIG_FSL_USDHC +# define CONFIG_SYS_MMC_ENV_DEV 0 +# define CONFIG_SYS_FSL_USDHC_NUM 1 +# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#endif + +/* SPL */ +#ifdef CONFIG_SPL +# define CONFIG_SPL_MMC_SUPPORT + +# include "imx6_spl.h" +# ifdef CONFIG_SPL_BUILD +# undef CONFIG_DM_GPIO +# undef CONFIG_DM_MMC +# endif +#endif + +#endif /* __IMX6UL_GEAM_CONFIG_H */ -- cgit v0.10.2 From 6116da989009bdfe3397f58b3e05461ab5cb3852 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:56:53 +0100 Subject: arm: dts: imx6ul-geam: Add I2C nodes Add I2C nodes for Engicam GEAM6UL module. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/dts/imx6ul-geam-kit.dts b/arch/arm/dts/imx6ul-geam-kit.dts index a039b6d..3672b02 100644 --- a/arch/arm/dts/imx6ul-geam-kit.dts +++ b/arch/arm/dts/imx6ul-geam-kit.dts @@ -59,6 +59,20 @@ }; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -77,6 +91,20 @@ }; &iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 -- cgit v0.10.2 From d31373c4acf6ffa8ecc496644263db61c98a6c9d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:56:54 +0100 Subject: imx6: geam6ul: Add I2C support Add I2C support for Engicam GEAM6UL module. geam6ul> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 geam6ul> i2c dev 0 Setting bus to 0 geam6ul> i2c dev Current bus is 0 geam6ul> i2c speed 100000 Setting bus speed to 100000 Hz geam6ul> i2c probe Valid chip addresses: 2C geam6ul> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index f225431..4f9b2e1 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -187,6 +187,7 @@ config TARGET_MX6UL_GEAM select OF_CONTROL select DM select DM_GPIO + select DM_I2C select DM_MMC select DM_THERMAL select SUPPORT_SPL diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 24f3fd6..e1e1dd2 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -25,11 +25,13 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_I2C=y CONFIG_OF_LIBFDT=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -- cgit v0.10.2 From 084cbb604807387b1a6ede1876273fbf056d6d48 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:56:55 +0100 Subject: imx6: geam6ul: Add NAND support Add NAND support for Engicam GEAM6UL board. Boot Log: -------- U-Boot SPL 2016.11-g537fa5f (Nov 28 2016 - 11:42:28) Trying to boot from NAND NAND : 256 MiB U-Boot 2016.11-g537fa5f (Nov 28 2016 - 11:20:06 +0100) CPU: Freescale i.MX6UL rev1.1 69 MHz (running at 396 MHz) CPU: Automotive temperature grade (-40C to 125C) at 42C Reset cause: WDOG Model: Engicam GEAM6UL DRAM: 128 MiB NAND: 256 MiB MMC: FSL_SDHC: 0 * Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c index 8530845..40f20a9 100644 --- a/board/engicam/geam6ul/geam6ul.c +++ b/board/engicam/geam6ul/geam6ul.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -36,11 +37,81 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_NAND_MXS + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* + * config gpmi and bch clock to 100 MHz + * bch/gpmi select PLL2 PFD2 400M + * 100M = 400M / 4 + */ + clrbits_le32(&mxc_ccm->cscmr1, + MXC_CCM_CSCMR1_BCH_CLK_SEL | + MXC_CCM_CSCMR1_GPMI_CLK_SEL); + clrsetbits_le32(&mxc_ccm->cscdr1, + MXC_CCM_CSCDR1_BCH_PODF_MASK | + MXC_CCM_CSCDR1_GPMI_PODF_MASK, + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif /* CONFIG_NAND_MXS */ + int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + return 0; } diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig new file mode 100644 index 0000000..b7a44c7 --- /dev/null +++ b/configs/imx6ul_geam_nand_defconfig @@ -0,0 +1,34 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_GEAM=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" +CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb" +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit" +CONFIG_SYS_PROMPT="geam6ul> " +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTO_COMPLETE=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_IMLS is not set +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_NAND=y +CONFIG_CMD_CACHE=y +CONFIG_OF_LIBFDT=y +CONFIG_MXC_UART=y +CONFIG_NAND_MXS=y +CONFIG_IMX_THERMAL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_DMA_SUPPORT=y diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h index 794a656..4fe130b 100644 --- a/include/configs/imx6ul_geam.h +++ b/include/configs/imx6ul_geam.h @@ -27,6 +27,10 @@ /* Environment in MMC */ # if defined(CONFIG_ENV_IS_IN_MMC) # define CONFIG_ENV_OFFSET 0x100000 +/* Environment in NAND */ +# elif defined(CONFIG_ENV_IS_IN_NAND) +# define CONFIG_ENV_OFFSET 0x400000 +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -111,9 +115,27 @@ # define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #endif +/* NAND */ +#ifdef CONFIG_NAND_MXS +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_BASE 0x40000000 +# define CONFIG_SYS_NAND_5_ADDR_CYCLE +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +# define CONFIG_APBH_DMA +# define CONFIG_APBH_DMA_BURST +# define CONFIG_APBH_DMA_BURST8 +#endif + /* SPL */ #ifdef CONFIG_SPL -# define CONFIG_SPL_MMC_SUPPORT +# ifdef CONFIG_NAND_MXS +# define CONFIG_SPL_NAND_SUPPORT +# else +# define CONFIG_SPL_MMC_SUPPORT +# endif # include "imx6_spl.h" # ifdef CONFIG_SPL_BUILD -- cgit v0.10.2 From b05c344809ef45be7a5df9b6f4cc694551b0d66e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:56:56 +0100 Subject: imx6: geam6ul: Enable MTD device support Enable MTD device, partition and command support. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h index 4fe130b..8938b80 100644 --- a/include/configs/imx6ul_geam.h +++ b/include/configs/imx6ul_geam.h @@ -124,6 +124,12 @@ # define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE # define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 +/* MTD device */ +# define CONFIG_MTD_DEVICE +# define CONFIG_CMD_MTDPARTS +# define CONFIG_MTD_PARTITIONS +# define MTDIDS_DEFAULT "nand0=nand" + # define CONFIG_APBH_DMA # define CONFIG_APBH_DMA_BURST # define CONFIG_APBH_DMA_BURST8 -- cgit v0.10.2 From 704b9cfc9e81dd22d94d67ed6952f1a7132f9f15 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:56:57 +0100 Subject: imx6: geam6ul: Add default mtd nand partition table geam6ul> mtdparts device nand0 , # parts = 6 0: spl 0x00200000 0x00000000 0 1: uboot 0x00200000 0x00200000 0 2: env 0x00100000 0x00400000 0 3: kernel 0x00400000 0x00500000 0 4: dtb 0x00100000 0x00900000 0 5: rootfs 0x1f600000 0x00a00000 0 Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h index 8938b80..7cfdfef 100644 --- a/include/configs/imx6ul_geam.h +++ b/include/configs/imx6ul_geam.h @@ -129,6 +129,8 @@ # define CONFIG_CMD_MTDPARTS # define CONFIG_MTD_PARTITIONS # define MTDIDS_DEFAULT "nand0=nand" +# define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl),2m(uboot)," \ + "1m(env),4m(kernel),1m(dtb),-(rootfs)" # define CONFIG_APBH_DMA # define CONFIG_APBH_DMA_BURST -- cgit v0.10.2 From 871ec6da42a52d24f700c708d90b194c83a06a9a Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:56:58 +0100 Subject: arm: imx6q: Add Engicam i.CoreM6 Quad/Dual RQS Starter Kit initial support Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44 +0530) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 4f9b2e1..7ad2d05 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -133,6 +133,16 @@ config TARGET_MX6Q_ICORE select DM_THERMAL select SUPPORT_SPL +config TARGET_MX6Q_ICORE_RQS + bool "Support Engicam i.Core RQS" + select MX6QDL + select OF_CONTROL + select DM + select DM_GPIO + select DM_MMC + select DM_THERMAL + select SUPPORT_SPL + config TARGET_MX6QSABREAUTO bool "mx6qsabreauto" select DM @@ -299,6 +309,7 @@ source "board/el/el6x/Kconfig" source "board/embest/mx6boards/Kconfig" source "board/engicam/geam6ul/Kconfig" source "board/engicam/icorem6/Kconfig" +source "board/engicam/icorem6_rqs/Kconfig" source "board/freescale/mx6qarm2/Kconfig" source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 79c2d76..a3a6502 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -299,6 +299,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6sll-evk.dtb \ imx6dl-icore.dtb \ imx6q-icore.dtb \ + imx6q-icore-rqs.dtb \ imx6ul-geam-kit.dtb dtb-$(CONFIG_MX7) += imx7-colibri.dtb diff --git a/arch/arm/dts/imx6q-icore-rqs.dts b/arch/arm/dts/imx6q-icore-rqs.dts new file mode 100644 index 0000000..9fa6ba0 --- /dev/null +++ b/arch/arm/dts/imx6q-icore-rqs.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015 Amarula Solutions B.V. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore-rqs.dtsi" + +/ { + model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit"; + compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi new file mode 100644 index 0000000..343ab35 --- /dev/null +++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2015 Amarula Solutions B.V. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +/ { + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 + >; + }; +}; diff --git a/board/engicam/icorem6_rqs/Kconfig b/board/engicam/icorem6_rqs/Kconfig new file mode 100644 index 0000000..1352c68 --- /dev/null +++ b/board/engicam/icorem6_rqs/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6Q_ICORE_RQS + +config SYS_BOARD + default "icorem6_rqs" + +config SYS_VENDOR + default "engicam" + +config SYS_CONFIG_NAME + default "imx6qdl_icore_rqs" + +endif diff --git a/board/engicam/icorem6_rqs/MAINTAINERS b/board/engicam/icorem6_rqs/MAINTAINERS new file mode 100644 index 0000000..4c6bd62 --- /dev/null +++ b/board/engicam/icorem6_rqs/MAINTAINERS @@ -0,0 +1,6 @@ +ICOREM6QDL_RQS BOARD +M: Jagan Teki +S: Maintained +F: board/engicam/icorem6_rqs +F: include/configs/imx6qdl_icore_rqs.h +F: configs/imx6q_icore_rqs_mmc_defconfig diff --git a/board/engicam/icorem6_rqs/Makefile b/board/engicam/icorem6_rqs/Makefile new file mode 100644 index 0000000..2e3933c --- /dev/null +++ b/board/engicam/icorem6_rqs/Makefile @@ -0,0 +1,6 @@ +# Copyright (C) 2016 Amarula Solutions B.V. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := icorem6_rqs.o diff --git a/board/engicam/icorem6_rqs/README b/board/engicam/icorem6_rqs/README new file mode 100644 index 0000000..f94e6e1 --- /dev/null +++ b/board/engicam/icorem6_rqs/README @@ -0,0 +1,30 @@ +How to use U-Boot on Engicam i.CoreM6 RQS Quad/Dual Starter Kit: +---------------------------------------------------------------- + +$ make mrproper + +- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual: +$ make imx6q_icore_rqs_mmc_defconfig + +- Build U-Boot +$ make + +This will generate the SPL image called SPL and the u-boot-dtb.img. + +- Flash the SPL image into the micro SD card: + +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + +- Flash the u-boot-dtb.img image into the micro SD card: + +sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Jumper settings: + +MMC Boot: JM3 Closed + +- Connect the Serial cable between the Starter Kit and the PC for the console. +(J28 is the Linux Serial console connector) + +- Insert the micro SD card in the board, power it up and U-Boot messages should +come up. diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c new file mode 100644 index 0000000..2769177 --- /dev/null +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -0,0 +1,399 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * Author: Jagan Teki + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart4_pads[] = { + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +int board_early_init_f(void) +{ + SETUP_IOMUX_PADS(uart4_pads); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include +#include + +#include +#include + +/* MMC board initialization is needed till adding DM support in SPL */ +#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) +#include +#include + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR, 1, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = 1; + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} +#endif + +/* + * Driving strength: + * 0x30 == 40 Ohm + * 0x28 == 48 Ohm + */ + +#define IMX6DQ_DRIVE_STRENGTH 0x30 +#define IMX6SDL_DRIVE_STRENGTH 0x28 + +/* configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + .dram_sdqs0 = 0x28, + .dram_sdqs1 = 0x28, + .dram_sdqs2 = 0x28, + .dram_sdqs3 = 0x28, + .dram_sdqs4 = 0x28, + .dram_sdqs5 = 0x28, + .dram_sdqs6 = 0x28, + .dram_sdqs7 = 0x28, + .dram_dqm0 = 0x28, + .dram_dqm1 = 0x28, + .dram_dqm2 = 0x28, + .dram_dqm3 = 0x28, + .dram_dqm4 = 0x28, + .dram_dqm5 = 0x28, + .dram_dqm6 = 0x28, + .dram_dqm7 = 0x28, + .dram_cas = 0x30, + .dram_ras = 0x30, + .dram_sdclk_0 = 0x30, + .dram_sdclk_1 = 0x30, + .dram_reset = 0x30, + .dram_sdcke0 = 0x3000, + .dram_sdcke1 = 0x3000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x30, + .dram_sdodt1 = 0x30, +}; + +/* configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + .grp_b0ds = 0x30, + .grp_b1ds = 0x30, + .grp_b2ds = 0x30, + .grp_b3ds = 0x30, + .grp_b4ds = 0x30, + .grp_b5ds = 0x30, + .grp_b6ds = 0x30, + .grp_b7ds = 0x30, + .grp_addds = 0x30, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ctlds = 0x30, + .grp_ddr_type = 0x000c0000, +}; + +/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + .dram_sdclk_0 = 0x30, + .dram_sdclk_1 = 0x30, + .dram_cas = 0x30, + .dram_ras = 0x30, + .dram_reset = 0x30, + .dram_sdcke0 = 0x30, + .dram_sdcke1 = 0x30, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x30, + .dram_sdodt1 = 0x30, + .dram_sdqs0 = 0x28, + .dram_sdqs1 = 0x28, + .dram_sdqs2 = 0x28, + .dram_sdqs3 = 0x28, + .dram_sdqs4 = 0x28, + .dram_sdqs5 = 0x28, + .dram_sdqs6 = 0x28, + .dram_sdqs7 = 0x28, + .dram_dqm0 = 0x28, + .dram_dqm1 = 0x28, + .dram_dqm2 = 0x28, + .dram_dqm3 = 0x28, + .dram_dqm4 = 0x28, + .dram_dqm5 = 0x28, + .dram_dqm6 = 0x28, + .dram_dqm7 = 0x28, +}; + +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x30, + .grp_ctlds = 0x30, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x28, + .grp_b1ds = 0x28, + .grp_b2ds = 0x28, + .grp_b3ds = 0x28, + .grp_b4ds = 0x28, + .grp_b5ds = 0x28, + .grp_b6ds = 0x28, + .grp_b7ds = 0x28, +}; + +/* mt41j256 */ +static struct mx6_ddr3_cfg mt41j256 = { + .mem_speed = 1066, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 13, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 0, +}; + +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + .p0_mpwldectrl0 = 0x000E0009, + .p0_mpwldectrl1 = 0x0018000E, + .p1_mpwldectrl0 = 0x00000007, + .p1_mpwldectrl1 = 0x00000000, + .p0_mpdgctrl0 = 0x43280334, + .p0_mpdgctrl1 = 0x031C0314, + .p1_mpdgctrl0 = 0x4318031C, + .p1_mpdgctrl1 = 0x030C0258, + .p0_mprddlctl = 0x3E343A40, + .p1_mprddlctl = 0x383C3844, + .p0_mpwrdlctl = 0x40404440, + .p1_mpwrdlctl = 0x4C3E4446, +}; + +/* DDR 64bit */ +static struct mx6_ddr_sysinfo mem_q = { + .ddr_type = DDR_TYPE_DDR3, + .dsize = 2, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 2, + .rtt_wr = 2, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { + .p0_mpwldectrl0 = 0x001F0024, + .p0_mpwldectrl1 = 0x00110018, + .p1_mpwldectrl0 = 0x001F0024, + .p1_mpwldectrl1 = 0x00110018, + .p0_mpdgctrl0 = 0x4230022C, + .p0_mpdgctrl1 = 0x02180220, + .p1_mpdgctrl0 = 0x42440248, + .p1_mpdgctrl1 = 0x02300238, + .p0_mprddlctl = 0x44444A48, + .p1_mprddlctl = 0x46484A42, + .p0_mpwrdlctl = 0x38383234, + .p1_mpwrdlctl = 0x3C34362E, +}; + +/* DDR 64bit 1GB */ +static struct mx6_ddr_sysinfo mem_dl = { + .dsize = 2, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 1, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +/* DDR 32bit 512MB */ +static struct mx6_ddr_sysinfo mem_s = { + .dsize = 1, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 1, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00003F3F, &ccm->CCGR0); + writel(0x0030FC00, &ccm->CCGR1); + writel(0x000FC000, &ccm->CCGR2); + writel(0x3F300000, &ccm->CCGR3); + writel(0xFF00F300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003CC, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +static void spl_dram_init(void) +{ + if (is_mx6solo()) { + mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); + } else if (is_mx6dl()) { + mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); + } else if (is_mx6dq()) { + mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); + mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); + } + + udelay(100); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + gpr_init(); + + /* iomux */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/configs/imx6q_icore_rqs_mmc_defconfig b/configs/imx6q_icore_rqs_mmc_defconfig new file mode 100644 index 0000000..eeecef8 --- /dev/null +++ b/configs/imx6q_icore_rqs_mmc_defconfig @@ -0,0 +1,38 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6Q_ICORE_RQS=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" +CONFIG_DEFAULT_FDT_FILE="imx6q-icore-rqs.dtb" +CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs" +CONFIG_SYS_PROMPT="icorem6qdl-rqs> " +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTO_COMPLETE=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_IMLS is not set +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y +CONFIG_MXC_UART=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_EXT_SUPPORT=y diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h new file mode 100644 index 0000000..7960355 --- /dev/null +++ b/include/configs/imx6qdl_icore_rqs.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * Configuration settings for the Engicam i.CoreM6 QDL RQS Starter Kits. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX6QLD_ICORE_RQS_CONFIG_H +#define __IMX6QLD_ICORE_RQS_CONFIG_H + +#include +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE SZ_128K + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Environment */ +#ifndef CONFIG_ENV_IS_NOWHERE +/* Environment in MMC */ +# if defined(CONFIG_ENV_IS_IN_MMC) +# define CONFIG_ENV_OFFSET 0x100000 +# endif +#endif + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc3\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x18000000\0" \ + "boot_fdt=try\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_SP_OFFSET) + +/* UART */ +#ifdef CONFIG_MXC_UART +# define CONFIG_MXC_UART_BASE UART4_BASE +#endif + +/* MMC */ +#ifdef CONFIG_FSL_USDHC +# define CONFIG_SYS_MMC_ENV_DEV 0 +# define CONFIG_SYS_FSL_USDHC_NUM 1 +# define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#endif + +/* SPL */ +#ifdef CONFIG_SPL +# define CONFIG_SPL_MMC_SUPPORT +# include "imx6_spl.h" +# ifdef CONFIG_SPL_BUILD +# undef CONFIG_DM_GPIO +# undef CONFIG_DM_MMC +# endif +#endif + +#endif /* __IMX6QLD_ICORE_RQS_CONFIG_H */ -- cgit v0.10.2 From 6121a54d603d03da2da87b10881a30a61a8614a3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:56:59 +0100 Subject: arm: imx6q: Add Engicam i.CoreM6 Solo/Duallite RQS Starter Kit initial support Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:56:07 +0530) CPU: Freescale i.MX6DL rev1.3 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 DualLite/Solo RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a3a6502..3ee608b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -298,6 +298,7 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6sll-evk.dtb \ imx6dl-icore.dtb \ + imx6dl-icore-rqs.dtb \ imx6q-icore.dtb \ imx6q-icore-rqs.dtb \ imx6ul-geam-kit.dtb diff --git a/arch/arm/dts/imx6dl-icore-rqs.dts b/arch/arm/dts/imx6dl-icore-rqs.dts new file mode 100644 index 0000000..0f1de3f --- /dev/null +++ b/arch/arm/dts/imx6dl-icore-rqs.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015 Amarula Solutions B.V. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore-rqs.dtsi" + +/ { + model = "Engicam i.CoreM6 DualLite/Solo RQS Starter Kit"; + compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; +}; diff --git a/board/engicam/icorem6_rqs/MAINTAINERS b/board/engicam/icorem6_rqs/MAINTAINERS index 4c6bd62..0556211 100644 --- a/board/engicam/icorem6_rqs/MAINTAINERS +++ b/board/engicam/icorem6_rqs/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/engicam/icorem6_rqs F: include/configs/imx6qdl_icore_rqs.h F: configs/imx6q_icore_rqs_mmc_defconfig +F: configs/imx6dl_icore_rqs_mmc_defconfig diff --git a/board/engicam/icorem6_rqs/README b/board/engicam/icorem6_rqs/README index f94e6e1..ccce622 100644 --- a/board/engicam/icorem6_rqs/README +++ b/board/engicam/icorem6_rqs/README @@ -1,11 +1,14 @@ -How to use U-Boot on Engicam i.CoreM6 RQS Quad/Dual Starter Kit: ----------------------------------------------------------------- +How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and Quad/Dual Starter Kit: +---------------------------------------------------------------------------------- $ make mrproper - Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual: $ make imx6q_icore_rqs_mmc_defconfig +- Configure U-Boot for Engicam i.CoreM6 RQS Solo/DualLite: +$ make imx6dl_icore_rqs_mmc_defconfig + - Build U-Boot $ make diff --git a/configs/imx6dl_icore_rqs_mmc_defconfig b/configs/imx6dl_icore_rqs_mmc_defconfig new file mode 100644 index 0000000..7fc7fa0 --- /dev/null +++ b/configs/imx6dl_icore_rqs_mmc_defconfig @@ -0,0 +1,38 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6Q_ICORE_RQS=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" +CONFIG_DEFAULT_FDT_FILE="imx6dl-icore-rqs.dtb" +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore-rqs" +CONFIG_SYS_PROMPT="icorem6qdl-rqs> " +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTO_COMPLETE=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_IMLS is not set +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y +CONFIG_MXC_UART=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_EXT_SUPPORT=y -- cgit v0.10.2 From 5bdf6b574a06fca4a3d7b797ee577d1d18fd3c51 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:57:00 +0100 Subject: imx6: icorem6: Rename engicam icorem6 defconfig files Rename defconfig files for better compatible with respective board names and dts files. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/board/engicam/icorem6/MAINTAINERS b/board/engicam/icorem6/MAINTAINERS index a425afb..0ef3a2c 100644 --- a/board/engicam/icorem6/MAINTAINERS +++ b/board/engicam/icorem6/MAINTAINERS @@ -3,5 +3,7 @@ M: Jagan Teki S: Maintained F: board/engicam/icorem6 F: include/configs/imx6qdl_icore.h -F: configs/imx6qdl_icore_mmc_defconfig -F: configs/imx6qdl_icore_nand_defconfig +F: configs/imx6q_icore_mmc_defconfig +F: configs/imx6q_icore_nand_defconfig +F: configs/imx6dl_icore_mmc_defconfig +F: configs/imx6dl_icore_nand_defconfig diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README index e47f85f..6461c0a 100644 --- a/board/engicam/icorem6/README +++ b/board/engicam/icorem6/README @@ -1,18 +1,16 @@ -How to use U-Boot on Engicam i.CoreM6 DualLite/Solo and Quad/Dual Starter Kit: +How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and Quad/Dual Starter Kit: ----------------------------------------------------------------------------- -- Configure U-Boot for Engicam i.CoreM6 QDL: - $ make mrproper -$ make imx6qdl_icore_mmc_defconfig - -- Build for i.CoreM6 DualLite/Solo -$ make +- Configure U-Boot for Engicam i.CoreM6 Quad/Dual: +$ make imx6q_icore_mmc_defconfig -- Build for i.CoreM6 Quad/Dual +- Configure U-Boot for Engicam i.CoreM6 Solo/DualLite: +$ make imx6dl_icore_mmc_defconfig -$ make DEVICE_TREE=imx6q-icore +- Build U-Boot +$ make This will generate the SPL image called SPL and the u-boot-dtb.img. @@ -33,6 +31,3 @@ MMC Boot: JM3 Closed - Insert the micro SD card in the board, power it up and U-Boot messages should come up. - -- Note: For loading Linux on Quad/Dual modules set the dtb as - icorem6qdl> setenv fdt_file imx6q-icore.dtb diff --git a/configs/imx6dl_icore_mmc_defconfig b/configs/imx6dl_icore_mmc_defconfig new file mode 100644 index 0000000..5f09425 --- /dev/null +++ b/configs/imx6dl_icore_mmc_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6Q_ICORE=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" +CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb" +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" +CONFIG_SYS_PROMPT="icorem6qdl> " +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTO_COMPLETE=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_IMLS is not set +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y +CONFIG_FEC_MXC=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_EXT_SUPPORT=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig new file mode 100644 index 0000000..af3a9f8 --- /dev/null +++ b/configs/imx6dl_icore_nand_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6Q_ICORE=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" +CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb" +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" +CONFIG_SYS_PROMPT="icorem6qdl> " +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTO_COMPLETE=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_NAND=y +CONFIG_CMD_CACHE=y +CONFIG_OF_LIBFDT=y +CONFIG_FEC_MXC=y +CONFIG_MXC_UART=y +CONFIG_NAND_MXS=y +CONFIG_IMX_THERMAL=y +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_DMA_SUPPORT=y diff --git a/configs/imx6q_icore_mmc_defconfig b/configs/imx6q_icore_mmc_defconfig new file mode 100644 index 0000000..8f812b4 --- /dev/null +++ b/configs/imx6q_icore_mmc_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6Q_ICORE=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" +CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb" +CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" +CONFIG_SYS_PROMPT="icorem6qdl> " +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTO_COMPLETE=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_IMLS is not set +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y +CONFIG_FEC_MXC=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_EXT_SUPPORT=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig new file mode 100644 index 0000000..4735be8 --- /dev/null +++ b/configs/imx6q_icore_nand_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6Q_ICORE=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" +CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb" +CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" +CONFIG_SYS_PROMPT="icorem6qdl> " +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTO_COMPLETE=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_NAND=y +CONFIG_CMD_CACHE=y +CONFIG_OF_LIBFDT=y +CONFIG_FEC_MXC=y +CONFIG_MXC_UART=y +CONFIG_NAND_MXS=y +CONFIG_IMX_THERMAL=y +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_DMA_SUPPORT=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig deleted file mode 100644 index 5f09425..0000000 --- a/configs/imx6qdl_icore_mmc_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_TARGET_MX6Q_ICORE=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" -CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb" -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" -CONFIG_SYS_PROMPT="icorem6qdl> " -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_DISPLAY_CPUINFO=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTO_COMPLETE=y -CONFIG_SYS_MAXARGS=32 -# CONFIG_CMD_IMLS is not set -# CONFIG_BLK is not set -# CONFIG_DM_MMC_OPS is not set -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MMC=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_LIBFDT=y -CONFIG_FEC_MXC=y -CONFIG_MXC_UART=y -CONFIG_IMX_THERMAL=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_SYS_I2C_MXC=y -CONFIG_VIDEO=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_EXT_SUPPORT=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig deleted file mode 100644 index af3a9f8..0000000 --- a/configs/imx6qdl_icore_nand_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_TARGET_MX6Q_ICORE=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" -CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb" -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" -CONFIG_SYS_PROMPT="icorem6qdl> " -CONFIG_SPL=y -CONFIG_BOOTDELAY=3 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_DISPLAY_CPUINFO=y -CONFIG_HUSH_PARSER=y -CONFIG_AUTO_COMPLETE=y -CONFIG_SYS_MAXARGS=32 -# CONFIG_CMD_IMLS is not set -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_NAND=y -CONFIG_CMD_CACHE=y -CONFIG_OF_LIBFDT=y -CONFIG_FEC_MXC=y -CONFIG_MXC_UART=y -CONFIG_NAND_MXS=y -CONFIG_IMX_THERMAL=y -# CONFIG_BLK is not set -# CONFIG_DM_MMC_OPS is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_SYS_I2C_MXC=y -CONFIG_VIDEO=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_DMA_SUPPORT=y -- cgit v0.10.2 From 5fdea9ff00e316659db0056bf43b1faec6aa1d09 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:57:01 +0100 Subject: arm: dts: imx6qdl-icore-rqs: Add I2C node's Add I2C nodes for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi index 343ab35..2aaa6e4 100644 --- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi @@ -48,6 +48,26 @@ }; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -63,6 +83,27 @@ }; &iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 -- cgit v0.10.2 From dca7c2878aaf6b9139752b2835a35a5aa588a3b7 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:57:02 +0100 Subject: imx6: icorem6_rqs: Add I2C support Add I2C support for Engicam i.CoreM6 RQS modules. icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl-rqs> i2c dev 0 Setting bus to 0 icorem6qdl-rqs> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl-rqs> i2c probe Valid chip addresses: 4F icorem6qdl-rqs> i2c md 4F 0xff 00ff: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 (active 0) 4f: generic_4f, offset len 1, flags 0 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 7ad2d05..d9e63ff 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -139,6 +139,7 @@ config TARGET_MX6Q_ICORE_RQS select OF_CONTROL select DM select DM_GPIO + select DM_I2C select DM_MMC select DM_THERMAL select SUPPORT_SPL diff --git a/configs/imx6dl_icore_rqs_mmc_defconfig b/configs/imx6dl_icore_rqs_mmc_defconfig index 7fc7fa0..19a721c 100644 --- a/configs/imx6dl_icore_rqs_mmc_defconfig +++ b/configs/imx6dl_icore_rqs_mmc_defconfig @@ -25,10 +25,12 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_I2C=y CONFIG_OF_LIBFDT=y CONFIG_MXC_UART=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/imx6q_icore_rqs_mmc_defconfig b/configs/imx6q_icore_rqs_mmc_defconfig index eeecef8..bbd10af 100644 --- a/configs/imx6q_icore_rqs_mmc_defconfig +++ b/configs/imx6q_icore_rqs_mmc_defconfig @@ -25,10 +25,12 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_I2C=y CONFIG_OF_LIBFDT=y CONFIG_MXC_UART=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_I2C_MXC=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -- cgit v0.10.2 From b443c88b1a8dd74a63993d0fee0bec0aaca0d96e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:57:03 +0100 Subject: arm: dts: imx6ul-geam: Add FEC node Add FEC node for Engicam GEAM6UL module. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/dts/imx6ul-geam-kit.dts b/arch/arm/dts/imx6ul-geam-kit.dts index 3672b02..07c21cb 100644 --- a/arch/arm/dts/imx6ul-geam-kit.dts +++ b/arch/arm/dts/imx6ul-geam-kit.dts @@ -59,6 +59,13 @@ }; }; +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -91,6 +98,20 @@ }; &iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 -- cgit v0.10.2 From bd363f80e4462afe2b7551a87ac808a22de58aa1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:57:04 +0100 Subject: imx6: geam6ul: Add FEC support Add FEC support for Engicam GEAM6UL module. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index d9e63ff..058b62d 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -197,6 +197,7 @@ config TARGET_MX6UL_GEAM select MX6UL select OF_CONTROL select DM + select DM_ETH select DM_GPIO select DM_I2C select DM_MMC diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index e1e1dd2..d5be076 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -18,6 +18,8 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y @@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_I2C=y CONFIG_OF_LIBFDT=y +CONFIG_FEC_MXC=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_PINCTRL=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index b7a44c7..cc45602 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -18,9 +18,12 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_LIBFDT=y +CONFIG_FEC_MXC=y CONFIG_MXC_UART=y CONFIG_NAND_MXS=y CONFIG_IMX_THERMAL=y diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h index 7cfdfef..48b1120 100644 --- a/include/configs/imx6ul_geam.h +++ b/include/configs/imx6ul_geam.h @@ -137,6 +137,16 @@ # define CONFIG_APBH_DMA_BURST8 #endif +/* Ethernet */ +#ifdef CONFIG_FEC_MXC +# define CONFIG_FEC_MXC_PHYADDR 0 +# define CONFIG_FEC_XCV_TYPE RMII + +# define CONFIG_MII +# define CONFIG_PHYLIB +# define CONFIG_PHY_SMSC +#endif + /* SPL */ #ifdef CONFIG_SPL # ifdef CONFIG_NAND_MXS -- cgit v0.10.2 From fcf7748303d2320ff5cd068d1eb91b0f02e9fa9f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:57:05 +0100 Subject: arm: dts: imx6qdl-icore-rqs: Add FEC node Add FEC node for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi index 2aaa6e4..750229b 100644 --- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi @@ -48,6 +48,31 @@ }; }; +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-handle = <ð_phy>; + phy-mode = "rgmii"; + status = "okay"; + + mdio { + eth_phy: ethernet-phy { + rxc-skew-ps = <1140>; + txc-skew-ps = <1140>; + txen-skew-ps = <600>; + rxdv-skew-ps = <240>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <600>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <240>; + txd0-skew-ps = <60>; + txd1-skew-ps = <60>; + txd2-skew-ps = <60>; + txd3-skew-ps = <240>; + }; + }; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -83,6 +108,27 @@ }; &iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -- cgit v0.10.2 From 854bb75be98ad792ff64c26ae38a1392ea185cd6 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 13 Dec 2016 17:57:06 +0100 Subject: imx6: icorem6_rqs: Add FEC support Add FEC support for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic Cc: Matteo Lisi Cc: Michael Trimarchi Signed-off-by: Jagan Teki diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 058b62d..c646966 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -138,6 +138,7 @@ config TARGET_MX6Q_ICORE_RQS select MX6QDL select OF_CONTROL select DM + select DM_ETH select DM_GPIO select DM_I2C select DM_MMC diff --git a/configs/imx6dl_icore_rqs_mmc_defconfig b/configs/imx6dl_icore_rqs_mmc_defconfig index 19a721c..230cd20 100644 --- a/configs/imx6dl_icore_rqs_mmc_defconfig +++ b/configs/imx6dl_icore_rqs_mmc_defconfig @@ -18,6 +18,8 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y @@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_I2C=y CONFIG_OF_LIBFDT=y +CONFIG_FEC_MXC=y CONFIG_MXC_UART=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/configs/imx6q_icore_rqs_mmc_defconfig b/configs/imx6q_icore_rqs_mmc_defconfig index bbd10af..f7c25c4 100644 --- a/configs/imx6q_icore_rqs_mmc_defconfig +++ b/configs/imx6q_icore_rqs_mmc_defconfig @@ -18,6 +18,8 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y @@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_I2C=y CONFIG_OF_LIBFDT=y +CONFIG_FEC_MXC=y CONFIG_MXC_UART=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h index 7960355..0121563 100644 --- a/include/configs/imx6qdl_icore_rqs.h +++ b/include/configs/imx6qdl_icore_rqs.h @@ -111,6 +111,17 @@ # define CONFIG_SYS_FSL_ESDHC_ADDR 0 #endif +/* Ethernet */ +#ifdef CONFIG_FEC_MXC +# define CONFIG_FEC_MXC_PHYADDR 3 +# define CONFIG_FEC_XCV_TYPE RGMII + +# define CONFIG_MII +# define CONFIG_PHYLIB +# define CONFIG_PHY_MICREL +# define CONFIG_PHY_MICREL_KSZ9021 +#endif + /* SPL */ #ifdef CONFIG_SPL # define CONFIG_SPL_MMC_SUPPORT -- cgit v0.10.2