From be3d87ea442cfcba881357e5c92eefecb12e628e Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 10 Dec 2013 13:13:10 +0530 Subject: board/t1040qds: Fix typo in t1040_pbi.cfg file T1040QDS has 256KB SRAM. Comment is showing wrong information. So update the comment. Signed-off-by: Prabhakar Kushwaha diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg index 624398a..10b1a6d 100644 --- a/board/freescale/t1040qds/t1040_pbi.cfg +++ b/board/freescale/t1040qds/t1040_pbi.cfg @@ -3,7 +3,7 @@ 09010000 00200400 09138000 00000000 091380c0 00000100 -#Configure CPC1 as 512KB SRAM +#Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 09010f00 08000000 -- cgit v0.10.2 From fbe76ae4e3bacd5183294488947ec148df28d55b Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Wed, 11 Dec 2013 12:42:11 +0530 Subject: board/freescale:Remove use of CONFIG_SPL_NAND_MINIMAL CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary review purpose. So, use CONFIG_SPL_NAND_BOOT config. Signed-off-by: Prabhakar Kushwaha diff --git a/README b/README index 895fef3..e58e9c0 100644 --- a/README +++ b/README @@ -3267,6 +3267,9 @@ FIT uImage format: Defines the size and behavior of the NAND that SPL uses to read U-Boot + CONFIG_SPL_NAND_BOOT + Add support NAND boot + CONFIG_SYS_NAND_U_BOOT_OFFS Location in NAND to read U-Boot from diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index 669fe8a..c8ecf5d 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c index 02655e9..07febc2 100644 --- a/board/freescale/bsc9132qds/tlb.c +++ b/board/freescale/bsc9132qds/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index a7af0f6..a3d36b3 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_MINIMAL +#ifdef CONFIG_SPL_NAND_BOOT SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_4K, 1), diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 4aed5af..584aba8 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -29,7 +29,7 @@ #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index f025e31..6170cbc 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -38,7 +38,7 @@ #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index fe5309a..ea5cb65 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -37,7 +37,7 @@ #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -- cgit v0.10.2 From 562de1d6da5bdc1789bd258d464d6ca57571861d Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 12 Dec 2013 12:09:01 +0530 Subject: board/t1040qds: Relax IFC FPGA timings Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion) is 0 i.e. 0 ns hold time on writes. This may not work on higher clock freqencies. So, Increase TCH as 0x8 i.e. 8 ip_clk. Signed-off-by: Prabhakar Kushwaha diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index d0ebd6a..8ecf188 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -248,7 +248,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -- cgit v0.10.2 From b135991a3cddd1a266c5fbd64e25eaaa61bde2d8 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 17 Dec 2013 14:25:52 +0530 Subject: powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain diff --git a/README b/README index e58e9c0..a0646c3 100644 --- a/README +++ b/README @@ -423,6 +423,11 @@ The following options need to be configured: CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. + CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + Single Source Clock is clocking mode present in some of FSL SoC's. + In this mode, a single differential clock is used to supply + clocks to the sysclock, ddrclock and usbclock. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 7c7467f..35867df 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -74,12 +74,33 @@ void get_sys_info(sys_info_t *sys_info) uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; uint mem_pll_rat; +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + uint single_src; +#endif sys_info->freq_systembus = sysclk; +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + /* + * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS + * are driven by separate DDR Refclock or single source + * differential clock. + */ + single_src = (in_be32(&gur->rcwsr[5]) >> + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; + /* + * For single source clocking, both ddrclock and syclock + * are driven by differential sysclock. + */ + if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) { + printf("Single Source Clock Configuration\n"); + sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; + } else +#endif #ifdef CONFIG_DDR_CLK_FREQ - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; #else - sys_info->freq_ddrbus = sysclk; + sys_info->freq_ddrbus = sysclk; #endif sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 244ccbf..3d8bd9a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -711,6 +711,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 672e8c6..68c3c82 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1774,6 +1774,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 -- cgit v0.10.2 From 9407c3fc2ea9f61243cd460a3fe64dfb396b3721 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 17 Dec 2013 11:21:08 -0800 Subject: powerpc/P1022DS: Define new nand_ecclayout structure macros Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to reduce the image size, by taking advantage of the new nand_ecclayout structure. Signed-off-by: York Sun CC: Prabhakar Kushwaha CC: Scott Wood diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index ba43cce..934a6cb 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -75,6 +75,8 @@ #endif #define CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 +#define CONFIG_SYS_NAND_MAX_OOBFREE 5 #ifdef CONFIG_NAND #define CONFIG_SPL -- cgit v0.10.2 From ab13ad58359e803d948267881e4f495927cb7548 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 17 Dec 2013 11:21:09 -0800 Subject: powerpc/B4860QDS: Define new nand_ecclayout structure macros Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to reduce the image size, by taking advantage of the new nand_ecclayout structure. Signed-off-by: York Sun CC: Prabhakar Kushwaha CC: Scott Wood diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 3c6cd61..c182158 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -289,6 +289,8 @@ unsigned long get_board_ddr_clk(void); /* NAND Flash on IFC */ #define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 #define CONFIG_SYS_NAND_BASE 0xff800000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) -- cgit v0.10.2 From 2ffa96d815c947ba09286e1a20ae832882707eba Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 18 Dec 2013 10:27:55 +0800 Subject: powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used, update it to new CONFIG_USB_MAX_CONTROLLER_COUNT. Signed-off-by: Shengzhou Liu diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 3d8bd9a..54ce2f0 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -746,7 +746,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 #endif -#define CONFIG_SYS_FSL_NUM_USB_CTRLS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV -- cgit v0.10.2 From 8fe207d0369dc31cd75b8660b48c1d77571a99e4 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Tue, 17 Dec 2013 22:11:07 -0600 Subject: powerpc/cms700: limit NAND data structure size This fixes a build break due to excessively large NAND data structures. Signed-off-by: Scott Wood Cc: Matthias Fuchs diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 4a5fc86..0bb22be 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -149,6 +149,9 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 48 + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is -- cgit v0.10.2 From c2444868ada52c7ae7ae92bcda3ebf7790615785 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Wed, 18 Dec 2013 15:09:57 +0800 Subject: powerpc/t4240: enable NAND boot support Signed-off-by: Shaohui Xie diff --git a/boards.cfg b/boards.cfg index c602a16..5d81e9f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -966,6 +966,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - -- cgit v0.10.2 From 3bce144b46c29e75e729f23a3728923e50a41df3 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Thu, 19 Dec 2013 13:38:11 +0800 Subject: powerpc/b4860/pbl: fix rcw cfg The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1. Signed-off-by: Shaohui Xie diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg index 577dabf..597d391 100644 --- a/board/freescale/b4860qds/b4_rcw.cfg +++ b/board/freescale/b4860qds/b4_rcw.cfg @@ -2,6 +2,6 @@ aa55aa55 010e0100 # serdes protocol 0x2A_0x98 140e0018 0f001218 00000000 00000000 -54980000 9000a000 f8025000 a9000000 +54980000 9000a000 e8104000 a9000000 01000000 00000000 00000000 0001b1f8 00000000 14000020 00000000 00000011 -- cgit v0.10.2 From 8c618dd66adfab736b88a86f51c057b019988a90 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 26 Dec 2013 12:40:55 +0530 Subject: board/t1040qds: Enable memory reset control Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start accessing it. Signed-off-by: Prabhakar Kushwaha diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 2aa176c..de3ea5c 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -239,3 +239,8 @@ void qixis_dump_switch(void) printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } } + +int board_need_mem_reset(void) +{ + return 1; +} diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8ecf188..7d0bc04 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -233,6 +233,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 #define CONFIG_SYS_CSPR3_EXT (0xf) #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ -- cgit v0.10.2