From 6e474eab446432e7480394ca3833c89a01dba078 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 22 Aug 2015 18:31:37 -0600
Subject: exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS
 devices

Add a TPM node to the various Chromebooks so that driver can be converted to
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Christophe Ricard<christophe-h.ricard@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index 32c0098..bda5499 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -206,6 +206,15 @@
 		};
 	};
 
+	i2c@12C90000 {
+		clock-frequency = <100000>;
+		tpm@20 {
+			reg = <0x20>;
+			u-boot,i2c-offset-len = <0>;
+			compatible = "infineon,slb9635tt";
+		};
+	};
+
 	spi@12d30000 {
 		spi-max-frequency = <50000000>;
 		firmware_storage_spi: flash@0 {
diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts
index 76d5323..81b3d29 100644
--- a/arch/arm/dts/exynos5250-spring.dts
+++ b/arch/arm/dts/exynos5250-spring.dts
@@ -59,6 +59,14 @@
 					 <&gpy4 2 0>;
 	};
 
+	i2c@12C90000 {
+		clock-frequency = <100000>;
+		tpm@20 {
+			reg = <0x20>;
+			compatible = "infineon,slb9645tt";
+		};
+	};
+
 	mmc@12200000 {
 		samsung,bus-width = <8>;
 		samsung,timing = <1 3 3>;
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
index 2d2b7c9..16d52f4 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -197,9 +197,9 @@
 
 	i2c@12E10000 { /* i2c9 */
 		clock-frequency = <400000>;
-                tpm@20 {
-                        compatible = "infineon,slb9645tt";
-                        reg = <0x20>;
+		tpm@20 {
+			compatible = "infineon,slb9645tt";
+			reg = <0x20>;
 		};
 	};
 
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
index 600c294..1d7ff23 100644
--- a/arch/arm/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -72,9 +72,9 @@
 
 	i2c@12E10000 { /* i2c9 */
 		clock-frequency = <400000>;
-                tpm@20 {
-                        compatible = "infineon,slb9645tt";
-                        reg = <0x20>;
+		tpm@20 {
+			compatible = "infineon,slb9645tt";
+			reg = <0x20>;
 		};
 	};
 
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index ad390bf..4291141 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -237,6 +237,11 @@
 		};
 	};
 
+	tpm {
+		reg = <0xfed40000 0x5000>;
+		compatible = "infineon,slb9635lpc";
+	};
+
 	microcode {
 		update@0 {
 #include "microcode/m12306a9_0000001b.dtsi"
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 84eae3a..36feb96 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -62,4 +62,9 @@
 		};
 	};
 
+	tpm {
+		reg = <0xfed40000 0x5000>;
+		compatible = "infineon,slb9635lpc";
+	};
+
 };
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