From be9b56df02168ca97562d6b9ec791136e4cd925a Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Thu, 23 Jul 2009 14:09:38 -0500
Subject: mpc83xx: CONFIG_83XX_GENERIC_PCI is now synonymous with CONFIG_PCI;
 remove the former

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
index dd35e6b..15e2c18 100644
--- a/cpu/mpc83xx/Makefile
+++ b/cpu/mpc83xx/Makefile
@@ -38,8 +38,8 @@ COBJS-y += spd_sdram.o
 COBJS-y += ecc.o
 COBJS-$(CONFIG_QE) += qe_io.o
 COBJS-$(CONFIG_FSL_SERDES) += serdes.o
-COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
-COBJS-$(CONFIG_83XX_GENERIC_PCIE) += pcie.o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-$(CONFIG_PCIE) += pcie.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
 COBJS	:= $(COBJS-y)
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 049c80d..d9aa60b 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -36,7 +36,6 @@
 #define CONFIG_MPC8313ERDB	1
 
 #define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI
 
 #define CONFIG_MISC_INIT_R
 
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 7e6b9eb..d5e62e3 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -332,8 +332,7 @@
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
 
 #define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI	1 /* Use generic PCI setup */
-#define CONFIG_83XX_GENERIC_PCIE	1
+#define CONFIG_PCIE
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index b5820ce..907965d 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -18,7 +18,6 @@
 #define CONFIG_MPC832x		1	/* MPC832x CPU specific */
 
 #define CONFIG_PCI		1
-#define CONFIG_83XX_GENERIC_PCI	1
 
 /*
  * System Clock Setup
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 6928981..4e23a11 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -334,7 +334,6 @@
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
-#define CONFIG_83XX_GENERIC_PCI
 #define CONFIG_83XX_PCI_STREAMING
 
 #undef CONFIG_EEPRO100
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 63c6dbc..3cf59ef 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -38,9 +38,6 @@
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
 
-#undef CONFIG_PCI
-#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
-
 #define PCI_66M
 #ifdef PCI_66M
 #define CONFIG_83XX_CLKIN	66000000	/* in Hz */
@@ -374,7 +371,6 @@
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
-#define CONFIG_83XX_GENERIC_PCI
 #define CONFIG_83XX_PCI_STREAMING
 
 #undef CONFIG_EEPRO100
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 037cad5..068df57 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -382,7 +382,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
-#define CONFIG_83XX_GENERIC_PCI
 
 #ifndef CONFIG_PCI_PNP
     #define PCI_ENET0_IOADDR	0x00000000
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 028ef8c..fe6ec48 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -369,7 +369,6 @@
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
-#define CONFIG_83XX_GENERIC_PCI
 #define CONFIG_83XX_PCI_STREAMING
 
 #undef CONFIG_EEPRO100
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 4fcca09..68d68bb 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -277,7 +277,6 @@
  * Addresses are mapped 1-1.
  */
 #define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI	1
 
 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 9045bc5..a2a2aad 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -381,8 +381,7 @@
 #ifndef __ASSEMBLY__
 extern int board_pci_host_broken(void);
 #endif
-#define CONFIG_83XX_GENERIC_PCI	1 /* Use generic PCI setup */
-#define CONFIG_83XX_GENERIC_PCIE	1
+#define CONFIG_PCIE
 #define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */
 
 #define CONFIG_HAS_FSL_DR_USB	1 /* fixup device tree for the DR USB */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 9132718..b637f73 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -49,8 +49,7 @@
 #define CONFIG_83XX_PCICLK	66666667 /* in HZ */
 #else
 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
-#define CONFIG_83XX_GENERIC_PCI	1
-#define CONFIG_83XX_GENERIC_PCIE	1
+#define CONFIG_PCIE
 #endif
 
 #ifndef CONFIG_SYS_CLK_FREQ
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index ac8cb57..aa91805 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -40,7 +40,6 @@
 #define CONFIG_SYS_IMMR		0xE0000000
 
 #define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI
 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 #define CONFIG_HARD_I2C
 #define CONFIG_TSEC_ENET
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 08b401e..b847ce8 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -37,7 +37,6 @@
 #define CONFIG_MPC8313			1
 
 #define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI
 
 #define CONFIG_MISC_INIT_R
 
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 541a27b..492bdcc 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -247,7 +247,6 @@ extern int tqm834x_num_flash_banks;
 #if defined(CONFIG_PCI)
 
 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
-#define CONFIG_83XX_GENERIC_PCI
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
 /* PCI1 host bridge */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 20dcd1c..84a251a 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -329,7 +329,6 @@
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
-#define CONFIG_83XX_GENERIC_PCI
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
-- 
cgit v0.10.2


From fe613cdd4eb2c5b257a60d8dfb7759742318c28a Mon Sep 17 00:00:00 2001
From: Paul Gortmaker <paul.gortmaker@windriver.com>
Date: Thu, 23 Jul 2009 17:10:55 -0400
Subject: sbc8349: combine HRCW flash and u-boot image flash

Up to this point in time, the sbc8349 board was storing the u-boot
image in flash 2x.  One for the HRCW value at the beginning of
flash (0xff80_0000), and once close to the end of flash (0xfff8_0000)
for the actual image that got executed.

This moves the TEXT_BASE to be the beginning of flash, which makes
the second copy of the image redundant, and frees up the flash
from the end of the environment storage to the end of the flash
device itself.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/board/sbc8349/config.mk b/board/sbc8349/config.mk
index 05fa5a0..eacb27e 100644
--- a/board/sbc8349/config.mk
+++ b/board/sbc8349/config.mk
@@ -24,4 +24,4 @@
 # SBC8349E
 #
 
-TEXT_BASE  =   0xFFF00000
+TEXT_BASE  =   0xFF800000
diff --git a/doc/README.sbc8349 b/doc/README.sbc8349
index a0ac638..908e768 100644
--- a/doc/README.sbc8349
+++ b/doc/README.sbc8349
@@ -21,15 +21,22 @@ Flash Details:
 
 The flash type is intel 28F640Jx (4096x16) [one device].  Base address
 is 0xFF80_0000 which is also where the Hardware Reset Configuration
-Word (HRCW) is stored.  Caution should be used to not overwrite the
-HRCW, or "CF RCW" with a Wind River ICE will be required to restore
-the HRCW and allow the board to enter background mode for further
-steps in the flash process.
+Word (HRCW) is stored.  Caution should be used to not reset the
+board without having a valid HRCW in place (i.e. erased flash) as
+then a Wind River ICE will be required to restore the HRCW and flash
+image.
 
 
 Restoring a corrupted or missing flash image:
 =============================================
 
+Note that U-boot versions up to and including 2009.06 had essentially
+two copies of u-boot in flash; one at the very beginning, which set
+the HRCW, and one at the very end, which was the image that was run.
+As of this point in time, the two have been combined into just one
+at the beginning of flash, which provides both the HRCW, and the image
+that is executed.  This frees up the remainder of flash for other uses.
+Use of the u-boot command "fli" will indicate what parts are in use.
 Details for storing U-boot to flash using a Wind River ICE can be found
 on page 19 of the board manual (request ERG-00328-001).  The following
 is a summary of that information:
@@ -39,9 +46,9 @@ is a summary of that information:
   - Select the appropriate flash type (listed above)
   - Prepare a u-boot image by using the Wind River Convert utility;
     by using "Convert and Add file" on the ELF file from your build.
-    Convert from FFF0_0000 to FFFF_FFFF (or to FFF3_FFFF if you are
-    trying to preserve your old environment settings).
-  - Set the start address of the erase/flash process to FFF0_0000
+    Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are
+    trying to preserve your old environment settings and user flash).
+  - Set the start address of the erase/flash process to FF80_0000
   - Set the target RAM required to 64kB.
   - Select sectors for erasing (see note on enviroment below)
   - Select Erase and Reprogram.
@@ -59,7 +66,7 @@ beginning with "SCGA TSEC1" and "SCGA TSEC2".  This allows you to
 use all the remaining register file content.
 
 If you wish to preserve your prior U-Boot environment settings,
-then convert (and erase to) 0xFFF3FFFF instead of 0xFFFFFFFF.
+then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF.
 The size for converting (and erasing) must be at least as large
 as u-boot.bin.
 
@@ -73,10 +80,13 @@ has been copied to the TFTP server, the commands are:
 
 	tftp 200000 u-boot.bin
 	protect off all
-	erase fff00000 fff3ffff
-	cp.b 200000 fff00000 3ffff
+	erase ff800000 ff83ffff
+	cp.b 200000 ff800000 40000
 	protect on all
 
+You may wish to do a "md ff800000 20" operation as a prefix and postfix
+to the above steps to inspect/compare the HRCW before/after as an extra
+safety check before resetting the board upon completion of the reflash.
 
 PCI:
 ====
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 84a251a..868bd54 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -651,8 +651,8 @@
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
 		"bootm\0"						\
 	"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"		\
-	"update=protect off fff00000 fff3ffff; "			\
-		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0"	\
+	"update=protect off ff800000 ff83ffff; "			\
+		"era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0"	\
 	"upd=run load update\0"						\
 	"fdtaddr=400000\0"						\
 	"fdtfile=sbc8349.dtb\0"						\
-- 
cgit v0.10.2


From c2e49f706ba13213f3c8da3a33e88010214e1997 Mon Sep 17 00:00:00 2001
From: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Date: Sat, 25 Jul 2009 06:19:12 +0200
Subject: mpc83xx: Add esd VME8349 board support

This patch adds support for the esd VME8349 board equipped with the
MPC8349. It's a VME PMC carrier board equipped with the Tundra
TSI148 VME-bridge.

Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 8244b51..7bf4786 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -32,6 +32,8 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 	mecp5200	MPC5200
 	pf5200		MPC5200
 
+	vme8349		MPC8349
+
 	CPCI750		PPC750FX/GX
 
 Yuli Barcohen <yuli@arabellasw.com>
diff --git a/MAKEALL b/MAKEALL
index 6515669..07349c2 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -364,6 +364,7 @@ LIST_83xx="		\
 	sbc8349		\
 	SIMPC8313_LP	\
 	TQM834x		\
+	vme8349		\
 "
 
 
diff --git a/Makefile b/Makefile
index ef535ed..665f491 100644
--- a/Makefile
+++ b/Makefile
@@ -2387,6 +2387,8 @@ SIMPC8313_SP_config: unconfig
 TQM834x_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
 
+vme8349_config:		unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
 
 #########################################################################
 ## MPC85xx Systems
diff --git a/board/esd/vme8349/Makefile b/board/esd/vme8349/Makefile
new file mode 100644
index 0000000..9f937c8
--- /dev/null
+++ b/board/esd/vme8349/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (c) 2009 esd gmbh hannover germany.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o caddy.o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esd/vme8349/caddy.c b/board/esd/vme8349/caddy.c
new file mode 100644
index 0000000..bda4117
--- /dev/null
+++ b/board/esd/vme8349/caddy.c
@@ -0,0 +1,194 @@
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+
+#include "caddy.h"
+
+static struct caddy_interface *caddy_interface;
+
+void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
+{
+	struct caddy_answer *answer;
+	uint32_t ptr;
+
+	answer = &caddy_interface->answer[caddy_interface->answer_in];
+	memset((void *)answer, 0, sizeof(struct caddy_answer));
+	answer->answer = cmd->cmd;
+	answer->issue = cmd->issue;
+	answer->status = status;
+	memcpy(answer->par, result, 5 * sizeof(result[0]));
+	ptr = caddy_interface->answer_in + 1;
+	ptr = ptr & (ANSWER_SIZE - 1);
+	if (ptr != caddy_interface->answer_out)
+		caddy_interface->answer_in = ptr;
+}
+
+int do_caddy(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned long base_addr;
+	uint32_t ptr;
+	struct caddy_cmd *caddy_cmd;
+	uint32_t result[5];
+	uint16_t data16;
+	uint8_t data8;
+	uint32_t status;
+	pci_dev_t dev;
+	void *pci_ptr;
+
+	if (argc < 2) {
+		puts("Missing parameter\n");
+		return 1;
+	}
+
+	base_addr = simple_strtoul(argv[1], NULL, 16);
+	caddy_interface = (struct caddy_interface *) base_addr;
+
+	memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
+	memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
+
+	while (ctrlc() == 0) {
+		if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
+			memset(result, 0, 5 * sizeof(result[0]));
+			status = 0;
+			caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
+			pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
+				(caddy_cmd->addr & 0x001fffff);
+
+			switch (caddy_cmd->cmd) {
+			case CADDY_CMD_IO_READ_8:
+				result[0] = in_8(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_READ_16:
+				result[0] = in_be16(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_READ_32:
+				result[0] = in_be32(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_WRITE_8:
+				data8 = caddy_cmd->par[0] & 0x000000ff;
+				out_8(pci_ptr, data8);
+				break;
+
+			case CADDY_CMD_IO_WRITE_16:
+				data16 = caddy_cmd->par[0] & 0x0000ffff;
+				out_be16(pci_ptr, data16);
+				break;
+
+			case CADDY_CMD_IO_WRITE_32:
+				out_be32(pci_ptr, caddy_cmd->par[0]);
+				break;
+
+			case CADDY_CMD_CONFIG_READ_8:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_byte(dev,
+							      caddy_cmd->addr,
+							      &data8);
+				result[0] = data8;
+				break;
+
+			case CADDY_CMD_CONFIG_READ_16:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_word(dev,
+							      caddy_cmd->addr,
+							      &data16);
+				result[0] = data16;
+				break;
+
+			case CADDY_CMD_CONFIG_READ_32:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_dword(dev,
+							       caddy_cmd->addr,
+							       &result[0]);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_8:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				data8 = caddy_cmd->par[3] & 0x000000ff;
+				status = pci_write_config_byte(dev,
+							       caddy_cmd->addr,
+							       data8);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_16:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				data16 = caddy_cmd->par[3] & 0x0000ffff;
+				status = pci_write_config_word(dev,
+							       caddy_cmd->addr,
+							       data16);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_32:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_write_config_dword(dev,
+								caddy_cmd->addr,
+								caddy_cmd->par[3]);
+				break;
+
+			default:
+				status = 0xffffffff;
+				break;
+			}
+
+			generate_answer(caddy_cmd, status, &result[0]);
+
+			ptr = caddy_interface->cmd_out + 1;
+			ptr = ptr & (CMD_SIZE - 1);
+			caddy_interface->cmd_out = ptr;
+		}
+
+		caddy_interface->heartbeat++;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	caddy,	2,	0,	do_caddy,
+	"Start Caddy server.",
+	"Start Caddy server with Data structure a given addr\n"
+	);
diff --git a/board/esd/vme8349/caddy.h b/board/esd/vme8349/caddy.h
new file mode 100644
index 0000000..65257ba
--- /dev/null
+++ b/board/esd/vme8349/caddy.h
@@ -0,0 +1,77 @@
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __CADDY_H__
+#define __CADDY_H__
+
+#define CMD_SIZE	1024
+#define ANSWER_SIZE	1024
+#define CADDY_MAGIC	"esd vme8349 V1.0"
+
+enum caddy_cmds {
+	CADDY_CMD_IO_READ_8,
+	CADDY_CMD_IO_READ_16,
+	CADDY_CMD_IO_READ_32,
+	CADDY_CMD_IO_WRITE_8,
+	CADDY_CMD_IO_WRITE_16,
+	CADDY_CMD_IO_WRITE_32,
+	CADDY_CMD_CONFIG_READ_8,
+	CADDY_CMD_CONFIG_READ_16,
+	CADDY_CMD_CONFIG_READ_32,
+	CADDY_CMD_CONFIG_WRITE_8,
+	CADDY_CMD_CONFIG_WRITE_16,
+	CADDY_CMD_CONFIG_WRITE_32,
+};
+
+struct caddy_cmd {
+	uint32_t cmd;
+	uint32_t issue;
+	uint32_t addr;
+	uint32_t par[5];
+};
+
+struct caddy_answer {
+	uint32_t answer;
+	uint32_t issue;
+	uint32_t status;
+	uint32_t par[5];
+};
+
+struct caddy_interface {
+	uint8_t  magic[16];
+	uint32_t cmd_in;
+	uint32_t cmd_out;
+	uint32_t heartbeat;
+	uint32_t reserved1;
+	struct caddy_cmd cmd[CMD_SIZE];
+	uint32_t answer_in;
+	uint32_t answer_out;
+	uint32_t reserved2;
+	uint32_t reserved3;
+	struct caddy_answer answer[CMD_SIZE];
+};
+
+#endif /* of __CADDY_H__ */
diff --git a/board/esd/vme8349/config.mk b/board/esd/vme8349/config.mk
new file mode 100644
index 0000000..1ae26ca
--- /dev/null
+++ b/board/esd/vme8349/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# VME8349E
+#
+
+TEXT_BASE  =   0xFFF00000
diff --git a/board/esd/vme8349/pci.c b/board/esd/vme8349/pci.c
new file mode 100644
index 0000000..d15203c
--- /dev/null
+++ b/board/esd/vme8349/pci.c
@@ -0,0 +1,119 @@
+/*
+ * pci.c -- esd VME8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci1_regions };
+	u8 reg8;
+	int monarch = 0;
+
+	i2c_set_bus_num(1);
+	/* Read the PCI_M66EN jumper setting */
+	if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, 1) == 0) ||
+	    (i2c_read(0x38                     , 0, 0, &reg8, 1) == 0)) {
+		if (reg8 & 0x40) {
+			clk->occr = 0xff000000;	/* 66 MHz PCI */
+			printf("PCI:   66MHz\n");
+		} else {
+			clk->occr = 0xffff0003;	/* 33 MHz PCI */
+			printf("PCI:   33MHz\n");
+		}
+		if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
+			monarch = 1;
+	} else {
+		clk->occr = 0xffff0003;	/* 33 MHz PCI */
+		printf("PCI:   33MHz (I2C read failed)\n");
+	}
+	udelay(2000);
+
+	/*
+	 * Assert/deassert PCI reset
+	 */
+	setbits_be32(&immr->gpio[0].dat, 0x00800000);
+	setbits_be32(&immr->gpio[0].dir, 0x00800000);
+	setbits_be32(&immr->gpio[1].dir, 0x08800000);
+	udelay(200);
+	setbits_be32(&immr->gpio[1].dat, 0x08000000);
+	udelay(200);
+	setbits_be32(&immr->gpio[1].dat, 0x08800000);
+	udelay(600000);
+	clrbits_be32(&immr->gpio[1].dat, 0x00100000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	udelay(2000);
+
+	if (monarch == 0)
+		mpc83xx_pci_init(1, reg, 0);
+}
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
new file mode 100644
index 0000000..e3bc151
--- /dev/null
+++ b/board/esd/vme8349/vme8349.c
@@ -0,0 +1,140 @@
+/*
+ * vme8349.c -- esd VME8349 board support
+ *
+ * Copyright (c) 2008-2009 esd gmbh.
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <asm/io.h>
+#include <asm/mmu.h>
+
+void ddr_enable_ecc(unsigned int dram_size);
+
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1);
+	     ddr_size = ddr_size>>1, ddr_size_log2++) {
+		if (ddr_size & 1)
+			return -1;
+	}
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar  = LAWAR_EN | ((ddr_size_log2 - 1) &
+						LAWAR_SIZE);
+
+#if (CONFIG_SYS_DDR_SIZE == 512)
+	im->ddr.csbnds[0].csbnds = 0x0000001f;
+#else
+#warning Currently any DDR size other than 512MiB is not supported
+#endif
+	im->ddr.cs_config[0]     = CONFIG_SYS_DDR_CONFIG | 0x00330000;
+
+	/* currently we use only one CS, so disable the other banks */
+	im->ddr.csbnds[1].csbnds = 0x00000000;
+	im->ddr.csbnds[2].csbnds = 0x00000000;
+	im->ddr.csbnds[3].csbnds = 0x00000000;
+	im->ddr.cs_config[1] = 0;
+	im->ddr.cs_config[2] = 0;
+	im->ddr.cs_config[3] = 0;
+
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	sync();
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+
+	msize = fixed_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+	/* Now check memory size (after ECC is initialized) */
+	msize = get_ram_size(0, msize);
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	puts("Board: esd VME8349\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 35c82b9..82e4eed 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -403,7 +403,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 		       PCI_DEV(dev));
 		break;
 #endif
-#ifdef CONFIG_MPC834x
+#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
 	case PCI_CLASS_BRIDGE_OTHER:
 		/*
 		 * The host/PCI bridge 1 seems broken in 8349 - it presents
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
new file mode 100644
index 0000000..1477552
--- /dev/null
+++ b/include/configs/vme8349.h
@@ -0,0 +1,608 @@
+/*
+ * esd vme8349 U-Boot configuration file
+ * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * reinhard.arlt@esd-electronics.de
+ * Based on the MPC8349EMDS config.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * vme8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC83xx		1	/* MPC83xx family */
+#define CONFIG_MPC834x		1	/* MPC834x family */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
+#define CONFIG_VME8349		1	/* ESD VME8349 board specific */
+
+#define CONFIG_PCI
+/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ	66000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
+#else
+#define CONFIG_SYS_CLK_FREQ	33000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
+#endif
+#endif
+
+#define CONFIG_SYS_IMMR		0xE0000000
+
+#undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#undef CONFIG_SPD_EEPROM		/* dont use SPD EEPROM for DDR setup*/
+#define CONFIG_SYS_83XX_DDR_USES_CS0	/* esd; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is sys memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+					 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE		512	/* MB */
+
+#if (CONFIG_SYS_DDR_SIZE == 512)
+#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10 | \
+					 CSCONFIG_BANK_BIT_3)
+#endif
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_TIMING_0	        0x00220802
+#define CONFIG_SYS_DDR_TIMING_1	        0x39377322
+#define CONFIG_SYS_DDR_TIMING_2	        0x2f9848ca	/* P9-45, tuning? */
+#define CONFIG_SYS_DDR_TIMING_3	        0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuf,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE		0x07940242
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+/* autocharge,no open page */
+#define CONFIG_SYS_DDR_INTERVAL	        0x04060100
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x63000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x04061000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER			        /* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE           128		/* flash size in MB */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
+					 (2 << BR_PS_SHIFT) |	/*  32bit */ \
+					 BR_V)			/* valid */
+
+#define CONFIG_SYS_OR0_PRELIM		0xF8006FF7	/* 128 MB flash size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001A	/* 128 MB window size */
+
+#define CONFIG_SYS_BR1_PRELIM		(0xf0000000 | 0x00001801)
+#define CONFIG_SYS_OR1_PRELIM		(0xffff8000 | 0x00000200)
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	0xf0000000
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(0x80000000 | 0x0000000e)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device*/
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase TO (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write TO (ms) */
+
+#define CONFIG_SYS_MID_FLASH_JUMP	0x7F000000
+#define CONFIG_SYS_MONITOR_BASE	        TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xF7000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_END		0x1000		/* size */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* size init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Malloc size */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR + 0x4600)
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0, 0x69}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C1_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_OFFSET	CONFIG_SYS_I2C1_OFFSET
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
+
+#define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_64BIT
+#define PCI_ONE_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#define CONFIG_NET_MULTI
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0xFIXME
+#endif
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_GMII		       /* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_PHY_M88E1111
+#define TSEC1_PHY_ADDR		0x08
+#define TSEC2_PHY_ADDR		0x10
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_IS_IN_FLASH
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0xc0000)
+	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else
+	#define CONFIG_SYS_NO_FLASH		/* Flash is not usable now */
+	#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_SYS_RTC_BUS_NUM  0x01
+#define CONFIG_SYS_I2C_RTC_ADDR	0x32
+#define CONFIG_RTC_RX8025
+#define CONFIG_CMD_TSI148
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_ENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMD_ELF
+/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x000043f0
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max num of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
+#define CONFIG_SYS_HZ		1000		/* decr freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Init Memory map for Linux*/
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#endif
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+
+#define CONFIG_SYS_HID2		HID2_HBE
+
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR	0x00100000
+#define CONFIG_SYS_GPIO1_DAT	0x00100000
+
+#define CONFIG_SYS_GPIO2_PRELIM
+#define CONFIG_SYS_GPIO2_DIR	0x78900000
+#define CONFIG_SYS_GPIO2_DAT	0x70100000
+
+#define CONFIG_HIGH_BATS		/* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT1L	(0)
+#define CONFIG_SYS_IBAT1U	(0)
+#define CONFIG_SYS_IBAT2L	(0)
+#define CONFIG_SYS_IBAT2U	(0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#if (CONFIG_SYS_DDR_SIZE == 512)
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_SDRAM_BASE+0x10000000 | \
+				 BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_SDRAM_BASE+0x10000000 | \
+				 BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#endif
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME		VME8349
+#define CONFIG_ROOTPATH		/tftpboot/rootfs
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_LOADADDR		500000	/* def location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	 115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=vme8349\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"		\
+	"update=protect off fff00000 fff3ffff; "			\
+		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+	"upd=run load update\0"						\
+	"fdtaddr=400000\0"						\
+	"fdtfile=vme8349.dtb\0"						\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* __CONFIG_H */
-- 
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