From bac6a1d1fa1cd80aa57881fa9c2152b853cd0ed4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 7 Oct 2008 10:28:46 -0500 Subject: 85xx: Remove setting of *cache-line-size in device trees ePAPR says if the *cache-block-size is the same as *cache-line-size than we don't need the *cache-line-size property. Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index bc1550d..037a60f 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -152,7 +152,6 @@ static inline void ft_fixup_l2cache(void *blob) } fdt_setprop(blob, off, "cache-unified", NULL, 0); fdt_setprop_cell(blob, off, "cache-block-size", line_size); - fdt_setprop_cell(blob, off, "cache-line-size", line_size); fdt_setprop_cell(blob, off, "cache-size", size); fdt_setprop_cell(blob, off, "cache-sets", num_sets); fdt_setprop_cell(blob, off, "cache-level", 2); @@ -181,7 +180,6 @@ static inline void ft_fixup_cache(void *blob) dnum_sets = dsize / (dline_size * dnum_ways); fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); - fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size); fdt_setprop_cell(blob, off, "d-cache-size", dsize); fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); @@ -192,7 +190,6 @@ static inline void ft_fixup_cache(void *blob) inum_sets = isize / (iline_size * inum_ways); fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); - fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size); fdt_setprop_cell(blob, off, "i-cache-size", isize); fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); -- cgit v0.10.2 From c0391111c33c22fabeddf8f4ca801ec7645b4f5c Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Sat, 27 Sep 2008 14:40:57 +0800 Subject: Fix the incorrect DDR clk freq reporting on 8536DS On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 67e81c0..f15b0a8 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -85,7 +85,8 @@ int checkcpu (void) struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 1cda1e3..485ba20 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_DDR_CLK_FREQ { - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; if (ddr_ratio != 0x7) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 559d6ea..50c9dde 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1552,6 +1552,13 @@ typedef struct par_io { */ typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ +#ifdef CONFIG_MPC8536 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 +#else +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 +#endif uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 2578bef..0d65b20 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -59,7 +59,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ -/* #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /\* ddrclk for MPC85xx *\/ FIXME-8536*/ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq from ICS307 instead of switches */ -- cgit v0.10.2 From 1f3ba317a5c5f3a7aabf580fddc211f4bb5a4540 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 3 Oct 2008 11:46:59 -0400 Subject: Minor fixes for I2C address on MPC8572DS MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1 according to the board spec, and adds the 2nd i2c bus offset. Signed-off-by: Haiying Wang diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index d7e3a88..87b1011 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -108,6 +108,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ +#define CFG_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ @@ -293,11 +294,14 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3100 +#define CFG_I2C_NOPROBES {0,0x29} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 /* * General PCI -- cgit v0.10.2 From 445a7b38308eb05b41de74165b20855db58c7ee5 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 3 Oct 2008 11:47:30 -0400 Subject: Add ID EEPROM support for MPC8572DS The ID EEPROM on MPC8572DS board locates on I2C bus 1. Its the storage for system information like mac addresses etc. This patch enables it. Signed-off-by: Haiying Wang diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 87b1011..fbe7b61 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -304,6 +304,17 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CFG_I2C2_OFFSET 0x3100 /* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CFG_I2C_EEPROM_NXID +#endif +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_BUS_NUM 1 + +/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -- cgit v0.10.2 From 5297246bbaa9943c0da1ec2e717b72e4ab6b830e Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 3 Oct 2008 11:48:03 -0400 Subject: Remove redundant #define for MPC8536DS Signed-off-by: Haiying Wang diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 0d65b20..b504add 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -303,7 +303,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_ID_EEPROM #ifdef CONFIG_ID_EEPROM -#define CONFIG_ID_EEPROM #define CFG_I2C_EEPROM_NXID #endif #define CFG_I2C_EEPROM_ADDR 0x57 -- cgit v0.10.2 From e46c7bfb8bc3c304cedd20f7a365d6e78d7eaf17 Mon Sep 17 00:00:00 2001 From: Rafal Czubak Date: Wed, 8 Oct 2008 13:41:30 +0200 Subject: FSL: Fix get_cpu_board_revision() return value. get_cpu_board_revision() returned board revision based on information stored in global static struct eeprom. It should instead use one from local struct board_eeprom, to which the data is actually read from EEPROM. The bug led to system hang after printing L1 cache information on U-Boot startup. The problem was observed on MPC8555CDS system and possibly affects other Freescale MPC85xx boards using CFG_I2C_EEPROM_CCID. The change has been successfully tested on MPC8555CDS system. Signed-off-by: Rafal Czubak diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index e53ead0..9bef92e 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -463,6 +463,6 @@ unsigned int get_cpu_board_revision(void) if ((be.major == 0xff) && (be.minor == 0xff)) return MPC85XX_CPU_BOARD_REV(0, 0); - return MPC85XX_CPU_BOARD_REV(e.major, e.minor); + return MPC85XX_CPU_BOARD_REV(be.major, be.minor); } #endif -- cgit v0.10.2 From dffd2446fb041f38ef034b0fcf41e51e5e489159 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Tue, 30 Sep 2008 10:55:57 +0200 Subject: 85xx: Using proper I2C source clock divider for MPC8544 Measurements with our MPC8544 board showed that the I2C bus frequency is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM. Signed-off-by: Wolfgang Grandegger diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 485ba20..70dfad0 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -102,9 +102,9 @@ int get_clocks (void) * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->i2c1_clk = sys_info.freqSystemBus / 3; - else gd->i2c1_clk = sys_info.freqSystemBus / 2; + else + gd->i2c1_clk = sys_info.freqSystemBus / 3; #else /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ gd->i2c1_clk = sys_info.freqSystemBus / 2; -- cgit v0.10.2 From f3bf9273939ffe1a60a32a2eef909097f15df56b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 8 Oct 2008 15:36:39 -0500 Subject: MPC8572DS: Fix compile warnings Commit 445a7b38308eb05b41de74165b20855db58c7ee5 introduced the following compile warnings: cmd_i2c.c:112: warning: missing braces around initializer cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]') Signed-off-by: Kumar Gala diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index fbe7b61..4114a42 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -299,7 +299,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0,0x29} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 -- cgit v0.10.2