From 6f8c351e98726ec9b569bf16f7efa2a4e4648727 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Mon, 27 Mar 2017 12:54:19 -0700 Subject: serial: ns16550: Link in the DM driver when when using platdata Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA. This is inconsistent with the majority of other drivers. This also blocks OF_PLATDATA boards with an 16550-compatible serial from using serial in SPL. Signed-off-by: Alexandru Gagniuc Reviewed-by: Simon Glass Added tweak for rock to avoid a TPL build failure: Signed-off-by: Simon Glass diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 20a065a..b61286e 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -40,6 +40,7 @@ CONFIG_PMIC_ACT8846=y CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y +# CONFIG_TPL_DM_SERIAL is not set CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0x20064000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 1f819d4..4f86780 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -452,8 +452,7 @@ const struct dm_serial_ops ns16550_serial_ops = { .setbrg = ns16550_serial_setbrg, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) /* * Please consider existing compatible strings before adding a new * one to keep this table compact. Or you may add a generic "ns16550" @@ -473,13 +472,16 @@ static const struct udevice_id ns16550_serial_ids[] = { { .compatible = "ti,dra742-uart", .data = PORT_NS16550 }, {} }; -#endif +#endif /* OF_CONTROL && !OF_PLATDATA */ #if CONFIG_IS_ENABLED(SERIAL_PRESENT) + +/* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */ +#if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL) U_BOOT_DRIVER(ns16550_serial) = { .name = "ns16550_serial", .id = UCLASS_SERIAL, -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .of_match = ns16550_serial_ids, .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), @@ -490,5 +492,6 @@ U_BOOT_DRIVER(ns16550_serial) = { .flags = DM_FLAG_PRE_RELOC, }; #endif -#endif /* !OF_PLATDATA */ +#endif /* SERIAL_PRESENT */ + #endif /* CONFIG_DM_SERIAL */ -- cgit v0.10.2 From 6db06f94e19d539bb7001a666e7c52672e0682ea Mon Sep 17 00:00:00 2001 From: George McCollister Date: Thu, 30 Mar 2017 09:44:24 -0500 Subject: patman: Convert byte arrays to strings os.read() returns a byte array in Python 3.5.2 and needs to be converted into a string. Check if the returned value is an instance of bytes and if it is decode it as a utf-8 string. If it is not a utf-8 encoded string the decoding may fail with an exception. Prior to this fix the comparisions check data == "" would fail when data was b'' and would cause an infinite memory leaking loop. joins would also fail with an exception below but due to the infinite loop it never made it that far. Signed-off-by: George McCollister Acked-by: Simon Glass diff --git a/tools/patman/cros_subprocess.py b/tools/patman/cros_subprocess.py index ebd4300..7c76014 100644 --- a/tools/patman/cros_subprocess.py +++ b/tools/patman/cros_subprocess.py @@ -190,6 +190,8 @@ class Popen(subprocess.Popen): # We will get an error on read if the pty is closed try: data = os.read(self.stdout.fileno(), 1024) + if isinstance(data, bytes): + data = data.decode('utf-8') except OSError: pass if data == "": @@ -205,6 +207,8 @@ class Popen(subprocess.Popen): # We will get an error on read if the pty is closed try: data = os.read(self.stderr.fileno(), 1024) + if isinstance(data, bytes): + data = data.decode('utf-8') except OSError: pass if data == "": -- cgit v0.10.2 From f156b5b59750f4140ffa2dd6a5eab686ba0212c3 Mon Sep 17 00:00:00 2001 From: George McCollister Date: Thu, 30 Mar 2017 09:44:25 -0500 Subject: dtoc: Decode val if it's a byte string With Python 3.5.2 encode will throw an exception if val is a byte array. Decode it to a string first. This assumes it's utf-8, if it's not valid utf-8 it will throw an exception. Signed-off-by: George McCollister Acked-by: Simon Glass diff --git a/tools/dtoc/fdt_util.py b/tools/dtoc/fdt_util.py index e6d523b..b9dfae8 100644 --- a/tools/dtoc/fdt_util.py +++ b/tools/dtoc/fdt_util.py @@ -24,6 +24,8 @@ def fdt32_to_cpu(val): A native-endian integer value """ if sys.version_info > (3, 0): + if isinstance(val, bytes): + val = val.decode('utf-8') val = val.encode('raw_unicode_escape') return struct.unpack('>I', val)[0] -- cgit v0.10.2 From c47a38b47770887dc9416382207364fb62899fc2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 2 Apr 2017 12:26:44 -0600 Subject: fdtgrep: Cope with the /aliases node being last With skeleton.dtsi being dropped it is more likely that the /aliases node will be last in the device tree. Update fdtgrep to handle this. Signed-off-by: Simon Glass Tested-by: Masahiro Yamada diff --git a/lib/libfdt/fdt_region.c b/lib/libfdt/fdt_region.c index d2ce4c1..8b8a547 100644 --- a/lib/libfdt/fdt_region.c +++ b/lib/libfdt/fdt_region.c @@ -63,6 +63,30 @@ static int region_list_contains_offset(struct fdt_region_state *info, return 0; } +/** + * fdt_add_alias_regions() - Add regions covering the aliases that we want + * + * The /aliases node is not automatically included by fdtgrep unless the + * command-line arguments cause to be included (or not excluded). However + * aliases are special in that we generally want to include those which + * reference a node that fdtgrep includes. + * + * In fact we want to include only aliases for those nodes still included in + * the fdt, and drop the other aliases since they point to nodes that will not + * be present. + * + * This function scans the aliases and adds regions for those which we want + * to keep. + * + * @fdt: Device tree to scan + * @region: List of regions + * @count: Number of regions in the list so far (i.e. starting point for this + * function) + * @max_regions: Maximum number of regions in @region list + * @info: Place to put the region state + * @return number of regions after processing, or -FDT_ERR_NOSPACE if we did + * not have enough room in the regions table for the regions we wanted to add. + */ int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count, int max_regions, struct fdt_region_state *info) { @@ -74,11 +98,17 @@ int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count, if (node < 0) return -FDT_ERR_NOTFOUND; - /* The aliases node must come before the others */ + /* + * Find the next node so that we know where the /aliases node ends. We + * need special handling if /aliases is the last node. + */ node_end = fdt_next_subnode(fdt, node); - if (node_end <= 0) - return -FDT_ERR_BADLAYOUT; - node_end -= sizeof(fdt32_t); + if (node_end == -FDT_ERR_NOTFOUND) + /* Move back to the FDT_END_NODE tag of '/' */ + node_end = fdt_size_dt_struct(fdt) - sizeof(fdt32_t) * 2; + else if (node_end < 0) /* other error */ + return node_end; + node_end -= sizeof(fdt32_t); /* Move to FDT_END_NODE tag of /aliases */ did_alias_header = 0; info->region = region; @@ -109,7 +139,7 @@ int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count, fdt_add_region(info, base + offset, next - offset); } - /* Add the 'end' tag */ + /* Add the FDT_END_NODE tag */ if (did_alias_header) fdt_add_region(info, base + node_end, sizeof(fdt32_t)); diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index b907827..e373c43 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -810,9 +810,6 @@ static int do_fdtgrep(struct display_info *disp, const char *filename) disp->flags); if (count < 0) { report_error("fdt_find_regions", count); - if (count == -FDT_ERR_BADLAYOUT) - fprintf(stderr, - "/aliases node must come before all other nodes\n"); return -1; } if (count <= max_regions) -- cgit v0.10.2 From ea168e3351cdb9a738ebfa4ad931a81b2f6d48dd Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Tue, 4 Apr 2017 10:46:56 -0700 Subject: core/uclass: Print name of device in uclass_find_device_by_seq() uclass_find_device_by_seq() prints seq and req_seq when debugging is enabled, but this information is not very useful by itself. Add the name of he driver to this information. This improves debugging as it shows which devices are being considered. Signed-off-by: Alexandru Gagniuc Acked-by: Simon Glass diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index d94d43a..04fb45b 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -250,7 +250,7 @@ int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq, return ret; list_for_each_entry(dev, &uc->dev_head, uclass_node) { - debug(" - %d %d\n", dev->req_seq, dev->seq); + debug(" - %d %d '%s'\n", dev->req_seq, dev->seq, dev->name); if ((find_req_seq ? dev->req_seq : dev->seq) == seq_or_req_seq) { *devp = dev; -- cgit v0.10.2 From 5a8a8045a928702d9b3fb6f73a4e9717040e09a9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 4 Apr 2017 13:00:19 -0600 Subject: dm: core: Ensure DMA regions start up with the cache clean There is a strange interaction with drivers which use DMA if the cache starts off in a dirty state. Buffer space which the driver reads (but has not previously written) can contain zero bytes from alloc_priv(). This can cause corruption of the memory used by DMA for incoming data. Fix this and add a comment to explain the problem. This allows the dwc2 driver to work correctly with driver model, for example. Signed-off-by: Simon Glass diff --git a/drivers/core/device.c b/drivers/core/device.c index e1b0ebf..09a115f 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -255,8 +255,36 @@ static void *alloc_priv(int size, uint flags) if (flags & DM_FLAG_ALLOC_PRIV_DMA) { priv = memalign(ARCH_DMA_MINALIGN, size); - if (priv) + if (priv) { memset(priv, '\0', size); + + /* + * Ensure that the zero bytes are flushed to memory. + * This prevents problems if the driver uses this as + * both an input and an output buffer: + * + * 1. Zeroes written to buffer (here) and sit in the + * cache + * 2. Driver issues a read command to DMA + * 3. CPU runs out of cache space and evicts some cache + * data in the buffer, writing zeroes to RAM from + * the memset() above + * 4. DMA completes + * 5. Buffer now has some DMA data and some zeroes + * 6. Data being read is now incorrect + * + * To prevent this, ensure that the cache is clean + * within this range at the start. The driver can then + * use normal flush-after-write, invalidate-before-read + * procedures. + * + * TODO(sjg@chromium.org): Drop this microblaze + * exception. + */ +#ifndef CONFIG_MICROBLAZE + flush_dcache_range((ulong)priv, (ulong)priv + size); +#endif + } } else { priv = calloc(1, size); } -- cgit v0.10.2 From b48bfc74ee410b1e6681c620633ffef32aafaba0 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 5 Apr 2017 17:46:41 +0200 Subject: tools: allow to override python Not force to use python from PATH. Issue was noted when building with Yocto, because python from the distro is always taken instead of python-native built during Yocto process. Signed-off-by: Stefano Babic CC: Simon Glass Reviewed-by: Simon Glass diff --git a/Makefile b/Makefile index 09b597d..8d4e605 100644 --- a/Makefile +++ b/Makefile @@ -348,7 +348,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy OBJDUMP = $(CROSS_COMPILE)objdump AWK = awk PERL = perl -PYTHON = python +PYTHON ?= python DTC = dtc CHECK = sparse diff --git a/tools/Makefile b/tools/Makefile index fa1b85b..2fc4a58 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -120,7 +120,7 @@ _libfdt.so-sharedobjs += $(LIBFDT_OBJS) libfdt: tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c - LDFLAGS="$(HOSTLDFLAGS)" CFLAGS= python $(srctree)/lib/libfdt/setup.py \ + LDFLAGS="$(HOSTLDFLAGS)" CFLAGS= ${PYTHON} $(srctree)/lib/libfdt/setup.py \ "$(_hostc_flags)" $^ mv _libfdt.so $@ -- cgit v0.10.2 From 9a6d2e2a6b0561732e52bd98e71432a7f4e9b3e2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 12 Apr 2017 18:23:26 -0600 Subject: buildman: Handle commit subjects containing unicode One of these has crept in in this commit: 40a808f1 ARCv2: SLC: Make sure busy bit is set properly on SLC flushing Adjust buildman to handle it. Signed-off-by: Simon Glass diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index 236e061..b0ea57e 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -95,8 +95,9 @@ u-boot/ source directory # Possible build outcomes OUTCOME_OK, OUTCOME_WARNING, OUTCOME_ERROR, OUTCOME_UNKNOWN = range(4) -# Translate a commit subject into a valid filename -trans_valid_chars = string.maketrans("/: ", "---") +# Translate a commit subject into a valid filename (and handle unicode) +trans_valid_chars = string.maketrans('/: ', '---') +trans_valid_chars = trans_valid_chars.decode('latin-1') BASE_CONFIG_FILENAMES = [ 'u-boot.cfg', 'u-boot-spl.cfg', 'u-boot-tpl.cfg' -- cgit v0.10.2 From 8c4e4101d68ca075bba641c88a398ee8ed81b07f Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 12:55:20 +0800 Subject: ARM: at91: gpio: fix at91_set_gpio_value() define When the CONFIG_ATMEL_LEGACY is undefined, according to the following defines, at91_set_gpio_value() references to at91_set_pio_value(x, y) with two parameters. #define at91_set_gpio_value(x, y) at91_set_pio_value(x, y) #define at91_get_gpio_value(x) at91_get_pio_value(x) But there isn't the implementation of at91_set_pio_value(x, y) with two parameters in U-Boot. This is an error. Same as at91_get_gpio_value(x) define. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 5a32bdb..df0f719 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -223,15 +223,13 @@ static inline unsigned pin_to_mask(unsigned pin) at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_gpio_input(x, y) \ at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_gpio_value(x, y) \ - at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y) -#define at91_get_gpio_value(x) \ - at91_get_pio_value((x - PIN_BASE) / 32,(x % 32)) -#else -#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y) -#define at91_get_gpio_value(x) at91_get_pio_value(x) #endif +#define at91_set_gpio_value(x, y) \ + at91_set_pio_value((x / 32), (x % 32), y) +#define at91_get_gpio_value(x) \ + at91_get_pio_value((x / 32), (x % 32)) + #define GPIO_PIOA_BASE (0) #define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) #define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) -- cgit v0.10.2 From 0de077df38a6a1120acf7833572d1ffc8f209f33 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 12:55:21 +0800 Subject: mtd: nand: atmel: use another functions to set gpio value Because there isn't the implementation of gpio_set/get_value() and gpio_set/get_value() after the at91 gpio driver is converted to support the driver model, use at91_set_gpio_value() and at91_get_gpio_value() Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 8669432..21d5d0e 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1222,7 +1222,8 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE; #ifdef CONFIG_SYS_NAND_ENABLE_PIN - gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE)); + at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN, + !(ctrl & NAND_NCE)); #endif this->IO_ADDR_W = (void *) IO_ADDR_W; } @@ -1234,7 +1235,7 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, #ifdef CONFIG_SYS_NAND_READY_PIN static int at91_nand_ready(struct mtd_info *mtd) { - return gpio_get_value(CONFIG_SYS_NAND_READY_PIN); + return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN); } #endif -- cgit v0.10.2 From 2dc63f73678c18831efce3ec1a383375aa5423f1 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 12:44:36 +0800 Subject: gpio: at91_gpio: remove CPU_HAS_PIO3 macro The intention of the removal is the preparation to introduce the new AT91 PIO pinctrl driver. Use the union to make the PIO3 and PIO2's registers be together and make their offset aligned. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c index a03abfc..28c8cf2 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c @@ -18,45 +18,45 @@ unsigned int has_lcdc() void at91_serial0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */ at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */ at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */ at91_periph_clk_enable(ATMEL_ID_USART2); } void at91_serial3_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */ - at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */ at91_periph_clk_enable(ATMEL_ID_USART3); } void at91_seriald_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ at91_periph_clk_enable(ATMEL_ID_SYS); } #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ at91_periph_clk_enable(ATMEL_ID_SPI0); @@ -72,9 +72,9 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ - at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ - at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ at91_periph_clk_enable(ATMEL_ID_SPI1); @@ -91,12 +91,12 @@ void at91_spi1_hw_init(unsigned long cs_mask) void at91_mci_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */ - at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */ at91_periph_clk_enable(ATMEL_ID_HSMCI0); } @@ -104,37 +104,37 @@ void at91_mci_hw_init(void) #ifdef CONFIG_LCD void at91_lcd_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */ - at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ - at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */ - - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ - at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */ + + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ at91_periph_clk_enable(ATMEL_ID_LCDC); } diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c index 3e4555a..8de086e 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c @@ -64,32 +64,32 @@ char *get_cpu_name() void at91_seriald_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ at91_periph_clk_enable(ATMEL_ID_SYS); } void at91_serial0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */ at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */ at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */ at91_periph_clk_enable(ATMEL_ID_USART2); } @@ -97,12 +97,12 @@ void at91_serial2_hw_init(void) void at91_mci_hw_init(void) { /* Initialize the MCI0 */ - at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */ - at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */ at91_periph_clk_enable(ATMEL_ID_HSMCI0); } @@ -110,20 +110,20 @@ void at91_mci_hw_init(void) #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ at91_periph_clk_enable(ATMEL_ID_SPI0); if (cs_mask & (1 << 0)) - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); if (cs_mask & (1 << 1)) - at91_set_b_periph(AT91_PIO_PORTA, 7, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 7, 0); if (cs_mask & (1 << 2)) - at91_set_b_periph(AT91_PIO_PORTA, 1, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 1, 0); if (cs_mask & (1 << 3)) - at91_set_b_periph(AT91_PIO_PORTB, 3, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTB, 3, 0); if (cs_mask & (1 << 4)) at91_set_pio_output(AT91_PIO_PORTA, 14, 0); if (cs_mask & (1 << 5)) @@ -136,20 +136,20 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ - at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ - at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ at91_periph_clk_enable(ATMEL_ID_SPI1); if (cs_mask & (1 << 0)) - at91_set_b_periph(AT91_PIO_PORTA, 8, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 8, 0); if (cs_mask & (1 << 1)) - at91_set_b_periph(AT91_PIO_PORTA, 0, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 0, 0); if (cs_mask & (1 << 2)) - at91_set_b_periph(AT91_PIO_PORTA, 31, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 31, 0); if (cs_mask & (1 << 3)) - at91_set_b_periph(AT91_PIO_PORTA, 30, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 30, 0); if (cs_mask & (1 << 4)) at91_set_pio_output(AT91_PIO_PORTA, 8, 0); if (cs_mask & (1 << 5)) @@ -181,45 +181,45 @@ void at91_macb_hw_init(void) /* Enable EMAC0 clock */ at91_periph_clk_enable(ATMEL_ID_EMAC0); /* EMAC0 pins setup */ - at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ } if (has_emac1()) { /* Enable EMAC1 clock */ at91_periph_clk_enable(ATMEL_ID_EMAC1); /* EMAC1 pins setup */ - at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ - at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ - at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ - at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ - at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ - at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ - at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ - at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ - at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ - at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ } #ifndef CONFIG_RMII /* Only emac0 support MII */ if (has_emac0()) { - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ } #endif } diff --git a/arch/arm/mach-at91/armv7/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c index 64ac262..6becdd7 100644 --- a/arch/arm/mach-at91/armv7/sama5d3_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c @@ -52,8 +52,8 @@ char *get_cpu_name() void at91_serial0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_USART0); @@ -61,8 +61,8 @@ void at91_serial0_hw_init(void) void at91_serial1_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_USART1); @@ -70,8 +70,8 @@ void at91_serial1_hw_init(void) void at91_serial2_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */ - at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_USART2); @@ -79,8 +79,8 @@ void at91_serial2_hw_init(void) void at91_seriald_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */ - at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_DBGU); @@ -89,9 +89,9 @@ void at91_seriald_hw_init(void) #if defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */ if (cs_mask & (1 << 0)) at91_set_pio_output(AT91_PIO_PORTD, 13, 1); @@ -110,18 +110,18 @@ void at91_spi0_hw_init(unsigned long cs_mask) #ifdef CONFIG_GENERIC_ATMEL_MCI void at91_mci_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */ - at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */ - at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */ - at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */ - at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */ #ifdef CONFIG_ATMEL_MCI_8BIT - at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */ - at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */ - at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */ - at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */ #endif - at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_MCI0); @@ -131,16 +131,16 @@ void at91_mci_hw_init(void) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_EMAC); @@ -148,23 +148,23 @@ void at91_macb_hw_init(void) void at91_gmac_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */ - - at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */ - - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */ + + at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */ + + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_GMAC); @@ -174,30 +174,30 @@ void at91_gmac_hw_init(void) #ifdef CONFIG_LCD void at91_lcd_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ /* The lower 16-bit of LCD only available on Port A */ - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_LCDC); diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h index 3012278..946f076 100644 --- a/arch/arm/mach-at91/include/mach/at91_pio.h +++ b/arch/arm/mach-at91/include/mach/at91_pio.h @@ -32,6 +32,8 @@ #define AT91_ASM_PIOD_ASR \ (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) +#define PIO_SCDR_DIV 0x3fff /* Slow Clock Divider Selection for Debouncing Mask */ + #ifndef __ASSEMBLY__ typedef struct at91_port { @@ -63,28 +65,32 @@ typedef struct at91_port { u32 puer; /* 0x64 Pull-up Enable Register */ u32 pusr; /* 0x68 Pad Pull-up Status Register */ u32 reserved4; -#if defined(CPU_HAS_PIO3) - u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ - u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ - u32 reserved5[2]; - u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ - u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ - u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ - u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ - u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ - u32 ppder; /* 0x94 Pad Pull-down Enable Register */ - u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ - u32 reserved6; /* */ -#else - u32 asr; /* 0x70 Select A Register */ - u32 bsr; /* 0x74 Select B Register */ - u32 absr; /* 0x78 AB Select Status Register */ - u32 reserved5[9]; /* */ -#endif + union { + struct { + u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ + u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ + u32 reserved5[2]; + u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ + u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ + u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ + u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ + u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ + u32 ppder; /* 0x94 Pad Pull-down Enable Register */ + u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ + u32 reserved6; /* */ + } pio3; + + struct { + u32 asr; /* 0x70 Select A Register */ + u32 bsr; /* 0x74 Select B Register */ + u32 absr; /* 0x78 AB Select Status Register */ + u32 reserved5[9]; /* */ + } pio2; + } mux; + u32 ower; /* 0xA0 Output Write Enable Register */ u32 owdr; /* 0xA4 Output Write Disable Register */ u32 owsr; /* OxA8 Output Write Status Register */ -#if defined(CPU_HAS_PIO3) u32 reserved7; /* */ u32 aimer; /* 0xB0 Additional INT Modes Enable Register */ u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */ @@ -104,9 +110,6 @@ typedef struct at91_port { u32 reserved11[5]; /* */ u32 schmitt; /* 0x100 Schmitt Trigger Register */ u32 reserved12[63]; -#else - u32 reserved6[85]; -#endif } at91_port_t; typedef union at91_pio { @@ -123,13 +126,6 @@ typedef union at91_pio { #ifdef CONFIG_AT91_GPIO int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); -#if defined(CPU_HAS_PIO3) -int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); -int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); -int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); -#endif int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); int at91_set_pio_output(unsigned port, unsigned pin, int value); @@ -138,6 +134,15 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on); int at91_set_pio_value(unsigned port, unsigned pin, int value); int at91_get_pio_value(unsigned port, unsigned pin); + +int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup); +int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup); +int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup); +int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup); +int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); +int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); +int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on); +int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); #endif #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 8100ebe..e7224e4 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -171,8 +171,6 @@ * Other misc defines */ #define ATMEL_PIO_PORTS 4 -#define CPU_HAS_PIO3 -#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP #define ATMEL_ID_UHP ATMEL_ID_UHPHS diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 33f6c97..d558f95 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -188,8 +188,6 @@ * Other misc defines */ #define ATMEL_PIO_PORTS 5 -#define CPU_HAS_PIO3 -#define PIO_SCDR_DIV 0x3fff #define CPU_HAS_PCR /* Timer */ diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index 90085da..78cc2a7 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -174,8 +174,6 @@ * Other misc defines */ #define ATMEL_PIO_PORTS 5 -#define CPU_HAS_PIO3 -#define PIO_SCDR_DIV 0x3fff #define CPU_HAS_PCR #define CPU_HAS_H32MXDIV diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index fc4f50d..58da2d2 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -71,10 +71,10 @@ static void at91sam9n12ek_nand_hw_init(void) /* Configure ENABLE pin for NandFlash */ at91_set_pio_output(AT91_PIO_PORTD, 4, 1); - at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ - at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ - at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ - at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ } #endif @@ -194,7 +194,7 @@ void at91sam9n12ek_ks8851_hw_init(void) &smc->cs[2].mode); /* Configure NCS2 PIN */ - at91_set_b_periph(AT91_PIO_PORTD, 19, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0); } #endif diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index b0d440d..cc81776 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -77,18 +77,18 @@ static void at91sam9x5ek_nand_hw_init(void) /* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); - at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ - at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ - at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ - at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ - at91_set_a_periph(AT91_PIO_PORTD, 6, 1); - at91_set_a_periph(AT91_PIO_PORTD, 7, 1); - at91_set_a_periph(AT91_PIO_PORTD, 8, 1); - at91_set_a_periph(AT91_PIO_PORTD, 9, 1); - at91_set_a_periph(AT91_PIO_PORTD, 10, 1); - at91_set_a_periph(AT91_PIO_PORTD, 11, 1); - at91_set_a_periph(AT91_PIO_PORTD, 12, 1); - at91_set_a_periph(AT91_PIO_PORTD, 13, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); } #endif @@ -128,49 +128,49 @@ vidinfo_t panel_info = { void lcd_enable(void) { if (has_lcdc()) - at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ } void lcd_disable(void) { if (has_lcdc()) - at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ } static void at91sam9x5ek_lcd_hw_init(void) { if (has_lcdc()) { - at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ - at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ - - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ - at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ + + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ at91_periph_clk_enable(ATMEL_ID_LCDC); } diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index ce67478..134c2fe 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -95,31 +95,31 @@ static void sama5d3xek_nor_hw_init(void) &smc->cs[0].mode); /* Address pin (A1 ~ A23) configuration */ - at91_set_a_periph(AT91_PIO_PORTE, 1, 0); - at91_set_a_periph(AT91_PIO_PORTE, 2, 0); - at91_set_a_periph(AT91_PIO_PORTE, 3, 0); - at91_set_a_periph(AT91_PIO_PORTE, 4, 0); - at91_set_a_periph(AT91_PIO_PORTE, 5, 0); - at91_set_a_periph(AT91_PIO_PORTE, 6, 0); - at91_set_a_periph(AT91_PIO_PORTE, 7, 0); - at91_set_a_periph(AT91_PIO_PORTE, 8, 0); - at91_set_a_periph(AT91_PIO_PORTE, 9, 0); - at91_set_a_periph(AT91_PIO_PORTE, 10, 0); - at91_set_a_periph(AT91_PIO_PORTE, 11, 0); - at91_set_a_periph(AT91_PIO_PORTE, 12, 0); - at91_set_a_periph(AT91_PIO_PORTE, 13, 0); - at91_set_a_periph(AT91_PIO_PORTE, 14, 0); - at91_set_a_periph(AT91_PIO_PORTE, 15, 0); - at91_set_a_periph(AT91_PIO_PORTE, 16, 0); - at91_set_a_periph(AT91_PIO_PORTE, 17, 0); - at91_set_a_periph(AT91_PIO_PORTE, 18, 0); - at91_set_a_periph(AT91_PIO_PORTE, 19, 0); - at91_set_a_periph(AT91_PIO_PORTE, 20, 0); - at91_set_a_periph(AT91_PIO_PORTE, 21, 0); - at91_set_a_periph(AT91_PIO_PORTE, 22, 0); - at91_set_a_periph(AT91_PIO_PORTE, 23, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0); /* CS0 pin configuration */ - at91_set_a_periph(AT91_PIO_PORTE, 26, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0); } #endif @@ -170,14 +170,14 @@ static void sama5d3xek_lcd_hw_init(void) gd->fb_base = CONFIG_SAMA5D3_LCD_BASE; /* The higher 8 bit of LCD is board related */ - at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */ - at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */ - at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */ - at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */ - at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */ - at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */ - at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */ - at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */ /* Configure lower 16 bit of LCD and enable clock */ at91_lcd_hw_init(); diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 23ec274..47f0bae 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -45,9 +45,9 @@ void spi_cs_deactivate(struct spi_slave *slave) static void sama5d4_xplained_spi0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ @@ -82,20 +82,20 @@ static void sama5d4_xplained_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ - at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ - at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ } #endif @@ -134,39 +134,39 @@ unsigned int has_lcdc(void) static void sama5d4_xplained_lcd_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ - - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ - - at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ - at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_LCDC); @@ -203,12 +203,12 @@ void lcd_show_board_info(void) #ifdef CONFIG_GENERIC_ATMEL_MCI void sama5d4_xplained_mci1_hw_init(void) { - at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ - at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ - at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ - at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ - at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ - at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ /* * As the mci io internal pull down is too strong, so if the io needs @@ -216,12 +216,12 @@ void sama5d4_xplained_mci1_hw_init(void) * the power consumption will increase, so disable the interanl pull * down to save the power. */ - at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_MCI1); @@ -239,16 +239,16 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MACB void sama5d4_xplained_macb0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_GMAC0); @@ -257,8 +257,8 @@ void sama5d4_xplained_macb0_hw_init(void) static void sama5d4_xplained_serial3_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ - at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_USART3); diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index 72bad23..d1b5ff5 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -45,9 +45,9 @@ void spi_cs_deactivate(struct spi_slave *slave) static void sama5d4ek_spi0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ @@ -82,20 +82,20 @@ static void sama5d4ek_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ - at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ - at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ } #endif @@ -135,33 +135,33 @@ unsigned int has_lcdc(void) static void sama5d4ek_lcd_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ - - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - - at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ - - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_LCDC); @@ -199,12 +199,12 @@ void lcd_show_board_info(void) #ifdef CONFIG_GENERIC_ATMEL_MCI void sama5d4ek_mci1_hw_init(void) { - at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ - at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ - at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ - at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ - at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ - at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ /* * As the mci io internal pull down is too strong, so if the io needs @@ -212,12 +212,12 @@ void sama5d4ek_mci1_hw_init(void) * the power consumption will increase, so disable the interanl pull * down to save the power. */ - at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_MCI1); @@ -235,16 +235,16 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MACB void sama5d4ek_macb0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_GMAC0); @@ -253,8 +253,8 @@ void sama5d4ek_macb0_hw_init(void) static void sama5d4ek_serial3_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ - at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_USART3); diff --git a/board/denx/ma5d4evk/ma5d4evk.c b/board/denx/ma5d4evk/ma5d4evk.c index ec0fa28..8146371 100644 --- a/board/denx/ma5d4evk/ma5d4evk.c +++ b/board/denx/ma5d4evk/ma5d4evk.c @@ -44,9 +44,9 @@ void spi_cs_deactivate(struct spi_slave *slave) static void ma5d4evk_spi0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ @@ -90,39 +90,39 @@ unsigned int has_lcdc(void) static void ma5d4evk_lcd_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */ - - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ - - at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ - at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_LCDC); @@ -134,16 +134,16 @@ static void ma5d4evk_lcd_hw_init(void) /* On-SoM eMMC */ void ma5d4evk_mci0_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */ - at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */ - at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */ - at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */ - at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */ - at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */ - at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */ - at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */ - at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */ - at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */ /* * As the mci io internal pull down is too strong, so if the io needs @@ -151,16 +151,16 @@ void ma5d4evk_mci0_hw_init(void) * the power consumption will increase, so disable the internal pull * down to save the power. */ - at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_MCI0); @@ -169,12 +169,12 @@ void ma5d4evk_mci0_hw_init(void) /* On-board MicroSD slot */ void ma5d4evk_mci1_hw_init(void) { - at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ - at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ - at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ - at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ - at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ - at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ /* * As the mci io internal pull down is too strong, so if the io needs @@ -182,16 +182,16 @@ void ma5d4evk_mci1_hw_init(void) * the power consumption will increase, so disable the internal pull * down to save the power. */ - at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); /* Deal with WP pin on the microSD slot. */ at91_set_pio_output(AT91_PIO_PORTE, 16, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 16, 1); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 16, 1); /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_MCI1); @@ -203,7 +203,7 @@ int board_mmc_init(bd_t *bis) /* De-assert reset on On-SoM eMMC */ at91_set_pio_output(AT91_PIO_PORTE, 15, 1); - at91_set_pio_pulldown(AT91_PIO_PORTE, 15, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 15, 0); ret = atmel_mci_init((void *)ATMEL_BASE_MCI0); if (ret) /* eMMC init failed, skip it. */ @@ -223,16 +223,16 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MACB void ma5d4evk_macb0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_GMAC0); @@ -242,17 +242,17 @@ void ma5d4evk_macb0_hw_init(void) static void ma5d4evk_serial_hw_init(void) { /* USART0 */ - at91_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */ - at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */ - at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */ at91_periph_clk_enable(ATMEL_ID_USART0); /* USART1 */ - at91_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */ - at91_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */ - at91_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */ at91_periph_clk_enable(ATMEL_ID_USART1); } @@ -273,7 +273,7 @@ int board_early_init_f(void) at91_set_pio_output(AT91_PIO_PORTB, 21, 0); udelay(100); at91_set_pio_output(AT91_PIO_PORTB, 21, 1); - at91_set_pio_pulldown(AT91_PIO_PORTB, 21, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTB, 21, 0); ma5d4evk_serial_hw_init(); diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index 3d7af09..a938a2c 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -51,9 +51,9 @@ void spi_cs_deactivate(struct spi_slave *slave) static void vinco_spi0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ @@ -76,16 +76,16 @@ static void vinco_usb_hw_init(void) #ifdef CONFIG_GENERIC_ATMEL_MCI void vinco_mci0_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */ - at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */ - at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */ - at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */ - at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */ - at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */ - at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */ - at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */ - at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */ - at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */ /* * As the mci io internal pull down is too strong, so if the io needs @@ -93,16 +93,16 @@ void vinco_mci0_hw_init(void) * the power consumption will increase, so disable the interanl pull * down to save the power. */ - at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_MCI0); @@ -120,16 +120,16 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MACB void vinco_macb0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_GMAC0); @@ -141,8 +141,8 @@ void vinco_macb0_hw_init(void) static void vinco_serial3_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ - at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_USART3); diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 8e52e3d..2f9e44b 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -59,11 +59,6 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) { struct at91_port *at91_port = at91_pio_get_port(port); -#if defined(CPU_HAS_PIO3) - if (use_pullup) - at91_set_pio_pulldown(port, pin, 0); -#endif - if (at91_port && (pin < GPIO_PER_BANK)) at91_set_port_pullup(at91_port, pin, use_pullup); @@ -100,14 +95,7 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); -#if defined(CPU_HAS_PIO3) - writel(readl(&at91_port->abcdsr1) & ~mask, - &at91_port->abcdsr1); - writel(readl(&at91_port->abcdsr2) & ~mask, - &at91_port->abcdsr2); -#else - writel(mask, &at91_port->asr); -#endif + writel(mask, &at91_port->mux.pio2.asr); writel(mask, &at91_port->pdr); } @@ -126,25 +114,62 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); -#if defined(CPU_HAS_PIO3) - writel(readl(&at91_port->abcdsr1) | mask, - &at91_port->abcdsr1); - writel(readl(&at91_port->abcdsr2) & ~mask, - &at91_port->abcdsr2); -#else - writel(mask, &at91_port->bsr); -#endif + writel(mask, &at91_port->mux.pio2.bsr); + writel(mask, &at91_port->pdr); + } + + return 0; +} + +/* + * mux the pin to the "A" internal peripheral role. + */ +int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup) +{ + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; + + if (at91_port && (pin < GPIO_PER_BANK)) { + mask = 1 << pin; + writel(mask, &at91_port->idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask, + &at91_port->mux.pio3.abcdsr1); + writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask, + &at91_port->mux.pio3.abcdsr2); + writel(mask, &at91_port->pdr); } return 0; } -#if defined(CPU_HAS_PIO3) +/* + * mux the pin to the "B" internal peripheral role. + */ +int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup) +{ + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; + + if (at91_port && (pin < GPIO_PER_BANK)) { + mask = 1 << pin; + writel(mask, &at91_port->idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&at91_port->mux.pio3.abcdsr1) | mask, + &at91_port->mux.pio3.abcdsr1); + writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask, + &at91_port->mux.pio3.abcdsr2); + + writel(mask, &at91_port->pdr); + } + + return 0; +} /* * mux the pin to the "C" internal peripheral role. */ -int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) +int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup) { struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; @@ -153,10 +178,10 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); - writel(readl(&at91_port->abcdsr1) & ~mask, - &at91_port->abcdsr1); - writel(readl(&at91_port->abcdsr2) | mask, - &at91_port->abcdsr2); + writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask, + &at91_port->mux.pio3.abcdsr1); + writel(readl(&at91_port->mux.pio3.abcdsr2) | mask, + &at91_port->mux.pio3.abcdsr2); writel(mask, &at91_port->pdr); } @@ -166,7 +191,7 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) /* * mux the pin to the "D" internal peripheral role. */ -int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) +int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup) { struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; @@ -175,16 +200,15 @@ int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &at91_port->idr); at91_set_pio_pullup(port, pin, use_pullup); - writel(readl(&at91_port->abcdsr1) | mask, - &at91_port->abcdsr1); - writel(readl(&at91_port->abcdsr2) | mask, - &at91_port->abcdsr2); + writel(readl(&at91_port->mux.pio3.abcdsr1) | mask, + &at91_port->mux.pio3.abcdsr1); + writel(readl(&at91_port->mux.pio3.abcdsr2) | mask, + &at91_port->mux.pio3.abcdsr2); writel(mask, &at91_port->pdr); } return 0; } -#endif #ifdef CONFIG_DM_GPIO static bool at91_get_port_output(struct at91_port *at91_port, int offset) @@ -263,10 +287,27 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; + if (is_on) + writel(mask, &at91_port->ifer); + else + writel(mask, &at91_port->ifdr); + } + + return 0; +} + +/* + * enable/disable the glitch filter. mostly used with IRQ handling. + */ +int at91_pio3_set_pio_deglitch(unsigned port, unsigned pin, int is_on) +{ + struct at91_port *at91_port = at91_pio_get_port(port); + u32 mask; + + if (at91_port && (pin < GPIO_PER_BANK)) { + mask = 1 << pin; if (is_on) { -#if defined(CPU_HAS_PIO3) - writel(mask, &at91_port->ifscdr); -#endif + writel(mask, &at91_port->mux.pio3.ifscdr); writel(mask, &at91_port->ifer); } else { writel(mask, &at91_port->ifdr); @@ -276,11 +317,10 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) return 0; } -#if defined(CPU_HAS_PIO3) /* * enable/disable the debounce filter. */ -int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) +int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) { struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; @@ -288,8 +328,8 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) if (at91_port && (pin < GPIO_PER_BANK)) { mask = 1 << pin; if (is_on) { - writel(mask, &at91_port->ifscer); - writel(div & PIO_SCDR_DIV, &at91_port->scdr); + writel(mask, &at91_port->mux.pio3.ifscer); + writel(div & PIO_SCDR_DIV, &at91_port->mux.pio3.scdr); writel(mask, &at91_port->ifer); } else { writel(mask, &at91_port->ifdr); @@ -303,7 +343,7 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) * enable/disable the pull-down. * If pull-up already enabled while calling the function, we disable it. */ -int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on) +int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on) { struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; @@ -312,18 +352,31 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on) mask = 1 << pin; if (is_on) { at91_set_pio_pullup(port, pin, 0); - writel(mask, &at91_port->ppder); + writel(mask, &at91_port->mux.pio3.ppder); } else - writel(mask, &at91_port->ppddr); + writel(mask, &at91_port->mux.pio3.ppddr); } return 0; } +int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) +{ + struct at91_port *at91_port = at91_pio_get_port(port); + + if (use_pullup) + at91_pio3_set_pio_pulldown(port, pin, 0); + + if (at91_port && (pin < GPIO_PER_BANK)) + at91_set_port_pullup(at91_port, pin, use_pullup); + + return 0; +} + /* * disable Schmitt trigger */ -int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin) +int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin) { struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; @@ -336,7 +389,6 @@ int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin) return 0; } -#endif /* * enable/disable the multi-driver. This is only valid for output and diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index be3d82e..eb8d2b3 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -333,7 +333,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd) ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK; writel(value, &pio->pioa.pdr); - writel(value, &pio->pioa.asr); + writel(value, &pio->pioa.mux.pio2.asr); #ifdef CONFIG_RMII value = ATMEL_PMX_BA_ERXCK; @@ -344,7 +344,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd) ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2; #endif writel(value, &pio->piob.pdr); - writel(value, &pio->piob.bsr); + writel(value, &pio->piob.mux.pio2.bsr); at91_periph_clk_enable(ATMEL_ID_EMAC); -- cgit v0.10.2 From 9319a756fffb0aae21adcd7caf8674411a22c165 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 12:44:37 +0800 Subject: pinctrl: at91: add pinctrl driver AT91 PIO controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. Each SoC will have to describe the its limitation and pin configuration via device tree. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h index 946f076..4840a2b 100644 --- a/arch/arm/mach-at91/include/mach/at91_pio.h +++ b/arch/arm/mach-at91/include/mach/at91_pio.h @@ -109,7 +109,11 @@ typedef struct at91_port { u32 wpsr; /* 0xE8 Write Protect Status Register */ u32 reserved11[5]; /* */ u32 schmitt; /* 0x100 Schmitt Trigger Register */ - u32 reserved12[63]; + u32 reserved12[4]; /* 0x104 ~ 0x110 */ + u32 driver1; /* 0x114 I/O Driver Register1(AT91SAM9x5's driver1) */ + u32 driver12; /* 0x118 I/O Driver Register12(AT91SAM9x5's driver2 or SAMA5D3x's driver1 ) */ + u32 driver2; /* 0x11C I/O Driver Register2(SAMA5D3x's driver2) */ + u32 reserved13[12]; /* 0x120 ~ 0x14C */ } at91_port_t; typedef union at91_pio { diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 9d0f501..355aeae 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -150,6 +150,20 @@ config ROCKCHIP_RK3288_PINCTRL definitions and pin control functions for each available multiplex function. +config PINCTRL_AT91 + bool "AT91 pinctrl driver" + depends on DM + help + This option is to enable the AT91 pinctrl driver for AT91 PIO + controller. AT91 PIO controller is a combined gpio-controller, + pin-mux and pin-config module. Each I/O pin may be dedicated as + a general-purpose I/O or be assigned to a function of an embedded + peripheral. Each I/O pin has a glitch filter providing rejection of + glitches lower than one-half of peripheral clock cycle and + a debouncing filter providing rejection of unwanted pulses from key + or push button operations. You can also control the multi-driver + capability, pull-up and pull-down feature on each I/O pin. + config PINCTRL_AT91PIO4 bool "AT91 PIO4 pinctrl driver" depends on DM diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 2ac9c19..bbb2480 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -5,6 +5,7 @@ obj-y += pinctrl-uclass.o obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o +obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-y += nxp/ obj-$(CONFIG_ARCH_ATH79) += ath79/ diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c new file mode 100644 index 0000000..904e1bd --- /dev/null +++ b/drivers/pinctrl/pinctrl-at91.c @@ -0,0 +1,453 @@ +/* + * Atmel PIO pinctrl driver + * + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MAX_GPIO_BANKS 5 +#define MAX_NB_GPIO_PER_BANK 32 + +#define MAX_PINMUX_ENTRIES 200 + +struct at91_pinctrl_priv { + struct at91_port *reg_base[MAX_GPIO_BANKS]; + u32 nbanks; +}; + +#define PULL_UP BIT(0) +#define MULTI_DRIVE BIT(1) +#define DEGLITCH BIT(2) +#define PULL_DOWN BIT(3) +#define DIS_SCHMIT BIT(4) +#define DRIVE_STRENGTH_SHIFT 5 +#define DRIVE_STRENGTH_MASK 0x3 +#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT) +#define OUTPUT BIT(7) +#define OUTPUT_VAL_SHIFT 8 +#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT) +#define DEBOUNCE BIT(16) +#define DEBOUNCE_VAL_SHIFT 17 +#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) + +/** + * These defines will translated the dt binding settings to our internal + * settings. They are not necessarily the same value as the register setting. + * The actual drive strength current of low, medium and high must be looked up + * from the corresponding device datasheet. This value is different for pins + * that are even in the same banks. It is also dependent on VCC. + * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive + * strength when there is no dt config for it. + */ +#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT) +#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT) +#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT) +#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT) + +enum at91_mux { + AT91_MUX_GPIO = 0, + AT91_MUX_PERIPH_A = 1, + AT91_MUX_PERIPH_B = 2, + AT91_MUX_PERIPH_C = 3, + AT91_MUX_PERIPH_D = 4, +}; + +/** + * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group + * on new IP with support for periph C and D the way to mux in + * periph A and B has changed + * So provide the right callbacks + * if not present means the IP does not support it + * @mux_A_periph: assign the corresponding pin to the peripheral A function. + * @mux_B_periph: assign the corresponding pin to the peripheral B function. + * @mux_C_periph: assign the corresponding pin to the peripheral C function. + * @mux_D_periph: assign the corresponding pin to the peripheral D function. + * @set_deglitch: enable/disable the deglitch feature. + * @set_debounce: enable/disable the debounce feature. + * @set_pulldown: enable/disable the pulldown feature. + * @disable_schmitt_trig: disable schmitt trigger + */ +struct at91_pinctrl_mux_ops { + void (*mux_A_periph)(struct at91_port *pio, u32 mask); + void (*mux_B_periph)(struct at91_port *pio, u32 mask); + void (*mux_C_periph)(struct at91_port *pio, u32 mask); + void (*mux_D_periph)(struct at91_port *pio, u32 mask); + void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on); + void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on, + u32 div); + void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on); + void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask); + void (*set_drivestrength)(struct at91_port *pio, u32 pin, + u32 strength); +}; + +static u32 two_bit_pin_value_shift_amount(u32 pin) +{ + /* return the shift value for a pin for "two bit" per pin registers, + * i.e. drive strength */ + return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2) + ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); +} + +static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask) +{ + writel(mask, &pio->idr); +} + +static void at91_mux_set_pullup(struct at91_port *pio, u32 mask, bool on) +{ + if (on) + writel(mask, &pio->mux.pio3.ppddr); + + writel(mask, (on ? &pio->puer : &pio->pudr)); +} + +static void at91_mux_set_output(struct at91_port *pio, unsigned mask, + bool is_on, bool val) +{ + writel(mask, (val ? &pio->sodr : &pio->codr)); + writel(mask, (is_on ? &pio->oer : &pio->odr)); +} + +static void at91_mux_set_multidrive(struct at91_port *pio, u32 mask, bool on) +{ + writel(mask, (on ? &pio->mder : &pio->mddr)); +} + +static void at91_mux_set_A_periph(struct at91_port *pio, u32 mask) +{ + writel(mask, &pio->mux.pio2.asr); +} + +static void at91_mux_set_B_periph(struct at91_port *pio, u32 mask) +{ + writel(mask, &pio->mux.pio2.bsr); +} + +static void at91_mux_pio3_set_A_periph(struct at91_port *pio, u32 mask) +{ + writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1); + writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2); +} + +static void at91_mux_pio3_set_B_periph(struct at91_port *pio, u32 mask) +{ + writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1); + writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2); +} + +static void at91_mux_pio3_set_C_periph(struct at91_port *pio, u32 mask) +{ + writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1); + writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2); +} + +static void at91_mux_pio3_set_D_periph(struct at91_port *pio, u32 mask) +{ + writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1); + writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2); +} + +static void at91_mux_set_deglitch(struct at91_port *pio, u32 mask, bool is_on) +{ + writel(mask, (is_on ? &pio->ifer : &pio->ifdr)); +} + +static void at91_mux_pio3_set_deglitch(struct at91_port *pio, + u32 mask, bool is_on) +{ + if (is_on) + writel(mask, &pio->mux.pio3.ifscdr); + at91_mux_set_deglitch(pio, mask, is_on); +} + +static void at91_mux_pio3_set_debounce(struct at91_port *pio, u32 mask, + bool is_on, u32 div) +{ + if (is_on) { + writel(mask, &pio->mux.pio3.ifscer); + writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr); + writel(mask, &pio->ifer); + } else { + writel(mask, &pio->mux.pio3.ifscdr); + } +} + +static void at91_mux_pio3_set_pulldown(struct at91_port *pio, + u32 mask, bool is_on) +{ + if (is_on) + writel(mask, &pio->pudr); + + writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr)); +} + +static void at91_mux_pio3_disable_schmitt_trig(struct at91_port *pio, + u32 mask) +{ + writel(readl(&pio->schmitt) | mask, &pio->schmitt); +} + +static void set_drive_strength(void *reg, u32 pin, u32 strength) +{ + u32 shift = two_bit_pin_value_shift_amount(pin); + + clrsetbits_le32(reg, DRIVE_STRENGTH_MASK << shift, strength << shift); +} + +static void at91_mux_sama5d3_set_drivestrength(struct at91_port *pio, + u32 pin, u32 setting) +{ + void *reg; + + reg = &pio->driver12; + if (pin >= MAX_NB_GPIO_PER_BANK / 2) + reg = &pio->driver2; + + /* do nothing if setting is zero */ + if (!setting) + return; + + /* strength is 1 to 1 with setting for SAMA5 */ + set_drive_strength(reg, pin, setting); +} + +static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio, + u32 pin, u32 setting) +{ + void *reg; + + reg = &pio->driver1; + if (pin >= MAX_NB_GPIO_PER_BANK / 2) + reg = &pio->driver12; + + /* do nothing if setting is zero */ + if (!setting) + return; + + /* strength is inverse on SAM9x5s with our defines + * 0 = hi, 1 = med, 2 = low, 3 = rsvd */ + setting = DRIVE_STRENGTH_HI - setting; + + set_drive_strength(reg, pin, setting); +} + +static struct at91_pinctrl_mux_ops at91rm9200_ops = { + .mux_A_periph = at91_mux_set_A_periph, + .mux_B_periph = at91_mux_set_B_periph, + .set_deglitch = at91_mux_set_deglitch, +}; + +static struct at91_pinctrl_mux_ops at91sam9x5_ops = { + .mux_A_periph = at91_mux_pio3_set_A_periph, + .mux_B_periph = at91_mux_pio3_set_B_periph, + .mux_C_periph = at91_mux_pio3_set_C_periph, + .mux_D_periph = at91_mux_pio3_set_D_periph, + .set_deglitch = at91_mux_pio3_set_deglitch, + .set_debounce = at91_mux_pio3_set_debounce, + .set_pulldown = at91_mux_pio3_set_pulldown, + .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, + .set_drivestrength = at91_mux_sam9x5_set_drivestrength, +}; + +static struct at91_pinctrl_mux_ops sama5d3_ops = { + .mux_A_periph = at91_mux_pio3_set_A_periph, + .mux_B_periph = at91_mux_pio3_set_B_periph, + .mux_C_periph = at91_mux_pio3_set_C_periph, + .mux_D_periph = at91_mux_pio3_set_D_periph, + .set_deglitch = at91_mux_pio3_set_deglitch, + .set_debounce = at91_mux_pio3_set_debounce, + .set_pulldown = at91_mux_pio3_set_pulldown, + .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, + .set_drivestrength = at91_mux_sama5d3_set_drivestrength, +}; + +static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask) +{ + writel(mask, &pio->pdr); +} + +static void at91_mux_gpio_enable(struct at91_port *pio, u32 mask, bool input) +{ + writel(mask, &pio->per); + writel(mask, (input ? &pio->odr : &pio->oer)); +} + +static int at91_pmx_set(struct at91_pinctrl_mux_ops *ops, + struct at91_port *pio, u32 mask, enum at91_mux mux) +{ + at91_mux_disable_interrupt(pio, mask); + switch (mux) { + case AT91_MUX_GPIO: + at91_mux_gpio_enable(pio, mask, 1); + break; + case AT91_MUX_PERIPH_A: + ops->mux_A_periph(pio, mask); + break; + case AT91_MUX_PERIPH_B: + ops->mux_B_periph(pio, mask); + break; + case AT91_MUX_PERIPH_C: + if (!ops->mux_C_periph) + return -EINVAL; + ops->mux_C_periph(pio, mask); + break; + case AT91_MUX_PERIPH_D: + if (!ops->mux_D_periph) + return -EINVAL; + ops->mux_D_periph(pio, mask); + break; + } + if (mux) + at91_mux_gpio_disable(pio, mask); + + return 0; +} + +static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops, + struct at91_port *pio, u32 pin, u32 config) +{ + u32 mask = BIT(pin); + + if ((config & PULL_UP) && (config & PULL_DOWN)) + return -EINVAL; + + at91_mux_set_output(pio, mask, config & OUTPUT, + (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT); + at91_mux_set_pullup(pio, mask, config & PULL_UP); + at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); + if (ops->set_deglitch) + ops->set_deglitch(pio, mask, config & DEGLITCH); + if (ops->set_debounce) + ops->set_debounce(pio, mask, config & DEBOUNCE, + (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); + if (ops->set_pulldown) + ops->set_pulldown(pio, mask, config & PULL_DOWN); + if (ops->disable_schmitt_trig && config & DIS_SCHMIT) + ops->disable_schmitt_trig(pio, mask); + if (ops->set_drivestrength) + ops->set_drivestrength(pio, pin, + (config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT); + + return 0; +} + +static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin) +{ + struct at91_pinctrl_priv *priv = dev_get_priv(dev); + + if (bank >= priv->nbanks) { + debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks); + return -EINVAL; + } + + if (pin >= MAX_NB_GPIO_PER_BANK) { + debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK); + return -EINVAL; + } + + return 0; +} + +static int at91_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + struct at91_pinctrl_priv *priv = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + int node = config->of_offset; + u32 cells[MAX_PINMUX_ENTRIES]; + const u32 *list = cells; + u32 bank, pin; + u32 conf, mask, count, i; + int size; + int ret; + enum at91_mux mux; + struct at91_port *pio; + struct at91_pinctrl_mux_ops *ops = + (struct at91_pinctrl_mux_ops *)dev_get_driver_data(dev); + + /* + * the binding format is atmel,pins = , + * do sanity check and calculate pins number + */ + size = fdtdec_get_int_array_count(blob, node, "atmel,pins", + cells, ARRAY_SIZE(cells)); + + /* we do not check return since it's safe node passed down */ + count = size >> 2; + if (!count) + return -EINVAL; + + for (i = 0; i < count; i++) { + bank = *list++; + pin = *list++; + mux = *list++; + conf = *list++; + + ret = at91_pin_check_config(dev, bank, pin); + if (ret) + return ret; + + pio = priv->reg_base[bank]; + mask = BIT(pin); + + ret = at91_pmx_set(ops, pio, mask, mux); + if (ret) + return ret; + + ret = at91_pinconf_set(ops, pio, pin, conf); + if (ret) + return ret; + } + + return 0; +} + +const struct pinctrl_ops at91_pinctrl_ops = { + .set_state = at91_pinctrl_set_state, +}; + +static int at91_pinctrl_probe(struct udevice *dev) +{ + struct at91_pinctrl_priv *priv = dev_get_priv(dev); + fdt_addr_t addr_base; + int index; + + for (index = 0; index < MAX_GPIO_BANKS; index++) { + addr_base = dev_get_addr_index(dev, index); + if (addr_base == FDT_ADDR_T_NONE) + break; + + priv->reg_base[index] = (struct at91_port *)addr_base; + } + + priv->nbanks = index; + + return 0; +} + +static const struct udevice_id at91_pinctrl_match[] = { + { .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops }, + { .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops }, + { .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops }, + {} +}; + +U_BOOT_DRIVER(at91_pinctrl) = { + .name = "pinctrl_at91", + .id = UCLASS_PINCTRL, + .of_match = at91_pinctrl_match, + .probe = at91_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct at91_pinctrl_priv), + .ops = &at91_pinctrl_ops, +}; diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h index bbca3d0..2732d6c 100644 --- a/include/dt-bindings/pinctrl/at91.h +++ b/include/dt-bindings/pinctrl/at91.h @@ -15,6 +15,8 @@ #define AT91_PINCTRL_DEGLITCH (1 << 2) #define AT91_PINCTRL_PULL_DOWN (1 << 3) #define AT91_PINCTRL_DIS_SCHMIT (1 << 4) +#define AT91_PINCTRL_OUTPUT (1 << 7) +#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8) #define AT91_PINCTRL_DEBOUNCE (1 << 16) #define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17) -- cgit v0.10.2 From 5a07a5f9224d792a27ac9894f86239bc7b3298ba Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 12:46:19 +0800 Subject: gpio: Kconfig: add CONFIG_AT91_GPIO option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CONFIG_AT91_GPIO option is used to select AT91 PIO GPIO driver. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass Reviewed-by: Andreas Bießmann diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index dc4108f..c95e9ac 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -28,6 +28,19 @@ config DWAPB_GPIO help Support for the Designware APB GPIO driver. +config AT91_GPIO + bool "AT91 PIO GPIO driver" + depends on DM_GPIO + default n + help + Say yes here to select AT91 PIO GPIO driver. AT91 PIO + controller manages up to 32 fully programmable input/output + lines. Each I/O line may be dedicated as a general-purpose + I/O or be assigned to a function of an embedded peripheral. + The assignment to a function of an embedded peripheral is + the responsibility of AT91 Pinctrl driver. This driver is + responsible for the general-purpose I/O. + config ATMEL_PIO4 bool "ATMEL PIO4 driver" depends on DM_GPIO -- cgit v0.10.2 From cf468880c37be1a7fea0a842a14ba1e1e388147c Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 12:46:20 +0800 Subject: gpio: at91_gpio: add the device tree support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the device tree support. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass Reviewed-by: Andreas Bießmann diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 2f9e44b..37955cc 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -572,14 +572,29 @@ static int at91_gpio_probe(struct udevice *dev) uc_priv->bank_name = plat->bank_name; uc_priv->gpio_count = GPIO_PER_BANK; + +#if CONFIG_IS_ENABLED(OF_CONTROL) + plat->base_addr = (uint32_t)dev_get_addr_ptr(dev); +#endif port->regs = (struct at91_port *)plat->base_addr; return 0; } +#if CONFIG_IS_ENABLED(OF_CONTROL) +static const struct udevice_id at91_gpio_ids[] = { + { .compatible = "atmel,at91rm9200-gpio" }, + { } +}; +#endif + U_BOOT_DRIVER(gpio_at91) = { .name = "gpio_at91", .id = UCLASS_GPIO, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = at91_gpio_ids, + .platdata_auto_alloc_size = sizeof(struct at91_port_platdata), +#endif .ops = &gpio_at91_ops, .probe = at91_gpio_probe, .priv_auto_alloc_size = sizeof(struct at91_port_priv), -- cgit v0.10.2 From f2f3c1576a5d4b15788843ab3353e6307fe380ba Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 12:46:21 +0800 Subject: gpio: at91_gpio: add the clock support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the clock support. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass Reviewed-by: Andreas Bießmann diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 37955cc..98dbd82 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -569,6 +570,18 @@ static int at91_gpio_probe(struct udevice *dev) struct at91_port_priv *port = dev_get_priv(dev); struct at91_port_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + + clk_free(&clk); uc_priv->bank_name = plat->bank_name; uc_priv->gpio_count = GPIO_PER_BANK; -- cgit v0.10.2 From 110fa9797d3b9f7e71aa0ba55905d6ade9a68c00 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 24 Mar 2017 09:18:41 +0800 Subject: ARM: at91: dt: add dts files for sama5d3xek board Add the device tree files for sama5d3xek board. The dts files are copied from Linux-4.9, do the changes as below. - add reg property for the pinctrl node. - move the gpio nodes (pioA, pioB, pioC ...) as the pinctrl's slibling nodes. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compile warning. - add spi0 node aliases. Signed-off-by: Wenyou Yang diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a2c0717..e7ccb53 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -347,6 +347,14 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ at91-sama5d2_xplained.dtb +dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ + sama5d31ek.dtb \ + sama5d33ek.dtb \ + sama5d34ek.dtb \ + sama5d35ek.dtb \ + sama5d36ek.dtb \ + sama5d36ek_cmp.dtb + dtb-$(CONFIG_ARCH_BCM283X) += \ bcm2835-rpi-a-plus.dtb \ bcm2835-rpi-a.dtb \ diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi new file mode 100644 index 0000000..84ee089 --- /dev/null +++ b/arch/arm/dts/sama5d3.dtsi @@ -0,0 +1,1539 @@ +/* + * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC + * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ + +#include "skeleton.dtsi" +#include +#include +#include +#include +#include + +/ { + model = "Atmel SAMA5D3 family SoC"; + compatible = "atmel,sama5d3", "atmel,sama5"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + serial5 = &uart0; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + tcb0 = &tcb0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + ssc0 = &ssc0; + ssc1 = &ssc1; + pwm0 = &pwm0; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0x0>; + }; + }; + + pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + sram: sram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x20000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + mmc0: mmc@f0000000 { + compatible = "atmel,hsmci"; + reg = <0xf0000000 0x600>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + }; + + spi0: spi@f0004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0004000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + ssc0: ssc@f0008000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0008000 0x4000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + tcb0: timer@f0010000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf0010000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + i2c0: i2c@f0014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf0014000 0x4000>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + i2c1: i2c@f0018000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf0018000 0x4000>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + + usart0: serial@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f0020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0020000 0x100>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart0: serial@f0024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0024000 0x100>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + pwm0: pwm@f002c000 { + compatible = "atmel,sama5d3-pwm"; + reg = <0xf002c000 0x300>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + status = "disabled"; + }; + + isi: isi@f0034000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf0034000 0x4000>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + sfr: sfr@f0038000 { + compatible = "atmel,sama5d3-sfr", "syscon"; + reg = <0xf0038000 0x60>; + }; + + mmc1: mmc@f8000000 { + compatible = "atmel,hsmci"; + reg = <0xf8000000 0x600>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; + }; + + spi1: spi@f8008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf8008000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + ssc1: ssc@f800c000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf800c000 0x4000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&ssc1_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + adc0: adc@f8018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9x5-adc"; + reg = <0xf8018000 0x100>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7 + &pinctrl_adc0_ad8 + &pinctrl_adc0_ad9 + &pinctrl_adc0_ad10 + &pinctrl_adc0_ad11 + >; + clocks = <&adc_clk>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-channels-used = <0xfff>; + atmel,adc-startup-time = <40>; + atmel,adc-use-external-triggers; + atmel,adc-vref = <3000>; + atmel,adc-res = <10 12>; + atmel,adc-sample-hold-time = <11>; + atmel,adc-res-names = "lowres", "highres"; + status = "disabled"; + + trigger@0 { + reg = <0>; + trigger-name = "external-rising"; + trigger-value = <0x1>; + trigger-external; + }; + trigger@1 { + reg = <1>; + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; + }; + trigger@2 { + reg = <2>; + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; + }; + trigger@3 { + reg = <3>; + trigger-name = "continuous"; + trigger-value = <0x6>; + }; + }; + + i2c2: i2c@f801c000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf801c000 0x4000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi2_clk>; + status = "disabled"; + }; + + usart2: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x100>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + sha@f8034000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xf8034000 0x100>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; + dma-names = "tx"; + clocks = <&sha_clk>; + clock-names = "sha_clk"; + }; + + aes@f8038000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xf8038000 0x100>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; + dma-names = "tx", "rx"; + clocks = <&aes_clk>; + clock-names = "aes_clk"; + }; + + tdes@f803c000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xf803c000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; + dma-names = "tx", "rx"; + clocks = <&tdes_clk>; + clock-names = "tdes_clk"; + }; + + trng@f8040000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xf8040000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&trng_clk>; + }; + + dma0: dma-controller@ffffe600 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffe600 0x200>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + + dma1: dma-controller@ffffe800 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffe800 0x200>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,sama5d3-ddramc"; + reg = <0xffffea00 0x200>; + clocks = <&ddrck>, <&mpddr_clk>; + clock-names = "ddrck", "mpddr"; + }; + + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xffffee00 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&dbgu_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d3-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <47>; + }; + + pinctrl@fffff200 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; + ranges = <0xfffff200 0xfffff200 0xa00>; + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ + 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ + 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ + 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ + 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ + >; + reg = <0xfffff200 0x100 /* pioA */ + 0xfffff400 0x100 /* pioB */ + 0xfffff600 0x100 /* pioC */ + 0xfffff800 0x100 /* pioD */ + 0xfffffa00 0x100 /* pioE */ + >; + + /* shared pinctrl settings */ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = + ; /* PD19 periph A ADTRG */ + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = + ; /* PD20 periph A AD0 */ + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = + ; /* PD21 periph A AD1 */ + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = + ; /* PD22 periph A AD2 */ + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = + ; /* PD23 periph A AD3 */ + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = + ; /* PD24 periph A AD4 */ + }; + pinctrl_adc0_ad5: adc0_ad5 { + atmel,pins = + ; /* PD25 periph A AD5 */ + }; + pinctrl_adc0_ad6: adc0_ad6 { + atmel,pins = + ; /* PD26 periph A AD6 */ + }; + pinctrl_adc0_ad7: adc0_ad7 { + atmel,pins = + ; /* PD27 periph A AD7 */ + }; + pinctrl_adc0_ad8: adc0_ad8 { + atmel,pins = + ; /* PD28 periph A AD8 */ + }; + pinctrl_adc0_ad9: adc0_ad9 { + atmel,pins = + ; /* PD29 periph A AD9 */ + }; + pinctrl_adc0_ad10: adc0_ad10 { + atmel,pins = + ; /* PD30 periph A AD10, conflicts with PCK0 */ + }; + pinctrl_adc0_ad11: adc0_ad11 { + atmel,pins = + ; /* PD31 periph A AD11, conflicts with PCK1 */ + }; + }; + + dbgu { + u-boot,dm-pre-reloc; + pinctrl_dbgu: dbgu-0 { + u-boot,dm-pre-reloc; + atmel,pins = + ; /* PB31 periph A with pullup */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ + }; + }; + + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + ; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ + }; + }; + + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ + }; + + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ + }; + + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */ + }; + }; + + mmc0 { + u-boot,dm-pre-reloc; + pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { + u-boot,dm-pre-reloc; + atmel,pins = + ; /* PD1 periph A MCI0_DA0 with pullup */ + }; + pinctrl_mmc0_dat1_3: mmc0_dat1_3 { + u-boot,dm-pre-reloc; + atmel,pins = + ; /* PD4 periph A MCI0_DA3 with pullup */ + }; + pinctrl_mmc0_dat4_7: mmc0_dat4_7 { + u-boot,dm-pre-reloc; + atmel,pins = + ; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ + }; + }; + + mmc1 { + u-boot,dm-pre-reloc; + pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { + u-boot,dm-pre-reloc; + atmel,pins = + ; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ + }; + pinctrl_mmc1_dat1_3: mmc1_dat1_3 { + u-boot,dm-pre-reloc; + atmel,pins = + ; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ + }; + }; + + nand0 { + pinctrl_nand0_ale_cle: nand0_ale_cle-0 { + atmel,pins = + ; /* PE22 periph A with pullup */ + }; + }; + + pwm0 { + pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { + atmel,pins = + ; /* conflicts with ISI_D4 and LCDDAT20 */ + }; + pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { + atmel,pins = + ; /* conflicts with GTX0 */ + }; + pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { + atmel,pins = + ; /* conflicts with ISI_D5 and LCDDAT21 */ + }; + pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { + atmel,pins = + ; /* conflicts with GTX1 */ + }; + + pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { + atmel,pins = + ; /* conflicts with ISI_D6 and LCDDAT22 */ + }; + pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { + atmel,pins = + ; /* conflicts with GRX0 */ + }; + pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { + atmel,pins = + ; /* conflicts with G125CKO and RTS1 */ + }; + pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { + atmel,pins = + ; /* conflicts with ISI_D7 and LCDDAT23 */ + }; + pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { + atmel,pins = + ; /* conflicts with GRX1 */ + }; + pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { + atmel,pins = + ; /* conflicts with IRQ */ + }; + + pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { + atmel,pins = + ; /* conflicts with GTXCK */ + }; + pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { + atmel,pins = + ; /* conflicts with MCI0_DA4 and TIOA0 */ + }; + pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { + atmel,pins = + ; /* conflicts with GTXEN */ + }; + pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { + atmel,pins = + ; /* conflicts with MCI0_DA5 and TIOB0 */ + }; + + pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { + atmel,pins = + ; /* conflicts with GRXDV */ + }; + pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { + atmel,pins = + ; /* conflicts with MCI0_DA6 and TCLK0 */ + }; + pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { + atmel,pins = + ; /* conflicts with GRXER */ + }; + pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { + atmel,pins = + ; /* conflicts with MCI0_DA7 */ + }; + }; + + spi0 { + u-boot,dm-pre-reloc; + pinctrl_spi0: spi0-0 { + u-boot,dm-pre-reloc; + atmel,pins = + ; /* PD12 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + u-boot,dm-pre-reloc; + pinctrl_spi1: spi1-0 { + u-boot,dm-pre-reloc; + atmel,pins = + ; /* PC24 periph A SPI1_SPCK pin */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx { + atmel,pins = + ; /* PC18 periph A TD0 */ + }; + + pinctrl_ssc0_rx: ssc0_rx { + atmel,pins = + ; /* PC21 periph A RD0 */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx { + atmel,pins = + ; /* PB6 periph B TD1, conflicts with TD1 */ + }; + + pinctrl_ssc1_rx: ssc1_rx { + atmel,pins = + ; /* PB11 periph B RD1, conflicts with GRXCK */ + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; /* conflicts with ISI_PCK */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; /* conflicts with TWCK0, ISI_HSYNC */ + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; /* PD18 periph A with pullup */ + }; + + pinctrl_usart0_rts_cts: usart0_rts_cts-0 { + atmel,pins = + ; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; /* PB29 periph A with pullup */ + }; + + pinctrl_usart1_rts_cts: usart1_rts_cts-0 { + atmel,pins = + ; /* PB27 periph A, conflicts with G125CKO */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; /* PE26 periph B with pullup, conflicts NCS0 */ + }; + + pinctrl_usart2_rts_cts: usart2_rts_cts-0 { + atmel,pins = + ; /* PE24 periph B, conflicts with A24 */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + ; /* PE19 periph B with pullup, conflicts with A19 */ + }; + + pinctrl_usart3_rts_cts: usart3_rts_cts-0 { + atmel,pins = + ; /* PE17 periph B, conflicts with A17 */ + }; + }; + }; + + pioA: gpio@fffff200 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + u-boot,dm-pre-reloc; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + u-boot,dm-pre-reloc; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + u-boot,dm-pre-reloc; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + u-boot,dm-pre-reloc; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioE_clk>; + u-boot,dm-pre-reloc; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,sama5d3-pmc", "syscon"; + reg = <0xfffffc00 0x120>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + u-boot,dm-pre-reloc; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clock-frequency = <12000000>; + clock-accuracy = <50000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main_rc_osc &main_osc>; + }; + + plla: pllack@0 { + compatible = "atmel,sama5d3-clk-pll"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <8000000 50000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <0 166000000>; + atmel,clk-divisors = <1 2 4 3>; + u-boot,dm-pre-reloc; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: progck@0 { + #clock-cells = <0>; + reg = <0>; + interrupts = ; + }; + + prog1: progck@1 { + #clock-cells = <0>; + reg = <1>; + interrupts = ; + }; + + prog2: progck@2 { + #clock-cells = <0>; + reg = <2>; + interrupts = ; + }; + }; + + smd: smdclk { + compatible = "atmel,at91sam9x5-clk-smd"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck@2 { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + smdck: smdck@4 { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + uhpck: uhpck@6 { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck@7 { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck@8 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck@9 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck@10 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + }; + + periphck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + u-boot,dm-pre-reloc; + + dbgu_clk: dbgu_clk@2 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <2>; + }; + + hsmc_clk: hsmc_clk@5 { + #clock-cells = <0>; + reg = <5>; + }; + + pioA_clk: pioA_clk@6 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <6>; + }; + + pioB_clk: pioB_clk@7 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <7>; + }; + + pioC_clk: pioC_clk@8 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <8>; + }; + + pioD_clk: pioD_clk@9 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <9>; + }; + + pioE_clk: pioE_clk@10 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <10>; + }; + + usart0_clk: usart0_clk@12 { + #clock-cells = <0>; + reg = <12>; + atmel,clk-output-range = <0 66000000>; + }; + + usart1_clk: usart1_clk@13 { + #clock-cells = <0>; + reg = <13>; + atmel,clk-output-range = <0 66000000>; + }; + + usart2_clk: usart2_clk@14 { + #clock-cells = <0>; + reg = <14>; + atmel,clk-output-range = <0 66000000>; + }; + + usart3_clk: usart3_clk@15 { + #clock-cells = <0>; + reg = <15>; + atmel,clk-output-range = <0 66000000>; + }; + + uart0_clk: uart0_clk@16 { + #clock-cells = <0>; + reg = <16>; + atmel,clk-output-range = <0 66000000>; + }; + + twi0_clk: twi0_clk@18 { + reg = <18>; + #clock-cells = <0>; + atmel,clk-output-range = <0 16625000>; + }; + + twi1_clk: twi1_clk@19 { + #clock-cells = <0>; + reg = <19>; + atmel,clk-output-range = <0 16625000>; + }; + + twi2_clk: twi2_clk@20 { + #clock-cells = <0>; + reg = <20>; + atmel,clk-output-range = <0 16625000>; + }; + + mci0_clk: mci0_clk@21 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <21>; + }; + + mci1_clk: mci1_clk@22 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <22>; + }; + + spi0_clk: spi0_clk@24 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <24>; + atmel,clk-output-range = <0 133000000>; + }; + + spi1_clk: spi1_clk@25 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <25>; + atmel,clk-output-range = <0 133000000>; + }; + + tcb0_clk: tcb0_clk@26 { + #clock-cells = <0>; + reg = <26>; + atmel,clk-output-range = <0 133000000>; + }; + + pwm_clk: pwm_clk@28 { + #clock-cells = <0>; + reg = <28>; + }; + + adc_clk: adc_clk@29 { + #clock-cells = <0>; + reg = <29>; + atmel,clk-output-range = <0 66000000>; + }; + + dma0_clk: dma0_clk@30 { + #clock-cells = <0>; + reg = <30>; + }; + + dma1_clk: dma1_clk@31 { + #clock-cells = <0>; + reg = <31>; + }; + + uhphs_clk: uhphs_clk@32 { + #clock-cells = <0>; + reg = <32>; + }; + + udphs_clk: udphs_clk@33 { + #clock-cells = <0>; + reg = <33>; + }; + + isi_clk: isi_clk@37 { + #clock-cells = <0>; + reg = <37>; + }; + + ssc0_clk: ssc0_clk@38 { + #clock-cells = <0>; + reg = <38>; + atmel,clk-output-range = <0 66000000>; + }; + + ssc1_clk: ssc1_clk@39 { + #clock-cells = <0>; + reg = <39>; + atmel,clk-output-range = <0 66000000>; + }; + + sha_clk: sha_clk@42 { + #clock-cells = <0>; + reg = <42>; + }; + + aes_clk: aes_clk@43 { + #clock-cells = <0>; + reg = <43>; + }; + + tdes_clk: tdes_clk@44 { + #clock-cells = <0>; + reg = <44>; + }; + + trng_clk: trng_clk@45 { + #clock-cells = <0>; + reg = <45>; + }; + + fuse_clk: fuse_clk@48 { + #clock-cells = <0>; + reg = <48>; + }; + + mpddr_clk: mpddr_clk@49 { + #clock-cells = <0>; + reg = <49>; + }; + }; + }; + + rstc@fffffe00 { + compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; + }; + + shutdown-controller@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&mck>; + }; + + watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + atmel,startup-time-usec = <75>; + }; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + atmel,startup-time-usec = <1200000>; + }; + + clk32k: slowck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + + rtc@fffffeb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffeb0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + }; + }; + + usb0: gadget@00500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,sama5d3-udc"; + reg = <0x00500000 0x100000 + 0xf8030000 0x4000>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + ep0: endpoint@0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1: endpoint@1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2: endpoint@2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3: endpoint@3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep4: endpoint@4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep5: endpoint@5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep6: endpoint@6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep7i: endpoint@7 { + reg = <7>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep8: endpoint@8 { + reg = <8>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep9: endpoint@9 { + reg = <9>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep10: endpoint@10 { + reg = <10>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep11: endpoint@11 { + reg = <11>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep12: endpoint@12 { + reg = <12>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep13: endpoint@13 { + reg = <13>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep14: endpoint@14 { + reg = <14>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep15: endpoint@15 { + reg = <15>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + }; + + usb1: ohci@00600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@00700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + nand0: nand@60000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = < 0x60000000 0x01000000 /* EBI CS3 */ + 0xffffc070 0x00000490 /* SMC PMECC regs */ + 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ + 0x00110000 0x00018000 /* ROM code */ + >; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand0_ale_cle>; + atmel,pmecc-lookup-table-offset = <0x0 0x8000>; + status = "disabled"; + + nfc@70000000 { + compatible = "atmel,sama5d3-nfc"; + #address-cells = <1>; + #size-cells = <1>; + reg = < + 0x70000000 0x08000000 /* NFC Command Registers */ + 0xffffc000 0x00000070 /* NFC HSMC regs */ + 0x00200000 0x00100000 /* NFC SRAM banks */ + >; + clocks = <&hsmc_clk>; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d31.dtsi b/arch/arm/dts/sama5d31.dtsi new file mode 100644 index 0000000..883878b --- /dev/null +++ b/arch/arm/dts/sama5d31.dtsi @@ -0,0 +1,16 @@ +/* + * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_uart.dtsi" + +/ { + compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/dts/sama5d31ek.dts b/arch/arm/dts/sama5d31ek.dts new file mode 100644 index 0000000..988f865 --- /dev/null +++ b/arch/arm/dts/sama5d31ek.dts @@ -0,0 +1,56 @@ +/* + * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d31.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D31-EK"; + compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + leds { + d3 { + label = "d3"; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sama5d33.dtsi b/arch/arm/dts/sama5d33.dtsi new file mode 100644 index 0000000..4b4434a --- /dev/null +++ b/arch/arm/dts/sama5d33.dtsi @@ -0,0 +1,14 @@ +/* + * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_gmac.dtsi" + +/ { + compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/dts/sama5d33ek.dts b/arch/arm/dts/sama5d33ek.dts new file mode 100644 index 0000000..a2aff7a --- /dev/null +++ b/arch/arm/dts/sama5d33ek.dts @@ -0,0 +1,49 @@ +/* + * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d33.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D33-EK"; + compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sama5d34.dtsi b/arch/arm/dts/sama5d34.dtsi new file mode 100644 index 0000000..aa01573 --- /dev/null +++ b/arch/arm/dts/sama5d34.dtsi @@ -0,0 +1,16 @@ +/* + * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_mci2.dtsi" + +/ { + compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/dts/sama5d34ek.dts b/arch/arm/dts/sama5d34ek.dts new file mode 100644 index 0000000..556ba65 --- /dev/null +++ b/arch/arm/dts/sama5d34ek.dts @@ -0,0 +1,66 @@ +/* + * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d34.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D34-EK"; + compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + + 24c256@50 { + compatible = "24c256"; + reg = <0x50>; + pagesize = <64>; + }; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + }; + }; + + leds { + d3 { + label = "d3"; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sama5d35.dtsi b/arch/arm/dts/sama5d35.dtsi new file mode 100644 index 0000000..16c39f4 --- /dev/null +++ b/arch/arm/dts/sama5d35.dtsi @@ -0,0 +1,18 @@ +/* + * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_uart.dtsi" +#include "sama5d3_tcb1.dtsi" + +/ { + compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/dts/sama5d35ek.dts b/arch/arm/dts/sama5d35ek.dts new file mode 100644 index 0000000..4e37cfd --- /dev/null +++ b/arch/arm/dts/sama5d35ek.dts @@ -0,0 +1,59 @@ +/* + * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d35.dtsi" +#include "sama5d3xmb.dtsi" + +/ { + model = "Atmel SAMA5D35-EK"; + compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + isi: isi@f0034000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + wakeup-source; + }; + }; +}; diff --git a/arch/arm/dts/sama5d36.dtsi b/arch/arm/dts/sama5d36.dtsi new file mode 100644 index 0000000..e85139e --- /dev/null +++ b/arch/arm/dts/sama5d36.dtsi @@ -0,0 +1,20 @@ +/* + * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC + * + * Copyright (C) 2013 Atmel, + * 2013 Josh Wu + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_tcb1.dtsi" +#include "sama5d3_uart.dtsi" + +/ { + compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/dts/sama5d36ek.dts b/arch/arm/dts/sama5d36ek.dts new file mode 100644 index 0000000..1fa7989 --- /dev/null +++ b/arch/arm/dts/sama5d36ek.dts @@ -0,0 +1,57 @@ +/* + * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Josh Wu + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d36.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D36-EK"; + compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sama5d36ek_cmp.dts b/arch/arm/dts/sama5d36ek_cmp.dts new file mode 100644 index 0000000..be41490 --- /dev/null +++ b/arch/arm/dts/sama5d36ek_cmp.dts @@ -0,0 +1,55 @@ +/* + * sama5d36ek_cmp.dts - Device Tree file for SAMA5D36-EK CMP board + * + * Copyright (C) 2016 Atmel, + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d36.dtsi" +#include "sama5d3xmb_cmp.dtsi" + +/ { + model = "Atmel SAMA5D36-EK"; + compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sama5d3_can.dtsi b/arch/arm/dts/sama5d3_can.dtsi new file mode 100644 index 0000000..177f088 --- /dev/null +++ b/arch/arm/dts/sama5d3_can.dtsi @@ -0,0 +1,74 @@ +/* + * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with + * CAN support + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff200 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + ; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + ; /* PB15 periph B TX, conflicts with GCOL */ + }; + }; + + }; + + pmc: pmc@fffffc00 { + periphck { + can0_clk: can0_clk@40 { + #clock-cells = <0>; + reg = <40>; + atmel,clk-output-range = <0 66000000>; + }; + + can1_clk: can1_clk@41 { + #clock-cells = <0>; + reg = <41>; + atmel,clk-output-range = <0 66000000>; + }; + }; + }; + + can0: can@f000c000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf000c000 0x300>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&can0_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8010000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8010000 0x300>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&can1_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_emac.dtsi b/arch/arm/dts/sama5d3_emac.dtsi new file mode 100644 index 0000000..b654e50 --- /dev/null +++ b/arch/arm/dts/sama5d3_emac.dtsi @@ -0,0 +1,55 @@ +/* + * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with + * Ethernet. + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff200 { + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + ; /* PC9 periph A EMDIO */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + macb1_clk: macb1_clk@35 { + #clock-cells = <0>; + reg = <35>; + }; + }; + }; + + macb1: ethernet@f802c000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + clocks = <&macb1_clk>, <&macb1_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_gmac.dtsi b/arch/arm/dts/sama5d3_gmac.dtsi new file mode 100644 index 0000000..81f6367 --- /dev/null +++ b/arch/arm/dts/sama5d3_gmac.dtsi @@ -0,0 +1,88 @@ +/* + * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with + * Gigabit Ethernet. + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff200 { + macb0 { + pinctrl_macb0_data_rgmii: macb0_data_rgmii { + atmel,pins = + ; /* PB7 periph A GRX3, conflicts with RK1 */ + }; + pinctrl_macb0_data_gmii: macb0_data_gmii { + atmel,pins = + ; /* PB26 periph B GRX7, conflicts with CTS1 */ + }; + pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { + atmel,pins = + ; /* PB18 periph A G125CK */ + }; + pinctrl_macb0_signal_gmii: macb0_signal_gmii { + atmel,pins = + ; /* PB27 periph B G125CKO */ + }; + + }; + }; + + pmc: pmc@fffffc00 { + periphck { + macb0_clk: macb0_clk@34 { + #clock-cells = <0>; + reg = <34>; + }; + }; + }; + + macb0: ethernet@f0028000 { + compatible = "atmel,sama5d3-gem"; + reg = <0xf0028000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_lcd.dtsi b/arch/arm/dts/sama5d3_lcd.dtsi new file mode 100644 index 0000000..14d7c2b --- /dev/null +++ b/arch/arm/dts/sama5d3_lcd.dtsi @@ -0,0 +1,215 @@ +/* + * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with + * LCD support + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include + +/ { + ahb { + apb { + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + pinctrl@fffff200 { + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt { + atmel,pins = + ; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ + }; + + pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + lcdc_clk: lcdc_clk@36 { + #clock-cells = <0>; + reg = <36>; + }; + }; + + systemck { + lcdck: lcdck@3 { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_mci2.dtsi b/arch/arm/dts/sama5d3_mci2.dtsi new file mode 100644 index 0000000..2d289ed --- /dev/null +++ b/arch/arm/dts/sama5d3_mci2.dtsi @@ -0,0 +1,59 @@ +/* + * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with + * 3 MMC ports + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff200 { + mmc2 { + pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { + atmel,pins = + ; /* PC11 periph A MCI2_DA0 with pullup */ + }; + pinctrl_mmc2_dat1_3: mmc2_dat1_3 { + atmel,pins = + ; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + mci2_clk: mci2_clk@23 { + #clock-cells = <0>; + reg = <23>; + }; + }; + }; + + mmc2: mmc@f8004000 { + compatible = "atmel,hsmci"; + reg = <0xf8004000 0x600>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; + clocks = <&mci2_clk>; + clock-names = "mci_clk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_tcb1.dtsi b/arch/arm/dts/sama5d3_tcb1.dtsi new file mode 100644 index 0000000..5be60b4 --- /dev/null +++ b/arch/arm/dts/sama5d3_tcb1.dtsi @@ -0,0 +1,39 @@ +/* + * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with + * 2 TC blocks. + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include +#include + +/ { + aliases { + tcb1 = &tcb1; + }; + + ahb { + apb { + pmc: pmc@fffffc00 { + periphck { + tcb1_clk: tcb1_clk@27 { + #clock-cells = <0>; + reg = <27>; + }; + }; + }; + + tcb1: timer@f8014000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8014000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_uart.dtsi b/arch/arm/dts/sama5d3_uart.dtsi new file mode 100644 index 0000000..6a547fd --- /dev/null +++ b/arch/arm/dts/sama5d3_uart.dtsi @@ -0,0 +1,79 @@ +/* + * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with + * UART support + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include +#include + +/ { + aliases { + serial5 = &uart0; + serial6 = &uart1; + }; + + ahb { + apb { + pinctrl@fffff200 { + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; /* PC30 periph A with pullup, conflicts with ISI_PCK */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + uart0_clk: uart0_clk@16 { + #clock-cells = <0>; + reg = <16>; + atmel,clk-output-range = <0 66000000>; + }; + + uart1_clk: uart1_clk@17 { + #clock-cells = <0>; + reg = <17>; + atmel,clk-output-range = <0 66000000>; + }; + }; + }; + + uart0: serial@f0024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0024000 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart1: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x200>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3xcm.dtsi b/arch/arm/dts/sama5d3xcm.dtsi new file mode 100644 index 0000000..2cf9c36 --- /dev/null +++ b/arch/arm/dts/sama5d3xcm.dtsi @@ -0,0 +1,123 @@ +/* + * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ + +/ { + compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + chosen { + bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; + }; + + macb0: ethernet@f0028000 { + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + }; + }; + + nand0: nand@60000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + d2 { + label = "d2"; + gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3xcm_cmp.dtsi b/arch/arm/dts/sama5d3xcm_cmp.dtsi new file mode 100644 index 0000000..77638c3 --- /dev/null +++ b/arch/arm/dts/sama5d3xcm_cmp.dtsi @@ -0,0 +1,166 @@ +/* + * sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module + * + * Copyright (C) 2016 Atmel, + * + * Licensed under GPLv2 or later. + */ + +/ { + compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + chosen { + bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; + }; + + macb0: ethernet@f0028000 { + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + }; + + i2c1: i2c@f0018000 { + pmic: act8865@5b { + compatible = "active-semi,act8865"; + reg = <0x5b>; + status = "disabled"; + + regulators { + vcc_1v8_reg: DCDC_REG1 { + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_1v2_reg: DCDC_REG2 { + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + vcc_3v3_reg: DCDC_REG3 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddana_reg: LDO_REG1 { + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddfuse_reg: LDO_REG2 { + regulator-name = "FUSE_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + }; + }; + }; + }; + + nand0: nand@60000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + d2 { + label = "d2"; + gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3xdm.dtsi b/arch/arm/dts/sama5d3xdm.dtsi new file mode 100644 index 0000000..035ab72 --- /dev/null +++ b/arch/arm/dts/sama5d3xdm.dtsi @@ -0,0 +1,41 @@ +/* + * sama5d3dm.dtsi - Device Tree file for SAMA5 display module + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ + +/ { + ahb { + apb { + i2c1: i2c@f0018000 { + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioE>; + interrupts = <31 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; + }; + + adc0: adc@f8018000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff200 { + board { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + ; /* PE31 GPIO with pull up deglith */ + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3xmb.dtsi b/arch/arm/dts/sama5d3xmb.dtsi new file mode 100644 index 0000000..f9ef905 --- /dev/null +++ b/arch/arm/dts/sama5d3xmb.dtsi @@ -0,0 +1,234 @@ +/* + * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3xcm.dtsi" + +/ { + compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &dbgu; + }; + + ahb { + apb { + mmc0: mmc@f0000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + status = "okay"; + u-boot,dm-pre-reloc; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; + }; + }; + + spi0: spi@f0004000 { + dmas = <0>, <0>; /* Do not use DMA for spi0 */ + u-boot,dm-pre-reloc; + + spi_flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + u-boot,dm-pre-reloc; + }; + }; + + ssc0: ssc@f0008000 { + atmel,clk-from-rk-pin; + }; + + /* + * i2c0 conflicts with ISI: + * disable it to allow the use of ISI + * can not enable audio when i2c0 disabled + */ + i2c0: i2c@f0014000 { + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck0>; + clock-names = "mclk"; + }; + }; + + i2c1: i2c@f0018000 { + ov2640: camera@0x30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; + /* use pck1 for the master clock of ov2640 */ + clocks = <&pck1>; + clock-names = "xvclk"; + assigned-clocks = <&pck1>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; + + usart1: serial@f0020000 { + dmas = <0>, <0>; /* Do not use DMA for usart1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + status = "okay"; + }; + + isi: isi@f0034000 { + port { + isi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; + + mmc1: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + u-boot,dm-pre-reloc; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; + }; + }; + + adc0: adc@f8018000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + status = "okay"; + }; + + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + /*interrupt-parent = <&pioE>;*/ + /*interrupts = <30 IRQ_TYPE_EDGE_FALLING>;*/ + reg = <1>; + }; + }; + + pinctrl@fffff200 { + board { + u-boot,dm-pre-reloc; + pinctrl_mmc0_cd: mmc0_cd { + u-boot,dm-pre-reloc; + atmel,pins = + ; /* PD17 GPIO with pullup deglitch */ + }; + + pinctrl_mmc1_cd: mmc1_cd { + u-boot,dm-pre-reloc; + atmel,pins = + ; /* PD18 GPIO with pullup deglitch */ + }; + + pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { + atmel,pins = + ; /* PD30 periph B */ + }; + + pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { + atmel,pins = + ; /* PD31 periph B ISI_MCK */ + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + ; /* PE24 gpio */ + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + ; /* PE29 gpio */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; /* PD29 GPIO with deglitch */ + }; + }; + }; + + dbgu: serial@ffffee00 { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ + status = "okay"; + u-boot,dm-pre-reloc; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + usb0: gadget@00500000 { + atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00600000 { + num-ports = <3>; + atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH + &pioD 26 GPIO_ACTIVE_LOW + &pioD 27 GPIO_ACTIVE_LOW + >; + status = "okay"; + }; + + usb2: ehci@00700000 { + status = "okay"; + }; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D3EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/sama5d3xmb_cmp.dtsi b/arch/arm/dts/sama5d3xmb_cmp.dtsi new file mode 100644 index 0000000..77f989c --- /dev/null +++ b/arch/arm/dts/sama5d3xmb_cmp.dtsi @@ -0,0 +1,236 @@ +/* + * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board + * + * Copyright (C) 2016 Atmel, + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3xcm_cmp.dtsi" + +/ { + compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &dbgu; + }; + + ahb { + apb { + mmc0: mmc@f0000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; + }; + }; + + spi0: spi@f0004000 { + dmas = <0>, <0>; /* Do not use DMA for spi0 */ + + spi_flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + ssc0: ssc@f0008000 { + atmel,clk-from-rk-pin; + }; + + /* + * i2c0 conflicts with ISI: + * disable it to allow the use of ISI + * can not enable audio when i2c0 disabled + */ + i2c0: i2c@f0014000 { + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck0>; + clock-names = "mclk"; + }; + }; + + i2c1: i2c@f0018000 { + ov2640: camera@0x30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; + /* use pck1 for the master clock of ov2640 */ + clocks = <&pck1>; + clock-names = "xvclk"; + assigned-clocks = <&pck1>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; + + usart1: serial@f0020000 { + dmas = <0>, <0>; /* Do not use DMA for usart1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + status = "okay"; + }; + + isi: isi@f0034000 { + port { + isi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; + + mmc1: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; + }; + }; + + adc0: adc@f8018000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + status = "okay"; + }; + + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + /*interrupt-parent = <&pioE>;*/ + /*interrupts = <30 IRQ_TYPE_EDGE_FALLING>;*/ + reg = <1>; + }; + }; + + pinctrl@fffff200 { + board { + pinctrl_gpio_keys: gpio_keys { + atmel,pins = + ; + }; + + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + ; /* PD17 GPIO with pullup deglitch */ + }; + + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + ; /* PD18 GPIO with pullup deglitch */ + }; + + pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { + atmel,pins = + ; /* PD30 periph B */ + }; + + pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { + atmel,pins = + ; /* PD31 periph B ISI_MCK */ + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + ; /* PE24 gpio */ + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + ; /* PE29 gpio */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; /* PD29 GPIO with deglitch */ + }; + }; + }; + + dbgu: serial@ffffee00 { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ + status = "okay"; + u-boot,dm-pre-reloc; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + usb0: gadget@00500000 { + atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D3EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + + status = "disabled"; + }; + + /* Conflict with LCD pins */ + gpio_keys { + compatible = "gpio-keys"; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + gpio-key,wakeup; + }; + }; +}; -- cgit v0.10.2 From 27ec910e8c32a0880a57f02c6c4cb7aa3fb5a1fe Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 24 Mar 2017 09:18:42 +0800 Subject: ARM: at91: dt: add dts file for sama5d3 Xplained Add the device tree file for sama5d3 Xplained board. The dts files are copied from the Linux-4.9, do changes as below. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compile warning. Signed-off-by: Wenyou Yang diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e7ccb53..c131149 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -355,6 +355,9 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ sama5d36ek.dtb \ sama5d36ek_cmp.dtb +dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ + at91-sama5d3_xplained.dtb + dtb-$(CONFIG_ARCH_BCM283X) += \ bcm2835-rpi-a-plus.dtb \ bcm2835-rpi-a.dtb \ diff --git a/arch/arm/dts/at91-sama5d3_xplained.dts b/arch/arm/dts/at91-sama5d3_xplained.dts new file mode 100644 index 0000000..6959710 --- /dev/null +++ b/arch/arm/dts/at91-sama5d3_xplained.dts @@ -0,0 +1,348 @@ +/* + * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "SAMA5D3 Xplained"; + compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5"; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &dbgu; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + mmc0: mmc@f0000000 { + u-boot,dm-pre-reloc; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + vmmc-supply = <&vcc_mmc0_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + }; + }; + + mmc1: mmc@f8000000 { + u-boot,dm-pre-reloc; + vmmc-supply = <&vcc_3v3_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "disabled"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 1 GPIO_ACTIVE_LOW>; + }; + }; + + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + + pmic: act8865@5b { + compatible = "active-semi,act8865"; + reg = <0x5b>; + status = "disabled"; + + regulators { + vcc_1v8_reg: DCDC_REG1 { + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_1v2_reg: DCDC_REG2 { + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_3v3_reg: DCDC_REG3 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddfuse_reg: LDO_REG1 { + regulator-name = "FUSE_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vddana_reg: LDO_REG2 { + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; + + macb0: ethernet@f0028000 { + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@7 { + reg = <0x7>; + }; + }; + + pwm0: pwm@f002c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>; + status = "okay"; + }; + + usart0: serial@f001c000 { + status = "okay"; + }; + + usart1: serial@f0020000 { + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + status = "okay"; + }; + + uart0: serial@f0024000 { + status = "okay"; + }; + + mmc1: mmc@f8000000 { + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>; + }; + }; + + spi1: spi@f8008000 { + cs-gpios = <&pioC 25 0>; + status = "okay"; + }; + + adc0: adc@f8018000 { + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7 + &pinctrl_adc0_ad8 + &pinctrl_adc0_ad9 + >; + status = "okay"; + }; + + i2c2: i2c@f801c000 { + dmas = <0>, <0>; /* Do not use DMA for i2c2 */ + pinctrl-0 = <&pinctrl_i2c2_pu>; + status = "okay"; + }; + + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + }; + }; + + dbgu: serial@ffffee00 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + pinctrl@fffff200 { + board { + u-boot,dm-pre-reloc; + pinctrl_i2c0_pu: i2c0_pu { + atmel,pins = + , + ; + }; + + pinctrl_i2c2_pu: i2c2_pu { + atmel,pins = + , + ; + }; + + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; + }; + + pinctrl_mmc0_cd: mmc0_cd { + u-boot,dm-pre-reloc; + atmel,pins = + ; + }; + + pinctrl_mmc1_cd: mmc1_cd { + u-boot,dm-pre-reloc; + atmel,pins = + ; + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; /* PE9, conflicts with A9 */ + }; + }; + }; + }; + + nand0: nand@60000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + + usb0: gadget@00500000 { + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00600000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 3 GPIO_ACTIVE_LOW + &pioE 4 GPIO_ACTIVE_LOW + >; + status = "okay"; + }; + + usb2: ehci@00700000 { + status = "okay"; + }; + }; + + vcc_mmc0_reg: fixedregulator@0 { + compatible = "regulator-fixed"; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + regulator-name = "mmc0-card-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + bp3 { + label = "PB_USER"; + gpios = <&pioE 29 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + d2 { + label = "d2"; + gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */ + linux,default-trigger = "heartbeat"; + }; + + d3 { + label = "d3"; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; -- cgit v0.10.2 From 2aaa4ce4bd0f04c100608f2c472eca63b51efbab Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 24 Mar 2017 09:18:43 +0800 Subject: ARM: dts: at91: add dts files for sama5d4 Xplained Add the device tree files for sama5d4 Xplained board. The dts files are copied from Linux-4.4, do the following changes. - add reg property for pinctrl node. - move the gpio nodes(pioA, pioB, pioC ...) from the pinctrl child's nodes to its slibling nodes. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compilation warnings. Signed-off-by: Wenyou Yang diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c131149..a6f947c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -358,6 +358,9 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ at91-sama5d3_xplained.dtb +dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \ + at91-sama5d4_xplained.dtb + dtb-$(CONFIG_ARCH_BCM283X) += \ bcm2835-rpi-a-plus.dtb \ bcm2835-rpi-a.dtb \ diff --git a/arch/arm/dts/at91-sama5d4_xplained.dts b/arch/arm/dts/at91-sama5d4_xplained.dts new file mode 100644 index 0000000..ca6aff2 --- /dev/null +++ b/arch/arm/dts/at91-sama5d4_xplained.dts @@ -0,0 +1,286 @@ +/* + * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board + * + * Copyright (C) 2015 Atmel, + * 2015 Josh Wu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "sama5d4.dtsi" + +/ { + model = "Atmel SAMA5D4 Xplained"; + compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &usart3; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + spi0: spi@f8010000 { + u-boot,dm-pre-reloc; + cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; + status = "okay"; + spi_flash@0 { + u-boot,dm-pre-reloc; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + i2c0: i2c@f8014000 { + status = "okay"; + }; + + macb0: ethernet@f8020000 { + phy-mode = "rmii"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + + phy0: ethernet-phy@1 { + interrupt-parent = <&pioE>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + }; + }; + + mmc1: mmc@fc000000 { + u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + vmmc-supply = <&vcc_mmc1_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 3 0>; + }; + }; + + usart3: serial@fc00c000 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + usart4: serial@fc010000 { + status = "okay"; + }; + + spi1: spi@fc018000 { + cs-gpios = <&pioB 21 0>; + status = "okay"; + }; + + adc0: adc@fc034000 { + pinctrl-names = "default"; + pinctrl-0 = < + /* external trigger conflicts with USBA_VBUS */ + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + atmel,adc-vref = <3300>; + status = "okay"; + }; + + watchdog@fc068640 { + status = "okay"; + }; + + pinctrl@fc06a000 { + board { + u-boot,dm-pre-reloc; + pinctrl_mmc1_cd: mmc1_cd { + u-boot,dm-pre-reloc; + atmel,pins = + ; + }; + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; + }; + pinctrl_macb0_phy_irq: macb0_phy_irq_0 { + atmel,pins = + ; + }; + }; + }; + }; + + usb0: gadget@00400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 11 GPIO_ACTIVE_HIGH + &pioE 14 GPIO_ACTIVE_HIGH + >; + status = "okay"; + }; + + usb2: ehci@00600000 { + status = "okay"; + }; + + nand0: nand@80000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + atmel,has-pmecc; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + d8 { + label = "d8"; + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + d10 { + label = "d10"; + gpios = <&pioE 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_3v3_reg: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VCC 3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + reg = <0 1>; + }; + + vcc_mmc1_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + gpio = <&pioE 4 GPIO_ACTIVE_LOW>; + regulator-name = "VDD MCI1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_reg>; + regulator-always-on; + reg = <1 1>; + }; +}; diff --git a/arch/arm/dts/sama5d4.dtsi b/arch/arm/dts/sama5d4.dtsi new file mode 100644 index 0000000..c6512ae --- /dev/null +++ b/arch/arm/dts/sama5d4.dtsi @@ -0,0 +1,1935 @@ +/* + * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" +#include +#include +#include +#include +#include + +/ { + model = "Atmel SAMA5D4 family SoC"; + compatible = "atmel,sama5d4"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &usart3; + serial1 = &usart4; + serial2 = &usart2; + serial3 = &usart0; + serial4 = &usart1; + serial5 = &uart0; + serial6 = &uart1; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + pwm0 = &pwm0; + ssc0 = &ssc0; + ssc1 = &ssc1; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + ns_sram: sram@00210000 { + compatible = "mmio-sram"; + reg = <0x00210000 0x10000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + usb0: gadget@00400000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,sama5d3-udc"; + reg = <0x00400000 0x100000 + 0xfc02c000 0x4000>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + ep0: endpoint@0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1: endpoint@1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2: endpoint@2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3: endpoint@3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep4: endpoint@4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep5: endpoint@5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep6: endpoint@6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep7: endpoint@7 { + reg = <7>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep8: endpoint@8 { + reg = <8>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep9: endpoint@9 { + reg = <9>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep10: endpoint@10 { + reg = <10>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep11: endpoint@11 { + reg = <11>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep12: endpoint@12 { + reg = <12>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep13: endpoint@13 { + reg = <13>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep14: endpoint@14 { + reg = <14>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep15: endpoint@15 { + reg = <15>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + }; + + usb1: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@00600000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00600000 0x100000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + L2: cache-controller@00a00000 { + compatible = "arm,pl310-cache"; + reg = <0x00a00000 0x1000>; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; + cache-unified; + cache-level = <2>; + }; + + nand0: nand@80000000 { + compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = < 0x80000000 0x08000000 /* EBI CS3 */ + 0xfc05c070 0x00000490 /* SMC PMECC regs */ + 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */ + >; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + status = "disabled"; + + nfc@90000000 { + compatible = "atmel,sama5d3-nfc"; + #address-cells = <1>; + #size-cells = <1>; + reg = < + 0x90000000 0x08000000 /* NFC Command Registers */ + 0xfc05c000 0x00000070 /* NFC HSMC regs */ + 0x00100000 0x00100000 /* NFC SRAM banks */ + >; + clocks = <&hsmc_clk>; + atmel,write-by-sram; + }; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + hlcdc: hlcdc@f0000000 { + compatible = "atmel,sama5d4-hlcdc"; + reg = <0xf0000000 0x4000>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + dma1: dma-controller@f0004000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0004000 0x200>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; + }; + + isi: isi@f0008000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf0008000 0x4000>; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + ramc0: ramc@f0010000 { + compatible = "atmel,sama5d3-ddramc"; + reg = <0xf0010000 0x200>; + clocks = <&ddrck>, <&mpddr_clk>; + clock-names = "ddrck", "mpddr"; + }; + + dma0: dma-controller@f0014000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0014000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + + pmc: pmc@f0018000 { + compatible = "atmel,sama5d3-pmc", "syscon"; + reg = <0xf0018000 0x120>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + u-boot,dm-pre-reloc; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clock-frequency = <12000000>; + clock-accuracy = <100000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main_rc_osc &main_osc>; + u-boot,dm-pre-reloc; + }; + + plla: pllack@0 { + compatible = "atmel,sama5d3-clk-pll"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <12000000 12000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main>; + u-boot,dm-pre-reloc; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <125000000 200000000>; + atmel,clk-divisors = <1 2 4 3>; + }; + + h32ck: h32mxck { + #clock-cells = <0>; + compatible = "atmel,sama5d4-clk-h32mx"; + clocks = <&mck>; + u-boot,dm-pre-reloc; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog@0 { + #clock-cells = <0>; + reg = <0>; + interrupts = ; + }; + + prog1: prog@1 { + #clock-cells = <0>; + reg = <1>; + interrupts = ; + }; + + prog2: prog@2 { + #clock-cells = <0>; + reg = <2>; + interrupts = ; + }; + }; + + smd: smdclk { + compatible = "atmel,at91sam9x5-clk-smd"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + ddrck: ddrck@2 { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + lcdck: lcdck@3 { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + + smdck: smdck@4 { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + uhpck: uhpcki@6 { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck@7 { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0@8 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1@9 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2@10 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + }; + + periph32ck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&h32ck>; + u-boot,dm-pre-reloc; + + pioD_clk: pioD_clk@5 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <5>; + }; + + usart0_clk: usart0_clk@6 { + #clock-cells = <0>; + reg = <6>; + }; + + usart1_clk: usart1_clk@7 { + #clock-cells = <0>; + reg = <7>; + }; + + icm_clk: icm_clk@9 { + #clock-cells = <0>; + reg = <9>; + }; + + aes_clk: aes_clk@12 { + #clock-cells = <0>; + reg = <12>; + }; + + tdes_clk: tdes_clk@14 { + #clock-cells = <0>; + reg = <14>; + }; + + sha_clk: sha_clk@15 { + #clock-cells = <0>; + reg = <15>; + }; + + matrix1_clk: matrix1_clk@17 { + #clock-cells = <0>; + reg = <17>; + }; + + hsmc_clk: hsmc_clk@22 { + #clock-cells = <0>; + reg = <22>; + }; + + pioA_clk: pioA_clk@23 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <23>; + }; + + pioB_clk: pioB_clk@24 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <24>; + }; + + pioC_clk: pioC_clk@25 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <25>; + }; + + pioE_clk: pioE_clk@26 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <26>; + }; + + uart0_clk: uart0_clk@27 { + #clock-cells = <0>; + reg = <27>; + }; + + uart1_clk: uart1_clk@28 { + #clock-cells = <0>; + reg = <28>; + }; + + usart2_clk: usart2_clk@29 { + #clock-cells = <0>; + reg = <29>; + }; + + usart3_clk: usart3_clk@30 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <30>; + }; + + usart4_clk: usart4_clk@31 { + #clock-cells = <0>; + reg = <31>; + }; + + twi0_clk: twi0_clk@32 { + reg = <32>; + #clock-cells = <0>; + }; + + twi1_clk: twi1_clk@33 { + #clock-cells = <0>; + reg = <33>; + }; + + twi2_clk: twi2_clk@34 { + #clock-cells = <0>; + reg = <34>; + }; + + mci0_clk: mci0_clk@35 { + #clock-cells = <0>; + reg = <35>; + }; + + mci1_clk: mci1_clk@36 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <36>; + }; + + spi0_clk: spi0_clk@37 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <37>; + }; + + spi1_clk: spi1_clk@38 { + #clock-cells = <0>; + reg = <38>; + }; + + spi2_clk: spi2_clk@39 { + #clock-cells = <0>; + reg = <39>; + }; + + tcb0_clk: tcb0_clk@40 { + #clock-cells = <0>; + reg = <40>; + }; + + tcb1_clk: tcb1_clk@41 { + #clock-cells = <0>; + reg = <41>; + }; + + tcb2_clk: tcb2_clk@42 { + #clock-cells = <0>; + reg = <42>; + }; + + pwm_clk: pwm_clk@43 { + #clock-cells = <0>; + reg = <43>; + }; + + adc_clk: adc_clk@44 { + #clock-cells = <0>; + reg = <44>; + }; + + dbgu_clk: dbgu_clk@45 { + #clock-cells = <0>; + reg = <45>; + }; + + uhphs_clk: uhphs_clk@46 { + #clock-cells = <0>; + reg = <46>; + }; + + udphs_clk: udphs_clk@47 { + #clock-cells = <0>; + reg = <47>; + }; + + ssc0_clk: ssc0_clki@48 { + #clock-cells = <0>; + reg = <48>; + }; + + ssc1_clk: ssc1_clk@49 { + #clock-cells = <0>; + reg = <49>; + }; + + trng_clk: trng_clk@53 { + #clock-cells = <0>; + reg = <53>; + }; + + macb0_clk: macb0_clk@54 { + #clock-cells = <0>; + reg = <54>; + }; + + macb1_clk: macb1_clk@55 { + #clock-cells = <0>; + reg = <55>; + }; + + fuse_clk: fuse_clk@57 { + #clock-cells = <0>; + reg = <57>; + }; + + securam_clk: securam_clk@59 { + #clock-cells = <0>; + reg = <59>; + }; + + smd_clk: smd_clk@61 { + #clock-cells = <0>; + reg = <61>; + }; + + twi3_clk: twi3_clk@62 { + #clock-cells = <0>; + reg = <62>; + }; + + catb_clk: catb_clk@63 { + #clock-cells = <0>; + reg = <63>; + }; + }; + + periph64ck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + dma0_clk: dma0_clk@8 { + #clock-cells = <0>; + reg = <8>; + }; + + cpkcc_clk: cpkcc_clk@10 { + #clock-cells = <0>; + reg = <10>; + }; + + aesb_clk: aesb_clk@13 { + #clock-cells = <0>; + reg = <13>; + }; + + mpddr_clk: mpddr_clk@16 { + #clock-cells = <0>; + reg = <16>; + }; + + matrix0_clk: matrix0_clk@18 { + #clock-cells = <0>; + reg = <18>; + }; + + vdec_clk: vdec_clk@19 { + #clock-cells = <0>; + reg = <19>; + }; + + dma1_clk: dma1_clk@50 { + #clock-cells = <0>; + reg = <50>; + }; + + lcdc_clk: lcdc_clk@51 { + #clock-cells = <0>; + reg = <51>; + }; + + isi_clk: isi_clk@52 { + #clock-cells = <0>; + reg = <52>; + }; + }; + }; + + mmc0: mmc@f8000000 { + compatible = "atmel,hsmci"; + reg = <0xf8000000 0x600>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(0))>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + }; + + uart0: serial@f8004000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8004000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(22))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@f8008000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf8008000 0x4000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(26))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(27))>; + dma-names = "tx", "rx"; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + pwm0: pwm@f800c000 { + compatible = "atmel,sama5d3-pwm"; + reg = <0xf800c000 0x300>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + status = "disabled"; + }; + + spi0: spi@f8010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf8010000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(10))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + i2c0: i2c@f8014000 { + compatible = "atmel,sama5d4-i2c"; + reg = <0xf8014000 0x4000>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(2))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + i2c1: i2c@f8018000 { + compatible = "atmel,sama5d4-i2c"; + reg = <0xf8018000 0x4000>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(4))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + + tcb0: timer@f801c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf801c000 0x100>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + macb0: ethernet@f8020000 { + compatible = "atmel,sama5d4-gem"; + reg = <0xf8020000 0x100>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + i2c2: i2c@f8024000 { + compatible = "atmel,sama5d4-i2c"; + reg = <0xf8024000 0x4000>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(6))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi2_clk>; + status = "disabled"; + }; + + sfr: sfr@f8028000 { + compatible = "atmel,sama5d4-sfr", "syscon"; + reg = <0xf8028000 0x60>; + }; + + usart0: serial@f802c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf802c000 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(37))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f8030000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8030000 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(39))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + mmc1: mmc@fc000000 { + compatible = "atmel,hsmci"; + reg = <0xfc000000 0x600>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(1))>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; + }; + + uart1: serial@fc004000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc004000 0x100>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(24))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fc008000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc008000 0x100>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(16))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fc00c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc00c000 0x100>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(18))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart4: serial@fc010000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc010000 0x100>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(20))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart4>; + clocks = <&usart4_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc1: ssc@fc014000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xfc014000 0x4000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(28))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(29))>; + dma-names = "tx", "rx"; + clocks = <&ssc1_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + spi1: spi@fc018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc018000 0x100>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(12))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi2: spi@fc01c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc01c000 0x100>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(14))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + clocks = <&spi2_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + tcb1: timer@fc020000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xfc020000 0x100>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + macb1: ethernet@fc028000 { + compatible = "atmel,sama5d4-gem"; + reg = <0xfc028000 0x100>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&macb1_clk>, <&macb1_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + trng@fc030000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xfc030000 0x100>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&trng_clk>; + }; + + adc0: adc@fc034000 { + compatible = "atmel,at91sam9x5-adc"; + reg = <0xfc034000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&adc_clk>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-channels-used = <0x01f>; + atmel,adc-startup-time = <40>; + atmel,adc-use-external-triggers; + atmel,adc-vref = <3000>; + atmel,adc-res = <8 10>; + atmel,adc-sample-hold-time = <11>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-ts-pressure-threshold = <10000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + trigger@0 { + trigger-name = "external-rising"; + trigger-value = <0x1>; + trigger-external; + reg = <0>; + }; + trigger@1 { + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; + reg = <1>; + }; + trigger@2 { + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; + reg = <2>; + }; + trigger@3 { + trigger-name = "continuous"; + trigger-value = <0x6>; + reg = <3>; + }; + }; + + aes@fc044000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xfc044000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(41))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(40))>; + dma-names = "tx", "rx"; + clocks = <&aes_clk>; + clock-names = "aes_clk"; + status = "okay"; + }; + + tdes@fc04c000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xfc04c000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(42))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(43))>; + dma-names = "tx", "rx"; + clocks = <&tdes_clk>; + clock-names = "tdes_clk"; + status = "okay"; + }; + + sha@fc050000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xfc050000 0x100>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(44))>; + dma-names = "tx"; + clocks = <&sha_clk>; + clock-names = "sha_clk"; + status = "okay"; + }; + + rstc@fc068600 { + compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; + reg = <0xfc068600 0x10>; + clocks = <&clk32k>; + }; + + shdwc@fc068610 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfc068610 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fc068630 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfc068630 0x10>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&h32ck>; + }; + + watchdog@fc068640 { + compatible = "atmel,sama5d4-wdt"; + reg = <0xfc068640 0x10>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + sckc@fc068650 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfc068650 0x4>; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <250000000>; + atmel,startup-time-usec = <75>; + }; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + atmel,startup-time-usec = <1200000>; + }; + + clk32k: slowck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + + rtc@fc0686b0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfc0686b0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + }; + + dbgu: serial@fc069000 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfc069000 0x200>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&dbgu_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + pioA: gpio@fc06a000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06a000 0x100>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fc06b000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06b000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; + + pioC: gpio@fc06c000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06c000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + u-boot,dm-pre-reloc; + }; + + pioD: gpio@fc068000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc068000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + }; + + pioE: gpio@fc06d000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06d000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioE_clk>; + }; + + pinctrl@fc06a000 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfc068000 0xfc068000 0x100 + 0xfc06a000 0xfc06a000 0x4000>; + /* WARNING: revisit as pin spec has changed */ + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ + 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ + 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ + 0x0003ff00 0x8002a800 0x00000000 /* pioD */ + 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ + >; + reg = < 0xfc06a000 0x100 + 0xfc06b000 0x100 + 0xfc06c000 0x100 + 0xfc068000 0x100 + 0xfc06d000 0x100 + >; + + /* pinctrl pin settings */ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = + ; /* conflicts with USBA_VBUS */ + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = + ; + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = + ; + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = + ; + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = + ; + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = + ; + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + , /* conflicts with D14 and TDI */ + ; /* conflicts with D15 and TDO */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; /* TWCK1, conflicts with UART0 TX and DIBN */ + }; + }; + + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + ; /* TWCK2, conflicts with RF0 */ + }; + }; + + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* ISI_HSYNC */ + }; + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ + }; + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ + }; + }; + + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD23 pin */ + }; + pinctrl_lcd_rgb777: lcd-rgb-3 { + atmel,pins = + /* LCDDAT0 conflicts with TMS */ + ; /* LCDD23 pin */ + }; + pinctrl_lcd_rgb888: lcd-rgb-4 { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + ; + }; + }; + + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + ; + }; + }; + + mmc0 { + pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { + atmel,pins = + ; + }; + pinctrl_mmc0_dat1_3: mmc0_dat1_3 { + atmel,pins = + ; + }; + pinctrl_mmc0_dat4_7: mmc0_dat4_7 { + atmel,pins = + ; + }; + }; + + mmc1 { + u-boot,dm-pre-reloc; + pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { + u-boot,dm-pre-reloc; + atmel,pins = + ; + }; + pinctrl_mmc1_dat1_3: mmc1_dat1_3 { + u-boot,dm-pre-reloc; + atmel,pins = + ; + }; + }; + + nand0 { + pinctrl_nand: nand-0 { + atmel,pins = + ; /* PC12 periph A Data bit 7 */ + }; + }; + + spi0 { + u-boot,dm-pre-reloc; + pinctrl_spi0: spi0-0 { + u-boot,dm-pre-reloc; + atmel,pins = + ; + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx { + atmel,pins = + ; /* TD0 */ + }; + + pinctrl_ssc0_rx: ssc0_rx { + atmel,pins = + ; /* RD0 */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx { + atmel,pins = + ; /* TD1 */ + }; + + pinctrl_ssc1_rx: ssc1_rx { + atmel,pins = + ; /* RD1 */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; + }; + }; + + spi2 { + pinctrl_spi2: spi2-0 { + atmel,pins = + ; + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; + }; + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = ; + }; + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = ; + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; + }; + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = ; + }; + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = ; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; + }; + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = ; /* conflicts with G0_RX3, PWMH1 */ + }; + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = ; /* conflicts with G0_TXER, ISI_VSYNC */ + }; + }; + + usart3 { + u-boot,dm-pre-reloc; + pinctrl_usart3: usart3-0 { + u-boot,dm-pre-reloc; + atmel,pins = + ; + }; + }; + + usart4 { + pinctrl_usart4: usart4-0 { + atmel,pins = + ; + }; + pinctrl_usart4_rts: usart4_rts-0 { + atmel,pins = ; /* conflicts with NWAIT, A19 */ + }; + pinctrl_usart4_cts: usart4_cts-0 { + atmel,pins = ; /* conflicts with A0/NBS0, MCI0_CDB */ + }; + }; + }; + + aic: interrupt-controller@fc06e000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d4-aic"; + interrupt-controller; + reg = <0xfc06e000 0x200>; + atmel,external-irqs = <56>; + }; + }; + }; +}; -- cgit v0.10.2 From 40e14221361970967bad1f87faf5151cb8bc982d Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 24 Mar 2017 09:18:44 +0800 Subject: ARM: dts: at91: add dts file for sama5d4ek Add the device tree file for sama5d4ek board. The dts file is copied from Linux-4.4, do the following changes. - add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. - fix the compilation warning. Signed-off-by: Wenyou Yang diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a6f947c..6a1d9c2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -358,6 +358,9 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ at91-sama5d3_xplained.dtb +dtb-$(CONFIG_TARGET_SAMA5D4EK) += \ + at91-sama5d4ek.dtb + dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \ at91-sama5d4_xplained.dtb diff --git a/arch/arm/dts/at91-sama5d4ek.dts b/arch/arm/dts/at91-sama5d4ek.dts new file mode 100644 index 0000000..b965f5b --- /dev/null +++ b/arch/arm/dts/at91-sama5d4ek.dts @@ -0,0 +1,341 @@ +/* + * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "sama5d4.dtsi" + +/ { + model = "Atmel SAMA5D4-EK"; + compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &usart3; + }; + + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + adc0: adc@fc034000 { + pinctrl-names = "default"; + pinctrl-0 = < + /* external trigger conflicts with USBA_VBUS */ + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */ + atmel,adc-vref = <3300>; + /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */ + status = "okay"; /* Enable ADC IIO support */ + }; + + mmc0: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 5 0>; + }; + }; + + ssc0: ssc@f8008000 { + status = "okay"; + }; + + spi0: spi@f8010000 { + u-boot,dm-pre-reloc; + cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; + status = "okay"; + spi_flash@0 { + u-boot,dm-pre-reloc; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + i2c0: i2c@f8014000 { + status = "okay"; + + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck2>; + clock-names = "mclk"; + }; + + qt1070:keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioE>; + interrupts = <25 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; + + atmel_mxt_ts@4c { + compatible = "atmel,atmel_mxt_ts"; + reg = <0x4c>; + interrupt-parent = <&pioE>; + interrupts = <24 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mxt_ts>; + }; + }; + + macb0: ethernet@f8020000 { + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioE>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + mmc1: mmc@fc000000 { + u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 6 0>; + }; + }; + + usart2: serial@fc008000 { + status = "okay"; + }; + + usart3: serial@fc00c000 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + usart4: serial@fc010000 { + status = "okay"; + }; + + watchdog@fc068640 { + status = "okay"; + }; + + pinctrl@fc06a000 { + board { + u-boot,dm-pre-reloc; + pinctrl_macb0_phy_irq: macb0_phy_irq { + atmel,pins = + ; + }; + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + ; + }; + pinctrl_mmc1_cd: mmc1_cd { + u-boot,dm-pre-reloc; + atmel,pins = + ; + }; + pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { + atmel,pins = + ; + }; + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + ; + }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + ; /* PE13 gpio */ + }; + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + ; + }; + pinctrl_mxt_ts: mxt_irq { + atmel,pins = + ; + }; + }; + }; + }; + + usb0: gadget@00400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ + &pioE 11 GPIO_ACTIVE_LOW + &pioE 12 GPIO_ACTIVE_LOW + >; + status = "okay"; + }; + + usb2: ehci@00600000 { + status = "okay"; + }; + + nand0: nand@80000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + atmel,has-pmecc; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + d8 { + label = "d8"; + /* PE28, conflicts with usart4 rts pin */ + gpios = <&pioE 28 GPIO_ACTIVE_LOW>; + }; + + d9 { + label = "d9"; + gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; + }; + + d10 { + label = "d10"; + gpios = <&pioE 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D4EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN1L", "Line In Jack", + "IN1R", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; +}; -- cgit v0.10.2 From c00d7c33ba0150ccac01aad67a56295bfc8ed824 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 24 Mar 2017 11:34:03 +0800 Subject: ARM: at91: spl: specify MMC and NAND boot device When OF_CONTROL is enabled, MMC boot device should not be detected automatically, it should be MMC1 fixedly only the status "enabled" is available. Add NAND Flash boot device as well. Signed-off-by: Wenyou Yang diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index 98f280c..e113336 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -39,12 +39,16 @@ u32 spl_boot_device(void) #if defined(CONFIG_SYS_USE_MMC) if (dev == ATMEL_SAMA5_BOOT_FROM_MCI) { +#if defined(CONFIG_SPL_OF_CONTROL) + return BOOT_DEVICE_MMC1; +#else if (off == 0) return BOOT_DEVICE_MMC1; if (off == 1) return BOOT_DEVICE_MMC2; printf("ERROR: MMC controller %i not present!\n", dev); hang(); +#endif } #endif @@ -53,6 +57,9 @@ u32 spl_boot_device(void) return BOOT_DEVICE_SPI; #endif + if (dev == ATMEL_SAMA5_BOOT_FROM_SMC) + return BOOT_DEVICE_NAND; + if (dev == ATMEL_SAMA5_BOOT_FROM_SAMBA) return BOOT_DEVICE_USB; -- cgit v0.10.2 From 730a7b47105ad6b6766344e59bb04c0cbb2e586a Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 24 Mar 2017 11:34:04 +0800 Subject: ARM: spl: atmel: bring in serial device before init Before setting up the serial communications, bring in the serial device from the device tree file. Signed-off-by: Wenyou Yang diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 688289e..847a30b 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -77,6 +77,8 @@ void s_init(void) void board_init_f(ulong dummy) { + int ret; + switch_to_main_crystal_osc(); #ifdef CONFIG_SAMA5D2 @@ -99,6 +101,12 @@ void board_init_f(ulong dummy) board_early_init_f(); + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + preloader_console_init(); mem_init(); -- cgit v0.10.2 From 5bede73c6c2478f2da9be64ee3a0d13d4b20f893 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 24 Mar 2017 11:34:05 +0800 Subject: ARM: spl: atmel: move mem_init() advance in SPL init. Because the MMC SPL puts the bbs section in the ddr memory, move calling mem_init() before calling spl_init(). Signed-off-by: Wenyou Yang diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 847a30b..b75c2cc 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -101,6 +101,8 @@ void board_init_f(ulong dummy) board_early_init_f(); + mem_init(); + ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); @@ -109,5 +111,4 @@ void board_init_f(ulong dummy) preloader_console_init(); - mem_init(); } -- cgit v0.10.2 From 7abd5aabfa8a2137c82d2f401d0da7413dd8cfaf Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 24 Mar 2017 11:34:06 +0800 Subject: ARM: at91: lds: use "_image_binary_end" for DT location The MMC SPL locates the BSS section to a different memory region from text, then use "_image_binary_end" variable to point to the correct device tree location. Signed-off-by: Wenyou Yang diff --git a/arch/arm/mach-at91/armv7/u-boot-spl.lds b/arch/arm/mach-at91/armv7/u-boot-spl.lds index c667c55..d2e41a0 100644 --- a/arch/arm/mach-at91/armv7/u-boot-spl.lds +++ b/arch/arm/mach-at91/armv7/u-boot-spl.lds @@ -47,6 +47,8 @@ SECTIONS *(.__end) } >.sram + _image_binary_end = .; + .bss : { . = ALIGN(4); -- cgit v0.10.2 From fc977b94a4988bd83e079c54c59c0754f8301b7f Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 13 Apr 2017 10:31:15 +0800 Subject: configs: at91-sama5_common: fix for CONFIG_AT91_GPIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add #ifndef CONFIG_DM_GPIO for CONFIG_AT91_GPIO define to avoid the redefine compilation error. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 3e97948..dbd4d84 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -27,7 +27,9 @@ #define CONFIG_ENV_VARS_UBOOT_CONFIG /* general purpose I/O */ +#ifndef CONFIG_DM_GPIO #define CONFIG_AT91_GPIO +#endif /* -- cgit v0.10.2 From 6dbadb4d95ee1590eb46bdd634c0b0cc3c693a7f Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 13 Apr 2017 10:31:16 +0800 Subject: board: sama5d4_xplained: update to support DM/DT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the configuration files to support the device tree and driver model, so do SPL. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 47f0bae..6684276 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -28,10 +28,12 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_ATMEL_SPI +#ifndef CONFIG_DM_SPI int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus == 0 && cs == 0; } +#endif void spi_cs_activate(struct spi_slave *slave) { diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 3e58495..72c239a 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -8,11 +8,15 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_FIT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -26,10 +30,35 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y -CONFIG_OF_LIBFDT=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 0c47883..0f6c2f4 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -6,7 +6,10 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_FIT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -24,10 +27,35 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y -CONFIG_OF_LIBFDT=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index e5d2f54..96816d4 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -4,9 +4,12 @@ CONFIG_TARGET_SAMA5D4_XPLAINED=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 @@ -25,10 +28,36 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 55f10ad..aced293 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -12,32 +12,21 @@ #include "at91-sama5_common.h" -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_USART3 -#define CONFIG_USART_ID ATMEL_ID_USART3 - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_SIZE 0x20000000 #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x210000 +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 #else #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -/* SerialFlash */ - #ifdef CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI -#define CONFIG_ATMEL_SPI0 -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 30000000 #endif @@ -58,32 +47,6 @@ #define CONFIG_ATMEL_NAND_HW_PMECC #endif -/* MMC */ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 -#endif - -/* USB */ - -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ATMEL -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -#endif - -/* USB device */ -#define CONFIG_USB_ETHER -#define CONFIG_USB_ETH_RNDIS -#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK" - -/* Ethernet Hardware */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY - /* LCD */ #ifdef CONFIG_LCD #define LCD_BPP LCD_COLOR16 @@ -107,7 +70,7 @@ /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x200000 -#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x18000 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 @@ -137,7 +100,7 @@ #elif CONFIG_SYS_USE_SERIALFLASH #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 #endif #endif -- cgit v0.10.2 From 3b93f852ca5ded9edca1939a5b78795f1df6fc92 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 13 Apr 2017 10:31:17 +0800 Subject: board: sama5d4_xplained: clean up code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Due to the introduction of the pinctrl and clk driver, and using device tree files, remove the unneeded hardcoded pin configuration and clock enabling code from the board file. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 6684276..30d4fb7 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -10,54 +10,17 @@ #include #include #include -#include #include #include #include #include #include -#include #include -#include -#include -#include #include -#include #include DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_ATMEL_SPI -#ifndef CONFIG_DM_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} -#endif - -void spi_cs_activate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); -} - -static void sama5d4_xplained_spi0_hw_init(void) -{ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ - - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SPI0); -} -#endif /* CONFIG_ATMEL_SPI */ - #ifdef CONFIG_NAND_ATMEL static void sama5d4_xplained_nand_hw_init(void) { @@ -202,61 +165,6 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD */ -#ifdef CONFIG_GENERIC_ATMEL_MCI -void sama5d4_xplained_mci1_hw_init(void) -{ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ - - /* - * As the mci io internal pull down is too strong, so if the io needs - * external pull up, the pull up resistor will be very small, if so - * the power consumption will increase, so disable the interanl pull - * down to save the power. - */ - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_MCI1); -} - -int board_mmc_init(bd_t *bis) -{ - /* Enable the power supply */ - at91_set_pio_output(AT91_PIO_PORTE, 4, 0); - - return atmel_mci_init((void *)ATMEL_BASE_MCI1); -} -#endif /* CONFIG_GENERIC_ATMEL_MCI */ - -#ifdef CONFIG_MACB -void sama5d4_xplained_macb0_hw_init(void) -{ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_GMAC0); -} -#endif - static void sama5d4_xplained_serial3_hw_init(void) { at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ @@ -268,12 +176,6 @@ static void sama5d4_xplained_serial3_hw_init(void) int board_early_init_f(void) { - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - at91_periph_clk_enable(ATMEL_ID_PIOE); - sama5d4_xplained_serial3_hw_init(); return 0; @@ -284,27 +186,15 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_ATMEL_SPI - sama5d4_xplained_spi0_hw_init(); -#endif #ifdef CONFIG_NAND_ATMEL sama5d4_xplained_nand_hw_init(); #endif -#ifdef CONFIG_GENERIC_ATMEL_MCI - sama5d4_xplained_mci1_hw_init(); -#endif -#ifdef CONFIG_MACB - sama5d4_xplained_macb0_hw_init(); -#endif #ifdef CONFIG_LCD sama5d4_xplained_lcd_hw_init(); #endif #ifdef CONFIG_CMD_USB sama5d4_xplained_usb_hw_init(); #endif -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - at91_udp_hw_init(); -#endif return 0; } @@ -316,34 +206,12 @@ int dram_init(void) return 0; } -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); -#endif - -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif -#endif - - return rc; -} - /* SPL */ #ifdef CONFIG_SPL_BUILD void spl_board_init(void) { -#ifdef CONFIG_SYS_USE_MMC - sama5d4_xplained_mci1_hw_init(); -#elif CONFIG_SYS_USE_NANDFLASH +#if CONFIG_SYS_USE_NANDFLASH sama5d4_xplained_nand_hw_init(); -#elif CONFIG_SYS_USE_SERIALFLASH - sama5d4_xplained_spi0_hw_init(); #endif } -- cgit v0.10.2 From 334794f58400e1a4fccd61dd8066c4f94f4605e7 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 13 Apr 2017 10:31:18 +0800 Subject: board: sama5d4_xplained: enable early debug UART MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 30d4fb7..94ecab2 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -165,6 +166,7 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD */ +#ifdef CONFIG_DEBUG_UART_BOARD_INIT static void sama5d4_xplained_serial3_hw_init(void) { at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ @@ -174,12 +176,21 @@ static void sama5d4_xplained_serial3_hw_init(void) at91_periph_clk_enable(ATMEL_ID_USART3); } -int board_early_init_f(void) +void board_debug_uart_init(void) { sama5d4_xplained_serial3_hw_init(); +} +#endif +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 72c239a..2b95a16 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -53,6 +53,12 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfc00c000 +CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 0f6c2f4..b0466c2 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -50,6 +50,12 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfc00c000 +CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 96816d4..57dec69 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -52,6 +52,12 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfc00c000 +CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y -- cgit v0.10.2 From ef33aa3dca7364d409518f8394bd51af60fc437f Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 13 Apr 2017 10:31:19 +0800 Subject: board: sama5d4ek: update to support DM/DT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the configuration files to support the device tree and driver model, so do SPL. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index d1b5ff5..a0e4bb7 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -28,10 +28,12 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_ATMEL_SPI +#ifndef CONFIG_DM_SPI int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus == 0 && cs == 0; } +#endif void spi_cs_activate(struct spi_slave *slave) { diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 7bf32e3..cf376d0 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -8,6 +8,9 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" CONFIG_BOOTDELAY=3 @@ -15,6 +18,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -28,9 +32,36 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 6092606..3e4c0a3 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -6,9 +6,13 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -26,11 +30,37 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index dff8995..ca3aae3 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -4,13 +4,15 @@ CONFIG_TARGET_SAMA5D4EK=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y @@ -27,11 +29,37 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 680d591..a5fd37f 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -12,32 +12,21 @@ #include "at91-sama5_common.h" -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_USART3 -#define CONFIG_USART_ID ATMEL_ID_USART3 - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_SIZE 0x20000000 #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x210000 +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 #else #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -/* SerialFlash */ - #ifdef CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI -#define CONFIG_ATMEL_SPI0 -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 30000000 #endif @@ -58,32 +47,6 @@ #define CONFIG_ATMEL_NAND_HW_PMECC #endif -/* MMC */ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 -#endif - -/* USB */ - -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ATMEL -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -#endif - -/* USB device */ -#define CONFIG_USB_ETHER -#define CONFIG_USB_ETH_RNDIS -#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK" - -/* Ethernet Hardware */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY - /* LCD */ #define LCD_BPP LCD_COLOR16 #define LCD_OUTPUT_BPP 18 @@ -105,7 +68,7 @@ /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x200000 -#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x18000 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 @@ -135,7 +98,7 @@ #elif CONFIG_SYS_USE_SERIALFLASH #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 #endif #endif -- cgit v0.10.2 From 33034a77a5c592bdf0fdf7b61c1d04e34b2d204f Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 13 Apr 2017 10:31:20 +0800 Subject: board: sama5d4ek: clean up code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Due to the introduction of the pinctrl and clk driver, and using device tree files, remove the unneeded hardcoded pin configuration and clock enabling code from the board file. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index a0e4bb7..f2d0a47 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -10,54 +10,17 @@ #include #include #include -#include #include #include #include #include #include -#include #include -#include -#include -#include #include -#include #include DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_ATMEL_SPI -#ifndef CONFIG_DM_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} -#endif - -void spi_cs_activate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); -} - -static void sama5d4ek_spi0_hw_init(void) -{ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ - - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SPI0); -} -#endif /* CONFIG_ATMEL_SPI */ - #ifdef CONFIG_NAND_ATMEL static void sama5d4ek_nand_hw_init(void) { @@ -198,61 +161,6 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD */ -#ifdef CONFIG_GENERIC_ATMEL_MCI -void sama5d4ek_mci1_hw_init(void) -{ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ - at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ - - /* - * As the mci io internal pull down is too strong, so if the io needs - * external pull up, the pull up resistor will be very small, if so - * the power consumption will increase, so disable the interanl pull - * down to save the power. - */ - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); - at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_MCI1); -} - -int board_mmc_init(bd_t *bis) -{ - /* Enable power for MCI1 interface */ - at91_set_pio_output(AT91_PIO_PORTE, 15, 0); - - return atmel_mci_init((void *)ATMEL_BASE_MCI1); -} -#endif /* CONFIG_GENERIC_ATMEL_MCI */ - -#ifdef CONFIG_MACB -void sama5d4ek_macb0_hw_init(void) -{ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_GMAC0); -} -#endif - static void sama5d4ek_serial3_hw_init(void) { at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ @@ -264,12 +172,6 @@ static void sama5d4ek_serial3_hw_init(void) int board_early_init_f(void) { - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - at91_periph_clk_enable(ATMEL_ID_PIOE); - sama5d4ek_serial3_hw_init(); return 0; @@ -280,27 +182,15 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_ATMEL_SPI - sama5d4ek_spi0_hw_init(); -#endif #ifdef CONFIG_NAND_ATMEL sama5d4ek_nand_hw_init(); #endif -#ifdef CONFIG_GENERIC_ATMEL_MCI - sama5d4ek_mci1_hw_init(); -#endif -#ifdef CONFIG_MACB - sama5d4ek_macb0_hw_init(); -#endif #ifdef CONFIG_LCD sama5d4ek_lcd_hw_init(); #endif #ifdef CONFIG_CMD_USB sama5d4ek_usb_hw_init(); #endif -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - at91_udp_hw_init(); -#endif return 0; } @@ -312,34 +202,12 @@ int dram_init(void) return 0; } -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); -#endif - -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif -#endif - - return rc; -} - /* SPL */ #ifdef CONFIG_SPL_BUILD void spl_board_init(void) { -#ifdef CONFIG_SYS_USE_MMC - sama5d4ek_mci1_hw_init(); -#elif CONFIG_SYS_USE_NANDFLASH +#if CONFIG_SYS_USE_NANDFLASH sama5d4ek_nand_hw_init(); -#elif CONFIG_SYS_USE_SERIALFLASH - sama5d4ek_spi0_hw_init(); #endif } -- cgit v0.10.2 From 22e10be456014400788f80d45fc5f5c0b9d4a81d Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 13 Apr 2017 10:31:21 +0800 Subject: board: sama5d4ek: enable early debug UART MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index f2d0a47..ffb4a50 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -161,6 +162,7 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD */ +#ifdef CONFIG_DEBUG_UART_BOARD_INIT static void sama5d4ek_serial3_hw_init(void) { at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ @@ -170,12 +172,21 @@ static void sama5d4ek_serial3_hw_init(void) at91_periph_clk_enable(ATMEL_ID_USART3); } -int board_early_init_f(void) +void board_debug_uart_init(void) { sama5d4ek_serial3_hw_init(); +} +#endif +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index cf376d0..8601d56 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -56,6 +56,12 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfc00c000 +CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 3e4c0a3..a9bcabf 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -54,6 +54,12 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfc00c000 +CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index ca3aae3..b56fd63 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -53,6 +53,12 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfc00c000 +CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y -- cgit v0.10.2