From f69766e4b5d47ecd3aa58677a8da875694f364f2 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 30 Jan 2008 14:55:14 -0600 Subject: 85xx: Add the concept of CFG_CCSRBAR_PHYS When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala diff --git a/board/atum8548/tlb.c b/board/atum8548/tlb.c index bb6ce76..1ef4de4 100644 --- a/board/atum8548/tlb.c +++ b/board/atum8548/tlb.c @@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe210_0000 1M PCI2 IO * 0xe300_0000 1M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), }; diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index 3eaff01..4fe2862 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c index 92f759b..c5434a0 100644 --- a/board/freescale/mpc8541cds/tlb.c +++ b/board/freescale/mpc8541cds/tlb.c @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c index 34cfb38..61fc609 100644 --- a/board/freescale/mpc8544ds/tlb.c +++ b/board/freescale/mpc8544ds/tlb.c @@ -75,7 +75,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe100_0000 255M PCI IO range */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index b21f71b..ab99af7 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe210_0000 1M PCI2 IO * 0xe300_0000 1M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c index 92f759b..c5434a0 100644 --- a/board/freescale/mpc8555cds/tlb.c +++ b/board/freescale/mpc8555cds/tlb.c @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 3eaff01..4fe2862 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c index 225fc94..a866c52 100644 --- a/board/freescale/mpc8568mds/tlb.c +++ b/board/freescale/mpc8568mds/tlb.c @@ -74,7 +74,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 8M PCI1 IO * 0xe280_0000 8M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_64M, 1), diff --git a/board/mpc8540eval/tlb.c b/board/mpc8540eval/tlb.c index f041236..1003bf6 100644 --- a/board/mpc8540eval/tlb.c +++ b/board/mpc8540eval/tlb.c @@ -27,7 +27,7 @@ #include struct fsl_e_tlb_entry tlb_table[] = { - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index 5d87537..a7f3813 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index 5d87537..a7f3813 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 8d6625e..6314005 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -81,7 +81,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe0000000 1M CCSRBAR * 0xe2000000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c index 155ff64..d073399 100644 --- a/board/sbc8560/tlb.c +++ b/board/sbc8560/tlb.c @@ -28,7 +28,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB for CCSRBAR (IMMR) */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), diff --git a/board/stxgp3/tlb.c b/board/stxgp3/tlb.c index 529f230..d410416 100644 --- a/board/stxgp3/tlb.c +++ b/board/stxgp3/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/stxssa/tlb.c b/board/stxssa/tlb.c index 46b1440..86cbd11 100644 --- a/board/stxssa/tlb.c +++ b/board/stxssa/tlb.c @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/tqm85xx/tlb.c b/board/tqm85xx/tlb.c index a178cfe..ad26cae 100644 --- a/board/tqm85xx/tlb.c +++ b/board/tqm85xx/tlb.c @@ -91,7 +91,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c0ff1d5..5f02e0e 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -127,12 +127,12 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { - set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR, + set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 0, BOOKE_PAGESZ_4K, 0); /* set up CCSR if we want it moved */ -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) { u32 temp; @@ -141,7 +141,7 @@ void cpu_init_early_f(void) 1, 1, BOOKE_PAGESZ_4K, 0); temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); - out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12); + out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12); temp = in_be32((volatile u32 *)CFG_CCSRBAR); } diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index c14376e..0d644da 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -96,6 +96,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5ea7b25..85934d7 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -100,6 +100,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 174215c..77eea73 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -83,6 +83,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 7334088..f1a86e6 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -82,6 +82,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index a894209..c83d9e2 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -98,6 +98,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a3db9f4..2d44df4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -96,6 +96,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 93877ae..fa0f7b3 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -82,6 +82,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 08884b3..e30302c 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -95,6 +95,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a12d193..7bb20e5 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -90,6 +90,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 819bee7..bd058fc 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -92,6 +92,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 8902f42..38a26dc 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -94,6 +94,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 2bbfe9a..946b3c2 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -99,6 +99,7 @@ #else #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ #endif +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 21e8baf..fca5f74 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -89,6 +89,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 516203a..49a7234 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -87,6 +87,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index f9ede5f..81a1e07 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -93,6 +93,7 @@ #else #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ #endif +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 047e1cf..fc5d0cc 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -114,6 +114,7 @@ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index e09dd71..15f690a 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -127,6 +127,7 @@ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -- cgit v0.10.2 From ec2b74ffd36f02c6123725e7c2533dd2deaf4b64 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 16:48:33 -0600 Subject: 85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala diff --git a/common/Makefile b/common/Makefile index 1c81fcf..382dd01 100644 --- a/common/Makefile +++ b/common/Makefile @@ -140,6 +140,7 @@ COBJS-y += crc16.o COBJS-y += xyzModem.o COBJS-y += cmd_mac.o COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o +COBJS-$(CONFIG_MP) += cmd_mp.o COBJS := $(COBJS-y) SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/common/cmd_mp.c b/common/cmd_mp.c new file mode 100644 index 0000000..d96e6a3 --- /dev/null +++ b/common/cmd_mp.c @@ -0,0 +1,96 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +int +cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long cpuid, val = 0; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + cpuid = simple_strtoul(argv[1], NULL, 10); + if (cpuid >= CONFIG_NR_CPUS) { + printf ("Core num: %d is out of range[0..%d]\n", + cpuid, CONFIG_NR_CPUS - 1); + return 1; + } + + + if (argc == 3) { + if (strncmp(argv[2], "reset", 5) == 0) { + cpu_reset(cpuid); + } else if (strncmp(argv[2], "status", 6) == 0) { + cpu_status(cpuid); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + return 0; + } + + /* 4 or greater, make sure its release */ + if (strncmp(argv[2], "release", 7) != 0) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + val = simple_strtoul(argv[3], NULL, 16); + + if (cpu_release(cpuid, val, argc - 4, argv + 4)) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return 0; +} + +#ifdef CONFIG_PPC +#define CPU_ARCH_HELP \ + " [args] : \n" \ + " pir - processor id (if writeable)\n" \ + " r3 - value for gpr 3\n" \ + " r4 - value for gpr 4\n" \ + " r6 - value for gpr 6\n" \ + " r7 - value for gpr 7\n" \ + "\n" \ + " Use '-' for any arg if you want the default value.\n" \ + " Default for r3, r4, r7 is 0, r6 is 0x65504150\n" \ + "\n" \ + " When cpu is released r5 = 0 per the ePAPR spec.\n" +#endif + +U_BOOT_CMD( + cpu, CFG_MAXARGS, 1, cpu_cmd, + "cpu - Multiprocessor CPU boot manipulation and release\n", + " reset - Reset cpu \n" + "cpu status - Status of cpu \n" + "cpu release [args] - Release cpu at with [args]\n" +#ifdef CPU_ARCH_HELP + CPU_ARCH_HELP +#endif + ); diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 2205dca..adbc585 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -29,6 +29,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o resetvec.o +SOBJS-$(CONFIG_MP) += release.o +SOBJS = $(SOBJS-y) +COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \ diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 5f02e0e..fce0c48 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -33,6 +33,7 @@ #include #include #include +#include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -328,5 +329,8 @@ int cpu_init_r(void) qe_reset(); #endif +#if defined(CONFIG_MP) + setup_mp(); +#endif return 0; } diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index a6b014c..43df1c7 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -28,6 +28,54 @@ #include extern void ft_qe_setup(void *blob); +#ifdef CONFIG_MP +#include "mp.h" +DECLARE_GLOBAL_DATA_PTR; + +void ft_fixup_cpu(void *blob, u64 memory_limit) +{ + int off; + ulong spin_tbl_addr = get_spin_addr(); + u32 bootpg, id = get_my_id(); + + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + + if (reg) { + if (*reg == id) { + fdt_setprop_string(blob, off, "status", "okay"); + } else { + u32 val = *reg * 24 + spin_tbl_addr; + val = cpu_to_fdt32(val); + fdt_setprop_string(blob, off, "status", + "disabled"); + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); + } + } else { + printf ("cpu NULL\n"); + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + /* Reserve the boot page so OSes dont use it */ + if ((u64)bootpg < memory_limit) { + off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); + if (off < 0) + printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); + } +} +#endif void ft_cpu_setup(void *blob, bd_t *bd) { @@ -62,4 +110,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + +#ifdef CONFIG_MP + ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); +#endif } diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c new file mode 100644 index 0000000..aa91cea --- /dev/null +++ b/cpu/mpc85xx/mp.c @@ -0,0 +1,190 @@ +/* + * Copyright 2008 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "mp.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define BOOT_ENTRY_ADDR 0 +#define BOOT_ENTRY_PIR 1 +#define BOOT_ENTRY_R3 2 +#define BOOT_ENTRY_R4 3 +#define BOOT_ENTRY_R6 4 +#define BOOT_ENTRY_R7 5 +#define NUM_BOOT_ENTRY 6 + +u32 get_my_id() +{ + return mfspr(SPRN_PIR); +} + +int cpu_reset(int nr) +{ + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + out_be32(&pic->pir, 1 << nr); + (void)in_be32(&pic->pir); + out_be32(&pic->pir, 0x0); + + return 0; +} + +int cpu_status(int nr) +{ + u32 *table, id = get_my_id(); + + if (nr == id) { + table = (u32 *)get_spin_addr(); + printf("table base @ 0x%08x\n", table); + } else { + table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; + printf("Running on cpu %d\n", id); + printf("\n"); + printf("table @ 0x%08x:\n", table); + printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR]); + printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); + printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3]); + printf(" r4 - 0x%08x\n", table[BOOT_ENTRY_R4]); + printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6]); + printf(" r7 - 0x%08x\n", table[BOOT_ENTRY_R7]); + } + + return 0; +} + +int cpu_release(int nr, unsigned long boot_addr, int argc, char *argv[]) +{ + u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; + + if (nr == get_my_id()) { + printf("Invalid to release the boot core.\n\n"); + return 1; + } + + if (argc != 5) { + printf("Invalid number of arguments to release.\n\n"); + return 1; + } + + /* handle pir, r3, r4, r6, r7 */ + for (i = 0; i < 5; i++) { + if (argv[i][0] != '-') { + val = simple_strtoul(argv[i], NULL, 16); + table[i+BOOT_ENTRY_PIR] = val; + } + } + + table[BOOT_ENTRY_ADDR] = boot_addr; + + return 0; +} + +ulong get_spin_addr(void) +{ + extern ulong __secondary_start_page; + extern ulong __spin_table; + + ulong addr = + (ulong)&__spin_table - (ulong)&__secondary_start_page; + addr += 0xfffff000; + + return addr; +} + +static void pq3_mp_up(unsigned long bootpg) +{ + u32 up, cpu_up_mask, whoami; + u32 *table = (u32 *)get_spin_addr(); + volatile u32 bpcr; + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + u32 devdisr; + int timeout = 10; + + whoami = in_be32(&pic->whoami); + out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); + + /* disable time base at the platform */ + devdisr = in_be32(&gur->devdisr); + if (whoami) + devdisr |= MPC85xx_DEVDISR_TB0; + else + devdisr |= MPC85xx_DEVDISR_TB1; + out_be32(&gur->devdisr, devdisr); + + /* release the hounds */ + up = ((1 << CONFIG_NR_CPUS) - 1); + bpcr = in_be32(&ecm->eebpcr); + bpcr |= (up << 24); + out_be32(&ecm->eebpcr, bpcr); + asm("sync; isync; msync"); + + cpu_up_mask = 1 << whoami; + /* wait for everyone */ + while (timeout) { + int i; + for (i = 1; i < CONFIG_NR_CPUS; i++) { + if (table[i * NUM_BOOT_ENTRY]) + cpu_up_mask |= (1 << i); + }; + + if ((cpu_up_mask & up) == up) + break; + + udelay(100); + timeout--; + } + + /* enable time base at the platform */ + if (whoami) + devdisr |= MPC85xx_DEVDISR_TB1; + else + devdisr |= MPC85xx_DEVDISR_TB0; + out_be32(&gur->devdisr, devdisr); + mtspr(SPRN_TBWU, 0); + mtspr(SPRN_TBWL, 0); + + devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); + out_be32(&gur->devdisr, devdisr); +} + +void setup_mp(void) +{ + extern ulong __secondary_start_page; + ulong fixup = (ulong)&__secondary_start_page; + u32 bootpg; + + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + + memcpy((void *)bootpg, (void *)fixup, 4096); + flush_cache(bootpg, 4096); + + pq3_mp_up(bootpg); +} diff --git a/cpu/mpc85xx/mp.h b/cpu/mpc85xx/mp.h new file mode 100644 index 0000000..d9fbb82 --- /dev/null +++ b/cpu/mpc85xx/mp.h @@ -0,0 +1,8 @@ +#ifndef __MPC85XX_MP_H_ +#define __MPC85XX_MP_H_ + +ulong get_spin_addr(void); +void setup_mp(void); +u32 get_my_id(void); + +#endif diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S new file mode 100644 index 0000000..fe1775c --- /dev/null +++ b/cpu/mpc85xx/release.S @@ -0,0 +1,148 @@ +#include +#include +#include + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include +#include + +#include +#include + +/* To boot secondary cpus, we need a place for them to start up. + * Normally, they start at 0xfffffffc, but that's usually the + * firmware, and we don't want to have to run the firmware again. + * Instead, the primary cpu will set the BPTR to point here to + * this page. We then set up the core, and head to + * start_secondary. Note that this means that the code below + * must never exceed 1023 instructions (the branch at the end + * would then be the 1024th). + */ + .globl __secondary_start_page + .align 12 +__secondary_start_page: +/* First do some preliminary setup */ + lis r3, HID0_EMCP@h /* enable machine check */ + ori r3,r3,HID0_TBEN@l /* enable Timebase */ +#ifdef CONFIG_PHYS_64BIT + ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ +#endif + mtspr SPRN_HID0,r3 + + li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mtspr SPRN_HID1,r3 + + /* Enable branch prediction */ + li r3,0x201 + mtspr SPRN_BUCSR,r3 + + /* Enable/invalidate the I-Cache */ + mfspr r0,SPRN_L1CSR1 + ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE) + mtspr SPRN_L1CSR1,r0 + isync + + /* Enable/invalidate the D-Cache */ + mfspr r0,SPRN_L1CSR0 + ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE) + msync + isync + mtspr SPRN_L1CSR0,r0 + isync + +#define toreset(x) (x - __secondary_start_page + 0xfffff000) + + /* get our PIR to figure out our table entry */ + lis r3,toreset(__spin_table)@h + ori r3,r3,toreset(__spin_table)@l + + /* r9 has the base address for the entry */ + mfspr r0,SPRN_PIR + mr r4,r0 + slwi r8,r4,4 + slwi r9,r4,3 + add r8,r8,r9 + add r9,r3,r8 + +#define EPAPR_MAGIC (0x65504150) +#define ENTRY_ADDR 0 +#define ENTRY_PIR 4 +#define ENTRY_R3 8 +#define ENTRY_R4 12 +#define ENTRY_R6 16 +#define ENTRY_R7 20 + + /* setup the entry */ + li r4,0 + li r8,1 + lis r6,EPAPR_MAGIC@h + ori r6,r6,EPAPR_MAGIC@l + stw r0,ENTRY_PIR(r9) + stw r8,ENTRY_ADDR(r9) + stw r4,ENTRY_R3(r9) + stw r4,ENTRY_R4(r9) + stw r6,ENTRY_R6(r9) + stw r4,ENTRY_R7(r9) + + /* spin waiting for addr */ +1: lwz r4,ENTRY_ADDR(r9) + andi. r11,r4,1 + bne 1b + + /* setup branch addr */ + mtctr r4 + + /* mark the entry as released */ + li r8,3 + stw r8,ENTRY_ADDR(r9) + + /* mask by ~64M to setup our tlb we will jump to */ + rlwinm r8,r4,0,0,5 + + /* setup r3, r5, r6, r7 */ + lwz r3,ENTRY_R3(r9) + lwz r4,ENTRY_R4(r9) + li r5,0 + lwz r6,ENTRY_R6(r9) + lwz r7,ENTRY_R7(r9) + + /* load up the pir */ + lwz r0,ENTRY_PIR(r9) + mtspr SPRN_PIR,r0 + mfspr r0,SPRN_PIR + stw r0,ENTRY_PIR(r9) + +/* + * Coming here, we know the cpu has one TLB mapping in TLB1[0] + * which maps 0xfffff000-0xffffffff one-to-one. We set up a + * second mapping that maps addr 1:1 for 64M, and then we jump to + * addr + */ + lis r9,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h + mtspr SPRN_MAS0,r9 + lis r9,(MAS1_VALID|MAS1_IPROT)@h + ori r9,r9,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l + mtspr SPRN_MAS1,r9 + /* WIMGE = 0b00000 for now */ + mtspr SPRN_MAS2,r8 + ori r8,r8,(MAS3_SX|MAS3_SW|MAS3_SR) + mtspr SPRN_MAS3,r8 + tlbwe + +/* Now we have another mapping for this page, so we jump to that + * mapping + */ + bctr + + .align 3 + .globl __spin_table +__spin_table: + .space CONFIG_NR_CPUS*24 + + /* Fill in the empty space. The actual reset vector is + * the last word of the page */ +__secondary_start_code_end: + .space 4092 - (__secondary_start_code_end - __secondary_start_page) +__secondary_reset_vector: + b __secondary_start_page diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index d769d70..712a078 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1578,7 +1578,11 @@ typedef struct ccsr_gur { #define MPC85xx_DEVDISR_RMSG 0x00040000 #define MPC85xx_DEVDISR_DDR 0x00010000 #define MPC85xx_DEVDISR_CPU 0x00008000 +#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU #define MPC85xx_DEVDISR_TB 0x00004000 +#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB +#define MPC85xx_DEVDISR_CPU1 0x00002000 +#define MPC85xx_DEVDISR_TB1 0x00001000 #define MPC85xx_DEVDISR_DMA 0x00000400 #define MPC85xx_DEVDISR_TSEC1 0x00000080 #define MPC85xx_DEVDISR_TSEC2 0x00000040 diff --git a/include/common.h b/include/common.h index e03ead1..f496073 100644 --- a/include/common.h +++ b/include/common.h @@ -669,4 +669,11 @@ void inline show_boot_progress (int val); #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +/* Multicore arch functions */ +#ifdef CONFIG_MP +int cpu_status(int nr); +int cpu_reset(int nr); +int cpu_release(int nr, unsigned long boot_addr, int argc, char *argv[]); +#endif + #endif /* __COMMON_H_ */ -- cgit v0.10.2 From 7aff0c051ad0613171cf2b9941ee48675c62e7cd Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 14 Feb 2008 11:04:23 -0600 Subject: 85xx: Added support for multicore boot mechanism Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 43df1c7..dadda90 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -77,6 +77,55 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif +#ifdef CONFIG_MP +#include "mp.h" +DECLARE_GLOBAL_DATA_PTR; + +void ft_fixup_cpu(void *blob, u64 memory_limit) +{ + int off; + ulong spin_tbl_addr = get_spin_addr(); + u32 bootpg, id = get_my_id(); + + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + + if (reg) { + if (*reg == id) { + fdt_setprop_string(blob, off, "status", "okay"); + } else { + u32 val = *reg * 24 + spin_tbl_addr; + val = cpu_to_fdt32(val); + fdt_setprop_string(blob, off, "status", + "disabled"); + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); + } + } else { + printf ("cpu NULL\n"); + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + /* Reserve the boot page so OSes dont use it */ + if ((u64)bootpg < memory_limit) { + off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); + if (off < 0) + printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); + } +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ -- cgit v0.10.2 From b83eef440cf3cef816172ccbb5897ccd8e403cf3 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 6 Feb 2008 01:12:57 -0600 Subject: Add the Freescale PCI device IDs Signed-off-by: Andy Fleming diff --git a/include/pci_ids.h b/include/pci_ids.h index 3b10452..b0c1957 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2050,3 +2050,26 @@ #define PCI_DEVICE_ID_MICROGATE_USC 0x0010 #define PCI_DEVICE_ID_MICROGATE_SCC 0x0020 #define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 + +#define PCI_VENDOR_ID_FREESCALE 0x1957 +#define PCI_DEVICE_ID_MPC8548E 0x0012 +#define PCI_DEVICE_ID_MPC8548 0x0013 +#define PCI_DEVICE_ID_MPC8543E 0x0014 +#define PCI_DEVICE_ID_MPC8543 0x0015 +#define PCI_DEVICE_ID_MPC8547E 0x0018 +#define PCI_DEVICE_ID_MPC8545E 0x0019 +#define PCI_DEVICE_ID_MPC8545 0x001a +#define PCI_DEVICE_ID_MPC8568E 0x0020 +#define PCI_DEVICE_ID_MPC8568 0x0021 +#define PCI_DEVICE_ID_MPC8567E 0x0022 +#define PCI_DEVICE_ID_MPC8567 0x0023 +#define PCI_DEVICE_ID_MPC8533E 0x0030 +#define PCI_DEVICE_ID_MPC8533 0x0031 +#define PCI_DEVICE_ID_MPC8544E 0x0032 +#define PCI_DEVICE_ID_MPC8544 0x0033 +#define PCI_DEVICE_ID_MPC8572E 0x0040 +#define PCI_DEVICE_ID_MPC8572 0x0041 +#define PCI_DEVICE_ID_MPC8641 0x7010 +#define PCI_DEVICE_ID_MPC8641D 0x7011 +#define PCI_DEVICE_ID_MPC8610 0x7018 + -- cgit v0.10.2 From 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 6 Feb 2008 01:19:40 -0600 Subject: Update SVR numbers to expand support FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index ac8b018..0ac004d 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2007 Freescale Semiconductor, Inc. + * Copyright 2004,2007,2008 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -30,6 +30,39 @@ #include #include +struct cpu_type { + char name[15]; + u32 soc_ver; +}; + +#define CPU_TYPE_ENTRY(x) {#x, SVR_##x} + +struct cpu_type cpu_type_list [] = { + CPU_TYPE_ENTRY(8533), + CPU_TYPE_ENTRY(8533_E), + CPU_TYPE_ENTRY(8540), + CPU_TYPE_ENTRY(8541), + CPU_TYPE_ENTRY(8541_E), + CPU_TYPE_ENTRY(8543), + CPU_TYPE_ENTRY(8543_E), + CPU_TYPE_ENTRY(8544), + CPU_TYPE_ENTRY(8544_E), + CPU_TYPE_ENTRY(8545), + CPU_TYPE_ENTRY(8545_E), + CPU_TYPE_ENTRY(8547_E), + CPU_TYPE_ENTRY(8548), + CPU_TYPE_ENTRY(8548_E), + CPU_TYPE_ENTRY(8555), + CPU_TYPE_ENTRY(8555_E), + CPU_TYPE_ENTRY(8560), + CPU_TYPE_ENTRY(8567), + CPU_TYPE_ENTRY(8567_E), + CPU_TYPE_ENTRY(8568), + CPU_TYPE_ENTRY(8568_E), + CPU_TYPE_ENTRY(8572), + CPU_TYPE_ENTRY(8572_E), +}; + int checkcpu (void) { sys_info_t sysinfo; @@ -39,47 +72,26 @@ int checkcpu (void) uint fam; uint ver; uint major, minor; + int i; u32 ddr_ratio; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); svr = get_svr(); - ver = SVR_VER(svr); + ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); puts("CPU: "); - switch (ver) { - case SVR_8540: - puts("8540"); - break; - case SVR_8541: - puts("8541"); - break; - case SVR_8555: - puts("8555"); - break; - case SVR_8560: - puts("8560"); - break; - case SVR_8548: - puts("8548"); - break; - case SVR_8548_E: - puts("8548_E"); - break; - case SVR_8544: - puts("8544"); - break; - case SVR_8544_E: - puts("8544_E"); - break; - case SVR_8568_E: - puts("8568_E"); - break; - default: + + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if (cpu_type_list[i].soc_ver == ver) { + puts(cpu_type_list[i].name); + break; + } + + if (i == ARRAY_SIZE(cpu_type_list)) puts("Unknown"); - break; - } + printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); @@ -142,10 +154,9 @@ int checkcpu (void) printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); } - if (ver == SVR_8560) { - printf("CPM: %lu Mhz\n", - sysinfo.freqSystemBus / 1000000); - } +#ifdef CONFIG_CPM2 + printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); +#endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index bf4e651..3c74764 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -69,7 +69,7 @@ checkcpu(void) printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); svr = get_svr(); - ver = SVR_VER(svr); + ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index b7a5b28..544cc01 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -879,22 +879,42 @@ #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ +/* Some parts define SVR[0:23] as the SOC version */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ + /* - * SVR_VER() Version Values + * SVR_SOC_VER() Version Values */ -#define SVR_8540 0x8030 -#define SVR_8560 0x8070 -#define SVR_8555 0x8079 -#define SVR_8541 0x807A -#define SVR_8544 0x8034 -#define SVR_8544_E 0x803C -#define SVR_8548 0x8031 -#define SVR_8548_E 0x8039 -#define SVR_8610 0x80A0 -#define SVR_8641 0x8090 -#define SVR_8568_E 0x807D +#define SVR_8533 0x803400 +#define SVR_8533_E 0x803C00 +#define SVR_8540 0x803000 +#define SVR_8541 0x807200 +#define SVR_8541_E 0x807A00 +#define SVR_8543 0x803200 +#define SVR_8543_E 0x803A00 +#define SVR_8544 0x803401 +#define SVR_8544_E 0x803C01 +#define SVR_8545 0x803102 +#define SVR_8545_E 0x803902 +#define SVR_8547_E 0x803901 +#define SVR_8548 0x803100 +#define SVR_8548_E 0x803900 +#define SVR_8555 0x807100 +#define SVR_8555_E 0x807900 +#define SVR_8560 0x807000 +#define SVR_8567 0x807600 +#define SVR_8567_E 0x807E00 +#define SVR_8568 0x807500 +#define SVR_8568_E 0x807D00 +#define SVR_8572 0x80E000 +#define SVR_8572_E 0x80E800 + +#define SVR_8610 0x80A000 +#define SVR_8641 0x809000 +#define SVR_8641D 0x809001 + /* I am just adding a single entry for 8260 boards. I think we may be -- cgit v0.10.2 From 591933ca6eabc440e6ed6967233aaf56fce464a3 Mon Sep 17 00:00:00 2001 From: James Yang Date: Fri, 8 Feb 2008 16:44:53 -0600 Subject: 85xx: get_tbclk() speed up and rounding fix Speed up get_tbclk() by referencing pre-computed bus clock frequency value from global data instead of sys_info_t. Fix rounding of result to nearest; previously it was rounding upwards. Signed-off-by: James Yang Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 0ac004d..4aac599 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -30,6 +30,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + struct cpu_type { char name[15]; u32 soc_ver; @@ -201,11 +203,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { - - sys_info_t sys_info; - - get_sys_info(&sys_info); - return ((sys_info.freqSystemBus + 7L) / 8L); + return (gd->bus_clk + 4UL)/8UL; } -- cgit v0.10.2 From e9ea679918fbc9a53fa2f2a904aac874ea736036 Mon Sep 17 00:00:00 2001 From: James Yang Date: Fri, 8 Feb 2008 16:46:27 -0600 Subject: 85xx: Show DDR memory data rate in addition to the memory clock frequency. Show the DDR memory data rate in addition to the memory clock frequency. For DDR/DDR2 memories the memory data rate is 2x the memory clock. Signed-off-by: James Yang Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 4aac599..dcd8817 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -122,13 +122,16 @@ int checkcpu (void) ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; switch (ddr_ratio) { case 0x0: - printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000); + printf(" DDR:%4lu MHz (%lu MT/s data rate), ", + sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000); break; case 0x7: - printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000); + printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", + sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000); break; default: - printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000); + printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", + sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000); break; } -- cgit v0.10.2 From a3e77fa5359b3f9f59e4e946b46d57a53057cc85 Mon Sep 17 00:00:00 2001 From: James Yang Date: Fri, 8 Feb 2008 18:05:08 -0600 Subject: 85xx: Speed up get_ddr_freq() and get_bus_freq() get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were called. However, get_sys_info() recalculates extraneous information when called each time. Have get_ddr_freq() and get_bus_freq() return memoized values from global_data instead. Signed-off-by: James Yang Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 952f30c..d90d397 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -48,6 +48,8 @@ void get_sys_info (sys_info_t * sysInfo) * overflow for processor speeds above 2GHz */ half_freqSystemBus = sysInfo->freqSystemBus/2; sysInfo->freqProcessor = e500_ratio*half_freqSystemBus; + + /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ sysInfo->freqDDRBus = sysInfo->freqSystemBus; #ifdef CONFIG_DDR_CLK_FREQ @@ -75,6 +77,7 @@ int get_clocks (void) get_sys_info (&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; + gd->mem_clk = sys_info.freqDDRBus; gd->i2c1_clk = sys_info.freqSystemBus; gd->i2c2_clk = sys_info.freqSystemBus; @@ -96,14 +99,7 @@ int get_clocks (void) *********************************************/ ulong get_bus_freq (ulong dummy) { - ulong val; - - sys_info_t sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqSystemBus; - - return val; + return gd->bus_clk; } /******************************************** @@ -112,12 +108,5 @@ ulong get_bus_freq (ulong dummy) *********************************************/ ulong get_ddr_freq (ulong dummy) { - ulong val; - - sys_info_t sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqDDRBus; - - return val; + return gd->mem_clk; } diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index ff6624a..b43dba3 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -52,9 +52,7 @@ typedef struct global_data { unsigned long scc_clk; unsigned long brg_clk; #endif -#if defined(CONFIG_MPC7448HPC2) unsigned long mem_clk; -#endif #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -- cgit v0.10.2 From 5893b3d0a4084f87a06a5d3dc03db91206818941 Mon Sep 17 00:00:00 2001 From: James Yang Date: Tue, 12 Feb 2008 16:35:07 -0600 Subject: 85xx: Expand CCSR space with more DDR controller registers. Signed-off-by: James Yang Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 712a078..3506aec 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -57,7 +57,7 @@ typedef struct ccsr_local_ecm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[780]; + char res20[780]; // XXX: LAW 8, LAW9 for 8572 uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ char res21[12]; uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ @@ -86,7 +86,12 @@ typedef struct ccsr_ddr { uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ - char res5[112]; + char res4a[48]; + uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */ + uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */ + uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ + uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ + char res5[48]; uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ @@ -103,7 +108,17 @@ typedef struct ccsr_ddr { char res7[20]; uint init_address; /* 0x2148 - DDR training initialization address */ uint init_ext_address; /* 0x214C - DDR training initialization extended address */ - char res8_1[2728]; + char res8_1[16]; + uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ + uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ + char reg8_1a[8]; + uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/ + uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/ + uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/ + uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ + uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ + uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ + char res8_1b[2672]; uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ char res8_2[512]; @@ -217,7 +232,7 @@ typedef struct ccsr_lbc { char res7[12]; uint lbcr; /* 0x50d0 - LBC Configuration Register */ uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ - char res8[12072]; + char res8[3880]; } ccsr_lbc_t; /* @@ -1628,6 +1643,8 @@ typedef struct ccsr_gur { #define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET) #define CFG_MPC85xx_DDR_OFFSET (0x2000) #define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET) +#define CFG_MPC85xx_DDR2_OFFSET (0x6000) +#define CFG_MPC85xx_DDR2_ADDR (CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET) #define CFG_MPC85xx_LBC_OFFSET (0x5000) #define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET) #define CFG_MPC85xx_PCIX_OFFSET (0x8000) -- cgit v0.10.2 From a5af4b358a7caa9c0aa374d4d894bf762ec37669 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 27 Feb 2008 22:00:27 -0600 Subject: 85xx: Fix merge duplication ft_fixup_cpu() got duplicated in some merge snafu. Remove the duplicate. Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index dadda90..43df1c7 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -77,55 +77,6 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif -#ifdef CONFIG_MP -#include "mp.h" -DECLARE_GLOBAL_DATA_PTR; - -void ft_fixup_cpu(void *blob, u64 memory_limit) -{ - int off; - ulong spin_tbl_addr = get_spin_addr(); - u32 bootpg, id = get_my_id(); - - /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ - if ((u64)gd->ram_size > 0xfffff000) - bootpg = 0xfffff000; - else - bootpg = gd->ram_size - 4096; - - off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); - while (off != -FDT_ERR_NOTFOUND) { - u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); - - if (reg) { - if (*reg == id) { - fdt_setprop_string(blob, off, "status", "okay"); - } else { - u32 val = *reg * 24 + spin_tbl_addr; - val = cpu_to_fdt32(val); - fdt_setprop_string(blob, off, "status", - "disabled"); - fdt_setprop_string(blob, off, "enable-method", - "spin-table"); - fdt_setprop(blob, off, "cpu-release-addr", - &val, sizeof(val)); - } - } else { - printf ("cpu NULL\n"); - } - off = fdt_node_offset_by_prop_value(blob, off, - "device_type", "cpu", 4); - } - - /* Reserve the boot page so OSes dont use it */ - if ((u64)bootpg < memory_limit) { - off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); - if (off < 0) - printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); - } -} -#endif - void ft_cpu_setup(void *blob, bd_t *bd) { #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ -- cgit v0.10.2 From 25eedb2c1958a13110c7de1fc809b624053cc69c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 19 Mar 2008 15:02:07 -0500 Subject: FSL: Clean up board/freescale/common/Makefile Each file that can be built here now follows some CONFIG_ option so that they are appropriately built or not, as needed. And CONFIG_ defines were added to various board config files to make sure that happens. The other board/freescale/*/Makefiles no longer need to reach up and over into ../common to build their individually needed files any more. Boards that are CDS specific were renamed with cds_ prefix. Signed-off-by: Jon Loeliger diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 6665e7f..6340b41 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -29,10 +29,18 @@ endif LIB = $(obj)lib$(VENDOR).a -COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o -COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o +COBJS-${CONFIG_FSL_CADMUS} += cadmus.o +COBJS-${CONFIG_FSL_CDS_EEPROM} += cds_eeprom.o +COBJS-${CONFIG_FSL_VIA} += cds_via.o COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o COBJS-${CONFIG_FSL_PIXIS} += pixis.o +COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o +COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o + +COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o +COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o +COBJS-${CONFIG_MPC8555CDS} += cds_pci_ft.o + SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/common/cds_eeprom.c b/board/freescale/common/cds_eeprom.c new file mode 100644 index 0000000..5034e0c --- /dev/null +++ b/board/freescale/common/cds_eeprom.c @@ -0,0 +1,60 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +#include "eeprom.h" + + +typedef struct { + char idee_pcbid[4]; /* "CCID" for CDC v1.X */ + u8 idee_major; + u8 idee_minor; + char idee_serial[10]; + char idee_errata[2]; + char idee_date[8]; /* yyyymmdd */ + /* The rest of the EEPROM space is reserved */ +} id_eeprom_t; + + +unsigned int +get_cpu_board_revision(void) +{ + uint major = 0; + uint minor = 0; + + id_eeprom_t id_eeprom; + + i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, + (uchar *) &id_eeprom, sizeof(id_eeprom)); + + major = id_eeprom.idee_major; + minor = id_eeprom.idee_minor; + + if (major == 0xff && minor == 0xff) { + major = minor = 0; + } + + return MPC85XX_CPU_BOARD_REV(major,minor); +} diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c new file mode 100644 index 0000000..6f221af --- /dev/null +++ b/board/freescale/common/cds_pci_ft.c @@ -0,0 +1,72 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "cadmus.h" + +#if defined(CONFIG_OF_BOARD_SETUP) +static void cds_pci_fixup(void *blob) +{ + int node, tmp[2]; + const char *path; + int len, slot, i; + u32 *map = NULL; + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + node = fdt_path_offset(blob, path); + if (node >= 0) { + map = fdt_getprop_w(blob, node, "interrupt-map", &len); + } + } + } + + if (map) { + len /= sizeof(u32); + + slot = get_pci_slot(); + + for (i=0;i +#include + +/* Config the VIA chip */ +void mpc85xx_config_via(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pci_dev_t bridge; + unsigned int cmdstat; + + /* Enable USB and IDE functions */ + pci_hose_write_config_byte(hose, dev, 0x48, 0x08); + + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + + /* + * Force the backplane P2P bridge to have a window + * open from 0x00000000-0x00001fff in PCI I/O space. + * This allows legacy I/O (i8259, etc) on the VIA + * southbridge to be accessed. + */ + bridge = PCI_BDF(0,BRIDGE_ID,0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); + pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); + pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); +} + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + /* + * Since the P2P window was forced to cover the fixed + * legacy I/O addresses, it is necessary to manually + * place the base addresses for the IDE and USB functions + * within this window. + */ + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); +} + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); +} + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); +} + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); +} + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); +} diff --git a/board/freescale/common/eeprom.c b/board/freescale/common/eeprom.c deleted file mode 100644 index 5034e0c..0000000 --- a/board/freescale/common/eeprom.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -#include "eeprom.h" - - -typedef struct { - char idee_pcbid[4]; /* "CCID" for CDC v1.X */ - u8 idee_major; - u8 idee_minor; - char idee_serial[10]; - char idee_errata[2]; - char idee_date[8]; /* yyyymmdd */ - /* The rest of the EEPROM space is reserved */ -} id_eeprom_t; - - -unsigned int -get_cpu_board_revision(void) -{ - uint major = 0; - uint minor = 0; - - id_eeprom_t id_eeprom; - - i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, - (uchar *) &id_eeprom, sizeof(id_eeprom)); - - major = id_eeprom.idee_major; - minor = id_eeprom.idee_minor; - - if (major == 0xff && minor == 0xff) { - major = minor = 0; - } - - return MPC85XX_CPU_BOARD_REV(major,minor); -} diff --git a/board/freescale/common/ft_board.c b/board/freescale/common/ft_board.c deleted file mode 100644 index 6f221af..0000000 --- a/board/freescale/common/ft_board.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "cadmus.h" - -#if defined(CONFIG_OF_BOARD_SETUP) -static void cds_pci_fixup(void *blob) -{ - int node, tmp[2]; - const char *path; - int len, slot, i; - u32 *map = NULL; - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - node = fdt_path_offset(blob, path); - if (node >= 0) { - map = fdt_getprop_w(blob, node, "interrupt-map", &len); - } - } - } - - if (map) { - len /= sizeof(u32); - - slot = get_pci_slot(); - - for (i=0;i -#include - -/* Config the VIA chip */ -void mpc85xx_config_via(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pci_dev_t bridge; - unsigned int cmdstat; - - /* Enable USB and IDE functions */ - pci_hose_write_config_byte(hose, dev, 0x48, 0x08); - - pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); - cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; - pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - - /* - * Force the backplane P2P bridge to have a window - * open from 0x00000000-0x00001fff in PCI I/O space. - * This allows legacy I/O (i8259, etc) on the VIA - * southbridge to be accessed. - */ - bridge = PCI_BDF(0,BRIDGE_ID,0); - pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); - pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); - pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); - pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); -} - -/* Function 1, IDE */ -void mpc85xx_config_via_usbide(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pciauto_config_device(hose, dev); - /* - * Since the P2P window was forced to cover the fixed - * legacy I/O addresses, it is necessary to manually - * place the base addresses for the IDE and USB functions - * within this window. - */ - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); -} - -/* Function 2, USB ports 0-1 */ -void mpc85xx_config_via_usb(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pciauto_config_device(hose, dev); - - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); -} - -/* Function 3, USB ports 2-3 */ -void mpc85xx_config_via_usb2(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pciauto_config_device(hose, dev); - - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); -} - -/* Function 5, Power Management */ -void mpc85xx_config_via_power(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pciauto_config_device(hose, dev); - - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); -} - -/* Function 6, AC97 Interface */ -void mpc85xx_config_via_ac97(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pciauto_config_device(hose, dev); - - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); -} diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile index d1a585a..3ae2e97 100644 --- a/board/freescale/mpc8541cds/Makefile +++ b/board/freescale/mpc8541cds/Makefile @@ -23,21 +23,16 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o \ - ../common/cadmus.o \ - ../common/eeprom.o \ - ../common/ft_board.o \ - ../common/via.o +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile index d1a585a..3ae2e97 100644 --- a/board/freescale/mpc8548cds/Makefile +++ b/board/freescale/mpc8548cds/Makefile @@ -23,21 +23,16 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o \ - ../common/cadmus.o \ - ../common/eeprom.o \ - ../common/ft_board.o \ - ../common/via.o +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile index d1a585a..3ae2e97 100644 --- a/board/freescale/mpc8555cds/Makefile +++ b/board/freescale/mpc8555cds/Makefile @@ -23,21 +23,16 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o \ - ../common/cadmus.o \ - ../common/eeprom.o \ - ../common/ft_board.o \ - ../common/via.o +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile index d9f20f9..8294d3b 100644 --- a/board/freescale/mpc8568mds/Makefile +++ b/board/freescale/mpc8568mds/Makefile @@ -23,9 +23,6 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile index 489689e..e17a9cb 100644 --- a/board/freescale/mpc8610hpcd/Makefile +++ b/board/freescale/mpc8610hpcd/Makefile @@ -21,10 +21,6 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).a COBJS := $(BOARD).o law.o diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index f1a86e6..3f3f741 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -49,6 +49,9 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_VIA +#define CONFIG_FSL_CDS_EEPROM + /* * When initializing flash, if we cannot find the manufacturer ID, * assume this is the AMD flash associated with the CDS board. @@ -274,6 +277,8 @@ extern unsigned long get_clock_freq(void); * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ +#define CONFIG_FSL_CADMUS + #define CADMUS_BASE_ADDR 0xf8000000 #define CFG_BR3_PRELIM 0xf8000801 #define CFG_OR3_PRELIM 0xfff00ff7 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 2d44df4..fc8ad88 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -57,6 +57,9 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_VIA +#define CONFIG_FSL_CDS_EEPROM + /* * When initializing flash, if we cannot find the manufacturer ID, * assume this is the AMD flash associated with the CDS board. @@ -297,6 +300,8 @@ extern unsigned long get_clock_freq(void); * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ +#define CONFIG_FSL_CADMUS + #define CADMUS_BASE_ADDR 0xf8000000 #define CFG_BR3_PRELIM 0xf8000801 #define CFG_OR3_PRELIM 0xfff00ff7 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index fa0f7b3..500b57c 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -49,6 +49,9 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_VIA +#define CONFIG_FSL_CDS_EEPROM + /* * When initializing flash, if we cannot find the manufacturer ID, * assume this is the AMD flash associated with the CDS board. @@ -274,6 +277,8 @@ extern unsigned long get_clock_freq(void); * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ +#define CONFIG_FSL_CADMUS + #define CADMUS_BASE_ADDR 0xf8000000 #define CFG_BR3_PRELIM 0xf8000801 #define CFG_OR3_PRELIM 0xfff00ff7 -- cgit v0.10.2 From 79679d80021ab095e639e250ca472fe526da02e2 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 26 Mar 2008 08:34:25 -0500 Subject: 85xx: Update multicore boot mechanism to ePAPR v0.81 spec The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala diff --git a/common/cmd_mp.c b/common/cmd_mp.c index d96e6a3..26a57c5 100644 --- a/common/cmd_mp.c +++ b/common/cmd_mp.c @@ -26,7 +26,7 @@ int cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - unsigned long cpuid, val = 0; + unsigned long cpuid; if (argc < 3) { printf ("Usage:\n%s\n", cmdtp->usage); @@ -59,9 +59,7 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - val = simple_strtoul(argv[3], NULL, 16); - - if (cpu_release(cpuid, val, argc - 4, argv + 4)) { + if (cpu_release(cpuid, argc - 3, argv + 3)) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } @@ -71,17 +69,16 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #ifdef CONFIG_PPC #define CPU_ARCH_HELP \ - " [args] : \n" \ + " [args] : \n" \ " pir - processor id (if writeable)\n" \ " r3 - value for gpr 3\n" \ - " r4 - value for gpr 4\n" \ " r6 - value for gpr 6\n" \ - " r7 - value for gpr 7\n" \ "\n" \ " Use '-' for any arg if you want the default value.\n" \ - " Default for r3, r4, r7 is 0, r6 is 0x65504150\n" \ + " Default for r3 is and r6 is 0\n" \ "\n" \ - " When cpu is released r5 = 0 per the ePAPR spec.\n" + " When cpu is released r4 and r5 = 0.\n" \ + " r7 will contain the size of the initial mapped area\n" #endif U_BOOT_CMD( diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 43df1c7..bde6d1e 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -52,7 +52,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) if (*reg == id) { fdt_setprop_string(blob, off, "status", "okay"); } else { - u32 val = *reg * 24 + spin_tbl_addr; + u32 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; val = cpu_to_fdt32(val); fdt_setprop_string(blob, off, "status", "disabled"); diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index aa91cea..d3727b0 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -28,14 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define BOOT_ENTRY_ADDR 0 -#define BOOT_ENTRY_PIR 1 -#define BOOT_ENTRY_R3 2 -#define BOOT_ENTRY_R4 3 -#define BOOT_ENTRY_R6 4 -#define BOOT_ENTRY_R7 5 -#define NUM_BOOT_ENTRY 6 - u32 get_my_id() { return mfspr(SPRN_PIR); @@ -63,40 +55,54 @@ int cpu_status(int nr) printf("Running on cpu %d\n", id); printf("\n"); printf("table @ 0x%08x:\n", table); - printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR]); + printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); - printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3]); - printf(" r4 - 0x%08x\n", table[BOOT_ENTRY_R4]); - printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6]); - printf(" r7 - 0x%08x\n", table[BOOT_ENTRY_R7]); + printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); + printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]); } return 0; } -int cpu_release(int nr, unsigned long boot_addr, int argc, char *argv[]) +static u8 boot_entry_map[4] = { + 0, + BOOT_ENTRY_PIR, + BOOT_ENTRY_R3_LOWER, + BOOT_ENTRY_R6_LOWER, +}; + +int cpu_release(int nr, int argc, char *argv[]) { u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; + u64 boot_addr; if (nr == get_my_id()) { printf("Invalid to release the boot core.\n\n"); return 1; } - if (argc != 5) { + if (argc != 4) { printf("Invalid number of arguments to release.\n\n"); return 1; } - /* handle pir, r3, r4, r6, r7 */ - for (i = 0; i < 5; i++) { +#ifdef CFG_64BIT_STRTOUL + boot_addr = simple_strtoull(argv[0], NULL, 16); +#else + boot_addr = simple_strtoul(argv[0], NULL, 16); +#endif + + /* handle pir, r3, r6 */ + for (i = 1; i < 4; i++) { if (argv[i][0] != '-') { + u8 entry = boot_entry_map[i]; val = simple_strtoul(argv[i], NULL, 16); - table[i+BOOT_ENTRY_PIR] = val; + table[entry] = val; } } - table[BOOT_ENTRY_ADDR] = boot_addr; + table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); + table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff); return 0; } diff --git a/cpu/mpc85xx/mp.h b/cpu/mpc85xx/mp.h index d9fbb82..b762ee2 100644 --- a/cpu/mpc85xx/mp.h +++ b/cpu/mpc85xx/mp.h @@ -5,4 +5,15 @@ ulong get_spin_addr(void); void setup_mp(void); u32 get_my_id(void); +#define BOOT_ENTRY_ADDR_UPPER 0 +#define BOOT_ENTRY_ADDR_LOWER 1 +#define BOOT_ENTRY_R3_UPPER 2 +#define BOOT_ENTRY_R3_LOWER 3 +#define BOOT_ENTRY_RESV 4 +#define BOOT_ENTRY_PIR 5 +#define BOOT_ENTRY_R6_UPPER 6 +#define BOOT_ENTRY_R6_LOWER 7 +#define NUM_BOOT_ENTRY 8 +#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32)) + #endif diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index fe1775c..3b7366f 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -57,61 +57,91 @@ __secondary_start_page: lis r3,toreset(__spin_table)@h ori r3,r3,toreset(__spin_table)@l - /* r9 has the base address for the entry */ + /* r10 has the base address for the entry */ mfspr r0,SPRN_PIR mr r4,r0 - slwi r8,r4,4 - slwi r9,r4,3 - add r8,r8,r9 - add r9,r3,r8 - -#define EPAPR_MAGIC (0x65504150) -#define ENTRY_ADDR 0 -#define ENTRY_PIR 4 -#define ENTRY_R3 8 -#define ENTRY_R4 12 -#define ENTRY_R6 16 -#define ENTRY_R7 20 + slwi r8,r4,5 + add r10,r3,r8 + +#define EPAPR_MAGIC (0x45504150) +#define ENTRY_ADDR_UPPER 0 +#define ENTRY_ADDR_LOWER 4 +#define ENTRY_R3_UPPER 8 +#define ENTRY_R3_LOWER 12 +#define ENTRY_RESV 16 +#define ENTRY_PIR 20 +#define ENTRY_R6_UPPER 24 +#define ENTRY_R6_LOWER 28 +#define ENTRY_SIZE 32 /* setup the entry */ - li r4,0 + li r3,0 li r8,1 - lis r6,EPAPR_MAGIC@h - ori r6,r6,EPAPR_MAGIC@l - stw r0,ENTRY_PIR(r9) - stw r8,ENTRY_ADDR(r9) - stw r4,ENTRY_R3(r9) - stw r4,ENTRY_R4(r9) - stw r6,ENTRY_R6(r9) - stw r4,ENTRY_R7(r9) + stw r0,ENTRY_PIR(r10) + stw r3,ENTRY_ADDR_UPPER(r10) + stw r8,ENTRY_ADDR_LOWER(r10) + stw r3,ENTRY_R3_UPPER(r10) + stw r4,ENTRY_R3_LOWER(r10) + stw r3,ENTRY_R6_UPPER(r10) + stw r3,ENTRY_R6_LOWER(r10) + + /* setup mapping for AS = 1, and jump there */ + lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h + mtspr SPRN_MAS0,r11 + lis r11,(MAS1_VALID|MAS1_IPROT)@h + ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l + mtspr SPRN_MAS1,r11 + lis r11,(0xfffff000|MAS2_I)@h + ori r11,r11,(0xfffff000|MAS2_I)@l + mtspr SPRN_MAS2,r11 + lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h + ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l + mtspr SPRN_MAS3,r11 + tlbwe + + bl 1f +1: mflr r11 + addi r11,r11,28 + mfmsr r13 + ori r12,r13,MSR_IS|MSR_DS@l + + mtspr SPRN_SRR0,r11 + mtspr SPRN_SRR1,r12 + rfi /* spin waiting for addr */ -1: lwz r4,ENTRY_ADDR(r9) +2: + lwz r4,ENTRY_ADDR_LOWER(r10) andi. r11,r4,1 - bne 1b + bne 2b + + /* get the upper bits of the addr */ + lwz r11,ENTRY_ADDR_UPPER(r10) /* setup branch addr */ - mtctr r4 + mtspr SPRN_SRR0,r4 /* mark the entry as released */ li r8,3 - stw r8,ENTRY_ADDR(r9) + stw r8,ENTRY_ADDR_LOWER(r10) /* mask by ~64M to setup our tlb we will jump to */ - rlwinm r8,r4,0,0,5 + rlwinm r12,r4,0,0,5 - /* setup r3, r5, r6, r7 */ - lwz r3,ENTRY_R3(r9) - lwz r4,ENTRY_R4(r9) + /* setup r3, r4, r5, r6, r7, r8, r9 */ + lwz r3,ENTRY_R3_LOWER(r10) + li r4,0 li r5,0 - lwz r6,ENTRY_R6(r9) - lwz r7,ENTRY_R7(r9) + lwz r6,ENTRY_R6_LOWER(r10) + lis r7,(64*1024*1024)@h + li r8,0 + li r9,0 /* load up the pir */ - lwz r0,ENTRY_PIR(r9) + lwz r0,ENTRY_PIR(r10) mtspr SPRN_PIR,r0 mfspr r0,SPRN_PIR - stw r0,ENTRY_PIR(r9) + stw r0,ENTRY_PIR(r10) /* * Coming here, we know the cpu has one TLB mapping in TLB1[0] @@ -119,26 +149,30 @@ __secondary_start_page: * second mapping that maps addr 1:1 for 64M, and then we jump to * addr */ - lis r9,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h - mtspr SPRN_MAS0,r9 - lis r9,(MAS1_VALID|MAS1_IPROT)@h - ori r9,r9,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l - mtspr SPRN_MAS1,r9 + lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h + mtspr SPRN_MAS0,r10 + lis r10,(MAS1_VALID|MAS1_IPROT)@h + ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l + mtspr SPRN_MAS1,r10 /* WIMGE = 0b00000 for now */ - mtspr SPRN_MAS2,r8 - ori r8,r8,(MAS3_SX|MAS3_SW|MAS3_SR) - mtspr SPRN_MAS3,r8 + mtspr SPRN_MAS2,r12 + ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR) + mtspr SPRN_MAS3,r12 +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr SPRN_MAS7,r11 +#endif tlbwe /* Now we have another mapping for this page, so we jump to that * mapping */ - bctr + mtspr SPRN_SRR1,r13 + rfi .align 3 .globl __spin_table __spin_table: - .space CONFIG_NR_CPUS*24 + .space CONFIG_NR_CPUS*ENTRY_SIZE /* Fill in the empty space. The actual reset vector is * the last word of the page */ diff --git a/include/common.h b/include/common.h index f496073..39bcd30 100644 --- a/include/common.h +++ b/include/common.h @@ -673,7 +673,7 @@ void inline show_boot_progress (int val); #ifdef CONFIG_MP int cpu_status(int nr); int cpu_reset(int nr); -int cpu_release(int nr, unsigned long boot_addr, int argc, char *argv[]); +int cpu_release(int nr, int argc, char *argv[]); #endif #endif /* __COMMON_H_ */ -- cgit v0.10.2 From dd6c910aadf27c822f17b87eae1a9bd0b2e3aa15 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 26 Mar 2008 08:53:53 -0500 Subject: 85xx: Add cpu_mp_lmb_reserve helper to reserve boot page Provide a board_lmb_reserve helper function to ensure we reserve the page of memory we are using for the boot page translation code. Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index d3727b0..7b10fba 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "mp.h" @@ -177,6 +178,19 @@ static void pq3_mp_up(unsigned long bootpg) out_be32(&gur->devdisr, devdisr); } +void cpu_mp_lmb_reserve(struct lmb *lmb) +{ + u32 bootpg; + + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + + lmb_reserve(lmb, bootpg, 4096); +} + void setup_mp(void) { extern ulong __secondary_start_page; diff --git a/cpu/mpc85xx/mp.h b/cpu/mpc85xx/mp.h index b762ee2..4329286 100644 --- a/cpu/mpc85xx/mp.h +++ b/cpu/mpc85xx/mp.h @@ -4,6 +4,7 @@ ulong get_spin_addr(void); void setup_mp(void); u32 get_my_id(void); +void cpu_mp_lmb_reserve(struct lmb *lmb); #define BOOT_ENTRY_ADDR_UPPER 0 #define BOOT_ENTRY_ADDR_LOWER 1 -- cgit v0.10.2