From e92c95180bb5bc5fd4051598a9d60beaba48988d Mon Sep 17 00:00:00 2001
From: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Date: Wed, 12 Mar 2008 12:15:29 +0900
Subject: sh: Add support SH4 cache control

Add support SH4 cache control and flash_cache function

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c
index 0ebf951..d94e139 100644
--- a/cpu/sh4/cpu.c
+++ b/cpu/sh4/cpu.c
@@ -24,6 +24,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/processor.h>
+#include <asm/cache.h>
 
 int checkcpu(void)
 {
@@ -51,7 +52,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 void flush_cache (unsigned long addr, unsigned long size)
 {
-
+	dcache_invalid_range( addr , addr + size );
 }
 
 void icache_enable (void)
diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
new file mode 100644
index 0000000..67474c7
--- /dev/null
+++ b/include/asm-sh/cache.h
@@ -0,0 +1,35 @@
+#ifndef __ASM_SH_CACHE_H
+#define __ASM_SH_CACHE_H
+
+#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+
+#define L1_CACHE_BYTES 32
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct *)(x))
+
+void dcache_wback_range(u32 start, u32 end)
+{
+    u32 v;
+
+    start &= ~(L1_CACHE_BYTES-1);
+    for (v = start; v < end; v+=L1_CACHE_BYTES) {
+        asm volatile("ocbwb     %0"
+                     : /* no output */
+                     : "m" (__m(v)));
+    }
+}
+
+void dcache_invalid_range(u32 start, u32 end)
+{
+    u32 v;
+
+    start &= ~(L1_CACHE_BYTES-1);
+    for (v = start; v < end; v+=L1_CACHE_BYTES) {
+        asm volatile("ocbi     %0"
+                     : /* no output */
+                     : "m" (__m(v)));
+    }
+}
+#endif /* CONFIG_SH4 || CONFIG_SH4A */
+
+#endif	/* __ASM_SH_CACHE_H */
-- 
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