From e2bc87d41ce866b30721d5b8ee395efefecd9bef Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 13 May 2017 20:11:30 -0400 Subject: sandbox: Fix comparison of unsigned enum expression warning In os_dirent_get_typename() we are checking that type falls within the known values of the enum os_dirent_t. With clang-3.8 testing this value as being >= 0 results in a warning as it will always be true. This assumes of course that we are only given valid data. Given that we want to sanity check the input, we change this to check that it falls within the range of the first to the last entry in the given enum. Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 35ea00c..7243bfc 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -395,7 +395,7 @@ const char *os_dirent_typename[OS_FILET_COUNT] = { const char *os_dirent_get_typename(enum os_dirent_t type) { - if (type >= 0 && type < OS_FILET_COUNT) + if (type >= OS_FILET_REG && type < OS_FILET_COUNT) return os_dirent_typename[type]; return os_dirent_typename[OS_FILET_UNKNOWN]; -- cgit v0.10.2 From d5686a61d64a7c7424d6d4c93ac60cf5e324f3ad Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 22 May 2017 13:48:52 -0400 Subject: buildman: Fix bloat option when 'new' only drops functions In the case where a new build only decreases sizes and does not increase any size we still want to report what functions have been dropped when doing a bloat comparison. Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index b0ea57e..acb0810 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -847,7 +847,7 @@ class Builder: delta.reverse() args = [add, -remove, grow, -shrink, up, -down, up - down] - if max(args) == 0: + if max(args) == 0 and min(args) == 0: return args = [self.ColourNum(x) for x in args] indent = ' ' * 15 -- cgit v0.10.2 From 21caa558ca1811a9995ed1c1b0e2c01cbdf25662 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Mon, 29 May 2017 15:31:22 -0600 Subject: patman: encode CC list to UTF-8 This change encodes the CC list to UTF-8 to avoid failures on maintainer-addresses that include non-ASCII characters (observed on Debian 7.11 with Python 2.7.3). Without this, I get the following failure: Traceback (most recent call last): File "tools/patman/patman", line 159, in options.add_maintainers) File "[snip]/u-boot/tools/patman/series.py", line 234, in MakeCcFile print(commit.patch, ', '.join(set(list)), file=fd) UnicodeEncodeError: 'ascii' codec can't encode character u'\xfc' in position 81: ordinal not in range(128) from Heiko's email address: [..., u'"Heiko St\xfcbner" ', ...] While with this change added this encodes to: "=?UTF-8?q?Heiko=20St=C3=BCbner?= " Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass Signed-off-by: Simon Glass Tested-by: Simon Glass Tested-by: Philipp Tomsich diff --git a/tools/patman/series.py b/tools/patman/series.py index c1b8652..134a381 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -119,7 +119,7 @@ class Series(dict): email = col.Color(col.YELLOW, "" % tag) if email: - print(' Cc: ', email) + print(' Cc: ', email.encode('utf-8')) print for item in to_set: print('To:\t ', item) @@ -230,7 +230,7 @@ class Series(dict): if add_maintainers: list += get_maintainer.GetMaintainer(commit.patch) all_ccs += list - print(commit.patch, ', '.join(set(list)), file=fd) + print(commit.patch, ', '.join(set(list)).encode('utf-8'), file=fd) self._generated_cc[commit.patch] = list if cover_fname: -- cgit v0.10.2 From 6f8abf765b9a8be4a32d84677cbbff1a1706b325 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 May 2017 15:31:23 -0600 Subject: patman: Adjust handling of unicode email address Don't mess with the email address when outputting them. Just make sure they are encoded with utf-8. Signed-off-by: Simon Glass Tested-by: Philipp Tomsich diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index 0d23079..167bda3 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -407,6 +407,8 @@ def EmailPatches(series, cover_fname, args, dry_run, raise_on_error, cc_fname, cc = [] cmd = ['git', 'send-email', '--annotate'] if in_reply_to: + if type(in_reply_to) != str: + in_reply_to = in_reply_to.encode('utf-8') cmd.append('--in-reply-to="%s"' % in_reply_to) if thread: cmd.append('--thread') diff --git a/tools/patman/series.py b/tools/patman/series.py index 134a381..7a3534f 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -119,7 +119,7 @@ class Series(dict): email = col.Color(col.YELLOW, "" % tag) if email: - print(' Cc: ', email.encode('utf-8')) + print(' Cc: ', email) print for item in to_set: print('To:\t ', item) @@ -229,13 +229,17 @@ class Series(dict): raise_on_error=raise_on_error) if add_maintainers: list += get_maintainer.GetMaintainer(commit.patch) + list = [m.encode('utf-8') if type(m) != str else m for m in list] all_ccs += list - print(commit.patch, ', '.join(set(list)).encode('utf-8'), file=fd) + print(commit.patch, ', '.join(set(list)), file=fd) self._generated_cc[commit.patch] = list if cover_fname: cover_cc = gitutil.BuildEmailList(self.get('cover_cc', '')) - cc_list = ', '.join([x.decode('utf-8') for x in set(cover_cc + all_ccs)]) + cover_cc = [m.encode('utf-8') if type(m) != str else m + for m in cover_cc] + cc_list = ', '.join([x.decode('utf-8') + for x in set(cover_cc + all_ccs)]) print(cover_fname, cc_list.encode('utf-8'), file=fd) fd.close() -- cgit v0.10.2 From 5c724dc4403c63b86fef8cccd2baa47cfa870986 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 May 2017 15:31:24 -0600 Subject: patman: Don't convert input data to unicode The communication filter reads data in blocks and converts each block to unicode (if necessary) one at a time. In the unlikely event that a unicode character in the input spans a block this will not work. We get an error like: UnicodeDecodeError: 'utf8' codec can't decode bytes in position 1022-1023: unexpected end of data There is no need to change the input to unicode, so the easiest fix is to drop this feature. Signed-off-by: Simon Glass Tested-by: Philipp Tomsich diff --git a/tools/patman/cros_subprocess.py b/tools/patman/cros_subprocess.py index 7c76014..ebd4300 100644 --- a/tools/patman/cros_subprocess.py +++ b/tools/patman/cros_subprocess.py @@ -190,8 +190,6 @@ class Popen(subprocess.Popen): # We will get an error on read if the pty is closed try: data = os.read(self.stdout.fileno(), 1024) - if isinstance(data, bytes): - data = data.decode('utf-8') except OSError: pass if data == "": @@ -207,8 +205,6 @@ class Popen(subprocess.Popen): # We will get an error on read if the pty is closed try: data = os.read(self.stderr.fileno(), 1024) - if isinstance(data, bytes): - data = data.decode('utf-8') except OSError: pass if data == "": -- cgit v0.10.2 From 2df3a01974a06145cc20c53d5f1309ccdb2b6946 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 May 2017 15:31:25 -0600 Subject: patman: Rename 'str' variable in EmailPatches() This is not a good variable name in Python because 'str' is a type. It shows up highlighted in some editors. Rename it. Signed-off-by: Simon Glass Tested-by: Philipp Tomsich diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index 167bda3..08be937 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -419,10 +419,10 @@ def EmailPatches(series, cover_fname, args, dry_run, raise_on_error, cc_fname, if cover_fname: cmd.append(cover_fname) cmd += args - str = ' '.join(cmd) + cmdstr = ' '.join(cmd) if not dry_run: - os.system(str) - return str + os.system(cmdstr) + return cmdstr def LookupEmail(lookup_name, alias=None, raise_on_error=True, level=0): -- cgit v0.10.2 From 04f7870635dff90ddc1b8465b5b8304c2d429a92 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 May 2017 15:31:26 -0600 Subject: patman: Don't report unicode character Unicode characters may appear in input patches so we should not warn about them. Drop this warning. Signed-off-by: Simon Glass Tested-by: Philipp Tomsich diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index cd4667f..324c654 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -308,15 +308,6 @@ class PatchStream: # Well that means this is an ordinary line else: - pos = 1 - # Look for ugly ASCII characters - for ch in line: - # TODO: Would be nicer to report source filename and line - if ord(ch) > 0x80: - self.warn.append("Line %d/%d ('%s') has funny ascii char" % - (self.linenum, pos, line)) - pos += 1 - # Look for space before tab m = re_space_before_tab.match(line) if m: -- cgit v0.10.2 From db116cc8d095ec499ae748ea864fa0def54ca3d6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 May 2017 15:31:27 -0600 Subject: patman: Don't return the series in FixPatches() There is no need for this function to return the same object that was passed in. Drop the return value. Signed-off-by: Simon Glass Tested-by: Philipp Tomsich diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index 324c654..6098728 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -477,7 +477,6 @@ def FixPatches(series, fnames): print count += 1 print('Cleaned %d patches' % count) - return series def InsertCoverLetter(fname, series, count): """Inserts a cover letter with the required info into patch 0 diff --git a/tools/patman/patman.py b/tools/patman/patman.py index fdbee67..63da3f3 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -141,8 +141,8 @@ else: series) # Fix up the patch files to our liking, and insert the cover letter - series = patchstream.FixPatches(series, args) - if series and cover_fname and series.get('cover'): + patchstream.FixPatches(series, args) + if cover_fname and series.get('cover'): patchstream.InsertCoverLetter(cover_fname, series, options.count) # Do a few checks on the series -- cgit v0.10.2 From 2eb5fc13b3494ab2d32edb6235826f3442254749 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 May 2017 15:31:28 -0600 Subject: patman: Add unicode to test patches Add some unicode to the test patches to make sure that patman does the right thing. Signed-off-by: Simon Glass Tested-by: Philipp Tomsich diff --git a/tools/patman/test.py b/tools/patman/test.py index 8c39f66..20dc9c1 100644 --- a/tools/patman/test.py +++ b/tools/patman/test.py @@ -1,3 +1,4 @@ +# -*- coding: utf-8 -*- # # Copyright (c) 2011 The Chromium OS Authors. # @@ -31,6 +32,10 @@ Subject: [PATCH (resend) 3/7] Tegra2: Add more clock support This adds functions to enable/disable clocks and reset to on-chip peripherals. +cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘u64 {aka long unsigned int}’ [-Wformat=] + BUG=chromium-os:13875 TEST=build U-Boot for Seaboard, boot @@ -53,6 +58,10 @@ Subject: [PATCH (resend) 3/7] Tegra2: Add more clock support This adds functions to enable/disable clocks and reset to on-chip peripherals. +cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘u64 {aka long unsigned int}’ [-Wformat=] + Signed-off-by: Simon Glass --- -- cgit v0.10.2 From 1f487f85d2d2a78a8d4e533253ed5c853540aea1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 May 2017 15:31:29 -0600 Subject: patman: Add a maintainer test feature to MakeCcFile() Allow the add_maintainers parameter to be a list of maintainers, thus allowing us to simulate calling the script in tests without actually needing it to work. Signed-off-by: Simon Glass Tested-by: Philipp Tomsich diff --git a/tools/patman/series.py b/tools/patman/series.py index 7a3534f..395b9ea 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -212,7 +212,9 @@ class Series(dict): cover_fname: If non-None the name of the cover letter. raise_on_error: True to raise an error when an alias fails to match, False to just print a message. - add_maintainers: Call the get_maintainers to CC maintainers + add_maintainers: Either: + True/False to call the get_maintainers to CC maintainers + List of maintainers to include (for testing) Return: Filename of temp file created """ @@ -227,7 +229,9 @@ class Series(dict): raise_on_error=raise_on_error) list += gitutil.BuildEmailList(commit.cc_list, raise_on_error=raise_on_error) - if add_maintainers: + if type(add_maintainers) == type(list): + list += add_maintainers + elif add_maintainers: list += get_maintainer.GetMaintainer(commit.patch) list = [m.encode('utf-8') if type(m) != str else m for m in list] all_ccs += list -- cgit v0.10.2 From a44f4fb72bcb954bf38385e2953f7320b9f25aa3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 May 2017 15:31:30 -0600 Subject: patman: Rename 'list' variable in MakeCcFile() This is not a good variable name in Python because 'list' is a type. It shows up highlighted in some editors. Rename it. Signed-off-by: Simon Glass Tested-by: Philipp Tomsich diff --git a/tools/patman/series.py b/tools/patman/series.py index 395b9ea..d3947a7 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -223,20 +223,20 @@ class Series(dict): fd = open(fname, 'w') all_ccs = [] for commit in self.commits: - list = [] + cc = [] if process_tags: - list += gitutil.BuildEmailList(commit.tags, + cc += gitutil.BuildEmailList(commit.tags, raise_on_error=raise_on_error) - list += gitutil.BuildEmailList(commit.cc_list, + cc += gitutil.BuildEmailList(commit.cc_list, raise_on_error=raise_on_error) - if type(add_maintainers) == type(list): - list += add_maintainers + if type(add_maintainers) == type(cc): + cc += add_maintainers elif add_maintainers: - list += get_maintainer.GetMaintainer(commit.patch) - list = [m.encode('utf-8') if type(m) != str else m for m in list] - all_ccs += list - print(commit.patch, ', '.join(set(list)), file=fd) - self._generated_cc[commit.patch] = list + cc += get_maintainer.GetMaintainer(commit.patch) + cc = [m.encode('utf-8') if type(m) != str else m for m in cc] + all_ccs += cc + print(commit.patch, ', '.join(set(cc)), file=fd) + self._generated_cc[commit.patch] = cc if cover_fname: cover_cc = gitutil.BuildEmailList(self.get('cover_cc', '')) -- cgit v0.10.2 From 6e87ae1c0730ec99b6824c2a3dc8510813f92b98 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 May 2017 15:31:31 -0600 Subject: patman: Add a functional test The existing test (patman --test) only covers basic checkpatch output. We have had some problems with unicode processing and could use test coverage for the various tags patman supports. Add a new functional test which runs most of the patman flow on a few test commits and checks that the results are correct. See the documentation in the test for a description of what it does. Signed-off-by: Simon Glass Tested-by: Philipp Tomsich diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py new file mode 100644 index 0000000..2c0da84 --- /dev/null +++ b/tools/patman/func_test.py @@ -0,0 +1,242 @@ +# -*- coding: utf-8 -*- +# +# Copyright 2017 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +import contextlib +import os +import re +import shutil +import sys +import tempfile +import unittest + +import gitutil +import patchstream +import settings + + +@contextlib.contextmanager +def capture(): + import sys + from cStringIO import StringIO + oldout,olderr = sys.stdout, sys.stderr + try: + out=[StringIO(), StringIO()] + sys.stdout,sys.stderr = out + yield out + finally: + sys.stdout,sys.stderr = oldout, olderr + out[0] = out[0].getvalue() + out[1] = out[1].getvalue() + + +class TestFunctional(unittest.TestCase): + def setUp(self): + self.tmpdir = tempfile.mkdtemp(prefix='patman.') + + def tearDown(self): + shutil.rmtree(self.tmpdir) + + @staticmethod + def GetPath(fname): + return os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), + 'test', fname) + + @classmethod + def GetText(self, fname): + return open(self.GetPath(fname)).read() + + @classmethod + def GetPatchName(self, subject): + fname = re.sub('[ :]', '-', subject) + return fname.replace('--', '-') + + def CreatePatchesForTest(self, series): + cover_fname = None + fname_list = [] + for i, commit in enumerate(series.commits): + clean_subject = self.GetPatchName(commit.subject) + src_fname = '%04d-%s.patch' % (i + 1, clean_subject[:52]) + fname = os.path.join(self.tmpdir, src_fname) + shutil.copy(self.GetPath(src_fname), fname) + fname_list.append(fname) + if series.get('cover'): + src_fname = '0000-cover-letter.patch' + cover_fname = os.path.join(self.tmpdir, src_fname) + fname = os.path.join(self.tmpdir, src_fname) + shutil.copy(self.GetPath(src_fname), fname) + + return cover_fname, fname_list + + def testBasic(self): + """Tests the basic flow of patman + + This creates a series from some hard-coded patches build from a simple + tree with the following metadata in the top commit: + + Series-to: u-boot + Series-prefix: RFC + Series-cc: Stefan Brüns + Cover-letter-cc: Lord Mëlchett + Series-version: 2 + Series-changes: 4 + - Some changes + + Cover-letter: + test: A test patch series + This is a test of how the cover + leter + works + END + + and this in the first commit: + + Series-notes: + some notes + about some things + from the first commit + END + + Commit-notes: + Some notes about + the first commit + END + + with the following commands: + + git log -n2 --reverse >/path/to/tools/patman/test/test01.txt + git format-patch --subject-prefix RFC --cover-letter HEAD~2 + mv 00* /path/to/tools/patman/test + + It checks these aspects: + - git log can be processed by patchstream + - emailing patches uses the correct command + - CC file has information on each commit + - cover letter has the expected text and subject + - each patch has the correct subject + - dry-run information prints out correctly + - unicode is handled correctly + - Series-to, Series-cc, Series-prefix, Cover-letter + - Cover-letter-cc, Series-version, Series-changes, Series-notes + - Commit-notes + """ + process_tags = True + ignore_bad_tags = True + stefan = u'Stefan Brüns ' + rick = 'Richard III ' + mel = u'Lord Mëlchett ' + ed = u'Lond Edmund Blackaddër +Date: Sat, 27 May 2017 20:52:11 -0600 +Subject: [RFC 0/2] *** SUBJECT HERE *** +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +*** BLURB HERE *** + +Simon Glass (2): + pci: Correct cast for sandbox + fdt: Correct cast for sandbox in fdtdec_setup_memory_size() + + cmd/pci.c | 3 ++- + fs/fat/fat.c | 1 + + lib/efi_loader/efi_memory.c | 1 + + lib/fdtdec.c | 3 ++- + 4 files changed, 6 insertions(+), 2 deletions(-) + +-- +2.7.4 + diff --git a/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch b/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch new file mode 100644 index 0000000..7191176 --- /dev/null +++ b/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch @@ -0,0 +1,48 @@ +From b9da5f937bd5ea4931ea17459bf79b2905d9594d Mon Sep 17 00:00:00 2001 +From: Simon Glass +Date: Sat, 15 Apr 2017 15:39:08 -0600 +Subject: [RFC 1/2] pci: Correct cast for sandbox +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This gives a warning with some native compilers: + +cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘u64 {aka long unsigned int}’ [-Wformat=] + +Fix it with a cast. + +Signed-off-by: Simon Glass +Series-notes: +some notes +about some things +from the first commit +END + +Commit-notes: +Some notes about +the first commit +END +--- + cmd/pci.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/cmd/pci.c b/cmd/pci.c +index 41b4fff..fe27b4f 100644 +--- a/cmd/pci.c ++++ b/cmd/pci.c +@@ -150,7 +150,8 @@ int pci_bar_show(struct udevice *dev) + if ((!is_64 && size_low) || (is_64 && size)) { + size = ~size + 1; + printf(" %d %#016llx %#016llx %d %s %s\n", +- bar_id, base, size, is_64 ? 64 : 32, ++ bar_id, (unsigned long long)base, ++ (unsigned long long)size, is_64 ? 64 : 32, + is_io ? "I/O" : "MEM", + prefetchable ? "Prefetchable" : ""); + } +-- +2.7.4 + diff --git a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_memory_.patch b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_memory_.patch new file mode 100644 index 0000000..e328497 --- /dev/null +++ b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_memory_.patch @@ -0,0 +1,73 @@ +From 5ab48490f03051875ab13d288a4bf32b507d76fd Mon Sep 17 00:00:00 2001 +From: Simon Glass +Date: Sat, 15 Apr 2017 15:39:08 -0600 +Subject: [RFC 2/2] fdt: Correct cast for sandbox in fdtdec_setup_memory_size() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This gives a warning with some native compilers: + +lib/fdtdec.c:1203:8: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘long unsigned int’ [-Wformat=] + +Fix it with a cast. + +Signed-off-by: Simon Glass +Series-to: u-boot +Series-prefix: RFC +Series-cc: Stefan Brüns +Cover-letter-cc: Lord Mëlchett +Series-version: 3 +Patch-cc: fred +Series-changes: 4 +- Some changes + +Cover-letter: +test: A test patch series +This is a test of how the cover +leter +works +END +--- + fs/fat/fat.c | 1 + + lib/efi_loader/efi_memory.c | 1 + + lib/fdtdec.c | 3 ++- + 3 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/fs/fat/fat.c b/fs/fat/fat.c +index a71bad1..ba169dc 100644 +--- a/fs/fat/fat.c ++++ b/fs/fat/fat.c +@@ -1,3 +1,4 @@ ++ + /* + * fat.c + * +diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c +index db2ae19..05f75d1 100644 +--- a/lib/efi_loader/efi_memory.c ++++ b/lib/efi_loader/efi_memory.c +@@ -1,3 +1,4 @@ ++ + /* + * EFI application memory management + * +diff --git a/lib/fdtdec.c b/lib/fdtdec.c +index c072e54..942244f 100644 +--- a/lib/fdtdec.c ++++ b/lib/fdtdec.c +@@ -1200,7 +1200,8 @@ int fdtdec_setup_memory_size(void) + } + + gd->ram_size = (phys_size_t)(res.end - res.start + 1); +- debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size); ++ debug("%s: Initial DRAM size %llx\n", __func__, ++ (unsigned long long)gd->ram_size); + + return 0; + } +-- +2.7.4 + diff --git a/tools/patman/test/test01.txt b/tools/patman/test/test01.txt new file mode 100644 index 0000000..8ad9587 --- /dev/null +++ b/tools/patman/test/test01.txt @@ -0,0 +1,56 @@ +commit b9da5f937bd5ea4931ea17459bf79b2905d9594d +Author: Simon Glass +Date: Sat Apr 15 15:39:08 2017 -0600 + + pci: Correct cast for sandbox + + This gives a warning with some native compilers: + + cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘u64 {aka long unsigned int}’ [-Wformat=] + + Fix it with a cast. + + Signed-off-by: Simon Glass + Series-notes: + some notes + about some things + from the first commit + END + + Commit-notes: + Some notes about + the first commit + END + +commit 5ab48490f03051875ab13d288a4bf32b507d76fd +Author: Simon Glass +Date: Sat Apr 15 15:39:08 2017 -0600 + + fdt: Correct cast for sandbox in fdtdec_setup_memory_size() + + This gives a warning with some native compilers: + + lib/fdtdec.c:1203:8: warning: format ‘%llx’ expects argument of type + ‘long long unsigned int’, but argument 3 has type + ‘long unsigned int’ [-Wformat=] + + Fix it with a cast. + + Signed-off-by: Simon Glass + Series-to: u-boot + Series-prefix: RFC + Series-cc: Stefan Brüns + Cover-letter-cc: Lord Mëlchett + Series-version: 3 + Patch-cc: fred + Series-changes: 4 + - Some changes + + Cover-letter: + test: A test patch series + This is a test of how the cover + leter + works + END -- cgit v0.10.2 From 1c2d2727d17a5a81caa3c611603a9e1c92ee86e1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:11 -0600 Subject: arm: arm720t: Support CONFIG_SKIP_LOWLEVEL_INIT_ONLY This option allows skipping the call to lowlevel() while still performing CP15 init. Support this on ARM720T so it can be used with Tegra. Signed-off-by: Simon Glass diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 0bb3441..365d8f0 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -38,7 +38,8 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) bl cpu_init_crit #endif @@ -62,7 +63,8 @@ c_runtime_cpu_setup: ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) cpu_init_crit: mov ip, lr -- cgit v0.10.2 From 579dfca2ef2fdff93ae78a942fef49f3d1da3f8c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:12 -0600 Subject: arm: Rename HCTR to HTCR This appears to be a typo. Fix it. Signed-off-by: Simon Glass diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index e9bbcf5..0f7020a 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -147,7 +147,7 @@ static inline void mmu_setup(void) #endif if (is_hyp()) { - /* Set HCTR to enable LPAE */ + /* Set HTCR to enable LPAE */ asm volatile("mcr p15, 4, %0, c2, c0, 2" : : "r" (reg) : "memory"); /* Set HTTBR0 */ -- cgit v0.10.2 From 10d602ac8b6f576d545e35a951e1a714de0158a3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:13 -0600 Subject: arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use instructions which are invalid on ARMv4T. This happens on Tegra since it has an ARMv4T boot CPU. Add a check for the architecture version to allow the code to be built. It will not actually be executed by the boot CPU, but needs to compile. Signed-off-by: Simon Glass diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0f7020a..f293573 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -129,7 +129,7 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); } -#ifdef CONFIG_ARMV7_LPAE +#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4 /* Set up 4 PTE entries pointing to our 4 1GB page tables */ for (i = 0; i < 4; i++) { u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4)); -- cgit v0.10.2 From 50a4886b3b8579a5d3dad337906de9b5a3fef6d1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:14 -0600 Subject: arm: Disable LPAE if not enabled If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature is disabled. This can happen if U-Boot is chain-loaded from another boot loader which does enable LPAE. Signed-off-by: Simon Glass diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f293573..cf852c0 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -172,6 +172,15 @@ static inline void mmu_setup(void) : : "r" (MEMORY_ATTRIBUTES) : "memory"); } #elif defined(CONFIG_CPU_V7) + if (is_hyp()) { + /* Set HTCR to disable LPAE */ + asm volatile("mcr p15, 4, %0, c2, c0, 2" + : : "r" (0) : "memory"); + } else { + /* Set TTBCR to disable LPAE */ + asm volatile("mcr p15, 0, %0, c2, c0, 2" + : : "r" (0) : "memory"); + } /* Set TTBR0 */ reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) -- cgit v0.10.2 From 422f04b68f59a8348428a6a5628a00a5689d0168 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:15 -0600 Subject: power: regulator: Add more debugging and fix a missing newline This file does not report a few possible errors and one message is missing a newline. Fix these. Signed-off-by: Simon Glass Reviewed-by: Jaehoon Chung diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index a42f80b..0a1d1b3 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -146,8 +146,10 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; ret = uclass_find_next_device(&dev)) { - if (ret) + if (ret) { + debug("regulator %s, ret=%d\n", dev->name, ret); continue; + } uc_pdata = dev_get_uclass_platdata(dev); if (!uc_pdata || strcmp(plat_name, uc_pdata->name)) @@ -156,7 +158,7 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) return uclass_get_device_tail(dev, 0, devp); } - debug("%s: can't find: %s\n", __func__, plat_name); + debug("%s: can't find: %s, ret=%d\n", __func__, plat_name, ret); return -ENODEV; } @@ -219,7 +221,7 @@ int regulator_autoset_by_name(const char *platname, struct udevice **devp) if (devp) *devp = dev; if (ret) { - debug("Can get the regulator: %s!", platname); + debug("Can get the regulator: %s (err=%d)\n", platname, ret); return ret; } -- cgit v0.10.2 From 46864cc8e82ade3523f4c474b7451bb960e4ad70 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:16 -0600 Subject: tegra: Init clocks even when SPL did not run At present early clock init happens in SPL. If SPL did not run (because for example U-Boot is chain-loaded from another boot loader) then the clocks are not set as U-Boot expects. Add a function to detect this and call the early clock init in U-Boot proper. Signed-off-by: Simon Glass diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 388afcb..f62b2a4 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -288,6 +288,9 @@ void clock_init(void); /* Initialize the PLLs */ void clock_early_init(void); +/* @return true if hardware indicates that clock_early_init() was called */ +bool clock_early_init_done(void); + /* Returns a pointer to the clock source register for a peripheral */ u32 *get_periph_source_reg(enum periph_id periph_id); diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 84f1ee5..1e627ba 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -191,6 +191,9 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); int board_early_init_f(void) { + if (!clock_early_init_done()) + clock_early_init(); + #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) #define USBCMD_FS2 (1 << 15) { diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 3bb7233..76436d8 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -825,3 +825,8 @@ int clock_external_output(int clk_id) return 0; } + +__weak bool clock_early_init_done(void) +{ + return true; +} diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 5e44061..5ae718b 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -891,6 +891,24 @@ void clock_early_init(void) udelay(2); } +/* + * clock_early_init_done - Check if clock_early_init() has been called + * + * Check a register that we set up to see if clock_early_init() has already + * been called. + * + * @return true if clock_early_init() was called, false if not + */ +bool clock_early_init_done(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 val; + + val = readl(&clkrst->crc_sclk_brst_pol); + + return val == 0x20002222; +} + void arch_timer_init(void) { struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; -- cgit v0.10.2 From c415dda8df1134ba60ff031110649ca4e2735174 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:17 -0600 Subject: tegra: dts: Add cros-ec SPI settings At present the interrupt does not work and the SPI bus runs much less quickly than it should. Add settings to fix this. Signed-off-by: Simon Glass diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi index fff1d78..65c3851 100644 --- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi +++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi @@ -12,4 +12,13 @@ u-boot,dm-pre-reloc; }; }; + + spi@7000d400 { + spi-deactivate-delay = <200>; + spi-max-frequency = <3000000>; + + cros_ec: cros-ec@0 { + ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + }; + }; }; -- cgit v0.10.2 From 4a7b9ee15ee0c5aa38bce0e32263fbb11572b475 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:18 -0600 Subject: tegra: spi: Wait a little after setting the clocks For devices that need a delay between SPI transactions we seem to need an additional delay before the first one if the CPU is running at full speed. Add this, under control of the existing setting. At present it will only be enabled with the Chrome OS EC. Signed-off-by: Simon Glass diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 802117e..9165934 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -152,6 +152,7 @@ static int tegra114_spi_probe(struct udevice *bus) bus->name, priv->freq, rate); } } + udelay(plat->deactivate_delay_us); /* Clear stale status here */ setbits_le32(®s->fifo_status, -- cgit v0.10.2 From dab4728b3daa67a9995deb03512d548c54939dcf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:19 -0600 Subject: tegra: nyan-big: Enable the dhrystone benchmark Enable this so we can roughly measure CPU performance. Also enable the cache command to allow for timing. Signed-off-by: Simon Glass diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index f0fad3e..fb2e479 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_TPM=y @@ -62,5 +63,6 @@ CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_TEGRA124=y CONFIG_VIDEO_BRIDGE=y +CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_ERRNO_STR=y -- cgit v0.10.2 From 505907a4677786dc179d7edd3d71bb5f273425cf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:20 -0600 Subject: tegra: video: Don't power up the SOR twice If U-Boot is the secondary boot loader, or has been run from itself, the SOR may already be powered up. Powering it up again causes a hang, so detect this situation and skip it. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c index 5e4140f..4324071 100644 --- a/drivers/video/tegra124/sor.c +++ b/drivers/video/tegra124/sor.c @@ -466,11 +466,20 @@ void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count) static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); + u32 reg; int ret; if (sor->power_is_up) return 0; + /* + * If for some reason it is already powered up, don't do it again. + * This can happen if U-Boot is the secondary boot loader. + */ + reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); + if (reg & DP_PADCTL_PD_TXD_0_NO) + return 0; + /* Set link bw */ tegra_dc_sor_set_link_bandwidth(dev, is_lvds ? CLK_CNTRL_DP_LINK_SPEED_LVDS : -- cgit v0.10.2 From 06cc85a29abfd0f022c51175912adff790aa2434 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:21 -0600 Subject: tegra: Enable CP15 init At present CP15 init is disabled on tegra. Use the correct option so that this init is performed on boot. This enables the instruction cache, for example, which is critical to the machine running at full speed. Signed-off-by: Simon Glass diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c03efd8..dd72e5b 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -105,7 +105,7 @@ /* overrides for SPL build here */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* remove I2C support */ #ifdef CONFIG_SYS_I2C_TEGRA -- cgit v0.10.2 From 1c6c7b6bd8961373a506cf7908e9fe61f6042341 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:22 -0600 Subject: tegra: clock: Avoid a divide-by-zero error The clock fix-up for tegra is still present in the code. It causes a divide-by-zero bug after relocation when chain-loading U-Boot from coreboot. Fix this by adding a check. Signed-off-by: Simon Glass Fixes: 7468676 (ARM: tegra: fix clock_get_periph_rate() for UART clocks) diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 76436d8..bac4211 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -339,8 +339,11 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, * return value doesn't help. In summary this clock driver is * quite broken but I'm afraid I have no idea how to fix it * without completely replacing it. + * + * Be careful to avoid a divide by zero error. */ - div -= 2; + if (div >= 1) + div -= 2; break; #endif default: -- cgit v0.10.2 From 13bdce8f8cadf07bc81d7000a04e48f3028de543 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:23 -0600 Subject: tegra: nyan-big: Add a .its file for chromium Add a sample .its file for booting U-Boot on a nyan-big Chromebook. Signed-off-by: Simon Glass diff --git a/doc/chromium/nyan-big.its b/doc/chromium/nyan-big.its new file mode 100644 index 0000000..8dc8d73 --- /dev/null +++ b/doc/chromium/nyan-big.its @@ -0,0 +1,42 @@ +/dts-v1/; + +/ { + description = "U-Boot mainline"; + #address-cells = <1>; + + images { + kernel@1 { + description = "U-Boot mainline"; + type = "kernel_noload"; + arch = "arm"; + os = "linux"; + data = /incbin/("../.././b/nyan-big/u-boot.bin"); + compression = "none"; + load = <0>; + entry = <0>; + hash@2 { + algo = "sha1"; + }; + }; + + fdt@1{ + description = "tegra124-nyan-big.dtb"; + data = /incbin/("../.././b/nyan-big/u-boot.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash@1{ + algo = "sha1"; + }; + }; + }; + + configurations { + default = "config@1"; + config@1 { + description = "Boot U-Boot"; + kernel = "kernel@1"; + fdt = "fdt@1"; + }; + }; +}; -- cgit v0.10.2 From c9af6673e8799dbc32b1654c152c1bf9c2454b72 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:24 -0600 Subject: README: Add instructions for chain-loading U-Boot Most Chromebooks support chain-loading U-Boot but instructions are somewhat scattered. Add a README to hold this information within the U-Boot tree. Also add the standard developer keys to simplify the instructions, since they are small. For now this only supports nyan-big. Signed-off-by: Simon Glass diff --git a/doc/README.chromium b/doc/README.chromium new file mode 100644 index 0000000..61e285d --- /dev/null +++ b/doc/README.chromium @@ -0,0 +1,182 @@ +Running U-Boot from coreboot on Chromebooks +=========================================== + +U-Boot can be used as a secondary boot loader in a few situations such as from +UEFI and coreboot (see README.x86). Recent Chromebooks use coreboot even on +ARM platforms to start up the machine. + +This document aims to provide a guide to booting U-Boot on a Chromebook. It +is only a starting point, and there are many guides on the interwebs. But +placing this information in the U-Boot tree should make it easier to find for +those who use U-Boot habitually. + +Most of these platforms are supported by U-Boot natively, but it is risky to +replace the ROM unless you have a servo board and cable to restore it with. + + +For all of these the standard U-Boot build instructions apply. For example on +ARM: + + sudo apt install gcc-arm-linux-gnueabi + mkdir b + make O=b/nyan_big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all + +You can obtain the vbutil_kernel utility here: + + https://drive.google.com/open?id=0B7WYZbZ9zd-3dHlVVXo4VXE2T0U + + +Snow (Samsung ARM Chromebook) +----------------------------- + +See here: + +https://www.chromium.org/chromium-os/firmware-porting-guide/using-nv-u-boot-on-the-samsung-arm-chromebook + + +Nyan-big +-------- + +Compiled based on information here: +https://lists.denx.de/pipermail/u-boot/2015-March/209530.html +https://git.collabora.com/cgit/user/tomeu/u-boot.git/commit/?h=nyan-big +https://lists.denx.de/pipermail/u-boot/2017-May/289491.html +https://github.com/chromeos-nvidia-androidtv/gnu-linux-on-acer-chromebook-13#copy-data-to-the-sd-card + +1. Patch U-Boot + +Open include/configs/tegra124-common.h + +Change: + +#define CONFIG_SYS_TEXT_BASE 0x80110000 + +to: + +#define CONFIG_SYS_TEXT_BASE 0x81000100 + + +2. Build U-Boot + + mkdir b + make -j8 O=b/nyan-big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all + + +3. Select a .its file + +Select something from doc/chromium which matches your board, or create your +own. + +Note that the device tree node is required, even though it is not actually +used by U-Boot. This is because the Chromebook expects to pass it to the +kernel, and crashes if it is not present. + + +4. Build and sign an image + + ./b/nyan-big/tools/mkimage -f doc/chromium/nyan-big.its u-boot-chromium.fit + echo test >dummy.txt + vbutil_kernel --arch arm --keyblock doc/chromium/devkeys/kernel.keyblock \ + --signprivate doc/chromium/devkeys/kernel_data_key.vbprivk \ + --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \ + --bootloader dummy.txt --pack u-boot.kpart + + +5. Prepare an SD card + + DISK=/dev/sdc # Replace with your actual SD card device + sudo cgpt create $DISK + sudo cgpt add -b 34 -s 32768 -P 1 -S 1 -t kernel $DISK + sudo cgpt add -b 32802 -s 2000000 -t rootfs $DISK + sudo gdisk $DISK # Enter command 'w' to write a protective MBR to the disk + + +6. Write U-Boot to the SD card + + sudo dd if=u-boot.kpart of=/dev/sdc1; sync + + +7. Start it up + +Reboot the device in dev mode. Make sure that you have USB booting enabled. To +do this, login as root (via Ctrl-Alt-forward_arrow) and type +'enable_dev_usb_boot'. You only need to do this once. + +Reboot the device with the SD card inserted. Press Clrl-U at the developer +mode screen. It should show something like the following on the display: + + U-Boot 2017.07-00637-g242eb42-dirty (May 22 2017 - 06:14:21 -0600) + + Model: Acer Chromebook 13 CB5-311 + Board: Google/NVIDIA Nyan-big, ID: 1 + + Net: No ethernet found. + Hit any key to stop autoboot: 0 + Tegra124 (Nyan-big) # + + +8. Known problems + +On the serial console the word MMC is chopped at the start of the line: + +C: sdhci@700b0000: 2, sdhci@700b0400: 1, sdhci@700b0600: 0 + +This is likely due to some problem with change-over of the serial driver +during relocation (or perhaps updating the clock setup in board_init()). + + +9. Notes + +To check that you copied the u-boot.its file correctly, use these commands. +You should see that the data at 0x100 in u-boot-chromium.fit is the first few +bytes of U-Boot: + + hd u-boot-chromium.fit |head -20 + ... + 00000100 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................| + + hd b/nyan-big/u-boot.bin |head + 00000000 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................| + + +The 'data' property of the FIT is set up to start at offset 0x100 bytes into +the file. The change to CONFIG_SYS_TEXT_BASE is also an offset of 0x100 bytes +from the load address. If this changes, you either need to modify U-Boot to be +fully relocatable, or expect it to hang. + + +Other notes +=========== + +flashrom +-------- + + Used to make a backup of your firmware, or to replace it. + + See: https://www.chromium.org/chromium-os/packages/cros-flashrom + + +coreboot +-------- + +Coreboot itself is not designed to actually boot an OS. Instead, a program +called Depthcharge is used. This originally came out of U-Boot and was then +heavily hacked and modified such that is is almost unrecognisable. It does +include a very small part of the U-Boot command-line interface but is not +usable as a general-purpose boot loader. + +In addition, it has a very unusual design in that it does not do device init +itself, but instead relies on coreboot. This is similar to (in U-Boot) having +a SPI driver with an empty probe() method, relying on whatever was set up +beforehand. It can be quite hard to figure out between these two code bases +what settings are actually used. When chain-loading into U-Boot we must be +careful to reinit anything that U-Boot expects. If not, some peripherals (or +the whole machine) may not work. This makes the process of chainloading more +complicated than it could be on some platforms. + +Finally, it supports only a subset of the U-Boot's FIT format. In particular +it uses a fixed address to load the FIT and does not support load/exec +addresses. This means that U-Boot must be able to boot from whatever +address Depthcharge happens to use (it is the CONFIG_KERNEL_START setting +in Depthcharge). In practice this means that the data in the kernel@1 FIT node +(see above) must start at the same address as U-Boot's CONFIG_SYS_TEXT_BASE. diff --git a/doc/chromium/devkeys/kernel.keyblock b/doc/chromium/devkeys/kernel.keyblock new file mode 100644 index 0000000..9740be4 Binary files /dev/null and b/doc/chromium/devkeys/kernel.keyblock differ diff --git a/doc/chromium/devkeys/kernel_data_key.vbprivk b/doc/chromium/devkeys/kernel_data_key.vbprivk new file mode 100644 index 0000000..8d392fb Binary files /dev/null and b/doc/chromium/devkeys/kernel_data_key.vbprivk differ -- cgit v0.10.2 From 385105983abf428de55eab9a1c2464889e94cc1b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:25 -0600 Subject: rockchip: Setup default PWM flags At present if the Signed-off-by: Simon Glass Fixes: 874ee59 (rockchip: pwm: implement pwm_set_invert()) diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 59eae09..28de62d 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -92,6 +92,7 @@ static int rk_pwm_probe(struct udevice *dev) return -EINVAL; } priv->freq = clk_get_rate(&clk); + priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE; return 0; } -- cgit v0.10.2 From 3238474b8f60b17e8a2ccd3e19dee9d836e7a277 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:26 -0600 Subject: rockchip: Fix regualtor typo in veyron This typo doesn't actually cause any problems, but is wrong. Fix it. Signed-off-by: Simon Glass diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts index 8aab607..2e6272b 100644 --- a/arch/arm/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -21,7 +21,7 @@ stdout-path = &uart2; }; - panel_regulator: panel-regualtor { + panel_regulator: panel-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; -- cgit v0.10.2 From 6f06ef57bb9031e322752343f7cf8f2408904452 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:27 -0600 Subject: rockchip: rk3288: Add error debugging to veyron_init() Add a debug() statement so we can see when something goes wrong with the regulator. Signed-off-by: Simon Glass diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 9894a25..18fd0dc 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -86,8 +86,10 @@ static int veyron_init(void) int ret; ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) + if (ret) { + debug("Cannot set regulator name\n"); return ret; + } /* Slowly raise to max CPU voltage to prevent overshoot */ ret = regulator_set_value(dev, 1200000); -- cgit v0.10.2 From f418676e9ab8b7ec5496fc83fe8ab2b92b26a58e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:28 -0600 Subject: rockchip: video: Add remove() methods Add remove() methods for EDP and VOP so that U-Boot can shut down the video on exit. This avoids leaving DMA running while booting Linux which can cause problems if Linux uses the frame buffer for something else. It also makes it clear what is needed to shut down video. While we are here, make rkvop_enable() static. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Squashed in 'rockchip: video: fix taking the VOP device out of standby': Signed-off-by: Philipp Tomsich diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c index e3e1ec7..3a5740a 100644 --- a/drivers/video/rockchip/rk3288_vop.c +++ b/drivers/video/rockchip/rk3288_vop.c @@ -70,6 +70,19 @@ static int rk3288_vop_probe(struct udevice *dev) return rk_vop_probe(dev); } +static int rk_vop_remove(struct udevice *dev) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + + setbits_le32(®s->sys_ctrl, V_STANDBY_EN(1)); + + /* wait frame complete (60Hz) to enter standby */ + mdelay(17); + + return 0; +} + struct rkvop_driverdata rk3288_driverdata = { .features = VOP_FEATURE_OUTPUT_10BIT, .set_pin_polarity = rk3288_set_pin_polarity, @@ -91,5 +104,6 @@ U_BOOT_DRIVER(rk_vop) = { .ops = &rk3288_vop_ops, .bind = rk_vop_bind, .probe = rk3288_vop_probe, + .remove = rk_vop_remove, .priv_auto_alloc_size = sizeof(struct rk_vop_priv), }; diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index 4e2030e..1527f96 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -1004,7 +1004,20 @@ static int rk_edp_ofdata_to_platdata(struct udevice *dev) return 0; } -int rk_edp_probe(struct udevice *dev) +static int rk_edp_remove(struct udevice *dev) +{ + struct rk_edp_priv *priv = dev_get_priv(dev); + struct rk3288_edp *regs = priv->regs; + + setbits_le32(®s->video_ctl_1, VIDEO_MUTE); + clrbits_le32(®s->video_ctl_1, VIDEO_EN); + clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL); + setbits_le32(®s->func_en_1, SW_FUNC_EN_N); + + return 0; +} + +static int rk_edp_probe(struct udevice *dev) { struct display_plat *uc_plat = dev_get_uclass_platdata(dev); struct rk_edp_priv *priv = dev_get_priv(dev); @@ -1080,5 +1093,6 @@ U_BOOT_DRIVER(dp_rockchip) = { .ops = &dp_rockchip_ops, .ofdata_to_platdata = rk_edp_ofdata_to_platdata, .probe = rk_edp_probe, + .remove = rk_edp_remove, .priv_auto_alloc_size = sizeof(struct rk_edp_priv), }; -- cgit v0.10.2 From 6b5a09aa385693f5921a96d93197f5c40e7f37f7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:29 -0600 Subject: rockchip: video: Take the vop device out of standby On reset the standby bit is clear, but if U-Boot is chain-loaded from another boot loader it may be set. Clear it before starting up video so that it works correctly. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Squashed in 'rockchip: video: fix taking the VOP device out of standby': Signed-off-by: Philipp Tomsich diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index 9343796..c979049 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -105,6 +105,9 @@ static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode) struct rk_vop_priv *priv = dev_get_priv(dev); struct rk3288_vop *regs = priv->regs; + /* remove from standby */ + clrbits_le32(®s->sys_ctrl, V_STANDBY_EN(1)); + switch (mode) { case VOP_MODE_HDMI: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, -- cgit v0.10.2 From ed54b1918e7745ec3af59f52e9e51048dfc0ad98 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:30 -0600 Subject: rockchip: jerry: Add a .its file for chromium Add a sample .its file for booting U-Boot on a jerry Chromebook. Signed-off-by: Simon Glass diff --git a/doc/chromium/chromebook_jerry.its b/doc/chromium/chromebook_jerry.its new file mode 100644 index 0000000..8cff840 --- /dev/null +++ b/doc/chromium/chromebook_jerry.its @@ -0,0 +1,42 @@ +/dts-v1/; + +/ { + description = "U-Boot mainline"; + #address-cells = <1>; + + images { + kernel@1 { + description = "U-Boot mainline"; + type = "kernel_noload"; + arch = "arm"; + os = "linux"; + data = /incbin/("../../b/chromebook_jerry/u-boot.bin"); + compression = "none"; + load = <0>; + entry = <0>; + hash@2 { + algo = "sha1"; + }; + }; + + fdt@1{ + description = "rk3288-veryron-jerry.dtb"; + data = /incbin/("../../b/chromebook_jerry/u-boot.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + hash@1{ + algo = "sha1"; + }; + }; + }; + + configurations { + default = "config@1"; + config@1 { + description = "Boot U-Boot"; + kernel = "kernel@1"; + fdt = "fdt@1"; + }; + }; +}; -- cgit v0.10.2 From b223c1aeade5b29c13347354edd1ce4e66f60b7f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:31 -0600 Subject: rockchip: rk3288: Convert clock driver to use shifted masks Shifted masks are the standard approach with rockchip since it allows use of the mask without shifting it each time. Update the definitions and the driver to match. Signed-off-by: Simon Glass diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index d575f4a..cb0a935 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -64,135 +64,137 @@ check_member(rk3288_cru, cru_emmc_con[1], 0x021c); /* CRU_CLKSEL11_CON */ enum { HSICPHY_DIV_SHIFT = 8, - HSICPHY_DIV_MASK = 0x3f, + HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT, MMC0_PLL_SHIFT = 6, - MMC0_PLL_MASK = 3, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, MMC0_PLL_SELECT_CODEC = 0, MMC0_PLL_SELECT_GENERAL, MMC0_PLL_SELECT_24MHZ, MMC0_DIV_SHIFT = 0, - MMC0_DIV_MASK = 0x3f, + MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, }; /* CRU_CLKSEL12_CON */ enum { EMMC_PLL_SHIFT = 0xe, - EMMC_PLL_MASK = 3, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, EMMC_PLL_SELECT_CODEC = 0, EMMC_PLL_SELECT_GENERAL, EMMC_PLL_SELECT_24MHZ, EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0x3f, + EMMC_DIV_MASK = 0x3f < EMMC_DIV_SHIFT, SDIO0_PLL_SHIFT = 6, - SDIO0_PLL_MASK = 3, + SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT, SDIO0_PLL_SELECT_CODEC = 0, SDIO0_PLL_SELECT_GENERAL, SDIO0_PLL_SELECT_24MHZ, SDIO0_DIV_SHIFT = 0, - SDIO0_DIV_MASK = 0x3f, + SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT, }; /* CRU_CLKSEL21_CON */ enum { - MAC_DIV_CON_SHIFT = 0xf, - MAC_DIV_CON_MASK = 0x1f, + MAC_DIV_CON_SHIFT = 0xf, + MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT, - RMII_EXTCLK_SHIFT = 4, - RMII_EXTCLK_MASK = 1, + RMII_EXTCLK_SHIFT = 4, + RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT, RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, RMII_EXTCLK_SELECT_EXT_CLK = 1, - EMAC_PLL_SHIFT = 0, - EMAC_PLL_MASK = 0x3, - EMAC_PLL_SELECT_NEW = 0x0, - EMAC_PLL_SELECT_CODEC = 0x1, - EMAC_PLL_SELECT_GENERAL = 0x2, + EMAC_PLL_SHIFT = 0, + EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT, + EMAC_PLL_SELECT_NEW = 0x0, + EMAC_PLL_SELECT_CODEC = 0x1, + EMAC_PLL_SELECT_GENERAL = 0x2, }; /* CRU_CLKSEL25_CON */ enum { SPI1_PLL_SHIFT = 0xf, - SPI1_PLL_MASK = 1, + SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT, SPI1_PLL_SELECT_CODEC = 0, SPI1_PLL_SELECT_GENERAL, SPI1_DIV_SHIFT = 8, - SPI1_DIV_MASK = 0x7f, + SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT, SPI0_PLL_SHIFT = 7, - SPI0_PLL_MASK = 1, + SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT, SPI0_PLL_SELECT_CODEC = 0, SPI0_PLL_SELECT_GENERAL, SPI0_DIV_SHIFT = 0, - SPI0_DIV_MASK = 0x7f, + SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT, }; /* CRU_CLKSEL37_CON */ enum { PCLK_CORE_DBG_DIV_SHIFT = 9, - PCLK_CORE_DBG_DIV_MASK = 0x1f, + PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT, ATCLK_CORE_DIV_CON_SHIFT = 4, - ATCLK_CORE_DIV_CON_MASK = 0x1f, + ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT, CLK_L2RAM_DIV_SHIFT = 0, - CLK_L2RAM_DIV_MASK = 7, + CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT, }; /* CRU_CLKSEL39_CON */ enum { ACLK_HEVC_PLL_SHIFT = 0xe, - ACLK_HEVC_PLL_MASK = 3, + ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT, ACLK_HEVC_PLL_SELECT_CODEC = 0, ACLK_HEVC_PLL_SELECT_GENERAL, ACLK_HEVC_PLL_SELECT_NEW, ACLK_HEVC_DIV_SHIFT = 8, - ACLK_HEVC_DIV_MASK = 0x1f, + ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT, SPI2_PLL_SHIFT = 7, - SPI2_PLL_MASK = 1, + SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT, SPI2_PLL_SELECT_CODEC = 0, SPI2_PLL_SELECT_GENERAL, SPI2_DIV_SHIFT = 0, - SPI2_DIV_MASK = 0x7f, + SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT, }; /* CRU_MODE_CON */ enum { + CRU_MODE_MASK = 3, + NPLL_MODE_SHIFT = 0xe, - NPLL_MODE_MASK = 3, + NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT, NPLL_MODE_SLOW = 0, NPLL_MODE_NORMAL, NPLL_MODE_DEEP, GPLL_MODE_SHIFT = 0xc, - GPLL_MODE_MASK = 3, + GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT, GPLL_MODE_SLOW = 0, GPLL_MODE_NORMAL, GPLL_MODE_DEEP, CPLL_MODE_SHIFT = 8, - CPLL_MODE_MASK = 3, + CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT, CPLL_MODE_SLOW = 0, CPLL_MODE_NORMAL, CPLL_MODE_DEEP, DPLL_MODE_SHIFT = 4, - DPLL_MODE_MASK = 3, + DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, DPLL_MODE_SLOW = 0, DPLL_MODE_NORMAL, DPLL_MODE_DEEP, APLL_MODE_SHIFT = 0, - APLL_MODE_MASK = 3, + APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT, APLL_MODE_SLOW = 0, APLL_MODE_NORMAL, APLL_MODE_DEEP, @@ -201,21 +203,21 @@ enum { /* CRU_APLL_CON0 */ enum { CLKR_SHIFT = 8, - CLKR_MASK = 0x3f, + CLKR_MASK = 0x3f << CLKR_SHIFT, CLKOD_SHIFT = 0, - CLKOD_MASK = 0xf, + CLKOD_MASK = 0xf << CLKOD_SHIFT, }; /* CRU_APLL_CON1 */ enum { LOCK_SHIFT = 0x1f, - LOCK_MASK = 1, + LOCK_MASK = 1 << LOCK_SHIFT, LOCK_UNLOCK = 0, LOCK_LOCK, CLKF_SHIFT = 0, - CLKF_MASK = 0x1fff, + CLKF_MASK = 0x1fff << CLKF_SHIFT, }; #endif diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 14851ca..f6ef7ec 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -59,14 +59,14 @@ enum { PLL_RESET_SHIFT = 5, /* CLKSEL0 */ - CORE_SEL_PLL_MASK = 1, CORE_SEL_PLL_SHIFT = 15, - A17_DIV_MASK = 0x1f, + CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, A17_DIV_SHIFT = 8, - MP_DIV_MASK = 0xf, + A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, MP_DIV_SHIFT = 4, - M0_DIV_MASK = 0xf, + MP_DIV_MASK = 0xf << MP_DIV_SHIFT, M0_DIV_SHIFT = 0, + M0_DIV_MASK = 0xf << M0_DIV_SHIFT, /* CLKSEL1: pd bus clk pll sel: codec or general */ PD_BUS_SEL_PLL_MASK = 15, @@ -75,41 +75,41 @@ enum { /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ PD_BUS_PCLK_DIV_SHIFT = 12, - PD_BUS_PCLK_DIV_MASK = 7, + PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ PD_BUS_HCLK_DIV_SHIFT = 8, - PD_BUS_HCLK_DIV_MASK = 3, + PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ PD_BUS_ACLK_DIV0_SHIFT = 3, - PD_BUS_ACLK_DIV0_MASK = 0x1f, + PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, PD_BUS_ACLK_DIV1_SHIFT = 0, - PD_BUS_ACLK_DIV1_MASK = 0x7, + PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, /* * CLKSEL10 * peripheral bus pclk div: * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 */ - PERI_SEL_PLL_MASK = 1, PERI_SEL_PLL_SHIFT = 15, + PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, PERI_SEL_CPLL = 0, PERI_SEL_GPLL, PERI_PCLK_DIV_SHIFT = 12, - PERI_PCLK_DIV_MASK = 3, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ PERI_HCLK_DIV_SHIFT = 8, - PERI_HCLK_DIV_MASK = 3, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, /* * peripheral bus aclk div: * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) */ PERI_ACLK_DIV_SHIFT = 0, - PERI_ACLK_DIV_MASK = 0x1f, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, SOCSTS_DPLL_LOCK = 1 << 5, SOCSTS_APLL_LOCK = 1 << 6, @@ -154,8 +154,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, /* enter reset */ rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); - rk_clrsetreg(&pll->con0, - CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK, + rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); @@ -198,7 +197,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, } /* pll enter slow-mode */ - rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_SLOW << DPLL_MODE_SHIFT); rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); @@ -208,7 +207,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, udelay(1); /* PLL enter normal-mode */ - rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); return 0; @@ -296,7 +295,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, { /* Assuming mac_clk is fed by an external clock */ rk_clrsetreg(&cru->cru_clksel_con[21], - RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT, + RMII_EXTCLK_MASK, RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); return 0; @@ -313,7 +312,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, if (ret) return ret; - rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, NPLL_MODE_SLOW << NPLL_MODE_SHIFT); rkclk_set_pll(cru, CLK_NEW, &npll_config); @@ -324,7 +323,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, udelay(1); } - rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, NPLL_MODE_NORMAL << NPLL_MODE_SHIFT); /* vop dclk source clk: npll,dclk_div: 1 */ @@ -352,8 +351,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) /* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_MASK | CPLL_MODE_MASK, GPLL_MODE_SLOW << GPLL_MODE_SHIFT | CPLL_MODE_SLOW << CPLL_MODE_SHIFT); @@ -382,10 +380,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) PD_BUS_ACLK_HZ && pclk_div < 0x7); rk_clrsetreg(&cru->cru_clksel_con[1], - PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT | - PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT | - PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT | - PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT, + PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | + PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, pclk_div << PD_BUS_PCLK_DIV_SHIFT | hclk_div << PD_BUS_HCLK_DIV_SHIFT | aclk_div << PD_BUS_ACLK_DIV0_SHIFT | @@ -407,9 +403,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) PERI_ACLK_HZ && (pclk_div < 0x4)); rk_clrsetreg(&cru->cru_clksel_con[10], - PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | - PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | - PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | + PERI_ACLK_DIV_MASK, PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | pclk_div << PERI_PCLK_DIV_SHIFT | hclk_div << PERI_HCLK_DIV_SHIFT | @@ -417,8 +412,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) /* PLL enter normal-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_MASK | CPLL_MODE_MASK, GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); } @@ -427,8 +421,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) { /* pll enter slow-mode */ - rk_clrsetreg(&cru->cru_mode_con, - APLL_MODE_MASK << APLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, APLL_MODE_SLOW << APLL_MODE_SHIFT); rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); @@ -444,10 +437,8 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz */ rk_clrsetreg(&cru->cru_clksel_con[0], - CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT | - A17_DIV_MASK << A17_DIV_SHIFT | - MP_DIV_MASK << MP_DIV_SHIFT | - M0_DIV_MASK << M0_DIV_SHIFT, + CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | + M0_DIV_MASK, 0 << A17_DIV_SHIFT | 3 << MP_DIV_SHIFT | 1 << M0_DIV_SHIFT); @@ -457,16 +448,14 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz */ rk_clrsetreg(&cru->cru_clksel_con[37], - CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT | - ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT | - PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT, + CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | + PCLK_CORE_DBG_DIV_MASK, 1 << CLK_L2RAM_DIV_SHIFT | 3 << ATCLK_CORE_DIV_CON_SHIFT | 3 << PCLK_CORE_DBG_DIV_SHIFT); /* PLL enter normal-mode */ - rk_clrsetreg(&cru->cru_mode_con, - APLL_MODE_MASK << APLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, APLL_MODE_NORMAL << APLL_MODE_SHIFT); } @@ -486,16 +475,16 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, con = readl(&cru->cru_mode_con); shift = clk_shift[clk_id]; - switch ((con >> shift) & APLL_MODE_MASK) { + switch ((con >> shift) & CRU_MODE_MASK) { case APLL_MODE_SLOW: return OSC_HZ; case APLL_MODE_NORMAL: /* normal mode */ con = readl(&pll->con0); - no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; - nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; + no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; + nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; con = readl(&pll->con1); - nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; + nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; return (24 * nf / (nr * no)) * 1000000; case APLL_MODE_DEEP: @@ -515,20 +504,20 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, case HCLK_EMMC: case SCLK_EMMC: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; - div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; break; case HCLK_SDMMC: case SCLK_SDMMC: con = readl(&cru->cru_clksel_con[11]); - mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; - div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; break; case HCLK_SDIO0: case SCLK_SDIO0: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK; - div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK; + mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; + div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; break; default: return -EINVAL; @@ -561,24 +550,21 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, case HCLK_EMMC: case SCLK_EMMC: rk_clrsetreg(&cru->cru_clksel_con[12], - EMMC_PLL_MASK << EMMC_PLL_SHIFT | - EMMC_DIV_MASK << EMMC_DIV_SHIFT, + EMMC_PLL_MASK | EMMC_DIV_MASK, mux << EMMC_PLL_SHIFT | (src_clk_div - 1) << EMMC_DIV_SHIFT); break; case HCLK_SDMMC: case SCLK_SDMMC: rk_clrsetreg(&cru->cru_clksel_con[11], - MMC0_PLL_MASK << MMC0_PLL_SHIFT | - MMC0_DIV_MASK << MMC0_DIV_SHIFT, + MMC0_PLL_MASK | MMC0_DIV_MASK, mux << MMC0_PLL_SHIFT | (src_clk_div - 1) << MMC0_DIV_SHIFT); break; case HCLK_SDIO0: case SCLK_SDIO0: rk_clrsetreg(&cru->cru_clksel_con[12], - SDIO0_PLL_MASK << SDIO0_PLL_SHIFT | - SDIO0_DIV_MASK << SDIO0_DIV_SHIFT, + SDIO0_PLL_MASK | SDIO0_DIV_MASK, mux << SDIO0_PLL_SHIFT | (src_clk_div - 1) << SDIO0_DIV_SHIFT); break; @@ -598,18 +584,18 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, switch (periph) { case SCLK_SPI0: con = readl(&cru->cru_clksel_con[25]); - mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK; - div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK; + mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; + div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; break; case SCLK_SPI1: con = readl(&cru->cru_clksel_con[25]); - mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK; - div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK; + mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; + div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; break; case SCLK_SPI2: con = readl(&cru->cru_clksel_con[39]); - mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK; - div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK; + mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; + div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; break; default: return -EINVAL; @@ -629,22 +615,19 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, switch (periph) { case SCLK_SPI0: rk_clrsetreg(&cru->cru_clksel_con[25], - SPI0_PLL_MASK << SPI0_PLL_SHIFT | - SPI0_DIV_MASK << SPI0_DIV_SHIFT, + SPI0_PLL_MASK | SPI0_DIV_MASK, SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | src_clk_div << SPI0_DIV_SHIFT); break; case SCLK_SPI1: rk_clrsetreg(&cru->cru_clksel_con[25], - SPI1_PLL_MASK << SPI1_PLL_SHIFT | - SPI1_DIV_MASK << SPI1_DIV_SHIFT, + SPI1_PLL_MASK | SPI1_DIV_MASK, SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | src_clk_div << SPI1_DIV_SHIFT); break; case SCLK_SPI2: rk_clrsetreg(&cru->cru_clksel_con[39], - SPI2_PLL_MASK << SPI2_PLL_SHIFT | - SPI2_DIV_MASK << SPI2_DIV_SHIFT, + SPI2_PLL_MASK | SPI2_DIV_MASK, SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | src_clk_div << SPI2_DIV_SHIFT); break; -- cgit v0.10.2 From d3cb46aa8c41e85b07ccf494ca90f3a7fe19373d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:32 -0600 Subject: rockchip: Init clocks again when chain-loading Detect with a previous boot loader has already set up the clocks and set them up again so that U-Boot gets what it expects. Signed-off-by: Simon Glass diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index f6ef7ec..792ee76 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -131,10 +131,8 @@ enum { /* Keep divisors as low as possible to reduce jitter and power usage */ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); -#ifdef CONFIG_SPL_BUILD static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); -#endif static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) @@ -340,9 +338,8 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, return 0; } -#endif +#endif /* CONFIG_SPL_BUILD */ -#ifdef CONFIG_SPL_BUILD static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) { u32 aclk_div; @@ -416,7 +413,6 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); } -#endif void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) { @@ -786,6 +782,7 @@ static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) static int rk3288_clk_probe(struct udevice *dev) { struct rk3288_clk_priv *priv = dev_get_priv(dev); + bool init_clocks = false; priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (IS_ERR(priv->grf)) @@ -796,8 +793,24 @@ static int rk3288_clk_probe(struct udevice *dev) priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif - rkclk_init(priv->cru, priv->grf); + init_clocks = true; #endif + if (!(gd->flags & GD_FLG_RELOC)) { + u32 reg; + + /* + * Init clocks in U-Boot proper if the NPLL is runnning. This + * indicates that a previous boot loader set up the clocks, so + * we need to redo it. U-Boot's SPL does not set this clock. + */ + reg = readl(&priv->cru->cru_mode_con); + if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == + NPLL_MODE_NORMAL) + init_clocks = true; + } + + if (init_clocks) + rkclk_init(priv->cru, priv->grf); return 0; } -- cgit v0.10.2 From fe974716326ce2eee4bcac710ce7ec007919845e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:33 -0600 Subject: rockchip: rk3288: Allow setting up clocks in U-Boot proper If U-Boot is chain-loaded from a previous boot loader we must set up the clocks the way U-Boot wants them. Add code for this. It will do nothing if SPL has already done the job. Signed-off-by: Simon Glass diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 18fd0dc..a354d99 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -309,3 +309,38 @@ U_BOOT_CMD( "display information about clocks", "" ); + +#define GRF_SOC_CON2 0xff77024c + +int board_early_init_f(void) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return ret; + } + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + return ret; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + return ret; + } + rk_setreg(GRF_SOC_CON2, 1 << 0); + + return 0; +} diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 6fc0dcc..bb88058 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_CMD_IMLS is not set -- cgit v0.10.2 From f8e468973b016140650b903328b10288a17343d9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:34 -0600 Subject: rockchip: Enable the video display banner Show the U-Boot banner and board information on the video display during boot. Signed-off-by: Simon Glass diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 9d183ce..0573571 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -54,4 +54,6 @@ #define CONFIG_ENV_OFFSET (96 * 1024) #endif +#define CONFIG_DISPLAY_BOARDINFO_LATE + #endif /* _ROCKCHIP_COMMON_H_ */ -- cgit v0.10.2 From 6b1bd076e801123d0d419892b0ac8f1311adb13f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:35 -0600 Subject: rockchip: jerry: Disable CONFIG_CONSOLE_SCROLL_LINES The display on jerry is so fast that this option is not needed. Drop it so that the display scrolls more smoothly. Signed-off-by: Simon Glass diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index bb88058..63de674 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -75,7 +75,6 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -- cgit v0.10.2 From fe67eaccd0d265ac01974980edad5395ade488eb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 May 2017 17:57:36 -0600 Subject: README: Add instructions for chain-loading U-Boot on jerry Add instructions for chromebook_jerry. Signed-off-by: Simon Glass diff --git a/doc/README.chromium b/doc/README.chromium index 61e285d..7bf4d87 100644 --- a/doc/README.chromium +++ b/doc/README.chromium @@ -145,6 +145,76 @@ from the load address. If this changes, you either need to modify U-Boot to be fully relocatable, or expect it to hang. +chromebook_jerry +---------------- + +The instruction are similar to those for Nyan with changes as noted below: + +1. Patch U-Boot + +Open include/configs/rk3288_common.h + +Change: + +#define CONFIG_SYS_TEXT_BASE 0x00100000 + +to: + +#define CONFIG_SYS_TEXT_BASE 0x02000100 + + + +2. Build U-Boot + + mkdir b + make -j8 O=b/chromebook_jerry CROSS_COMPILE=arm-linux-gnueabi- \ + chromebook_jerry_defconfig all + + +3. See above + +4. Build and sign an image + + ./b/chromebook_jerry/tools/mkimage -f doc/chromium/chromebook_jerry.its \ + u-boot-chromium.fit + echo test >dummy.txt + vbutil_kernel --arch arm --keyblock doc/chromium/devkeys/kernel.keyblock \ + --signprivate doc/chromium/devkeys/kernel_data_key.vbprivk \ + --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \ + --bootloader dummy.txt --pack u-boot.kpart + + +5. See above + +6. See above + +7. Start it up + +Reboot the device in dev mode. Make sure that you have USB booting enabled. To +do this, login as root (via Ctrl-Alt-forward_arrow) and type +'enable_dev_usb_boot'. You only need to do this once. + +Reboot the device with the SD card inserted. Press Clrl-U at the developer +mode screen. It should show something like the following on the display: + + U-Boot 2017.05-00649-g72acdbf-dirty (May 29 2017 - 14:57:05 -0600) + + Model: Google Jerry + Net: Net Initialization Skipped + No ethernet found. + Hit any key to stop autoboot: 0 + + +8. Known problems + +None as yet. + + +9. Notes + +None as yet. + + Other notes =========== -- cgit v0.10.2 From b0e994c29e726dc0ba02a44adbd050f5f9f0b995 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Thu, 8 Jun 2017 03:07:08 +0200 Subject: buildman: disable localized and unicode output of all build tools Build tools like Make, gcc or binutils support localized output or unicode encoded output dependent on the default system locale. This is not useful for buildman, where we want reproducible warning or error messages or where the output of binutils is further processed. Signed-off-by: Daniel Schwierzeck diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 5cf97ac..2076323 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -144,7 +144,9 @@ class Toolchain: """Returns an environment for using the toolchain. Thie takes the current environment and adds CROSS_COMPILE so that - the tool chain will operate correctly. + the tool chain will operate correctly. This also disables localized + output and possibly unicode encoded output of all build tools by + adding LC_ALL=C. Args: full_path: Return the full path in CROSS_COMPILE and don't set @@ -159,6 +161,8 @@ class Toolchain: env['CROSS_COMPILE'] = wrapper + self.cross env['PATH'] = self.path + ':' + env['PATH'] + env['LC_ALL'] = 'C' + return env -- cgit v0.10.2 From aafbe82fb6ffc233f0db57b675c2577cf37c846b Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Thu, 8 Jun 2017 03:07:09 +0200 Subject: buildman: properly translate strings for log and err files to ASCII The build output can still produce unicode encoded output. But in the buildman's log and err files we only want plain ASCII characters. To handle all situations with unicode and non-unicode output, encode the stdout and stderr strings to UTF-8 and afterwards to ASCII with replacing all special characters. Signed-off-by: Daniel Schwierzeck diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index acaf500..9e8ca80 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -280,13 +280,15 @@ class BuilderThread(threading.Thread): outfile = os.path.join(build_dir, 'log') with open(outfile, 'w') as fd: if result.stdout: - fd.write(result.stdout.encode('latin-1', 'ignore')) + # We don't want unicode characters in log files + fd.write(result.stdout.decode('UTF-8').encode('ASCII', 'replace')) errfile = self.builder.GetErrFile(result.commit_upto, result.brd.target) if result.stderr: with open(errfile, 'w') as fd: - fd.write(result.stderr.encode('latin-1', 'ignore')) + # We don't want unicode characters in log files + fd.write(result.stderr.decode('UTF-8').encode('ASCII', 'replace')) elif os.path.exists(errfile): os.remove(errfile) -- cgit v0.10.2 From 9620d87259572ef21f0df60988d9a932ca673779 Mon Sep 17 00:00:00 2001 From: Hannes Schmelzer Date: Tue, 30 May 2017 15:05:44 +0200 Subject: cmd/fdt: support single value replacement within an array With this commit we can modify single values within an array of a dts property. This is useful if we have for example a pwm-backlight where we want to modifiy the pwm frequency per u-boot script. The pwm is described in dts like this: backlight { pwms = <0x0000002b 0x00000000 0x004c4b40>; }; For changing the frequency, here the 3rd parameter, we simply type: fdt set /backlight pwms ; For doing all this we: - backup the property content into our 'SCRATCHPAD' - only modify the array-cell if the new content doesn't start with '?' Signed-off-by: Hannes Schmelzer Reviewed-by: Simon Glass diff --git a/cmd/fdt.c b/cmd/fdt.c index a21415d..e55102a 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -257,6 +257,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *prop; /* property */ int nodeoffset; /* node offset from libfdt */ static char data[SCRATCHPAD]; /* storage for the property */ + const void *ptmp; int len; /* new length of the property */ int ret; /* return value */ @@ -268,13 +269,6 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) pathp = argv[2]; prop = argv[3]; - if (argc == 4) { - len = 0; - } else { - ret = fdt_parse_prop(&argv[4], argc - 4, data, &len); - if (ret != 0) - return ret; - } nodeoffset = fdt_path_offset (working_fdt, pathp); if (nodeoffset < 0) { @@ -286,6 +280,21 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } + if (argc == 4) { + len = 0; + } else { + ptmp = fdt_getprop(working_fdt, nodeoffset, prop, &len); + if (len > SCRATCHPAD) { + printf("prop (%d) doesn't fit in scratchpad!\n", + len); + return 1; + } + memcpy(data, ptmp, len); + ret = fdt_parse_prop(&argv[4], argc - 4, data, &len); + if (ret != 0) + return ret; + } + ret = fdt_setprop(working_fdt, nodeoffset, prop, data, len); if (ret < 0) { printf ("libfdt fdt_setprop(): %s\n", fdt_strerror(ret)); @@ -766,7 +775,11 @@ static int fdt_parse_prop(char * const *newval, int count, char *data, int *len) cp = newp; tmp = simple_strtoul(cp, &newp, 0); - *(fdt32_t *)data = cpu_to_fdt32(tmp); + if (*cp != '?') + *(fdt32_t *)data = cpu_to_fdt32(tmp); + else + newp++; + data += 4; *len += 4; -- cgit v0.10.2