/* * Device Tree Source for UniPhier PXs3 SoC * * Copyright (C) 2017 Socionext Inc. * Author: Masahiro Yamada * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ /memreserve/ 0x80000000 0x00080000; / { compatible = "socionext,uniphier-pxs3"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; }; }; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x000>; enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x001>; enable-method = "psci"; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x002>; enable-method = "psci"; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x003>; enable-method = "psci"; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; clocks { refclk: ref { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; clock-frequency = <58820000>; }; serial1: serial@54006900 { compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; clock-frequency = <58820000>; }; serial2: serial@54006a00 { compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; clock-frequency = <58820000>; }; serial3: serial@54006b00 { compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; clock-frequency = <58820000>; }; i2c0: i2c@58780000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; reg = <0x58780000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 41 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; clock-frequency = <100000>; }; i2c1: i2c@58781000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; reg = <0x58781000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 42 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; clock-frequency = <100000>; }; i2c2: i2c@58782000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; reg = <0x58782000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 43 4>; clocks = <&peri_clk 6>; clock-frequency = <100000>; }; i2c3: i2c@58783000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; reg = <0x58783000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 44 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; clock-frequency = <100000>; }; /* chip-internal connection for HDMI */ i2c6: i2c@58786000 { compatible = "socionext,uniphier-fi2c"; reg = <0x58786000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 26 4>; clocks = <&peri_clk 10>; clock-frequency = <400000>; }; system_bus: system-bus@58c00000 { compatible = "socionext,uniphier-system-bus"; status = "disabled"; reg = <0x58c00000 0x400>; #address-cells = <2>; #size-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_system_bus>; }; smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; sdctrl@59810000 { compatible = "socionext,uniphier-pxs3-sdctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; sd_clk: clock { compatible = "socionext,uniphier-pxs3-sd-clock"; #clock-cells = <1>; }; sd_rst: reset { compatible = "socionext,uniphier-pxs3-sd-reset"; #reset-cells = <1>; }; }; perictrl@59820000 { compatible = "socionext,uniphier-pxs3-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; peri_clk: clock { compatible = "socionext,uniphier-pxs3-peri-clock"; #clock-cells = <1>; }; peri_rst: reset { compatible = "socionext,uniphier-pxs3-peri-reset"; #reset-cells = <1>; }; }; emmc: sdhc@5a000000 { compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; status = "disabled"; reg = <0x5a000000 0x400>; interrupts = <0 78 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc_1v8>; clocks = <&sys_clk 4>; bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; }; sd: sdhc@5a400000 { compatible = "socionext,uniphier-sdhc"; status = "disabled"; reg = <0x5a400000 0x800>; interrupts = <0 76 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd>; clocks = <&sd_clk 0>; reset-names = "host"; resets = <&sd_rst 0>; bus-width = <4>; cap-sd-highspeed; }; soc-glue@5f800000 { compatible = "socionext,uniphier-pxs3-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; pinctrl: pinctrl { compatible = "socionext,uniphier-pxs3-pinctrl"; }; }; aidet@5fc20000 { compatible = "simple-mfd", "syscon"; reg = <0x5fc20000 0x200>; }; gic: interrupt-controller@5fe00000 { compatible = "arm,gic-v3"; reg = <0x5fe00000 0x10000>, /* GICD */ <0x5fe80000 0x80000>; /* GICR */ interrupt-controller; #interrupt-cells = <3>; interrupts = <1 9 4>; }; sysctrl@61840000 { compatible = "socionext,uniphier-pxs3-sysctrl", "simple-mfd", "syscon"; reg = <0x61840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-pxs3-clock"; #clock-cells = <1>; }; sys_rst: reset { compatible = "socionext,uniphier-pxs3-reset"; #reset-cells = <1>; }; }; nand: nand@68000000 { compatible = "socionext,denali-nand-v5b"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clocks = <&sys_clk 2>; nand-ecc-strength = <8>; }; }; }; /include/ "uniphier-pinctrl.dtsi"