/*
 * Copyright 2017 Scalys B.V.
 * opensource@scalys.com
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h>
#endif
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <ahci.h>
#include <mmc.h>
#include <scsi.h>
#include <fsl_esdhc.h>
#include <environment.h>
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
#include <fsl_csu.h>
#include "usb_grapeboard.h"
#include <../../../include/generated/autoconf.h>

DECLARE_GLOBAL_DATA_PTR;

/* GPIO1 registers */
#define CONFIG_SYS_GPIO1 0x2300000
#define CONFIG_SYS_GPIO2 0x2310000
#define GPIO_MASK(shift) (0x80000000 >> shift)

/* =====================================================
 * Grapeboard ExPI mapping (* pin name at ls1012a side)
 * Note: The secondary options require modified RCW.
 * =====================================================
 *                 3V3 -| 1       2|- 5V0
 *             I2C_SDA -| 3       4|- 5V0
 *             I2C_SCL -| 5       6|- GND
 *          CLK0_25MHZ -| 7       8|- UART_TXD
 *                 GND -| 9      10|- UART_RXD
 *           GPIO1_27* -|11      12|- GPIO2_04*
 *           GPIO2_05* -|13      14|- GND
 *           GPIO2_06* -|15      16|- GPIO2_07*
 *                 3V3 -|17      18|- GPIO2_09*
 *  SPI_MOSI/GPIO1_24* -|19      20|- GND
 *  SPI_MISO/GPIO1_28* -|21      22|- GPIO2_10*
 *   SPI_CLK/GPIO1_29* -|23      24|- SPI_CE0/GPIO1_25*
 *                 GND -|25      26|- SPI_CE1/GPIO1_26*
 */

/* ExPI gpios */
#define gpio1_27 GPIO_MASK(27) /* ExPI pin 11 */
#define gpio2_04 GPIO_MASK(4)  /* ExPI pin 12 */
#define gpio2_05 GPIO_MASK(5)  /* ExPI pin 13 */
#define gpio2_06 GPIO_MASK(6)  /* ExPI pin 15 */
#define gpio2_07 GPIO_MASK(7)  /* ExPI pin 16 */
#define gpio2_09 GPIO_MASK(9)  /* ExPI pin 18 */
#define gpio2_10 GPIO_MASK(10) /* ExPI pin 22 */

/* M2 gpios */
#define gpio1_22 GPIO_MASK(22)
#define gpio2_00 GPIO_MASK(0)
#define gpio2_01 GPIO_MASK(1)
#define gpio2_02 GPIO_MASK(2)
#define M2_CFG1  GPIO_MASK(11) /* gpio2_11 */
#define M2_CFG0  GPIO_MASK(12) /* gpio2_12 */
#define M2_CFG2  GPIO_MASK(13) /* gpio2_13 */
#define M2_CFG3  GPIO_MASK(14) /* gpio2_14 */

/* Other gpios */
#define QSPI_MUX_N_MASK (0x80000000 >> 3) /* gpio2_03 */

int checkboard(void)
{
	struct ccsr_gpio *pgpio = (void *)(CONFIG_SYS_GPIO2);
	int m2_config = 0;

	puts("Board: Grape board\n");
	/* set QSPI chip select muxing to 0 */

	setbits_be32(&pgpio->gpdir, QSPI_MUX_N_MASK);
	clrbits_be32(&pgpio->gpdat, QSPI_MUX_N_MASK);

	usb_hub_init();


	/* M.2 init: read input values of M.2 config signals */
	clrbits_be32(&pgpio->gpdir, (M2_CFG0 | M2_CFG1 | M2_CFG2 | M2_CFG3));
	m2_config = (in_be32(&pgpio->gpdat) & (M2_CFG0 | M2_CFG1 | M2_CFG2 | M2_CFG3));

	switch(m2_config >> 17) {
	case 0:
		printf("M.2: SATA SSD module found on M.2 port\n");
#ifdef CONFIG_SERDES_D_TO_PCIE
		printf("Warning: SERDES has not been configured in RCW for SATA!\n");
#endif
		break;
	case 1:
		printf("M.2: PCIe SSD module found on M.2 port\n");
#ifdef CONFIG_SERDES_D_TO_SATA
		printf("Warning: SERDES has not been configured in RCW for PCIe!\n");
#endif
		break;
	case 0xf:
		printf("M.2: No module detected on M.2 port\n");
		break;
	default:
		printf("M.2: A module has been detected on M.2 port(TODO: add module type)\n");
		break;
	}

	return 0;
}

int dram_init(void)
{
	static const struct fsl_mmdc_info mparam = {
		0x05180000,	/* mdctl */
		0x00030035,	/* mdpdc */
		0x12554000,	/* mdotc */
		0xbabf7954,	/* mdcfg0 */
		0xdb328f64,	/* mdcfg1 */
		0x01ff00db,	/* mdcfg2 */
		0x00001680,	/* mdmisc */
		0x0f3c8000,	/* mdref */
		0x00002000,	/* mdrwd */
		0x00bf1023,	/* mdor */
		0x0000003f,	/* mdasp */
		0x0000022a,	/* mpodtctrl */
		0xa1390003,	/* mpzqhwctrl */
	};

	mmdc_init(&mparam);

	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
	/* This will break-before-make MMU for DDR */
	update_early_mmu_table();
#endif

	return 0;
}

int board_early_init_f(void)
{
	fsl_lsch2_early_init_f();

	return 0;
}

int board_init(void)
{
	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
					CONFIG_SYS_CCI400_OFFSET);
	/*
	 * Set CCI-400 control override register to enable barrier
	 * transaction
	 */
	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);

#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
	erratum_a010315();
#endif

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif

#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif

#ifdef CONFIG_FSL_LS_PPA
	ppa_init();
#endif
	return 0;
}

int esdhc_status_fixup(void *blob, const char *compat)
{
	/*char esdhc0_path[] = "/soc/esdhc@1560000";*/

	return 0;
}

void scsi_init(void)
{
#if defined(CONFIG_SCSI_AHCI_PLAT) && defined(CONFIG_SERDES_D_TO_SATA)
	struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;

	/* Disable SATA ECC */
	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);

	ahci_init((void __iomem *)CONFIG_SYS_SATA);
	scsi_scan(0);
#else
	printf("Disabled\n");
#endif
}


int ft_board_setup(void *blob, bd_t *bd)
{
	arch_fixup_fdt(blob);

	ft_cpu_setup(blob, bd);

	return 0;
}