From 5434caf5ba32d0779f309d7a8d13e985dc667f5b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 16 Jun 2013 15:39:02 +0200 Subject: ARM: mxs: Consolidate configuration options Pull all the duplicate configuration options into configs/mxs.h from the board configuration files. This reduces the files greatly and makes them somewhat more readable. Besides, we do no longer have such a horrible duplication of code. Note that the mx23evk grew in size slightly. This is due to the CONFIG_SYS_CBSIZE now being set to 1024 as it is on the rest of MXS systems. This patch also fixes the OCRAM size for i.MX23. The i.MX23 has only 32kB of OCRAM, while i.MX28 has 128kB of OCRAM. I verified the configuration didn't change for each of the boards, but I didn't boot-test it on the boards I do not have. I configured U-Boot for each board using the "make ... _config" command and then ran "cpp -I include -dM include/config.h" , which dumped all the configuration options. I did this both before and after this patch and finally compared the results for each MXS board. Actually, the results do differ slightly, since the configs/mxs.h file now properly includes the correct iomux-mx23.h or iomux-mx28.h , so while comparing, I had to ignore these new defines. These have no impact on U-Boot configuration though. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Lauri Hintsala Cc: Otavio Salvador Cc: Stefano Babic diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index 3242133..7081f37 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -19,34 +19,16 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIGS_APX4DEVKIT_H__ +#define __CONFIGS_APX4DEVKIT_H__ -/* SoC configurations */ +/* System configurations */ #define CONFIG_MX28 /* i.MX28 SoC */ -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ - #define MACH_TYPE_APX4DEVKIT 3712 #define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT -#include - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_ARCH_MISC_INIT - -/* SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - /* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION @@ -66,78 +48,26 @@ #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_USB -/* Memory configurations */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 +/* Environment */ #define CONFIG_ENV_OVERWRITE - -/* U-Boot general configurations */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-Boot version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc. */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_OF_LIBFDT #define CONFIG_ENV_IS_IN_NAND -/* Serial Driver */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* DMA */ -#define CONFIG_APBH_DMA - -/* MMC Driver */ -#ifdef CONFIG_ENV_IS_IN_MMC +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_ENV_OFFSET (256 * 1024) #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 #endif -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_MXS_MMC -#endif - -/* NAND Driver */ -#ifdef CONFIG_ENV_IS_IN_NAND +/* Environment is in NAND */ +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_SIZE (128 * 1024) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE @@ -147,12 +77,8 @@ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) #endif +/* UBI and NAND partitioning */ #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MXS -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS #define CONFIG_CMD_MTDPARTS @@ -167,43 +93,30 @@ #define MTDPARTS_DEFAULT "" #endif -/* Ethernet on SOC (FEC) */ +/* FEC Ethernet on SoC */ #ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC #define CONFIG_NET_MULTI #define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC #define CONFIG_FEC_MXC_PHYADDR 0 #define IMX_FEC_BASE MXS_ENET0_BASE -#define CONFIG_MII -#define CONFIG_FEC_XCV_TYPE RMII #endif /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif -/* I2C */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MXS -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#endif /* RTC */ -#if defined(CONFIG_CMD_DATE) +#ifdef CONFIG_CMD_DATE #define CONFIG_RTC_PCF8563 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 #endif /* Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 1 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTCOMMAND "run bootcmd_nand" @@ -233,4 +146,7 @@ "ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \ "" -#endif /* __CONFIG_H */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_APX4DEVKIT_H__ */ diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 10ccc3b..b6fa6eb 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -17,43 +17,17 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __M28EVK_CONFIG_H__ -#define __M28EVK_CONFIG_H__ +#ifndef __CONFIGS_M28EVK_H__ +#define __CONFIGS_M28EVK_H__ -/* - * SoC configurations - */ -#define CONFIG_MX28 /* i.MX28 SoC */ -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ -/* - * Define M28EVK machine type by hand until it lands in mach-types - */ +/* System configurations */ +#define CONFIG_MX28 /* i.MX28 SoC */ #define MACH_TYPE_M28EVK 3613 - #define CONFIG_MACH_TYPE MACH_TYPE_M28EVK -#include - +/* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_MISC_INIT - -/* - * SPL - */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - -/* - * U-Boot Commands - */ #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION @@ -82,86 +56,18 @@ #define CONFIG_REGEX /* Enable regular expression support */ -/* - * Memory configurations - */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Serial Driver - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ - -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_GENERIC_MMC -#define CONFIG_MXS_MMC -#endif -/* - * APBH DMA - */ -#define CONFIG_APBH_DMA - -/* - * NAND - */ +/* Environment */ #define CONFIG_ENV_SIZE (16 * 1024) -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MXS -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_ENV_IS_IN_NAND /* Environment is in NAND */ -#define CONFIG_ENV_IS_IN_NAND +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_RANGE (512 * 1024) @@ -190,40 +96,22 @@ #define CONFIG_ENV_IS_NOWHERE #endif -/* - * Ethernet on SOC (FEC) - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_ETHPRIME "FEC0" +/* FEC Ethernet on SoC */ +#ifdef CONFIG_CMD_NET #define CONFIG_FEC_MXC -#define CONFIG_MII -#define CONFIG_FEC_XCV_TYPE RMII #endif -/* - * I2C - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MXS -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#endif - -/* - * EEPROM - */ -#ifdef CONFIG_CMD_EEPROM +/* EEPROM */ +#ifdef CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #endif -/* - * RTC - */ -#ifdef CONFIG_CMD_DATE +/* RTC */ +#ifdef CONFIG_CMD_DATE /* Use the internal RTC in the MXS chip */ #define CONFIG_RTC_INTERNAL -#ifdef CONFIG_RTC_INTERNAL +#ifdef CONFIG_RTC_INTERNAL #define CONFIG_RTC_MXS #else #define CONFIG_RTC_M41T62 @@ -232,32 +120,22 @@ #endif #endif -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS +/* USB */ +#ifdef CONFIG_CMD_USB #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_EHCI_MXS_PORT1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif -/* - * SPI - */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_HARD_SPI -#define CONFIG_MXS_SPI -#define CONFIG_SPI_HALF_DUPLEX +/* SPI */ +#ifdef CONFIG_CMD_SPI #define CONFIG_DEFAULT_SPI_BUS 2 #define CONFIG_DEFAULT_SPI_CS 0 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 /* SPI FLASH */ -#ifdef CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SF_DEFAULT_BUS 2 @@ -270,18 +148,12 @@ #define CONFIG_ENV_SPI_MAX_HZ 40000000 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 #endif + #endif -/* - * LCD - */ -#ifdef CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_MXS +/* LCD */ +#ifdef CONFIG_VIDEO #define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP @@ -290,22 +162,15 @@ #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) #endif -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS +/* Booting Linux */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " #define CONFIG_BOOTCOMMAND "run bootcmd_net" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_OF_LIBFDT -/* - * Extra Environments - */ +/* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ @@ -346,4 +211,7 @@ "fi ; " \ "fi\0" -#endif /* __M28EVK_CONFIG_H__ */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_M28EVK_H__ */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index 38ad7f4..418d4fd 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -16,40 +16,15 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __MX23_OLINUXINO_CONFIG_H__ -#define __MX23_OLINUXINO_CONFIG_H__ +#ifndef __CONFIGS_MX23_OLINUXINO_H__ +#define __CONFIGS_MX23_OLINUXINO_H__ -#include - -/* - * SoC configurations - */ +/* System configurations */ #define CONFIG_MX23 /* i.MX23 SoC */ -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ - #define CONFIG_MACH_TYPE 4105 -#include - +/* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_MISC_INIT - -/* - * SPL - */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - -/* - * U-Boot Commands - */ #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION @@ -64,92 +39,36 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_USB -/* - * Memory configurations - */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER +/* Environment */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OVERWRITE -/* - * Serial Driver - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (256 * 1024) +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif -/* - * Status LED - */ +/* Status LED */ #define CONFIG_STATUS_LED #define CONFIG_GPIO_LED #define CONFIG_BOARD_SPECIFIC_LED -#define STATUS_LED_BOOT 0 -#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1 +#define STATUS_LED_BOOT 0 +#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1 #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_GENERIC_MMC -#define CONFIG_MXS_MMC -#endif - -/* - * APBH DMA - */ -#define CONFIG_APBH_DMA - /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif @@ -159,31 +78,13 @@ #define CONFIG_USB_ETHER_SMSC95XX #endif -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS +/* Booting Linux */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_OF_LIBFDT -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET (256 * 1024) -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* - * Extra Environments - */ +/* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "update_sd_firmware_filename=u-boot.sd\0" \ "update_sd_firmware=" /* Update the SD firmware partition */ \ @@ -265,4 +166,7 @@ "fi; " \ "else run netboot; fi" -#endif /* __MX23_OLINUXINO_CONFIG_H__ */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_MX23_OLINUXINO_H__ */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 3a58afe..b52b9e6 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -19,33 +19,15 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ -#ifndef __MX23EVK_CONFIG_H__ -#define __MX23EVK_CONFIG_H__ +#ifndef __CONFIGS_MX23EVK_H__ +#define __CONFIGS_MX23EVK_H__ -/* SoC configurations */ +/* System configurations */ #define CONFIG_MX23 /* i.MX23 SoC */ - -#include - -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ - #define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK -#define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_MISC_INIT - -/* SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - /* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH #include #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS @@ -62,86 +44,33 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_VIDEO -/* Memory configurations */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 +/* Environment */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_MMC -/* U-Boot general configurations */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -/* Serial Driver */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ - -/* DMA */ -#define CONFIG_APBH_DMA - -/* MMC Driver */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_MXS_MMC +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (256 * 1024) +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 #endif /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif /* Framebuffer support */ #ifdef CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP @@ -151,21 +80,10 @@ #endif /* Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_OF_LIBFDT - -/* Environment */ -#define CONFIG_ENV_IS_IN_MMC -#ifdef CONFIG_ENV_IS_IN_MMC - #define CONFIG_ENV_OFFSET (256 * 1024) - #define CONFIG_ENV_SIZE (16 * 1024) - #define CONFIG_SYS_MMC_ENV_DEV 0 -#endif /* Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -224,4 +142,7 @@ "fi; " \ "else exit; fi" -#endif /* __MX23EVK_CONFIG_H__ */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_MX23EVK_H__ */ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index de69182..877b811 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -16,33 +16,16 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#ifndef __MX28EVK_CONFIG_H__ -#define __MX28EVK_CONFIG_H__ +#ifndef __CONFIGS_MX28EVK_H__ +#define __CONFIGS_MX28EVK_H__ -/* SoC configurations */ +/* System configurations */ #define CONFIG_MX28 /* i.MX28 SoC */ - -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ - #define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK - -#include - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_MISC_INIT - -/* SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > " /* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION @@ -57,6 +40,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_NFS #define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SETEXPR #define CONFIG_CMD_SF #define CONFIG_CMD_SPI @@ -66,81 +50,24 @@ #define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_VIDEO -/* Memory configurations */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 +/* Environment */ +#define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_OVERWRITE -/* U-Boot general configurations */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER - -/* Serial Driver */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -/* DMA */ -#define CONFIG_APBH_DMA - -/* MMC Driver */ -#ifdef CONFIG_ENV_IS_IN_MMC - #define CONFIG_ENV_OFFSET (256 * 1024) - #define CONFIG_ENV_SIZE (16 * 1024) - #define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#define CONFIG_CMD_SAVEENV -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_MXS_MMC +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (256 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 #endif -/* NAND Driver */ -#define CONFIG_ENV_SIZE (16 * 1024) -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MXS -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - /* Environment is in NAND */ -#ifdef CONFIG_ENV_IS_IN_NAND +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_RANGE (512 * 1024) @@ -149,6 +76,21 @@ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) #endif +/* Environemnt is in SPI flash */ +#if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ +#define CONFIG_ENV_OFFSET 0x40000 /* 256K */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_BUS 2 +#define CONFIG_ENV_SPI_MAX_HZ 24000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#endif + +/* UBI and NAND partitioning */ +#ifdef CONFIG_CMD_NAND #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS #define CONFIG_CMD_MTDPARTS @@ -168,13 +110,10 @@ "-(filesystem)" #endif -/* Ethernet on SOC (FEC) */ +/* FEC Ethernet on SoC */ #ifdef CONFIG_CMD_NET -#define CONFIG_NET_MULTI -#define CONFIG_ETHPRIME "FEC0" #define CONFIG_FEC_MXC -#define CONFIG_MII -#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_NET_MULTI #define CONFIG_MX28_FEC_MAC_IN_OCOTP #endif @@ -185,65 +124,35 @@ /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_SMSC95XX #endif -/* I2C */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MXS -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#endif - /* SPI */ #ifdef CONFIG_CMD_SPI -#define CONFIG_HARD_SPI -#define CONFIG_MXS_SPI -#define CONFIG_SPI_HALF_DUPLEX #define CONFIG_DEFAULT_SPI_BUS 2 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 /* SPI Flash */ #ifdef CONFIG_CMD_SF #define CONFIG_SPI_FLASH -#define CONFIG_SF_DEFAULT_BUS 2 -#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 /* this may vary and depends on the installed chip */ #define CONFIG_SPI_FLASH_SST #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 - -/* (redundant) environemnt in SPI flash */ -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ -#define CONFIG_ENV_OFFSET 0x40000 /* 256K */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_BUS 2 -#define CONFIG_ENV_SPI_MAX_HZ 24000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#endif #endif + #endif /* Framebuffer support */ #ifdef CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP @@ -253,15 +162,12 @@ #endif /* Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_OF_LIBFDT -/* Extra Environments */ +/* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ @@ -372,4 +278,7 @@ "fi; " \ "else run netboot; fi" -#endif /* __MX28EVK_CONFIG_H__ */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_MX28EVK_H__ */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h new file mode 100644 index 0000000..a684166 --- /dev/null +++ b/include/configs/mxs.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2013 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIGS_MXS_H__ +#define __CONFIGS_MXS_H__ + +/* + * Includes + */ + +#if defined(CONFIG_MX23) && defined(CONFIG_MX28) +#error Select either CONFIG_MX23 or CONFIG_MX28 , never both! +#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28) +#error Select one of CONFIG_MX23 or CONFIG_MX28 ! +#endif + +#include + +#if defined(CONFIG_MX23) +#include +#elif defined(CONFIG_MX28) +#include +#endif + +/* + * CPU specifics + */ + +/* Ticks per second */ +#define CONFIG_SYS_HZ 1000 + +/* MXS uses FDT */ +#define CONFIG_OF_LIBFDT + +/* Startup hooks */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT + +/* SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NO_CPU_SUPPORT_CODE +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* Memory sizes */ +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ + +/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +#if defined(CONFIG_MX23) +#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) +#elif defined(CONFIG_MX28) +#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) +#endif + +/* Point initial SP in SRAM so SPL can use it too. */ +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * We need to sacrifice first 4 bytes of RAM here to avoid triggering some + * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot + * binary. In case there was more of this mess, 0x100 bytes are skipped. + */ +#define CONFIG_SYS_TEXT_BASE 0x40000100 + +/* U-Boot general configuration */ +#define CONFIG_SYS_LONGHELP +#ifndef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Booting Linux */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +/* + * Drivers + */ + +/* APBH DMA */ +#define CONFIG_APBH_DMA + +/* GPIO */ +#define CONFIG_MXS_GPIO + +/* DUART Serial Driver */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } +#define CONFIG_CONS_INDEX 0 +/* Default baudrate can be overriden by board! */ +#ifndef CONFIG_BAUDRATE +#define CONFIG_BAUDRATE 115200 +#endif + +/* FEC Ethernet on SoC */ +#ifdef CONFIG_FEC_MXC +#define CONFIG_MII +#ifndef CONFIG_ETHPRIME +#define CONFIG_ETHPRIME "FEC0" +#endif +#ifndef CONFIG_FEC_XCV_TYPE +#define CONFIG_FEC_XCV_TYPE RMII +#endif +#endif + +/* I2C */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_I2C_MXS +#define CONFIG_HARD_I2C +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 400000 +#endif +#endif + +/* LCD */ +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_MXS_MMC +#endif + +/* NAND */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x60000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#endif + +/* SPI */ +#ifdef CONFIG_CMD_SPI +#define CONFIG_HARD_SPI +#define CONFIG_MXS_SPI +#define CONFIG_SPI_HALF_DUPLEX +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MXS +#define CONFIG_EHCI_IS_TDI +#endif + +#endif /* __CONFIGS_MXS_H__ */ diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index 349497f..b7b46b4 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -19,48 +19,16 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __SC_SPS_1_H__ -#define __SC_SPS_1_H__ +#ifndef __CONFIGS_SC_SPS_1_H__ +#define __CONFIGS_SC_SPS_1_H__ -/* - * SoC configurations - */ +/* System configuration */ #define CONFIG_MX28 /* i.MX28 SoC */ -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ - -/* - * Define SC_SPS_1 machine type by hand until it lands in mach-types - */ #define MACH_TYPE_SC_SPS_1 4172 - #define CONFIG_MACH_TYPE MACH_TYPE_SC_SPS_1 -#include - +/* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_ARCH_MISC_INIT - -#define CONFIG_ENV_IS_IN_MMC - -#define CONFIG_OF_LIBFDT - -/* - * SPL - */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - -/* - * U-Boot Commands - */ #include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION @@ -78,119 +46,47 @@ #define CONFIG_CMD_SETEXPR #define CONFIG_CMD_USB -/* - * Memory configurations - */ +/* Memory configuration */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Point initial SP in SRAM so SPL can use it too. */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -/* - * Serial Driver - */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_APBH_DMA -#define CONFIG_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_GENERIC_MMC -#define CONFIG_MXS_MMC -#endif +/* Environment */ #define CONFIG_ENV_SIZE (16 * 1024) -#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_IS_IN_MMC + +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_ENV_OFFSET (256 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 #else #define CONFIG_ENV_IS_NOWHERE #endif -/* - * Ethernet on SOC (FEC) - */ +/* FEC Ethernet on SoC */ #ifdef CONFIG_CMD_NET -#define CONFIG_ETHPRIME "FEC0" #define CONFIG_FEC_MXC -#define CONFIG_MII -#define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC #endif -/* - * USB - */ +/* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #endif -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS +/* Booting Linux */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTARGS "console=ttyAMA0,115200" -#define CONFIG_BOOTCOMMAND "bootm " +#define CONFIG_BOOTCOMMAND "bootm" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* - * Extra Environments - */ +/* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "update_sd_firmware_filename=u-boot.sd\0" \ "update_sd_firmware=" /* Update the SD firmware partition */ \ @@ -202,4 +98,7 @@ "fi ; " \ "fi\0" -#endif /* __SC_SPS_1_H__ */ +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_SC_SPS_1_H__ */ -- cgit v0.10.2 From 04c79cbd5f8f773aa7823feec6e77862e7e6426f Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Mon, 15 Jul 2013 15:58:27 +0200 Subject: mxc_gpio: Correct the GPIO handling in gpio_direction_output() Setting the direction and an output value should be done by First, set the desired output value. Then, switch to output. If this is done in the inverse order, like at the moment, there can be a glitch on the GPIO line while switching first the old output value and aftwards the new one. Fix this by inverting the order of the direction/set_value calls. Signed-off-by: Dirk Behme Acked-by: Stefano Babic diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index a388064..1d820d4 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -143,10 +143,10 @@ int gpio_direction_input(unsigned gpio) int gpio_direction_output(unsigned gpio, int value) { - int ret = mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT); + int ret = gpio_set_value(gpio, value); if (ret < 0) return ret; - return gpio_set_value(gpio, value); + return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT); } -- cgit v0.10.2 From d727ab3c6ab6328e645c03e38199c256259a2dc3 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sat, 20 Jul 2013 17:21:19 -0300 Subject: wandboard: Use splash image at screen center by default Signed-off-by: Otavio Salvador Acked-by: Fabio Estevam diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index ee6bf21..dd06bd7 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -113,6 +113,7 @@ "script=boot.scr\0" \ "uimage=uImage\0" \ "console=ttymxc0\0" \ + "splashpos=m,m\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ -- cgit v0.10.2 From 0f5141e9c57e96de11642a5baa7ffbb17aecc761 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:45 -0500 Subject: ARM: move interrupt_init to before relocation interrupt_init also sets up the abort stack, but is not setup before relocation. So any aborts during relocation will hang and not print out any useful information. Fix this by moving the interrupt_init to after the stack setup in board_init_f. Signed-off-by: Rob Herring diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 09ab4ad..c90843e 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -447,6 +447,7 @@ void board_init_f(ulong bootflag) addr_sp += 128; /* leave 32 words for abort-stack */ gd->irq_sp = addr_sp; #endif + interrupt_init(); debug("New Stack Pointer is: %08lx\n", addr_sp); @@ -648,8 +649,6 @@ void board_init_r(gd_t *id, ulong dest_addr) misc_init_r(); #endif - /* set up exceptions */ - interrupt_init(); /* enable exceptions */ enable_interrupts(); -- cgit v0.10.2 From 393ee7f3429965148dcc0e3ec77cba456e9762f8 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:46 -0500 Subject: net: calxedaxgmac: enable rx cut-thru There is no reason to wait for the entire frame to start DMA on receive, so enable rx cut-thru for better performance. Signed-off-by: Rob Herring diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index e3553d6..803687a 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -400,7 +400,7 @@ static int xgmac_init(struct eth_device *dev, bd_t * bis) /* set flow control parameters and store and forward mode */ value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) | (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) | - XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF | XGMAC_CORE_OMR_RSF; + XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF; writel(value, ®s->core_opmode); /* enable pause frames */ -- cgit v0.10.2 From 185a5bb0f5bd4666913932cc4c4d6ffa6dd7b34b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:47 -0500 Subject: ARM: highbank: update config options Various changes to highbank config: Enable EFI partitions Enable ext4 and FAT filesystems Enable bootz command and raw initrd Increase cmd and print buffer size to 1K Change serial baudrate to 115200 Enable hush shell Signed-off-by: Rob Herring diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 62cc08c..5e5d8e6 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -18,7 +18,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_DCACHE_OFF #define CONFIG_L2_OFF +#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_NO_FLASH #define CFG_HZ 1000 @@ -26,6 +28,7 @@ #define CONFIG_OF_LIBFDT #define CONFIG_FIT +#define CONFIG_SUPPORT_RAW_INITRD #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* @@ -38,7 +41,7 @@ #define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) } #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_SYS_BOOTCOUNT_SINGLEWORD @@ -54,6 +57,7 @@ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION #define CONFIG_CALXEDA_XGMAC @@ -68,12 +72,15 @@ #include #define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_MEMORY #define CONFIG_CMD_LOADS #define CONFIG_CMD_SCSI #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT #define CONFIG_CMD_PXE #define CONFIG_MENU @@ -84,15 +91,18 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_PROMPT "Highbank #" +#define CONFIG_SYS_HUSH_PARSER /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_LOAD_ADDR 0x800000 +#define CONFIG_SYS_64BIT_LBA + /*----------------------------------------------------------------------- * Physical Memory Map -- cgit v0.10.2 From ec0e413f934fd70968b4ca0daa530cbe8f5cdb4f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:48 -0500 Subject: ARM: highbank: fix get_tbclk value to timer rate get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ. Signed-off-by: Rob Herring diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index 0f985e2..da33d3c 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -124,5 +124,5 @@ ulong get_timer_masked(void) ulong get_tbclk(void) { - return CONFIG_SYS_HZ; + return SYSTIMER_RATE; } -- cgit v0.10.2 From 714d1f5da53101ec44ab9c3d10564462b102bd8f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:49 -0500 Subject: ARM: highbank: set timer prescaler to 256 The 150MHz clock rate gives u-boot time functions problems and there's no benefit to a fast clock, so lower the rate. Signed-off-by: Rob Herring diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index da33d3c..d93de1e 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -26,7 +26,7 @@ #undef SYSTIMER_BASE #define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */ -#define SYSTIMER_RATE 150000000 +#define SYSTIMER_RATE (150000000 / 256) static ulong timestamp; static ulong lastinc; @@ -40,9 +40,11 @@ int timer_init(void) /* * Setup timer0 */ + writel(0, &systimer_base->timer0control); writel(SYSTIMER_RELOAD, &systimer_base->timer0load); writel(SYSTIMER_RELOAD, &systimer_base->timer0value); - writel(SYSTIMER_EN | SYSTIMER_32BIT, &systimer_base->timer0control); + writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256, + &systimer_base->timer0control); reset_timer_masked(); diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h index e745e37..08125f7 100644 --- a/arch/arm/include/asm/arch-armv7/systimer.h +++ b/arch/arm/include/asm/arch-armv7/systimer.h @@ -30,6 +30,8 @@ #define SYSTIMER_RELOAD 0xFFFFFFFF #define SYSTIMER_EN (1 << 7) #define SYSTIMER_32BIT (1 << 1) +#define SYSTIMER_PRESC_16 (1 << 2) +#define SYSTIMER_PRESC_256 (1 << 3) struct systimer { u32 timer0load; /* 0x00 */ -- cgit v0.10.2 From 0f7cf3803f59b0c8d94aa52cc8827aab28591eb4 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:50 -0500 Subject: ARM: highbank: avoid bss write in timer_init The timer_init function is called before relocation and writes to bss data were corrupting relocation data. Fix this by removing the call to reset_timer_masked. The initial timer count should be 0 or near 0 anyway, so initializing the variables are not needed. Signed-off-by: Rob Herring diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index d93de1e..832c012 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -46,8 +46,6 @@ int timer_init(void) writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256, &systimer_base->timer0control); - reset_timer_masked(); - return 0; } -- cgit v0.10.2 From e1df283c26f14776419bff675b7887cf04bc1c20 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:51 -0500 Subject: ARM: highbank: enable reset on command timeout Enable resetting on command timeout. The timeout is set with environment setting bootretry. Signed-off-by: Rob Herring diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 5e5d8e6..9bf56c7 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -85,6 +85,9 @@ #define CONFIG_MENU #define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY + /* * Miscellaneous configurable options */ -- cgit v0.10.2 From 76c3999db439491a406cd6e7778300c992cda785 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:52 -0500 Subject: ARM: highbank: setup peripherals based on power domain status Accessing powered down peripherals will hang the bus, so check power domain status before initializing SATA and fixup the FDT to disable unused peripherals. Signed-off-by: Rob Herring diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 09cd45d..b224aae 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -23,13 +23,21 @@ #include #include +#define HB_AHCI_BASE 0xffe08000 + #define HB_SREG_A9_PWR_REQ 0xfff3cf00 #define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04 +#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20 + #define HB_PWR_SUSPEND 0 #define HB_PWR_SOFT_RESET 1 #define HB_PWR_HARD_RESET 2 #define HB_PWR_SHUTDOWN 3 +#define PWRDOM_STAT_SATA 0x80000000 +#define PWRDOM_STAT_PCI 0x40000000 +#define PWRDOM_STAT_EMMC 0x20000000 + DECLARE_GLOBAL_DATA_PTR; /* @@ -58,9 +66,12 @@ int misc_init_r(void) { char envbuffer[16]; u32 boot_choice; + u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); - ahci_init(0xffe08000); - scsi_scan(1); + if (reg & PWRDOM_STAT_SATA) { + ahci_init(HB_AHCI_BASE); + scsi_scan(1); + } boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff; sprintf(envbuffer, "bootcmd%d", boot_choice); @@ -85,6 +96,22 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; } +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *fdt, bd_t *bd) +{ + static const char disabled[] = "disabled"; + u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); + + if (!(reg & PWRDOM_STAT_SATA)) + do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status", + disabled, sizeof(disabled), 1); + + if (!(reg & PWRDOM_STAT_EMMC)) + do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status", + disabled, sizeof(disabled), 1); +} +#endif + void reset_cpu(ulong addr) { writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ); diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 9bf56c7..e01d4bb 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -27,6 +27,7 @@ #define CONFIG_SYS_HZ CFG_HZ #define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP #define CONFIG_FIT #define CONFIG_SUPPORT_RAW_INITRD #define CONFIG_SYS_BOOTMAPSZ (16 << 20) -- cgit v0.10.2 From 953950234dfb555abdaaa7b8ce92779bbc9e269a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:53 -0500 Subject: ARM: highbank: compile misc_init_r only if CONFIG_MISC_INIT_R Compile misc_init_r only if CONFIG_MISC_INIT_R is enabled. Signed-off-by: Rob Herring diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index b224aae..b0c20fe 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -62,6 +62,7 @@ int board_eth_init(bd_t *bis) return rc; } +#ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { char envbuffer[16]; @@ -83,6 +84,7 @@ int misc_init_r(void) return 0; } +#endif int dram_init(void) { -- cgit v0.10.2 From 76116f29ee846bb5c8106cb580408fe4beab66f1 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:54 -0500 Subject: highbank: enable keyed autoboot stop Restrict autoboot interruption to "s" or "d" keys. This will prevent some unwanted stopping and also allow disabling the reset on command timeout. Signed-off-by: Rob Herring diff --git a/include/configs/highbank.h b/include/configs/highbank.h index e01d4bb..5710be5 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -88,6 +88,8 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_RESET_TO_RETRY +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds...\nPress to stop or to delay\n", bootdelay /* * Miscellaneous configurable options -- cgit v0.10.2 From 12607adcd5181a8f6eab885a5fe4ba2fa12ef92a Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 2 Jul 2013 17:00:18 -0500 Subject: socfpga: Move board/socfpga_cyclone5 to board/socfpga Because the SOCFPGA platform will include support for Cyclone V and Arria V FPGA parts, renaming socfpga_cyclone5 folder to socfpga to be more generic. Signed-off-by: Dinh Nguyen Reviewed-by: Pavel Machek Cc: Chin Liang See Cc: Wolfgang Denk CC: Pavel Machek Cc: Tom Rini v2: - Add Reviewed-by: Pavel Machek - Cc: Tom Rini diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile new file mode 100644 index 0000000..43bbc37 --- /dev/null +++ b/board/altera/socfpga/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := socfpga_cyclone5.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c new file mode 100644 index 0000000..7725be1 --- /dev/null +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Print CPU information + */ +int print_cpuinfo(void) +{ + puts("CPU : Altera SOCFPGA Platform\n"); + return 0; +} + +/* + * Print Board information + */ +int checkboard(void) +{ + puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + return 0; +} + +/* + * Initialization function which happen at early stage of c code + */ +int board_early_init_f(void) +{ + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + icache_enable(); + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + return 0; +} +#endif + +/* + * DesignWare Ethernet initialization + */ +/* We know all the init functions have been run now */ +int board_eth_init(bd_t *bis) +{ + return 0; +} diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile deleted file mode 100644 index 43bbc37..0000000 --- a/board/altera/socfpga_cyclone5/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# (C) Copyright 2010, Thomas Chou -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := socfpga_cyclone5.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c deleted file mode 100644 index 7725be1..0000000 --- a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Print CPU information - */ -int print_cpuinfo(void) -{ - puts("CPU : Altera SOCFPGA Platform\n"); - return 0; -} - -/* - * Print Board information - */ -int checkboard(void) -{ - puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); - return 0; -} - -/* - * Initialization function which happen at early stage of c code - */ -int board_early_init_f(void) -{ - return 0; -} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - icache_enable(); - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - return 0; -} -#endif - -/* - * DesignWare Ethernet initialization - */ -/* We know all the init functions have been run now */ -int board_eth_init(bd_t *bis) -{ - return 0; -} diff --git a/boards.cfg b/boards.cfg index 6a368de..b80b674 100644 --- a/boards.cfg +++ b/boards.cfg @@ -337,7 +337,7 @@ kzm9g arm armv7 kzm9g kmc armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile zynq arm armv7 zynq xilinx zynq zynq_dcc arm armv7 zynq xilinx zynq zynq:ZYNQ_DCC -socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga +socfpga_cyclone5 arm armv7 socfpga altera socfpga actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 -- cgit v0.10.2 From f8b1e86d4707718e52cf6466845e463c358627ee Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 26 Jul 2013 11:37:17 -0300 Subject: mx6qsabrelite: Remove mx6qsabrelite code in favor of nitrogen6x mx6qsabrelite and nitrogen6q boards are hardware compatible, so let's avoid the code duplication and only use the nitrogen6x source code to make board code maintainance easier. Tested booting a mainline device tree kernel on a mx6qsabrelite board. Signed-off-by: Fabio Estevam diff --git a/MAINTAINERS b/MAINTAINERS index 081cf96..0a900dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -601,7 +601,6 @@ Jason Liu mx53evk i.MX53 mx53loco i.MX53 mx6qarm2 i.MX6Q - mx6qsabrelite i.MX6Q Enric Balletbo i Serra @@ -1067,6 +1066,7 @@ Pali Rohár nokia_rx51 ARM ARMV7 (OMAP34xx SoC) Eric Nelson + mx6qsabrelite i.MX6Q 1GB nitrogen6dl i.MX6DL 1GB nitrogen6dl2g i.MX6DL 2GB nitrogen6q i.MX6Q/6D 1GB diff --git a/board/boundary/nitrogen6x/README.mx6qsabrelite b/board/boundary/nitrogen6x/README.mx6qsabrelite new file mode 100644 index 0000000..12a9c85 --- /dev/null +++ b/board/boundary/nitrogen6x/README.mx6qsabrelite @@ -0,0 +1,72 @@ +U-Boot for the Freescale i.MX6q SabreLite board + +This file contains information for the port of U-Boot to the Freescale +i.MX6q SabreLite board. + +1. Boot source, boot from SD card +--------------------------------- + +The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports +boot from SD card only. However, by default, the SabreLite +boards boot from the SPI NOR flash. These boards need to be reflashed with +a small SD card loader to support boot from SD card. This small SD card loader +will be flashed into the SPI NOR. The board will still boot from SPI NOR, but +the loader will in turn request the BootROM to load the U-Boot from SD card. + +The SD card loader is available from + +https://wiki.linaro.org/Boards/MX6QSabreLite + +under a open-source 3-clause BSD license. + +To update the SPI-NOR on the SabreLite board without the Freescale +manufacturing tool use the following procedure: + +1. Write this SD card loader onto a large SD card using: + + sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx + +Note: Replace sXx with the device representing the SD card in your system. + +Note: This writes SD card loader at address 0 + +2. Put this SD card into the slot for the large SD card (SD3 on the bottom of +the board). Make sure SW1 switch is at position "00", so that it can boot +from the fuses. + +3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot +(the default one the board is shipped with, starting from the SPI NOR) and +enter the following commands: + + MX6Q SABRELITE U-Boot > mmc dev 0 + MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200 + MX6Q SABRELITE U-Boot > sf probe + MX6Q SABRELITE U-Boot > sf erase 0 0x40000 + MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000 + +4. done. + +In case you somehow do not succeed with this procedure you will have to use +the Freescale manufacturing tool in order to reflash the SPI-NOR. + +Note: The board now boots from full size SD3 on the bottom of the board. NOT + the micro SD4/BOOT slot on the top of the board. I.e. you have to use + full size SD cards. + +This information is taken from + +https://wiki.linaro.org/Boards/MX6QSabreLite + +2. Build +-------- + +To build U-Boot for the SabreLite board: + + make mx6qsabrelite_config + make + +To copy the resulting u-boot.imx to the SD card: + + sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2&&sudo sync + +Note: Replace sXx with the device representing the SD card in your system. diff --git a/board/freescale/mx6qsabrelite/Makefile b/board/freescale/mx6qsabrelite/Makefile deleted file mode 100644 index cf344e4..0000000 --- a/board/freescale/mx6qsabrelite/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx6qsabrelite.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/freescale/mx6qsabrelite/README b/board/freescale/mx6qsabrelite/README deleted file mode 100644 index 12a9c85..0000000 --- a/board/freescale/mx6qsabrelite/README +++ /dev/null @@ -1,72 +0,0 @@ -U-Boot for the Freescale i.MX6q SabreLite board - -This file contains information for the port of U-Boot to the Freescale -i.MX6q SabreLite board. - -1. Boot source, boot from SD card ---------------------------------- - -The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports -boot from SD card only. However, by default, the SabreLite -boards boot from the SPI NOR flash. These boards need to be reflashed with -a small SD card loader to support boot from SD card. This small SD card loader -will be flashed into the SPI NOR. The board will still boot from SPI NOR, but -the loader will in turn request the BootROM to load the U-Boot from SD card. - -The SD card loader is available from - -https://wiki.linaro.org/Boards/MX6QSabreLite - -under a open-source 3-clause BSD license. - -To update the SPI-NOR on the SabreLite board without the Freescale -manufacturing tool use the following procedure: - -1. Write this SD card loader onto a large SD card using: - - sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx - -Note: Replace sXx with the device representing the SD card in your system. - -Note: This writes SD card loader at address 0 - -2. Put this SD card into the slot for the large SD card (SD3 on the bottom of -the board). Make sure SW1 switch is at position "00", so that it can boot -from the fuses. - -3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot -(the default one the board is shipped with, starting from the SPI NOR) and -enter the following commands: - - MX6Q SABRELITE U-Boot > mmc dev 0 - MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200 - MX6Q SABRELITE U-Boot > sf probe - MX6Q SABRELITE U-Boot > sf erase 0 0x40000 - MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000 - -4. done. - -In case you somehow do not succeed with this procedure you will have to use -the Freescale manufacturing tool in order to reflash the SPI-NOR. - -Note: The board now boots from full size SD3 on the bottom of the board. NOT - the micro SD4/BOOT slot on the top of the board. I.e. you have to use - full size SD cards. - -This information is taken from - -https://wiki.linaro.org/Boards/MX6QSabreLite - -2. Build --------- - -To build U-Boot for the SabreLite board: - - make mx6qsabrelite_config - make - -To copy the resulting u-boot.imx to the SD card: - - sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2&&sudo sync - -Note: Replace sXx with the device representing the SD card in your system. diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c deleted file mode 100644 index 862bc30..0000000 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ /dev/null @@ -1,848 +0,0 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -/* I2C1, SGTL5000 */ -struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } -}; - -/* I2C2 Camera, MIPI */ -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -/* I2C3, J15 - RGB connector */ -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, - .gp = IMX_GPIO_NR(7, 11) - } -}; - -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const enet_pads1[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -/* Button assignments for J14 */ -static iomux_v3_cfg_t const button_pads[] = { - /* Menu */ - MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), - /* Back */ - MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), - /* Labelled Search (mapped to Power under Android) */ - MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), - /* Home */ - MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), - /* Volume Down */ - MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), - /* Volume Up */ - MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), -}; - -static void setup_iomux_enet(void) -{ - gpio_direction_output(IMX_GPIO_NR(3, 23), 0); - gpio_direction_output(IMX_GPIO_NR(6, 30), 1); - gpio_direction_output(IMX_GPIO_NR(6, 25), 1); - gpio_direction_output(IMX_GPIO_NR(6, 27), 1); - gpio_direction_output(IMX_GPIO_NR(6, 28), 1); - gpio_direction_output(IMX_GPIO_NR(6, 29), 1); - imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); - gpio_direction_output(IMX_GPIO_NR(6, 24), 1); - - /* Need delay 10ms according to KSZ9021 spec */ - udelay(1000 * 10); - gpio_set_value(IMX_GPIO_NR(3, 23), 1); - - imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); -} - -iomux_v3_cfg_t const usb_pads[] = { - MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); -} - -#ifdef CONFIG_USB_EHCI_MX6 -int board_ehci_hcd_init(int port) -{ - imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); - - /* Reset USB hub */ - gpio_direction_output(IMX_GPIO_NR(7, 12), 0); - mdelay(2); - gpio_set_value(IMX_GPIO_NR(7, 12), 1); - - return 0; -} -#endif - -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(IMX_GPIO_NR(7, 0)); - ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); - } else { - gpio_direction_input(IMX_GPIO_NR(2, 6)); - ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - s32 status = 0; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - - usdhc_cfg[0].max_bus_width = 4; - usdhc_cfg[1].max_bus_width = 4; - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; - } - - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - } - - return status; -} -#endif - -#ifdef CONFIG_MXC_SPI -iomux_v3_cfg_t const ecspi1_pads[] = { - /* SS1 */ - MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), -}; - -void setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, - ARRAY_SIZE(ecspi1_pads)); -} -#endif - -int board_phy_config(struct phy_device *phydev) -{ - /* min rx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); - /* min tx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); - /* max rx/tx clock delay, min rx/tx control */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - uint32_t base = IMX_FEC_BASE; - struct mii_dev *bus = NULL; - struct phy_device *phydev = NULL; - int ret; - - setup_iomux_enet(); - -#ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(base, -1); - if (!bus) - return 0; - /* scan phy 4,5,6,7 */ - phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); - if (!phydev) { - free(bus); - return 0; - } - printf("using phy at %d\n", phydev->addr); - ret = fec_probe(bis, -1, base, bus, phydev); - if (ret) { - printf("FEC MXC: %s:failed\n", __func__); - free(phydev); - free(bus); - } -#endif - return 0; -} - -static void setup_buttons(void) -{ - imx_iomux_v3_setup_multiple_pads(button_pads, - ARRAY_SIZE(button_pads)); -} - -#ifdef CONFIG_CMD_SATA - -int setup_sata(void) -{ - struct iomuxc_base_regs *const iomuxc_regs - = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; - int ret = enable_sata_clock(); - if (ret) - return ret; - - clrsetbits_le32(&iomuxc_regs->gpr[13], - IOMUXC_GPR13_SATA_MASK, - IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB - |IOMUXC_GPR13_SATA_PHY_7_SATA2M - |IOMUXC_GPR13_SATA_SPEED_3G - |(3<phy_stat0) & HDMI_PHY_HPD; -} - -static void enable_hdmi(struct display_info_t const *dev) -{ - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - u8 reg; - printf("%s: setup HDMI monitor\n", __func__); - reg = readb(&hdmi->phy_conf0); - reg |= HDMI_PHY_CONF0_PDZ_MASK; - writeb(reg, &hdmi->phy_conf0); - - udelay(3000); - reg |= HDMI_PHY_CONF0_ENTMDS_MASK; - writeb(reg, &hdmi->phy_conf0); - udelay(3000); - reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; - writeb(reg, &hdmi->phy_conf0); - writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); -} - -static int detect_i2c(struct display_info_t const *dev) -{ - return ((0 == i2c_set_bus_num(dev->bus)) - && - (0 == i2c_probe(dev->addr))); -} - -static void enable_lvds(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *) - IOMUXC_BASE_ADDR; - u32 reg = readl(&iomux->gpr[2]); - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; - writel(reg, &iomux->gpr[2]); - gpio_direction_output(LVDS_BACKLIGHT_GP, 1); -} - -static void enable_rgb(struct display_info_t const *dev) -{ - imx_iomux_v3_setup_multiple_pads( - rgb_pads, - ARRAY_SIZE(rgb_pads)); - gpio_direction_output(RGB_BACKLIGHT_GP, 1); -} - -static struct display_info_t const displays[] = {{ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = 2, - .addr = 0x4, - .pixfmt = IPU_PIX_FMT_LVDS666, - .detect = detect_i2c, - .enable = enable_lvds, - .mode = { - .name = "Hannstar-XGA", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = 2, - .addr = 0x38, - .pixfmt = IPU_PIX_FMT_LVDS666, - .detect = detect_i2c, - .enable = enable_lvds, - .mode = { - .name = "wsvga-lvds", - .refresh = 60, - .xres = 1024, - .yres = 600, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = 2, - .addr = 0x48, - .pixfmt = IPU_PIX_FMT_RGB666, - .detect = detect_i2c, - .enable = enable_rgb, - .mode = { - .name = "wvga-rgb", - .refresh = 57, - .xres = 800, - .yres = 480, - .pixclock = 37037, - .left_margin = 40, - .right_margin = 60, - .upper_margin = 10, - .lower_margin = 10, - .hsync_len = 20, - .vsync_len = 10, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED -} } }; - -int board_video_skip(void) -{ - int i; - int ret; - char const *panel = getenv("panel"); - if (!panel) { - for (i = 0; i < ARRAY_SIZE(displays); i++) { - struct display_info_t const *dev = displays+i; - if (dev->detect(dev)) { - panel = dev->mode.name; - printf("auto-detected panel %s\n", panel); - break; - } - } - if (!panel) { - panel = displays[0].mode.name; - printf("No panel detected: default to %s\n", panel); - } - } else { - for (i = 0; i < ARRAY_SIZE(displays); i++) { - if (!strcmp(panel, displays[i].mode.name)) - break; - } - } - if (i < ARRAY_SIZE(displays)) { - ret = ipuv3_fb_init(&displays[i].mode, 0, - displays[i].pixfmt); - if (!ret) { - displays[i].enable(displays+i); - printf("Display: %s (%ux%u)\n", - displays[i].mode.name, - displays[i].mode.xres, - displays[i].mode.yres); - } else - printf("LCD %s cannot be configured: %d\n", - displays[i].mode.name, ret); - } else { - printf("unsupported panel %s\n", panel); - ret = -EINVAL; - } - return (0 != ret); -} - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - - int reg; - - /* Turn on LDB0,IPU,IPU DI0 clocks */ - reg = __raw_readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET - |MXC_CCM_CCGR3_LDB_DI0_MASK; - writel(reg, &mxc_ccm->CCGR3); - - /* Turn on HDMI PHY clock */ - reg = __raw_readl(&mxc_ccm->CCGR2); - reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK - |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; - writel(reg, &mxc_ccm->CCGR2); - - /* clear HDMI PHY reset */ - writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); - - /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ - writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); - writel(0x13<pfd_480_set); - - /* set LDB0, LDB1 clk select to 011/011 */ - reg = readl(&mxc_ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (3<cs2cdr); - - reg = readl(&mxc_ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, &mxc_ccm->cscmr2); - - reg = readl(&mxc_ccm->chsccdr); - reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK - |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK - |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - <chsccdr); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH - |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW - |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG - |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT - |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT - |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED - |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - <gpr[3]); - - /* backlights off until needed */ - imx_iomux_v3_setup_multiple_pads(backlight_pads, - ARRAY_SIZE(backlight_pads)); - gpio_direction_input(LVDS_BACKLIGHT_GP); - gpio_direction_input(RGB_BACKLIGHT_GP); -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_buttons(); - -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); -#endif - return 0; -} - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - -#ifdef CONFIG_CMD_SATA - setup_sata(); -#endif - - return 0; -} - -int checkboard(void) -{ - puts("Board: MX6Q-Sabre Lite\n"); - - return 0; -} - -struct button_key { - char const *name; - unsigned gpnum; - char ident; -}; - -static struct button_key const buttons[] = { - {"back", IMX_GPIO_NR(2, 2), 'B'}, - {"home", IMX_GPIO_NR(2, 4), 'H'}, - {"menu", IMX_GPIO_NR(2, 1), 'M'}, - {"search", IMX_GPIO_NR(2, 3), 'S'}, - {"volup", IMX_GPIO_NR(7, 13), 'V'}, - {"voldown", IMX_GPIO_NR(4, 5), 'v'}, -}; - -/* - * generate a null-terminated string containing the buttons pressed - * returns number of keys pressed - */ -static int read_keys(char *buf) -{ - int i, numpressed = 0; - for (i = 0; i < ARRAY_SIZE(buttons); i++) { - if (!gpio_get_value(buttons[i].gpnum)) - buf[numpressed++] = buttons[i].ident; - } - buf[numpressed] = '\0'; - return numpressed; -} - -static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char envvalue[ARRAY_SIZE(buttons)+1]; - int numpressed = read_keys(envvalue); - setenv("keybd", envvalue); - return numpressed == 0; -} - -U_BOOT_CMD( - kbd, 1, 1, do_kbd, - "Tests for keypresses, sets 'keybd' environment variable", - "Returns 0 (true) to shell if key is pressed." -); - -#ifdef CONFIG_PREBOOT -static char const kbd_magic_prefix[] = "key_magic"; -static char const kbd_command_prefix[] = "key_cmd"; - -static void preboot_keys(void) -{ - int numpressed; - char keypress[ARRAY_SIZE(buttons)+1]; - numpressed = read_keys(keypress); - if (numpressed) { - char *kbd_magic_keys = getenv("magic_keys"); - char *suffix; - /* - * loop over all magic keys - */ - for (suffix = kbd_magic_keys; *suffix; ++suffix) { - char *keys; - char magic[sizeof(kbd_magic_prefix) + 1]; - sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); - keys = getenv(magic); - if (keys) { - if (!strcmp(keys, keypress)) - break; - } - } - if (*suffix) { - char cmd_name[sizeof(kbd_command_prefix) + 1]; - char *cmd; - sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); - cmd = getenv(cmd_name); - if (cmd) { - setenv("preboot", cmd); - return; - } - } - } -} -#endif - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, - {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int misc_init_r(void) -{ -#ifdef CONFIG_PREBOOT - preboot_keys(); -#endif - -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - return 0; -} diff --git a/boards.cfg b/boards.cfg index 6a368de..f919c53 100644 --- a/boards.cfg +++ b/boards.cfg @@ -268,7 +268,7 @@ vision2 arm armv7 vision2 ttcontr cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q -mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +mx6qsabrelite arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE mx6dlsabresd arm armv7 mx6sabresd freescale mx6 mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL mx6qsabresd arm armv7 mx6sabresd freescale mx6 mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h deleted file mode 100644 index c7db81d..0000000 --- a/include/configs/mx6qsabrelite.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q Sabre Lite board. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MX6 -#define CONFIG_MX6Q - -#include "mx6_common.h" - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_MACH_TYPE 3769 - -#include -#include - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MISC_INIT_R -#define CONFIG_MXC_GPIO - -#define CONFIG_CMD_FUSE -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -#define CONFIG_CMD_SF -#ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_SST -#define CONFIG_MXC_SPI -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) -#define CONFIG_SF_DEFAULT_SPEED 25000000 -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) -#endif - -/* I2C Configs */ -#define CONFIG_CMD_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - -/* MMC Configs */ -#define CONFIG_FSL_ESDHC -#define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_MMC -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMD_SATA -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#define CONFIG_LIBATA -#endif - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_MII -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 -#define CONFIG_PHYLIB -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_MICREL_KSZ9021 - -/* USB Configs */ -#define CONFIG_CMD_USB -#define CONFIG_CMD_FAT -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 -#define CONFIG_USB_STORAGE -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* Miscellaneous commands */ -#define CONFIG_CMD_BMODE - -/* Framebuffer and LCD */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_IPUV3_CLK 260000000 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Command definition */ -#include - -#undef CONFIG_CMD_IMLS - -#define CONFIG_BOOTDELAY 1 - -#define CONFIG_PREBOOT "" - -#define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_TEXT_BASE 0x17800000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "console=ttymxc1\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx6q-sabrelite.dtb\0" \ - "fdt_addr=0x11000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${uimage}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "MX6QSABRELITE U-Boot > " -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_CMDLINE_EDITING - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ENV_SIZE (8 * 1024) - -#define CONFIG_ENV_IS_IN_MMC -/* #define CONFIG_ENV_IS_IN_SPI_FLASH */ - -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (8 * 1024) -#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -#endif - -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ - -#ifndef CONFIG_SYS_DCACHE_OFF -#define CONFIG_CMD_CACHE -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 74df66c..85eecfc 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -186,6 +186,80 @@ #define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC +#if defined(CONFIG_SABRELITE) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttymxc1\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6q-sabrelite.dtb\0" \ + "fdt_addr=0x11000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#else #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc1\0" \ "clearenv=if sf probe || sf probe || sf probe 1 ; then " \ @@ -219,6 +293,7 @@ "done ; " \ "done\0" \ +#endif /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER @@ -258,8 +333,11 @@ #define CONFIG_ENV_SIZE (8 * 1024) -/* #define CONFIG_ENV_IS_IN_MMC */ +#if defined(CONFIG_SABRELITE) +#define CONFIG_ENV_IS_IN_MMC +#else #define CONFIG_ENV_IS_IN_SPI_FLASH +#endif #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_ENV_OFFSET (6 * 64 * 1024) -- cgit v0.10.2 From bf0e86606df37e3344b14d12e58aa8799a15fe37 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 14 Jun 2013 10:55:00 +0200 Subject: arm: omap3: spl: Fix problem with 8bit NAND devices Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit access. This patch adds support for 8bit NAND devices as well. Signed-off-by: Stefan Roese Cc: Tom Rini diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index 1832aff..e649409 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -21,6 +21,17 @@ struct gpmc *gpmc_cfg; #if defined(CONFIG_CMD_NAND) +#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT) +static const u32 gpmc_m_nand[GPMC_MAX_REG] = { + SMNAND_GPMC_CONFIG1, + SMNAND_GPMC_CONFIG2, + SMNAND_GPMC_CONFIG3, + SMNAND_GPMC_CONFIG4, + SMNAND_GPMC_CONFIG5, + SMNAND_GPMC_CONFIG6, + 0, +}; +#else static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, M_NAND_GPMC_CONFIG2, @@ -29,6 +40,7 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG5, M_NAND_GPMC_CONFIG6, 0 }; +#endif #endif /* CONFIG_CMD_NAND */ #if defined(CONFIG_CMD_ONENAND) -- cgit v0.10.2 From 3864cb2133b8d4a45dbad603f7b0b9f051d617ff Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Fri, 14 Jun 2013 14:22:36 +0200 Subject: da850evm: Use clrbits function with correct endianess The current code uses clrbits_be32 which is incorrect since we are on a little endian machine here. This patch fixes this issue and also removes some unnecessary code: Reading the current GPIO bank state is not required if we are using the SET and CLEAR GPIO registers for setting/clearing bits. Signed-off-by: Christian Riesch Cc: Nagabhushana Netagunte Cc: Rajashekhara, Sudhakar diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 01745b2..85b4830 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -323,10 +323,6 @@ int board_early_init_f(void) int board_init(void) { -#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC) - u32 val; -#endif - #ifndef CONFIG_USE_IRQ irq_init(); #endif @@ -366,12 +362,10 @@ int board_init(void) #ifdef CONFIG_USE_NOR /* Set the GPIO direction as output */ - clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); + clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); /* Set the output as low */ - val = readl(GPIO_BANK0_REG_SET_ADDR); - val |= (0x01 << 11); - writel(val, GPIO_BANK0_REG_CLR_ADDR); + writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR); #endif #ifdef CONFIG_DAVINCI_MMC @@ -379,9 +373,7 @@ int board_init(void) clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); /* Set the output as high */ - val = readl(GPIO_BANK0_REG_SET_ADDR); - val |= (0x01 << 11); - writel(val, GPIO_BANK0_REG_SET_ADDR); + writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR); #endif #ifdef CONFIG_DRIVER_TI_EMAC -- cgit v0.10.2 From e4c444b34b6ff6b347e552805ee89c48f85785bb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 28 Jun 2013 14:43:01 -0400 Subject: spl_mmc.c: Detect missing kernel image in RAW MMC Currently, we assume that if we can read from MMC correctly, we have found a valid image. This is not the case as an empty area will read just fine. Add a check for a valid IH_MAGIC. Signed-off-by: Tom Rini Reviewed-by: Peter Korsgaard diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index e369ce3..f27b4c2 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -13,6 +13,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -30,6 +31,9 @@ static int mmc_load_image_raw(struct mmc *mmc, unsigned long sector) if (err == 0) goto end; + if (image_get_magic(header) != IH_MAGIC) + return -1; + spl_parse_image_header(header); /* convert size to sectors - round up */ -- cgit v0.10.2 From c4ec281822562de4ac5850d3b623412be8b721a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Mon, 8 Jul 2013 15:21:34 +0200 Subject: omap3/sys_info: fix printout of OMAP36XX L3 freqency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz used by OMAP34xx/OMAP35xx. Also fix checkpatch warning about alignment. Signed-off-by: Andreas Bießmann diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index 9a3303f..258786b 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -342,9 +342,9 @@ int print_cpuinfo (void) } if (CPU_OMAP36XX == get_cpu_family()) - printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n", - cpu_family_s, cpu_s, sec_s, - rev_s_37xx[get_cpu_rev()], max_clk); + printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n", + cpu_family_s, cpu_s, sec_s, + rev_s_37xx[get_cpu_rev()], max_clk); else printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n", cpu_family_s, cpu_s, sec_s, -- cgit v0.10.2 From d118d7660120635a91bde47fdb9da3776462c0b2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 8 Jul 2013 12:15:14 -0400 Subject: README.falcon: Note how we determine if we can boot the OS or not Reviewed-by: Peter Korsgaard Signed-off-by: Tom Rini diff --git a/doc/README.falcon b/doc/README.falcon index 93e855d..6357b1e 100644 --- a/doc/README.falcon +++ b/doc/README.falcon @@ -41,6 +41,8 @@ file (CONFIG_CMD_SPL_NAND_OFS for NAND). 3. Boot the board into Falcon Mode. SPL will load the kernel and copy the parameters which are saved in the persistent area to the required address. +If a valid uImage is not found at the defined location, U-Boot will be +booted instead. It is required to implement a custom mechanism to select if SPL loads U-Boot or another image. -- cgit v0.10.2 From d78959937f586e326b63dc2ed2ee47283366c264 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 8 Jul 2013 12:15:15 -0400 Subject: am335x_evm: Correct DFU ALT settings for falcon mode Now that we have falcon mode enabled, the partiton numbers for NAND have changed, and we need to list entries for updating these parts of the system. While adding falcon mode entires for eMMC (raw), we round up the limit on U-Boot for ease of math later. Signed-off-by: Tom Rini Reviewed-by: Peter Korsgaard diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c5a6d4b..b974d1b 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -238,7 +238,11 @@ "rootfs part 0 2;" \ "MLO fat 0 1;" \ "MLO.raw mmc 100 100;" \ - "u-boot.img.raw mmc 300 3C0;" \ + "u-boot.img.raw mmc 300 400;" \ + "spl-os-args.raw mmc 80 80;" \ + "spl-os-image.raw mmc 900 2000;" \ + "spl-os-args fat 0 1;" \ + "spl-os-image fat 0 1;" \ "u-boot.img fat 0 1;" \ "uEnv.txt fat 0 1" #define DFU_ALT_INFO_NAND \ @@ -247,8 +251,9 @@ "SPL.backup2 part 0 3;" \ "SPL.backup3 part 0 4;" \ "u-boot part 0 5;" \ - "kernel part 0 7;" \ - "rootfs part 0 8" + "u-boot-spl-os part 0 6;" \ + "kernel part 0 8;" \ + "rootfs part 0 9" /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -- cgit v0.10.2 From 3afd8e0828396046c617d2fd6f755457ae52850e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 8 Jul 2013 12:15:16 -0400 Subject: am335x_evm: Update eMMC falcon mode locations The previous location used for the "args" portion of falcon mode was too small to allow for a device tree to be saved there, so move the location slightly and increase the size. In addition, our previous kernel location was part of the area we set aside for U-Boot itself, so move it up a bit higher. Signed-off-by: Tom Rini Reviewed-by: Peter Korsgaard diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index b974d1b..d60f732 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -337,9 +337,9 @@ #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_DRAM_1 + 0x100) /* raw mmc */ -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ /* nand */ #define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */ -- cgit v0.10.2 From a7d39afbb0097fb50dfb56fe501716b4a29282ef Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 8 Jul 2013 12:15:17 -0400 Subject: am335x_evm: Correct CONFIG_CMD_SPL_WRITE_SIZE We use CONFIG_CMD_SPL_WRITE_SIZE when reading/writing the args portion of falcon mode to NAND. Previously it was half the size of the eraseblock which is too small, increase to eraseblock size. Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index d60f732..0f12c75 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -344,7 +344,7 @@ /* nand */ #define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#define CONFIG_CMD_SPL_WRITE_SIZE 0x1000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 /* spl export command */ #define CONFIG_CMD_SPL -- cgit v0.10.2 From 5d4dbf1c3a1d86b4289ab3e5cde120a6f3c26e9b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 8 Jul 2013 12:15:18 -0400 Subject: am335x_evm: Add basic README Add a README for the family of boards the am335x_evm covers, and include instructions on preparing and using falcon mode, for various media. Signed-off-by: Tom Rini Reviewed-by: Peter Korsgaard Reviewed-by: Lukasz Majewski diff --git a/board/ti/am335x/README b/board/ti/am335x/README new file mode 100644 index 0000000..ccc5e16 --- /dev/null +++ b/board/ti/am335x/README @@ -0,0 +1,113 @@ +Summary +======= + +This document covers various features of the 'am335x_evm' build, and some of +the related build targets (am335x_evm_uartN, etc). + +Hardware +======== + +The binary produced by this board supports, based on parsing of the EEPROM +documented in TI's reference designs: +- AM335x GP EVM +- AM335x EVM SK +- Beaglebone White +- Beaglebone Black + +Falcon Mode +=========== + +The default build includes "Falcon Mode" (see doc/README.falcon) via NAND, +eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is +to read a 'c' on the console while in SPL at any point prior to loading the +OS payload (so as soon as possible) to opt to booting full U-Boot. Also +note that while one can program Falcon Mode "in place" great care needs to +be taken by the user to not 'brick' their setup. As these are all eval +boards with multiple boot methods, recovery should not be an issue in this +worst-case however. + +Falcon Mode: eMMC +================= + +The recommended layout in this case is: + +MMC BLOCKS |--------------------------------| LOCATION IN BYTES +0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000 +0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000 +0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000 +0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000 +0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000 +0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000 +0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000 + +Note that when we run 'spl export' it will prepare to boot the kernel. +This includes relocation of the uImage from where we loaded it to the entry +point defined in the header. As these locations overlap by default, it +would leave us with an image that if written to MMC will not boot, so +instead of using the loadaddr variable we use 0x81000000 in the following +example. In this example we are loading from the network, for simplicity, +and assume a valid partition table already exists and 'mmc dev' has already +been run to select the correct device. Also note that if you previously +had a FAT partition (such as on a Beaglebone Black) it is not enough to +write garbage into the area, you must delete it from the partition table +first. + +# Ensure we are able to talk with this mmc device +U-Boot # mmc rescan +U-Boot # tftp 81000000 am335x/MLO +# Write to two of the backup locations ROM uses +U-Boot # mmc write 81000000 100 100 +U-Boot # mmc write 81000000 200 100 +# Write U-Boot to the location set in the config +U-Boot # tftp 81000000 am335x/u-boot.img +U-Boot # mmc write 81000000 300 400 +# Load kernel and device tree into memory, perform export +U-Boot # tftp 81000000 am335x/uImage +U-Boot # run findfdt +U-Boot # tftp ${fdtaddr} am335x/${fdtfile} +U-Boot # run mmcargs +U-Boot # spl export fdt 81000000 - ${fdtaddr} +# Write the updated device tree to MMC +U-Boot # mmc write ${fdtaddr} 80 80 +# Write the uImage to MMC +U-Boot # mmc write 81000000 900 2000 + +Falcon Mode: FAT SD cards +========================= + +In this case the additional file is written to the filesystem. In this +example we assume that the uImage and device tree to be used are already on +the FAT filesystem (only the uImage MUST be for this to function +afterwards) along with a Falcon Mode aware MLO and the FAT partition has +already been created and marked bootable: + +U-Boot # mmc rescan +# Load kernel and device tree into memory, perform export +U-Boot # load mmc 0:1 ${loadaddr} uImage +U-Boot # run findfdt +U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile} +U-Boot # run mmcargs +U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} + +This will print a number of lines and then end with something like: + Using Device Tree in place at 80f80000, end 80f85928 + Using Device Tree in place at 80f80000, end 80f88928 +So then you: + +U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928 + +Falcon Mode: NAND +================= + +In this case the additional data is written to another partition of the +NAND. In this example we assume that the uImage and device tree to be are +already located on the NAND somewhere (such as fileystem or mtd partition) +along with a Falcon Mode aware MLO written to the correct locations for +booting and mtdparts have been configured correctly for the board: + +U-Boot # nand read ${loadaddr} kernel +U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb +U-Boot # run nandargs +U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} +U-Boot # nand erase.part u-boot-spl-os +U-Boot # nand write ${fdtaddr} u-boot-spl-os -- cgit v0.10.2 From 2bf36ac638ab2db9f0295aa47064976eeebf80c1 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Mon, 8 Jul 2013 16:04:37 +0530 Subject: drivers: net: cpsw: remove hard coding bd ram for cpsw BD ram address may vary in various SOC, so removing the hardcoding and passing the same information through platform data Signed-off-by: Mugunthan V N diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 7138d73..15e249d 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -435,6 +435,7 @@ static struct cpsw_platform_data cpsw_data = { .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 17fba5a..c469645 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -207,6 +207,7 @@ static struct cpsw_platform_data cpsw_data = { .ale_entries = 1024, .host_port_reg_ofs = 0x28, .hw_stats_reg_ofs = 0x400, + .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 379b679..dc0a2be 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -51,8 +51,6 @@ #define CPDMA_RXCP_VER1 0x160 #define CPDMA_RXCP_VER2 0x260 -#define CPDMA_RAM_ADDR 0x4a102000 - /* Descriptor mode bits */ #define CPDMA_DESC_SOP BIT(31) #define CPDMA_DESC_EOP BIT(30) @@ -984,12 +982,12 @@ int cpsw_register(struct cpsw_platform_data *data) return -ENOMEM; } - priv->descs = (void *)CPDMA_RAM_ADDR; priv->host_port = data->host_port_num; priv->regs = regs; priv->host_port_regs = regs + data->host_port_reg_ofs; priv->dma_regs = regs + data->cpdma_reg_ofs; priv->ale_regs = regs + data->ale_reg_ofs; + priv->descs = (void *)regs + data->bd_ram_ofs; int idx = 0; diff --git a/include/cpsw.h b/include/cpsw.h index 296b0e5..743cb96 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -39,6 +39,7 @@ struct cpsw_platform_data { int ale_entries; /* ale table size */ u32 host_port_reg_ofs; /* cpdma host port registers */ u32 hw_stats_reg_ofs; /* cpsw hw stats counters */ + u32 bd_ram_ofs; /* Buffer Descriptor RAM offset */ u32 mac_control; struct cpsw_slave_data *slave_data; void (*control)(int enabled); -- cgit v0.10.2 From 454ac635257f78a369015bde7795ddf979d64e12 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Mon, 8 Jul 2013 16:04:38 +0530 Subject: drivers: net: cpsw: Enable statistics for all port Enable hardware statistics for all ports, enabling only to host port is useless Signed-off-by: Mugunthan V N diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index dc0a2be..f1e9f72 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -772,6 +772,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis) /* enable statistics collection only on the host port */ __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); + __raw_writel(0x7, &priv->regs->stat_port_en); cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); -- cgit v0.10.2 From 65e9d56fb9ce9cfd7ffff7afaa6b7de50e400e06 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 8 Jul 2013 16:04:39 +0530 Subject: ARM: DRA7xx: Lock DPLL_GMAC Locking DPLL_GMAC [mugunthanvnm@ti.com:Configure only if CPSW is selected] Signed-off-by: Lokesh Vutla Signed-off-by: Mugunthan V N diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 20fa678..7580594 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -196,6 +196,18 @@ static const struct dpll_params *get_ddr_dpll_params return &dpll_data->ddr[sysclk_ind]; } +#ifdef CONFIG_DRIVER_TI_CPSW +static const struct dpll_params *get_gmac_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->gmac) + return NULL; + return &dpll_data->gmac[sysclk_ind]; +} +#endif + static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { @@ -398,6 +410,12 @@ static void setup_dplls(void) params = get_ddr_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, params, DPLL_LOCK, "ddr"); + +#ifdef CONFIG_DRIVER_TI_CPSW + params = get_gmac_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params, + DPLL_LOCK, "gmac"); +#endif } #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ea3554d..c21674a 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -247,6 +247,16 @@ static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ }; +static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { + {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ + {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ + {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + struct dplls omap5_dplls_es1 = { .mpu = mpu_dpll_params_800mhz, .core = core_dpll_params_2128mhz_ddr532, @@ -283,6 +293,7 @@ struct dplls dra7xx_dplls = { .iva = iva_dpll_params_2330mhz_dra7xx, .usb = usb_dpll_params_1920mhz, .ddr = ddr_dpll_params_2128mhz, + .gmac = gmac_dpll_params_2000mhz, }; struct pmic_data palmas = { diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 54d8c2b..b0416ad 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -798,6 +798,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, .cm_clkmode_dpll_dsp = 0x4a005234, .cm_shadow_freq_config1 = 0x4a005260, + .cm_clkmode_dpll_gmac = 0x4a0052a8, /* cm1.mpu */ .cm_mpu_mpu_clkctrl = 0x4a005320, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index b56e949..ad27db2 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -73,6 +73,7 @@ struct prcm_regs { u32 cm_ssc_deltamstep_dpll_ddrphy; u32 cm_clkmode_dpll_dsp; u32 cm_shadow_freq_config1; + u32 cm_clkmode_dpll_gmac; u32 cm_mpu_mpu_clkctrl; /* cm1.dsp */ @@ -483,6 +484,7 @@ struct dplls { const struct dpll_params *iva; const struct dpll_params *usb; const struct dpll_params *ddr; + const struct dpll_params *gmac; }; struct pmic_data { -- cgit v0.10.2 From f986d9720836433ded29f06c8f5aed462bd20924 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Mon, 8 Jul 2013 16:04:40 +0530 Subject: ARM: DRA7xx: Enable GMAC clock control Enabling CPSW module by enabling GMAC clock control Signed-off-by: Mugunthan V N diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index c21674a..fbbc486 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -393,6 +393,9 @@ void enable_basic_clocks(void) (*prcm)->cm_l3init_clkstctrl, (*prcm)->cm_memif_clkstctrl, (*prcm)->cm_l4cfg_clkstctrl, +#ifdef CONFIG_DRIVER_TI_CPSW + (*prcm)->cm_gmac_clkstctrl, +#endif 0 }; @@ -420,6 +423,9 @@ void enable_basic_clocks(void) (*prcm)->cm_wkup_wdtimer2_clkctrl, (*prcm)->cm_l4per_uart3_clkctrl, (*prcm)->cm_l4per_i2c1_clkctrl, +#ifdef CONFIG_DRIVER_TI_CPSW + (*prcm)->cm_gmac_gmac_clkctrl, +#endif 0 }; @@ -476,7 +482,6 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l3init_fsusb_clkctrl, 0 }; - do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index b0416ad..9dfeff9 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -896,6 +896,8 @@ struct prcm_regs const dra7xx_prcm = { .cm_l3init_hsusbhost_clkctrl = 0x4a009340, .cm_l3init_hsusbotg_clkctrl = 0x4a009348, .cm_l3init_hsusbtll_clkctrl = 0x4a009350, + .cm_gmac_clkstctrl = 0x4a0093c0, + .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, /* cm2.l4per */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index ad27db2..2c5bd1a 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -340,6 +340,10 @@ struct prcm_regs { /* SCRM stuff, used by some boards */ u32 scrm_auxclk0; u32 scrm_auxclk1; + + /* GMAC Clk Ctrl */ + u32 cm_gmac_gmac_clkctrl; + u32 cm_gmac_clkstctrl; }; struct omap_sys_ctrl_regs { -- cgit v0.10.2 From b1e26e3bfb1d53d4fd713a2a5f11b7ddf2bcaeec Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Mon, 8 Jul 2013 16:04:41 +0530 Subject: ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 9dfeff9..579818d 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -378,6 +378,10 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_status = 0x4A002134, + .control_core_mac_id_0_lo = 0x4A002514, + .control_core_mac_id_0_hi = 0x4A002518, + .control_core_mac_id_1_lo = 0x4A00251C, + .control_core_mac_id_1_hi = 0x4A002520, .control_core_mmr_lock1 = 0x4A002540, .control_core_mmr_lock2 = 0x4A002544, .control_core_mmr_lock3 = 0x4A002548, diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 3de5984..fb5a568 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -99,6 +99,8 @@ struct watchdog { #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ +#define BIT(x) (1 << (x)) + #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 @@ -158,4 +160,8 @@ struct watchdog { #define PRM_RSTST (PRM_DEVICE_BASE + 0x4) #define PRM_RSTST_WARM_RESET_MASK 0x7FEA +/* DRA7XX CPSW Config space */ +#define CPSW_BASE 0x48484000 +#define CPSW_MDIO_BASE 0x48485000 + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index d08fcff..597c692 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -192,6 +192,27 @@ struct s32ktimer { #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) +/* IO Delay module defines */ +#define CFG_IO_DELAY_BASE 0x4844A000 +#define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C) + +/* CPSW IO Delay registers*/ +#define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C) +#define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758) +#define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764) +#define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770) +#define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C) +#define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C) +#define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC) +#define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0) +#define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94) +#define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88) + +#define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA +#define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB +#define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000 +#define CFG_IO_DELAY_LOCK_MASK 0x400 + #ifndef __ASSEMBLY__ struct srcomp_params { s8 divide_factor; @@ -208,5 +229,10 @@ struct ctrl_ioregs { u32 ctrl_emif_sdram_config_ext; u32 ctrl_ddr_ctrl_ext_0; }; + +struct io_delay { + u32 addr; + u32 dly; +}; #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2c5bd1a..66f416f 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -348,6 +348,10 @@ struct prcm_regs { struct omap_sys_ctrl_regs { u32 control_status; + u32 control_core_mac_id_0_lo; + u32 control_core_mac_id_0_hi; + u32 control_core_mac_id_1_lo; + u32 control_core_mac_id_1_hi; u32 control_std_fuse_opp_vdd_mpu_2; u32 control_core_mmr_lock1; u32 control_core_mmr_lock2; diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 8190e4b..9a114e2 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -23,12 +23,53 @@ #include #endif +#ifdef CONFIG_DRIVER_TI_CPSW +#include +#endif + DECLARE_GLOBAL_DATA_PTR; const struct omap_sysinfo sysinfo = { "Board: DRA7xx\n" }; +/* + * Adjust I/O delays on the Tx control and data lines of each MAC port. This + * is a workaround in order to work properly with the DP83865 PHYs on the EVM. + * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we + * essentially need to counteract the DRA7xx internal delay, and we do this + * by delaying the control and data lines. If not using this PHY, you probably + * don't need to do this stuff! + */ +static void dra7xx_adj_io_delay(const struct io_delay *io_dly) +{ + int i = 0; + u32 reg_val; + u32 delta; + u32 coarse; + u32 fine; + + writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); + + while(io_dly[i].addr) { + writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, + io_dly[i].addr); + delta = io_dly[i].dly; + reg_val = readl(io_dly[i].addr) & 0x3ff; + coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); + coarse = (coarse > 0x1F) ? (0x1F) : (coarse); + fine = (reg_val & 0x1F) + (delta & 0x1F); + fine = (fine > 0x1F) ? (0x1F) : (fine); + reg_val = CFG_IO_DELAY_ACCESS_PATTERN | + CFG_IO_DELAY_LOCK_MASK | + ((coarse << 5) | (fine)); + writel(reg_val, io_dly[i].addr); + i++; + } + + writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); +} + /** * @brief board_init * @@ -42,11 +83,6 @@ int board_init(void) return 0; } -int board_eth_init(bd_t *bis) -{ - return 0; -} - /** * @brief misc_init_r - Configure EVM board specific configurations * such as power configurations, ethernet initialization as phase2 of @@ -85,3 +121,107 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + uint32_t ctrl_val; + const struct io_delay io_dly[] = { + {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, + {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, + {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, + {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, + {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, + {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, + {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, + {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, + {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, + {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, + {0} + }; + + /* Adjust IO delay for RGMII tx path */ + dra7xx_adj_io_delay(io_dly); + + /* try reading mac address from efuse */ + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = mac_lo & 0xFF; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = (mac_lo & 0xFF0000) >> 16; + + if (!getenv("ethaddr")) { + printf(" not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); + ctrl_val |= 0x22; + writel(ctrl_val, (*ctrl)->control_core_control_io1); + + ret = cpsw_register(&cpsw_data); + if (ret < 0) + printf("Error %d registering CPSW switch\n", ret); + + return ret; +} +#endif -- cgit v0.10.2 From dec7f748356735efd3e2af269d8d0a21a44cf984 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Mon, 8 Jul 2013 16:04:42 +0530 Subject: ARM: DRA7xx: Add CPSW and MDIO pinmux support Adding CPSW Slave 0 and MDIO pinmux support for DRA7xx EVM Signed-off-by: Mugunthan V N diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index ec83422..0a86594 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -37,5 +37,19 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ + {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ + {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ + {RGMII0_TXC, (M0) }, + {RGMII0_TXCTL, (M0) }, + {RGMII0_TXD3, (M0) }, + {RGMII0_TXD2, (M0) }, + {RGMII0_TXD1, (M0) }, + {RGMII0_TXD0, (M0) }, + {RGMII0_RXC, (IEN | M0) }, + {RGMII0_RXCTL, (IEN | M0) }, + {RGMII0_RXD3, (IEN | M0) }, + {RGMII0_RXD2, (IEN | M0) }, + {RGMII0_RXD1, (IEN | M0) }, + {RGMII0_RXD0, (IEN | M0) }, }; #endif /* _MUX_DATA_DRA7XX_H_ */ -- cgit v0.10.2 From c9be62caba2c727e62b681add94a4814ea1e6651 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Mon, 8 Jul 2013 16:04:43 +0530 Subject: ARM: DRA7xx: Enable CPSW Ethernet support Enabling CPSW Ethernet support in DRA7xx EVM. Signed-off-by: Mugunthan V N diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 70b204f..51be73d 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -28,4 +28,23 @@ #define CONSOLEDEV "ttyO0" +/* CPSW Ethernet */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 2 + #endif /* __CONFIG_DRA7XX_EVM_H */ -- cgit v0.10.2 From 664979a2a9f764b63b8094458b87247d254b0cc1 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 15 Jul 2013 07:11:28 -0500 Subject: omap3_beagle: remove JFFS2 support. We do not use JFFS2 by default and it conflicts with CONFIG_CMD_FS_GENERIC (ls command is the same). Since most of our BOOTCMD can be simplified by using the FS_GENERIC, dropping JFFS2 Signed-off-by: Nishanth Menon Acked-by: Joel Fernandes diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 7958ca5..8992c35 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -134,7 +134,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define MTDIDS_DEFAULT "nand0=nand" @@ -187,13 +186,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ - /* partition */ /* Environment information */ #define CONFIG_BOOTDELAY 3 -- cgit v0.10.2 From a33e3c79f3723ec1693db7db732435ee46771eb1 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 15 Jul 2013 07:11:29 -0500 Subject: omap3_beagle: replace uImage.beagle with generic uImage e682930867f7dfc4a01784fe452fad9e962d65a (BeagleBoard: config: use uImage.beagle for tftp) Introduced uImage.beagle which does not happen to be default output file of Linux kernel build make uImage (output is uImage). So, replace uImage.beagle with uImage Signed-off-by: Nishanth Menon diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 8992c35..a5cd66d 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -194,7 +194,7 @@ "loadaddr=0x80200000\0" \ "rdaddr=0x81000000\0" \ "usbtty=cdc_acm\0" \ - "bootfile=uImage.beagle\0" \ + "bootfile=uImage\0" \ "console=ttyO2,115200n8\0" \ "mpurate=auto\0" \ "buddy=none\0" \ -- cgit v0.10.2 From af4d896fede8428493c1f4fe185b26d9cc08d4d5 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 15 Jul 2013 07:11:30 -0500 Subject: beagleboard: remove RevB support for BeagleBoard Xm As reported in http://marc.info/?l=u-boot&m=137358037827735&w=2 There is no need for the "xMB" variant, as the gpio pins used for identification where never changed from the xMA when the newer silcon was used for the xMB, So rename XM A revision as AB revision and report accordingly Reported-by: Robert Nelson Signed-off-by: Nishanth Menon diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 36f7345..62e9bea 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -166,8 +166,7 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; } - case REVISION_XM_A: - case REVISION_XM_B: + case REVISION_XM_AB: case REVISION_XM_C: if (pop_mfr == 0) { /* 256MB DDR */ @@ -240,8 +239,7 @@ static void beagle_display_init(void) case REVISION_C4: omap3_dss_panel_config(&dvid_cfg); break; - case REVISION_XM_A: - case REVISION_XM_B: + case REVISION_XM_AB: case REVISION_XM_C: default: omap3_dss_panel_config(&dvid_cfg_xm); @@ -260,12 +258,11 @@ static void beagle_dvi_pup(void) case REVISION_AXBX: case REVISION_CX: case REVISION_C4: - case REVISION_XM_A: gpio_request(170, ""); gpio_direction_output(170, 0); gpio_set_value(170, 1); break; - case REVISION_XM_B: + case REVISION_XM_AB: case REVISION_XM_C: default: #define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3) @@ -343,19 +340,9 @@ int misc_init_r(void) TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, TWL4030_PM_RECEIVER_DEV_GRP_P1); break; - case REVISION_XM_A: - printf("Beagle xM Rev A\n"); - setenv("beaglerev", "xMA"); - MUX_BEAGLE_XM(); - /* Set VAUX2 to 1.8V for EHCI PHY */ - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, - TWL4030_PM_RECEIVER_VAUX2_VSEL_18, - TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, - TWL4030_PM_RECEIVER_DEV_GRP_P1); - break; - case REVISION_XM_B: - printf("Beagle xM Rev B\n"); - setenv("beaglerev", "xMB"); + case REVISION_XM_AB: + printf("Beagle xM Rev A/B\n"); + setenv("beaglerev", "xMAB"); MUX_BEAGLE_XM(); /* Set VAUX2 to 1.8V for EHCI PHY */ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, @@ -468,8 +455,7 @@ int misc_init_r(void) twl4030_power_init(); switch (get_board_revision()) { - case REVISION_XM_A: - case REVISION_XM_B: + case REVISION_XM_AB: twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); break; default: diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index 76be358..6dd2ffe 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -23,8 +23,7 @@ const omap3_sysinfo sysinfo = { #define REVISION_AXBX 0x7 #define REVISION_CX 0x6 #define REVISION_C4 0x5 -#define REVISION_XM_A 0x0 -#define REVISION_XM_B 0x1 +#define REVISION_XM_AB 0x0 #define REVISION_XM_C 0x2 /* -- cgit v0.10.2 From 102ce9ea7afdda80fe25aa786975e1722196bdb9 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 15 Jul 2013 07:11:31 -0500 Subject: omap3_beagle: enable CMD_FS_GENERIC and simplify load of image/ramdisk CMD_FS_GENERIC allows us to simplify where we load up our image from either from ext2/fat etc. So, lets use that instead of cumbersome options we currently use. Sticking with existing conventions, defaults will be: ramdisk=ramdisk.gz bootpart=0:2 (second partition) bootdir=/boot (/boot in second partition) This matches with the default behavior, these can be overriden by env files as needed. Signed-off-by: Nishanth Menon diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index a5cd66d..4d93ad2 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -134,6 +134,7 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_FS_GENERIC /* Generic FS support */ #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define MTDIDS_DEFAULT "nand0=nand" @@ -195,6 +196,9 @@ "rdaddr=0x81000000\0" \ "usbtty=cdc_acm\0" \ "bootfile=uImage\0" \ + "ramdisk=ramdisk.gz\0" \ + "bootdir=/boot\0" \ + "bootpart=0:2\0" \ "console=ttyO2,115200n8\0" \ "mpurate=auto\0" \ "buddy=none\0" \ @@ -243,9 +247,8 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${ramroot} " \ "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \ + "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ @@ -277,7 +280,7 @@ "echo Running uenvcmd ...;" \ "run uenvcmd;" \ "fi;" \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot;" \ "fi;" \ "fi;" \ -- cgit v0.10.2 From 2ade496fd88ebe947f8fd8ae4a07fc3bf1f41e60 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 15 Jul 2013 07:11:32 -0500 Subject: omap3_beagle: support findfdt and loadfdt for devicetree support For folks not using concatenated device tree with uImage, having an handy function to find and load device tree is very handy. So introduce findfdt and loadfdt and run findfdt by default to make it easier on user scripts. Signed-off-by: Nishanth Menon diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 4d93ad2..dacabb6 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -194,6 +194,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "rdaddr=0x81000000\0" \ + "fdt_high=0xffffffff\0" \ + "fdtaddr=0x80f80000\0" \ "usbtty=cdc_acm\0" \ "bootfile=uImage\0" \ "ramdisk=ramdisk.gz\0" \ @@ -234,6 +236,17 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ + "findfdt=" \ + "if test $beaglerev = AxBx; then " \ + "setenv fdtfile omap3-beagle.dtb; fi; " \ + "if test $beaglerev = Cx; then " \ + "setenv fdtfile omap3-beagle.dtb; fi; " \ + "if test $beaglerev = xMAB; then " \ + "setenv fdtfile omap3-beagle-xm.dtb; fi; " \ + "if test $beaglerev = xMC; then " \ + "setenv fdtfile omap3-beagle-xm.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ @@ -249,6 +262,7 @@ "rootfstype=${ramrootfstype}\0" \ "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ @@ -265,6 +279,7 @@ "userbutton_nonxm=gpio input 7;\0" /* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */ #define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run userbutton; then " \ "setenv bootenv uEnv.txt;" \ -- cgit v0.10.2 From ea70690d6636bf1461ab601fbaa00039896d76c6 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 15 Jul 2013 07:11:33 -0500 Subject: omap3_beagle: support booting from zImage and device tree as last option If no other bootoption works, try loading up device tree and zImage. This is selected as the last option to allow backward compatibility as well as support the recent trend in moving kernel boot to using zImage and device tree. NOTE: if uImage is present in bootpart, it will try this first and will assume this is to be booted with bootm (so may be concatenated image or plain vanilla ATAG MACHINE_ID based image) Signed-off-by: Nishanth Menon diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index dacabb6..4487451 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -266,6 +266,9 @@ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ + "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} 280000 400000; " \ @@ -300,6 +303,11 @@ "fi;" \ "fi;" \ "run nandboot;" \ + "setenv bootfile zImage;" \ + "if run loadimage; then " \ + "run loadfdt;" \ + "run mmcbootz; " \ + "fi; " \ #define CONFIG_AUTO_COMPLETE 1 /* -- cgit v0.10.2 From 5ea7f0e328c19542ce96d8242125b51b3dbca86b Mon Sep 17 00:00:00 2001 From: Pardeep Kumar Singla Date: Thu, 25 Jul 2013 12:12:13 -0500 Subject: mx6: Factor out common HDMI setup code Instead of duplicating HDMI setup code for every mx6 board, factor out the common code Signed-off-by: Pardeep Kumar Singla Acked-By: Eric Nelson diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 3c0d908..ce063ae 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -468,6 +468,14 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +void enable_ipu_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; + writel(reg, &mxc_ccm->CCGR3); +} /***************************************************/ U_BOOT_CMD( diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index fc436fb..a79369f 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include struct scu_regs { u32 ctrl; @@ -228,3 +230,44 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { } + +#ifdef CONFIG_IMX_HDMI +void imx_enable_hdmi_phy(void) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + u8 reg; + reg = readb(&hdmi->phy_conf0); + reg |= HDMI_PHY_CONF0_PDZ_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); +} + +void imx_setup_hdmi(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + int reg; + + /* Turn on HDMI PHY clock */ + reg = readl(&mxc_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| + MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; + writel(reg, &mxc_ccm->CCGR2); + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_PODF_DIVIDE_BY_3 + << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + |(CHSCCDR_IPU_PRE_CLK_540M_PFD + << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); +} +#endif diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index cfd4edc..d03d24a 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -65,5 +65,5 @@ void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); - +void enable_ipu_clock(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h index 9dccb3f..5cd6aa6 100644 --- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h +++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h @@ -21,6 +21,11 @@ #ifndef __MXC_HDMI_H__ #define __MXC_HDMI_H__ +#ifdef CONFIG_IMX_HDMI +void imx_enable_hdmi_phy(void); +void imx_setup_hdmi(void); +#endif + /* * Hdmi controller registers */ diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 8f0f9b8..1b82633 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -480,22 +480,9 @@ static int detect_hdmi(struct display_info_t const *dev) return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; } -static void enable_hdmi(struct display_info_t const *dev) +static void do_enable_hdmi(struct display_info_t const *dev) { - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - u8 reg; - printf("%s: setup HDMI monitor\n", __func__); - reg = readb(&hdmi->phy_conf0); - reg |= HDMI_PHY_CONF0_PDZ_MASK; - writeb(reg, &hdmi->phy_conf0); - - udelay(3000); - reg |= HDMI_PHY_CONF0_ENTMDS_MASK; - writeb(reg, &hdmi->phy_conf0); - udelay(3000); - reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; - writeb(reg, &hdmi->phy_conf0); - writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); + imx_enable_hdmi_phy(); } static int detect_i2c(struct display_info_t const *dev) @@ -528,7 +515,7 @@ static struct display_info_t const displays[] = {{ .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, .detect = detect_hdmi, - .enable = enable_hdmi, + .enable = do_enable_hdmi, .mode = { .name = "HDMI", .refresh = 60, @@ -653,25 +640,15 @@ static void setup_display(void) struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - int reg; + enable_ipu_clock(); + imx_setup_hdmi(); /* Turn on LDB0,IPU,IPU DI0 clocks */ reg = __raw_readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET - |MXC_CCM_CCGR3_LDB_DI0_MASK; + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; writel(reg, &mxc_ccm->CCGR3); - /* Turn on HDMI PHY clock */ - reg = __raw_readl(&mxc_ccm->CCGR2); - reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK - |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; - writel(reg, &mxc_ccm->CCGR2); - - /* clear HDMI PHY reset */ - writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); - /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); writel(0x13<pfd_480_set); @@ -689,15 +666,8 @@ static void setup_display(void) writel(reg, &mxc_ccm->cscmr2); reg = readl(&mxc_ccm->chsccdr); - reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK - |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK - |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - <chsccdr); reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 43c02ac..6cd28ed 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -211,23 +211,6 @@ int board_phy_config(struct phy_device *phydev) } #if defined(CONFIG_VIDEO_IPUV3) -static void enable_hdmi(void) -{ - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - u8 reg; - reg = readb(&hdmi->phy_conf0); - reg |= HDMI_PHY_CONF0_PDZ_MASK; - writeb(reg, &hdmi->phy_conf0); - - udelay(3000); - reg |= HDMI_PHY_CONF0_ENTMDS_MASK; - writeb(reg, &hdmi->phy_conf0); - udelay(3000); - reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; - writeb(reg, &hdmi->phy_conf0); - writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); -} - static struct fb_videomode const hdmi = { .name = "HDMI", .refresh = 60, @@ -253,7 +236,7 @@ int board_video_skip(void) if (ret) printf("HDMI cannot be configured: %d\n", ret); - enable_hdmi(); + imx_enable_hdmi_phy(); return ret; } @@ -261,33 +244,14 @@ int board_video_skip(void) static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; int reg; - /* Turn on IPU clock */ - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; - writel(reg, &mxc_ccm->CCGR3); - - /* Turn on HDMI PHY clock */ - reg = readl(&mxc_ccm->CCGR2); - reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK - | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; - writel(reg, &mxc_ccm->CCGR2); - - /* clear HDMI PHY reset */ - writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + enable_ipu_clock(); + imx_setup_hdmi(); reg = readl(&mxc_ccm->chsccdr); - reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK - | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK - | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) - | (CHSCCDR_PODF_DIVIDE_BY_3 - << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) - | (CHSCCDR_IPU_PRE_CLK_540M_PFD - << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->chsccdr); } #endif /* CONFIG_VIDEO_IPUV3 */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 85eecfc..b057039 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -154,6 +154,7 @@ #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_CMD_HDMIDETECT #define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index dd06bd7..1f83e89 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -100,6 +100,7 @@ #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_HDMI #if defined(CONFIG_MX6DL) #define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb" -- cgit v0.10.2 From 58cc97877713f46d2e7dfd515844c29c70c56d82 Mon Sep 17 00:00:00 2001 From: Pardeep Kumar Singla Date: Thu, 25 Jul 2013 12:12:14 -0500 Subject: mx6qsabresd: Add splash screen support via HDMI Signed-off-by: Pardeep Kumar Singla diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 222ee98..4694b5c 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -29,7 +29,12 @@ #include #include #include - +#include +#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -239,6 +244,60 @@ int board_phy_config(struct phy_device *phydev) return 0; } +#if defined(CONFIG_VIDEO_IPUV3) +static struct fb_videomode const hdmi = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +}; + +int board_video_skip(void) +{ + int ret; + + ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); + + if (ret) + printf("HDMI cannot be configured: %d\n", ret); + + imx_enable_hdmi_phy(); + return ret; +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int board_eth_init(bd_t *bis) { int ret; @@ -255,6 +314,9 @@ int board_eth_init(bd_t *bis) int board_early_init_f(void) { setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif return 0; } diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 53cc559..dd93fff 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -20,6 +20,7 @@ #define CONFIG_MX6 #include "mx6_common.h" +#include #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -32,7 +33,7 @@ #define CONFIG_REVISION_TAG /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 76675f4..5637c19 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -17,6 +17,9 @@ #ifndef __MX6QSABRESD_CONFIG_H #define __MX6QSABRESD_CONFIG_H +#include +#include + #define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONSOLE_DEV "ttymxc0" @@ -31,4 +34,20 @@ #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ #endif +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_HDMI + #endif /* __MX6QSABRESD_CONFIG_H */ -- cgit v0.10.2 From a11f18737c996a737b85be46b2e8363b7fa2659c Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Wed, 24 Jul 2013 17:57:06 -0700 Subject: imx: Add documentation for imx specific commands CONFIG_CMD_HDMIDETECT CONFIG_CMD_BMODE Signed-off-by: Robert Winkler Acked-by: Otavio Salvador diff --git a/README b/README index bcfffc3..657faaa 100644 --- a/README +++ b/README @@ -2598,6 +2598,21 @@ CBFS (Coreboot Filesystem) support Note: There is also a sha1sum command, which should perhaps be deprecated in favour of 'hash sha1'. +- Freescale i.MX specific commands: + CONFIG_CMD_HDMIDETECT + This enables 'hdmidet' command which returns true if an + HDMI monitor is detected. This command is i.MX 6 specific. + + CONFIG_CMD_BMODE + This enables the 'bmode' (bootmode) command for forcing + a boot from specific media. + + This is useful for forcing the ROM's usb downloader to + activate upon a watchdog reset which is nice when iterating + on U-Boot. Using the reset button or running bmode normal + will set it back to normal. This command currently + supports i.MX53 and i.MX6. + - Signing support: CONFIG_RSA -- cgit v0.10.2 From 10f779da54b8a8c85df6d58592c40836d8e7ed49 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Tue, 23 Jul 2013 15:07:56 -0700 Subject: imx: nitrogen6x: mx6qsabrelite: Add support for DVI monitors A little background is probably appropriate for this patch. Since "the beginning" of usage of the SABRE Lite and Nitrogen6x boards, DVI detection has been somewhat broken. Some (most) DVI monitors don't produce the "HPD" bit in the PHY_STAT0 register, but do show proper toggling of the RX_SENSE0..3 bits. Creating a new the bit-mask to include all five bits and modifying the 'hdmidet' command and internal detection routines allows these monitors to function properly in U-Boot. A related patch to our kernels allows things to work under Linux: https://github.com/boundarydevices/linux-imx6/commit/7d8752905c118af9063738a533227de0b2f6ecd4 Signed-off-by: Robert Winkler Acked-by: Stefano Babic diff --git a/arch/arm/imx-common/cmd_hdmidet.c b/arch/arm/imx-common/cmd_hdmidet.c index 794bf50..ce0b26e 100644 --- a/arch/arm/imx-common/cmd_hdmidet.c +++ b/arch/arm/imx-common/cmd_hdmidet.c @@ -27,8 +27,7 @@ static int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - u8 reg = readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; - return (reg&HDMI_PHY_HPD) ? 0 : 1; + return (readb(&hdmi->phy_stat0) & HDMI_DVI_STAT) ? 0 : 1; } U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet, diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h index 5cd6aa6..2d93658 100644 --- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h +++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h @@ -901,6 +901,9 @@ enum { HDMI_PHY_HPD = 0x02, HDMI_PHY_TX_PHY_LOCK = 0x01, +/* Convenience macro RX_SENSE | HPD */ + HDMI_DVI_STAT = 0xF2, + /* PHY_I2CM_SLAVE_ADDR field values */ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 1b82633..ff033da 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -477,7 +477,7 @@ struct display_info_t { static int detect_hdmi(struct display_info_t const *dev) { struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; + return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; } static void do_enable_hdmi(struct display_info_t const *dev) -- cgit v0.10.2 From 4acb4d391f005c0c72f7b84041b3884e4260a5a4 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Fri, 26 Jul 2013 17:53:45 -0700 Subject: mxc_ipuv3: fix memory alignment of framebuffer The frame-buffer on i.MX boards needs to be aligned for DMA. Signed-off-by: Eric Nelson diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c index ace226c..d922d5d 100644 --- a/drivers/video/mxc_ipuv3_fb.c +++ b/drivers/video/mxc_ipuv3_fb.c @@ -415,8 +415,9 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length; } - - fbi->screen_base = (char *)malloc(fbi->fix.smem_len); + fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN); + fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN, + fbi->fix.smem_len); fbi->fix.smem_start = (unsigned long)fbi->screen_base; if (fbi->screen_base == 0) { puts("Unable to allocate framebuffer memory\n"); -- cgit v0.10.2 From 97559b5203e01b033e01aac2d5c0858b2bdaa7aa Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 17 Jul 2013 12:24:30 -0400 Subject: board/ti/am335x/README: Document NAND programming The AM335x GP EVM ships with NAND. Document programming of the chip including the redundant locations that the ROM will check. Signed-off-by: Tom Rini diff --git a/board/ti/am335x/README b/board/ti/am335x/README index ccc5e16..6d45352 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -13,6 +13,30 @@ documented in TI's reference designs: - AM335x EVM SK - Beaglebone White - Beaglebone Black +' +NAND +==== + +The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In +this example to program the NAND we assume that an SD card has been +inserted with the files to write in the first SD slot and that mtdparts +have been configured correctly for the board. As a time saving measure we +load MLO into memory in one location, copy it into the three locatations +that the ROM checks for additional valid copies, then load U-Boot into +memory. We then write that whole section of memory to NAND. + +U-Boot # mmc rescan +U-Boot # env default -f -a +U-Boot # nand erase.chip +U-Boot # saveenv +U-Boot # load mmc 0 81000000 MLO +U-Boot # cp.b 81000000 81020000 20000 +U-Boot # cp.b 81000000 81040000 20000 +U-Boot # cp.b 81000000 81060000 20000 +U-Boot # load mmc 0 81080000 u-boot.img +U-Boot # nand write 81000000 0 260000 +U-Boot # load mmc 0 ${loadaddr} uImage +U-Boot # nand write ${loadaddr} kernel 500000 Falcon Mode =========== -- cgit v0.10.2 From 989bd7a8cb443cf2fe607ec69b4da61f3040a0bb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 18 Jul 2013 15:12:58 -0400 Subject: am335x_evm: Drop useless CONFIG_ENV_IS_NOWHERE We always set a CONFIG_ENV_IS_...somewhere... so drop the initial define of NOWHERE. Reviewed-by: Peter Korsgaard Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 0f12c75..ea8669a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -306,8 +306,6 @@ #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_ENV_IS_NOWHERE - /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK @@ -467,7 +465,6 @@ * 0x442000 - 0x800000 : Userland */ #if defined(CONFIG_SPI_BOOT) -# undef CONFIG_ENV_IS_NOWHERE # define CONFIG_ENV_IS_IN_SPI_FLASH # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED # define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ @@ -515,7 +512,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #if !defined(CONFIG_SPI_BOOT) -#undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -- cgit v0.10.2 From 6454028abbfcbfb6c448bafa165eeebf2da420c8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 18 Jul 2013 15:12:59 -0400 Subject: am335x_evm: Update SPI_BOOT support, add MTDPARTS info - Style cleanup (# define -> #define) - Due to ROM issues, redudant loading isn't feasible, so drop. - Given extra space, increase max size of U-Boot to 512KiB - Correct env size to match usage (we had not re-defined ENV_SIZE). - Given extra space, keep env size as 128KiB, add redundant environment. Reviewed-by: Peter Korsgaard Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ea8669a..6bc4423 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -367,7 +367,7 @@ #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SPL_MUSB_NEW_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" @@ -453,22 +453,27 @@ #endif /* - * Default to using SPI for environment, etc. We have multiple copies - * of SPL as the ROM will check these locations. - * 0x0 - 0x20000 : First copy of SPL - * 0x20000 - 0x40000 : Second copy of SPL - * 0x40000 - 0x60000 : Third copy of SPL - * 0x60000 - 0x80000 : Fourth copy of SPL - * 0x80000 - 0xDF000 : U-Boot - * 0xDF000 - 0xE0000 : U-Boot Environment - * 0xE0000 - 0x442000 : Linux Kernel + * Default to using SPI for environment, etc. + * 0x000000 - 0x020000 : SPL (128KiB) + * 0x020000 - 0x0A0000 : U-Boot (512KiB) + * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) + * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) + * 0x0E0000 - 0x442000 : Linux Kernel * 0x442000 - 0x800000 : Userland */ #if defined(CONFIG_SPI_BOOT) -# define CONFIG_ENV_IS_IN_SPI_FLASH -# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ -# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ +#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=m25p80-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \ + "512k(u-boot),128k(u-boot-env1)," \ + "128k(u-boot-env2),3464k(kernel)," \ + "-(rootfs)" #endif /* SPI support */ /* Unsupported features */ @@ -497,13 +502,6 @@ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND #define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nand0=omap2-nand.0" -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ - "128k(SPL.backup1)," \ - "128k(SPL.backup2)," \ - "128k(SPL.backup3),1792k(u-boot)," \ - "128k(u-boot-spl-os)," \ - "128k(u-boot-env),5m(kernel),-(rootfs)" #define CONFIG_NAND_OMAP_GPMC #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ @@ -512,6 +510,13 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #if !defined(CONFIG_SPI_BOOT) +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3),1792k(u-boot)," \ + "128k(u-boot-spl-os)," \ + "128k(u-boot-env),5m(kernel),-(rootfs)" #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -- cgit v0.10.2 From ace4275eb33b7833d96fa2db02d253e06cc1a734 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 18 Jul 2013 15:13:01 -0400 Subject: am335x_evm: Rework board_is_foo() checks We rework the various board_is_foo() checks to take a pointer to struct am335x_baseboard_id rather than using a local copy in board.c. This allows us to make use of the same checks in mux.c as well as fixing problems when this code could be running from read-only memory. Reviewed-by: Peter Korsgaard Signed-off-by: Tom Rini diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 15e249d..00802b6 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -40,43 +40,10 @@ static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -static struct am335x_baseboard_id __attribute__((section (".data"))) header; - -static inline int board_is_bone(void) -{ - return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); -} - -static inline int board_is_bone_lt(void) -{ - return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); -} - -static inline int board_is_evm_sk(void) -{ - return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); -} - -static inline int board_is_idk(void) -{ - return !strncmp(header.config, "SKU#02", 6); -} - -static int __maybe_unused board_is_gp_evm(void) -{ - return !strncmp("A33515BB", header.name, 8); -} - -int board_is_evm_15_or_later(void) -{ - return (!strncmp("A33515BB", header.name, 8) && - strncmp("1.5", header.version, 3) <= 0); -} - /* * Read header information from EEPROM into global structure. */ -static int read_eeprom(void) +static int read_eeprom(struct am335x_baseboard_id *header) { /* Check if baseboard eeprom is available */ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { @@ -86,28 +53,28 @@ static int read_eeprom(void) } /* read the eeprom using i2c */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, - sizeof(header))) { + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, + sizeof(struct am335x_baseboard_id))) { puts("Could not read the EEPROM; something fundamentally" " wrong on the I2C bus.\n"); return -EIO; } - if (header.magic != 0xEE3355AA) { + if (header->magic != 0xEE3355AA) { /* * read the eeprom using i2c again, * but use only a 1 byte address */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, - (uchar *)&header, sizeof(header))) { + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct am335x_baseboard_id))) { puts("Could not read the EEPROM; something " "fundamentally wrong on the I2C bus.\n"); return -EIO; } - if (header.magic != 0xEE3355AA) { + if (header->magic != 0xEE3355AA) { printf("Incorrect magic number (0x%x) in EEPROM\n", - header.magic); + header->magic); return -EINVAL; } } @@ -281,12 +248,14 @@ int spl_start_uboot(void) */ void s_init(void) { +#ifdef CONFIG_SPL_BUILD + struct am335x_baseboard_id header; + /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. */ -#ifdef CONFIG_SPL_BUILD save_omap_boot_params(); #endif @@ -335,11 +304,11 @@ void s_init(void) /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (read_eeprom() < 0) + if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); enable_board_pin_mux(&header); - if (board_is_evm_sk()) { + if (board_is_evm_sk(&header)) { /* * EVM SK 1.2A and later use gpio0_7 to enable DDR3. * This is safe enough to do on older revs. @@ -348,15 +317,15 @@ void s_init(void) gpio_direction_output(GPIO_DDR_VTT_EN, 1); } - if (board_is_evm_sk()) + if (board_is_evm_sk(&header)) config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); - else if (board_is_bone_lt()) + else if (board_is_bone_lt(&header)) config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data, 0); - else if (board_is_evm_15_or_later()) + else if (board_is_evm_15_or_later(&header)) config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); else @@ -370,10 +339,6 @@ void s_init(void) */ int board_init(void) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (read_eeprom() < 0) - puts("Could not get board ID.\n"); - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; gpmc_init(); @@ -386,6 +351,10 @@ int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG char safe_string[HDR_NAME_LEN + 1]; + struct am335x_baseboard_id header; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); /* Now set variables based on the header. */ strncpy(safe_string, (char *)header.name, sizeof(header.name)); @@ -450,6 +419,7 @@ int board_eth_init(bd_t *bis) int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; + __maybe_unused struct am335x_baseboard_id header; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); @@ -471,7 +441,11 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_DRIVER_TI_CPSW - if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + if (board_is_bone(&header) || board_is_bone_lt(&header) || + board_is_idk(&header)) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; @@ -500,7 +474,7 @@ int board_eth_init(bd_t *bis) #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 #define AR8051_RGMII_TX_CLK_DLY 0x100 - if (board_is_evm_sk() || board_is_gp_evm()) { + if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { const char *devname; devname = miiphy_get_current_dev(); diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index 9fea1f1..bc700d5 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -29,6 +29,37 @@ struct am335x_baseboard_id { char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; }; +static inline int board_is_bone(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BONE", HDR_NAME_LEN); +} + +static inline int board_is_bone_lt(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN); +} + +static inline int board_is_evm_sk(struct am335x_baseboard_id *header) +{ + return !strncmp("A335X_SK", header->name, HDR_NAME_LEN); +} + +static inline int board_is_idk(struct am335x_baseboard_id *header) +{ + return !strncmp(header->config, "SKU#02", 6); +} + +static inline int board_is_gp_evm(struct am335x_baseboard_id *header) +{ + return !strncmp("A33515BB", header->name, HDR_NAME_LEN); +} + +static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header) +{ + return (board_is_gp_evm(header) && + strncmp("1.5", header->version, 3) <= 0); +} + /* * We have three pin mux functions that must exist. We must be able to enable * uart0, for initial output and i2c0 to read the main EEPROM. We then have a diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 0283708..2e09d98 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -262,13 +262,13 @@ static unsigned short detect_daughter_board_profile(void) void enable_board_pin_mux(struct am335x_baseboard_id *header) { /* Do board-specific muxes. */ - if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) { + if (board_is_bone(header)) { /* Beaglebone pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(mmc1_pin_mux); - } else if (!strncmp(header->config, "SKU#01", 6)) { + } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ unsigned short profile = detect_daughter_board_profile(); configure_module_pin_mux(rgmii1_pin_mux); @@ -283,7 +283,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } - } else if (!strncmp(header->config, "SKU#02", 6)) { + } else if (board_is_idk(header)) { /* * Industrial Motor Control (IDK) * note: IDK console is on UART3 by default. @@ -292,13 +292,13 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_no_cd_pin_mux); - } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) { + } else if (board_is_evm_sk(header)) { /* Starter Kit EVM */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux_sk_evm); - } else if (!strncmp(header->name, "A335BNLT", HDR_NAME_LEN)) { + } else if (board_is_bone_lt(header)) { /* Beaglebone LT pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); -- cgit v0.10.2 From 392bba4ad0049832f50eb368a04992f9719744b0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 18 Jul 2013 15:13:02 -0400 Subject: am33xx: Correct gpmc_cfg->irqstatus/enable Based on our usage of the GPMC, either with NOR or NAND we do not need to be setting the irqstatus or irqenable bits and should clear them like we have historically. Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index f81c9a8..03e8c66 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -69,8 +69,8 @@ void gpmc_init(void) #endif /* global settings */ writel(0x00000008, &gpmc_cfg->sysconfig); - writel(0x00000100, &gpmc_cfg->irqstatus); - writel(0x00000100, &gpmc_cfg->irqenable); + writel(0x00000000, &gpmc_cfg->irqstatus); + writel(0x00000000, &gpmc_cfg->irqenable); writel(0x00000012, &gpmc_cfg->config); /* * Disable the GPMC0 config set by ROM code -- cgit v0.10.2 From cd8845d7a49687e9e7f727c9d821accf22854dd3 Mon Sep 17 00:00:00 2001 From: Steve Kipisz Date: Thu, 18 Jul 2013 15:13:03 -0400 Subject: am335x_evm: Add support for the NOR module on the memory cape This patch adds support for the NOR module that attaches to the memory cape for a Beaglebone board. This does not add booting support; only support so that you can boot from SD/MMC and see the NOR module so that it can be programmed. Signed-off-by: Steve Kipisz [trini: Clean up config changes slightly] Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index 03e8c66..b6eb466 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -71,7 +71,11 @@ void gpmc_init(void) writel(0x00000008, &gpmc_cfg->sysconfig); writel(0x00000000, &gpmc_cfg->irqstatus); writel(0x00000000, &gpmc_cfg->irqenable); +#ifdef CONFIG_NOR + writel(0x00000200, &gpmc_cfg->config); +#else writel(0x00000012, &gpmc_cfg->config); +#endif /* * Disable the GPMC0 config set by ROM code */ diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index aef4e82..983ea28 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -30,6 +30,7 @@ * * Currently valid part Names are (PART): * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL */ #define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 @@ -45,6 +46,14 @@ #define M_NAND_GPMC_CONFIG6 0x16000f80 #define M_NAND_GPMC_CONFIG7 0x00000008 +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 /* max number of GPMC regs */ diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 00802b6..b12341d 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -339,10 +340,22 @@ void s_init(void) */ int board_init(void) { +#ifdef CONFIG_NOR + const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; +#endif + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; gpmc_init(); +#ifdef CONFIG_NOR + /* Reconfigure CS0 for NOR instead of NAND. */ + enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0], + CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M); +#endif + return 0; } diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 2e09d98..187468e 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -190,6 +190,56 @@ static struct module_pin_mux nand_pin_mux[] = { {-1}, }; +#if defined(CONFIG_NOR) +static struct module_pin_mux bone_norcape_pin_mux[] = { + {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */ + {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */ + {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */ + {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */ + {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */ + {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */ + {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */ + {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */ + {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */ + {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */ + {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */ + {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */ + {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */ + {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */ + {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */ + {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */ + {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */ + {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */ + {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */ + {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */ + {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */ + {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */ + {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */ + {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */ + {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */ + {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */ + {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */ + {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */ + {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */ + {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */ + {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */ + {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */ + {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */ + {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */ + {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */ + {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */ + + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */ + {-1}, +}; +#endif + + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -268,6 +318,9 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(mmc1_pin_mux); +#if defined(CONFIG_NOR) + configure_module_pin_mux(bone_norcape_pin_mux); +#endif } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ unsigned short profile = detect_daughter_board_profile(); diff --git a/boards.cfg b/boards.cfg index 94261da..4c90579 100644 --- a/boards.cfg +++ b/boards.cfg @@ -242,6 +242,7 @@ vexpress_ca15_tc2 arm armv7 vexpress armltd vexpress_ca5x2 arm armv7 vexpress armltd vexpress_ca9x4 arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 +am335x_evm_nor arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 6bc4423..48491e7 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -523,4 +523,32 @@ #endif #endif +/* + * NOR Size = 16 MiB + * Number of Sectors/Blocks = 128 + * Sector Size = 128 KiB + * Word length = 16 bits + * Default layout: + * 0x000000 - 0x07FFFF : U-Boot (512 KiB) + * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB) + * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB) + * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB) + * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) + */ +#if defined(CONFIG_NOR) +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_FLASH +#endif /* NOR support */ + #endif /* ! __CONFIG_AM335X_EVM_H */ -- cgit v0.10.2 From c5c7a7c32d552592ac49749e5c184c89bd50c098 Mon Sep 17 00:00:00 2001 From: Steve Kipisz Date: Thu, 18 Jul 2013 15:13:04 -0400 Subject: am335x_evm: Add support to boot from NOR. NOR requires that s_init be within the first 4KiB of the image so that we can perform the rest of the required pinmuxing to talk with the rest of NOR that we are found on. When NOR_BOOT is set we save our environment in NOR at 512KiB and a redundant copy at 768KiB. We avoid using SPL for this case and u-boot.bin is written directly to the start of NOR. We enclose the DMM-related parts of arch/arm/cpu/armv7/am33xx/emif4.c with TI81xx checks as at this time U-Boot does not discard unused sections in the main build and this code relies on functions specific to (and only provided in) ti81xx-related code. Cc: Albert ARIBAUD Signed-off-by: Steve Kipisz Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 07ab91c..f1623db 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -142,7 +142,7 @@ int arch_misc_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) void rtc32k_enable(void) { struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index ad7b70f..55dc321 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -35,9 +35,11 @@ void dram_init_banksize(void) } -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) +#ifdef CONFIG_TI81XX static struct dmm_lisa_map_regs *hw_lisa_map_regs = (struct dmm_lisa_map_regs *)DMM_BASE; +#endif static struct vtp_reg *vtpreg[2] = { (struct vtp_reg *)VTP0_CTRL_ADDR, (struct vtp_reg *)VTP1_CTRL_ADDR}; @@ -45,6 +47,7 @@ static struct vtp_reg *vtpreg[2] = { static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; #endif +#ifdef CONFIG_TI81XX void config_dmm(const struct dmm_lisa_map_regs *regs) { enable_dmm_clocks(); @@ -59,6 +62,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs) writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); } +#endif static void config_vtp(int nr) { diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile index cb2b999..3dbeeda 100644 --- a/board/ti/am335x/Makefile +++ b/board/ti/am335x/Makefile @@ -10,7 +10,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -ifdef CONFIG_SPL_BUILD +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y) COBJS := mux.o endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index b12341d..728afc2 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -83,7 +83,7 @@ static int read_eeprom(struct am335x_baseboard_id *header) return 0; } -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) static const struct ddr_data ddr2_data = { .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | (MT47H128M16RT25E_RD_DQS<<20) | @@ -249,10 +249,28 @@ int spl_start_uboot(void) */ void s_init(void) { -#ifdef CONFIG_SPL_BUILD - struct am335x_baseboard_id header; + __maybe_unused struct am335x_baseboard_id header; /* + * The ROM will only have set up sufficient pinmux to allow for the + * first 4KiB NOR to be read, we must finish doing what we know of + * the NOR mux in this space in order to continue. + */ +#ifdef CONFIG_NOR_BOOT + asm("stmfd sp!, {r2 - r4}"); + asm("movw r4, #0x8A4"); + asm("movw r3, #0x44E1"); + asm("orr r4, r4, r3, lsl #16"); + asm("mov r2, #9"); + asm("mov r3, #8"); + asm("gpmc_mux: str r2, [r4], #4"); + asm("subs r3, r3, #1"); + asm("bne gpmc_mux"); + asm("ldmfd sp!, {r2 - r4}"); +#endif + +#ifdef CONFIG_SPL_BUILD + /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. @@ -270,7 +288,7 @@ void s_init(void) while (readl(&wdtimer->wdtwwps) != 0x0) ; -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) /* Setup the PLLs and the clocks for the peripherals */ pll_init(); @@ -298,9 +316,16 @@ void s_init(void) uart_soft_reset(); +#if defined(CONFIG_NOR_BOOT) + /* We want our console now. */ + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; +#else gd = &gdata; preloader_console_init(); +#endif /* Initalize the board header */ enable_i2c0_pin_mux(); diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 187468e..5b7ed63 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -190,7 +190,7 @@ static struct module_pin_mux nand_pin_mux[] = { {-1}, }; -#if defined(CONFIG_NOR) +#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) static struct module_pin_mux bone_norcape_pin_mux[] = { {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */ {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */ @@ -317,8 +317,10 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#ifndef CONFIG_NOR configure_module_pin_mux(mmc1_pin_mux); -#if defined(CONFIG_NOR) +#endif +#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) configure_module_pin_mux(bone_norcape_pin_mux); #endif } else if (board_is_gp_evm(header)) { diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds new file mode 100644 index 0000000..a173f62 --- /dev/null +++ b/board/ti/am335x/u-boot.lds @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + board/ti/am335x/libam335x.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/boards.cfg b/boards.cfg index 4c90579..8f1da74 100644 --- a/boards.cfg +++ b/boards.cfg @@ -243,6 +243,7 @@ vexpress_ca5x2 arm armv7 vexpress armltd vexpress_ca9x4 arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 am335x_evm_nor arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR +am335x_evm_norboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 48491e7..3ca35c3 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -40,6 +40,9 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +/* Custom script for NOR */ +#define CONFIG_SYS_LDSCRIPT "board/ti/am335x/u-boot.lds" + #define CONFIG_SYS_CACHELINE_SIZE 64 /* commands to include */ @@ -306,6 +309,7 @@ #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_SYS_CONSOLE_INFO_QUIET +#ifndef CONFIG_NOR_BOOT /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK @@ -377,6 +381,7 @@ #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC +#endif #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) @@ -405,14 +410,18 @@ * header. That is 0x800FFFC0--0x80100000 should not be used for any * other needs. */ +#ifdef CONFIG_NOR_BOOT +#define CONFIG_SYS_TEXT_BASE 0x08000000 +#else #define CONFIG_SYS_TEXT_BASE 0x80800000 +#endif #define CONFIG_SYS_SPL_MALLOC_START 0x80a08000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) #define CONFIG_SKIP_LOWLEVEL_INIT #endif @@ -509,7 +518,7 @@ /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#if !defined(CONFIG_SPI_BOOT) +#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ "128k(SPL.backup1)," \ @@ -547,6 +556,19 @@ #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#ifdef CONFIG_NOR_BOOT +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */ +#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */ +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ + "512k(u-boot)," \ + "128k(u-boot-env1)," \ + "128k(u-boot-env2)," \ + "4m(kernel),-(rootfs)" +#endif #define CONFIG_MTD_DEVICE #define CONFIG_CMD_FLASH #endif /* NOR support */ -- cgit v0.10.2 From 486da22967474f3f72717883a4315fda46346897 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 18 Jul 2013 15:13:05 -0400 Subject: board/ti/am335x/README: Document NOR programming The Beaglebone White may be populated with a memory cape that has a NOR module. Document how to program it. Signed-off-by: Tom Rini diff --git a/board/ti/am335x/README b/board/ti/am335x/README index 6d45352..67b5246 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -38,6 +38,29 @@ U-Boot # nand write 81000000 0 260000 U-Boot # load mmc 0 ${loadaddr} uImage U-Boot # nand write ${loadaddr} kernel 500000 +NOR +=== + +The Beaglebone White can be equiped with a "memory cape" that in turn can +have a NOR module plugged into it. In this case it is then possible to +program and boot from NOR. Note that due to how U-Boot is architectured we +must build a specific version of U-Boot that knows we have NOR flash. This +build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot' +build that will assume that the environment is on NOR rather than NAND. In +the following example we assume that and SD card has been populated with +MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the +'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a +binary must be written to the start of NOR, with no header or similar +prepended. In the following example we use a size of 512KiB (0x80000) +as that is how much space we set aside before the environment, as per +the config file. + +U-Boot # mmc rescan +U-Boot # load mmc 0 ${loadaddr} u-boot.bin +U-Boot # protect off 08000000 +80000 +U-Boot # erase 08000000 +80000 +U-Boot # cp.b ${loadaddr} 08000000 ${filesize} + Falcon Mode =========== -- cgit v0.10.2 From f6d1f6e4a58edae4776937647381a43fea5e83a5 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 23 Jul 2013 15:32:36 +0200 Subject: net, phy, cpsw: fix gigabit register access accessing a lan9303 switch with the cpsw driver results in wrong speed detection, as the switch sets the BMSR_ERCAP in BMSR register, and follow read of the MII_STAT1000 register fails, as the switch does not support it. Current code did not check, if a phy_read() fails ... fix this. Signed-off-by: Heiko Schocher Cc: Joe Hershberger Acked-by: Mugunthan V N Signed-off-by: Tom Rini diff --git a/boards.cfg b/boards.cfg index 8f1da74..ffb8a27 100644 --- a/boards.cfg +++ b/boards.cfg @@ -241,16 +241,16 @@ integratorcp_cm946es arm arm946es integrator armltd vexpress_ca15_tc2 arm armv7 vexpress armltd vexpress_ca5x2 arm armv7 vexpress armltd vexpress_ca9x4 arm armv7 vexpress armltd -am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 +am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND am335x_evm_nor arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR am335x_evm_norboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT -am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 -am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 -am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4 -am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5 -am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 -am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT +am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=1,NAND +am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=1,NAND +am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=1,NAND +am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=1,NAND +am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=1,NAND +am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT ti814x_evm arm armv7 ti814x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index f1e9f72..9bab71a 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -487,7 +487,7 @@ static inline void wait_for_idle(void) static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, int dev_addr, int phy_reg) { - unsigned short data; + int data; u32 reg; if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 6fe793d..62925bb 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -277,7 +277,7 @@ int genphy_parse_link(struct phy_device *phydev) /* We're using autonegotiation */ if (mii_reg & BMSR_ANEGCAPABLE) { u32 lpa = 0; - u32 gblpa = 0; + int gblpa = 0; u32 estatus = 0; /* Check for gigabit capability */ @@ -286,6 +286,10 @@ int genphy_parse_link(struct phy_device *phydev) * both PHYs in the link */ gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000); + if (gblpa < 0) { + debug("Could not read MII_STAT1000. Ignoring gigabit capability\n"); + gblpa = 0; + } gblpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000) << 2; } -- cgit v0.10.2 From 317fab2df2b06d44d1f91bd44d421f3ef1013ac9 Mon Sep 17 00:00:00 2001 From: Justin Waters Date: Thu, 11 Jul 2013 09:54:58 -0400 Subject: am335x_evm: Make NAND support modular Give the user the ability to disable NAND support by defining CONFIG_NO_NAND. This will allow custom hardware to easily support this configuration. Signed-off-by: Justin Waters [trini: Make apply on top of other series] Signed-off-by: Tom Rini diff --git a/boards.cfg b/boards.cfg index ffb8a27..e49d6dd 100644 --- a/boards.cfg +++ b/boards.cfg @@ -242,7 +242,7 @@ vexpress_ca15_tc2 arm armv7 vexpress armltd vexpress_ca5x2 arm armv7 vexpress armltd vexpress_ca9x4 arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND -am335x_evm_nor arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR +am335x_evm_nor arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR am335x_evm_norboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=1,NAND diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 3ca35c3..b633128 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -51,6 +51,27 @@ #define CONFIG_CMD_ASKENV #define CONFIG_VERSION_VARIABLE +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandsrcaddr=0x280000\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ + "bootm ${loadaddr}\0" \ + "nandimgsize=0x500000\0" +#else +#define NANDARGS "" +#endif + /* set to negative value for no autoboot */ #define CONFIG_BOOTDELAY 1 #define CONFIG_ENV_VARS_UBOOT_CONFIG @@ -66,19 +87,12 @@ "fdtfile=undefined\0" \ "console=ttyO0,115200n8\0" \ "optargs=\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ "dfu_alt_info_mmc=" DFU_ALT_INFO_MMC "\0" \ "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \ - "dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ "bootpart=0:2\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ - "nandsrcaddr=0x280000\0" \ - "nandimgsize=0x500000\0" \ "rootpath=/export/rootfs\0" \ "nfsopts=nolock\0" \ "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ @@ -89,10 +103,6 @@ "${optargs} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ "spiroot=/dev/mtdblock4 rw\0" \ "spirootfstype=jffs2\0" \ "spisrcaddr=0xe0000\0" \ @@ -121,10 +131,6 @@ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr} - ${fdtaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ - "bootm ${loadaddr}\0" \ "spiboot=echo Booting from spi ...; " \ "run spiargs; " \ "sf probe ${spibusno}:0; " \ @@ -150,7 +156,8 @@ "if test $board_name = A335X_SK; then " \ "setenv fdtfile am335x-evmsk.dtb; fi; " \ "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" + "echo WARNING: Could not determine device tree to use; fi; \0" \ + NANDARGS #endif #define CONFIG_BOOTCOMMAND \ @@ -234,7 +241,6 @@ /* USB Device Firmware Update support */ #define CONFIG_DFU_FUNCTION #define CONFIG_DFU_MMC -#define CONFIG_DFU_NAND #define CONFIG_CMD_DFU #define DFU_ALT_INFO_MMC \ "boot part 0 1;" \ @@ -248,6 +254,8 @@ "spl-os-image fat 0 1;" \ "u-boot.img fat 0 1;" \ "uEnv.txt fat 0 1" +#ifdef CONFIG_NAND +#define CONFIG_DFU_NAND #define DFU_ALT_INFO_NAND \ "SPL part 0 1;" \ "SPL.backup1 part 0 2;" \ @@ -257,6 +265,7 @@ "u-boot-spl-os part 0 6;" \ "kernel part 0 8;" \ "rootfs part 0 9" +#endif /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ @@ -344,9 +353,11 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ /* nand */ +#ifdef CONFIG_NAND #define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif /* spl export command */ #define CONFIG_CMD_SPL @@ -376,12 +387,13 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT + +#ifdef CONFIG_NAND #define CONFIG_SPL_NAND_AM33XX_BCH #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#endif #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) @@ -403,6 +415,8 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif +#endif /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM @@ -506,7 +520,6 @@ #define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC -#define CONFIG_NAND /* NAND support */ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND -- cgit v0.10.2 From 2c7c03bed1a1cb6e85eeb07c6495ac3cd2e97702 Mon Sep 17 00:00:00 2001 From: Justin Waters Date: Thu, 11 Jul 2013 09:54:59 -0400 Subject: am335x_evm: Add command line editing Many modern U-Boot ports enable command line editing and a history buffer. The am335x_evm configuration is fairly comprehensive as it is, so a few extra kb should not be noticable, and it adds a very convenient feature. Signed-off-by: Justin Waters diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index b633128..b1d7f5f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -37,6 +37,9 @@ #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024) +#define CONFIG_AUTO_COMPLETE #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -- cgit v0.10.2 From a3aa70afb72b147a21f0e39d72ceb3f253d58498 Mon Sep 17 00:00:00 2001 From: Justin Waters Date: Thu, 11 Jul 2013 09:55:00 -0400 Subject: am335x_evm: Rework bootcmd to handle two MMC devs The BeagleBone Black can boot from either the MMC card or eMMC chip on board. We should try both interfaces. This modification also allows a graceful fallback if a device exists but boot images are not present on it. Changes for v2: * Fix boot partition - it should always show up as mmcblk0p2 * Fix missing FDT load Signed-off-by: Justin Waters diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index b1d7f5f..049a8e4 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -131,9 +131,23 @@ "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ "loaduimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr} - ${fdtaddr}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run loadfdt;" \ + "run mmcargs; " \ + "bootm ${loadaddr} - ${fdtaddr};" \ + "fi;" \ + "fi;\0" \ "spiboot=echo Booting from spi ...; " \ "run spiargs; " \ "sf probe ${spibusno}:0; " \ @@ -165,23 +179,11 @@ #define CONFIG_BOOTCOMMAND \ "run findfdt; " \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run loadfdt;" \ - "run mmcboot;" \ - "fi;" \ - "else " \ - "run nandboot;" \ - "fi;" \ + "run mmcboot;" \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:2; " \ + "run mmcboot;" \ + "run nandboot;" /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ -- cgit v0.10.2 From 341d2c0e13d8bb177504b7ca16f2e6f555f78d4f Mon Sep 17 00:00:00 2001 From: Justin Waters Date: Thu, 11 Jul 2013 09:55:01 -0400 Subject: Add additional MLO images to .gitignore This rule catches images such as MLO.byteswap Signed-off-by: Justin Waters diff --git a/.gitignore b/.gitignore index 771b860..d1282e7 100644 --- a/.gitignore +++ b/.gitignore @@ -24,7 +24,7 @@ # Top-level generic files # -/MLO +/MLO* /SPL /System.map /u-boot -- cgit v0.10.2 From 8c6ede1fd21d4c132aba31a0f1cef2a478bafe96 Mon Sep 17 00:00:00 2001 From: Justin Waters Date: Thu, 11 Jul 2013 09:55:02 -0400 Subject: am335x_evm: Add support for eMMC environment Some boards, such as the BeagleBone Black, have an eMMC chip intstead of NAND. We can use the eMMC boot partition to store the environment, since it isn't used for anything else. This allows us to have a configurable environment on those boards. Signed-off-by: Justin Waters diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 049a8e4..e32066d 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -502,7 +502,12 @@ "512k(u-boot),128k(u-boot-env1)," \ "128k(u-boot-env2),3464k(kernel)," \ "-(rootfs)" -#endif /* SPI support */ +#elif defined(CONFIG_EMMC_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#endif /* Unsupported features */ #undef CONFIG_USE_IRQ -- cgit v0.10.2 From f881a4df4f34e3902b27003a20b7cf9f15251482 Mon Sep 17 00:00:00 2001 From: Justin Waters Date: Thu, 11 Jul 2013 09:55:03 -0400 Subject: am335x_evm: Add am335x_boneblack variant The BeagleBone Black differs from the other AM335x boards in a few significant ways, so it makes sense to create a custom configuration for it. In particular, it uses eMMC instead of NAND flash. Signed-off-by: Justin Waters diff --git a/boards.cfg b/boards.cfg index e49d6dd..211ed58 100644 --- a/boards.cfg +++ b/boards.cfg @@ -251,6 +251,7 @@ am335x_evm_uart3 arm armv7 am335x ti am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=1,NAND am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=1,NAND am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT +am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT ti814x_evm arm armv7 ti814x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC -- cgit v0.10.2 From 61c1775f16ed122a07168545afbc1a04ece2bc22 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Thu, 11 Jul 2013 13:10:27 -0500 Subject: gpio: tca642x: Add the tca642x gpio expander driver Add the tca642x gpio expander driver Datasheet: http://www.ti.com/product/tca6424a Signed-off-by: Dan Murphy diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index af94bf5..71ddb00 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o COBJS-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o COBJS-$(CONFIG_ADI_GPIO2) += adi_gpio2.o +COBJS-$(CONFIG_TCA642X) += tca642x.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c new file mode 100644 index 0000000..6386835 --- /dev/null +++ b/drivers/gpio/tca642x.c @@ -0,0 +1,333 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * Author: Dan Murphy + * + * Derived work from the pca953x.c driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* tca642x register address definitions */ +struct tca642x_bank_info tca642x_regs[] = { + { .input_reg = 0x00, + .output_reg = 0x04, + .polarity_reg = 0x08, + .configuration_reg = 0x0c }, + { .input_reg = 0x01, + .output_reg = 0x05, + .polarity_reg = 0x09, + .configuration_reg = 0x0d }, + { .input_reg = 0x02, + .output_reg = 0x06, + .polarity_reg = 0x0a, + .configuration_reg = 0x0e }, +}; + +/* + * Modify masked bits in register + */ +static int tca642x_reg_write(uchar chip, uint8_t addr, + uint8_t reg_bit, uint8_t data) +{ + uint8_t valw; + int org_bus_num; + int ret; + + org_bus_num = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM); + + if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) { + printf("Could not read before writing\n"); + ret = -1; + goto error; + } + valw &= ~reg_bit; + valw |= data; + + ret = i2c_write(chip, addr, 1, (u8 *)&valw, 1); + +error: + i2c_set_bus_num(org_bus_num); + return ret; +} + +static int tca642x_reg_read(uchar chip, uint8_t addr, uint8_t *data) +{ + uint8_t valw; + int org_bus_num; + int ret = 0; + + org_bus_num = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM); + if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) { + ret = -1; + goto error; + } + + *data = valw; + +error: + i2c_set_bus_num(org_bus_num); + return ret; +} + +/* + * Set output value of IO pins in 'reg_bit' to corresponding value in 'data' + * 0 = low, 1 = high + */ +int tca642x_set_val(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data) +{ + uint8_t out_reg = tca642x_regs[gpio_bank].output_reg; + + return tca642x_reg_write(chip, out_reg, reg_bit, data); +} + +/* + * Set read polarity of IO pins in 'reg_bit' to corresponding value in 'data' + * 0 = read pin value, 1 = read inverted pin value + */ +int tca642x_set_pol(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data) +{ + uint8_t pol_reg = tca642x_regs[gpio_bank].polarity_reg; + + return tca642x_reg_write(chip, pol_reg, reg_bit, data); +} + +/* + * Set direction of IO pins in 'reg_bit' to corresponding value in 'data' + * 0 = output, 1 = input + */ +int tca642x_set_dir(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data) +{ + uint8_t config_reg = tca642x_regs[gpio_bank].configuration_reg; + + return tca642x_reg_write(chip, config_reg, reg_bit, data); +} + +/* + * Read current logic level of all IO pins + */ +int tca642x_get_val(uchar chip, uint8_t gpio_bank) +{ + uint8_t val; + uint8_t in_reg = tca642x_regs[gpio_bank].input_reg; + + if (tca642x_reg_read(chip, in_reg, &val) < 0) + return -1; + + return (int)val; +} + +/* + * Set the inital register states for the tca642x gpio expander + */ +int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]) +{ + int i, ret; + uint8_t config_reg; + uint8_t polarity_reg; + uint8_t output_reg; + + for (i = 0; i < 3; i++) { + config_reg = tca642x_regs[i].configuration_reg; + ret = tca642x_reg_write(chip, config_reg, 0xff, + init_data[i].configuration_reg); + polarity_reg = tca642x_regs[i].polarity_reg; + ret = tca642x_reg_write(chip, polarity_reg, 0xff, + init_data[i].polarity_reg); + output_reg = tca642x_regs[i].output_reg; + ret = tca642x_reg_write(chip, output_reg, 0xff, + init_data[i].output_reg); + } + + return ret; +} + +#ifdef CONFIG_CMD_TCA642X +/* + * Display tca642x information + */ +static int tca642x_info(uchar chip) +{ + int i, j; + uint8_t data; + + printf("tca642x@ 0x%x (%d pins):\n", chip, 24); + for (i = 0; i < 3; i++) { + printf("Bank %i\n", i); + if (tca642x_reg_read(chip, + tca642x_regs[i].configuration_reg, + &data) < 0) + return -1; + printf("\tConfiguration: "); + for (j = 7; j >= 0; j--) + printf("%c", data & (1 << j) ? 'i' : 'o'); + printf("\n"); + + if (tca642x_reg_read(chip, + tca642x_regs[i].polarity_reg, &data) < 0) + return -1; + printf("\tPolarity: "); + for (j = 7; j >= 0; j--) + printf("%c", data & (1 << j) ? '1' : '0'); + printf("\n"); + + if (tca642x_reg_read(chip, + tca642x_regs[i].input_reg, &data) < 0) + return -1; + printf("\tInput value: "); + for (j = 7; j >= 0; j--) + printf("%c", data & (1 << j) ? '1' : '0'); + printf("\n"); + + if (tca642x_reg_read(chip, + tca642x_regs[i].output_reg, &data) < 0) + return -1; + printf("\tOutput value: "); + for (j = 7; j >= 0; j--) + printf("%c", data & (1 << j) ? '1' : '0'); + printf("\n"); + } + + return 0; +} + +cmd_tbl_t cmd_tca642x[] = { + U_BOOT_CMD_MKENT(device, 3, 0, (void *)TCA642X_CMD_DEVICE, "", ""), + U_BOOT_CMD_MKENT(output, 4, 0, (void *)TCA642X_CMD_OUTPUT, "", ""), + U_BOOT_CMD_MKENT(input, 3, 0, (void *)TCA642X_CMD_INPUT, "", ""), + U_BOOT_CMD_MKENT(invert, 4, 0, (void *)TCA642X_CMD_INVERT, "", ""), + U_BOOT_CMD_MKENT(info, 2, 0, (void *)TCA642X_CMD_INFO, "", ""), +}; + +int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR; + int ret = CMD_RET_USAGE, val; + uint8_t gpio_bank = 0; + uint8_t bank_shift; + ulong ul_arg2 = 0; + ulong ul_arg3 = 0; + cmd_tbl_t *c; + + c = find_cmd_tbl(argv[1], cmd_tca642x, ARRAY_SIZE(cmd_tca642x)); + + /* All commands but "device" require 'maxargs' arguments */ + if (!c || + !((argc == (c->maxargs)) || + (((int)c->cmd == TCA642X_CMD_DEVICE) && + (argc == (c->maxargs - 1))))) { + return CMD_RET_USAGE; + } + + /* arg2 used as chip number or pin number */ + if (argc > 2) + ul_arg2 = simple_strtoul(argv[2], NULL, 10); + + /* arg3 used as pin or invert value */ + if (argc > 3) { + ul_arg3 = simple_strtoul(argv[3], NULL, 10) & 0x1; + if (ul_arg2 <= 7) { + gpio_bank = 0; + } else if ((ul_arg2 >= 10) && (ul_arg2 <= 17)) { + gpio_bank = 1; + } else if ((ul_arg2 >= 20) && (ul_arg2 <= 27)) { + gpio_bank = 2; + } else { + printf("Requested pin is not available\n"); + ret = CMD_RET_FAILURE; + goto error; + } + } + + switch ((int)c->cmd) { + case TCA642X_CMD_INFO: + ret = tca642x_info(chip); + if (ret) + ret = CMD_RET_FAILURE; + break; + + case TCA642X_CMD_DEVICE: + if (argc == 3) + chip = (uint8_t)ul_arg2; + printf("Current device address: 0x%x\n", chip); + ret = CMD_RET_SUCCESS; + break; + + case TCA642X_CMD_INPUT: + bank_shift = ul_arg2 - (gpio_bank * 10); + ret = tca642x_set_dir(chip, gpio_bank, (1 << bank_shift), + TCA642X_DIR_IN << bank_shift); + val = (tca642x_get_val(chip, gpio_bank) & + (1 << bank_shift)) != 0; + + if (ret) + ret = CMD_RET_FAILURE; + else + printf("chip 0x%02x, pin 0x%lx = %d\n", chip, + ul_arg2, val); + break; + + case TCA642X_CMD_OUTPUT: + bank_shift = ul_arg2 - (gpio_bank * 10); + ret = tca642x_set_dir(chip, gpio_bank, (1 << bank_shift), + (TCA642X_DIR_OUT << bank_shift)); + if (!ret) + ret = tca642x_set_val(chip, + gpio_bank, (1 << bank_shift), + (ul_arg3 << bank_shift)); + if (ret) + ret = CMD_RET_FAILURE; + break; + + case TCA642X_CMD_INVERT: + bank_shift = ul_arg2 - (gpio_bank * 10); + ret = tca642x_set_pol(chip, gpio_bank, (1 << bank_shift), + (ul_arg3 << bank_shift)); + if (ret) + ret = CMD_RET_FAILURE; + break; + } +error: + if (ret == CMD_RET_FAILURE) + eprintf("Error talking to chip at 0x%x\n", chip); + + return ret; +} + +U_BOOT_CMD( + tca642x, 5, 1, do_tca642x, + "tca642x gpio access", + "device [dev]\n" + " - show or set current device address\n" + "tca642x info\n" + " - display info for current chip\n" + "tca642x output pin 0|1\n" + " - set pin as output and drive low or high\n" + "tca642x invert pin 0|1\n" + " - disable/enable polarity inversion for reads\n" + "tca642x input pin\n" + " - set pin as input and read value" +); + +#endif /* CONFIG_CMD_TCA642X */ diff --git a/include/tca642x.h b/include/tca642x.h new file mode 100644 index 0000000..bda86c1 --- /dev/null +++ b/include/tca642x.h @@ -0,0 +1,69 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * Author: Dan Murphy + * + * Derived work from the pca953x.c driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TCA642X_H_ +#define __TCA642X_H_ + +#ifdef CONFIG_CMD_TCA642X +enum { + TCA642X_CMD_INFO, + TCA642X_CMD_DEVICE, + TCA642X_CMD_OUTPUT, + TCA642X_CMD_INPUT, + TCA642X_CMD_INVERT, +}; +#endif + +#define TCA642X_OUT_LOW 0 +#define TCA642X_OUT_HIGH 1 +#define TCA642X_POL_NORMAL 0 +#define TCA642X_POL_INVERT 1 +#define TCA642X_DIR_OUT 0 +#define TCA642X_DIR_IN 1 + +/* Default to an address that hopefully won't corrupt other i2c devices */ +#ifndef CONFIG_SYS_I2C_TCA642X_ADDR +#define CONFIG_SYS_I2C_TCA642X_ADDR (~0) +#endif + +/* Default to an address that hopefully won't corrupt other i2c devices */ +#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM +#define CONFIG_SYS_I2C_TCA642X_BUS_NUM (0) +#endif + +struct tca642x_bank_info { + uint8_t input_reg; + uint8_t output_reg; + uint8_t polarity_reg; + uint8_t configuration_reg; +}; + +int tca642x_set_val(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data); +int tca642x_set_pol(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data); +int tca642x_set_dir(uchar chip, uint8_t gpio_bank, + uint8_t reg_bit, uint8_t data); +int tca642x_get_val(uchar chip, uint8_t gpio_bank); +int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]); + +#endif /* __TCA642X_H_ */ -- cgit v0.10.2 From fdce7b633a1de24456226b18527cc7900c34282a Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Thu, 11 Jul 2013 13:10:28 -0500 Subject: gpio: omap5-uevm: Configure the tca6424 gpio expander Configure the tca6424 gpio expander This allows use of the debug and tri color LEDs. Signed-off-by: Dan Murphy diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index ea83e6c..2c00648 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "mux_data.h" @@ -20,6 +21,25 @@ const struct omap_sysinfo sysinfo = { }; /** + * @brief tca642x_init - uEVM default values for the GPIO expander + * input reg, output reg, polarity reg, configuration reg + */ +struct tca642x_bank_info tca642x_init[] = { + { .input_reg = 0x00, + .output_reg = 0x04, + .polarity_reg = 0x00, + .configuration_reg = 0x80 }, + { .input_reg = 0x00, + .output_reg = 0x00, + .polarity_reg = 0x00, + .configuration_reg = 0xff }, + { .input_reg = 0x00, + .output_reg = 0x00, + .polarity_reg = 0x00, + .configuration_reg = 0x40 }, +}; + +/** * @brief board_init * * @return 0 @@ -30,6 +50,8 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ + tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init); + return 0; } diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h index 36b723e..612c13e 100644 --- a/board/ti/omap5_uevm/mux_data.h +++ b/board/ti/omap5_uevm/mux_data.h @@ -40,6 +40,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ + {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ + {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ }; diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 9c045d3..47568e9 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -37,6 +37,11 @@ #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART +#define CONFIG_TCA642X +#define CONFIG_CMD_TCA642X +#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 +#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 + #define CONFIG_SYS_PROMPT "OMAP5432 uEVM # " #define CONSOLEDEV "ttyO2" -- cgit v0.10.2 From 94d77fb656d49f2b0efe2de5605a52c5145d2c3b Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 10:48:52 +0530 Subject: ARM: AM33xx: Cleanup dplls data Locking sequence for all the dplls is same. In the current code same sequence is done repeatedly for each dpll. Instead have a generic function for locking dplls and pass dpll data to that function. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla Tested-by: Heiko Schocher Acked-by: Heiko Schocher diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index dbd1ec3..7fd21af 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -10,6 +10,7 @@ LIB = $(obj)lib$(SOC).o COBJS-$(CONFIG_AM33XX) += clock_am33xx.o COBJS-$(CONFIG_TI814X) += clock_ti814x.o +COBJS-$(CONFIG_AM33XX) += clock.o COBJS += sys_info.o COBJS += mem.o COBJS += ddr.o diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c new file mode 100644 index 0000000..15f4a2c --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -0,0 +1,111 @@ +/* + * clock.c + * + * Clock initialization for AM33XX boards. + * Derived from OMAP4 boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +static void setup_post_dividers(const struct dpll_regs *dpll_regs, + const struct dpll_params *params) +{ + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, dpll_regs->cm_div_m3_dpll); + if (params->m4 >= 0) + writel(params->m4, dpll_regs->cm_div_m4_dpll); + if (params->m5 >= 0) + writel(params->m5, dpll_regs->cm_div_m5_dpll); + if (params->m6 >= 0) + writel(params->m6, dpll_regs->cm_div_m6_dpll); +} + +static inline void do_lock_dpll(const struct dpll_regs *dpll_regs) +{ + clrsetbits_le32(dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_lock(const struct dpll_regs *dpll_regs) +{ + if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, + (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("DPLL locking failed for 0x%x\n", + dpll_regs->cm_clkmode_dpll); + hang(); + } +} + +static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs) +{ + clrsetbits_le32(dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_bypass(const struct dpll_regs *dpll_regs) +{ + if (!wait_on_value(ST_DPLL_CLK_MASK, 0, + (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("Bypassing DPLL failed 0x%x\n", + dpll_regs->cm_clkmode_dpll); + } +} + +static void bypass_dpll(const struct dpll_regs *dpll_regs) +{ + do_bypass_dpll(dpll_regs); + wait_for_bypass(dpll_regs); +} + +void do_setup_dpll(const struct dpll_regs *dpll_regs, + const struct dpll_params *params) +{ + u32 temp; + + if (!params) + return; + + temp = readl(dpll_regs->cm_clksel_dpll); + + bypass_dpll(dpll_regs); + + /* Set M & N */ + temp &= ~CM_CLKSEL_DPLL_M_MASK; + temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; + + temp &= ~CM_CLKSEL_DPLL_N_MASK; + temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; + + writel(temp, dpll_regs->cm_clksel_dpll); + + setup_post_dividers(dpll_regs, params); + + /* Wait till the DPLL locks */ + do_lock_dpll(dpll_regs); + wait_for_lock(dpll_regs); +} + +void setup_dplls(void) +{ + const struct dpll_params *params; + do_setup_dpll(&dpll_core_regs, &dpll_core); + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu); + do_setup_dpll(&dpll_per_regs, &dpll_per); + writel(0x300, &cmwkup->clkdcoldodpllper); + + params = get_dpll_ddr_params(); + do_setup_dpll(&dpll_ddr_regs, params); +} diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index fb3fb43..d5d47ad 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -18,56 +18,51 @@ #define PRCM_FORCE_WAKEUP 0x2 #define PRCM_FUNCTL 0x0 -#define PRCM_EMIF_CLK_ACTIVITY BIT(2) -#define PRCM_L3_GCLK_ACTIVITY BIT(4) - -#define PLL_BYPASS_MODE 0x4 -#define ST_MN_BYPASS 0x00000100 -#define ST_DPLL_CLK 0x00000001 -#define CLK_SEL_MASK 0x7ffff -#define CLK_DIV_MASK 0x1f -#define CLK_DIV2_MASK 0x7f -#define CLK_SEL_SHIFT 0x8 -#define CLK_MODE_SEL 0x7 -#define CLK_MODE_MASK 0xfffffff8 -#define CLK_DIV_SEL 0xFFFFFFE0 #define CPGMAC0_IDLE 0x30000 -#define DPLL_CLKDCOLDO_GATE_CTRL 0x300 - #define OSC (V_OSCK/1000000) -#define MPUPLL_M CONFIG_SYS_MPUCLK -#define MPUPLL_N (OSC-1) -#define MPUPLL_M2 1 - -/* Core PLL Fdll = 1 GHZ, */ -#define COREPLL_M 1000 -#define COREPLL_N (OSC-1) - -#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ -#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ -#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */ - -/* - * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll - * frequency needs to be set to 960 MHZ. Hence, - * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below - */ -#define PERPLL_M 960 -#define PERPLL_N (OSC-1) -#define PERPLL_M2 5 - -/* DDR Freq is 266 MHZ for now */ -/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ -#define DDRPLL_M 266 -#define DDRPLL_N (OSC-1) -#define DDRPLL_M2 1 - const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC; +const struct dpll_regs dpll_mpu_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x88, + .cm_idlest_dpll = CM_WKUP + 0x20, + .cm_clksel_dpll = CM_WKUP + 0x2C, + .cm_div_m2_dpll = CM_WKUP + 0xA8, +}; + +const struct dpll_regs dpll_core_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x90, + .cm_idlest_dpll = CM_WKUP + 0x5C, + .cm_clksel_dpll = CM_WKUP + 0x68, + .cm_div_m4_dpll = CM_WKUP + 0x80, + .cm_div_m5_dpll = CM_WKUP + 0x84, + .cm_div_m6_dpll = CM_WKUP + 0xD8, +}; + +const struct dpll_regs dpll_per_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x8C, + .cm_idlest_dpll = CM_WKUP + 0x70, + .cm_clksel_dpll = CM_WKUP + 0x9C, + .cm_div_m2_dpll = CM_WKUP + 0xAC, +}; + +const struct dpll_regs dpll_ddr_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x94, + .cm_idlest_dpll = CM_WKUP + 0x34, + .cm_clksel_dpll = CM_WKUP + 0x40, + .cm_div_m2_dpll = CM_WKUP + 0xA0, +}; + +const struct dpll_params dpll_mpu = { + CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_core = { + 1000, OSC-1, -1, -1, 10, 8, 4}; +const struct dpll_params dpll_per = { + 960, OSC-1, 5, -1, -1, -1, -1}; + static void enable_interface_clocks(void) { /* Enable all the Interconnect Modules */ @@ -238,142 +233,6 @@ static void enable_per_clocks(void) ; } -void mpu_pll_config_val(int mpull_m) -{ - u32 clkmode, clksel, div_m2; - - clkmode = readl(&cmwkup->clkmoddpllmpu); - clksel = readl(&cmwkup->clkseldpllmpu); - div_m2 = readl(&cmwkup->divm2dpllmpu); - - /* Set the PLL to bypass Mode */ - writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu); - while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS) - ; - - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N); - writel(clksel, &cmwkup->clkseldpllmpu); - - div_m2 = div_m2 & ~CLK_DIV_MASK; - div_m2 = div_m2 | MPUPLL_M2; - writel(div_m2, &cmwkup->divm2dpllmpu); - - clkmode = clkmode | CLK_MODE_SEL; - writel(clkmode, &cmwkup->clkmoddpllmpu); - - while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK) - ; -} - -static void mpu_pll_config(void) -{ - mpu_pll_config_val(CONFIG_SYS_MPUCLK); -} - -static void core_pll_config(void) -{ - u32 clkmode, clksel, div_m4, div_m5, div_m6; - - clkmode = readl(&cmwkup->clkmoddpllcore); - clksel = readl(&cmwkup->clkseldpllcore); - div_m4 = readl(&cmwkup->divm4dpllcore); - div_m5 = readl(&cmwkup->divm5dpllcore); - div_m6 = readl(&cmwkup->divm6dpllcore); - - /* Set the PLL to bypass Mode */ - writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore); - - while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS) - ; - - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N); - writel(clksel, &cmwkup->clkseldpllcore); - - div_m4 = div_m4 & ~CLK_DIV_MASK; - div_m4 = div_m4 | COREPLL_M4; - writel(div_m4, &cmwkup->divm4dpllcore); - - div_m5 = div_m5 & ~CLK_DIV_MASK; - div_m5 = div_m5 | COREPLL_M5; - writel(div_m5, &cmwkup->divm5dpllcore); - - div_m6 = div_m6 & ~CLK_DIV_MASK; - div_m6 = div_m6 | COREPLL_M6; - writel(div_m6, &cmwkup->divm6dpllcore); - - clkmode = clkmode | CLK_MODE_SEL; - writel(clkmode, &cmwkup->clkmoddpllcore); - - while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK) - ; -} - -static void per_pll_config(void) -{ - u32 clkmode, clksel, div_m2; - - clkmode = readl(&cmwkup->clkmoddpllper); - clksel = readl(&cmwkup->clkseldpllper); - div_m2 = readl(&cmwkup->divm2dpllper); - - /* Set the PLL to bypass Mode */ - writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper); - - while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS) - ; - - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N); - writel(clksel, &cmwkup->clkseldpllper); - - div_m2 = div_m2 & ~CLK_DIV2_MASK; - div_m2 = div_m2 | PERPLL_M2; - writel(div_m2, &cmwkup->divm2dpllper); - - clkmode = clkmode | CLK_MODE_SEL; - writel(clkmode, &cmwkup->clkmoddpllper); - - while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK) - ; - - writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper); -} - -void ddr_pll_config(unsigned int ddrpll_m) -{ - u32 clkmode, clksel, div_m2; - - clkmode = readl(&cmwkup->clkmoddpllddr); - clksel = readl(&cmwkup->clkseldpllddr); - div_m2 = readl(&cmwkup->divm2dpllddr); - - /* Set the PLL to bypass Mode */ - clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE; - writel(clkmode, &cmwkup->clkmoddpllddr); - - /* Wait till bypass mode is enabled */ - while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS) - != ST_MN_BYPASS) - ; - - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N); - writel(clksel, &cmwkup->clkseldpllddr); - - div_m2 = div_m2 & CLK_DIV_SEL; - div_m2 = div_m2 | DDRPLL_M2; - writel(div_m2, &cmwkup->divm2dpllddr); - - clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL; - writel(clkmode, &cmwkup->clkmoddpllddr); - - /* Wait till dpll is locked */ - while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK) - ; -} - void enable_emif_clocks(void) { /* Enable the EMIF_FW Functional clock */ @@ -390,10 +249,7 @@ void enable_emif_clocks(void) */ void pll_init() { - mpu_pll_config(); - core_pll_config(); - per_pll_config(); - + setup_dplls(); /* Enable the required interconnect clocks */ enable_interface_clocks(); diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 55dc321..15c4734 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -79,6 +79,10 @@ static void config_vtp(int nr) ; } +void __weak ddr_pll_config(unsigned int ddrpll_m) +{ +} + void config_ddr(unsigned int pll, unsigned int ioctrl, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 44c1e5d..703b80e 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -13,4 +13,74 @@ #include +#define LDELAY 1000000 + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F + +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 m4; + s8 m5; + s8 m6; +}; + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_dpll; + u32 cm_div_m5_dpll; + u32 cm_div_m6_dpll; +}; + +extern const struct dpll_regs dpll_mpu_regs; +extern const struct dpll_regs dpll_core_regs; +extern const struct dpll_regs dpll_per_regs; +extern const struct dpll_regs dpll_ddr_regs; +extern const struct dpll_params dpll_mpu; +extern const struct dpll_params dpll_core; +extern const struct dpll_params dpll_per; +extern const struct dpll_params dpll_ddr; + +extern const struct cm_wkuppll *cmwkup; + +void setup_dplls(void); +const struct dpll_params *get_dpll_ddr_params(void); +void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); + #endif diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 18d7d99..683ba8e 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -146,6 +146,8 @@ void set_sdram_timings(const struct emif_regs *regs, int nr); */ void config_ddr_phy(const struct emif_regs *regs, int nr); +void ddr_pll_config(unsigned int ddrpll_m); + struct ddr_cmd_regs { unsigned int resv0[7]; unsigned int cm0csratio; /* offset 0x01C */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 1424f90..dbcede0 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -37,4 +37,5 @@ void omap_nand_switch_ecc(uint32_t, uint32_t); void rtc32k_enable(void); void uart_soft_reset(void); +u32 wait_on_value(u32, u32, void *, u32); #endif diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index c0f0c0d..034a8aa 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -66,6 +66,16 @@ static struct emif_regs ddr3_emif_reg_data = { .zq_config = K4B2G1646EBIH9_ZQ_CFG, .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY, }; + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 303, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + #endif /* diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 6291d03..17a98ff 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -44,6 +44,15 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* DDR RAM defines */ #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J256M8HX15E_RD_DQS, .datawdsratio0 = MT41J256M8HX15E_WR_DQS, diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 728afc2..2be2297 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -242,6 +242,33 @@ int spl_start_uboot(void) } #endif +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_evm_sk = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_bone_black = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + struct am335x_baseboard_id header; + + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + if (board_is_evm_sk(&header)) + return &dpll_ddr_evm_sk; + else if (board_is_bone_lt(&header)) + return &dpll_ddr_bone_black; + else if (board_is_evm_15_or_later(&header)) + return &dpll_ddr_evm_sk; + else + return &dpll_ddr; +} + #endif /* -- cgit v0.10.2 From 95cb69faeb45f6396a1336bff201a50ea1677d85 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 10:48:53 +0530 Subject: ARM: AM33xx: Cleanup clocks layer Cleaning up the clocks layer. This helps in addition of new Soc with minimal changes. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla Tested-by: Heiko Schocher Acked-by: Heiko Schocher diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index f1623db..64a3af7 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -56,12 +56,6 @@ int cpu_mmc_init(bd_t *bis) } #endif -void setup_clocks_for_console(void) -{ - /* Not yet implemented */ - return; -} - /* AM33XX has two MUSB controllers which can be host or gadget */ #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \ (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 15f4a2c..8e5f3c6 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -98,7 +98,7 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs, wait_for_lock(dpll_regs); } -void setup_dplls(void) +static void setup_dplls(void) { const struct dpll_params *params; do_setup_dpll(&dpll_core_regs, &dpll_core); @@ -109,3 +109,63 @@ void setup_dplls(void) params = get_dpll_ddr_params(); do_setup_dpll(&dpll_ddr_regs, params); } + +static inline void wait_for_clk_enable(u32 *clkctrl_addr) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + u32 bound = LDELAY; + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + clkctrl = readl(clkctrl_addr); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + if (--bound == 0) { + printf("Clock enable failed for 0x%p idlest 0x%x\n", + clkctrl_addr, clkctrl); + return; + } + } +} + +static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, + u32 wait_for_enable) +{ + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, + enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); + debug("Enable clock module - %p\n", clkctrl_addr); + if (wait_for_enable) + wait_for_clk_enable(clkctrl_addr); +} + +static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) +{ + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, + enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); + debug("Enable clock domain - %p\n", clkctrl_reg); +} + +void do_enable_clocks(u32 *const *clk_domains, + u32 *const *clk_modules_explicit_en, u8 wait_for_enable) +{ + u32 i, max = 100; + + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clk_domains[i]; i++) { + enable_clock_domain(clk_domains[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { + enable_clock_module(clk_modules_explicit_en[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; +} + +void prcm_init() +{ + enable_basic_clocks(); + setup_dplls(); +} diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index d5d47ad..e5f287b 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -14,17 +14,12 @@ #include #include -#define PRCM_MOD_EN 0x2 -#define PRCM_FORCE_WAKEUP 0x2 -#define PRCM_FUNCTL 0x0 - -#define CPGMAC0_IDLE 0x30000 #define OSC (V_OSCK/1000000) -const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; -const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; -const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; -const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC; +struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; +struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; +struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC; const struct dpll_regs dpll_mpu_regs = { .cm_clkmode_dpll = CM_WKUP + 0x88, @@ -63,199 +58,85 @@ const struct dpll_params dpll_core = { const struct dpll_params dpll_per = { 960, OSC-1, 5, -1, -1, -1, -1}; -static void enable_interface_clocks(void) -{ - /* Enable all the Interconnect Modules */ - writel(PRCM_MOD_EN, &cmper->l3clkctrl); - while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4lsclkctrl); - while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4fwclkctrl); - while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl); - while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l3instrclkctrl); - while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4hsclkctrl); - while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl); - while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN) - ; -} - -/* - * Force power domain wake up transition - * Ensure that the corresponding interface clock is active before - * using the peripheral - */ -static void power_domain_wkup_transition(void) +void setup_clocks_for_console(void) { - writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl); + clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + clrsetbits_le32(&cmwkup->wkup_uart0ctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart1clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart2clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart3clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart4clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart5clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); } -/* - * Enable the peripheral clock for required peripherals - */ -static void enable_per_clocks(void) +void enable_basic_clocks(void) { - /* Enable the control module though RBL would have done it*/ - writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl); - while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN) - ; - - /* Enable the module clock */ - writel(PRCM_MOD_EN, &cmper->timer2clkctrl); - while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN) - ; + u32 *const clk_domains[] = { + &cmper->l3clkstctrl, + &cmper->l4fwclkstctrl, + &cmper->l3sclkstctrl, + &cmper->l4lsclkstctrl, + &cmwkup->wkclkstctrl, + &cmper->emiffwclkctrl, + &cmrtc->clkstctrl, + 0 + }; + + u32 *const clk_modules_explicit_en[] = { + &cmper->l3clkctrl, + &cmper->l4lsclkctrl, + &cmper->l4fwclkctrl, + &cmwkup->wkl4wkclkctrl, + &cmper->l3instrclkctrl, + &cmper->l4hsclkctrl, + &cmwkup->wkgpio0clkctrl, + &cmwkup->wkctrlclkctrl, + &cmper->timer2clkctrl, + &cmper->gpmcclkctrl, + &cmper->elmclkctrl, + &cmper->mmc0clkctrl, + &cmper->mmc1clkctrl, + &cmwkup->wkup_i2c0ctrl, + &cmper->gpio1clkctrl, + &cmper->gpio2clkctrl, + &cmper->gpio3clkctrl, + &cmper->i2c1clkctrl, + &cmper->cpgmac0clkctrl, + &cmper->spi0clkctrl, + &cmrtc->rtcclkctrl, + &cmper->usb0clkctrl, + &cmper->emiffwclkctrl, + &cmper->emifclkctrl, + 0 + }; + + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); /* Select the Master osc 24 MHZ as Timer2 clock source */ writel(0x1, &cmdpll->clktimer2clk); - - /* UART0 */ - writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl); - while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN) - ; - - /* UART1 */ -#ifdef CONFIG_SERIAL2 - writel(PRCM_MOD_EN, &cmper->uart1clkctrl); - while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL2 */ - - /* UART2 */ -#ifdef CONFIG_SERIAL3 - writel(PRCM_MOD_EN, &cmper->uart2clkctrl); - while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL3 */ - - /* UART3 */ -#ifdef CONFIG_SERIAL4 - writel(PRCM_MOD_EN, &cmper->uart3clkctrl); - while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL4 */ - - /* UART4 */ -#ifdef CONFIG_SERIAL5 - writel(PRCM_MOD_EN, &cmper->uart4clkctrl); - while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL5 */ - - /* UART5 */ -#ifdef CONFIG_SERIAL6 - writel(PRCM_MOD_EN, &cmper->uart5clkctrl); - while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL6 */ - - /* GPMC */ - writel(PRCM_MOD_EN, &cmper->gpmcclkctrl); - while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN) - ; - - /* ELM */ - writel(PRCM_MOD_EN, &cmper->elmclkctrl); - while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN) - ; - - /* MMC0*/ - writel(PRCM_MOD_EN, &cmper->mmc0clkctrl); - while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN) - ; - - /* MMC1 */ - writel(PRCM_MOD_EN, &cmper->mmc1clkctrl); - while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN) - ; - - /* i2c0 */ - writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl); - while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN) - ; - - /* gpio1 module */ - writel(PRCM_MOD_EN, &cmper->gpio1clkctrl); - while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN) - ; - - /* gpio2 module */ - writel(PRCM_MOD_EN, &cmper->gpio2clkctrl); - while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN) - ; - - /* gpio3 module */ - writel(PRCM_MOD_EN, &cmper->gpio3clkctrl); - while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN) - ; - - /* i2c1 */ - writel(PRCM_MOD_EN, &cmper->i2c1clkctrl); - while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN) - ; - - /* Ethernet */ - writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl); - while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL) - ; - - /* spi0 */ - writel(PRCM_MOD_EN, &cmper->spi0clkctrl); - while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN) - ; - - /* RTC */ - writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl); - while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN) - ; - - /* MUSB */ - writel(PRCM_MOD_EN, &cmper->usb0clkctrl); - while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN) - ; -} - -void enable_emif_clocks(void) -{ - /* Enable the EMIF_FW Functional clock */ - writel(PRCM_MOD_EN, &cmper->emiffwclkctrl); - /* Enable EMIF0 Clock */ - writel(PRCM_MOD_EN, &cmper->emifclkctrl); - /* Poll if module is functional */ - while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN) - ; -} - -/* - * Configure the PLL/PRCM for necessary peripherals - */ -void pll_init() -{ - setup_dplls(); - /* Enable the required interconnect clocks */ - enable_interface_clocks(); - - /* Power domain wake up transition */ - power_domain_wkup_transition(); - - /* Enable the required peripherals */ - enable_per_clocks(); } diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index 658772b..965e875 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -264,11 +264,6 @@ const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE; */ static void enable_per_clocks(void) { - /* UART0 */ - writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); - while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) - ; - /* HSMMC1 */ writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) @@ -455,8 +450,6 @@ void sata_pll_config(void) ; } -void enable_emif_clocks(void) {}; - void enable_dmm_clocks(void) { writel(PRCM_MOD_EN, &cmdef->fwclkctrl); @@ -477,13 +470,19 @@ void enable_dmm_clocks(void) ; } +void setup_clocks_for_console(void) +{ + unlock_pll_control_mmr(); + /* UART0 */ + writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); + while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) + ; +} /* * Configure the PLL/PRCM for necessary peripherals */ -void pll_init() +void prcm_init(void) { - unlock_pll_control_mmr(); - /* Enable the control module */ writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 15c4734..21cefd4 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -87,7 +87,6 @@ void config_ddr(unsigned int pll, unsigned int ioctrl, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) { - enable_emif_clocks(); ddr_pll_config(pll); config_vtp(nr); config_cmd_ctrl(ctrl, nr); diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 703b80e..0d4b9ae 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -15,6 +15,28 @@ #define LDELAY 1000000 +/*CM___CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 + +/* CM___CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) @@ -77,10 +99,12 @@ extern const struct dpll_params dpll_core; extern const struct dpll_params dpll_per; extern const struct dpll_params dpll_ddr; -extern const struct cm_wkuppll *cmwkup; +extern struct cm_wkuppll *const cmwkup; -void setup_dplls(void); const struct dpll_params *get_dpll_ddr_params(void); void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); +void prcm_init(void); +void enable_basic_clocks(void); +void do_enable_clocks(u32 *const *, u32 *const *, u8); #endif diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 683ba8e..18d7d99 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -146,8 +146,6 @@ void set_sdram_timings(const struct emif_regs *regs, int nr); */ void config_ddr_phy(const struct emif_regs *regs, int nr); -void ddr_pll_config(unsigned int ddrpll_m); - struct ddr_cmd_regs { unsigned int resv0[7]; unsigned int cm0csratio; /* offset 0x01C */ diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 034a8aa..a065a74 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -103,11 +103,7 @@ void s_init(void) ; #ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); + setup_clocks_for_console(); enable_uart0_pin_mux(); @@ -116,6 +112,11 @@ void s_init(void) preloader_console_init(); + prcm_init(); + + /* Enable RTC32K clock */ + rtc32k_enable(); + /* Configure board pin mux */ enable_board_pin_mux(); diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 2be2297..a6edc2d 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -317,10 +317,7 @@ void s_init(void) #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); + setup_clocks_for_console(); #ifdef CONFIG_SERIAL1 enable_uart0_pin_mux(); @@ -354,12 +351,14 @@ void s_init(void) preloader_console_init(); #endif - /* Initalize the board header */ - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + prcm_init(); + if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); + /* Enable RTC32K clock */ + rtc32k_enable(); + enable_board_pin_mux(&header); if (board_is_evm_sk(&header)) { /* diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index c469645..bd708bb 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -125,11 +125,7 @@ void s_init(void) /* Enable timer */ timer_init(); - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); + setup_clocks_for_console(); /* Set UART pins */ enable_uart0_pin_mux(); @@ -147,6 +143,12 @@ void s_init(void) preloader_console_init(); + /* Setup the PLLs and the clocks for the peripherals */ + prcm_init(); + + /* Enable RTC32K clock */ + rtc32k_enable(); + config_dmm(&evm_lisa_map_regs); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, -- cgit v0.10.2 From 0660481a59cccd324fc2dfcad9734318a8c25a90 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 30 Jul 2013 10:48:54 +0530 Subject: ARM: AM33xx: Move s_init to a common place s_init has the same outline for all the AM33xx based board. So making it generic. This also helps in addition of new Soc with minimal changes. Signed-off-by: Lokesh Vutla Signed-off-by: Heiko Schocher Signed-off-by: Tom Rini Tested-by: Heiko Schocher Acked-by: Heiko Schocher diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 64a3af7..2ea3d69 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -137,7 +137,7 @@ int arch_misc_init(void) } #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) -void rtc32k_enable(void) +static void rtc32k_enable(void) { struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; @@ -153,11 +153,7 @@ void rtc32k_enable(void) writel((1 << 3) | (1 << 6), &rtc->osc); } -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - -void uart_soft_reset(void) +static void uart_soft_reset(void) { struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; u32 regval; @@ -174,4 +170,58 @@ void uart_soft_reset(void) regval |= UART_SMART_IDLE_EN; writel(regval, &uart_base->uartsyscfg); } + +static void watchdog_disable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} #endif + +void s_init(void) +{ + /* + * The ROM will only have set up sufficient pinmux to allow for the + * first 4KiB NOR to be read, we must finish doing what we know of + * the NOR mux in this space in order to continue. + */ +#ifdef CONFIG_NOR_BOOT + enable_norboot_pin_mux(); +#endif + /* + * Save the boot parameters passed from romcode. + * We cannot delay the saving further than this, + * to prevent overwrites. + */ +#ifdef CONFIG_SPL_BUILD + save_omap_boot_params(); +#endif +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + watchdog_disable(); + timer_init(); + set_uart_mux_conf(); + setup_clocks_for_console(); + uart_soft_reset(); +#endif +#ifdef CONFIG_NOR_BOOT + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; +#else + gd = &gdata; + preloader_console_init(); +#endif +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + prcm_init(); + set_mux_conf_regs(); + /* Enable RTC32K clock */ + rtc32k_enable(); + sdram_init(); +#endif +} diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index 965e875..93c7f7b 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -277,6 +277,12 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0) ; + + /* RTC clocks */ + writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl); + while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN) + ; } /* diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 80e1899..140379f 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -16,8 +16,10 @@ #define CONFIG_SYS_MPUCLK 550 #endif -extern void pll_init(void); -extern void enable_emif_clocks(void); +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + extern void enable_dmm_clocks(void); #endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index dbcede0..c6070a3 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -35,7 +35,11 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size); void omap_nand_switch_ecc(uint32_t, uint32_t); -void rtc32k_enable(void); -void uart_soft_reset(void); +void set_uart_mux_conf(void); +void set_mux_conf_regs(void); +void sdram_init(void); u32 wait_on_value(u32, u32, void *, u32); +#ifdef CONFIG_NOR_BOOT +void enable_norboot_pin_mux(void); +#endif #endif diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index a065a74..f71aaa0 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -27,8 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - /* MII mode defines */ #define RMII_MODE_ENABLE 0x4D @@ -76,54 +74,22 @@ const struct dpll_params *get_dpll_ddr_params(void) return &dpll_ddr; } -#endif - -/* - * Early system init of muxing and clocks. - */ -void s_init(void) +void set_uart_mux_conf(void) { - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#ifdef CONFIG_SPL_BUILD - setup_clocks_for_console(); - enable_uart0_pin_mux(); +} - uart_soft_reset(); - gd = &gdata; - - preloader_console_init(); - - prcm_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - - /* Configure board pin mux */ +void set_mux_conf_regs(void) +{ enable_board_pin_mux(); +} +void sdram_init(void) +{ config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 17a98ff..f3bad76 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -30,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - /* MII mode defines */ #define MII_MODE_ENABLE 0x0 #define RGMII_MODE_ENABLE 0xA @@ -85,57 +83,27 @@ static struct emif_regs ddr3_emif_reg_data = { .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, }; -#endif -/* - * early system init of muxing and clocks. - */ -void s_init(void) +void set_uart_mux_conf(void) { - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* - * WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - enable_uart0_pin_mux(); - uart_soft_reset(); - - gd = &gdata; - - preloader_console_init(); +} +void set_mux_conf_regs(void) +{ /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); enable_board_pin_mux(); +} +void sdram_init(void) +{ config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index a6edc2d..eac9cc9 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -30,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - /* MII mode defines */ #define MII_MODE_ENABLE 0x0 #define RGMII_MODE_ENABLE 0x3A @@ -269,56 +267,8 @@ const struct dpll_params *get_dpll_ddr_params(void) return &dpll_ddr; } -#endif - -/* - * early system init of muxing and clocks. - */ -void s_init(void) +void set_uart_mux_conf(void) { - __maybe_unused struct am335x_baseboard_id header; - - /* - * The ROM will only have set up sufficient pinmux to allow for the - * first 4KiB NOR to be read, we must finish doing what we know of - * the NOR mux in this space in order to continue. - */ -#ifdef CONFIG_NOR_BOOT - asm("stmfd sp!, {r2 - r4}"); - asm("movw r4, #0x8A4"); - asm("movw r3, #0x44E1"); - asm("orr r4, r4, r3, lsl #16"); - asm("mov r2, #9"); - asm("mov r3, #8"); - asm("gpmc_mux: str r2, [r4], #4"); - asm("subs r3, r3, #1"); - asm("bne gpmc_mux"); - asm("ldmfd sp!, {r2 - r4}"); -#endif - -#ifdef CONFIG_SPL_BUILD - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ - save_omap_boot_params(); -#endif - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) - /* Setup the PLLs and the clocks for the peripherals */ - setup_clocks_for_console(); - #ifdef CONFIG_SERIAL1 enable_uart0_pin_mux(); #endif /* CONFIG_SERIAL1 */ @@ -337,29 +287,25 @@ void s_init(void) #ifdef CONFIG_SERIAL6 enable_uart5_pin_mux(); #endif /* CONFIG_SERIAL6 */ +} - uart_soft_reset(); +void set_mux_conf_regs(void) +{ + __maybe_unused struct am335x_baseboard_id header; -#if defined(CONFIG_NOR_BOOT) - /* We want our console now. */ - gd->baudrate = CONFIG_BAUDRATE; - serial_init(); - gd->have_console = 1; -#else - gd = &gdata; + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); - preloader_console_init(); -#endif + enable_board_pin_mux(&header); +} - prcm_init(); +void sdram_init(void) +{ + __maybe_unused struct am335x_baseboard_id header; if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); - /* Enable RTC32K clock */ - rtc32k_enable(); - - enable_board_pin_mux(&header); if (board_is_evm_sk(&header)) { /* * EVM SK 1.2A and later use gpio0_7 to enable DDR3. @@ -383,8 +329,8 @@ void s_init(void) else config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 5b7ed63..b2bfda5 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -239,6 +239,25 @@ static struct module_pin_mux bone_norcape_pin_mux[] = { }; #endif +#if defined(CONFIG_NOR_BOOT) +static struct module_pin_mux norboot_pin_mux[] = { + {OFFSET(lcd_data1), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data2), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data3), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data4), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data5), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data6), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data7), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data8), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data9), MODE(1) | PULLUDDIS}, + {-1}, +}; + +void enable_norboot_pin_mux(void) +{ + configure_module_pin_mux(norboot_pin_mux); +} +#endif void enable_uart0_pin_mux(void) { diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index bd708bb..31ddc68 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -27,30 +27,10 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SPL_BUILD -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -#endif - static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* UART Defines */ #ifdef CONFIG_SPL_BUILD -static void uart_enable(void) -{ - /* UART softreset */ - uart_soft_reset(); -} - -static void wdt_disable(void) -{ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; -} - static const struct cmd_control evm_ddr2_cctrl_data = { .cmd0csratio = 0x80, .cmd0dldiff = 0x04, @@ -100,63 +80,32 @@ static const struct ddr_data evm_ddr2_data = { .datauserank0delay = 1, .datadldiff0 = 0x4, }; -#endif -/* - * early system init of muxing and clocks. - */ -void s_init(void) +void set_uart_mux_conf(void) { -#ifdef CONFIG_SPL_BUILD - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - wdt_disable(); - - /* Enable timer */ - timer_init(); - - setup_clocks_for_console(); - /* Set UART pins */ enable_uart0_pin_mux(); +} +void set_mux_conf_regs(void) +{ /* Set MMC pins */ enable_mmc1_pin_mux(); /* Set Ethernet pins */ enable_enet_pin_mux(); +} - /* Enable UART */ - uart_enable(); - - gd = &gdata; - - preloader_console_init(); - - /* Setup the PLLs and the clocks for the peripherals */ - prcm_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - +void sdram_init(void) +{ config_dmm(&evm_lisa_map_regs); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif0_regs, 0); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif1_regs, 1); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. -- cgit v0.10.2 From 32f420b8ecffee33af01ee452fa1238fa91e399f Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 10:48:55 +0530 Subject: musb: Disable extra prints There are many musb prints in SPL and U-Boot log. These prints are required only during musb debug. So replacing printk with pr_debug in musb_core. Signed-off-by: Lokesh Vutla Tested-by: Heiko Schocher Acked-by: Heiko Schocher diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c index da93571..36681b6 100644 --- a/drivers/usb/musb-new/musb_core.c +++ b/drivers/usb/musb-new/musb_core.c @@ -1311,9 +1311,7 @@ static int __devinit ep_config_from_table(struct musb *musb) break; } - printk(KERN_DEBUG "%s: setup fifo_mode %d\n", - musb_driver_name, fifo_mode); - + pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); done: offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); @@ -1341,10 +1339,9 @@ done: musb->nr_endpoints = max(epn, musb->nr_endpoints); } - printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", - musb_driver_name, - n + 1, musb->config->num_eps * 2 - 1, - offset, (1 << (musb->config->ram_bits + 2))); + pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1, + musb->config->num_eps * 2 - 1, offset, + (1 << (musb->config->ram_bits + 2))); if (!musb->bulk_ep) { pr_debug("%s: missing bulk\n", musb_driver_name); @@ -1447,8 +1444,7 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb) if (reg & MUSB_CONFIGDATA_SOFTCONE) strcat(aInfo, ", SoftConn"); - printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", - musb_driver_name, reg, aInfo); + pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); aDate[0] = 0; if (MUSB_CONTROLLER_MHDRC == musb_type) { @@ -1469,8 +1465,8 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb) snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), MUSB_HWVERS_MINOR(musb->hwvers), (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); - printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", - musb_driver_name, type, aRevision, aDate); + pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type, + aRevision, aDate); /* configure ep0 */ musb_configure_ep0(musb); @@ -2122,7 +2118,7 @@ musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev, pm_runtime_put(musb->controller); - dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", + pr_debug("USB %s mode controller at %p using %s, IRQ %d\n", ({char *s; switch (musb->board_mode) { case MUSB_HOST: s = "Host"; break; -- cgit v0.10.2 From fbf2728da300a96b2e2a6ba6b266bc80c8c21160 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 11:36:27 +0530 Subject: ARM: AM43xx: Add Board files Add board specific information for AM43xx. Signed-off-by: Lokesh Vutla diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile new file mode 100644 index 0000000..4a1bb7c --- /dev/null +++ b/board/ti/am43xx/Makefile @@ -0,0 +1,38 @@ +# +# Makefile +# +# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c new file mode 100644 index 0000000..f5b9100 --- /dev/null +++ b/board/ti/am43xx/board.c @@ -0,0 +1,56 @@ +/* + * board.c + * + * Board functions for TI AM43XX based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD + +const struct dpll_params dpll_ddr = { + 266, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +void sdram_init(void) +{ +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + return 0; +} +#endif diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h new file mode 100644 index 0000000..8ca098b --- /dev/null +++ b/board/ti/am43xx/board.h @@ -0,0 +1,17 @@ +/* + * board.h + * + * TI AM437x boards information header + * Derived from AM335x board. + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c new file mode 100644 index 0000000..700e9a7 --- /dev/null +++ b/board/ti/am43xx/mux.c @@ -0,0 +1,27 @@ +/* + * mux.c + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux(void) +{ +} -- cgit v0.10.2 From c06e498a16eae82eda3a6947c2375990df20bd3a Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 11:36:28 +0530 Subject: ARM: AM43xx: Add header files Adding the following data: -> Prcm structure -> Base addresses -> Pin mux structure. Signed-off-by: Lokesh Vutla diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index bcb4c50..10b56e0 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -43,13 +43,6 @@ #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ | BIT(3) | BIT(4)) -/* Reset control */ -#ifdef CONFIG_AM33XX -#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) -#elif defined(CONFIG_TI814X) -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#endif -#define PRM_RSTST (PRM_RSTCTRL + 8) #define PRM_RSTCTRL_RESET 0x01 #define PRM_RSTST_WARM_RESET_MASK 0x232 @@ -108,6 +101,7 @@ struct gpmc { /* Used for board specific gpmc initialization */ extern struct gpmc *gpmc_cfg; +#ifndef CONFIG_AM43XX /* Encapsulating core pll registers */ struct cm_wkuppll { unsigned int wkclkstctrl; /* offset 0x00 */ @@ -211,6 +205,162 @@ struct cm_perpll { unsigned int resv10[8]; unsigned int cpswclkstctrl; /* offset 0x144 */ }; +#else +/* Encapsulating core pll registers */ +struct cm_wkuppll { + unsigned int resv0[136]; + unsigned int wkl4wkclkctrl; /* offset 0x220 */ + unsigned int resv1[55]; + unsigned int wkclkstctrl; /* offset 0x300 */ + unsigned int resv2[15]; + unsigned int wkup_i2c0ctrl; /* offset 0x340 */ + unsigned int resv3; + unsigned int wkup_uart0ctrl; /* offset 0x348 */ + unsigned int resv4[5]; + unsigned int wkctrlclkctrl; /* offset 0x360 */ + unsigned int resv5; + unsigned int wkgpio0clkctrl; /* offset 0x368 */ + + unsigned int resv6[109]; + unsigned int clkmoddpllcore; /* offset 0x520 */ + unsigned int idlestdpllcore; /* offset 0x524 */ + unsigned int resv61; + unsigned int clkseldpllcore; /* offset 0x52C */ + unsigned int resv7[2]; + unsigned int divm4dpllcore; /* offset 0x538 */ + unsigned int divm5dpllcore; /* offset 0x53C */ + unsigned int divm6dpllcore; /* offset 0x540 */ + + unsigned int resv8[7]; + unsigned int clkmoddpllmpu; /* offset 0x560 */ + unsigned int idlestdpllmpu; /* offset 0x564 */ + unsigned int resv9; + unsigned int clkseldpllmpu; /* offset 0x56c */ + unsigned int divm2dpllmpu; /* offset 0x570 */ + + unsigned int resv10[11]; + unsigned int clkmoddpllddr; /* offset 0x5A0 */ + unsigned int idlestdpllddr; /* offset 0x5A4 */ + unsigned int resv11; + unsigned int clkseldpllddr; /* offset 0x5AC */ + unsigned int divm2dpllddr; /* offset 0x5B0 */ + + unsigned int resv12[11]; + unsigned int clkmoddpllper; /* offset 0x5E0 */ + unsigned int idlestdpllper; /* offset 0x5E4 */ + unsigned int resv13; + unsigned int clkseldpllper; /* offset 0x5EC */ + unsigned int divm2dpllper; /* offset 0x5F0 */ + unsigned int resv14[8]; + unsigned int clkdcoldodpllper; /* offset 0x614 */ + + unsigned int resv15[2]; + unsigned int clkmoddplldisp; /* offset 0x620 */ + unsigned int resv16[2]; + unsigned int clkseldplldisp; /* offset 0x62C */ + unsigned int divm2dplldisp; /* offset 0x630 */ +}; + +/* + * Encapsulating peripheral functional clocks + * pll registers + */ +struct cm_perpll { + unsigned int l3clkstctrl; /* offset 0x00 */ + unsigned int resv0[7]; + unsigned int l3clkctrl; /* Offset 0x20 */ + unsigned int resv1[7]; + unsigned int l3instrclkctrl; /* offset 0x40 */ + unsigned int resv2[3]; + unsigned int ocmcramclkctrl; /* offset 0x50 */ + unsigned int resv3[9]; + unsigned int tpccclkctrl; /* offset 0x78 */ + unsigned int resv4; + unsigned int tptc0clkctrl; /* offset 0x80 */ + + unsigned int resv5[7]; + unsigned int l4hsclkctrl; /* offset 0x0A0 */ + unsigned int resv6; + unsigned int l4fwclkctrl; /* offset 0x0A8 */ + unsigned int resv7[85]; + unsigned int l3sclkstctrl; /* offset 0x200 */ + unsigned int resv8[7]; + unsigned int gpmcclkctrl; /* offset 0x220 */ + unsigned int resv9[5]; + unsigned int mcasp0clkctrl; /* offset 0x238 */ + unsigned int resv10; + unsigned int mcasp1clkctrl; /* offset 0x240 */ + unsigned int resv11; + unsigned int mmc2clkctrl; /* offset 0x248 */ + unsigned int resv12[5]; + unsigned int usb0clkctrl; /* offset 0x260 */ + unsigned int resv13[103]; + unsigned int l4lsclkstctrl; /* offset 0x400 */ + unsigned int resv14[7]; + unsigned int l4lsclkctrl; /* offset 0x420 */ + unsigned int resv15; + unsigned int dcan0clkctrl; /* offset 0x428 */ + unsigned int resv16; + unsigned int dcan1clkctrl; /* offset 0x430 */ + unsigned int resv17[13]; + unsigned int elmclkctrl; /* offset 0x468 */ + + unsigned int resv18[3]; + unsigned int gpio1clkctrl; /* offset 0x478 */ + unsigned int resv19; + unsigned int gpio2clkctrl; /* offset 0x480 */ + unsigned int resv20; + unsigned int gpio3clkctrl; /* offset 0x488 */ + unsigned int resv21[7]; + + unsigned int i2c1clkctrl; /* offset 0x4A8 */ + unsigned int resv22; + unsigned int i2c2clkctrl; /* offset 0x4B0 */ + unsigned int resv23[3]; + unsigned int mmc0clkctrl; /* offset 0x4C0 */ + unsigned int resv24; + unsigned int mmc1clkctrl; /* offset 0x4C8 */ + + unsigned int resv25[13]; + unsigned int spi0clkctrl; /* offset 0x500 */ + unsigned int resv26; + unsigned int spi1clkctrl; /* offset 0x508 */ + unsigned int resv27[9]; + unsigned int timer2clkctrl; /* offset 0x530 */ + unsigned int resv28; + unsigned int timer3clkctrl; /* offset 0x538 */ + unsigned int resv29; + unsigned int timer4clkctrl; /* offset 0x540 */ + unsigned int resv30[5]; + unsigned int timer7clkctrl; /* offset 0x558 */ + + unsigned int resv31[9]; + unsigned int uart1clkctrl; /* offset 0x580 */ + unsigned int resv32; + unsigned int uart2clkctrl; /* offset 0x588 */ + unsigned int resv33; + unsigned int uart3clkctrl; /* offset 0x590 */ + unsigned int resv34; + unsigned int uart4clkctrl; /* offset 0x598 */ + unsigned int resv35; + unsigned int uart5clkctrl; /* offset 0x5A0 */ + unsigned int resv36[87]; + + unsigned int emifclkstctrl; /* offset 0x700 */ + unsigned int resv361[7]; + unsigned int emifclkctrl; /* offset 0x720 */ + unsigned int resv37[3]; + unsigned int emiffwclkctrl; /* offset 0x730 */ + unsigned int resv371; + unsigned int otfaemifclkctrl; /* offset 0x738 */ + unsigned int resv38[57]; + unsigned int lcdclkctrl; /* offset 0x820 */ + unsigned int resv39[183]; + unsigned int cpswclkstctrl; /* offset 0xB00 */ + unsigned int resv40[7]; + unsigned int cpgmac0clkctrl; /* offset 0xB20 */ +}; +#endif /* CONFIG_AM43XX */ /* Encapsulating Display pll registers */ struct cm_dpll { diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 02f5f8a..fa0bbda 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -17,6 +17,8 @@ #include #elif defined(CONFIG_TI814X) #include +#elif defined(CONFIG_AM43XX) +#include #endif /* @@ -45,8 +47,6 @@ #define EMIF4_1_CFG_BASE 0x4D000000 /* PLL related registers */ -#define CM_PER 0x44E00000 -#define CM_WKUP 0x44E00400 #define CM_DPLL 0x44E00500 #define CM_DEVICE 0x44E00700 #define CM_RTC 0x44E00800 @@ -74,8 +74,4 @@ /* CPSW Config space */ #define CPSW_BASE 0x4A100000 -/* OTG */ -#define USB0_OTG_BASE 0x47401000 -#define USB1_OTG_BASE 0x47401800 - #endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index 432f0c7..5297c63 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -28,6 +28,11 @@ /* PRCM Base Address */ #define PRCM_BASE 0x44E00000 +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 + +#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) +#define PRM_RSTST (PRM_RSTCTRL + 8) /* VTP Base address */ #define VTP0_CTRL_ADDR 0x44E10E0C @@ -43,4 +48,8 @@ /* RTC base address */ #define RTC_BASE 0x44E3E000 +/* OTG */ +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 + #endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h new file mode 100644 index 0000000..d4d5c41 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -0,0 +1,51 @@ +/* + * hardware_am43xx.h + * + * AM43xx hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AM43XX_HARDWARE_AM43XX_H +#define __AM43XX_HARDWARE_AM43XX_H + +/* Module base addresses */ + +/* UART Base Address */ +#define UART0_BASE 0x44E09000 + +/* GPIO Base address */ +#define GPIO2_BASE 0x481AC000 + +/* Watchdog Timer */ +#define WDT_BASE 0x44E35000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x44DF0000 +#define CM_WKUP 0x44DF2800 +#define CM_PER 0x44DF8800 + +#define PRM_RSTCTRL (PRCM_BASE + 0x4000) +#define PRM_RSTST (PRM_RSTCTRL + 4) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x44E10E0C + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x44E12000 +#define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_DATA_REGS_NR 2 + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A101000 + +/* RTC base address */ +#define RTC_BASE 0x44E3E000 + +#endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index 451d935..1ad8cb1 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -25,6 +25,11 @@ /* PRCM Base Address */ #define PRCM_BASE 0x48180000 +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 + +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) +#define PRM_RSTST (PRM_RSTCTRL + 8) /* PLL Subsystem Base Address */ #define PLL_SUBSYS_BASE 0x481C5000 @@ -43,4 +48,8 @@ /* RTC base address */ #define RTC_BASE 0x480C0000 +/* OTG */ +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 + #endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index 1c6b65f..f760d84 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -23,6 +23,8 @@ #include #elif defined(CONFIG_TI814X) #include +#elif defined(CONFIG_AM43XX) +#include #endif struct module_pin_mux { diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h new file mode 100644 index 0000000..0206912 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -0,0 +1,142 @@ +/* + * mux_am43xx.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MUX_AM43XX_H_ +#define _MUX_AM43XX_H_ + +#include +#include + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 19) +#define RXACTIVE (0x1 << 18) +#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 16) /* Pull up/down enable */ +#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */ +#define MODE(val) val /* used for Readability */ + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; +}; + +#endif /* _MUX_AM43XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 66c61e5..d54cf5e 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -15,11 +15,6 @@ #ifndef _OMAP_H_ #define _OMAP_H_ -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ #ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 @@ -28,5 +23,9 @@ #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #define SRAM_SCRATCH_SPACE_ADDR 0x4031B800 +#elif defined(CONFIG_AM43XX) +#define NON_SECURE_SRAM_START 0x402F0400 +#define NON_SECURE_SRAM_END 0x40340000 +#define SRAM_SCRATCH_SPACE_ADDR 0x4033C000 #endif #endif diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index e428512..570f45c 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -9,7 +9,7 @@ #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 -#ifdef CONFIG_AM33XX +#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #elif defined(CONFIG_TI814X) @@ -22,7 +22,7 @@ #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF -#ifdef CONFIG_AM33XX +#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 #elif defined(CONFIG_TI814X) -- cgit v0.10.2 From 3b34ac13fe1e841e8f4ab00dda6a5a7df0568710 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 11:36:29 +0530 Subject: ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 7fd21af..bd8e752 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -10,7 +10,12 @@ LIB = $(obj)lib$(SOC).o COBJS-$(CONFIG_AM33XX) += clock_am33xx.o COBJS-$(CONFIG_TI814X) += clock_ti814x.o -COBJS-$(CONFIG_AM33XX) += clock.o +COBJS-$(CONFIG_AM43XX) += clock_am43xx.o + +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) +COBJS += clock.o +endif + COBJS += sys_info.o COBJS += mem.o COBJS += ddr.o diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c new file mode 100644 index 0000000..c4890f2 --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -0,0 +1,110 @@ +/* + * clock_am43xx.c + * + * clocks for AM43XX based boards + * Derived from AM33XX based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; +struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; + +const struct dpll_regs dpll_mpu_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x560, + .cm_idlest_dpll = CM_WKUP + 0x564, + .cm_clksel_dpll = CM_WKUP + 0x56c, + .cm_div_m2_dpll = CM_WKUP + 0x570, +}; + +const struct dpll_regs dpll_core_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x520, + .cm_idlest_dpll = CM_WKUP + 0x524, + .cm_clksel_dpll = CM_WKUP + 0x52C, + .cm_div_m4_dpll = CM_WKUP + 0x538, + .cm_div_m5_dpll = CM_WKUP + 0x53C, + .cm_div_m6_dpll = CM_WKUP + 0x540, +}; + +const struct dpll_regs dpll_per_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x5E0, + .cm_idlest_dpll = CM_WKUP + 0x5E4, + .cm_clksel_dpll = CM_WKUP + 0x5EC, + .cm_div_m2_dpll = CM_WKUP + 0x5F0, +}; + +const struct dpll_regs dpll_ddr_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x5A0, + .cm_idlest_dpll = CM_WKUP + 0x5A4, + .cm_clksel_dpll = CM_WKUP + 0x5AC, + .cm_div_m2_dpll = CM_WKUP + 0x5B0, +}; + +const struct dpll_params dpll_mpu = { + -1, -1, -1, -1, -1, -1, -1}; +const struct dpll_params dpll_core = { + -1, -1, -1, -1, -1, -1, -1}; +const struct dpll_params dpll_per = { + -1, -1, -1, -1, -1, -1, -1}; + +void setup_clocks_for_console(void) +{ + /* Do not add any spl_debug prints in this function */ + clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + /* Enable UART0 */ + clrsetbits_le32(&cmwkup->wkup_uart0ctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} + +void enable_basic_clocks(void) +{ + u32 *const clk_domains[] = { + &cmper->l3clkstctrl, + &cmper->l3sclkstctrl, + &cmper->l4lsclkstctrl, + &cmwkup->wkclkstctrl, + &cmper->emifclkstctrl, + 0 + }; + + u32 *const clk_modules_explicit_en[] = { + &cmper->l3clkctrl, + &cmper->l4lsclkctrl, + &cmper->l4fwclkctrl, + &cmwkup->wkl4wkclkctrl, + &cmper->l3instrclkctrl, + &cmper->l4hsclkctrl, + &cmwkup->wkgpio0clkctrl, + &cmwkup->wkctrlclkctrl, + &cmper->timer2clkctrl, + &cmper->gpmcclkctrl, + &cmper->elmclkctrl, + &cmper->mmc0clkctrl, + &cmper->mmc1clkctrl, + &cmwkup->wkup_i2c0ctrl, + &cmper->gpio1clkctrl, + &cmper->gpio2clkctrl, + &cmper->gpio3clkctrl, + &cmper->i2c1clkctrl, + &cmper->emiffwclkctrl, + &cmper->emifclkctrl, + &cmper->otfaemifclkctrl, + 0 + }; + + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); +} diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index f5b9100..51b2576 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include "board.h" @@ -19,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD const struct dpll_params dpll_ddr = { - 266, OSC-1, 1, -1, -1, -1, -1}; + -1, -1, -1, -1, -1, -1, -1}; const struct dpll_params *get_dpll_ddr_params(void) { -- cgit v0.10.2 From 806d2792472436a523084775190a11e9d8315275 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 11:36:30 +0530 Subject: ARM: OMAP: Add CONFIG_OMAP_COMMON Adding a new CONFIG_OMAP_COMMON which is included by all boards that needs to build cpu/armv7/omap-common folder. Signed-off-by: Lokesh Vutla diff --git a/Makefile b/Makefile index 7206aba..5461a21 100644 --- a/Makefile +++ b/Makefile @@ -322,7 +322,7 @@ LIBS-y += api/libapi.o LIBS-y += post/libpost.o LIBS-y += test/libtest.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_OMAP_COMMON),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 540a119..ce3903b 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -8,7 +8,7 @@ CROSS_COMPILE ?= arm-linux- ifndef CONFIG_STANDALONE_LOAD_ADDR -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_OMAP_COMMON),) CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 else CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 98f29d4..75b3753 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -21,7 +21,7 @@ COBJS += vc.o COBJS += abb.o endif -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifeq ($(CONFIG_OMAP34XX),) COBJS += boot-common.o SOBJS += lowlevel_init.o endif diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index e32066d..dcc3d68 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -18,6 +18,7 @@ #define CONFIG_AM33XX #define CONFIG_OMAP +#define CONFIG_OMAP_COMMON #include diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 9bf283a..1fd2508 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -19,6 +19,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ +#define CONFIG_OMAP_COMMON #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 5c61697..6500878 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -19,6 +19,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ +#define CONFIG_OMAP_COMMON #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 39a216e..bc5b66c 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -24,6 +24,7 @@ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP_GPIO #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ +#define CONFIG_OMAP_COMMON #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 513121a..cb79b4e 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -21,6 +21,7 @@ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM diff --git a/include/configs/dig297.h b/include/configs/dig297.h index bf91625..30e3908 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -30,6 +30,7 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 12f28f8..240ad78 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -16,6 +16,7 @@ #define CONFIG_AM33XX #define CONFIG_OMAP +#define CONFIG_OMAP_COMMON #include diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index c17267e..a2e70ff 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -18,6 +18,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index c2b1631..85ae016 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -16,6 +16,7 @@ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_MCX /* working with mcx */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define MACH_TYPE_MCX 3656 #define CONFIG_MACH_TYPE MACH_TYPE_MCX diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 36c6800..cfc5f12 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -28,6 +28,7 @@ #define CONFIG_OMAP3430 /* which is in a 3430 */ #define CONFIG_OMAP3_RX51 /* working with RX51 */ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ +#define CONFIG_OMAP_COMMON #define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 4487451..c1245e7 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -19,6 +19,7 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 3b3e25a..edf6543 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -15,6 +15,7 @@ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP34XX /* belonging to 34XX family */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 3dd6d32..ee6db51 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -18,6 +18,7 @@ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SYS_TEXT_BASE 0x80400000 diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 5526b43..0c88419 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -24,6 +24,7 @@ #define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */ #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 3e018c0..88380a4 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -14,6 +14,7 @@ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3_OVERO /* working with overo */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 3e8bd67..91a2568 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -17,6 +17,7 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 836a3d8..a5e469c 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -23,6 +23,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 3687045..c747d52 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -19,6 +19,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index c57df8e..cb8c7ec 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -21,6 +21,7 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 719cb83..e9f2383 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -20,6 +20,7 @@ #define CONFIG_OMAP44XX 1 /* which is a 44XX */ #define CONFIG_OMAP4430 1 /* which is in a 4430 */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON /* Get CPU defs */ #include diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 7dd56cf..7662e2e 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -20,6 +20,7 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP54XX /* which is a 54XX */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON /* Get CPU defs */ #include diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 9b16c47..07af32b 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -21,6 +21,7 @@ #define CONFIG_AM33XX #define CONFIG_OMAP +#define CONFIG_OMAP_COMMON #include diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index c297827..c215f0b 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -16,6 +16,7 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index eac5ad0..c31f4d8 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -20,6 +20,7 @@ #define CONFIG_TI814X #define CONFIG_SYS_NO_FLASH #define CONFIG_OMAP +#define CONFIG_OMAP_COMMON #include diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 4e2cb65..a9b2714 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -19,6 +19,7 @@ /* High Level Configuration Options */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP_COMMON #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER /* diff --git a/spl/Makefile b/spl/Makefile index 6e5299b..28ebc96 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -83,7 +83,7 @@ LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_OMAP_COMMON),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif -- cgit v0.10.2 From 571804086fe6c85c302db72b096cd6796a653e49 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 11:36:31 +0530 Subject: ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 2ba88d0..8f27507 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -16,7 +16,7 @@ COBJS += cache_v7.o COBJS += cpu.o COBJS += syslib.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),) SOBJS += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 6b9ce36..6b4772b 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -40,7 +40,8 @@ void save_omap_boot_params(void) if ((boot_device >= MMC_BOOT_DEVICES_START) && (boot_device <= MMC_BOOT_DEVICES_END)) { -#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) +#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) && \ + !defined(CONFIG_AM43XX) if ((omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) { gd->arch.omap_boot_params.omap_bootmode = diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index d77c25f..bc976ba 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -57,7 +57,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ - defined(CONFIG_AM33XX) || defined(CONFIG_TI814X) + defined(CONFIG_AM33XX) || defined(CONFIG_TI814X) || \ + defined(CONFIG_AM43XX) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); @@ -72,7 +73,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(UART_LCRVAL, &com_port->lcr); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ - defined(CONFIG_TI814X) + defined(CONFIG_TI814X) || defined(CONFIG_AM43XX) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); -- cgit v0.10.2 From 8d0afcd7c216610100c50f75c788bb1254d68871 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 11:36:32 +0530 Subject: ARM: AM43xx: Add config file Add config file Signed-off-by: Lokesh Vutla diff --git a/boards.cfg b/boards.cfg index 211ed58..8d86a1b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -252,6 +252,7 @@ am335x_evm_uart4 arm armv7 am335x ti am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=1,NAND am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT +am43xx_evm arm armv7 am43xx ti am33xx am43xx_evm:SERIAL1,CONS_INDEX=1 ti814x_evm arm armv7 ti814x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h new file mode 100644 index 0000000..5c802a1 --- /dev/null +++ b/include/configs/am43xx_evm.h @@ -0,0 +1,135 @@ +/* + * am43xx_evm.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_AM43XX_EVM_H +#define __CONFIG_AM43XX_EVM_H + +#define CONFIG_AM43XX +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON + +#include + +#define CONFIG_DMA_COHERENT +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* commands to include */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_VERSION_VARIABLE + +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_CMD_ECHO + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + + /* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) +/* Platform/Board specific defs */ +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ + +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ +4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } + +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +#define CONFIG_ENV_IS_NOWHERE + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80800000 + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (101 * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_SPL_MALLOC_START 0x80a08000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#endif /* __CONFIG_AM43XX_EVM_H */ -- cgit v0.10.2 From d69cc4a318d35e202243785f3d1d9a07ef48a688 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 25 Jul 2013 09:27:36 +0200 Subject: ARM: IGEP0033: Remove undef of CONFIG_CMD_MEMTEST After commit: 79cd2f814b1c75efd47161ac27f4cbebf768240f config_cmd_default.h: Remove CONFIG_CMD_MEMTEST It's not necessary to undef the CONFIG_CMD_MEMTEST, so we can remove it from configuration file. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 240ad78..5a33e0d 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -60,13 +60,6 @@ #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS -/* - * Because the issues explained in doc/README.memory-test, the "mtest command - * is considered deprecated. It should not be enabled in most normal ports of - * U-Boot. - */ -#undef CONFIG_CMD_MEMTEST - #define CONFIG_BOOTDELAY 1 /* negative for no autoboot */ #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -- cgit v0.10.2 From 2e6bc670198e08b76bf9e30deb27fdcd4c525e98 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Enric=20Balletb=C3=B2=20i=20Serra?= Date: Thu, 25 Jul 2013 09:27:37 +0200 Subject: ARM: IGEP0033: Add support for Flattened Device Tree. Now, the default kernel to boot the IGEP COM AQUILA is device tree based. As old kernel is deprecated we should adapt the boot commands to use DTB files. Also, with v3.9 and later of the Linux Kernel, uImage isn't builtable anymore by default, so we should switch to use the bootz command. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 5a33e0d..75a05c0 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -42,6 +42,9 @@ /* Display cpuinfo */ #define CONFIG_DISPLAY_CPUINFO +/* Flattened Device Tree */ +#define CONFIG_OF_LIBFDT + /* Commands to include */ #include @@ -64,37 +67,27 @@ #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "rdaddr=0x81000000\0" \ - "bootfile=/boot/uImage\0" \ + "loadaddr=0x80F80000\0" \ + "dtbaddr=0x80200000\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "dtbfile=am335x-base0033.dtb\0" \ "console=ttyO0,115200n8\0" \ - "optargs=\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext4 rootwait\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ - "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "loaduimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ + "env import -t ${loadaddr} ${filesize}\0" \ + "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \ + "load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootm ${loadaddr}\0" \ + "bootz ${loadaddr} - ${dtbaddr}\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ @@ -107,7 +100,7 @@ "echo Running uenvcmd ...;" \ "run uenvcmd;" \ "fi;" \ - "if run loaduimage; then " \ + "if run mmcload; then " \ "run mmcboot;" \ "fi;" \ "fi;" \ -- cgit v0.10.2 From 3a2f040050e0bbd601adbbe23a5fa64d5342a922 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 25 Jul 2013 09:27:38 +0200 Subject: ARM: IGEP0033: Remove CYGNUS name from header. We will not use CYGNUS names for any IGEP COM based on AM335x processor, so, to avoid confusion, remove from headers. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index f71aaa0..87c6736 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -1,5 +1,5 @@ /* - * Board functions for IGEP COM AQUILA/CYGNUS based boards + * Board functions for IGEP COM AQUILA based boards * * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ * diff --git a/board/isee/igep0033/board.h b/board/isee/igep0033/board.h index a6f17e3..a11d7ab 100644 --- a/board/isee/igep0033/board.h +++ b/board/isee/igep0033/board.h @@ -1,5 +1,5 @@ /* - * IGEP COM AQUILA/CYGNUS boards information header + * IGEP COM AQUILA boards information header * * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ * -- cgit v0.10.2 From cf8d0057aa57d794870203963c8187ab180fce42 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 25 Jul 2013 09:27:39 +0200 Subject: ARM: IGEP0033: Add support to boot from NAND. Add to the default environment the possibily to boot from NAND using a ubi rootfs. Also the partition scheme is set as follows: Start Size SPL : 0x00000000 0x00080000 (512KiB) U-Boot : 0x00080000 0x00100000 (1MiB) U-Boot Env : 0x00180000 0x00020000 (128KiB) File System : 0x001C0000 - The ubiboot script gets the kernel and the dtb file from the boot directory of the File System. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 75a05c0..dd21a46 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -63,6 +63,10 @@ #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS +/* Make the verbose messages from UBI stop printing */ +#define CONFIG_UBI_SILENCE_MSG +#define CONFIG_UBIFS_SILENCE_MSG + #define CONFIG_BOOTDELAY 1 /* negative for no autoboot */ #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -73,21 +77,34 @@ "bootfile=zImage\0" \ "dtbfile=am335x-base0033.dtb\0" \ "console=ttyO0,115200n8\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ + "ubiroot=ubi0:filesystem rw ubi.mtd=3,2048\0" \ "mmcrootfstype=ext4 rootwait\0" \ + "ubirootfstype=ubifs rootwait\0" \ "mmcargs=setenv bootargs console=${console} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ + "ubiargs=setenv bootargs console=${console} " \ + "root=${ubiroot} " \ + "rootfstype=${ubirootfstype}\0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t ${loadaddr} ${filesize}\0" \ "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \ "load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \ + "ubiload=ubi part filesystem 2048; ubifsmount ubi0; " \ + "ubifsload ${loadaddr} ${bootdir}/${bootfile}; " \ + "ubifsload ${dtbaddr} ${bootdir}/${dtbfile} \0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootz ${loadaddr} - ${dtbaddr}\0" \ + "ubiboot=echo Booting from nand (ubifs) ...; " \ + "run ubiargs; run ubiload; " \ + "bootz ${loadaddr} - ${dtbaddr}\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ @@ -103,6 +120,8 @@ "if run mmcload; then " \ "run mmcboot;" \ "fi;" \ + "else " \ + "run ubiboot;" \ "fi;" \ /* Max number of command args */ @@ -182,18 +201,21 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION 1 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_ENV_OFFSET 0x180000 /* environment starts here */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_OFFSET + CONFIG_SYS_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #define CONFIG_MTD_PARTITIONS #define CONFIG_MTD_DEVICE #define CONFIG_RBTREE #define CONFIG_LZO -#define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:512k(SPL),"\ - "1m(U-Boot),128k(U-Boot Env),"\ - "5m(Kernel),-(File System)" +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(spl),"\ + "1m(uboot),256k(environment),"\ + "-(filesystem)" /* Unsupported features */ #undef CONFIG_USE_IRQ -- cgit v0.10.2 From 5c119cb2befb830144e3496668773188081ccf77 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 25 Jul 2013 09:27:40 +0200 Subject: ARM: IGEP0033: Remove duplicate / unused #defines. As config was originally based on am335x_evm.h we have also some duplicate / unnused #defines. Commit 15191c91 removed these #defines on various AM335x boards but not for IGEP COM AQUILA. This patch simply removes them for this board. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index dd21a46..18be38a 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -137,7 +137,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ -#define CONFIG_SYS_HZ 1000 /* 1ms clock */ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ @@ -150,7 +149,7 @@ /* Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 @@ -159,7 +158,6 @@ #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SERIAL_MULTI #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 @@ -273,10 +271,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ECCSTEPS 4 -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) - #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -- cgit v0.10.2 From 49720a4b5a41aa20cd0f30e279bccf9d1fc648c0 Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Wed, 24 Jul 2013 12:22:34 -0700 Subject: omap: overo: update support for Micron 1GB POP Signed-off-by: Ash Charles diff --git a/board/overo/overo.c b/board/overo/overo.c index a6e2e93..92d3de4 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -153,6 +153,12 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->ctrlb = HYNIX_V_ACTIMB_165; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; + case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ + timings->mcfg = MCFG(512 << 20, 15); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; default: timings->mcfg = MICRON_V_MCFG_165(128 << 20); timings->ctrla = MICRON_V_ACTIMA_165; diff --git a/board/overo/overo.h b/board/overo/overo.h index 88e197d..64604de 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -21,6 +21,7 @@ const omap3_sysinfo sysinfo = { #define REVISION_0 0x0 #define REVISION_1 0x1 #define REVISION_2 0x2 +#define REVISION_3 0x3 /* * IEN - Input Enable -- cgit v0.10.2 From 802b3c7c1826018530acc8a7b8fe83f11614c937 Mon Sep 17 00:00:00 2001 From: Ash Charles Date: Wed, 24 Jul 2013 12:22:35 -0700 Subject: omap: overo: Use 200MHz SDRC timings for revision 1, 2 & 3 boards Gumstix uses 200Mhz RAM on revision 1, 2 & 3 COMs, so use 200MHz timings rather than 165MHz. Based on 6cf8bf44b1f8550e12f7f2a16e01890e5de8443d Signed-off-by: Ash Charles diff --git a/board/overo/overo.c b/board/overo/overo.c index 92d3de4..aace42a 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -142,16 +142,16 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = MICRON_V_MCFG_165(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = HYNIX_V_MCFG_165(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_165; - timings->ctrlb = HYNIX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ timings->mcfg = MCFG(512 << 20, 15); -- cgit v0.10.2 From a704a6d615179a25f556c99d31cbc4ee366ffb54 Mon Sep 17 00:00:00 2001 From: Naumann Andreas Date: Tue, 9 Jul 2013 09:43:17 +0200 Subject: ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e. In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in Certain Configurations' of the TI Errata it is recommended to use certain div/mult values for the DPLL5 clock setup. So far u-boot used the old 34xx values, so I added the errata recommended values specificly for 36xx init only. Also, the FSEL registers exist no longer, so removed them from init. Tested this on a AM3703 board with 19.2MHz oscillator, which previously couldnt lock the dpll5 (kernel complained). As a consequence the EHCI USB port wasnt usable in U-Boot and kernel. With this patch, kernel panics disappear and USB working fine in u-boot and kernel. Signed-off-by: Andreas Naumann [trini: Add extern to Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 3acbc9c..e903ed9 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -478,6 +478,24 @@ static void dpll4_init_36xx(u32 sil_index, u32 clk_index) wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); } +static void dpll5_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param(); + + /* Moving it to the right sysclk base */ + ptr = ptr + clk_index; + + /* PER2 DPLL (DPLL5) */ + sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP); + wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); + sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */ + sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */ + sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/ + sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); +} + static void mpu_init_36xx(u32 sil_index, u32 clk_index) { struct prcm *prcm_base = (struct prcm *)PRCM_BASE; @@ -582,7 +600,7 @@ void prcm_init(void) dpll3_init_36xx(0, clk_index); dpll4_init_36xx(0, clk_index); - dpll5_init_34xx(0, clk_index); + dpll5_init_36xx(0, clk_index); iva_init_36xx(0, clk_index); mpu_init_36xx(0, clk_index); diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index bdf74ea..98c3c03 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -464,6 +464,19 @@ per_36x_dpll_param: .word 26000, 432, 12, 9, 16, 9, 4, 3, 1 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1 +per2_36x_dpll_param: +/* 12MHz */ +.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12 +/* 13MHz */ +.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13 +/* 19.2MHz */ +.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2 +/* 26MHz */ +.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26 +/* 38.4MHz */ +.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4 + + ENTRY(get_36x_mpu_dpll_param) adr r0, mpu_36x_dpll_param mov pc, lr @@ -483,3 +496,8 @@ ENTRY(get_36x_per_dpll_param) adr r0, per_36x_dpll_param mov pc, lr ENDPROC(get_36x_per_dpll_param) + +ENTRY(get_36x_per2_dpll_param) + adr r0, per2_36x_dpll_param + mov pc, lr +ENDPROC(get_36x_per2_dpll_param) diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h index da776cf..514839c 100644 --- a/arch/arm/include/asm/arch-omap3/clock.h +++ b/arch/arm/include/asm/arch-omap3/clock.h @@ -61,6 +61,7 @@ extern dpll_param *get_36x_mpu_dpll_param(void); extern dpll_param *get_36x_iva_dpll_param(void); extern dpll_param *get_36x_core_dpll_param(void); extern dpll_param *get_36x_per_dpll_param(void); +extern dpll_param *get_36x_per2_dpll_param(void); extern void *_end_vect, *_start; diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h index bf7fa00..df73c4b 100644 --- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h +++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h @@ -323,4 +323,26 @@ #define PER_36XX_FSEL_38P4 0x07 #define PER_36XX_M2_38P4 0x09 +/* 36XX PER2 DPLL */ + +#define PER2_36XX_M_12 0x50 +#define PER2_36XX_N_12 0x00 +#define PER2_36XX_M2_12 0x08 + +#define PER2_36XX_M_13 0x1BB +#define PER2_36XX_N_13 0x05 +#define PER2_36XX_M2_13 0x08 + +#define PER2_36XX_M_19P2 0x32 +#define PER2_36XX_N_19P2 0x00 +#define PER2_36XX_M2_19P2 0x08 + +#define PER2_36XX_M_26 0x1BB +#define PER2_36XX_N_26 0x0B +#define PER2_36XX_M2_26 0x08 + +#define PER2_36XX_M_38P4 0x19 +#define PER2_36XX_N_38P4 0x00 +#define PER2_36XX_M2_38P4 0x08 + #endif /* endif _CLOCKS_OMAP3_H_ */ -- cgit v0.10.2 From 2f6af82719723033b35f2bf97e3fe4f65400781f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 5 Aug 2013 10:49:42 +0900 Subject: ARM: omap24xx: remove remainders of dead board Since Commit 7f5eef9 removed OMAP2420H4 support, arm1136/omap24xx has not been used at all. Signed-off-by: Masahiro Yamada diff --git a/arch/arm/cpu/arm1136/omap24xx/Makefile b/arch/arm/cpu/arm1136/omap24xx/Makefile deleted file mode 100644 index 7d76d96..0000000 --- a/arch/arm/cpu/arm1136/omap24xx/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -SOBJS = reset.o - -COBJS = timer.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm1136/omap24xx/reset.S b/arch/arm/cpu/arm1136/omap24xx/reset.S deleted file mode 100644 index dd0752b..0000000 --- a/arch/arm/cpu/arm1136/omap24xx/reset.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * armboot - Startup Code for OMP2420/ARM1136 CPU-core - * - * Copyright (c) 2004 Texas Instruments - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.globl reset_cpu -reset_cpu: - ldr r1, rstctl /* get addr for global reset reg */ - mov r3, #0x2 /* full reset pll+mpu */ - str r3, [r1] /* force reset */ - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PM_RSTCTRL_WKUP diff --git a/arch/arm/cpu/arm1136/omap24xx/timer.c b/arch/arm/cpu/arm1136/omap24xx/timer.c deleted file mode 100644 index b1eef27d..0000000 --- a/arch/arm/cpu/arm1136/omap24xx/timer.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments - * Richard Woodruff - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) -#define TIMER_LOAD_VAL 0 - -/* macro to read the 32 bit timer */ -#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+TCRR) \ - / (TIMER_CLOCK / CONFIG_SYS_HZ) - -DECLARE_GLOBAL_DATA_PTR; - -int timer_init (void) -{ - int32_t val; - - /* Start the counter ticking up */ - *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ - val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ - *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ - - /* reset time */ - gd->arch.lastinc = READ_TIMER; /* capture current incrementer value */ - gd->arch.tbl = 0; /* start "advancing" time stamp */ - - return(0); -} -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay (unsigned long usec) -{ - ulong tmo, tmp; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - tmp = get_timer (0); /* get current timestamp */ - if ((tmo + tmp + 1) < tmp) { /* if setting this forward will roll */ - /* time stamp, then reset time */ - gd->arch.lastinc = READ_TIMER; /* capture incrementer value */ - gd->arch.tbl = 0; /* start time stamp */ - } else { - tmo += tmp; /* else, set advancing stamp wake up time */ - } - while (get_timer_masked () < tmo)/* loop till event */ - /*NOP*/; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (now >= gd->arch.lastinc) { /* normal mode (non roll) */ - /* move stamp fordward with absoulte diff ticks */ - gd->arch.tbl += (now - gd->arch.lastinc); - } else { - /* we have rollover of incrementer */ - gd->arch.tbl += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ)) - - gd->arch.lastinc) + now; - } - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - tbclk = CONFIG_SYS_HZ; - return tbclk; -} -- cgit v0.10.2 From 0474fb0e2b22a831cf47848b21bdb3e152c108bc Mon Sep 17 00:00:00 2001 From: Taras Kondratiuk Date: Tue, 6 Aug 2013 16:16:50 +0300 Subject: omap: emif: Set initial DDR PHY config first Commit "OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon" (f40107345cbcd6e0d1747eda45e76c4e2a6df0db) changed sequence to set final DDR PHY config register value at the beginning. Looks like it was made by mistake and should be reverted. Signed-off-by: Taras Kondratiuk diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index ece3655..b0e1caa 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -153,7 +153,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs) * un-locked frequency & default RL */ writel(regs->sdram_config_init, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); do_ext_phy_settings(base, regs); -- cgit v0.10.2 From 2be6bed003e20e0049d245b1447277cafbb30a72 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 7 Aug 2013 17:53:18 +0200 Subject: ARM: igep00x0.h: Enable the use of CMD_EXT4, CMD_FS_GENERIC and zImage. Able to load the kernel from some form of ext[234] or FAT. Also, with v3.9 and later of the Linux Kernel, uImage isn't builtable anymore by default, so we should switch to use the bootz command. Signed-off-by: Enric Balletbo i Serra diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index a2e70ff..a555e5a 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -98,8 +98,9 @@ #include #define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_EXT4 #define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ #ifdef CONFIG_BOOT_ONENAND @@ -164,17 +165,17 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loadzimage=load mmc ${mmcdev} ${loadaddr} zImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ + "bootz ${loadaddr}\0" \ "nandboot=echo Booting from onenand ...; " \ "run nandargs; " \ "onenand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ + "bootz ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ @@ -186,7 +187,7 @@ "echo Running uenvcmd ...;" \ "run uenvcmd;" \ "fi;" \ - "if run loaduimage; then " \ + "if run loadzimage; then " \ "run mmcboot;" \ "fi;" \ "fi;" \ -- cgit v0.10.2 From a2fa28bc988fdc1cb5cc00abc8b63626bc3c9f76 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 7 Aug 2013 17:53:19 +0200 Subject: OMAP3: igep00x0: allow booting with a FDT from MMC IGEP boards now have Device Tree support in the mainline kernel. To boot an IGEP board using a DT, a uEnv.txt plain text file could be used to define a custom uenvcmd that will be run by the default boot command. It is more convenient to change the default boot command to allow loading a FDT if it is stored in the boot dir of the rootfs uSD/MMC partition. If no FDT is found then the defaul command tries to boot a zImage without a DT using legacy boot. Signed-off-by: Javier Martinez Canillas diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 77a9bc6..7a7500b 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -138,6 +138,18 @@ int board_mmc_init(bd_t *bis) } #endif +void set_fdt(void) +{ + switch (gd->bd->bi_arch_number) { + case MACH_TYPE_IGEP0020: + setenv("dtbfile", "omap3-igep0020.dtb"); + break; + case MACH_TYPE_IGEP0030: + setenv("dtbfile", "omap3-igep0030.dtb"); + break; + } +} + /* * Routine: misc_init_r * Description: Configure board specific parts @@ -150,6 +162,8 @@ int misc_init_r(void) dieid_num_r(); + set_fdt(); + return 0; } diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index a555e5a..722c566 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -138,6 +138,9 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "usbtty=cdc_acm\0" \ "loadaddr=0x82000000\0" \ + "dtbaddr=0x81600000\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ "usbtty=cdc_acm\0" \ "console=ttyO2,115200n8\0" \ "mpurate=auto\0" \ @@ -168,10 +171,13 @@ "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ - "loadzimage=load mmc ${mmcdev} ${loadaddr} zImage\0" \ + "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootz ${loadaddr}\0" \ + "mmcbootfdt=echo Booting with DT from mmc ...; " \ + "bootz ${loadaddr} - ${dtbaddr}\0" \ "nandboot=echo Booting from onenand ...; " \ "run nandargs; " \ "onenand read ${loadaddr} 280000 400000; " \ @@ -188,6 +194,11 @@ "run uenvcmd;" \ "fi;" \ "if run loadzimage; then " \ + "if test -n $dtbfile; then " \ + "if run loadfdt; then " \ + "run mmcbootfdt;" \ + "fi;" \ + "fi;" \ "run mmcboot;" \ "fi;" \ "fi;" \ -- cgit v0.10.2 From dd5729a0281eb86fd4fe07701219c4f5e40b3bb9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 9 Aug 2013 11:22:12 -0400 Subject: am33xx: CONFIG_DMA_COHERENT defines are unused, remove Acked-by: Dan Murphy Signed-off-by: Tom Rini diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 18be38a..2ee1367 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -28,10 +28,6 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -/* DMA defines */ -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) - #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_SYS_MALLOC_LEN (1024 << 10) #define CONFIG_SYS_LONGHELP /* undef to save memory */ diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 07af32b..a3f8ead 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -25,9 +25,6 @@ #include -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) - #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_SYS_MALLOC_LEN (1024 << 10) #define CONFIG_SYS_LONGHELP /* undef to save memory */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index c31f4d8..42d113d 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -24,9 +24,6 @@ #include -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) - #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_SYS_MALLOC_LEN (1024 << 10) #define CONFIG_SYS_LONGHELP /* undef to save memory */ -- cgit v0.10.2 From 73feefdc1ab0173f5a3d12ed78f967d6c0664849 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 9 Aug 2013 11:22:13 -0400 Subject: am33xx: Stop using PHYS_DRAM_1 define We defined PHYS_DRAM_1 to 0x80000000 (start of DRAM) and then used this for CONFIG_SYS_SDRAM_BASE. But then we kept on referencing PHYS_DRAM_1 in other places. Change to directly setting CONFIG_SYS_DRAM_BASE and then using that name in code. Signed-off-by: Tom Rini diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 87c6736..a24c22b 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -96,7 +96,7 @@ void sdram_init(void) */ int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; gpmc_init(); diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index f3bad76..f53c5bb 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -112,7 +112,7 @@ int board_init(void) { i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index eac9cc9..04c37e2 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -343,7 +343,7 @@ int board_init(void) STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; #endif - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; gpmc_init(); diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 31ddc68..e406326 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -112,7 +112,7 @@ void sdram_init(void) */ int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 2ee1367..e08fc14 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -136,10 +136,9 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) /* Platform/Board specific defs */ diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index a3f8ead..d4d4d79 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -123,7 +123,7 @@ * memtest works on 8 MB in DRAM after skipping 32MB from * start addr of ram disk */ -#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (64 << 20)) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + (8 * 1024 * 1024)) @@ -147,10 +147,9 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 19) /* 512MiB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) /* Platform/Board specific defs */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 42d113d..dfc4c75 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -117,7 +117,7 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MEMTEST_START PHYS_DRAM_1 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + PHYS_DRAM_1_SIZE - (8 << 12)) @@ -137,11 +137,10 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 banks of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ #define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) -- cgit v0.10.2 From 4db4076206d643065c6cd5b87a7b014e15ff17e0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 9 Aug 2013 11:22:14 -0400 Subject: am335x_evm: Use default baud rate table Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index dcc3d68..d6ccf26 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -315,8 +315,6 @@ #define CONFIG_OMAP_GPIO #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ -4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } /* CPU */ #define CONFIG_ARCH_CPU_INIT -- cgit v0.10.2 From ec101fdb8d419975c7722c1d23470d9674350c3c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 9 Aug 2013 11:22:15 -0400 Subject: arm: spl: For Falcon Mode, set a default machid of ~0 With device trees, boards do not always set CONFIG_MACH_TYPE now, so we must not rely on this define being set. The kernel uses ~0 to see if we have a valid machine number or not, so set that as the default, invalid machine, id and only fix if CONFIG_MACH_TYPE is set. Acked-by: Dan Murphy Tested-by: Heiko Schocher Cc: Albert ARIBAUD Signed-off-by: Tom Rini diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 583bdb3..26d0be4 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -45,12 +45,17 @@ void __weak board_init_f(ulong dummy) #ifdef CONFIG_SPL_OS_BOOT void __noreturn jump_to_image_linux(void *arg) { + unsigned long machid = 0xffffffff; +#ifdef CONFIG_MACH_TYPE + machid = CONFIG_MACH_TYPE; +#endif + debug("Entering kernel arg pointer: 0x%p\n", arg); typedef void (*image_entry_arg_t)(int, int, void *) __attribute__ ((noreturn)); image_entry_arg_t image_entry = (image_entry_arg_t) spl_image.entry_point; cleanup_before_linux(); - image_entry(0, CONFIG_MACH_TYPE, arg); + image_entry(0, machid, arg); } #endif -- cgit v0.10.2 From bc6fff9ac7145fc067b8b2de4457d7af98209ec0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 9 Aug 2013 11:22:16 -0400 Subject: am335x_evm: Bring in 'boot_fdt' logic from i.MX Bring in the 'boot_fdt' environment variable that i.MX boards use to try and load a device tree when booting. Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index d6ccf26..d236a89 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -85,6 +85,7 @@ "loadaddr=0x80200000\0" \ "fdtaddr=0x80F80000\0" \ "fdt_high=0xffffffff\0" \ + "boot_fdt=try\0" \ "rdaddr=0x81000000\0" \ "bootdir=/boot\0" \ "bootfile=uImage\0" \ @@ -132,6 +133,20 @@ "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ "loaduimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcloados=run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ "mmcboot=mmc dev ${mmcdev}; " \ "if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ @@ -143,11 +158,7 @@ "echo Running uenvcmd ...;" \ "run uenvcmd;" \ "fi;" \ - "if run loaduimage; then " \ - "run loadfdt;" \ - "run mmcargs; " \ - "bootm ${loadaddr} - ${fdtaddr};" \ - "fi;" \ + "run mmcloados;" \ "fi;\0" \ "spiboot=echo Booting from spi ...; " \ "run spiargs; " \ -- cgit v0.10.2 From 8769455861aa003fdc1d120f7aae7482a92b61d7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 9 Aug 2013 11:22:17 -0400 Subject: TI:am33xx: Create common config files for TI ARMv7 platforms, and AM33xx We create two new files, include/configs/ti_armv7_common.h for all of the common IP blocks and related features / commands we share in virtually all of our platforms. We then create include/configs/ti_am335x_common.h for everything common to the am335x SoC leaving just the board specific parts to include/configs/ti_am335x_common.h. Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index d236a89..e0a87f8 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -16,44 +16,20 @@ #ifndef __CONFIG_AM335X_EVM_H #define __CONFIG_AM335X_EVM_H -#define CONFIG_AM33XX -#define CONFIG_OMAP -#define CONFIG_OMAP_COMMON +#include -#include - -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) - -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "U-Boot# " -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_SYS_NO_FLASH #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_STACKSIZE (128 * 1024) -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) /* Custom script for NOR */ #define CONFIG_SYS_LDSCRIPT "board/ti/am335x/u-boot.lds" -#define CONFIG_SYS_CACHELINE_SIZE 64 - -/* commands to include */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_VERSION_VARIABLE +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) #ifdef CONFIG_NAND #define NANDARGS \ @@ -76,10 +52,8 @@ #define NANDARGS "" #endif -/* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ @@ -197,60 +171,11 @@ "run mmcboot;" \ "run nandboot;" -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_CMD_ECHO - -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * memtest works on 8 MB in DRAM after skipping 32MB from - * start addr of ram disk - */ -#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ - + (8 * 1024 * 1024)) - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ - -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_FS_GENERIC - -#define CONFIG_SPI -#define CONFIG_OMAP3_SPI -#define CONFIG_MTD_DEVICE -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED (24000000) - /* USB Composite download gadget - g_dnl */ #define CONFIG_USB_GADGET #define CONFIG_USBDOWNLOAD_GADGET /* USB TI's IDs */ -#define CONFIG_USBD_HS #define CONFIG_G_DNL_VENDOR_NUM 0x0403 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" @@ -284,109 +209,24 @@ "rootfs part 0 9" #endif - /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - /* Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 /* 1ms clock */ - /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 /* I2C Configuration */ -#define CONFIG_I2C -#define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP24XX_I2C #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_OMAP_GPIO - -#define CONFIG_BAUDRATE 115200 - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_CONSOLE_INFO_QUIET - +/* SPL */ #ifndef CONFIG_NOR_BOOT -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -/* - * Place the image at the start of the ROM defined image space. - * We limit our size to the ROM-defined downloaded image area, and use the - * rest of the space for stack. - */ -#define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR - -#define CONFIG_SPL_OS_BOOT - -#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#ifdef CONFIG_SPL_OS_BOOT -/* fat */ -#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args" -#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_DRAM_1 + 0x100) - -/* raw mmc */ -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ - -/* nand */ -#ifdef CONFIG_NAND -#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 -#endif - -/* spl export command */ -#define CONFIG_CMD_SPL -#endif - -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_YMODEM_SUPPORT #define CONFIG_SPL_NET_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -401,14 +241,7 @@ #define CONFIG_SPL_MUSB_NEW_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" -#define CONFIG_SPL_BOARD_INIT - #ifdef CONFIG_NAND -#define CONFIG_SPL_NAND_AM33XX_BCH -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) @@ -428,30 +261,16 @@ #define CONFIG_SYS_NAND_ECCBYTES 14 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif #endif /* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. + * For NOR boot, we must set this to the start of where NOR is mapped + * in memory. */ #ifdef CONFIG_NOR_BOOT #define CONFIG_SYS_TEXT_BASE 0x08000000 -#else -#define CONFIG_SYS_TEXT_BASE 0x80800000 -#endif -#define CONFIG_SYS_SPL_MALLOC_START 0x80a08000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -/* Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT #endif /* @@ -506,7 +325,6 @@ #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ #define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ #define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ -#define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nor0=m25p80-flash.0" #define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \ "512k(u-boot),128k(u-boot-env1)," \ @@ -519,22 +337,13 @@ #define CONFIG_SYS_MMC_ENV_PART 2 #endif -/* Unsupported features */ -#undef CONFIG_USE_IRQ +/* SPI flash. */ +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_SPEED 24000000 -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_DRIVER_TI_CPSW -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI +/* Network. */ #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB #define CONFIG_PHY_ADDR 0 @@ -543,14 +352,7 @@ /* NAND support */ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_NAND_OMAP_GPMC #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 -#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND - devices */ #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ @@ -579,6 +381,7 @@ */ #if defined(CONFIG_NOR) #undef CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_FLASH #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_FLASH_CFI @@ -594,7 +397,6 @@ #define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */ #define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */ -#define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nor0=physmap-flash.0" #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ "512k(u-boot)," \ @@ -602,8 +404,6 @@ "128k(u-boot-env2)," \ "4m(kernel),-(rootfs)" #endif -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_FLASH #endif /* NOR support */ #endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h new file mode 100644 index 0000000..fd3ffab --- /dev/null +++ b/include/configs/ti_am335x_common.h @@ -0,0 +1,60 @@ +/* + * ti_am335x_common.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/am3359#technicaldocuments + */ + +#ifndef __CONFIG_TI_AM335X_COMMON_H__ +#define __CONFIG_TI_AM335X_COMMON_H__ + +#define CONFIG_AM33XX +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#include + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 + +/* Network defines. */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 + +/* SPL defines. */ +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_YMODEM_SUPPORT + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Now bring in the rest of the common code. */ +#include + +#endif /* __CONFIG_TI_AM335X_COMMON_H__ */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h new file mode 100644 index 0000000..525b867 --- /dev/null +++ b/include/configs/ti_armv7_common.h @@ -0,0 +1,248 @@ +/* + * ti_armv7_common.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + * + * The various ARMv7 SoCs from TI all share a number of IP blocks when + * implementing a given feature. Rather than define these in every + * board or even SoC common file, we define a common file to be re-used + * in all cases. While technically true that some of these details are + * configurable at the board design, they are common throughout SoC + * reference platforms as well as custom designs and become de facto + * standards. + */ + +#ifndef __CONFIG_TI_ARMV7_COMMON_H__ +#define __CONFIG_TI_ARMV7_COMMON_H__ + +/* Common define for many platforms. */ +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON + +/* + * We typically do not contain NOR flash. In the cases where we do, we + * undefine this later. + */ +#define CONFIG_SYS_NO_FLASH + +/* Support both device trees and ATAGs. */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Our DDR memory always starts at 0x80000000 and U-Boot shall have + * relocated itself to higher in memory by the time this value is used. + */ +#define CONFIG_SYS_LOAD_ADDR 0x80000000 + +/* + * Default to a quick boot delay. + */ +#define CONFIG_BOOTDELAY 1 + +/* + * DDR information. We say (for simplicity) that we have 1 bank, + * always, even when we have more. We always start at 0x80000000, + * and we place the initial stack pointer in our SRAM. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/* Timer information. */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +/* I2C IP block */ +#define CONFIG_I2C +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_DRIVER_OMAP24XX_I2C + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC + +/* McSPI IP block */ +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI + +/* GPIO block */ +#define CONFIG_OMAP_GPIO + +/* + * GPMC NAND block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_NAND +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_BASE 0x8000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#endif + +/* + * The following are general good-enough settings for U-Boot. We set a + * large malloc pool as we generally have a lot of DDR, and we opt for + * function over binary size in the main portion of U-Boot as this is + * generally easily constrained later if needed. We enable the config + * options that give us information in the environment about what board + * we are on so we do not need to rely on the command prompt. We set a + * console baudrate of 115200 and use the default baud rate table. + */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_VERSION_VARIABLE +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_BAUDRATE 115200 + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* + * When we have SPI, NOR or NAND flash we expect to be making use of + * mtdparts, both for ease of use in U-Boot and for passing information + * on to the Linux kernel. + */ +#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND) +#define CONFIG_MTD_DEVICE /* Required for mtdparts */ +#define CONFIG_CMD_MTDPARTS +#endif + +/* + * For commands to use, we take the default list and add a few other + * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH + * prior to this include, in order to skip a few commands. When we do + * have flash, if we expect these commands they must be enabled in that + * config. + */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_BOOTZ + +/* + * Common filesystems support. When we have removable storage we + * enabled a number of useful commands and support. + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC +#endif + +/* + * Our platforms make use of SPL to initalize the hardware (primarily + * memory) enough for full U-Boot to be loaded. We also support Falcon + * Mode so that the Linux kernel can be booted directly from SPL + * instead, if desired. We make use of the general SPL framework found + * under common/spl/. Given our generally common memory map, we set a + * number of related defaults and sizes here. + */ +#ifndef CONFIG_NOR_BOOT +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_OS_BOOT + +/* + * Place the image at the start of the ROM defined image space. + * We limit our size to the ROM-defined downloaded image area, and use the + * rest of the space for stack. We load U-Boot itself into memory at + * 0x80800000 for legacy reasons (to not conflict with older SPLs). We + * have our BSS be placed 1MiB after this, to allow for the default + * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. + * We have the SPL malloc pool at the end of the BSS area. + */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ + +/* FAT sd card locations. */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) + +/* FAT */ +#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args" + +/* RAW SD card / eMMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ + +/* NAND */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif + +/* spl export command */ +#define CONFIG_CMD_SPL +#endif + +#ifdef CONFIG_MMC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#endif + +/* General parts of the framework. */ +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#endif +#endif /* !CONFIG_NOR_BOOT */ + +#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ -- cgit v0.10.2 From a8017574809bfcfd98c7752d193291bde4b09699 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 9 Aug 2013 11:22:18 -0400 Subject: TI:omap5/dra7xx: Convert to ti_armv7_common.h Update omap5_common.h to use ti_armv7_common.h, and in turn update dra7xx_evm.h and omap5_uevm.h slightly. The biggest changes here are that IP blocks which exist on the platform, and had clocks enabled, now have the drivers being built as well. Signed-off-by: Tom Rini diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 51be73d..58786ff 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -12,21 +12,18 @@ #ifndef __CONFIG_DRA7XX_EVM_H #define __CONFIG_DRA7XX_EVM_H -/* High Level Configuration Options */ -#define CONFIG_DRA7XX /* in a TI DRA7XX core */ -#define CONFIG_ENV_IS_NOWHERE /* For now. */ - -#include +#define CONFIG_DRA7XX -#define CONFIG_SYS_PROMPT "DRA752 EVM # " +#define CONFIG_ENV_IS_NOWHERE /* For now. */ +#define CONSOLEDEV "ttyO0" #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 UART1_BASE #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_OMAP_ABE_SYSCK -#define CONSOLEDEV "ttyO0" +#include /* CPSW Ethernet */ #define CONFIG_CMD_NET diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 7662e2e..8e82fed 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -9,112 +9,59 @@ * TI OMAP5 AND DRA7XX common configuration settings * * SPDX-License-Identifier: GPL-2.0+ + * + * For more details, please see the technical documents listed at + * http://www.ti.com/product/omap5432 */ #ifndef __CONFIG_OMAP5_COMMON_H #define __CONFIG_OMAP5_COMMON_H -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP54XX /* which is a 54XX */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON - -/* Get CPU defs */ -#include -#include - -/* Display CPU and Board Info */ +#define CONFIG_OMAP54XX #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_MISC_INIT_R +#define CONFIG_ARCH_CPU_INIT -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ +#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE + +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + +/* Defines for SDRAM init */ +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PALMAS_POWER +#endif + +#include +#include -/* - * Size of malloc() pool - * Total Size Environment - 128k - * Malloc - add 256k - */ #define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) -/* Vector Base */ -#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE -/* - * Hardware drivers - */ +#include /* - * serial port - NS16550 compatible + * Hardware drivers */ -#define V_NS16550_CLK 48000000 - #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -/* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C -#define CONFIG_I2C_MULTI_BUS - -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* Flash */ -#define CONFIG_SYS_NO_FLASH - -/* Cache */ -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_CACHELINE_SHIFT 6 - -/* commands to include */ -#include - -/* Enabled commands */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_SYS_NS16550_CLK 48000000 -/* Disabled commands */ +/* Per-SoC commands */ #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMLS /* List all found images */ /* * Environment setup */ - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT4 - -#define CONFIG_ENV_OVERWRITE - #ifndef PARTS_DEFAULT #define PARTS_DEFAULT #endif @@ -179,96 +126,11 @@ "fi; " \ "fi" -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -/* - * memtest setup - */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20)) - -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 - -/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* - * SDRAM Memory Map - * Even though we use two CS all the memory - * is mapped to one contiguous block - */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -/* Defines for SDRAM init */ -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PALMAS_POWER -#endif /* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40300350 #define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_DISPLAY_PRINT - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -/* - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 80E7FFC0--0x80E80000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80E80000 - -/* - * BSS and malloc area 64MB into memory to allow enough - * space for the kernel at the beginning of memory - */ -#define CONFIG_SPL_BSS_START_ADDR 0x84000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SPL_GPIO_SUPPORT - #endif /* __CONFIG_OMAP5_COMMON_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 47568e9..d10c2b5 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -17,8 +17,6 @@ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" -#include - #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200 @@ -42,9 +40,9 @@ #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 -#define CONFIG_SYS_PROMPT "OMAP5432 uEVM # " - #define CONSOLEDEV "ttyO2" - #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 + +#include + #endif /* __CONFIG_OMAP5_EVM_H */ -- cgit v0.10.2 From 0fedc4a50748fb7688114383a43f28e96ce58579 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 9 Aug 2013 11:22:19 -0400 Subject: TI:armv7: Enable CONFIG_CMD_SPI Add the generic "poke the SPI bus" command, with the SPI related defines. Acked-by: Dan Murphy Signed-off-by: Tom Rini diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 525b867..6a65b4c 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -76,6 +76,7 @@ /* McSPI IP block */ #define CONFIG_SPI #define CONFIG_OMAP3_SPI +#define CONFIG_CMD_SPI /* GPIO block */ #define CONFIG_OMAP_GPIO -- cgit v0.10.2 From a1665ed1367ba6295b4794c0db25109b010cc88d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 9 Aug 2013 11:22:20 -0400 Subject: TI:armv7: Enable CONFIG_CMD_GPIO Add the generic "poke a GPIO" command, with the GPIO related defines. Acked-by: Dan Murphy Signed-off-by: Tom Rini diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 6a65b4c..e0ab691 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -80,6 +80,7 @@ /* GPIO block */ #define CONFIG_OMAP_GPIO +#define CONFIG_CMD_GPIO /* * GPMC NAND block. We support 1 device and the physical address to -- cgit v0.10.2 From 78056717e3a3216ff136ac8ce7e7355f593856e8 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 5 Aug 2013 16:00:35 +0200 Subject: arm/davinci/da850: add uart0_pins_rtscts and RMII_MHz_50_CLK in emac_pins_rmii pinmux Signed-off-by: Heiko Schocher Cc: Tom Rini diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c index f603f2f..6105f63 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c @@ -28,6 +28,11 @@ const struct pinmux_config uart0_pins_txrx[] = { { pinmux(3), 2, 5 }, /* UART0_TXD */ }; +const struct pinmux_config uart0_pins_rtscts[] = { + { pinmux(3), 2, 6 }, + { pinmux(3), 2, 7 }, +}; + const struct pinmux_config uart1_pins_txrx[] = { { pinmux(4), 2, 6 }, /* UART1_RXD */ { pinmux(4), 2, 7 }, /* UART1_TXD */ @@ -51,6 +56,7 @@ const struct pinmux_config emac_pins_rmii[] = { { pinmux(14), 8, 5 }, /* RMII_RXD[1] */ { pinmux(14), 8, 6 }, /* RMII_RXD[0] */ { pinmux(14), 8, 7 }, /* RMII_RXER */ + { pinmux(15), 0, 0 }, /* RMII_MHz_50_CLK */ { pinmux(15), 8, 1 }, /* RMII_CRS_DV */ }; diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h index 4d45799..2d82af5 100644 --- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h @@ -23,12 +23,13 @@ extern const struct pinmux_config spi1_pins_scs0[1]; /* UART pin muxer settings */ extern const struct pinmux_config uart0_pins_txrx[2]; +extern const struct pinmux_config uart0_pins_rtscts[2]; extern const struct pinmux_config uart1_pins_txrx[2]; extern const struct pinmux_config uart2_pins_txrx[2]; extern const struct pinmux_config uart2_pins_rtscts[2]; /* EMAC pin muxer settings*/ -extern const struct pinmux_config emac_pins_rmii[7]; +extern const struct pinmux_config emac_pins_rmii[8]; extern const struct pinmux_config emac_pins_rmii_clk_source[1]; extern const struct pinmux_config emac_pins_mii[15]; extern const struct pinmux_config emac_pins_mdio[2]; -- cgit v0.10.2 From 7f442e36f15789eb4924222f8922c924215d4c6c Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 5 Aug 2013 16:00:36 +0200 Subject: bootstage: get more BOOTSTAGE_ID* in show_boot_progress() In case CONFIG_BOOTSTAGE is not defined, call from bootstage_mark_name() show_boot_progress(), so get more BOOTSTAGE_ID* ids in show_boot_progress() if CONFIG_BOOTSTAGE is not defined. Signed-off-by: Heiko Schocher Cc: Simon Glass Cc: Tom Rini Cc: Albert Aribaud Acked-by: Simon Glass diff --git a/include/bootstage.h b/include/bootstage.h index 25b4e07..87bf906 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -353,6 +353,7 @@ static inline ulong bootstage_error(enum bootstage_id id) static inline ulong bootstage_mark_name(enum bootstage_id id, const char *name) { + show_boot_progress(id); return 0; } -- cgit v0.10.2 From 9c8deaeeb79523d45d836c730c59c857f53b5f65 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 5 Aug 2013 16:00:37 +0200 Subject: arm, da850: enable the correct uart in arch_cpu_init() in arch_cpu_init() uart2 is fix enabled, without reference the setting from CONFIG_SYS_NS16550_COM1. Use the setting from CONFIG_SYS_NS16550_COM1 for enabling the console. Signed-off-by: Heiko Schocher Cc: Albert ARIBAUD Cc: Tom Rini Cc: Christian Riesch diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index f6bf1ef..a3bbbb8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -299,7 +299,11 @@ int arch_cpu_init(void) */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), +#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) + &davinci_uart0_ctrl_regs->pwremu_mgmt); +#else &davinci_uart2_ctrl_regs->pwremu_mgmt); +#endif #if defined(CONFIG_SYS_DA850_DDR_INIT) da850_ddr_setup(); -- cgit v0.10.2 From 03efcb05054fb7da9ef5fc76244bfa40e2e2c4b5 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 5 Aug 2013 16:00:38 +0200 Subject: arm, da850: add ipam390 board support add the am1808 based ipam390 board from Barix. - 128MByte, DDR2, synchronous RAM 16bit databus to SDRAM interface - 128MByte, NAND Flash, 8bit databus to the NANDFlash Interface - Ethernet PHY Micrel KSZ8051R via RMII - Console on UART 0 - booting fron nand flash - spl falcon bootmode Signed-off-by: Heiko Schocher Cc: Tom Rini diff --git a/MAINTAINERS b/MAINTAINERS index 081cf96..ffa64c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -448,6 +448,7 @@ Heiko Schocher cam_enc_4xx davinci/ARM926EJS charon MPC5200 ids8247 MPC8247 + ipam390 davinci/ARM926EJS jupiter MPC5200 kmsupx5 MPC8321 mucmc52 MPC5200 diff --git a/board/Barix/ipam390/Makefile b/board/Barix/ipam390/Makefile new file mode 100644 index 0000000..c84ee05 --- /dev/null +++ b/board/Barix/ipam390/Makefile @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS += ipam390.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Barix/ipam390/README.ipam390 b/board/Barix/ipam390/README.ipam390 new file mode 100644 index 0000000..2d155a3 --- /dev/null +++ b/board/Barix/ipam390/README.ipam390 @@ -0,0 +1,229 @@ +Summary +======= +The README is for the boot procedure on the ipam390 board + +In the context of U-Boot, the board is booted in three stages. The initial +bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits +in the internal ROM. The RBL initializes the internal memory and then +depending on the exact board and pin configurations will initialize another +controller (such as NAND) to continue the boot process by loading +the secondary program loader (SPL). The SPL will initialize the system +further (some clocks, SDRAM). As on this board is used the falcon boot +mode, now 2 ways are possible depending on the GPIO 7_14 input pin, +connected with the "soft reset switch" + +If this pin is logical 1 (high level): +spl code starts the kernel image without delay + +If this pin is logical 0 (low level): +spl code starts the u-boot image + +AIS is an image format defined by TI for the images that are to be loaded +to memory by the RBL. The image is divided into a series of sections and +the image's entry point is specified. Each section comes with meta data +like the target address the section is to be copied to and the size of the +section, which is used by the RBL to load the image. At the end of the +image the RBL jumps to the image entry point. The AIS format allows for +other things such as programming the clocks and SDRAM if the header is +programmed for it. We do not take advantage of this and instead use SPL as +it allows for additional flexibility (run-time detect of board revision, +loading the next image from a different media, etc). + +Compilation +=========== +run "./MAKEALL ipam390" in the u-boot source tree. +Once this build completes you will have a u-boot.ais file that needs to +be written to the nand flash. + +Flashing the images to NAND +========================== +The AIS image can be written to NAND flash using the following commands. +Assuming that the network is configured and enabled and the u-boot.ais file +is tftp'able. + +U-Boot > print upd_uboot +upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize} +U-Boot > +U-Boot > run upd_uboot +Using DaVinci-EMAC device +TFTP from server 192.168.1.1; our IP address is 192.168.20.71 +Filename '/tftpboot/ipam390/u-boot.ais'. +Load address: 0xc0000000 +Loading: ################################## + 1.5 MiB/s +done +Bytes transferred = 493716 (78894 hex) + +NAND erase.part: device 0 offset 0x20000, size 0x160000 +Erasing at 0x160000 -- 100% complete. +OK + +NAND write: device 0 offset 0x20000, size 0x78894 + 493716 bytes written: OK +U-Boot > + +Recovery +======== + +In the case of a "bricked" board, you need to use the TI tools found +here[1] to create an uboot-uart-ais.bin file + +- cd to the u-boot source tree + +- compile the u-boot for the ipam390 board: +$ ./MAKEALL ipam390 + + -> Now we shall have u-boot.bin + +- Create u-boot-uart-ais.bin +$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini +ipam390-ais-uart.cfg -o ./uboot-uart-ais.bin ./u-boot.bin@0xC1080000; + +Note: The ipam390-ais-uart.cfg is found in the board directory +for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg + +- We can now run bootloader on IPAM390 via UART using the command below: + +$ mono ./slh_OMAP-L138.exe -waitForDevice -v -p /dev/tty.UC-232AC uboot-uart-ais.bin +NOTE: Do not cancel the command execution! The command takes 20+ seconds +to upload u-boot over serial and run it! +Outcome: +Waiting for the OMAP-L138... +(AIS Parse): Read magic word 0x41504954. +(AIS Parse): Waiting for BOOTME... (power on or reset target now) +(AIS Parse): BOOTME received! +(AIS Parse): Performing Start-Word Sync... +(AIS Parse): Performing Ping Opcode Sync... +(AIS Parse): Processing command 0: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 1: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 2: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 3: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 4: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 5: 0x58535901. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Loading section... +(AIS Parse): Loaded 326516-Byte section to address 0xC1080000. +(AIS Parse): Processing command 6: 0x58535906. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Performing jump and close... +(AIS Parse): AIS complete. Jump to address 0xC1080000. +(AIS Parse): Waiting for DONE... +(AIS Parse): Boot completed successfully. + +Operation completed successfully. + +Falcon Bootmode (boot linux without booting U-Boot) +=================================================== + +The Falcon Mode extends this way allowing to start the Linux kernel directly +from SPL. A new command is added to U-Boot to prepare the parameters that SPL +must pass to the kernel, using ATAGS or Device Tree. + +In normal mode, these parameters are generated each time before +loading the kernel, passing to Linux the address in memory where +the parameters can be read. +With Falcon Mode, this snapshot can be saved into persistent storage and SPL is +informed to load it before running the kernel. + +To boot the kernel, these steps under a Falcon-aware U-Boot are required: + +1. Boot the board into U-Boot. +Use the "spl export" command to generate the kernel parameters area or the DT. +U-Boot runs as when it boots the kernel, but stops before passing the control +to the kernel. + +Here the command sequence for the ipam390 board: +- load the linux kernel image into ram: + +U-Boot > nand read c0100000 2 200000 400000 + +NAND read: device 0 offset 0x200000, size 0x400000 + 4194304 bytes read: OK + +- generate the bootparms image: + +U-Boot > spl export atags c0100000 +## Booting kernel from Legacy Image at c0100000 ... + Image Name: Linux-3.5.1 + Image Type: ARM Linux Kernel Image (uncompressed) + Data Size: 2504280 Bytes = 2.4 MiB + Load Address: c0008000 + Entry Point: c0008000 + Verifying Checksum ... OK + Loading Kernel Image ... OK +subcommand not supported +subcommand not supported +Argument image is now in RAM at: 0xc0000100 + +- copy the bootparms image into nand: + +U-Boot > mtdparts + +device nand0 , # parts = 6 + #: name size offset mask_flags + 0: u-boot-env 0x00020000 0x00000000 0 + 1: u-boot 0x00160000 0x00020000 0 + 2: bootparms 0x00020000 0x00180000 0 + 3: factory-info 0x00060000 0x001a0000 0 + 4: kernel 0x00400000 0x00200000 0 + 5: rootfs 0x07a00000 0x00600000 0 + +active partition: nand0,0 - (u-boot-env) 0x00020000 @ 0x00000000 + +defaults: +mtdids : nand0=davinci_nand.0 +mtdparts: mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs) +U-Boot > nand erase.part bootparms + +NAND erase.part: device 0 offset 0x180000, size 0x20000 +Erasing at 0x180000 -- 100% complete. +OK +U-Boot > nand write c0000100 180000 20000 + +NAND write: device 0 offset 0x180000, size 0x20000 + 131072 bytes written: OK +U-Boot > + +You can use also the predefined U-Boot Environment variable "setbootparms", +which will do all the above steps in one command: + +U-Boot > print setbootparms +setbootparms=nand read c0100000 200000 400000;spl export atags c0100000;nand erase.part bootparms;nand write c0000100 180000 20000 +U-Boot > run setbootparms + +NAND read: device 0 offset 0x200000, size 0x400000 + 4194304 bytes read: OK +## Booting kernel from Legacy Image at c0100000 ... + Image Name: Linux-3.5.1 + Image Type: ARM Linux Kernel Image (uncompressed) + Data Size: 2504280 Bytes = 2.4 MiB + Load Address: c0008000 + Entry Point: c0008000 + Verifying Checksum ... OK + Loading Kernel Image ... OK +subcommand not supported +subcommand not supported +Argument image is now in RAM at: 0xc0000100 + +NAND erase.part: device 0 offset 0x180000, size 0x20000 +Erasing at 0x180000 -- 100% complete. +OK + +NAND write: device 0 offset 0x180000, size 0x20000 + 131072 bytes written: OK +U-Boot > + +Links +===== +[1] + http://sourceforge.net/projects/dvflashutils/files/OMAP-L138/ diff --git a/board/Barix/ipam390/ipam390-ais-uart.cfg b/board/Barix/ipam390/ipam390-ais-uart.cfg new file mode 100644 index 0000000..e1a99f2 --- /dev/null +++ b/board/Barix/ipam390/ipam390-ais-uart.cfg @@ -0,0 +1,202 @@ +; General settings that can be overwritten in the host code +; that calls the AISGen library. +[General] + +; Can be 8 or 16 - used in emifa +busWidth=8 + +; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW +BootMode=UART + +; 8,16,24 - used for SPI,I2C +;AddrWidth=8 + +; NO_CRC,SECTION_CRC,SINGLE_CRC +crcCheckType=NO_CRC + +; This section allows setting the PLL0 system clock with a +; specified multiplier and divider as shown. The clock source +; can also be chosen for internal or external. +; |------24|------16|-------8|-------0| +; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV| +; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7| +;[PLL0CONFIG] +;PLL0CFG0 = 0x00180001 +;PLL0CFG1 = 0x00000205 + +[PLLANDCLOCKCONFIG] +PLL0CFG0 = 0x00180001 +PLL0CFG1 = 0x00000205 +PERIPHCLKCFG = 0x00000051 + +; This section allows setting up the PLL1. Usually this will +; take place as part of the EMIF3a DDR setup. The format of +; the input args is as follows: +; |------24|------16|-------8|-------0| +; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| +; PLL1CFG1: | RSVD | PLLDIV3| +[PLL1CONFIG] +PLL1CFG0 = 0x18010001 +PLL1CFG1 = 0x00000002 + +; This section lets us configure the peripheral interface +; of the current booting peripheral (I2C, SPI, or UART). +; Use with caution. The format of the PERIPHCLKCFG field +; is as follows: +; SPI: |------24|------16|-------8|-------0| +; | RSVD |PRESCALE| +; +; I2C: |------24|------16|-------8|-------0| +; | RSVD |PRESCALE| CLKL | CLKH | +; +; UART: |------24|------16|-------8|-------0| +; | RSVD | OSR | DLH | DLL | +[PERIPHCLKCFG] +PERIPHCLKCFG = 0x00000051 + +; This section can be used to configure the PLL1 and the EMIF3a registers +; for starting the DDR2 interface. +; See PLL1CONFIG section for the format of the PLL1CFG fields. +; |------24|------16|-------8|-------0| +; PLL1CFG0: | PLL1CFG | +; PLL1CFG1: | PLL1CFG | +; DDRPHYC1R: | DDRPHYC1R | +; SDCR: | SDCR | +; SDTIMR: | SDTIMR | +; SDTIMR2: | SDTIMR2 | +; SDRCR: | SDRCR | +; CLK2XSRC: | CLK2XSRC | +[EMIF3DDR] +PLL1CFG0 = 0x18010001 +PLL1CFG1 = 0x00000002 +DDRPHYC1R = 0x000000C2 +SDCR = 0x0017C432 +SDTIMR = 0x26922A09 +SDTIMR2 = 0x4414C722 +SDRCR = 0x00000498 +CLK2XSRC = 0x00000000 + +; This section can be used to configure the EMIFA to use +; CS0 as an SDRAM interface. The fields required to do this +; are given below. +; |------24|------16|-------8|-------0| +; SDBCR: | SDBCR | +; SDTIMR: | SDTIMR | +; SDRSRPDEXIT: | SDRSRPDEXIT | +; SDRCR: | SDRCR | +; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE | +;[EMIF25SDRAM] +;SDBCR = 0x00004421 +;SDTIMR = 0x42215810 +;SDRSRPDEXIT = 0x00000009 +;SDRCR = 0x00000410 +;DIV4p5_CLK_ENABLE = 0x00000001 + +; This section can be used to configure the async chip selects +; of the EMIFA (CS2-CS5). The fields required to do this +; are given below. +; |------24|------16|-------8|-------0| +; A1CR: | A1CR | +; A2CR: | A2CR | +; A3CR: | A3CR | +; A4CR: | A4CR | +; NANDFCR: | NANDFCR | +;[EMIF25ASYNC] +;A1CR = 0x00000000 +;A2CR = 0x00000000 +;A3CR = 0x00000000 +;A4CR = 0x00000000 +;NANDFCR = 0x00000000 +[EMIF25ASYNC] +A1CR = 0x00000000 +A2CR = 0x3FFFFFFE +A3CR = 0x00000000 +A4CR = 0x00000000 +NANDFCR = 0x00000012 + +; This section should be used in place of PLL0CONFIG when +; the I2C, SPI, or UART modes are being used. This ensures that +; the system PLL and the peripheral's clocks are changed together. +; See PLL0CONFIG section for the format of the PLL0CFG fields. +; See PERIPHCLKCFG section for the format of the CLKCFG field. +; |------24|------16|-------8|-------0| +; PLL0CFG0: | PLL0CFG | +; PLL0CFG1: | PLL0CFG | +; PERIPHCLKCFG: | CLKCFG | +;[PLLANDCLOCKCONFIG] +;PLL0CFG0 = 0x00180001 +;PLL0CFG1 = 0x00000205 +;PERIPHCLKCFG = 0x00010032 + +; This section should be used to setup the power state of modules +; of the two PSCs. This section can be included multiple times to +; allow the configuration of any or all of the device modules. +; |------24|------16|-------8|-------0| +; LPSCCFG: | PSCNUM | MODULE | PD | STATE | +;[PSCCONFIG] +;LPSCCFG= + +; This section allows setting of a single PINMUX register. +; This section can be included multiple times to allow setting +; as many PINMUX registers as needed. +; |------24|------16|-------8|-------0| +; REGNUM: | regNum | +; MASK: | mask | +; VALUE: | value | +;[PINMUX] +;REGNUM = 5 +;MASK = 0x00FF0000 +;VALUE = 0x00880000 + +; No Params required - simply include this section for the fast boot +; function to be called +;[FASTBOOT] + +; This section allows setting up the PLL1. Usually this will +; take place as part of the EMIF3a DDR setup. The format of +; the input args is as follows: +; |------24|------16|-------8|-------0| +; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| +; PLL1CFG1: | RSVD | PLLDIV3| +;[PLL1CONFIG] +;PLL1CFG0 = 0x15010001 +;PLL1CFG1 = 0x00000002 + +; This section can be used to configure the PLL1 and the EMIF3a registers +; for starting the DDR2 interface on ARM-boot D800K002 devices. +; |------24|------16|-------8|-------0| +; DDRPHYC1R: | DDRPHYC1R | +; SDCR: | SDCR | +; SDTIMR: | SDTIMR | +; SDTIMR2: | SDTIMR2 | +; SDRCR: | SDRCR | +; CLK2XSRC: | CLK2XSRC | +;[ARM_EMIF3DDR_PATCHFXN] +;DDRPHYC1R = 0x000000C2 +;SDCR = 0x0017C432 +;SDTIMR = 0x26922A09 +;SDTIMR2 = 0x4414C722 +;SDRCR = 0x00000498 +;CLK2XSRC = 0x00000000 + +; This section can be used to configure the PLL1 and the EMIF3a registers +; for starting the DDR2 interface on DSP-boot D800K002 devices. +; |------24|------16|-------8|-------0| +; DDRPHYC1R: | DDRPHYC1R | +; SDCR: | SDCR | +; SDTIMR: | SDTIMR | +; SDTIMR2: | SDTIMR2 | +; SDRCR: | SDRCR | +; CLK2XSRC: | CLK2XSRC | +;[DSP_EMIF3DDR_PATCHFXN] +;DDRPHYC1R = 0x000000C4 +;SDCR = 0x08134632 +;SDTIMR = 0x26922A09 +;SDTIMR2 = 0x0014C722 +;SDRCR = 0x00000492 +;CLK2XSRC = 0x00000000 + +;[INPUTFILE] +;FILENAME=u-boot.bin +;LOADADDRESS=0xC1080000 +;ENTRYPOINTADDRESS=0xC1080000 diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c new file mode 100644 index 0000000..f3f276e --- /dev/null +++ b/board/Barix/ipam390/ipam390.c @@ -0,0 +1,348 @@ +/* + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * Based on: + * U-Boot:board/davinci/da8xxevm/da850evm.c + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on da830evm.c. Original Copyrights follow: + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. + * Copyright (C) 2007 Sergey Kubushyn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DRIVER_TI_EMAC +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII +#define HAS_RMII 1 +#else +#define HAS_RMII 0 +#endif +#endif /* CONFIG_DRIVER_TI_EMAC */ + +void dsp_lpsc_on(unsigned domain, unsigned int id) +{ + dv_reg_p mdstat, mdctl, ptstat, ptcmd; + struct davinci_psc_regs *psc_regs; + + psc_regs = davinci_psc0_regs; + mdstat = &psc_regs->psc0.mdstat[id]; + mdctl = &psc_regs->psc0.mdctl[id]; + ptstat = &psc_regs->ptstat; + ptcmd = &psc_regs->ptcmd; + + while (*ptstat & (0x1 << domain)) + ; + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + *ptcmd = 0x1 << domain; + + while (*ptstat & (0x1 << domain)) + ; + while ((*mdstat & 0x1f) != 0x03) + ; /* Probably an overkill... */ +} + +static void dspwake(void) +{ + unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; + u32 val; + + /* if the device is ARM only, return */ + if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) + return; + + if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) + return; + + *resetvect++ = 0x1E000; /* DSP Idle */ + /* clear out the next 10 words as NOP */ + memset(resetvect, 0, sizeof(unsigned) * 10); + + /* setup the DSP reset vector */ + writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); + + dsp_lpsc_on(1, DAVINCI_LPSC_GEM); + val = readl(PSC0_MDCTL + (15 * 4)); + val |= 0x100; + writel(val, (PSC0_MDCTL + (15 * 4))); +} + +int misc_init_r(void) +{ + dspwake(); + return 0; +} + +static const struct pinmux_config gpio_pins[] = { + /* GP7[14] selects bootmode*/ + { pinmux(16), 8, 3 }, /* GP7[14] */ +}; + +const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_DRIVER_TI_EMAC + PINMUX_ITEM(emac_pins_mdio), +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII + PINMUX_ITEM(emac_pins_rmii), +#else + PINMUX_ITEM(emac_pins_mii), +#endif +#endif + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), + PINMUX_ITEM(uart0_pins_txrx), + PINMUX_ITEM(uart0_pins_rtscts), +#ifdef CONFIG_NAND_DAVINCI + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_nand), +#endif + PINMUX_ITEM(gpio_pins), +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ + { DAVINCI_LPSC_EMAC }, /* image download */ + { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_UART0 }, /* console */ + { DAVINCI_LPSC_GPIO }, +}; + +const int lpsc_size = ARRAY_SIZE(lpsc); + +#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK +#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 +#endif + +#define REV_AM18X_EVM 0x100 + +/* + * get_board_rev() - setup to pass kernel board revision information + * Returns: + * bit[0-3] Maximum cpu clock rate supported by onboard SoC + * 0000b - 300 MHz + * 0001b - 372 MHz + * 0010b - 408 MHz + * 0011b - 456 MHz + */ +u32 get_board_rev(void) +{ + char *s; + u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; + u32 rev = 0; + + s = getenv("maxcpuclk"); + if (s) + maxcpuclk = simple_strtoul(s, NULL, 10); + + if (maxcpuclk >= 456000000) + rev = 3; + else if (maxcpuclk >= 408000000) + rev = 2; + else if (maxcpuclk >= 372000000) + rev = 1; +#ifdef CONFIG_DA850_AM18X_EVM + rev |= REV_AM18X_EVM; +#endif + return rev; +} + +int board_early_init_f(void) +{ + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return 1; + + return 0; +} + +int board_init(void) +{ +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* setup the SUSPSRC for ARM to control emulation suspend */ + writel(readl(&davinci_syscfg_regs->suspsrc) & + ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART0), + &davinci_syscfg_regs->suspsrc); + + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) + return 1; + +#ifdef CONFIG_DRIVER_TI_EMAC + davinci_emac_mii_mode_sel(HAS_RMII); +#endif /* CONFIG_DRIVER_TI_EMAC */ + + /* enable the console UART */ + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), +#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) + &davinci_uart0_ctrl_regs->pwremu_mgmt); +#else + &davinci_uart2_ctrl_regs->pwremu_mgmt); +#endif + return 0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ + +static int init_led(int gpio, char *name, int val) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) + return -1; + ret = gpio_direction_output(gpio, val); + if (ret) + return -1; + + return gpio; +} + +#define LED_ON 0 +#define LED_OFF 1 + +#if !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int status) +{ + static int red; + static int green; + + if (red == 0) + red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF); + if (red != CONFIG_IPAM390_GPIO_LED_RED) + return; + if (green == 0) + green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", + LED_OFF); + if (green != CONFIG_IPAM390_GPIO_LED_GREEN) + return; + + switch (status) { + case BOOTSTAGE_ID_RUN_OS: + /* + * set normal state + * LED Red : off + * LED green: off + */ + gpio_set_value(red, LED_OFF); + gpio_set_value(green, LED_OFF); + break; + case BOOTSTAGE_ID_MAIN_LOOP: + /* + * U-Boot operation + * LED Red : on + * LED green: on + */ + gpio_set_value(red, LED_ON); + gpio_set_value(green, LED_ON); + break; + } +} +#endif +#endif + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + int ret; + int bootmode = 0; + + /* + * GP7[14] selects bootmode: + * 1: boot linux + * 0: boot u-boot + * if error accessing gpio boot U-Boot + * + * SPL bootmode + * 0: boot linux + * 1: boot u-boot + */ + ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode"); + if (ret) + bootmode = 1; + if (!bootmode) { + ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE); + if (ret) + bootmode = 1; + } + if (!bootmode) + ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE); + if (!bootmode) + if (ret == 0) + bootmode = 1; + if (bootmode) { + /* + * Booting U-Boot + * LED Red : on + * LED green: off + */ + init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); + init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); + } else { + /* + * Booting Linux + * LED Red : off + * LED green: off + */ + init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF); + init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); + } + return bootmode; +} +#endif diff --git a/board/Barix/ipam390/u-boot-spl-ipam390.lds b/board/Barix/ipam390/u-boot-spl-ipam390.lds new file mode 100644 index 0000000..5480d1f --- /dev/null +++ b/board/Barix/ipam390/u-boot-spl-ipam390.lds @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_FOOTPRINT } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __start = .; + arch/arm/cpu/arm926ejs/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sram + + __image_copy_end = .; + _end = .; +} diff --git a/boards.cfg b/boards.cfg index 8d86a1b..60ecb31 100644 --- a/boards.cfg +++ b/boards.cfg @@ -140,6 +140,7 @@ pm9g45 arm arm926ejs pm9g45 ronetix portuxg20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20,PORTUXG20 stamp9g20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20 cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx +ipam390 arm arm926ejs ipam390 Barix davinci da830evm arm arm926ejs da8xxevm davinci davinci da850_am18xxevm arm arm926ejs da8xxevm davinci davinci da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 da850evm arm arm926ejs da8xxevm davinci davinci da850evm:MAC_ADDR_IN_SPIFLASH diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h new file mode 100644 index 0000000..82d4298 --- /dev/null +++ b/include/configs/ipam390.h @@ -0,0 +1,331 @@ +/* + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * Based on: + * U-Boot:include/configs/da850evm.h + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_BARIX_IPAM390 + +/* + * SoC Configuration + */ +#define CONFIG_MACH_DAVINCI_DA850_EVM +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_DA850_PLL_INIT +#define CONFIG_SYS_DA850_DDR_INIT +#define CONFIG_SYS_TEXT_BASE 0xc1080000 + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ + +/* memtest start addr */ +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) + +/* memtest will be run on 16MB */ +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024) + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ + +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ + DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2 | \ + DAVINCI_SYSCFG_SUSPSRC_UART0 | \ + DAVINCI_SYSCFG_SUSPSRC_EMAC) + +/* + * PLL configuration + */ +#define CONFIG_SYS_DV_CLKMODE 0 +#define CONFIG_SYS_DA850_PLL0_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 +#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 + +#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 + +#define CONFIG_SYS_DA850_PLL0_PLLM 24 +#define CONFIG_SYS_DA850_PLL1_PLLM 24 + +/* + * DDR2 memory configuration + */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT)) +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498 + +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004 +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020 + + +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ + (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WTR_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ + (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (2 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (2 << DV_DDR_SDCR_CL_SHIFT) | \ + (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(2) | \ + DAVINCI_ABCR_WSTROBE(2) | \ + DAVINCI_ABCR_WHOLD(1) | \ + DAVINCI_ABCR_RSETUP(1) | \ + DAVINCI_ABCR_RSTROBE(4) | \ + DAVINCI_ABCR_RHOLD(0) | \ + DAVINCI_ABCR_TA(1) | \ + DAVINCI_ABCR_ASIZE_8BIT) + + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ + +/* + * Flash & Environment + */ +#define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_NAND_CS 3 +#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CONFIG_SYS_NAND_MASK_CLE 0x10 +#define CONFIG_SYS_NAND_MASK_ALE 0x8 +#undef CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000 +#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ + CONFIG_SYS_NAND_U_BOOT_SIZE - \ + CONFIG_SYS_MALLOC_LEN - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_NAND_ECCPOS { \ + 24, 25, 26, 27, 28, \ + 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ + 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ + 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ + 59, 60, 61, 62, 63 } +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 10 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_LOAD + +/* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +/* + * U-Boot general configuration + */ +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_HWCONFIG /* enable hwconfig */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS \ + "mem=128M console=ttyS0,115200n8 root=/dev/mtdblock0p4 rw noinitrd ip=dhcp" +#define CONFIG_BOOTDELAY 3 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=dsp:wake=yes\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "setbootparms=nand read c0100000 200000 400000;" \ + "spl export atags c0100000;" \ + "nand erase.part bootparms;" \ + "nand write c0000100 180000 20000\0" \ + "\0" + +/* + * U-Boot commands + */ +#include +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY + +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + +#ifndef CONFIG_DRIVER_TI_EMAC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#endif + +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_LZO +#define CONFIG_RBTREE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +#define MTDIDS_NAME_STR "davinci_nand.0" +#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR +#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ + "128k(u-boot-env)," \ + "1408k(u-boot)," \ + "128k(bootparms)," \ + "384k(factory-info)," \ + "4M(kernel)," \ + "-(rootfs)" + +/* defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" +#define CONFIG_SPL_STACK 0x8001ff00 +#define CONFIG_SPL_TEXT_BASE 0x80000000 +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_MAX_FOOTPRINT 32768 + +/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +/* add FALCON boot mode */ +#define CONFIG_CMD_SPL +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 +#define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR +#define CONFIG_CMD_SPL_NAND_OFS 0x00180000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 + +/* GPIO support */ +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_DA8XX_GPIO +#define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14) + +#define CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11) +#define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12) + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 9ed6e41239e17c97d786219b5ffca4a8a118c71f Mon Sep 17 00:00:00 2001 From: TENART Antoine Date: Tue, 2 Jul 2013 12:05:58 +0200 Subject: Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 8f27507..b723e22 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -16,7 +16,7 @@ COBJS += cache_v7.o COBJS += cpu.o COBJS += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),) SOBJS += lowlevel_init.o endif diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index d54cf5e..1f84311 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -19,7 +19,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 #define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 -#elif defined(CONFIG_TI814X) +#elif defined(CONFIG_TI81XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #define SRAM_SCRATCH_SPACE_ADDR 0x4031B800 diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index bc976ba..181c818 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -57,7 +57,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ - defined(CONFIG_AM33XX) || defined(CONFIG_TI814X) || \ + defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX) || \ defined(CONFIG_AM43XX) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif @@ -73,7 +73,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(UART_LCRVAL, &com_port->lcr); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ - defined(CONFIG_TI814X) || defined(CONFIG_AM43XX) + defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); -- cgit v0.10.2 From dcf846d5dae75b81eccce46c577fd3957e73d474 Mon Sep 17 00:00:00 2001 From: TENART Antoine Date: Tue, 2 Jul 2013 12:05:59 +0200 Subject: Add TI816X support Signed-off-by: Antoine Tenart [trini: Fix warnings about vtp things in emif4.c, adapt AM43XX] Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index bd8e752..f6a297c 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -16,6 +16,7 @@ ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) COBJS += clock.o endif +COBJS-$(CONFIG_TI816X) += clock_ti816x.o COBJS += sys_info.o COBJS += mem.o COBJS += ddr.o diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index 93c7f7b..ef14f47 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -100,103 +100,8 @@ struct ad_pll { #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) -/* PRCM */ #define ENET_CLKCTRL_CMPL 0x30000 -#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) - -struct cm_def { - unsigned int resv0[2]; - unsigned int l3fastclkstctrl; - unsigned int resv1[1]; - unsigned int pciclkstctrl; - unsigned int resv2[1]; - unsigned int ducaticlkstctrl; - unsigned int resv3[1]; - unsigned int emif0clkctrl; - unsigned int emif1clkctrl; - unsigned int dmmclkctrl; - unsigned int fwclkctrl; - unsigned int resv4[10]; - unsigned int usbclkctrl; - unsigned int resv5[1]; - unsigned int sataclkctrl; - unsigned int resv6[4]; - unsigned int ducaticlkctrl; - unsigned int pciclkctrl; -}; - -#define CM_ALWON_BASE (PRCM_BASE + 0x1400) - -struct cm_alwon { - unsigned int l3slowclkstctrl; - unsigned int ethclkstctrl; - unsigned int l3medclkstctrl; - unsigned int mmu_clkstctrl; - unsigned int mmucfg_clkstctrl; - unsigned int ocmc0clkstctrl; - unsigned int vcpclkstctrl; - unsigned int mpuclkstctrl; - unsigned int sysclk4clkstctrl; - unsigned int sysclk5clkstctrl; - unsigned int sysclk6clkstctrl; - unsigned int rtcclkstctrl; - unsigned int l3fastclkstctrl; - unsigned int resv0[67]; - unsigned int mcasp0clkctrl; - unsigned int mcasp1clkctrl; - unsigned int mcasp2clkctrl; - unsigned int mcbspclkctrl; - unsigned int uart0clkctrl; - unsigned int uart1clkctrl; - unsigned int uart2clkctrl; - unsigned int gpio0clkctrl; - unsigned int gpio1clkctrl; - unsigned int i2c0clkctrl; - unsigned int i2c1clkctrl; - unsigned int mcasp345clkctrl; - unsigned int atlclkctrl; - unsigned int mlbclkctrl; - unsigned int pataclkctrl; - unsigned int resv1[1]; - unsigned int uart3clkctrl; - unsigned int uart4clkctrl; - unsigned int uart5clkctrl; - unsigned int wdtimerclkctrl; - unsigned int spiclkctrl; - unsigned int mailboxclkctrl; - unsigned int spinboxclkctrl; - unsigned int mmudataclkctrl; - unsigned int resv2[2]; - unsigned int mmucfgclkctrl; - unsigned int resv3[2]; - unsigned int ocmc0clkctrl; - unsigned int vcpclkctrl; - unsigned int resv4[2]; - unsigned int controlclkctrl; - unsigned int resv5[2]; - unsigned int gpmcclkctrl; - unsigned int ethernet0clkctrl; - unsigned int ethernet1clkctrl; - unsigned int mpuclkctrl; - unsigned int debugssclkctrl; - unsigned int l3clkctrl; - unsigned int l4hsclkctrl; - unsigned int l4lsclkctrl; - unsigned int rtcclkctrl; - unsigned int tpccclkctrl; - unsigned int tptc0clkctrl; - unsigned int tptc1clkctrl; - unsigned int tptc2clkctrl; - unsigned int tptc3clkctrl; - unsigned int resv7[4]; - unsigned int dcan01clkctrl; - unsigned int mmchs0clkctrl; - unsigned int mmchs1clkctrl; - unsigned int mmchs2clkctrl; - unsigned int custefuseclkctrl; -}; - #define SATA_PLL_BASE (CTRL_BASE + 0x0720) struct sata_pll { diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c new file mode 100644 index 0000000..ace4a5a --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c @@ -0,0 +1,445 @@ +/* + * clock_ti816x.c + * + * Clocks for TI816X based boards + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * Based on TI-PSP-04.00.02.14 : + * + * Copyright (C) 2009, Texas Instruments, Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define CM_PLL_BASE (CTRL_BASE + 0x0400) + +/* Main PLL */ +#define MAIN_N 64 +#define MAIN_P 0x1 +#define MAIN_INTFREQ1 0x8 +#define MAIN_FRACFREQ1 0x800000 +#define MAIN_MDIV1 0x2 +#define MAIN_INTFREQ2 0xE +#define MAIN_FRACFREQ2 0x0 +#define MAIN_MDIV2 0x1 +#define MAIN_INTFREQ3 0x8 +#define MAIN_FRACFREQ3 0xAAAAB0 +#define MAIN_MDIV3 0x3 +#define MAIN_INTFREQ4 0x9 +#define MAIN_FRACFREQ4 0x55554F +#define MAIN_MDIV4 0x3 +#define MAIN_INTFREQ5 0x9 +#define MAIN_FRACFREQ5 0x374BC6 +#define MAIN_MDIV5 0xC +#define MAIN_MDIV6 0x48 +#define MAIN_MDIV7 0x4 + +/* DDR PLL */ +#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x4 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x3 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */ +#define DDR_N 50 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x9 +#define DDR_FRACFREQ2 0x0 +#define DDR_MDIV2 0x19 +#define DDR_INTFREQ3 0x13 +#define DDR_FRACFREQ3 0x800000 +#define DDR_MDIV3 0x2 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#endif + +#define CONTROL_STATUS (CTRL_BASE + 0x40) +#define DDR_RCD (CTRL_BASE + 0x070C) +#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) +#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) +#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) + +#define INTCPS_SYSCONFIG 0x48200010 +#define CM_SYSCLK10_CLKSEL 0x48180324 + +struct cm_pll { + unsigned int mainpll_ctrl; /* offset 0x400 */ + unsigned int mainpll_pwd; + unsigned int mainpll_freq1; + unsigned int mainpll_div1; + unsigned int mainpll_freq2; + unsigned int mainpll_div2; + unsigned int mainpll_freq3; + unsigned int mainpll_div3; + unsigned int mainpll_freq4; + unsigned int mainpll_div4; + unsigned int mainpll_freq5; + unsigned int mainpll_div5; + unsigned int resv0[1]; + unsigned int mainpll_div6; + unsigned int resv1[1]; + unsigned int mainpll_div7; + unsigned int ddrpll_ctrl; /* offset 0x440 */ + unsigned int ddrpll_pwd; + unsigned int resv2[1]; + unsigned int ddrpll_div1; + unsigned int ddrpll_freq2; + unsigned int ddrpll_div2; + unsigned int ddrpll_freq3; + unsigned int ddrpll_div3; + unsigned int ddrpll_freq4; + unsigned int ddrpll_div4; + unsigned int ddrpll_freq5; + unsigned int ddrpll_div5; + unsigned int videopll_ctrl; /* offset 0x470 */ + unsigned int videopll_pwd; + unsigned int videopll_freq1; + unsigned int videopll_div1; + unsigned int videopll_freq2; + unsigned int videopll_div2; + unsigned int videopll_freq3; + unsigned int videopll_div3; + unsigned int resv3[4]; + unsigned int audiopll_ctrl; /* offset 0x4A0 */ + unsigned int audiopll_pwd; + unsigned int resv4[2]; + unsigned int audiopll_freq2; + unsigned int audiopll_div2; + unsigned int audiopll_freq3; + unsigned int audiopll_div3; + unsigned int audiopll_freq4; + unsigned int audiopll_div4; + unsigned int audiopll_freq5; + unsigned int audiopll_div5; +}; + +const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; +const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; +const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE; +const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + +void enable_dmm_clocks(void) +{ + writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); + writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); + writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); + + /* Wait for clocks to be active */ + while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) + ; + /* Wait for emif0 to be fully functional, including OCP */ + while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) + ; + /* Wait for emif1 to be fully functional, including OCP */ + while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) + ; + + writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); + /* Wait for dmm to be fully functional, including OCP */ + while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) + ; + + /* Enable Tiled Access */ + writel(0x80000000, DMM_PAT_BASE_ADDR); +} + +/* assume delay is aprox at least 1us */ +static void ddr_delay(int d) +{ + int i; + + /* + * read a control register. + * this is a bit more delay and cannot be optimized by the compiler + * assuming one read takes 200 cycles and A8 is runing 1 GHz + * somewhat conservative setting + */ + for (i = 0; i < 50*d; i++) + readl(CONTROL_STATUS); +} + +static void main_pll_init_ti816x(void) +{ + u32 main_pll_ctrl = 0; + + /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFFB; + main_pll_ctrl |= BIT(2); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Enable PLL by setting BIT3 in its ctrl reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFF7; + main_pll_ctrl |= BIT(3); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Write the values of N,P in the CTRL reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFF; + main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Power up clock1-7 */ + writel(0x0, &cmpll->mainpll_pwd); + + /* Program the freq and divider values for clock1-7 */ + writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), + &cmpll->mainpll_freq1); + writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), + &cmpll->mainpll_freq2); + writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), + &cmpll->mainpll_freq3); + writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), + &cmpll->mainpll_freq4); + writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), + &cmpll->mainpll_freq5); + writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5); + + writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6); + + writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7); + + /* Wait for PLL to lock */ + while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) + ; + + /* Put the PLL in normal mode, disable bypass */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFFB; + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); +} + +static void ddr_pll_bypass_ti816x(void) +{ + u32 ddr_pll_ctrl = 0; + + /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFFFFFFFB; + ddr_pll_ctrl |= BIT(2); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); +} + +static void ddr_pll_init_ti816x(void) +{ + u32 ddr_pll_ctrl = 0; + /* Enable PLL by setting BIT3 in its ctrl reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFFFFFFF7; + ddr_pll_ctrl |= BIT(3); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); + + /* Write the values of N,P in the CTRL reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFF; + ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); + + ddr_delay(10); + + /* Power up clock1-5 */ + writel(0x0, &cmpll->ddrpll_pwd); + + /* Program the freq and divider values for clock1-3 */ + writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), + &cmpll->ddrpll_freq2); + writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2); + writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); + ddr_delay(1); + writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + &cmpll->ddrpll_freq3); + ddr_delay(1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + &cmpll->ddrpll_freq3); + + ddr_delay(5); + + /* Wait for PLL to lock */ + while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) + ; + + /* Power up RCD */ + writel(BIT(0), DDR_RCD); +} + +static void peripheral_enable(void) +{ + /* Wake-up the l3_slow clock */ + writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); + + /* + * Note on Timers: + * There are 8 timers(0-7) out of which timer 0 is a secure timer. + * Timer 0 mux should not be changed + * + * To access the timer registers we need the to be + * enabled which is what we do in the first step + */ + + /* Enable timer1 */ + writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl); + /* Select timer1 clock to be CLKIN (27MHz) */ + writel(BIT(1), CM_TIMER1_CLKSEL); + + /* Wait for timer1 to be ON-ACTIVE */ + while (((readl(&cmalwon->l3slowclkstctrl) + & (0x80000<<1))>>20) != 1) + ; + /* Wait for timer1 to be enabled */ + while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0) + ; + /* Active posted mode */ + writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54)); + while (readl(DM_TIMER1_BASE + 0x10) & BIT(0)) + ; + /* Start timer1 */ + writel(BIT(0), (DM_TIMER1_BASE + 0x38)); + + /* eFuse */ + writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL); + while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN) + ; + + /* Enable gpio0 */ + writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl); + while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN) + ; + writel((BIT(8)), &cmalwon->gpio0clkctrl); + + /* Enable spi */ + writel(PRCM_MOD_EN, &cmalwon->spiclkctrl); + while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN) + ; + + /* Enable i2c0 */ + writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl); + while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN) + ; + + /* Enable ethernet0 */ + writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); + + /* Enable hsmmc */ + writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl); + while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN) + ; +} + +void setup_clocks_for_console(void) +{ + /* Fix ROM code bug - from TI-PSP-04.00.02.14 */ + writel(0x0, CM_SYSCLK10_CLKSEL); + + ddr_pll_bypass_ti816x(); + + /* Enable uart0-2 */ + writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); + while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl); + while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl); + while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN) + ; + while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) + ; +} + +void prcm_init(void) +{ + /* Enable the control */ + writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); + + main_pll_init_ti816x(); + ddr_pll_init_ti816x(); + + /* + * With clk freqs setup to desired values, + * enable the required peripherals + */ + peripheral_enable(); +} diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 21cefd4..59ad25c 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -40,9 +40,11 @@ void dram_init_banksize(void) static struct dmm_lisa_map_regs *hw_lisa_map_regs = (struct dmm_lisa_map_regs *)DMM_BASE; #endif +#ifndef CONFIG_TI816X static struct vtp_reg *vtpreg[2] = { (struct vtp_reg *)VTP0_CTRL_ADDR, (struct vtp_reg *)VTP1_CTRL_ADDR}; +#endif #ifdef CONFIG_AM33XX static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; #endif @@ -64,6 +66,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs) } #endif +#ifndef CONFIG_TI816X static void config_vtp(int nr) { writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, @@ -78,6 +81,7 @@ static void config_vtp(int nr) VTP_CTRL_READY) ; } +#endif void __weak ddr_pll_config(unsigned int ddrpll_m) { @@ -88,7 +92,9 @@ void config_ddr(unsigned int pll, unsigned int ioctrl, const struct emif_regs *regs, int nr) { ddr_pll_config(pll); +#ifndef CONFIG_TI816X config_vtp(nr); +#endif config_cmd_ctrl(ctrl, nr); config_ddr_data(data, nr); diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 0d4b9ae..519249e 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -13,6 +13,10 @@ #include +#ifdef CONFIG_TI81XX +#include +#endif + #define LDELAY 1000000 /*CM___CLKCTRL */ diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h new file mode 100644 index 0000000..f069922 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h @@ -0,0 +1,142 @@ +/* + * ti81xx.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef _CLOCK_TI81XX_H_ +#define _CLOCK_TI81XX_H_ + +#define PRCM_MOD_EN 0x2 + +#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) +#define CM_ALWON_BASE (PRCM_BASE + 0x1400) + +struct cm_def { + unsigned int resv0[2]; + unsigned int l3fastclkstctrl; + unsigned int resv1[1]; + unsigned int pciclkstctrl; + unsigned int resv2[1]; + unsigned int ducaticlkstctrl; + unsigned int resv3[1]; + unsigned int emif0clkctrl; + unsigned int emif1clkctrl; + unsigned int dmmclkctrl; + unsigned int fwclkctrl; + unsigned int resv4[10]; + unsigned int usbclkctrl; + unsigned int resv5[1]; + unsigned int sataclkctrl; + unsigned int resv6[4]; + unsigned int ducaticlkctrl; + unsigned int pciclkctrl; +}; + +struct cm_alwon { + unsigned int l3slowclkstctrl; + unsigned int ethclkstctrl; + unsigned int l3medclkstctrl; + unsigned int mmu_clkstctrl; + unsigned int mmucfg_clkstctrl; + unsigned int ocmc0clkstctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkstctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkstctrl; +#endif + unsigned int mpuclkstctrl; + unsigned int sysclk4clkstctrl; + unsigned int sysclk5clkstctrl; + unsigned int sysclk6clkstctrl; + unsigned int rtcclkstctrl; + unsigned int l3fastclkstctrl; + unsigned int resv0[67]; + unsigned int mcasp0clkctrl; + unsigned int mcasp1clkctrl; + unsigned int mcasp2clkctrl; + unsigned int mcbspclkctrl; + unsigned int uart0clkctrl; + unsigned int uart1clkctrl; + unsigned int uart2clkctrl; + unsigned int gpio0clkctrl; + unsigned int gpio1clkctrl; + unsigned int i2c0clkctrl; + unsigned int i2c1clkctrl; +#if defined(CONFIG_TI814X) + unsigned int mcasp345clkctrl; + unsigned int atlclkctrl; + unsigned int mlbclkctrl; + unsigned int pataclkctrl; + unsigned int resv1[1]; + unsigned int uart3clkctrl; + unsigned int uart4clkctrl; + unsigned int uart5clkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv1[1]; + unsigned int timer1clkctrl; + unsigned int timer2clkctrl; + unsigned int timer3clkctrl; + unsigned int timer4clkctrl; + unsigned int timer5clkctrl; + unsigned int timer6clkctrl; + unsigned int timer7clkctrl; +#endif + unsigned int wdtimerclkctrl; + unsigned int spiclkctrl; + unsigned int mailboxclkctrl; + unsigned int spinboxclkctrl; + unsigned int mmudataclkctrl; + unsigned int resv2[2]; + unsigned int mmucfgclkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv3[2]; +#elif defined(CONFIG_TI816X) + unsigned int resv3[1]; + unsigned int sdioclkctrl; +#endif + unsigned int ocmc0clkctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkctrl; +#endif + unsigned int resv4[2]; + unsigned int controlclkctrl; + unsigned int resv5[2]; + unsigned int gpmcclkctrl; + unsigned int ethernet0clkctrl; + unsigned int ethernet1clkctrl; + unsigned int mpuclkctrl; +#if defined(CONFIG_TI814X) + unsigned int debugssclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv6[1]; +#endif + unsigned int l3clkctrl; + unsigned int l4hsclkctrl; + unsigned int l4lsclkctrl; + unsigned int rtcclkctrl; + unsigned int tpccclkctrl; + unsigned int tptc0clkctrl; + unsigned int tptc1clkctrl; + unsigned int tptc2clkctrl; + unsigned int tptc3clkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv6[4]; + unsigned int dcan01clkctrl; + unsigned int mmchs0clkctrl; + unsigned int mmchs1clkctrl; + unsigned int mmchs2clkctrl; + unsigned int custefuseclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int sr0clkctrl; + unsigned int sr1clkctrl; +#endif +}; + +#endif /* _CLOCK_TI81XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 18d7d99..95f7a9a 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -192,37 +192,46 @@ struct ddr_data_regs { * correspond to DATA1 registers defined here. */ struct ddr_regs { - unsigned int resv0[7]; - unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv0[3]; + unsigned int cm0config; /* offset 0x00C */ + unsigned int cm0configclk; /* offset 0x010 */ unsigned int resv1[2]; + unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv2[2]; unsigned int cm0dldiff; /* offset 0x028 */ unsigned int cm0iclkout; /* offset 0x02C */ - unsigned int resv2[8]; + unsigned int resv3[4]; + unsigned int cm1config; /* offset 0x040 */ + unsigned int cm1configclk; /* offset 0x044 */ + unsigned int resv4[2]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv3[2]; + unsigned int resv5[2]; unsigned int cm1dldiff; /* offset 0x05C */ unsigned int cm1iclkout; /* offset 0x060 */ - unsigned int resv4[8]; + unsigned int resv6[4]; + unsigned int cm2config; /* offset 0x074 */ + unsigned int cm2configclk; /* offset 0x078 */ + unsigned int resv7[2]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv5[2]; + unsigned int resv8[2]; unsigned int cm2dldiff; /* offset 0x090 */ unsigned int cm2iclkout; /* offset 0x094 */ - unsigned int resv6[12]; + unsigned int resv9[12]; unsigned int dt0rdsratio0; /* offset 0x0C8 */ - unsigned int resv7[4]; + unsigned int resv10[4]; unsigned int dt0wdsratio0; /* offset 0x0DC */ - unsigned int resv8[4]; + unsigned int resv11[4]; unsigned int dt0wiratio0; /* offset 0x0F0 */ - unsigned int resv9; + unsigned int resv12; unsigned int dt0wimode0; /* offset 0x0F8 */ unsigned int dt0giratio0; /* offset 0x0FC */ - unsigned int resv10; + unsigned int resv13; unsigned int dt0gimode0; /* offset 0x104 */ unsigned int dt0fwsratio0; /* offset 0x108 */ - unsigned int resv11[4]; + unsigned int resv14[4]; unsigned int dt0dqoffset; /* offset 0x11C */ unsigned int dt0wrsratio0; /* offset 0x120 */ - unsigned int resv12[4]; + unsigned int resv15[4]; unsigned int dt0rdelays0; /* offset 0x134 */ unsigned int dt0dldiff0; /* offset 0x138 */ }; diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index fa0bbda..2055b25 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -15,6 +15,8 @@ #include #ifdef CONFIG_AM33XX #include +#elif defined(CONFIG_TI816X) +#include #elif defined(CONFIG_TI814X) #include #elif defined(CONFIG_AM43XX) @@ -53,21 +55,13 @@ #define CM_CEFUSE 0x44E00A00 #define PRM_DEVICE 0x44E00F00 -/* VTP Base address */ -#define VTP1_CTRL_ADDR 0x48140E10 - /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 /* UART */ #define DEFAULT_UART_BASE UART0_BASE -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - /* GPMC Base address */ #define GPMC_BASE 0x50000000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index 5297c63..8973fd8 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -36,12 +36,18 @@ /* VTP Base address */ #define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 #define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 2 +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + /* CPSW Config space */ #define CPSW_MDIO_BASE 0x4A101000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index d4d5c41..303c594 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -36,10 +36,13 @@ /* VTP Base address */ #define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 #define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 2 /* CPSW Config space */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index 1ad8cb1..4509a23 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -36,12 +36,18 @@ /* VTP Base address */ #define VTP0_CTRL_ADDR 0x48140E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x47C0C400 #define DDR_PHY_DATA_ADDR 0x47C0C4C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 4 +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + /* CPSW Config space */ #define CPSW_MDIO_BASE 0x4A100800 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h new file mode 100644 index 0000000..3c68064 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h @@ -0,0 +1,61 @@ +/* + * hardware_ti816x.h + * + * TI816x hardware specific header + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * Based on TI-PSP-04.00.02.14 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AM33XX_HARDWARE_TI816X_H +#define __AM33XX_HARDWARE_TI816X_H + +/* UART */ +#define UART0_BASE 0x48020000 +#define UART1_BASE 0x48022000 +#define UART2_BASE 0x48024000 + +/* Watchdog Timer */ +#define WDT_BASE 0x480C2000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x48140000 + +/* PRCM Base Address */ +#define PRCM_BASE 0x48180000 + +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) +#define PRM_RSTST (PRM_RSTCTRL + 8) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x48198358 +#define VTP1_CTRL_ADDR 0x4819A358 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x48198000 +#define DDR_PHY_DATA_ADDR 0x481980C8 +#define DDR_PHY_CMD_ADDR2 0x4819A000 +#define DDR_PHY_DATA_ADDR2 0x4819A0C8 +#define DDR_DATA_REGS_NR 4 + + +#define DDRPHY_0_CONFIG_BASE 0x48198000 +#define DDRPHY_1_CONFIG_BASE 0x4819A000 +#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ + DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) + +/* RTC base address */ +#define RTC_BASE 0x480C0000 + +#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 51ba791..724e252 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -27,6 +27,9 @@ #if defined(CONFIG_TI814X) #undef MMC_CLOCK_REFERENCE #define MMC_CLOCK_REFERENCE 192 /* MHz */ +#elif defined(CONFIG_TI816X) +#undef MMC_CLOCK_REFERENCE +#define MMC_CLOCK_REFERENCE 48 /* MHz */ #endif #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index f760d84..3249437 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -23,6 +23,8 @@ #include #elif defined(CONFIG_TI814X) #include +#elif defined(CONFIG_TI816X) +#include #elif defined(CONFIG_AM43XX) #include #endif diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h new file mode 100644 index 0000000..e4e5a48 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h @@ -0,0 +1,363 @@ +/* + * mux_ti816x.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_TI816X_H_ +#define _MUX_TI816X_H_ + +#include +#include + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) /* used for Readability */ + + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int pincntl1; + int pincntl2; + int pincntl3; + int pincntl4; + int pincntl5; + int pincntl6; + int pincntl7; + int pincntl8; + int pincntl9; + int pincntl10; + int pincntl11; + int pincntl12; + int pincntl13; + int pincntl14; + int pincntl15; + int pincntl16; + int pincntl17; + int pincntl18; + int pincntl19; + int pincntl20; + int pincntl21; + int pincntl22; + int pincntl23; + int pincntl24; + int pincntl25; + int pincntl26; + int pincntl27; + int pincntl28; + int pincntl29; + int pincntl30; + int pincntl31; + int pincntl32; + int pincntl33; + int pincntl34; + int pincntl35; + int pincntl36; + int pincntl37; + int pincntl38; + int pincntl39; + int pincntl40; + int pincntl41; + int pincntl42; + int pincntl43; + int pincntl44; + int pincntl45; + int pincntl46; + int pincntl47; + int pincntl48; + int pincntl49; + int pincntl50; + int pincntl51; + int pincntl52; + int pincntl53; + int pincntl54; + int pincntl55; + int pincntl56; + int pincntl57; + int pincntl58; + int pincntl59; + int pincntl60; + int pincntl61; + int pincntl62; + int pincntl63; + int pincntl64; + int pincntl65; + int pincntl66; + int pincntl67; + int pincntl68; + int pincntl69; + int pincntl70; + int pincntl71; + int pincntl72; + int pincntl73; + int pincntl74; + int pincntl75; + int pincntl76; + int pincntl77; + int pincntl78; + int pincntl79; + int pincntl80; + int pincntl81; + int pincntl82; + int pincntl83; + int pincntl84; + int pincntl85; + int pincntl86; + int pincntl87; + int pincntl88; + int pincntl89; + int pincntl90; + int pincntl91; + int pincntl92; + int pincntl93; + int pincntl94; + int pincntl95; + int pincntl96; + int pincntl97; + int pincntl98; + int pincntl99; + int pincntl100; + int pincntl101; + int pincntl102; + int pincntl103; + int pincntl104; + int pincntl105; + int pincntl106; + int pincntl107; + int pincntl108; + int pincntl109; + int pincntl110; + int pincntl111; + int pincntl112; + int pincntl113; + int pincntl114; + int pincntl115; + int pincntl116; + int pincntl117; + int pincntl118; + int pincntl119; + int pincntl120; + int pincntl121; + int pincntl122; + int pincntl123; + int pincntl124; + int pincntl125; + int pincntl126; + int pincntl127; + int pincntl128; + int pincntl129; + int pincntl130; + int pincntl131; + int pincntl132; + int pincntl133; + int pincntl134; + int pincntl135; + int pincntl136; + int pincntl137; + int pincntl138; + int pincntl139; + int pincntl140; + int pincntl141; + int pincntl142; + int pincntl143; + int pincntl144; + int pincntl145; + int pincntl146; + int pincntl147; + int pincntl148; + int pincntl149; + int pincntl150; + int pincntl151; + int pincntl152; + int pincntl153; + int pincntl154; + int pincntl155; + int pincntl156; + int pincntl157; + int pincntl158; + int pincntl159; + int pincntl160; + int pincntl161; + int pincntl162; + int pincntl163; + int pincntl164; + int pincntl165; + int pincntl166; + int pincntl167; + int pincntl168; + int pincntl169; + int pincntl170; + int pincntl171; + int pincntl172; + int pincntl173; + int pincntl174; + int pincntl175; + int pincntl176; + int pincntl177; + int pincntl178; + int pincntl179; + int pincntl180; + int pincntl181; + int pincntl182; + int pincntl183; + int pincntl184; + int pincntl185; + int pincntl186; + int pincntl187; + int pincntl188; + int pincntl189; + int pincntl190; + int pincntl191; + int pincntl192; + int pincntl193; + int pincntl194; + int pincntl195; + int pincntl196; + int pincntl197; + int pincntl198; + int pincntl199; + int pincntl200; + int pincntl201; + int pincntl202; + int pincntl203; + int pincntl204; + int pincntl205; + int pincntl206; + int pincntl207; + int pincntl208; + int pincntl209; + int pincntl210; + int pincntl211; + int pincntl212; + int pincntl213; + int pincntl214; + int pincntl215; + int pincntl216; + int pincntl217; + int pincntl218; + int pincntl219; + int pincntl220; + int pincntl221; + int pincntl222; + int pincntl223; + int pincntl224; + int pincntl225; + int pincntl226; + int pincntl227; + int pincntl228; + int pincntl229; + int pincntl230; + int pincntl231; + int pincntl232; + int pincntl233; + int pincntl234; + int pincntl235; + int pincntl236; + int pincntl237; + int pincntl238; + int pincntl239; + int pincntl240; + int pincntl241; + int pincntl242; + int pincntl243; + int pincntl244; + int pincntl245; + int pincntl246; + int pincntl247; + int pincntl248; + int pincntl249; + int pincntl250; + int pincntl251; + int pincntl252; + int pincntl253; + int pincntl254; + int pincntl255; + int pincntl256; + int pincntl257; + int pincntl258; + int pincntl259; + int pincntl260; + int pincntl261; + int pincntl262; + int pincntl263; + int pincntl264; + int pincntl265; + int pincntl266; + int pincntl267; + int pincntl268; + int pincntl269; + int pincntl270; + int pincntl271; + int pincntl272; + int pincntl273; + int pincntl274; + int pincntl275; + int pincntl276; + int pincntl277; + int pincntl278; + int pincntl279; + int pincntl280; + int pincntl281; + int pincntl282; + int pincntl283; + int pincntl284; + int pincntl285; + int pincntl286; + int pincntl287; + int pincntl288; + int pincntl289; + int pincntl290; + int pincntl291; + int pincntl292; + int pincntl293; + int pincntl294; + int pincntl295; + int pincntl296; + int pincntl297; + int pincntl298; + int pincntl299; + int pincntl300; + int pincntl301; + int pincntl302; + int pincntl303; + int pincntl304; + int pincntl305; + int pincntl306; + int pincntl307; + int pincntl308; + int pincntl309; + int pincntl310; + int pincntl311; + int pincntl312; + int pincntl313; + int pincntl314; + int pincntl315; + int pincntl316; + int pincntl317; + int pincntl318; + int pincntl319; + int pincntl320; + int pincntl321; + int pincntl322; + int pincntl323; +}; + +#endif /* endif _MUX_TI816X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 570f45c..95de9aa 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -7,6 +7,14 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_SPL_H_ +#if defined(CONFIG_TI816X) +#define BOOT_DEVICE_XIP 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_MMC1 6 +#define BOOT_DEVICE_MMC2 5 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_MMC2_2 0xFF +#else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) @@ -21,11 +29,12 @@ #define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF +#endif #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 -#elif defined(CONFIG_TI814X) +#elif defined(CONFIG_TI81XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 #endif -- cgit v0.10.2 From 425faf74cd8189c87919f7e72a0101c684ee3b9f Mon Sep 17 00:00:00 2001 From: TENART Antoine Date: Tue, 2 Jul 2013 12:06:00 +0200 Subject: Add TI816X evm board support Signed-off-by: Antoine Tenart [trini: Change to SPDX, fix a few compiler warnings, adapt to CONFIG_OMAP_COMMON] Signed-off-by: Tom Rini diff --git a/MAINTAINERS b/MAINTAINERS index ffa64c9..4033b88 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -945,6 +945,10 @@ Lucas Stach colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core) +Antoine Tenart + + TI816X ARM ARMV7 (TI816x Soc) + Nick Thompson da830evm ARM926EJS (DA830/OMAP-L137) diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile new file mode 100644 index 0000000..17ce72a --- /dev/null +++ b/board/ti/ti816x/Makefile @@ -0,0 +1,37 @@ +# +# Copyright (C) 2013, Adeneo Embedded +# Antoine Tenart, +# +# Based on TI-PSP-04.00.02.14 : +# +# Copyright (C) 2009, Texas Instruments, Incorporated +# +# SPDX-License-Identifier: GPL-2.0 +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := evm.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c new file mode 100644 index 0000000..74d35e9 --- /dev/null +++ b/board/ti/ti816x/evm.c @@ -0,0 +1,229 @@ +/* + * evm.c + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +static struct module_pin_mux mmc_pin_mux[] = { + { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) }, + { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { -1 }, +}; + +const struct dmm_lisa_map_regs evm_lisa_map_regs = { + .dmm_lisa_map_0 = 0x00000000, + .dmm_lisa_map_1 = 0x00000000, + .dmm_lisa_map_2 = 0x80640300, + .dmm_lisa_map_3 = 0xC0640320, +}; + +/* + * DDR2 related definitions + */ +#ifdef CONFIG_TI816X_EVM_DDR2 +static struct ddr_data ddr2_data = { + .datardsratio0 = ((0x40<<10) | (0x40<<0)), + .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)), + .datawiratio0 = ((0x0<<10) | (0x0<<0)), + .datagiratio0 = ((0x0<<10) | (0x0<<0)), + .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)), + .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)), + .datauserank0delay = 0x1, + .datadldiff0 = 0x0, /* depend on cpu rev, set later */ +}; + +static struct cmd_control ddr2_ctrl = { + .cmd0csratio = 0x80, + .cmd0dldiff = 0x04, /* reset value is 0x4 */ + .cmd0iclkout = 0x00, + + .cmd1csratio = 0x80, + .cmd1dldiff = 0x04, /* reset value is 0x4 */ + .cmd1iclkout = 0x00, + + .cmd2csratio = 0x80, + .cmd2dldiff = 0x04, /* reset value is 0x4 */ + .cmd2iclkout = 0x00, + +}; + +static struct emif_regs ddr2_emif0_regs = { + .sdram_config = 0x43801A3A, + .ref_ctrl = 0x10000C30, + .sdram_tim1 = 0x0AAB15E2, + .sdram_tim2 = 0x423631D2, + .sdram_tim3 = 0x0080032F, + .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ +}; + +static struct emif_regs ddr2_emif1_regs = { + .sdram_config = 0x43801A3A, + .ref_ctrl = 0x10000C30, + .sdram_tim1 = 0x0AAB15E2, + .sdram_tim2 = 0x423631D2, + .sdram_tim3 = 0x0080032F, + .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ +}; +#endif + +/* + * DDR3 related definitions + */ + +#if defined(CONFIG_TI816X_DDR_PLL_400) +#define RD_DQS 0x03B +#define WR_DQS 0x0A6 +#define RD_DQS_GATE 0x12A +#define EMIF_SDCFG 0x62A41032 +#define EMIF_SDREF 0x10000C30 +#define EMIF_TIM1 0x0CCCE524 +#define EMIF_TIM2 0x30308023 +#define EMIF_TIM3 0x009F82CF +#define EMIF_PHYCFG 0x0000010B +#elif defined(CONFIG_TI816X_DDR_PLL_531) +#define RD_DQS 0x039 +#define WR_DQS 0x0B4 +#define RD_DQS_GATE 0x13D +#define EMIF_SDCFG 0x62A51832 +#define EMIF_SDREF 0x1000102E +#define EMIF_TIM1 0x0EF136AC +#define EMIF_TIM2 0x30408063 +#define EMIF_TIM3 0x009F83AF +#define EMIF_PHYCFG 0x0000010C +#elif defined(CONFIG_TI816X_DDR_PLL_675) +#define RD_DQS 0x039 +#define WR_DQS 0x091 +#define RD_DQS_GATE 0x196 +#define EMIF_SDCFG 0x62A63032 +#define EMIF_SDREF 0x10001491 +#define EMIF_TIM1 0x13358875 +#define EMIF_TIM2 0x5051806C +#define EMIF_TIM3 0x009F84AF +#define EMIF_PHYCFG 0x0000010F +#elif defined(CONFIG_TI816X_DDR_PLL_796) +#define RD_DQS 0x035 +#define WR_DQS 0x093 +#define RD_DQS_GATE 0x1B3 +#define EMIF_SDCFG 0x62A73832 +#define EMIF_SDREF 0x10001841 +#define EMIF_TIM1 0x1779C9FE +#define EMIF_TIM2 0x50608074 +#define EMIF_TIM3 0x009F857F +#define EMIF_PHYCFG 0x00000110 +#endif + +static struct ddr_data ddr3_data = { + .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), + .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), + .datawiratio0 = ((0x20<<10) | 0x20<<0), + .datagiratio0 = ((0x20<<10) | 0x20<<0), + .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), + .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), + .datauserank0delay = 0x1, + .datadldiff0 = 0x0, /* depend on cpu rev, set later */ +}; + +static const struct cmd_control ddr3_ctrl = { + .cmd0csratio = 0x100, + .cmd0dldiff = 0x004, /* reset value is 0x4 */ + .cmd0iclkout = 0x001, + + .cmd1csratio = 0x100, + .cmd1dldiff = 0x004, /* reset value is 0x4 */ + .cmd1iclkout = 0x001, + + .cmd2csratio = 0x100, + .cmd2dldiff = 0x004, /* reset value is 0x4 */ + .cmd2iclkout = 0x001, +}; + +static const struct emif_regs ddr3_emif0_regs = { + .sdram_config = EMIF_SDCFG, + .ref_ctrl = EMIF_SDREF, + .sdram_tim1 = EMIF_TIM1, + .sdram_tim2 = EMIF_TIM2, + .sdram_tim3 = EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +}; + +static const struct emif_regs ddr3_emif1_regs = { + .sdram_config = EMIF_SDCFG, + .ref_ctrl = EMIF_SDREF, + .sdram_tim1 = EMIF_TIM1, + .sdram_tim2 = EMIF_TIM2, + .sdram_tim3 = EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +}; + +void set_uart_mux_conf(void) {} + +void set_mux_conf_regs(void) +{ + configure_module_pin_mux(mmc_pin_mux); +} + +void sdram_init(void) +{ + config_dmm(&evm_lisa_map_regs); + +#ifdef CONFIG_TI816X_EVM_DDR2 + ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + + if (CONFIG_TI816X_USE_EMIF0) { + ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = + (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); + config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0); + } + + if (CONFIG_TI816X_USE_EMIF1) { + ddr2_emif1_regs.emif_ddr_phy_ctlr_1 = + (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); + config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1); + } +#endif + +#ifdef CONFIG_TI816X_EVM_DDR3 + ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + + if (CONFIG_TI816X_USE_EMIF0) + config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0); + + if (CONFIG_TI816X_USE_EMIF1) + config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1); +#endif +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/boards.cfg b/boards.cfg index 60ecb31..15ff800 100644 --- a/boards.cfg +++ b/boards.cfg @@ -255,6 +255,7 @@ am335x_evm_usbspl arm armv7 am335x ti am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT am43xx_evm arm armv7 am43xx ti am33xx am43xx_evm:SERIAL1,CONS_INDEX=1 ti814x_evm arm armv7 ti814x ti am33xx +ti816x_evm arm armv7 ti816x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC sama5d3xek_nandflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h new file mode 100644 index 0000000..e90490c --- /dev/null +++ b/include/configs/ti816x_evm.h @@ -0,0 +1,180 @@ +/* + * ti816x_evm.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TI816X_EVM_H +#define __CONFIG_TI816X_EVM_H + +#define CONFIG_TI81XX +#define CONFIG_TI816X +#define CONFIG_SYS_NO_FLASH +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON + +#define CONFIG_ARCH_CPU_INIT + +#include + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) +#define CONFIG_SYS_LONGHELP /* undef save memory */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "u-boot/ti816x# " +#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG /* required for ramdisk support */ + +#include /* u-boot default commands */ + +#define CONFIG_VERSION_VARIABLE +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x81000000\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan;" \ + "fatload mmc 0 ${loadaddr} uImage;" \ + "bootm ${loadaddr}" \ + +#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ + +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +#define CONFIG_CMD_ASKEN +#define CONFIG_CMD_ECHO +#define CONFIG_OMAP_GPIO +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_FS_FAT + +/* + * Only one of the following two options (DDR3/DDR2) should be enabled + * CONFIG_TI816X_EVM_DDR2 + * CONFIG_TI816X_EVM_DDR3 + */ +#define CONFIG_TI816X_EVM_DDR3 + +/* + * Supported values: 400, 531, 675 or 796 MHz + */ +#define CONFIG_TI816X_DDR_PLL_796 + +#define CONFIG_TI816X_USE_EMIF0 1 +#define CONFIG_TI816X_USE_EMIF1 1 + + +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ +#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ + +#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/** + * Platform/Board specific defs + */ +#define CONFIG_SYS_CLK_FREQ 27000000 +#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +#undef CONFIG_NAND_OMAP_GPMC + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ + +#define CONFIG_BAUDRATE 115200 + +/* allow overwriting serial config and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SERIAL1 +#define CONFIG_SERIAL2 +#define CONFIG_SERIAL3 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +#define CONFIG_ENV_IS_NOWHERE + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40400000 +#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#endif -- cgit v0.10.2