From 12a11a405781bdb817091192f66b82c8fe35ae08 Mon Sep 17 00:00:00 2001
From: vojo <joris.van.vossen@sintecs.nl>
Date: Tue, 12 Sep 2017 11:08:00 +0200
Subject: T2081 initial support and minor fixes


diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index b770a6a..fd907de 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -444,11 +444,11 @@ config PPC_T1042
 	depends on TARGET_SIMC_TXXXX
 	select ARCH_T1042
 
-#config PPC_T2081
-#	bool
-#	prompt "T2081"
-#	depends on TARGET_SIMC_TXXXX
-#	select ARCH_T2081
+config PPC_T2081
+	bool
+	prompt "T2081"
+	depends on TARGET_SIMC_TXXXX
+	select ARCH_T2081
 endchoice	
 
 config ARCH_B4420
diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig
index 4ac5c59..a82d91d 100644
--- a/board/scalys/simc-t10xx/Kconfig
+++ b/board/scalys/simc-t10xx/Kconfig
@@ -1,4 +1,4 @@
-if (TARGET_SIMC_TXXXX || TARGET_QT1040_1GB) && !ARCH_T2081
+if ((TARGET_SIMC_TXXXX && !ARCH_T2081) || TARGET_QT1040_1GB) 
 
 config SYS_BOARD
 	string
diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c
index c8e5a13..80235fe 100644
--- a/board/scalys/simc-t10xx/dragonfruit.c
+++ b/board/scalys/simc-t10xx/dragonfruit.c
@@ -11,16 +11,20 @@
 
 #include "dragonfruit.h"
 
+uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
+uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+uint32_t regval;
+
 /*
  * SERDER MUX Configuration pins:
  * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
  * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
  * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
  */
-#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
-#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
-#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
-#define SERDES_CLK_OE  MPC85XX_GPIO_NR(2, 29)
+#define MUX_SER0_1_SEL (0x80000000 >> 25)
+#define MUX_SER2_3_SEL (0x80000000 >> 26)
+#define MUX_SER5_6_SEL (0x80000000 >> 27)
+#define SERDES_CLK_OE  (0x80000000 >> 29)
 
 /* 
  * MUX_SER0_1_SEL
@@ -150,21 +154,29 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	printf("-----------------------------------------------------\n");
 	printf("Serdes lane configuration:\n");
 	if ((mux_config & 1) > 0) {
-		gpio_direction_output(MUX_SER0_1_SEL, 1);
+		regval = in_be32(gpio2_gpdat);
+		regval |= MUX_SER0_1_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("A: SFP slot 0 (T2081 only)\n");
 		printf("B: SFP slot 1\n");
 	} else {
-		gpio_direction_output(MUX_SER0_1_SEL, 0);
+		regval = in_be32(gpio2_gpdat);
+		regval &= ~MUX_SER0_1_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("A: PCIe slot 1 on lane 0\n");
 		printf("B: PCIe slot 1 on lane 1\n");
 	}
 	
 	if ((mux_config & 2) > 0) {
-		gpio_direction_output(MUX_SER2_3_SEL, 1);
+		regval = in_be32(gpio2_gpdat);
+		regval |= MUX_SER2_3_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("C: SFP slot 2\n");
 		printf("D: SFP slot 3\n");
 	} else {
-		gpio_direction_output(MUX_SER2_3_SEL, 0);
+		regval = in_be32(gpio2_gpdat);
+		regval &= ~MUX_SER2_3_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("C: PCIe slot 1 on lane 2\n");
 		printf("D: PCIe slot 1 on lane 3\n");
 	}
@@ -172,11 +184,15 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	printf("E: PCIe slot 4 on lane 0\n");
 	
 	if ((mux_config & 4) > 0) {
-		gpio_direction_output(MUX_SER5_6_SEL, 1);
+		regval = in_be32(gpio2_gpdat);
+		regval |= MUX_SER5_6_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("F: PCIe slot 2 on lane 0\n");
 		printf("G: PCIe slot 3 on lane 0\n");
 	} else {
-		gpio_direction_output(MUX_SER5_6_SEL, 0);
+		regval = in_be32(gpio2_gpdat);
+		regval &= ~MUX_SER5_6_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("F: PCIe slot 4 on lane 1\n");
 		printf("G: PCIe slot 4 on lane 2\n");
 	}
@@ -185,7 +201,14 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	printf("-----------------------------------------------------\n");
 
 	/* Enable serdes clock */
-	gpio_direction_output(SERDES_CLK_OE, 1);
+	regval = in_be32(gpio2_gpdat);
+	regval |= SERDES_CLK_OE;
+	out_be32(gpio2_gpdat, regval);
+	
+	/* Set outputs to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= (MUX_SER0_1_SEL | MUX_SER2_3_SEL | MUX_SER5_6_SEL | SERDES_CLK_OE);
+	out_be32(gpio2_gpdir, regval);
 
 	return ret;
 }
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
index 48b9f68..87ec66f 100644
--- a/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
+++ b/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 AA55AA55 010E0100
 
-0c0a000c 0c000000 00000000 00000000 
+0a0a000c 0c000000 00000000 00000000 
 81000002 40000002 e8105000 21000000 
 00000000 cafebabe 00000000 00030ffc 
 00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
index 5cf027e..9fd7e93 100644
--- a/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
+++ b/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 AA55AA55 010E0100
 #
-0c0a000c 0c000000 00000000 00000000 
+0a0a000c 0c000000 00000000 00000000 
 81000002 40000002 e8023000 21000000 
 00000000 cafebabe 00000000 00030ffc 
 00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
index b5cc904..43b7304 100644
--- a/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
+++ b/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 AA55AA55 010E0100
 #
-0c0a000c 0c000000 00000000 00000000
+0a0a000c 0c000000 00000000 00000000
 81000002 40000002 68105000 21000000
 00000000 cafebabe 00000000 00030ffc
 00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
index dfc4250..6cede86 100644
--- a/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
+++ b/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 AA55AA55 010E0100
 #
-0c0a000c 0c000000 00000000 00000000 
+0a0a000c 0c000000 00000000 00000000 
 81000002 40000002 58105000 21000000 
 00000000 cafebabe 00000000 00030ffc 
 00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/spl.c b/board/scalys/simc-t10xx/spl.c
index c861284..cfb6e04 100644
--- a/board/scalys/simc-t10xx/spl.c
+++ b/board/scalys/simc-t10xx/spl.c
@@ -152,7 +152,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 		break;
 	case 0x40:
 		/* SD/MMC (eSDHC) boot */
-		#ifdef CONFIG_SPL_MMC_BOOT
+#if defined(CONFIG_SPL_MMC_BOOT) || defined(CONFIG_SDHC_FLASH_BOOT)
 		setup_ifc_nand(IFC_CS0);
 		setup_ifc_nor(IFC_CS1);
 		
@@ -160,7 +160,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 		mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 			   (uchar *)CONFIG_ENV_ADDR);
 		boot = mmc_boot;
-		#endif
+#endif
 		break;
 	case 0x105:
 		/* NAND boot */
diff --git a/board/scalys/simc-t2081/dragonfruit.c b/board/scalys/simc-t2081/dragonfruit.c
index 286b2c2..a2d6653 100644
--- a/board/scalys/simc-t2081/dragonfruit.c
+++ b/board/scalys/simc-t2081/dragonfruit.c
@@ -9,16 +9,20 @@
 #include <asm/gpio.h>
 #include "dragonfruit.h"
 
+uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
+uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+uint32_t regval;
+
 /*
  * SERDER MUX Configuration pins:
  * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
  * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
  * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
  */
-#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
-#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
-#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
-#define SERDES_CLK_OE  MPC85XX_GPIO_NR(2, 29)
+#define MUX_SER0_1_SEL (0x80000000 >> 25)
+#define MUX_SER2_3_SEL (0x80000000 >> 26)
+#define MUX_SER5_6_SEL (0x80000000 >> 27)
+#define SERDES_CLK_OE  (0x80000000 >> 29)
 
 /* 
  * MUX_SER0_1_SEL
@@ -80,9 +84,6 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	 * Note: The SERDES lanes A&B, C&D, and F&G can only be switched 
 	 * as pairs using the multiplexers. Which means some SERDES options are only partly usable.
 	 * 
-	 * Note 2/TODO: SERDES PLL2 must be powered down using SRDS_PLL_PD_S1 when
-	 * SRDS_PRTCL_S1 is any of the following values: 0x00, 0x40, 0x60, 0x67, 
-	 * 0x85, 0x87, 0x8D, 0x45.
 	 * 
 	 * T2081 has 8 SERDES lanes at up to 10GHz (ie. SERDES 2 configurations are DNC)
 	 * 
@@ -120,29 +121,32 @@ int scalys_carrier_setup_muxing(int serdes_config)
 		printf("Unsupported SERDES configuration (%02x) detected for dragonfruit carrier board (Warning: Using default multiplexer settings)!\n", serdes_config);
 	}
 	
-	
-
-
-
-	
 	printf("-----------------------------------------------------\n");
 	printf("Serdes lane configuration:\n");
 	if ((mux_config & 1) > 0) {
-		gpio_direction_output(MUX_SER0_1_SEL, 1);
+		regval = in_be32(gpio2_gpdat);
+		regval |= MUX_SER0_1_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("A: SFP slot 0 (T2081 only)\n");
 		printf("B: SFP slot 1\n");
 	} else {
-		gpio_direction_output(MUX_SER0_1_SEL, 0);
+		regval = in_be32(gpio2_gpdat);
+		regval &= ~MUX_SER0_1_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("A: PCIe slot 1 on lane 0\n");
 		printf("B: PCIe slot 1 on lane 1\n");
 	}
 	
 	if ((mux_config & 2) > 0) {
-		gpio_direction_output(MUX_SER2_3_SEL, 1);
+		regval = in_be32(gpio2_gpdat);
+		regval |= MUX_SER2_3_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("C: SFP slot 2\n");
 		printf("D: SFP slot 3\n");
 	} else {
-		gpio_direction_output(MUX_SER2_3_SEL, 0);
+		regval = in_be32(gpio2_gpdat);
+		regval &= ~MUX_SER2_3_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("C: PCIe slot 1 on lane 2\n");
 		printf("D: PCIe slot 1 on lane 3\n");
 	}
@@ -150,11 +154,15 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	printf("E: PCIe slot 4 on lane 0\n");
 	
 	if ((mux_config & 4) > 0) {
-		gpio_direction_output(MUX_SER5_6_SEL, 1);
+		regval = in_be32(gpio2_gpdat);
+		regval |= MUX_SER5_6_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("F: PCIe slot 2 on lane 0\n");
 		printf("G: PCIe slot 3 on lane 0\n");
 	} else {
-		gpio_direction_output(MUX_SER5_6_SEL, 0);
+		regval = in_be32(gpio2_gpdat);
+		regval &= ~MUX_SER5_6_SEL;
+		out_be32(gpio2_gpdat, regval);
 		printf("F: PCIe slot 4 on lane 1\n");
 		printf("G: PCIe slot 4 on lane 2\n");
 	}
@@ -163,7 +171,14 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	printf("-----------------------------------------------------\n");
 
 	/* Enable serdes clock */
-	gpio_direction_output(SERDES_CLK_OE, 1);
+	regval = in_be32(gpio2_gpdat);
+	regval |= SERDES_CLK_OE;
+	out_be32(gpio2_gpdat, regval);
+	
+	/* Set outputs to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= (MUX_SER0_1_SEL | MUX_SER2_3_SEL | MUX_SER5_6_SEL | SERDES_CLK_OE);
+	out_be32(gpio2_gpdir, regval);
 
 	return ret;
 }
diff --git a/board/scalys/simc-t2081/eth.c b/board/scalys/simc-t2081/eth.c
index c25a81c..10c59f8 100644
--- a/board/scalys/simc-t2081/eth.c
+++ b/board/scalys/simc-t2081/eth.c
@@ -30,7 +30,8 @@ uint8_t sfp_phy_config[][2] = {
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FMAN_ENET
-	struct memac_mdio_info memac_mdio_info;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
 	unsigned int i;
 	uint8_t i2c_data;
 	int ret;
@@ -51,12 +52,19 @@ int board_eth_init(bd_t *bis)
 	
 	printf("Initializing Fman\n");
 
-	memac_mdio_info.regs =
+	dtsec_mdio_info.regs =
 		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 
 	/* Register the real 1G MDIO bus */
-	fm_memac_mdio_init(bis, &memac_mdio_info);
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+	
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
 
    /* Marvell 88E1111 Setup
 	* 
@@ -155,7 +163,6 @@ int board_eth_init(bd_t *bis)
 	}
 	
 	/* Two external pin interfaces
-	 * MAC1|MAC2|MAC3 SGMII interface
 	 * MAC3|MAC4|MAC10 EC1|EC2 RGMII interface
 	 */
 	
@@ -174,10 +181,9 @@ int board_eth_init(bd_t *bis)
 				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;*/
 			fm_info_set_phy_address(i, phy_addr);
 			break;
-		case PHY_INTERFACE_MODE_QSGMII:
-			/* TODO, get fixed phy here */
+/*		case PHY_INTERFACE_MODE_QSGMII:
 			fm_info_set_phy_address(i, i+2); 
-			break;
+			break;*/
 		case PHY_INTERFACE_MODE_NONE:
 			fm_info_set_phy_address(i, 0);
 			break;
@@ -191,8 +197,22 @@ int board_eth_init(bd_t *bis)
 			//fm_info_set_phy_address(i, 0);
 			break;
 		}
-		fm_info_set_mdio(i,
-				 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+		fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+	}
+
+	
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+			fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+		default:
+			break;
+		}
+		fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
 	}
 	
 	cpu_eth_init(bis);
@@ -200,7 +220,7 @@ int board_eth_init(bd_t *bis)
 	return pci_eth_init(bis);
 }
 
-/*void fdt_fixup_board_enet(void *fdt)
+void fdt_fixup_board_enet(void *fdt)
 {
 	return;
-}*/
+}
diff --git a/board/scalys/simc-t2081/law.c b/board/scalys/simc-t2081/law.c
index cc03808a..ec8ed07 100644
--- a/board/scalys/simc-t2081/law.c
+++ b/board/scalys/simc-t2081/law.c
@@ -12,17 +12,19 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_SYS_NO_FLASH
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif	
 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
 	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
 #endif
 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
 	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
 #endif
+/*#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif*/
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
@@ -30,3 +32,4 @@ struct law_entry law_table[] = {
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
+
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
index e3ed70b..9b0a4d6 100644
--- a/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
@@ -38,7 +38,9 @@
 091241c8 03008028
 091241cc 28000000
 # Set IFC_CCR clkdiv to 2 (=/3) to get: 
-# (platform clock/2/3=83.3MHz)
+# (platform clock/2/3
 0912444c 02008000
+#Write clk_out reg (platform clock/2)
+#090E1A00 0001D800
 #Flush PBL data (Wait 0xFFFFF cycles )
 091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
index 2746cf4..88dc8ab 100644
--- a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
@@ -1,20 +1,29 @@
 #PBL preamble and RCW header
 AA55AA55 010E0100
 #
-#0a06000c 0c000000 00000000 00000000
-#aa000002 00004000 e8105000 21000000
-#00000000 cafebabe 00000000 00030ffc
-#00000314 0000000c 00000000 00000001
-#
+## SYS_CLK: 100MHz PLAT:600MHz Core:1800MHz FMAN:700MHz (1800MHz speedgrade)
+## DDR:1600MT/s
+# 0c06000e 12000000 00000000 40000000
+# 6c000002 40004000 e8105000 41000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000009 00000000 00000004
 
-# #SerDes=0xaa, Core:1200MHz, DDR:1600MT/s
-# 0a06000c 0c000000 00000000 00000000
-# 66000002 00404000 e8105000 21000000
+## SYS_CLK: 100MHz PLAT:600MHz Core:1500MHz FMAN: 700MHz (1533MHz speedgrade)
+## DDR:1600MT/s
+# 0c06000e 0f000000 00000000 40000000
+# bc000002 40004000 e8105000 41000000
 # 00000000 cafebabe 00000000 00030ffc
-# 00000314 00000008 00000000 00000001
+# 00000314 80000009 00000000 00000004
 
 
-0c06000c 0c000000 00000000 00000000
-aa000002 40404000 e8105000 21000000
+### lowest valid clock & pll settings
+# 0806000a 0a000000 00000000 20000000
+# bc000002 40004000 e8105000 61000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000009 00000000 00000004
+
+## PCI SATA + Virtualization demo 
+0c06000e 12000000 00000000 40000000
+aa000002 40004000 e8105000 41000000
 00000000 cafebabe 00000000 00030ffc
-00000314 80000009 00000000 00000001
+00000314 80000009 00000000 00000004
diff --git a/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
index d8ac2bd..08c3b2a 100644
--- a/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
@@ -1,8 +1,9 @@
 #PBL preamble and RCW header
 AA55AA55 010E0100
 #
-0c06000c 0c000000 00000000 00000000
-aa000002 40404000 e8023000 21000000
+## SYS_CLK: 100MHz PLAT:600MHz Core:1800MHz FMAN:700MHz (Max speedgrade)
+## DDR:1600MT/s SERDES:0x6c 
+0c06000e 12000000 00000000 40000000
+6c000002 40004000 e8023000 41000000
 00000000 cafebabe 00000000 00030ffc
-00000314 80000009 00000000 00000001
-
+00000314 80000009 00000000 00000004
diff --git a/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
index fd38b58..849721a 100644
--- a/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
@@ -27,5 +27,7 @@
 09000010 00000000
 09000014 ff000000
 09000018 81000000
+#Write clk_out reg (platform clock/2)
+#090E1A00 0000EC00
 #Flush PBL data (Wait 0xFFFFF cycles )
 091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
index f06629c..e7c9aad 100644
--- a/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
@@ -1,18 +1,11 @@
 #PBL preamble and RCW header
 AA55AA55 010E0100
+#
+## SYS_CLK: 100MHz PLAT:600MHz Core:1800MHz FMAN:700MHz (Max speedgrade)
+## DDR:1600MT/s SERDES:0x6c  
+0c06000e 12000000 00000000 40000000
+6c000002 40004000 68105000 41000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000004
 
-#SerDes=0xaa, Core:1200MHz, DDR:1600MT/s
-# 0a06000c 0c000000 00000000 00000000
-# 66000002 00404000 68105000 21000000
-# 00000000 cafebabe 00000000 00030ffc
-# 00000314 00000008 00000000 00000001
-
-# 0c06000c 0c000000 00000000 00000000
-# 66000002 40404000 68105000 21000000
-# 00000000 cafebabe 00000000 00030ffc
-# 00000314 80000008 00000000 00000001
 
-0c06000c 0c000000 00000000 00000000
-aa000002 40404000 68105000 21000000
-00000000 cafebabe 00000000 00030ffc
-00000314 80000009 00000000 00000001
diff --git a/board/scalys/simc-t2081/spl.c b/board/scalys/simc-t2081/spl.c
index f0fb9dd..d36e9f4 100644
--- a/board/scalys/simc-t2081/spl.c
+++ b/board/scalys/simc-t2081/spl.c
@@ -152,7 +152,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 		break;
 	case 0x40:
 		/* SD/MMC (eSDHC) boot */
-		#ifdef CONFIG_SPL_MMC_BOOT
+#if defined(CONFIG_SPL_MMC_BOOT) || defined(CONFIG_SDHC_FLASH_BOOT)
 		setup_ifc_nand(IFC_CS0);
 		setup_ifc_nor(IFC_CS1);
 		
@@ -160,7 +160,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 		mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 			   (uchar *)CONFIG_ENV_ADDR);
 		boot = mmc_boot;
-		#endif
+#endif
 		break;
 	case 0x105:
 		/* NAND boot */
diff --git a/board/scalys/simc-t2081/tlb.c b/board/scalys/simc-t2081/tlb.c
index c03282e..ddaa10e 100644
--- a/board/scalys/simc-t2081/tlb.c
+++ b/board/scalys/simc-t2081/tlb.c
@@ -39,7 +39,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_512K, 1),
+		      0, 0, BOOKE_PAGESZ_1M, 1),
 #elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 512K SRAM, in case of Secure Boot
@@ -65,45 +65,60 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_64M, 1), /* modified to simc-t1040 equivalent */
+		      0, 2, BOOKE_PAGESZ_64M, 1),
 
 #ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_PCI
-	/* *I*G* - PCI */
+	/* *I*G* - PCIe 1, 0x80000000 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+
+	/* *I*G* - PCIe 2, 0xa0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 3, 0xb0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+			  
+	/* *I*G* - PCIe 4, 0xc0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI I/O */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256K, 1),
-#endif
+		      0, 7, BOOKE_PAGESZ_256K, 1),
 
-	/* Bman/Qman */
+
+	/* Bman/Qman
+	 */
 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 5, BOOKE_PAGESZ_16M, 1),
+		      0, 9, BOOKE_PAGESZ_16M, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
 		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_16M, 1),
+		      0, 10, BOOKE_PAGESZ_16M, 1),
 #endif
 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 7, BOOKE_PAGESZ_16M, 1),
+		      0, 11, BOOKE_PAGESZ_16M, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
 		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_16M, 1),
+		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 9, BOOKE_PAGESZ_4M, 1),
+		      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
 #ifdef CONFIG_SYS_NAND_BASE
 	/*
@@ -113,17 +128,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_64K, 1),
+		      0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
 			  
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 12, BOOKE_PAGESZ_1G, 1),
+		      0, 19, BOOKE_PAGESZ_1G, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 13, BOOKE_PAGESZ_1G, 1)
+		      0, 20, BOOKE_PAGESZ_1G, 1)
 #endif
 
 };
diff --git a/configs/QT1040-1GB_nand_defconfig b/configs/QT1040-1GB_nand_defconfig
index b24245f..21736da 100644
--- a/configs/QT1040-1GB_nand_defconfig
+++ b/configs/QT1040-1GB_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_QT1040_1GB=y
 CONFIG_PPC_T1040=y
 CONFIG_SYS_FSL_DDR3=y
+CONFIG_SYS_FSL_IFC_CLK_DIV=6
 
 CONFIG_HUSH_PARSER=y
 
@@ -18,6 +19,7 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_IMLS=n
 CONFIG_CMD_I2C=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_MMC-y
 
 CONFIG_PHYLIB=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/T1_simc-t10xx_nand_defconfig b/configs/T1_simc-t10xx_nand_defconfig
index 80b24e7..ca6002e 100644
--- a/configs/T1_simc-t10xx_nand_defconfig
+++ b/configs/T1_simc-t10xx_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_SIMC_TXXXX=y
 CONFIG_PPC_T1040=y
 CONFIG_SYS_FSL_DDR3=y
+CONFIG_SYS_FSL_IFC_CLK_DIV=6
 
 CONFIG_HUSH_PARSER=y
 
@@ -18,6 +19,7 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_IMLS=n
 CONFIG_CMD_I2C=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_MMC=y
 
 CONFIG_PHYLIB=y
 CONFIG_PHY_MARVELL=y
diff --git a/configs/T2_simc-t2081_nand_defconfig b/configs/T2_simc-t2081_nand_defconfig
index 780b70f..8012171 100644
--- a/configs/T2_simc-t2081_nand_defconfig
+++ b/configs/T2_simc-t2081_nand_defconfig
@@ -3,6 +3,7 @@ CONFIG_PPC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_SIMC_TXXXX=y
 CONFIG_PPC_T2081=y
+CONFIG_SYS_FSL_IFC_CLK_DIV=6
 
 CONFIG_HUSH_PARSER=y
 
@@ -17,6 +18,8 @@ CONFIG_CMD_SF=y
 CONFIG_CMD_IMLS=n
 CONFIG_CMD_I2C=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MMC=y
 
 CONFIG_PHYLIB=y
 CONFIG_PHY_MARVELL=y
@@ -41,3 +44,4 @@ CONFIG_DM_GPIO=y
 CONFIG_MPC85XX_GPIO=y
 
 CONFIG_SYS_MALLOC_F=n
+
diff --git a/include/configs/QT1040-1GB.h b/include/configs/QT1040-1GB.h
index 3aa4c37..061b88e 100644
--- a/include/configs/QT1040-1GB.h
+++ b/include/configs/QT1040-1GB.h
@@ -499,7 +499,9 @@
 /* #define CONFIG_DOS_PARTITION */
 #endif  /* CONFIG_PCI */
 
-/* SATA */
+/*
+ * SATA 
+ */
 #define CONFIG_FSL_SATA_V2
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
@@ -521,18 +523,26 @@
 
 #define CONFIG_SPI_FLASH_MTD
 
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif /* CONFIG_USB_EHCI*/ 
+#define CONFIG_HAS_FSL_DR_USB
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
+#define CONFIG_EHCI_DESC_BIG_ENDIAN /* Endiannes fix for EHCI USB */
+#endif
+#endif
 
+/*
+ * SDHC
+ */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
+/*#define CONFIG_CMD_MMC*/
 /* #define CONFIG_GENERIC_MMC */
 #define CONFIG_CMD_EXT2
 /*#define CONFIG_CMD_FAT*/
@@ -573,26 +583,25 @@
 #define CONFIG_QE
 #define CONFIG_U_QE
 
-#if 0
-/* TODO: move FMAN/QE ucode to boot source */
 /* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SDCARD)
-/*
+/* TODO: move FMAN/QE ucode to boot source */
+
+#if defined(CONFIG_SDHC_FLASH_BOOT)
+/* 
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+/*#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
-#define CONFIG_SYS_QE_FW_ADDR			(512 * 0x920)
-#endif
-#endif
-#if defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_QE_FW_ADDR			(512 * 0x920)*/
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
+#define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
 
-/* #define CONFIG_SYS_QE_FW_IN_NAND
-#define CONFIG_SYS_QE_FW_LENGTH		(0x10000) */
+#elif defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
 #define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
 
 #else
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 803d8fb..dc8a546 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -647,7 +647,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_HAS_FSL_DR_USB
-#endif
+#endif /* CONFIG_USB_EHCI_HCD*/
 
 /*
  * SDHC
diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h
index 1c0c677..31a1189 100644
--- a/include/configs/simc-t10xx.h
+++ b/include/configs/simc-t10xx.h
@@ -549,7 +549,9 @@
 /* #define CONFIG_DOS_PARTITION */
 #endif  /* CONFIG_PCI */
 
-/* SATA */
+/*
+ * SATA 
+ */
 #define CONFIG_FSL_SATA_V2
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_LIBATA
@@ -571,18 +573,26 @@
 
 #define CONFIG_SPI_FLASH_MTD
 
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif /* CONFIG_USB_EHCI*/ 
+#define CONFIG_HAS_FSL_DR_USB
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
+#define CONFIG_EHCI_DESC_BIG_ENDIAN /* Endiannes fix for EHCI USB */
+#endif
+#endif
 
+/*
+ * SDHC
+ */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
+/*#define CONFIG_CMD_MMC*/
 /* #define CONFIG_GENERIC_MMC */
 #define CONFIG_CMD_EXT2
 /*#define CONFIG_CMD_FAT*/
@@ -623,29 +633,25 @@
 #define CONFIG_QE
 #define CONFIG_U_QE
 
-#if 0
-/* TODO: move FMAN/QE ucode to boot source */
 /* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SDCARD)
-/*
+/* TODO: move FMAN/QE ucode to boot source */
+
+#if defined(CONFIG_SDHC_FLASH_BOOT)
+/* 
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+/*#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
-#define CONFIG_SYS_QE_FW_ADDR			(512 * 0x920)
-
-
-#el
-#endif
-#endif
-#if defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_QE_FW_ADDR			(512 * 0x920)*/
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
+#define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
 
-/* #define CONFIG_SYS_QE_FW_IN_NAND
-#define CONFIG_SYS_QE_FW_LENGTH		(0x10000) */
+#elif defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
 #define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
 
 #else
diff --git a/include/configs/simc-t2081.h b/include/configs/simc-t2081.h
index 0e3908f..90a84ef 100644
--- a/include/configs/simc-t2081.h
+++ b/include/configs/simc-t2081.h
@@ -14,8 +14,6 @@
 #ifndef __SIMC_T2081_H
 #define __SIMC_T2081_H
 
-#define CONFIG_FSL_SATA_V2
-
 #include <generated/autoconf.h>
 
 #define CONFIG_MTD_UBI_WL_THRESHOLD	4096
@@ -36,11 +34,36 @@
 
 #ifdef CONFIG_RAMBOOT_PBL
 
-/* Todo boot sources */
+/* We have to specify all the PBL and RCW since they are used without being 
+ * proccessed by the preprocessor */
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NAND_FLASH_BOOT)
+/* Secure boot from NAND flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_nand_secure_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_nand_secure_rcw.cfg
+#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NOR_FLASH_BOOT)
+/* Secure boot from NOR flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_nor_secure_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_nor_secure_rcw.cfg
+#elif defined(CONFIG_NAND_FLASH_BOOT)
+/* normal boot from NAND flash */
 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
-
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
-/* Todo boot sources */
+#elif defined(CONFIG_NOR_FLASH_BOOT)
+/* normal boot from NOR flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
+#elif defined(CONFIG_SPI_FLASH_BOOT)
+/* normal boot frop SPI flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_spi_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_spi_rcw.cfg
+#elif defined(CONFIG_SDHC_FLASH_BOOT)
+/* normal boot fro sdhc flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
+#else
+/* unknown configuration, this should not happen */
+#error Invalid Boot configuration
+#endif
 
 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 #define CONFIG_SPL_ENV_SUPPORT
@@ -76,10 +99,16 @@
 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
+#ifndef CONFIG_SDHC_FLASH_BOOT 
 #define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #define CONFIG_SPL_NAND_BOOT
+#endif
 #endif /* CONFIG_NAND */
 
+#ifdef CONFIG_SDHC_FLASH_BOOT
+#define CONFIG_SDCARD
+#endif
+
 #ifdef CONFIG_SDCARD
 #define	CONFIG_RESET_VECTOR_ADDRESS	0x30000FFC
 #define CONFIG_SPL_MMC_SUPPORT
@@ -412,14 +441,17 @@
 /* The lowest and highest voltage allowed for T208xRDB */
 #define VDD_MV_MIN			819
 #define VDD_MV_MAX			1212
+
+
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE2		/* PCIE controller 2 */
-#define CONFIG_PCIE3		/* PCIE controller 3 */
-#define CONFIG_PCIE4		/* PCIE controller 4 */
+/* #define CONFIG_PCI */		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controler 1 */
+#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE4		/* PCIE controler 4 */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
@@ -457,6 +489,7 @@
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
@@ -464,15 +497,14 @@
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
-
+#define CONFIG_NET_MULTI
 #define CONFIG_E1000
-#define CONFIG_E1000_SPI
-#define CONFIG_CMD_E1000
-
-#define CONFIG_PCI_SCAN_SHOW        /* show pci devices on startup */
-/* #define CONFIG_DOS_PARTITION  */
-#endif  /* CONFIG_PCI */
+/*#define CONFIG_PCI_PNP*/		/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+/* #define CONFIG_DOS_PARTITION */
+#endif
 
+#if 0 /* T2081 has no SATA */
 /*
  * SATA
  */
@@ -490,17 +522,21 @@
 #define CONFIG_LBA48
 /* #define CONFIG_DOS_PARTITION */
 #endif
+#endif
 
 /*#define CONFIG_SPI_FLASH_MTD*/
 
 /*
  * USB
  */
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_HAS_FSL_DR_USB
-#endif /* CONFIG_USB_EHCI*/ 
+#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
+#define CONFIG_EHCI_DESC_BIG_ENDIAN /* Endiannes fix for EHCI USB */
+#endif
+#endif
 
 /*
  * SDHC
@@ -511,7 +547,7 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_CMD_MMC
+/*#define CONFIG_CMD_MMC*/
 /* #define CONFIG_GENERIC_MMC */
 #define CONFIG_CMD_EXT2
 /*#define CONFIG_CMD_FAT*/
@@ -551,25 +587,29 @@
 /* #define CONFIG_SYS_DPAA_RMAN */
 #define CONFIG_SYS_INTERLAKEN
 
-/*TODO: QE not supported on T2081???
+/*TODO: QE not supported on T2081
  #define CONFIG_QE
  #define CONFIG_U_QE */
 
 /* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SDCARD)
-/*
+/* TODO: move FMAN/QE ucode to boot source */
+
+#if defined(CONFIG_SDHC_FLASH_BOOT)
+/* 
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+/*#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
-#elif defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_QE_FW_ADDR			(512 * 0x920)*/
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
+#define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
 
-/* #define CONFIG_SYS_QE_FW_IN_NAND This define has been moved out of this file in this u-boot version */
-/* #define CONFIG_SYS_QE_FW_LENGTH		(0x10000) This define has been moved out of this file in this u-boot version */
+#elif defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
 #define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
 
 #else
@@ -592,7 +632,7 @@
 #define CONFIG_SYS_RGMII1_PHY_ADDR      0x00
 #define CONFIG_SYS_RGMII2_PHY_ADDR      0x01
 
-#define FM1_10GEC1_PHY_ADDR	0x00  /* Todo implement further and test!! */
+#define FM1_10GEC1_PHY_ADDR	0x00
 #define FM1_10GEC2_PHY_ADDR	0x01
 
 #define CONFIG_MII          /* MII PHY management */
@@ -697,8 +737,7 @@
 #define MTDPART_DEFAULT_PARTITIONS \
 	"2M@0x0(u-boot)," \
 	"256k(env)," \
-	"256k(fman_ucode)," \
-	"256k(qe_ucode),"
+	"256k(fman_ucode),"
 
 #ifdef CONFIG_NAND_FLASH
 
@@ -718,7 +757,7 @@
 #ifdef CONFIG_NOR_FLASH
 #define NOR_ENV	\
 	"update-uboot-nor-nw=" \
-		"dhcp; tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nor;" \
+		"tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nor;" \
 		"if test $? = \"0\"; then " \
 			"protect off 0xe8000000 0xe81fffff;" \
 			"erase 0xe8000000 0xe81fffff;" \
@@ -741,16 +780,8 @@
 			"erase 0xe8240000 0xe827ffff;" \
 			"cp.w ${loadaddr} 0xe8240000 ${filesize};" \
 		"fi\0" \
-	"update-qe-ucode-nor-usb=" \
-		"usb start;" \
-		"fatload usb 0 ${loadaddr} iram_Type_A_T2080_r1.0.bin;" \
-		"if test $? = \"0\"; then " \
-			"protect off 0xe8280000 0xe82bffff;" \
-			"erase 0xe8280000 0xe82bffff;" \
-			"cp.w ${loadaddr} 0xe8280000 ${filesize};" \
-		"fi\0" \
+	\
 	"update-ubi-rootfs-nor="\
-		"dhcp;" \
 		"ubi part ubipart_nor;" \
 		"if test $? = \"0\"; then " \
 			"tftp ${TFTP_PATH}/ubi_rootfs_image.nor.ubifs;" \
@@ -776,7 +807,6 @@
 #ifdef CONFIG_NAND_FLASH
 #define NAND_ENV \
     "update-uboot-nand-nw=" \
-        "dhcp;" \
         "tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nand;" \
         "if test $? = \"0\"; then " \
             "nand erase.part u-boot;" \
@@ -796,14 +826,7 @@
         "nand write ${loadaddr} fman_ucode ${filesize};" \
         "\0" \
     \
-    "update-qe-ucode-nand-usb=" \
-        "usb start;" \
-        "fatload usb 0 ${loadaddr} iram_Type_A_T2080_r1.0.bin;" \
-        "nand erase.part qe_ucode;" \
-        "nand write ${loadaddr} qe_ucode ${filesize};" \
-        "\0" \
     "update-ubi-rootfs-nand="\
-        "dhcp;" \
         "ubi part ubipart_nand;" \
         "if test $? = \"0\"; then " \
             "tftp ${TFTP_PATH}/ubi_rootfs_image.nand.ubifs;" \
@@ -821,6 +844,14 @@
         "bootm ${fitaddr}#conf@1" \
         "\0" \
     \
+    "sataboot-nand=" \
+        "ubi part ubipart_nand;" \
+        "ubifsmount ubi0:rootfs;" \
+        "ubifsload ${fitaddr} /boot/fitImage.itb;" \
+        "setenv bootargs ${bootargs} ${bootargs_sata};" \
+        "bootm ${fitaddr}#conf@1" \
+        "\0" \
+    \
     "set_ubiboot_args_nand=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nand ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0"
 #else
 #define NAND_ENV
@@ -844,13 +875,17 @@
     "hwconfig=" \
         "fsl_ddr:bank_intlv=null;"\
         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
-        "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+        "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+        "fsl_fm1_xaui_phy:xfi" "\0"\
     \
     "ethaddr=02:00:00:ba:be:01\0" \
     "eth1addr=02:00:00:ba:be:02\0" \
     "eth2addr=02:00:00:ba:be:03\0" \
     "eth3addr=02:00:00:ba:be:04\0" \
     "eth4addr=02:00:00:ba:be:05\0" \
+    "eth5addr=02:00:00:ba:be:06\0" \
+    "eth6addr=02:00:00:ba:be:07\0" \
+    "eth7addr=02:00:00:ba:be:08\0" \
     \
     "autoload=no\0" \
     "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \
@@ -872,11 +907,11 @@
 	"setenv mtdparts \"${mtdparts};\"fe110000.spi:" MTDPART_DEFAULT_PARTITIONS "-(storage);"\
 	";fi\0" \
     \
-    "netboot=dhcp; tftp ${fitaddr} ${TFTP_PATH}/fitImage.itb; bootm ${fitaddr}#conf@1\0" \
+    "netboot=tftp ${fitaddr} ${TFTP_PATH}/fitImage.itb; bootm ${fitaddr}#conf@1\0" \
     \
     "bootcmd=run setfans; run "BOOTCMD"\0" \
     \
-    "bootargs_sata=rootfstype=ext3 root=/dev/sda1\0" \
+    "bootargs_sata=rootfstype=ext4 root=/dev/sda1 rw\0" \
     "bootargs=console=ttyS0,115200 rootwait panic=10\0" \
 
 #endif	/* SIMC_T2081_H */
-- 
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