From 24a514c44557601de52df3c8bc0ee789bef8714c Mon Sep 17 00:00:00 2001 From: Ben Gardiner Date: Wed, 20 Apr 2011 16:25:06 -0400 Subject: da850evm: fix NAND WSTROBE and TA timings The current NAND timings, introduced in commit a3f88293ddd13facd734769c1664d35ab4ed681f da850evm: setup the NAND flash timings , incorrectly set WSTROBE and TA to 0. A more recent inspection of the values set by the Linux kernel indicates that these should be set to 1. Set the WSTROBE and TA field of the EMIFA cycle-count timings configuration to 1 to match the values set by linux. Signed-off-by: Ben Gardiner CC: Stefano Babic CC: Sandeep Paulraj CC: Scott Wood Signed-off-by: Sandeep Paulraj diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index b088c9c..73eaa48 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -179,12 +179,12 @@ int board_init(void) * Linux kernel @ 25MHz EMIFA */ writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(0) | + DAVINCI_ABCR_WSTROBE(1) | DAVINCI_ABCR_WHOLD(0) | DAVINCI_ABCR_RSETUP(0) | DAVINCI_ABCR_RSTROBE(1) | DAVINCI_ABCR_RHOLD(0) | - DAVINCI_ABCR_TA(0) | + DAVINCI_ABCR_TA(1) | DAVINCI_ABCR_ASIZE_8BIT), &davinci_emif_regs->ab2cr); /* CS3 */ #endif -- cgit v0.10.2 From b73850f7644db4f4c68f6efda43928a5be5a8534 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 10 Apr 2011 08:17:50 +0000 Subject: MX31: mx31pdk: Add watchdog support Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 826fb4a..08addd2 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -28,9 +28,17 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_HW_WATCHDOG +void hw_watchdog_reset(void) +{ + mxc_hw_watchdog_reset(); +} +#endif + int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -68,6 +76,14 @@ int board_init(void) return 0; } +int board_late_init(void) +{ +#ifdef CONFIG_HW_WATCHDOG + mxc_hw_watchdog_enable(); +#endif + return 0; +} + int checkboard(void) { printf("Board: MX31PDK\n"); diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index d4c6d16..f5d3ee7 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -61,6 +61,7 @@ #define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 +#define CONFIG_HW_WATCHDOG #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 @@ -98,6 +99,8 @@ */ #undef CONFIG_CMD_IMLS +#define BOARD_LATE_INIT + #define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2 From e53bcd947daaf6d6c05c545ddb734cb89fc40772 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 9 Apr 2011 10:43:24 +0000 Subject: gpio: imx: Fix return value on error Signed-off-by: Fabio Estevam diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 1037862..6efbb02 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -24,6 +24,7 @@ #include #include #include +#include /* GPIO port description */ static unsigned long gpio_ports[] = { @@ -47,7 +48,7 @@ int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction) u32 l; if (port >= ARRAY_SIZE(gpio_ports)) - return 1; + return -EINVAL; gpio &= 0x1f; @@ -95,7 +96,7 @@ int mxc_gpio_get(unsigned int gpio) u32 l; if (port >= ARRAY_SIZE(gpio_ports)) - return -1; + return -EINVAL; gpio &= 0x1f; -- cgit v0.10.2 From d109b11e54739212632e3f5309c62a7d5cd49773 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 26 Apr 2011 07:40:19 +0200 Subject: MX31: removed warning due to missing prototype Drop warning caused by missing prototype for mxc_hw_watchdog_reset(). Signed-off-by: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 8dc6e82..1ff917e 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -31,5 +31,6 @@ extern void mx31_set_pad(enum iomux_pins pin, u32 config); void mx31_uart1_hw_init(void); void mx31_spi2_hw_init(void); +void mxc_hw_watchdog_enable(void); #endif /* __ASM_ARCH_CLOCK_H */ -- cgit v0.10.2 From 2f22045be5590e3034b0d55cac9fd050f7837a17 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 29 Apr 2011 08:56:27 +0200 Subject: MX31: change return value of get_cpu_rev Drop warnings in get_cpu_rev and changes the return value (a u32 instead of char * is returned) of the function to be coherent with other processors. Signed-off-by: Stefano Babic CC: Detlev Zundel CC: Fabio Estevam diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 18572b9..fccd2cd 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -107,18 +107,18 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) } struct mx3_cpu_type mx31_cpu_type[] = { - { .srev = 0x00, .v = "1.0" }, - { .srev = 0x10, .v = "1.1" }, - { .srev = 0x11, .v = "1.1" }, - { .srev = 0x12, .v = "1.15" }, - { .srev = 0x13, .v = "1.15" }, - { .srev = 0x14, .v = "1.2" }, - { .srev = 0x15, .v = "1.2" }, - { .srev = 0x28, .v = "2.0" }, - { .srev = 0x29, .v = "2.0" }, + { .srev = 0x00, .v = 0x10 }, + { .srev = 0x10, .v = 0x11 }, + { .srev = 0x11, .v = 0x11 }, + { .srev = 0x12, .v = 0x1F }, + { .srev = 0x13, .v = 0x1F }, + { .srev = 0x14, .v = 0x12 }, + { .srev = 0x15, .v = 0x12 }, + { .srev = 0x28, .v = 0x20 }, + { .srev = 0x29, .v = 0x20 }, }; -char *get_cpu_rev(void) +u32 get_cpu_rev(void) { u32 i, srev; @@ -129,7 +129,8 @@ char *get_cpu_rev(void) for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) if (srev == mx31_cpu_type[i].srev) return mx31_cpu_type[i].v; - return "unknown"; + + return srev | 0x8000; } char *get_reset_cause(void) @@ -161,8 +162,12 @@ char *get_reset_cause(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { - printf("CPU: Freescale i.MX31 rev %s at %d MHz.", - get_cpu_rev(), mx31_get_mcu_main_clk() / 1000000); + u32 srev = get_cpu_rev(); + + printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.", + (srev & 0xF0) >> 4, (srev & 0x0F), + ((srev & 0x8000) ? " unknown" : ""), + mx31_get_mcu_main_clk() / 1000000); printf("Reset cause: %s\n", get_reset_cause()); return 0; } diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index c830a03..306f966 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -105,7 +105,7 @@ struct iim_regs { struct mx3_cpu_type { u8 srev; - char *v; + u32 v; }; #define IOMUX_PADNUM_MASK 0x1ff -- cgit v0.10.2 From 29d53d19f3d0ed6505f52b459e3a092b93f641b5 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 3 May 2011 21:17:34 +0530 Subject: Kirkwood: allow to override CONFIG_SYS_TCLK This patch allow to override CONFIG_SYS_TCLK from board configuration files. This is needed for the Network Space v2 which use a non standard core clock frequency (166MHz instead of 200MHz for a 6281 SoC). As a possible enhancement for 6281 and 6282 devices, TCLK could be dynamically detected by checking the Sample at Reset register bit 21. Additionally this patch fix a typo. Signed-off-by: Simon Guinot Acked-by: Prafulla Wadaskar diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h b/arch/arm/include/asm/arch-kirkwood/kw88f6281.h index 80723ea..22d10f1 100644 --- a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h +++ b/arch/arm/include/asm/arch-kirkwood/kw88f6281.h @@ -27,11 +27,13 @@ #ifndef _ASM_ARCH_KW88F6281_H #define _ASM_ARCH_KW88F6281_H -/* SOC specific definations */ +/* SOC specific definitions */ #define KW88F6281_REGS_PHYS_BASE 0xf1000000 #define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE -/* TCLK Core Clock defination*/ -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ +/* TCLK Core Clock definition */ +#ifndef CONFIG_SYS_TCLK +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ +#endif #endif /* _ASM_ARCH_KW88F6281_H */ -- cgit v0.10.2 From 2f795ac74eceea36199f07b385d2c85f61396a04 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Tue, 3 May 2011 21:17:34 +0530 Subject: mv-common.h: fix DRAM banks configuration The asm/arch/config.h header define CONFIG_NR_DRAM_BANKS_MAX, which is needed to configure DRAM banks. This patch move the asm/arch/config.h header inclusion above the DRAM banks configuration. Additionally this patch fix a typo. Signed-off-by: Simon Guinot diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index a8937dd..0a39257 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -113,6 +113,9 @@ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* ====> Include platform Common Definitions */ +#include + /* * DRAM Banks configuration, Custom config can be done in .h */ @@ -124,10 +127,7 @@ #endif #endif /* CONFIG_NR_DRAM_BANKS */ -/* ====> Include platform Common Definations */ -#include - -/* ====> Include driver Common Definations */ +/* ====> Include driver Common Definitions */ /* * Common NAND configuration */ -- cgit v0.10.2 From f846604ff57487e0d6e5ddebf8c4c4c02bd5e077 Mon Sep 17 00:00:00 2001 From: Clint Adams <[clint@debian.org]> Date: Fri, 6 May 2011 22:06:47 +0530 Subject: Rename openrd_base files to openrd Signed-off-by: Clint Adams Cc: Albert ARIBAUD Cc: Prafulla Wadaskar Cc: Julian Pidancet diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile new file mode 100644 index 0000000..19020e4 --- /dev/null +++ b/board/Marvell/openrd/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2009 +# Net Insight +# Written-by: Simon Kagstrom +# +# Based on sheevaplug: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := openrd.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg new file mode 100644 index 0000000..757eb28 --- /dev/null +++ b/board/Marvell/openrd/kwbimage.cfg @@ -0,0 +1,168 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strength reduced +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 +# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 +# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. +# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) + +DATA 0xFFD0149C 0x0000E40f # CPU ODT Control +# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm +# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm +# bit14: 1, M_STARTBURST_IN ODT: Enabled +# bit15: 1, DDR IO ODT Unit: Use ODT block +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c new file mode 100644 index 0000000..e53fa16 --- /dev/null +++ b/board/Marvell/openrd/openrd.c @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2009 + * Net Insight + * Written-by: Simon Kagstrom + * + * Based on sheevaplug.c: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "openrd.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(OPENRD_OE_VAL_LOW, + OPENRD_OE_VAL_HIGH, + OPENRD_OE_LOW, OPENRD_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, /* Alt UART1_TXD */ + MPP14_SD_D0, /* Alt UART1_RXD */ + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_TSMP9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, /* UART1 / SD sel */ + MPP35_TDM_CH0_TX_QL, + MPP36_TDM_SPI_CS1, + MPP37_TDM_CH2_TX_QL, + MPP38_TDM_CH2_RX_QL, + MPP39_AUDIO_I2SBCLK, + MPP40_AUDIO_I2SDO, + MPP41_AUDIO_I2SLRC, + MPP42_AUDIO_I2SMCLK, + MPP43_AUDIO_I2SDI, + MPP44_AUDIO_EXTCLK, + MPP45_TDM_PCLK, + MPP46_TDM_FS, + MPP47_TDM_DRX, + MPP48_TDM_DTX, + MPP49_TDM_CH0_RX_QL, + 0 + }; + + kirkwood_mpp_conf(kwmpp_config); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/openrd/openrd.h b/board/Marvell/openrd/openrd.h new file mode 100644 index 0000000..f3daf17 --- /dev/null +++ b/board/Marvell/openrd/openrd.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2009 + * Net Insight + * Written-by: Simon Kagstrom + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __OPENRD_BASE_H +#define __OPENRD_BASE_H + +#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ +#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ +#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ +#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __OPENRD_BASE_H */ diff --git a/board/Marvell/openrd_base/Makefile b/board/Marvell/openrd_base/Makefile deleted file mode 100644 index d6d0ed3..0000000 --- a/board/Marvell/openrd_base/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -# -# (C) Copyright 2009 -# Net Insight -# Written-by: Simon Kagstrom -# -# Based on sheevaplug: -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -# MA 02110-1301 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := openrd_base.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/Marvell/openrd_base/kwbimage.cfg b/board/Marvell/openrd_base/kwbimage.cfg deleted file mode 100644 index 757eb28..0000000 --- a/board/Marvell/openrd_base/kwbimage.cfg +++ /dev/null @@ -1,168 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor -# Written-by: Prafulla Wadaskar -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -# MA 02110-1301 USA -# -# Refer docs/README.kwimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x37543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x000000cc # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs1width=x8 -# bit7-6: 11, Cs1size=1Gb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000042 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strength reduced -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 - -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) -# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 -# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 -# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. -# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) - -DATA 0xFFD0149C 0x0000E40f # CPU ODT Control -# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 -# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm -# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm -# bit14: 1, M_STARTBURST_IN ODT: Enabled -# bit15: 1, DDR IO ODT Unit: Use ODT block -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c deleted file mode 100644 index 10109c1..0000000 --- a/board/Marvell/openrd_base/openrd_base.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * (C) Copyright 2009 - * Net Insight - * Written-by: Simon Kagstrom - * - * Based on sheevaplug.c: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "openrd_base.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - kw_config_gpio(OPENRD_OE_VAL_LOW, - OPENRD_OE_VAL_HIGH, - OPENRD_OE_LOW, OPENRD_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, /* Alt UART1_TXD */ - MPP14_SD_D0, /* Alt UART1_RXD */ - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GPIO, - MPP29_TSMP9, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GPIO, /* UART1 / SD sel */ - MPP35_TDM_CH0_TX_QL, - MPP36_TDM_SPI_CS1, - MPP37_TDM_CH2_TX_QL, - MPP38_TDM_CH2_RX_QL, - MPP39_AUDIO_I2SBCLK, - MPP40_AUDIO_I2SDO, - MPP41_AUDIO_I2SLRC, - MPP42_AUDIO_I2SMCLK, - MPP43_AUDIO_I2SDI, - MPP44_AUDIO_EXTCLK, - MPP45_TDM_PCLK, - MPP46_TDM_FS, - MPP47_TDM_DRX, - MPP48_TDM_DTX, - MPP49_TDM_CH0_RX_QL, - 0 - }; - - kirkwood_mpp_conf(kwmpp_config); - return 0; -} - -int board_init(void) -{ - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - u16 reg; - u16 devadr; - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1116 Initialized on %s\n", name); -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/openrd_base/openrd_base.h b/board/Marvell/openrd_base/openrd_base.h deleted file mode 100644 index f3daf17..0000000 --- a/board/Marvell/openrd_base/openrd_base.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2009 - * Net Insight - * Written-by: Simon Kagstrom - * - * Based on sheevaplug.h: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __OPENRD_BASE_H -#define __OPENRD_BASE_H - -#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ -#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ -#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ -#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -#endif /* __OPENRD_BASE_H */ diff --git a/boards.cfg b/boards.cfg index f0d3440..6bcda28 100644 --- a/boards.cfg +++ b/boards.cfg @@ -108,7 +108,7 @@ suen8 arm arm926ejs km_arm keymile mgcoge2un arm arm926ejs km_arm keymile kirkwood guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood -openrd_base arm arm926ejs - Marvell kirkwood +openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE rd6281a arm arm926ejs - Marvell kirkwood sheevaplug arm arm926ejs - Marvell kirkwood dockstar arm arm926ejs - Seagate kirkwood diff --git a/include/configs/openrd.h b/include/configs/openrd.h new file mode 100644 index 0000000..13dc34c --- /dev/null +++ b/include/configs/openrd.h @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2009 + * Net Insight + * Written-by: Simon Kagstrom + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_OPENRD_H +#define _CONFIG_OPENRD_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nOpenRD_base" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_OPENRD_BASE /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_IDE + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0x60000 +#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "${x_bootcmd_usb}; bootm 0x6400000;" + +#define MTDIDS_DEFAULT "nand0=nand_mtd" +#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ + "0x400000@0x100000(uImage),"\ + "0x1fb00000@0x500000(rootfs)" + +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ + "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ + "mtdids="MTDIDS_DEFAULT"\0" \ + "mtdparts="MTDPARTS_DEFAULT"\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0x8 +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ + +#endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h deleted file mode 100644 index cfdd09c..0000000 --- a/include/configs/openrd_base.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * (C) Copyright 2009 - * Net Insight - * Written-by: Simon Kagstrom - * - * Based on sheevaplug.h: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _CONFIG_OPENRD_BASE_H -#define _CONFIG_OPENRD_BASE_H - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nOpenRD_base" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_MACH_OPENRD_BASE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#include -#define CONFIG_CMD_AUTOSCRIPT -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_IDE - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" - -#define MTDIDS_DEFAULT "nand0=nand_mtd" -#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ - "0x400000@0x100000(uImage),"\ - "0x1fb00000@0x500000(rootfs)" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ - "mtdids="MTDIDS_DEFAULT"\0" \ - "mtdparts="MTDPARTS_DEFAULT"\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0x8 -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#endif /* _CONFIG_OPENRD_BASE_H */ -- cgit v0.10.2 From 21861f2d39ac8cab88dd3cfa1285aa4f69023b10 Mon Sep 17 00:00:00 2001 From: Clint Adams <[clint@debian.org]> Date: Fri, 6 May 2011 22:06:47 +0530 Subject: Add definitions for OpenRD-Client and OpenRD-Ultimate Signed-off-by: Clint Adams Cc: Albert ARIBAUD Cc: Prafulla Wadaskar Cc: Julian Pidancet diff --git a/MAKEALL b/MAKEALL index c3df657..d592374 100755 --- a/MAKEALL +++ b/MAKEALL @@ -361,6 +361,8 @@ LIST_ARM9=" \ omap5912osk \ omap730p2 \ openrd_base \ + openrd_client \ + openrd_ultimate \ rd6281a \ sbc2410x \ scb9328 \ diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index e53fa16..14ca88e 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -110,7 +110,13 @@ int board_init(void) /* * arch number of board */ +#if defined(CONFIG_BOARD_IS_OPENRD_BASE) gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; +#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; +#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; diff --git a/boards.cfg b/boards.cfg index 6bcda28..4f48d19 100644 --- a/boards.cfg +++ b/boards.cfg @@ -109,6 +109,8 @@ mgcoge2un arm arm926ejs km_arm keymile guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE +openrd_client arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT +openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE rd6281a arm arm926ejs - Marvell kirkwood sheevaplug arm arm926ejs - Marvell kirkwood dockstar arm arm926ejs - Seagate kirkwood diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 13dc34c..7299749 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -33,7 +33,19 @@ /* * Version number information */ -#define CONFIG_IDENT_STRING "\nOpenRD_base" +#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE +# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate" +#else +# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT +# define CONFIG_IDENT_STRING "\nOpenRD-Client" +# else +# ifdef CONFIG_BOARD_IS_OPENRD_BASE +# define CONFIG_IDENT_STRING "\nOpenRD-Base" +# else +# error Unknown OpenRD board specified +# endif +# endif +#endif /* * High Level Configuration Options (easy to change) -- cgit v0.10.2 From 1615db3c1c8e0b359c15453423f8beb8c4821415 Mon Sep 17 00:00:00 2001 From: Clint Adams <[clint@debian.org]> Date: Fri, 6 May 2011 22:06:47 +0530 Subject: Initialize second PHY on OpenRD-Client and OpenRD-Ultimate Though the OpenRD-Base only has one gigabit Ethernet port, both the OpenRD-Client and OpenRD-Ultimate each have two. On the Ultimate, the PHY addresses are consecutive, but on the Client they are not. (based on <62a0952ce368acc725063a00a5ec680a639d6c27.1301040318.git.julian.pidancet@citrix.com> ) Signed-off-by: Clint Adams Cc: Albert ARIBAUD Cc: Prafulla Wadaskar Cc: Julian Pidancet diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index 14ca88e..87939de 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -124,12 +124,11 @@ int board_init(void) } #ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) +/* Configure and enable MV88E1116/88E1121 PHY */ +void mv_phy_init(char *name) { u16 reg; u16 devadr; - char *name = "egiga0"; if (miiphy_set_current_dev(name)) return; @@ -154,6 +153,24 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, devadr); - printf("88E1116 Initialized on %s\n", name); + printf(PHY_NO" Initialized on %s\n", name); +} + +void reset_phy(void) +{ + mv_phy_init("egiga0"); + +#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT + /* Kirkwood ethernet driver is written with the assumption that in case + * of multiple PHYs, their addresses are consecutive. But unfortunately + * in case of OpenRD-Client, PHY addresses are not consecutive.*/ + miiphy_write("egiga1", 0xEE, 0xEE, 24); +#endif + +#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ + defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) + /* configure and initialize both PHY's */ + mv_phy_init("egiga1"); +#endif } #endif /* CONFIG_RESET_PHY_R */ diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 7299749..8d86067 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -117,8 +117,18 @@ * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0x8 +# ifdef CONFIG_BOARD_IS_OPENRD_BASE +# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +# else +# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ +# endif +# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE +# define CONFIG_PHY_BASE_ADR 0x0 +# define PHY_NO "88E1121" +# else +# define CONFIG_PHY_BASE_ADR 0x8 +# define PHY_NO "88E1116" +# endif #endif /* CONFIG_CMD_NET */ /* -- cgit v0.10.2 From 2e73808ee97d75400881d1fe144b062f427cfcb9 Mon Sep 17 00:00:00 2001 From: Clint Adams <[clint@debian.org]> Date: Fri, 6 May 2011 22:06:47 +0530 Subject: Enable multiple fs options for Marvell SoC family on OpenRD boards Signed-off-by: Clint Adams Cc: Albert ARIBAUD Cc: Prafulla Wadaskar Cc: Julian Pidancet diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 8d86067..3256cb3 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -60,6 +60,7 @@ * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS #include #define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP -- cgit v0.10.2