From 5c19689b5e1f02f85528e7258623cc17c191097b Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Thu, 31 Mar 2016 15:54:38 +0200 Subject: dm: gpio: Add DM GPIO driver for MPC8xxx platforms This driver adds DM GPIO support for the NXP QorIQ T10xx series. ported from the linux kernel 4.5 * (b562e44f507e863c6792946e4e1b1449fbbac85d) * and removed the interrupt functionallity. This driver could also support the older platforms, as well as the new LayerScape (ARM) based platforms, but these platforms are not supported at this time. diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h index da7352a..530175f 100644 --- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h @@ -14,6 +14,10 @@ #ifndef __ASM_ARCH_MX85XX_GPIO_H #define __ASM_ARCH_MX85XX_GPIO_H +#ifdef CONFIG_MPC8XXX_GPIO +#include +#else #include +#endif #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 53ca6d9..746ad2a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3196,4 +3196,14 @@ struct ccsr_scfg { u32 res4[60]; u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */ }; + +#if defined(CONFIG_PPC_T1013) || defined(CONFIG_PPC_T1014) ||\ + defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) ||\ + defined(CONFIG_PPC_T1023) || defined(CONFIG_PPC_T1024) ||\ + defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +#define CONFIG_SYS_MPC8XXX_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x130000) +#define CONFIG_SYS_MPC8XXX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000) +#define CONFIG_SYS_MPC8XXX_GPIO3_ADDR (CONFIG_SYS_IMMR + 0x132000) +#define CONFIG_SYS_MPC8XXX_GPIO4_ADDR (CONFIG_SYS_IMMR + 0x133000) +#endif #endif /*__IMMAP_85xx__*/ diff --git a/arch/powerpc/include/asm/mpc8xxx_gpio.h b/arch/powerpc/include/asm/mpc8xxx_gpio.h new file mode 100644 index 0000000..d4a5b7c --- /dev/null +++ b/arch/powerpc/include/asm/mpc8xxx_gpio.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2016 Scalys B.V. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _POWERPC_ASM_MPC8XXX_GPIO_H +#define _POWERPC_ASM_MPC8XXX_GPIO_H + +#define MPC8XXX_GPIO_NR(port, pin) ((((port)-1)*32)+((pin)&31)) +#define MPC8XXX_GPIO_TO_PORT(gpio) (gpio/32) +#define MPC8XXX_GPIO_TO_PIN(gpio) (gpio&31) + +static inline void mpc8xxx_gpio_set(uint32_t gpio, int value) +{ + int port, pin; + ccsr_gpio_t *gpio_regs; + uint32_t regval; + + port = MPC8XXX_GPIO_TO_PORT(gpio); + pin = MPC8XXX_GPIO_TO_PIN(gpio); + + switch (port) { +#ifdef CONFIG_SYS_MPC8XXX_GPIO1_ADDR + case 0: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO1_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO2_ADDR + case 1: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO2_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO3_ADDR + case 2: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO3_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO4_ADDR + case 3: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO4_ADDR; + break; +#endif + default: + return; + } + + /* Set output */ + regval = in_be32(&(gpio_regs->gpdat)); + regval |= (0x80000000 >> pin); + out_be32(&(gpio_regs->gpdat), regval); + + /* Set direction to acivate gpio pin */ + regval = in_be32(&(gpio_regs->gpdir)); + regval |= (0x80000000 >> pin); + out_be32(&(gpio_regs->gpdir), regval); +} + +static inline int mpc8xxx_gpio_get(uint32_t gpio, int value) +{ + int port, pin; + ccsr_gpio_t *gpio_regs; + uint32_t regval; + + port = MPC8XXX_GPIO_TO_PORT(gpio); + pin = MPC8XXX_GPIO_TO_PIN(gpio); + + switch (port) { +#ifdef CONFIG_SYS_MPC8XXX_GPIO1_ADDR + case 0: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO1_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO2_ADDR + case 1: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO2_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO3_ADDR + case 2: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO3_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO4_ADDR + case 3: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO4_ADDR; + break; +#endif + default: + return; + } + + /* Get inputs */ + regval = in_be32(&(gpio_regs->gpdat)); + regval <<= pin; + regval &= 1; + + return regval; +} + +#endif /* _POWERPC_ASM_MPC8XXX_GPIO_H */ diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f56a606..2564dd2 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -28,6 +28,13 @@ config DWAPB_GPIO help Support for the Designware APB GPIO driver. +config MPC8XXX_GPIO + bool "NXP (Freescale) MPC8xxx driver" + depends on DM_GPIO + default n + help + Support for the NXP (Freescale) MPC/QorIQ GPIO controller + config ATMEL_PIO4 bool "ATMEL PIO4 driver" depends on DM diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 4f071c4..8a76a62 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o obj-$(CONFIG_ALTERA_PIO) += altera_pio.o obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o +obj-$(CONFIG_MPC8XXX_GPIO) += gpio-mpc8xxx.o obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c new file mode 100644 index 0000000..c5d72ef --- /dev/null +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -0,0 +1,178 @@ + +/* + * GPIOs on MPC512x/8349/8572/8610/T-series and compatible + * + * Driver ported from the linux kernel 4.5 (b562e44f507e863c6792946e4e1b1449fbbac85d) + * and removed the interrupt functionallity. + * + * Copyright (C) 2008 Peter Korsgaard + * Copyright (c) 2016 Scalys B.V. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MPC8XXX_GPIO_PINS 32 + +static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) +{ + return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); +} + +static int mpc8xxx_dm_gpio_set(struct udevice *dev, unsigned pin, int val) +{ + struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); + +#if defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) + + if (val) { + plat->data |= mpc8xxx_gpio2mask(pin); + } else { + plat->data &= ~mpc8xxx_gpio2mask(pin); + } + + out_be32(&(plat->regs->gpdat), plat->data); +#else + if (val) { + setbits_be32(&(plat->regs->gpdat), mpc8xxx_gpio2mask(pin)); + } else { + clrbits_be32(&(plat->regs->gpdat), mpc8xxx_gpio2mask(pin)); + } +#endif + return 0; +} + +static int mpc8xxx_dm_gpio_dir_in(struct udevice *dev, unsigned int gpio) +{ + struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); + + clrbits_be32(&(plat->regs->gpdir), mpc8xxx_gpio2mask(gpio)); + + return 0; +} + +static int mpc8xxx_dm_gpio_dir_out(struct udevice *dev, unsigned int gpio, + int val) +{ + struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); + + mpc8xxx_dm_gpio_set(dev, gpio, val); + + setbits_be32(&(plat->regs->gpdir), mpc8xxx_gpio2mask(gpio)); + + return 0; +} + +static int mpc8xxx_dm_gpio_get(struct udevice *dev, unsigned int gpio) +{ + int ret = 0; + struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); + +#if defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) + uint32_t data_val, out_mask, out_shadow; + + /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs + * defined as output cannot be determined by reading GPDAT register, + * so we use shadow data register instead. The status of input pins + * is determined by reading GPDAT register. + */ + out_mask = in_be32(&plat->regs->gpdir); + + data_val = in_be32(&plat->regs->gpdat) & ~out_mask; + out_shadow = plat->data & out_mask; + + ret = ! !((data_val | out_shadow) & mpc8xxx_gpio2mask(gpio)); +#else + if (in_be32(&plat->regs->gpdat) & mpc8xxx_gpio2mask(gpio)) { + ret = 1; + } else { + ret = 0; + } +#endif + return ret; +} + +static int mpc8xxx_dm_gpio_get_function(struct udevice *dev, unsigned gpio) +{ + int ret = GPIOF_UNUSED; + struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); + + if (in_be32(&plat->regs->gpdir) & mpc8xxx_gpio2mask(gpio)) { + ret = GPIOF_OUTPUT; + } else { + ret = GPIOF_INPUT; + } + return ret; +} + +static const struct udevice_id mpc8xxx_gpio_ids[] = { + {.compatible = "fsl,mpc8349-gpio",}, + {.compatible = "fsl,mpc8572-gpio",}, + {.compatible = "fsl,mpc8610-gpio",}, + {.compatible = "fsl,mpc5121-gpio",}, + {.compatible = "fsl,mpc5125-gpio",}, + {.compatible = "fsl,pq3-gpio",}, + {.compatible = "fsl,qoriq-gpio",}, + {} +}; + +static const struct dm_gpio_ops mpc8xxx_gpio_ops = { + .direction_input = mpc8xxx_dm_gpio_dir_in, + .direction_output = mpc8xxx_dm_gpio_dir_out, + .get_value = mpc8xxx_dm_gpio_get, + .set_value = mpc8xxx_dm_gpio_set, + .get_function = mpc8xxx_dm_gpio_get_function, +}; + +#ifdef SPL_OF_CONTROL +static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev) +{ + int register_address; + struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); + + register_address = + fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); + if (register_address == -1) { + debug("%s: Invalid register offset %d\n", __func__, + register_address); + return -EINVAL; + } + plat->regs = map_physmem(register_address, sizeof(ccsr_gpio_t), + MAP_NOCACHE); + plat->gpio_count = MPC8XXX_GPIO_PINS; + plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, + "bank-name", NULL); + + return 0; +} +#endif + +static int mpc8xxx_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); + + uc_priv->gpio_count = MPC8XXX_GPIO_PINS; + uc_priv->bank_name = plat->bank_name; + + return 0; +} + +U_BOOT_DRIVER(gpio_mpc8xxx) = { + .name = "gpio-mpc8xxx",.id = UCLASS_GPIO,.of_match = + mpc8xxx_gpio_ids,.ops = &mpc8xxx_gpio_ops, +#ifdef SPL_OF_CONTROL + .ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata, +#endif +.platdata_auto_alloc_size = + sizeof(struct mpc8xxx_gpio_platdata),.probe = mpc8xxx_gpio_probe,}; diff --git a/include/dm/platform_data/gpio_mpc8xxx.h b/include/dm/platform_data/gpio_mpc8xxx.h new file mode 100644 index 0000000..37e5241 --- /dev/null +++ b/include/dm/platform_data/gpio_mpc8xxx.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2016 Scalys B.V. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MPC8XXX_GPIO_H +#define _MPC8XXX_GPIO_H + +struct mpc8xxx_gpio_platdata { + const char *bank_name; + ccsr_gpio_t *regs; + int gpio_count; +#if defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) + /* shadowed data register used to work around errata on + * MPC8572 and MPC8535 where it is not possible to read the + * state of an output pin */ + uint32_t data; +#endif +}; + +#endif -- cgit v0.10.2 From 96602f16d3abad2d2871ec2d09194789c540fa47 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Thu, 31 Mar 2016 17:35:05 +0200 Subject: Add support for the Scalys SimC-t10xx SOM diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 0b89157..d6d372f 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -152,6 +152,10 @@ config TARGET_UCP1020 config TARGET_CYRUS bool "Support Varisys Cyrus" +config TARGET_SIMC_T10XX + bool "Support simc-t10xx" + select SUPPORT_SPL + endchoice source "board/freescale/b4860qds/Kconfig" @@ -187,6 +191,7 @@ source "board/freescale/t4rdb/Kconfig" source "board/gdsys/p1022/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/sbc8548/Kconfig" +source "board/scalys/simc-t10xx/Kconfig" source "board/socrates/Kconfig" source "board/varisys/cyrus/Kconfig" source "board/xes/xpedite520x/Kconfig" diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 746ad2a..e0df5ad 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3200,7 +3200,7 @@ struct ccsr_scfg { #if defined(CONFIG_PPC_T1013) || defined(CONFIG_PPC_T1014) ||\ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) ||\ defined(CONFIG_PPC_T1023) || defined(CONFIG_PPC_T1024) ||\ - defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ + defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) #define CONFIG_SYS_MPC8XXX_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x130000) #define CONFIG_SYS_MPC8XXX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000) #define CONFIG_SYS_MPC8XXX_GPIO3_ADDR (CONFIG_SYS_IMMR + 0x132000) diff --git a/arch/powerpc/include/asm/mpc8xxx_gpio.h b/arch/powerpc/include/asm/mpc8xxx_gpio.h index d4a5b7c..1069638 100644 --- a/arch/powerpc/include/asm/mpc8xxx_gpio.h +++ b/arch/powerpc/include/asm/mpc8xxx_gpio.h @@ -6,6 +6,8 @@ #ifndef _POWERPC_ASM_MPC8XXX_GPIO_H #define _POWERPC_ASM_MPC8XXX_GPIO_H +#include + #define MPC8XXX_GPIO_NR(port, pin) ((((port)-1)*32)+((pin)&31)) #define MPC8XXX_GPIO_TO_PORT(gpio) (gpio/32) #define MPC8XXX_GPIO_TO_PIN(gpio) (gpio&31) @@ -86,7 +88,7 @@ static inline int mpc8xxx_gpio_get(uint32_t gpio, int value) break; #endif default: - return; + return -ENODEV; } /* Get inputs */ diff --git a/board/scalys/common/Makefile b/board/scalys/common/Makefile new file mode 100644 index 0000000..dc95801 --- /dev/null +++ b/board/scalys/common/Makefile @@ -0,0 +1,7 @@ +# Copyright 2016 Scalys B.V. +# opensource@scalys.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board_configuration_data.o diff --git a/board/scalys/common/board_configuration_data.c b/board/scalys/common/board_configuration_data.c new file mode 100644 index 0000000..fe96a2e --- /dev/null +++ b/board/scalys/common/board_configuration_data.c @@ -0,0 +1,393 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "board_configuration_data.h" + +DECLARE_GLOBAL_DATA_PTR; + +int add_mac_addressess_to_env(const void* blob) +{ + const char *propname; + const void *value; + int prop_offset, len; + int count = 0; + char mac_string[19], eth_string[10]; + uint8_t mac_address[6]; + + if (fdt_check_header(blob) != 0) { + printf( "Board Configuration Data FDT corrupt\n"); + return -1; + } + + int nodeoff = fdt_path_offset(blob, "/network"); + + if (nodeoff < 0) { + printf("Network node not found\n"); + return -1; + } + for (prop_offset = fdt_first_property_offset(blob, nodeoff); + prop_offset > 0; + prop_offset = fdt_next_property_offset(blob, prop_offset)) { + value = fdt_getprop_by_offset(blob, prop_offset, + &propname, &len); + if (!value) { + return -EINVAL; + } + + memcpy(mac_address, value, 6); + + //ret = fdtdec_get_byte_array( blob, prop_offset, propname, mac_address, 6 ); + + if (count) { + snprintf(eth_string, sizeof(eth_string), "eth%iaddr", count); + } + else { + snprintf(eth_string, sizeof(eth_string), "ethaddr"); + } + + snprintf(mac_string, sizeof(mac_string), + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_address[0], mac_address[1], mac_address[2], + mac_address[3], mac_address[4], mac_address[5] + ); + + printf("%s : [ %s ]\n", propname, mac_string ); + + setenv( eth_string, mac_string); + + count++; + + } + printf("Done reading BCD\n"); + + return 0; +} + +const void* get_boardinfo_eeprom(void) +{ + uint32_t bcd_data_lenght; + uint8_t *bcd_data = NULL; + uint32_t calculated_crc, received_crc; + int dtb_length; + int old_i2c_bus; + int ret = 0; + + old_i2c_bus = i2c_get_bus_num(); + + /* Set the selected I2C interface to the correct bus */ + i2c_set_bus_num(BCD_I2C_BUS); + + /* Read the last 4 bytes to determine the lenght of the DTB data */ + ret = i2c_read(BCD_I2C_ADDRESS, (BCD_EEPROM_SIZE-4), 2, (uint8_t*) &bcd_data_lenght, 4 ); + if (ret != 0) { + debug("Error reading bcd length\n"); + errno = -ENODEV; + goto err_no_free; + } + + /* Convert lenght from big endianess to architecture endianess */ + bcd_data_lenght = ntohl(bcd_data_lenght); + debug("bcd_data_lenght = %i\n", bcd_data_lenght ); + + if (bcd_data_lenght > BCD_EEPROM_SIZE ) { + debug("%02x %02x %02x %02x\n", + ( (uint8_t*) &bcd_data_lenght)[0], + ( (uint8_t*) &bcd_data_lenght)[1], + ( (uint8_t*) &bcd_data_lenght)[2], + ( (uint8_t*) &bcd_data_lenght)[3] ); + errno = -EMSGSIZE; + goto err_no_free; + } + + /* Allocate, and verify memory for the BCD data */ + bcd_data = (uint8_t*) malloc(bcd_data_lenght); + if (bcd_data == NULL) { + debug("Error locating memory for BCD data\n"); + goto err_no_free; + } + debug("Allocated memory for BCD data\n"); + + /* Read the DTB BCD data to memory */ + ret = i2c_read(BCD_I2C_ADDRESS, (BCD_EEPROM_SIZE-bcd_data_lenght), 2, (uint8_t*) bcd_data, bcd_data_lenght ); + debug("Read data from I2C bus\n"); + + if (ret != 0) { + debug("Error reading complete BCD data from EEPROM\n"); + errno = -ENOMEM; + goto err_free; + } + dtb_length = bcd_data_lenght - BCD_LENGTH_SIZE - BCD_HASH_SIZE; + + /* Calculate CRC on read DTB data */ + calculated_crc = crc32( 0, bcd_data, dtb_length); + + /* Received CRC is packed after the DTB data */ + received_crc = *((uint32_t*) &bcd_data[dtb_length]); + + /* Convert CRC from big endianess to architecture endianess */ + received_crc = ntohl(received_crc); + + if (calculated_crc != received_crc) { + debug("Checksum error. expected %08x, got %08x\n", + calculated_crc, received_crc); + free(bcd_data); + errno = -EBADMSG; + goto err_free; + } + + /* Everything checked out, return the BCD data. + * The caller is expected to free this data */ + return bcd_data; + +err_free: + /* free the allocated buffer */ + free(bcd_data); + +err_no_free: + /* Set the selected I2C interface back to the original bus */ + i2c_set_bus_num(old_i2c_bus); + + return NULL; +} + +#ifndef CONFIG_SPL_BUILD + +#ifndef CONFIG_CMD_FDT_MAX_DUMP +#define CONFIG_CMD_FDT_MAX_DUMP 64 +#endif + +/* + * Heuristic to guess if this is a string or concatenated strings. + */ + +static int is_printable_string(const void *data, int len) +{ + const char *s = data; + + /* zero length is not */ + if (len == 0) + return 0; + + /* must terminate with zero or '\n' */ + if (s[len - 1] != '\0' && s[len - 1] != '\n') + return 0; + + /* printable or a null byte (concatenated strings) */ + while (((*s == '\0') || isprint(*s) || isspace(*s)) && (len > 0)) { + /* + * If we see a null, there are three possibilities: + * 1) If len == 1, it is the end of the string, printable + * 2) Next character also a null, not printable. + * 3) Next character not a null, continue to check. + */ + if (s[0] == '\0') { + if (len == 1) + return 1; + if (s[1] == '\0') + return 0; + } + s++; + len--; + } + + /* Not the null termination, or not done yet: not printable */ + if (*s != '\0' || (len != 0)) + return 0; + + return 1; +} + +/* + * Print the property in the best format, a heuristic guess. Print as + * a string, concatenated strings, a byte, word, double word, or (if all + * else fails) it is printed as a stream of bytes. + */ +static void print_data(const void *data, int len) +{ + int j; + + /* no data, don't print */ + if (len == 0) + return; + + /* + * It is a string, but it may have multiple strings (embedded '\0's). + */ + if (is_printable_string(data, len)) { + puts("\""); + j = 0; + while (j < len) { + if (j > 0) + puts("\", \""); + puts(data); + j += strlen(data) + 1; + data += strlen(data) + 1; + } + puts("\""); + return; + } + + if ((len %4) == 0) { + if (len > CONFIG_CMD_FDT_MAX_DUMP) + printf("* 0x%p [0x%08x]", data, len); + else { + const __be32 *p; + + printf("<"); + for (j = 0, p = data; j < len/4; j++) + printf("0x%08x%s", fdt32_to_cpu(p[j]), + j < (len/4 - 1) ? " " : ""); + printf(">"); + } + } else { /* anything else... hexdump */ + if (len > CONFIG_CMD_FDT_MAX_DUMP) + printf("* 0x%p [0x%08x]", data, len); + else { + const u8 *s; + + printf("["); + for (j = 0, s = data; j < len; j++) + printf("%02x%s", s[j], j < len - 1 ? " " : ""); + printf("]"); + } + } +} + +/* + * Recursively print (a portion of) the working_fdt. The depth parameter + * determines how deeply nested the fdt is printed. + */ +#define MAX_LEVEL 4 +static int bcd_fdt_print(const void* address, int depth) +{ + static char tabs[MAX_LEVEL+1] = + "\t\t\t\t\t"; + const void *nodep; /* property node pointer */ + int nodeoffset; /* node offset from libfdt */ + int nextoffset; /* next node offset from libfdt */ + uint32_t tag; /* tag */ + int len; /* length of the property */ + int level = 0; /* keep track of nesting level */ + const struct fdt_property *fdt_prop; + const char *pathp; + + nodeoffset = fdt_path_offset (address, "/"); + if (nodeoffset < 0) { + /* + * Not found or something else bad happened. + */ + printf ("libfdt fdt_path_offset() returned %s\n", + fdt_strerror(nodeoffset)); + return 1; + } + + /* + * The user passed in a node path and no property, + * print the node and all subnodes. + */ + while(level >= 0) { + tag = fdt_next_tag(address, nodeoffset, &nextoffset); + switch(tag) { + case FDT_BEGIN_NODE: + pathp = fdt_get_name(address, nodeoffset, NULL); + if (level <= depth) { + if (pathp == NULL) + pathp = "/* NULL pointer error */"; + if (*pathp == '\0') + pathp = "/"; /* root is nameless */ + printf("%s%s {\n", + &tabs[MAX_LEVEL - level], pathp); + } + level++; + if (level >= MAX_LEVEL) { + printf("Nested too deep, aborting.\n"); + return 1; + } + break; + case FDT_END_NODE: + level--; + if (level <= depth) + printf("%s};\n", &tabs[MAX_LEVEL - level]); + if (level == 0) { + level = -1; /* exit the loop */ + } + break; + case FDT_PROP: + fdt_prop = fdt_offset_ptr(address, nodeoffset, + sizeof(*fdt_prop)); + pathp = fdt_string(address, + fdt32_to_cpu(fdt_prop->nameoff)); + len = fdt32_to_cpu(fdt_prop->len); + nodep = fdt_prop->data; + if (len < 0) { + printf ("libfdt fdt_getprop(): %s\n", + fdt_strerror(len)); + return 1; + } else if (len == 0) { + /* the property has no value */ + if (level <= depth) + printf("%s%s;\n", + &tabs[MAX_LEVEL - level], + pathp); + } else { + if (level <= depth) { + printf("%s%s = ", + &tabs[MAX_LEVEL - level], + pathp); + print_data (nodep, len); + printf(";\n"); + } + } + break; + case FDT_NOP: + printf("%s/* NOP */\n", &tabs[MAX_LEVEL - level]); + break; + case FDT_END: + return 1; + default: + if (level <= depth) + printf("Unknown tag 0x%08X\n", tag); + return 1; + } + nodeoffset = nextoffset; + } + return 0; +} + +int do_bcdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const void* bcd_dtc_blob; + int ret = 0; + + bcd_dtc_blob = get_boardinfo_eeprom(); + + if (bcd_dtc_blob != NULL) { + bcd_fdt_print(bcd_dtc_blob, 4); + } + + return ret; +} + +/* U_BOOT_CMD(name,maxargs,repeatable,command,"usage","help") */ +U_BOOT_CMD( + bcdinfo, + 1, + 1, + do_bcdinfo, + "Show the Board Configuration Data (stored in eeprom)", + "" +); +#endif \ No newline at end of file diff --git a/board/scalys/common/board_configuration_data.h b/board/scalys/common/board_configuration_data.h new file mode 100644 index 0000000..14cbec0 --- /dev/null +++ b/board/scalys/common/board_configuration_data.h @@ -0,0 +1,22 @@ +#ifndef _BCD_H +#define _BCD_H + +#define BCD_LENGTH_SIZE 4 +#define BCD_HASH_SIZE 4 + +#ifndef BCD_I2C_BUS +#define BCD_I2C_BUS 0 +#endif + +#ifndef BCD_I2C_ADDRESS +#define BCD_I2C_ADDRESS 0x51 +#endif + +#ifndef BCD_EEPROM_SIZE +#define BCD_EEPROM_SIZE 0x10000 +#endif + +const void* get_boardinfo_eeprom(void); +int add_mac_addressess_to_env(const void* blob); + +#endif /* _BCD_H */ diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig new file mode 100644 index 0000000..77ebe76 --- /dev/null +++ b/board/scalys/simc-t10xx/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SIMC_T10XX + +config SYS_BOARD + string + default "simc-t10xx" + +config SYS_VENDOR + string + default "scalys" + +config SYS_CONFIG_NAME + string + default "simc-t10xx" + +endif diff --git a/board/scalys/simc-t10xx/Makefile b/board/scalys/simc-t10xx/Makefile new file mode 100644 index 0000000..83ac551 --- /dev/null +++ b/board/scalys/simc-t10xx/Makefile @@ -0,0 +1,19 @@ +# Copyright 2016 Scalys B.V. +# opensource@scalys.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +UBOOTINCLUDE += -I$(srctree)/board/$(VENDOR)/common/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += simc-t10xx.o +obj-y += eth.o +obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o +obj-y += dragonfruit.o \ No newline at end of file diff --git a/board/scalys/simc-t10xx/ddr.c b/board/scalys/simc-t10xx/ddr.c new file mode 100644 index 0000000..ca5407e --- /dev/null +++ b/board/scalys/simc-t10xx/ddr.c @@ -0,0 +1,135 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ +#define DDR_RST_N MPC8XXX_GPIO_NR(2, 12) + +/* MT41K512M8RH-125 */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 0x100000000ULL, + .capacity = 0x200000000ULL, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 1, + .n_row_addr = 16, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = EDC_ECC, + .burst_lengths_bitmask = 0x0c, + .tckmin_x_ps = 1250, + .tckmax_ps = 1499, + .caslat_x = (1 << 11), + .taa_ps = 13750, + .trcd_ps = 13750, + .trp_ps = 13750, + .tras_ps = 35000, + .trc_ps = 48750, + .tfaw_ps = 30000, + .twr_ps = 15000, + .trfc_ps = 260000, + .trrd_ps = 6000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 70200000, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + + if (ctrl_num != 0) { + printf("Only 1 memory controller supported, but %i requested\n", + ctrl_num); + return; + } + + if (pdimm == NULL ) { + printf("Error, no valid dimm pararmeter supplied\n"); + return; + } + + if (!pdimm->n_ranks) { + printf("No ranks in dimm parameters. Configuration error?\n"); + return; + } + + /* set odt_rd_cfg and odt_wr_cfg. */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_wr_cfg = 4; + } + + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 13; + popts->wrlvl_start = 7; /* 7/8 clock delay */ + popts->wrlvl_ctl_2 = 0x06070809; + popts->wrlvl_ctl_3 = 0x0d0f0a09; + + popts->ddr_cdr1 = 0x800c0000; + popts->ddr_cdr2 = 0x00000001; + + /* Clock is launched 1/4 applied cycle after address/command */ + popts->clk_adjust = 4; +} + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Soldered-down discrete DDR3"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + +#ifdef GPIO_IN_SPL_WORKING + gpio_request(DDR_RST_N, "DDR_RST_N"); + gpio_direction_output(DDR_RST_N, 1); +#else + mpc8xxx_gpio_set(DDR_RST_N,1); +#endif + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + /* DDR has been initialised by SPL loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + + return dram_size; +} diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c new file mode 100644 index 0000000..5c45020 --- /dev/null +++ b/board/scalys/simc-t10xx/dragonfruit.c @@ -0,0 +1,89 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include "dragonfruit.h" + + +/* + * SERDER MUX Configuration pins: + * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL + * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL + * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL + * + * MUX_SER0_1_SEL + * 0: SERDES A => Slot1, lane 0 + * SERDES B => Slot1, lane 1 + * 1: SERDES A => CS4315 retimer => SFP+ 0 + * SERDES B => CS4315 retimer => SFP+ 1 + * + * MUX_SER2_3_SEL + * 0: SERDES C => Slot1, lane 2 + * SERDES D => Slot1, lane 3 + * 1: SERDES C => QSFP+ 2 + * SERDES D => QSFP+ 3 + * + * SERDES E => Slot 4, lane 0 + * + * MUX_SER5_6_SEL + * 0: SERDES F => SLOT4, lane 1 + * SERDES G => SLOT4, lane 2 + * 1: SERDES F => SLOT2 + * SERDES G => SLOT3 + * + * SERDES H => Slot 4, lane 3 + */ + +#define MUX_SER0_1_SEL MPC8XXX_GPIO_NR(2, 25) +#define MUX_SER2_3_SEL MPC8XXX_GPIO_NR(2, 26) +#define MUX_SER5_6_SEL MPC8XXX_GPIO_NR(2, 27) +#define SERDES_CLK_OE MPC8XXX_GPIO_NR(2, 29) + +int scalys_carrier_setup_muxing(int serdes_config) +{ + int ret = 0; + + ret = gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel"); + if (ret != 0) { + printf("gpio request failed(%i)\n", ret); + } + gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel"); + gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel"); + gpio_request(SERDES_CLK_OE, "serdes_clk_oe"); + + switch(serdes_config){ + case 0x06: + /* A-D: PCIe1 (5/2.5G); E: PCIe2 (5/2.5G); + * F: PCIe3 (5/2.5G); G: PCIe4 (5/2.5); H: SATA.1 (3/1.5G) */ + gpio_direction_output(MUX_SER0_1_SEL, 0); + gpio_direction_output(MUX_SER2_3_SEL, 0); + gpio_direction_output(MUX_SER5_6_SEL, 1); + + break; + case 0x86: + case 0x88: + /* A: PCIe1 (5/2.5G); B: sg.m3; C: sg.m1; D: sg.m2; + * E: PCIe2 (5/2.5G); F:PCIe3 (5/2.5G); G: SATA2(3/1.5G); + * H: SATA1(3/1.5G) */ + gpio_direction_output(MUX_SER0_1_SEL, 1); + gpio_direction_output(MUX_SER2_3_SEL, 1); + gpio_direction_output(MUX_SER5_6_SEL, 1); + + break; + default: + printf("Unsupported SERDES configuration (%02x)\n", serdes_config); + } + + /* Enable serdes clock */ + gpio_direction_output(SERDES_CLK_OE, 1); + + return ret; +} \ No newline at end of file diff --git a/board/scalys/simc-t10xx/dragonfruit.h b/board/scalys/simc-t10xx/dragonfruit.h new file mode 100644 index 0000000..900b2e4 --- /dev/null +++ b/board/scalys/simc-t10xx/dragonfruit.h @@ -0,0 +1,6 @@ +#ifndef _DRAGON_FRUIT_H +#define _DRAGON_FRUIT_H + +int scalys_carrier_setup_muxing(int serdes_config); + +#endif /* _DRAGON_FRUIT_H */ \ No newline at end of file diff --git a/board/scalys/simc-t10xx/eth.c b/board/scalys/simc-t10xx/eth.c new file mode 100644 index 0000000..2533137 --- /dev/null +++ b/board/scalys/simc-t10xx/eth.c @@ -0,0 +1,140 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../../freescale/common/fman.h" + +uint8_t sfp_phy_config[][2] = { + { 0x1b, 0x90 }, + { 0x1b, 0x84 }, + { 0x09, 0x0F }, + { 0x09, 0x00 }, + { 0x00, 0x81 }, + { 0x00, 0x40 }, +}; + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + uint8_t i2c_data; + int ret; + int phy_addr = 0; + + uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; + uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; + uint32_t regval; + + printf("Initializing Fman\n"); + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* Remove reset from Ethernet PHY's + * IFC_PERR_B : GPIO2_15 : eth1_reset + * IFC_CS_N2 : GPIO2_11 : eth2_reset */ +// gpio_set_value(2, 0); + + /* Clear outputs to activate reset */ + regval = in_be32(gpio2_gpdat); + regval &= ~((0x80000000 >> 11 ) | (0x80000000 >> 15)); + out_be32(gpio2_gpdat, regval); + + /* Set outputs to output mode */ + regval = in_be32(gpio2_gpdir); + regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15)); + out_be32(gpio2_gpdir, regval); + + /* Wait for 10 ms to to meet reset timing */ + mdelay(10); + + /* Set outputs to de-activate reset */ + regval = in_be32(gpio2_gpdat); + regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15)); + out_be32(gpio2_gpdat, regval); + + + /* Remove SFP TX_disable */ + i2c_set_bus_num(0); + i2c_data = 0x3b; + ret = i2c_write(0x22, 0x0E, 1, &i2c_data, 1); + + mdelay(100); + + i2c_set_bus_num(3); + + for (phy_addr=0; phy_addr<4; phy_addr++) { + i2c_data = (1 << phy_addr); + ret = i2c_write(0x70, 0, 1, &i2c_data, 1); + if (ret) { + printf("Error Setting SFP i2c MUX\n"); + break; + } + + for ( i = 0; i < 6; i++) { + ret = i2c_write(0x56, sfp_phy_config[i][0], 1, &(sfp_phy_config[i][1]), 1); + if (ret) { + printf("Error sfp phy(%i:%i):%02x to address %02x\n", phy_addr, i, sfp_phy_config[i][1],sfp_phy_config[i][0]); + break; + } + } + } + + /* Two external pin interfaces + * MAC1|MAC2|MAC3 SGMII interface + * MAC4|MAC5 EC1|EC2 RGMII interface + */ + + /* + * Program on board RGMII, SGMII PHY addresses. + */ + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_RGMII: + if (FM1_DTSEC4 == i) + phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; + if (FM1_DTSEC5 == i) + phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; + case PHY_INTERFACE_MODE_QSGMII: + fm_info_set_phy_address(i, 0); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + case PHY_INTERFACE_MODE_SGMII: + printf("TODO, add phy interface to SGMII\n"); + fm_info_set_phy_address(i, PHY_INTERFACE_MODE_NONE); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + //fm_info_set_phy_address(i, 0); + break; + } + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + } + cpu_eth_init(bis); +#endif + return pci_eth_init(bis); +} diff --git a/board/scalys/simc-t10xx/law.c b/board/scalys/simc-t10xx/law.c new file mode 100644 index 0000000..c3b5e85 --- /dev/null +++ b/board/scalys/simc-t10xx/law.c @@ -0,0 +1,32 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); \ No newline at end of file diff --git a/board/scalys/simc-t10xx/pci.c b/board/scalys/simc-t10xx/pci.c new file mode 100644 index 0000000..ab9edbb --- /dev/null +++ b/board/scalys/simc-t10xx/pci.c @@ -0,0 +1,77 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + + uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000; + uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008; + uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; + uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; + uint32_t regval; + + debug("%s\n", __FUNCTION__); + + //TODO, when present pins are available on the board, use them to enable only active slots + /* + * IRQ[0-3] : PCIe present detect signals + * IRQ[0] : SLOT1_PRSNT2_N : XXX + * IRQ[1] : SLOT2_PRSNT2_N : XXX + * IRQ[2] : SLOT3_PRSNT2_N : XXX + * IRQ[3] : SLOT4_PRSNT2_N : XXX + * + * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 + * IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N + * IFC_CS_N5 : GPIO1_IO10 : PCIe SLOT2_REFCLK_OE_N + * IFC_CS_N6 : GPIO1_IO11 : PCIe SLOT3_REFCLK_OE_N + * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N + */ + + /* Set output to 0 to enable reference clocks */ + regval = in_be32(gpio1_gpdat); + regval &= ~( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) ); + out_be32(gpio1_gpdat, regval); + + /* Set Enable outputs*/ + regval = in_be32(gpio1_gpdir); + regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) ); + out_be32(gpio1_gpdir, regval); + + + + /* Remove reset from PCIe devices */ + + /* Set IFC_PAR0 to output mode */ + regval = in_be32(gpio2_gpdir); + regval |= ( 0x80000000 >> 13 ); + out_be32(gpio2_gpdir, regval); + + /* Set output to 1 to clear reset */ + regval = in_be32(gpio2_gpdat); + regval |= ( 0x80000000 >> 13 ); + out_be32(gpio2_gpdat, regval); + + /* Wait for 100 ms to allow the PCIe device to become ready */ + mdelay(100); + + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/scalys/simc-t10xx/simc-t10xx.c b/board/scalys/simc-t10xx/simc-t10xx.c new file mode 100644 index 0000000..f5b8a2c --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10xx.c @@ -0,0 +1,147 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dragonfruit.h" +#include + + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: simc-t10xx\n" ); + return 0; +} + +int misc_init_r(void) +{ + const void* bcd_dtc_blob; + int serdes_config; + ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int ret; + /* + * Initialize and set the LED's on the module to indicate u-boot is alive + * IFC_A30 : led green : GPIO2_30 + * IFC_A31 : led red : GPIO2_31 + */ + #define MODULE_LED_RED MPC8XXX_GPIO_NR(2, 31) + #define MODULE_LED_GREEN MPC8XXX_GPIO_NR(2, 30) + gpio_request(MODULE_LED_RED, "module_led_red"); + gpio_request(MODULE_LED_GREEN, "module_led_green"); + + gpio_direction_output(MODULE_LED_RED, 0); + gpio_direction_output(MODULE_LED_GREEN, 1); + + /* SERDES configuration is determined boot time through the RCW config. + * It is located in the fourth RCW word (bit 128-135 of the RCW). */ + serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24); + scalys_carrier_setup_muxing(serdes_config); + + bcd_dtc_blob = get_boardinfo_eeprom(); + if (bcd_dtc_blob != NULL) { + /* Board Configuration Data is intact, ready for parsing */ + ret = add_mac_addressess_to_env(bcd_dtc_blob); + if (ret != 0) { + printf("Error adding BCD data to environement\n"); + } + } + + return 0; +} + +/* Platform data for the GPIOs */ +static const struct mpc8xxx_gpio_platdata gpio_platdata[] = { + { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO1_ADDR, + .bank_name = "GPIO1_" }, + { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO2_ADDR, + .bank_name = "GPIO2_" }, + { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO3_ADDR, + .bank_name = "GPIO3_" }, + { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO4_ADDR, + .bank_name = "GPIO4_" }, +}; + +U_BOOT_DEVICES(mpc8xxx_gpios) = { + { "gpio-mpc8xxx", &gpio_platdata[0] }, + { "gpio-mpc8xxx", &gpio_platdata[1] }, + { "gpio-mpc8xxx", &gpio_platdata[2] }, + { "gpio-mpc8xxx", &gpio_platdata[3] }, +}; + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + debug( "ft_board_setup\n" ); + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + debug( "fdt_fixup_memory\n" ); + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + debug( "pci_of_setup\n" ); + FT_FSL_PCI_SETUP; +#endif + debug( "fdt_fixup_liodn\n" ); + fdt_fixup_liodn(blob); + +#ifdef CONFIG_HAS_FSL_DR_USB + debug( "fdt_fixup_dr_usb\n" ); + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + debug( "fdt_fixup_fman_ethernet\n" ); + fdt_fixup_fman_ethernet(blob); +#endif + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + struct fsl_esdhc_cfg *cfg; + + cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); + cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + cfg->sdhc_clk = gd->arch.sdhc_clk; + cfg->max_bus_width = 4; + return fsl_esdhc_initialize(bis, cfg); + + return 0; +} + +#if 0 +void board_detail(void) +{ + do_bcdinfo(); +} +#endif \ No newline at end of file diff --git a/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg new file mode 100644 index 0000000..59e2c66 --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg @@ -0,0 +1,43 @@ +#PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 (LAW 13) +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure IFC controller +# (IFC_CSPR1) +09124010 ff8000c3 +# IFC_AMASK1 +#091240A0 C0000000 +#ECC DISABLED: +# 4K pages: 09124130 0110a200 +09124130 0108a100 +# IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND +091241c0 181c080c +091241c4 3850141a +091241c8 03008028 +091241cc 28000000 +#Flush PBL data (Wait 0xFFFFF cycles ) +091380c0 000fffff \ No newline at end of file diff --git a/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg b/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg new file mode 100644 index 0000000..1ddbe0c --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg @@ -0,0 +1,17 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +#120C0015 15000000 00000000 00000000 +#06000000 00C00002 E8104000 21000000 +#00000000 CAFEBABE 00000000 00030ffc +#00000314 0014500C 00000000 00000000 +# +#120C0015 15000000 00000000 00000000 +#06000000 00000002 E8105000 21000000 +#00000000 CAFEBABE 00000000 00230FFC +#00000714 0014500C 00000000 00000000 + +120C0015 15000000 00000000 00000000 +86000000 00000002 E8104000 21000000 +00000000 CAFEBABE 00000000 00030FFC +00000314 0014500C 00000000 00000000 diff --git a/board/scalys/simc-t10xx/spl.c b/board/scalys/simc-t10xx/spl.c new file mode 100644 index 0000000..3675169 --- /dev/null +++ b/board/scalys/simc-t10xx/spl.c @@ -0,0 +1,112 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + // TODO i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/scalys/simc-t10xx/tlb.c b/board/scalys/simc-t10xx/tlb.c new file mode 100644 index 0000000..1890034 --- /dev/null +++ b/board/scalys/simc-t10xx/tlb.c @@ -0,0 +1,123 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_PCI + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), +#endif + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/T1_simc-t10xx_nand_defconfig b/configs/T1_simc-t10xx_nand_defconfig new file mode 100644 index 0000000..fb14e16 --- /dev/null +++ b/configs/T1_simc-t10xx_nand_defconfig @@ -0,0 +1,40 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_SIMC_T10XX=y + + +CONFIG_HUSH_PARSER=y + +CONFIG_CMD_ECHO=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_GPIO=y + +CONFIG_CMD_FLASH=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_IMLS=n +CONFIG_CMD_I2C=y + +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB=y + +CONFIG_OF_LIBFDT=y +CONFIG_SPL_OF_LIBFDT=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_OF_BOARD_SETUP=y + +CONFIG_CMD_DM=y +CONFIG_SPL_DM=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_MPC8XXX_GPIO=y + +CONFIG_SYS_MALLOC_F=n diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h new file mode 100644 index 0000000..9e7b54b --- /dev/null +++ b/include/configs/simc-t10xx.h @@ -0,0 +1,722 @@ +/* + * Copyright 2016 Scalys B.V. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SIMC_T10XX_H +#define __SIMC_T10XX_H + +/* + * SIMC-T10xx board configuration file + */ +#define CONFIG_PHYS_64BIT +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) /* MT29F8G08ABBCAH4*/ + +/* + * System and DDR clock + */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* 66.67MHz */ +#define CONFIG_DDR_CLK_FREQ 133333333 /* 133.33MHz */ + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg + +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT + +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x30001000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif /* CONFIG_SPL_BUILD */ + +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif /* CONFIG_NAND */ + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +/* High Level Configuration Options */ +#define CONFIG_E500 /* BOOKE e500 family */ +#include +#define CONFIG_BOOKE +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ + + +/* #define CONFIG_DEEP_SLEEP */ /* support deep sleep */ +#define CONFIG_SILENT_CONSOLE + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif /* CONFIG_RESET_VECTOR_ADDRESS */ + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + + +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCI_INDIRECT_BRIDGE + + +/* The number of available PCI controllers depends on the RCW */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ + +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x100000 /* Refer to mtdparts */ +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif /* CONFIG_SPIFLASH */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC + +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0x0BADC0DE +#endif /* CONFIG_DDR_ECC */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +/* #define CONFIG_SYS_DRAM_TEST Executes a memoty test at U-Boot start */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST + +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif /* CONFIG_RAMBOOT_PBL */ +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR (2) +#define CONFIG_CHIP_SELECTS_PER_CTRL (4) + +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_FSL_DDR3 + +#define CONFIG_SYS_SDRAM_SIZE 8192 /* In MByte, for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) + +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC on encode */ \ + CSOR_NAND_ECC_DEC_EN | /* ECC on decode */ \ + CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \ + CSOR_NAND_RAL_3 | /* RAL = 3Byes */ \ + CSOR_NAND_PGS_2K | /* Page Size = 2K */ \ + CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \ + CSOR_NAND_PB(64)) /* Pages Per Block = 64 */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) + +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) + +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) + +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +/*#define CONFIG_CMD_NAND*/ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +/*#define CONFIG_BOARD_EARLY_INIT_R*/ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +#define CONFIG_SPL_GPIO_SUPPORT + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) + +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif + +/* Use the HUSH parser */ +/*#define CONFIG_SYS_HUSH_PARSER*/ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ + + +/* new uImage format support */ +#if 0 +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#endif + + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C3_SPEED 400000 +#define CONFIG_SYS_FSL_I2C4_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 4, Base address 203000 */ +#ifdef CONFIG_PCIE4 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 +#define CONFIG_E1000_SPI +#define CONFIG_CMD_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 + +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA + +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_DOS_PARTITION +#endif + + +#define CONFIG_USB_EHCI_FSL +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif /* CONFIG_USB_EHCI*/ + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +/* QE Connector is available on SiMC-T10x but not part of this development */ +#ifdef QE_CONNCECTOR +#define CONFIG_QE +#define CONFIG_U_QE +#endif + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (0x140000) /* Refer to mtdparts */ +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif + + +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHY_MARVELL +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x00 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x01 + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#endif + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 1000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +#define CONFIG_CMD_BOOTZ + +#define CONFIG_SYS_NO_FLASH + + +#ifdef CONFIG_SECURE_BOOT +#include +#define CONFIG_CMD_BLOB +#endif + +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +/* #define CONFIG_UBI_SILENCE_MSG */ +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_SPI_FLASH +#define CONFIG_FSL_ESPI + +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION + +/*#define CONFIG_CMD_SF*/ +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.0" + +#define MTDPARTS_DEFAULT \ + "mtdparts=fff800000.flash:," \ + "1M@0x0(u-boot)," \ + "256k(env)," \ + "256k(fman_ucode)," \ + "0x3fdc0000(ubipart)," \ + "1M@0x3ff00000(bbt)ro}" + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define CONFIG_BOOTDELAY 3 /*-1 disables auto-boot*/ +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=" \ + "fsl_ddr:bank_intlv=null;"\ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + \ + "ethaddr=00:00:00:ca:fe:00\0" \ + "eth1addr=00:00:00:ca:fe:01\0" \ + "eth2addr=00:00:00:ca:fe:02\0" \ + "eth3addr=00:00:00:ca:fe:03\0" \ + \ + "autoload=no\0" \ + "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \ + "TFTP_PATH=\0" \ + \ + "mtdids=nand0=fff800000.flash\0" \ + "mtdparts=mtdparts=fff800000.flash:1M@0x0(u-boot),256k(env),256k(fman_ucode),0x3fdc0000(ubipart),1M@0x3ff00000(bbt)ro\0" \ + \ + "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \ + "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \ + "i2c mw 0x2e 0x5f 0xc8;i2c mw 0x2e 0x60 0xc8;i2c mw 0x2e 0x61 0xc8;" \ + "i2c mw 0x2e 0x30 0x20;i2c mw 0x2e 0x31 0x20;i2c mw 0x2e 0x32 0x20;\0"\ + \ + "update-uboot=dhcp; tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin; if test $? = \"0\"; then nand erase.part u-boot; nand write ${loadaddr} 0 ${filesize};fi\0" \ + "update-uboot-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin;" \ + "nand erase.part u-boot;" \ + "nand write ${loadaddr} u-boot ${filesize};" \ + "\0" \ + \ + "update-fman-ucode-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} fsl_fman_ucode_t1040_r1.1_106_4_17.bin;" \ + "nand erase.part fman_ucode;" \ + "nand write ${loadaddr} fman_ucode ${filesize};" \ + "\0" \ + \ + "update-ubi-rootfs="\ + "dhcp;" \ + "ubi part ubipart;" \ + "if test $? = \"0\"; then " \ + "tftp ${TFTP_PATH}/fsl-image-core-simc-t1022-tcb-02.ubifs;" \ + "if test $? = \"0\"; then " \ + "ubi write ${loadaddr} rootfs ${filesize};" \ + "fi;" \ + "fi;" \ + "\0" \ + \ + "ubiboot=" \ + "ubi part ubipart;" \ + "ubifsmount ubi0:rootfs;" \ + "ubifsload ${fitaddr} /boot/fitImage.itb;" \ + "run set_ubiboot_args;" \ + "bootm ${fitaddr}#conf@1" \ + "\0" \ + \ + "set_ubiboot_args=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=3 ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0" \ + \ + "netboot=dhcp; tftp ${fitaddr} ${TFTP_PATH}/fitImage.itb; bootm ${fitaddr}#conf@1\0" \ + \ + "bootcmd=run setfans; usb start; run ubiboot\0" \ + \ + "bootargs_sata=rootfstype=ext3 root=/dev/sda1\0" \ + "bootargs=console=ttyS0,115200 rootwait panic=10\0" \ + +#endif /* SIMC_T10XX_H */ -- cgit v0.10.2 From 2e45982ef5d5ee30c29d7a2c1da23b74903cf658 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Fri, 20 May 2016 10:14:13 +0200 Subject: Add missing T1040 serdes configurations diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c index d5dccd5..5e3e463 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c @@ -27,6 +27,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1}, + [0x81] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2, + PCIE2, PCIE2, PCIE4, SATA1}, [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE3, PCIE4, SATA1}, [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, @@ -37,6 +39,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1}, [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2, PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5}, + [0x8E] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2, + AURORA, PCIE3, SGMII_SW1_MAC4, SATA1}, [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, -- cgit v0.10.2 From 99aab114e21c41535f7d0c65cc025ab768379de0 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Wed, 25 May 2016 17:09:58 +0200 Subject: add CONFIG_ZERO_BOOTDELAY_CHECK flag diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h index 9e7b54b..8c6f7be 100644 --- a/include/configs/simc-t10xx.h +++ b/include/configs/simc-t10xx.h @@ -649,8 +649,10 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 3 /*-1 disables auto-boot*/ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* Also check for boot interruption, when bootdelay is zero */ #define CONFIG_BAUDRATE 115200 + #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2 From 85ed20e27529a442e4e4bd59e4aaad31920e49ae Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Tue, 31 May 2016 11:04:22 +0200 Subject: Fix double free on checkum error diff --git a/board/scalys/common/board_configuration_data.c b/board/scalys/common/board_configuration_data.c index fe96a2e..b6374da 100644 --- a/board/scalys/common/board_configuration_data.c +++ b/board/scalys/common/board_configuration_data.c @@ -143,7 +143,6 @@ const void* get_boardinfo_eeprom(void) if (calculated_crc != received_crc) { debug("Checksum error. expected %08x, got %08x\n", calculated_crc, received_crc); - free(bcd_data); errno = -EBADMSG; goto err_free; } -- cgit v0.10.2 From 1d91100dcbe35700a27621c1205d09f4945882c7 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Fri, 20 May 2016 10:18:13 +0200 Subject: Add T1040 support for scalys simc-t10xx diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig index 77ebe76..2b8d1a4 100644 --- a/board/scalys/simc-t10xx/Kconfig +++ b/board/scalys/simc-t10xx/Kconfig @@ -11,5 +11,63 @@ config SYS_VENDOR config SYS_CONFIG_NAME string default "simc-t10xx" + +config RAMBOOT_PBL + bool + default y + +config SPL_FSL_PBL + bool + default y + +choice + prompt "Bootsource" + +config NAND + bool + prompt "NAND boot" + default y + help + Select NAND as the bootsource + +endchoice + +choice + prompt "SYSCLK frequency" + default SYS_CLK_FREQ_100 + +config SYS_CLK_FREQ_66 + bool + prompt "66.6 MHz" + +config SYS_CLK_FREQ_100 + bool + prompt "100 MHz" + +endchoice + +choice + prompt "CPU type" + default PPC_T1040 + help + Select the exact type of CPU which is used on the version of the simc-t10xx module + +config PPC_T1020 + bool + prompt "T1020" + +config PPC_T1022 + bool + prompt "T1040" + +config PPC_T1040 + bool + prompt "T1040" + +config PPC_T1042 + bool + prompt "T1042" + +endchoice endif diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c index 5c45020..1656054 100644 --- a/board/scalys/simc-t10xx/dragonfruit.c +++ b/board/scalys/simc-t10xx/dragonfruit.c @@ -68,8 +68,10 @@ int scalys_carrier_setup_muxing(int serdes_config) gpio_direction_output(MUX_SER5_6_SEL, 1); break; + case 0x81: case 0x86: case 0x88: + case 0x89: /* A: PCIe1 (5/2.5G); B: sg.m3; C: sg.m1; D: sg.m2; * E: PCIe2 (5/2.5G); F:PCIe3 (5/2.5G); G: SATA2(3/1.5G); * H: SATA1(3/1.5G) */ diff --git a/board/scalys/simc-t10xx/eth.c b/board/scalys/simc-t10xx/eth.c index 2533137..2f5c401 100644 --- a/board/scalys/simc-t10xx/eth.c +++ b/board/scalys/simc-t10xx/eth.c @@ -13,6 +13,25 @@ #include #include + + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//#include "../common/fman.h" +//#include "../common/qixis.h" + + + + #include "../../freescale/common/fman.h" uint8_t sfp_phy_config[][2] = { @@ -33,6 +52,13 @@ int board_eth_init(bd_t *bis) int ret; int phy_addr = 0; +#ifdef CONFIG_VSC9953 + int lane; + phy_interface_t phy_int; + struct mii_dev *bus; + struct ccsr_scfg *scfg; +#endif + uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; uint32_t regval; @@ -106,7 +132,6 @@ int board_eth_init(bd_t *bis) */ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; - switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) @@ -116,7 +141,8 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(i, phy_addr); break; case PHY_INTERFACE_MODE_QSGMII: - fm_info_set_phy_address(i, 0); + /* TODO, get fixed phy here */ + fm_info_set_phy_address(i, i+2); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); @@ -134,6 +160,44 @@ int board_eth_init(bd_t *bis) fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); } + +#ifdef CONFIG_VSC9953 + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + int lane = -1; + int phy_addr = 0; + int phy_int = PHY_INTERFACE_MODE_NONE; + switch (i) { + case 0: + case 1: + case 2: + vsc9953_port_enable(i); + vsc9953_port_info_set_phy_int(i, PHY_INTERFACE_MODE_SGMII); + break; + case 3: + case 4: + case 5: + case 6: + case 7: + continue; + case 8: + /* FM1@DTSEC1 is connected to SW1@PORT8 */ + vsc9953_port_enable(i); + break; + case 9: + /* Enable L2 On MAC2 using SCFG */ + scfg = (struct ccsr_scfg *) CONFIG_SYS_MPC85xx_SCFG; + + out_be32(&scfg->esgmiiselcr, + in_be32(&scfg->esgmiiselcr) | + (0x80000000)); + vsc9953_port_enable(i); + break; + } + bus = lane; + + } +#endif + cpu_eth_init(bis); #endif return pci_eth_init(bis); diff --git a/board/scalys/simc-t10xx/simc-t1022_rcw.cfg b/board/scalys/simc-t10xx/simc-t1022_rcw.cfg new file mode 100644 index 0000000..1ddbe0c --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t1022_rcw.cfg @@ -0,0 +1,17 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +#120C0015 15000000 00000000 00000000 +#06000000 00C00002 E8104000 21000000 +#00000000 CAFEBABE 00000000 00030ffc +#00000314 0014500C 00000000 00000000 +# +#120C0015 15000000 00000000 00000000 +#06000000 00000002 E8105000 21000000 +#00000000 CAFEBABE 00000000 00230FFC +#00000714 0014500C 00000000 00000000 + +120C0015 15000000 00000000 00000000 +86000000 00000002 E8104000 21000000 +00000000 CAFEBABE 00000000 00030FFC +00000314 0014500C 00000000 00000000 diff --git a/board/scalys/simc-t10xx/simc-t1040_rcw.cfg b/board/scalys/simc-t10xx/simc-t1040_rcw.cfg new file mode 100644 index 0000000..ae0edf3 --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t1040_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +0A0C000C 0C000000 00000000 00000000 +81000002 00000002 E8105000 21000000 +00000000 CAFEBABE 00000000 00030FFC +00000314 0014500C 00000000 00000000 diff --git a/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg index 59e2c66..c5fd95d 100644 --- a/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg +++ b/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg @@ -29,15 +29,14 @@ #Configure IFC controller # (IFC_CSPR1) 09124010 ff8000c3 -# IFC_AMASK1 -#091240A0 C0000000 -#ECC DISABLED: -# 4K pages: 09124130 0110a200 +# IFC_CSOR_NAND 09124130 0108a100 # IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND 091241c0 181c080c 091241c4 3850141a 091241c8 03008028 091241cc 28000000 +# Set IFC_CCR clkdiv to 6 (IFC clock to platform clock/6=83.3MHz) +0912444c 05008000 #Flush PBL data (Wait 0xFFFFF cycles ) 091380c0 000fffff \ No newline at end of file diff --git a/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg b/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg deleted file mode 100644 index 1ddbe0c..0000000 --- a/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg +++ /dev/null @@ -1,17 +0,0 @@ -#PBL preamble and RCW header -AA55AA55 010E0100 -# -#120C0015 15000000 00000000 00000000 -#06000000 00C00002 E8104000 21000000 -#00000000 CAFEBABE 00000000 00030ffc -#00000314 0014500C 00000000 00000000 -# -#120C0015 15000000 00000000 00000000 -#06000000 00000002 E8105000 21000000 -#00000000 CAFEBABE 00000000 00230FFC -#00000714 0014500C 00000000 00000000 - -120C0015 15000000 00000000 00000000 -86000000 00000002 E8104000 21000000 -00000000 CAFEBABE 00000000 00030FFC -00000314 0014500C 00000000 00000000 diff --git a/configs/T1_simc-t10xx_nand_defconfig b/configs/T1_simc-t10xx_nand_defconfig index fb14e16..1f86ae3 100644 --- a/configs/T1_simc-t10xx_nand_defconfig +++ b/configs/T1_simc-t10xx_nand_defconfig @@ -1,5 +1,4 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_SIMC_T10XX=y diff --git a/include/configs/simc-t10x0.h b/include/configs/simc-t10x0.h new file mode 100644 index 0000000..75cae27 --- /dev/null +++ b/include/configs/simc-t10x0.h @@ -0,0 +1,18 @@ +#ifndef _SIMC_T10X0 +#define _SIMC_T10X0 + +#define CONFIG_PHY_VITESSE + +/* Enable VSC9953 L2 Switch driver on T1040 SoC */ +#define CONFIG_VSC9953 +#define CONFIG_CMD_ETHSW +#ifdef CONFIG_T1040RDB +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#else +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c +#endif + + +#endif /* _SIMC_T10X0 */ \ No newline at end of file diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h index 8c6f7be..8a13e92 100644 --- a/include/configs/simc-t10xx.h +++ b/include/configs/simc-t10xx.h @@ -7,6 +7,8 @@ #ifndef __SIMC_T10XX_H #define __SIMC_T10XX_H +#include "simc-t10x0.h" + /* * SIMC-T10xx board configuration file */ @@ -18,12 +20,27 @@ /* * System and DDR clock */ -#define CONFIG_SYS_CLK_FREQ 66666666 /* 66.67MHz */ -#define CONFIG_DDR_CLK_FREQ 133333333 /* 133.33MHz */ +#if defined(CONFIG_SYS_CLK_FREQ_66) +#define CONFIG_SYS_CLK_FREQ 66666666 /* 66.6 MHz */ +#elif defined(CONFIG_SYS_CLK_FREQ_100) +#define CONFIG_SYS_CLK_FREQ 100000000 /* 100 MHz */ +#endif + +#define CONFIG_DDR_CLK_FREQ 133333333 /* 133.33MHz */ #ifdef CONFIG_RAMBOOT_PBL + + + +/* PBI commands are cpu independent for now */ #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg + +/* Set the RCW config depending on the CPU type */ +#if defined(CONFIG_PPC_T1022) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1022_rcw.cfg +#elif defined(CONFIG_PPC_T1040) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_rcw.cfg +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -661,10 +678,12 @@ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ \ - "ethaddr=00:00:00:ca:fe:00\0" \ - "eth1addr=00:00:00:ca:fe:01\0" \ - "eth2addr=00:00:00:ca:fe:02\0" \ - "eth3addr=00:00:00:ca:fe:03\0" \ + "l2switchaddr=02:00:00:ba:be:00\0" \ + "ethaddr=02:00:00:ba:be:01\0" \ + "eth1addr=02:00:00:ba:be:02\0" \ + "eth2addr=02:00:00:ba:be:03\0" \ + "eth3addr=02:00:00:ba:be:04\0" \ + "eth4addr=02:00:00:ba:be:05\0" \ \ "autoload=no\0" \ "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \ -- cgit v0.10.2 From 98d1bb37c2bf1efed77bfea7de6b3d5a67247ab6 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Fri, 15 Jul 2016 14:39:04 +0200 Subject: Disable serdes PLL 2 in RCW diff --git a/board/scalys/simc-t10xx/simc-t1040_rcw.cfg b/board/scalys/simc-t10xx/simc-t1040_rcw.cfg index ae0edf3..323ea71 100644 --- a/board/scalys/simc-t10xx/simc-t1040_rcw.cfg +++ b/board/scalys/simc-t10xx/simc-t1040_rcw.cfg @@ -2,6 +2,6 @@ AA55AA55 010E0100 # 0A0C000C 0C000000 00000000 00000000 -81000002 00000002 E8105000 21000000 +81000002 00400002 E8105000 21000000 00000000 CAFEBABE 00000000 00030FFC 00000314 0014500C 00000000 00000000 -- cgit v0.10.2 From b8b6bb937ddb64a2c7a318660874aee50b6d387f Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Fri, 15 Jul 2016 14:51:48 +0200 Subject: Fix bootsource Kconfig warning diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig index 2b8d1a4..d43dc85 100644 --- a/board/scalys/simc-t10xx/Kconfig +++ b/board/scalys/simc-t10xx/Kconfig @@ -22,11 +22,10 @@ config SPL_FSL_PBL choice prompt "Bootsource" - + default NAND config NAND bool prompt "NAND boot" - default y help Select NAND as the bootsource -- cgit v0.10.2 From 6d249763300432a786ee03cdbb09dd3b065c5189 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Fri, 15 Jul 2016 14:54:26 +0200 Subject: Add autoconf include so we can use Kconfig params diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h index 8a13e92..f53c201 100644 --- a/include/configs/simc-t10xx.h +++ b/include/configs/simc-t10xx.h @@ -8,6 +8,7 @@ #define __SIMC_T10XX_H #include "simc-t10x0.h" +#include /* * SIMC-T10xx board configuration file -- cgit v0.10.2 From 3592045f3964bc5c6f3b2f657ae1e2abbcede0d5 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Fri, 16 Sep 2016 15:16:50 +0200 Subject: merge with master diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 80b2b13..7a878be 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3198,14 +3198,4 @@ struct ccsr_scfg { u32 res4[60]; u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */ }; - -#if defined(CONFIG_PPC_T1013) || defined(CONFIG_PPC_T1014) ||\ - defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) ||\ - defined(CONFIG_PPC_T1023) || defined(CONFIG_PPC_T1024) ||\ - defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) -#define CONFIG_SYS_MPC8XXX_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x130000) -#define CONFIG_SYS_MPC8XXX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000) -#define CONFIG_SYS_MPC8XXX_GPIO3_ADDR (CONFIG_SYS_IMMR + 0x132000) -#define CONFIG_SYS_MPC8XXX_GPIO4_ADDR (CONFIG_SYS_IMMR + 0x133000) -#endif #endif /*__IMMAP_85xx__*/ diff --git a/arch/powerpc/include/asm/mpc8xxx_gpio.h b/arch/powerpc/include/asm/mpc8xxx_gpio.h deleted file mode 100644 index 1069638..0000000 --- a/arch/powerpc/include/asm/mpc8xxx_gpio.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2016 Scalys B.V. - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _POWERPC_ASM_MPC8XXX_GPIO_H -#define _POWERPC_ASM_MPC8XXX_GPIO_H - -#include - -#define MPC8XXX_GPIO_NR(port, pin) ((((port)-1)*32)+((pin)&31)) -#define MPC8XXX_GPIO_TO_PORT(gpio) (gpio/32) -#define MPC8XXX_GPIO_TO_PIN(gpio) (gpio&31) - -static inline void mpc8xxx_gpio_set(uint32_t gpio, int value) -{ - int port, pin; - ccsr_gpio_t *gpio_regs; - uint32_t regval; - - port = MPC8XXX_GPIO_TO_PORT(gpio); - pin = MPC8XXX_GPIO_TO_PIN(gpio); - - switch (port) { -#ifdef CONFIG_SYS_MPC8XXX_GPIO1_ADDR - case 0: - gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO1_ADDR; - break; -#endif -#ifdef CONFIG_SYS_MPC8XXX_GPIO2_ADDR - case 1: - gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO2_ADDR; - break; -#endif -#ifdef CONFIG_SYS_MPC8XXX_GPIO3_ADDR - case 2: - gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO3_ADDR; - break; -#endif -#ifdef CONFIG_SYS_MPC8XXX_GPIO4_ADDR - case 3: - gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO4_ADDR; - break; -#endif - default: - return; - } - - /* Set output */ - regval = in_be32(&(gpio_regs->gpdat)); - regval |= (0x80000000 >> pin); - out_be32(&(gpio_regs->gpdat), regval); - - /* Set direction to acivate gpio pin */ - regval = in_be32(&(gpio_regs->gpdir)); - regval |= (0x80000000 >> pin); - out_be32(&(gpio_regs->gpdir), regval); -} - -static inline int mpc8xxx_gpio_get(uint32_t gpio, int value) -{ - int port, pin; - ccsr_gpio_t *gpio_regs; - uint32_t regval; - - port = MPC8XXX_GPIO_TO_PORT(gpio); - pin = MPC8XXX_GPIO_TO_PIN(gpio); - - switch (port) { -#ifdef CONFIG_SYS_MPC8XXX_GPIO1_ADDR - case 0: - gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO1_ADDR; - break; -#endif -#ifdef CONFIG_SYS_MPC8XXX_GPIO2_ADDR - case 1: - gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO2_ADDR; - break; -#endif -#ifdef CONFIG_SYS_MPC8XXX_GPIO3_ADDR - case 2: - gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO3_ADDR; - break; -#endif -#ifdef CONFIG_SYS_MPC8XXX_GPIO4_ADDR - case 3: - gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO4_ADDR; - break; -#endif - default: - return -ENODEV; - } - - /* Get inputs */ - regval = in_be32(&(gpio_regs->gpdat)); - regval <<= pin; - regval &= 1; - - return regval; -} - -#endif /* _POWERPC_ASM_MPC8XXX_GPIO_H */ diff --git a/board/scalys/common/Makefile b/board/scalys/common/Makefile index dc95801..92c36e7 100644 --- a/board/scalys/common/Makefile +++ b/board/scalys/common/Makefile @@ -5,3 +5,7 @@ # obj-y += board_configuration_data.o + +ifdef CONFIG_SECURE_BOOT + obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o +endif diff --git a/board/scalys/common/cmd_esbc_validate.c b/board/scalys/common/cmd_esbc_validate.c new file mode 100644 index 0000000..cefe3cc --- /dev/null +++ b/board/scalys/common/cmd_esbc_validate.c @@ -0,0 +1,84 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (fsl_check_boot_mode_secure() == 0) { + printf("Boot Mode is Non-Secure. Not entering spin loop.\n"); + return 0; + } + + printf("Core is entering spin loop.\n"); +loop: + goto loop; + + return 0; +} + +static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + char *hash_str = NULL; + uintptr_t haddr; + int ret; + uintptr_t img_addr = 0; + char buf[20]; + + if (argc < 2) + return cmd_usage(cmdtp); + else if (argc > 2) + /* Second arg - Optional - Hash Str*/ + hash_str = argv[2]; + + /* First argument - header address -32/64bit */ + haddr = (uintptr_t)simple_strtoul(argv[1], NULL, 16); + + /* With esbc_validate command, Image address must be + * part of header. So, the function is called + * by passing this argument as 0. + */ + ret = fsl_secboot_validate(haddr, hash_str, &img_addr); + + /* Need to set "img_addr" even if validation failure. + * Required when SB_EN in RCW set and non-fatal error + * to continue U-Boot + */ + sprintf(buf, "%lx", img_addr); + setenv("img_addr", buf); + + if (ret) + return 1; + + printf("esbc_validate command successful\n"); + return 0; +} + +/***************************************************/ +static char esbc_validate_help_text[] = + "esbc_validate hdr_addr - Validates signature using\n" + " RSA verification\n" + " $hdr_addr Address of header of the image\n" + " to be validated.\n" + " $hash_val -Optional\n" + " It provides Hash of public/srk key to be\n" + " used to verify signature.\n"; + +U_BOOT_CMD( + esbc_validate, 3, 0, do_esbc_validate, + "Validates signature on a given image using RSA verification", + esbc_validate_help_text +); + +U_BOOT_CMD( + esbc_halt, 1, 0, do_esbc_halt, + "Put the core in spin loop (Secure Boot Only)", + "" +); diff --git a/board/scalys/common/fsl_validate.c b/board/scalys/common/fsl_validate.c new file mode 100644 index 0000000..8c171b1 --- /dev/null +++ b/board/scalys/common/fsl_validate.c @@ -0,0 +1,927 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_LS102XA +#include +#endif + +#define SHA256_BITS 256 +#define SHA256_BYTES (256/8) +#define SHA256_NIBBLES (256/4) +#define NUM_HEX_CHARS (sizeof(ulong) * 2) + +#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ + ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ + ((key_len) == 2 * KEY_SIZE_BYTES)) + +/* This array contains DER value for SHA-256 */ +static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, + 0x04, 0x20 + }; + +static u8 hash_val[SHA256_BYTES]; + +#ifdef CONFIG_ESBC_HDR_LS +/* New Barker Code for LS ESBC Header */ +static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 }; +#else +static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 }; +#endif + +void branch_to_self(void) __attribute__ ((noreturn)); + +/* + * This function will put core in infinite loop. + * This will be called when the ESBC can not proceed further due + * to some unknown errors. + */ +void branch_to_self(void) +{ + printf("Core is in infinite loop due to errors.\n"); +self: + goto self; +} + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +static u32 check_ie(struct fsl_secboot_img_priv *img) +{ + if (img->hdr.ie_flag) + return 1; + + return 0; +} + +/* This function returns the CSF Header Address of uboot + * For MPC85xx based platforms, the LAW mapping for NOR + * flash changes in uboot code. Hence the offset needs + * to be calculated and added to the new NOR flash base + * address + */ +#if defined(CONFIG_MPC85xx) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); + u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); + u32 flash_addr, addr; + int found = 0; + int i = 0; + + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + flash_addr = flash_info[i].start[0]; + addr = flash_info[i].start[0] + csf_flash_offset; + if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) { + debug("Barker found on addr %x\n", addr); + found = 1; + break; + } + } + + if (!found) + return -1; + + *csf_addr = addr; + *flash_base_addr = flash_addr; + + return 0; +} +#else +/* For platforms like LS1020, correct flash address is present in + * the header. So the function reqturns flash base address as 0 + */ +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); + + if (memcmp((u8 *)(uintptr_t)csf_hdr_addr, + barker_code, ESBC_BARKER_LEN)) + return -1; + + *csf_addr = csf_hdr_addr; + *flash_base_addr = 0; + return 0; +} +#endif + +static int get_ie_info_addr(u32 *ie_addr) +{ + struct fsl_secboot_img_hdr *hdr; + struct fsl_secboot_sg_table *sg_tbl; + u32 flash_base_addr, csf_addr; + + if (get_csf_base_addr(&csf_addr, &flash_base_addr)) + return -1; + + hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr; + + /* For SoC's with Trust Architecture v1 with corenet bus + * the sg table field in CSF header has absolute address + * for sg table in memory. In other Trust Architecture, + * this field specifies the offset of sg table from the + * base address of CSF Header + */ +#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) + sg_tbl = (struct fsl_secboot_sg_table *) + (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + flash_base_addr); +#else + sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr + + (u32)hdr->psgtable); +#endif + + /* IE Key Table is the first entry in the SG Table */ +#if defined(CONFIG_MPC85xx) + *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + flash_base_addr; +#else + *ie_addr = sg_tbl->src_addr; +#endif + + debug("IE Table address is %x\n", *ie_addr); + return 0; +} + +#endif + +#ifdef CONFIG_KEY_REVOCATION +/* This function checks srk_table_flag in header and set/reset srk_flag.*/ +static u32 check_srk(struct fsl_secboot_img_priv *img) +{ +#ifdef CONFIG_ESBC_HDR_LS + /* In LS, No SRK Flag as SRK is always present*/ + return 1; +#else + if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) + return 1; + + return 0; +#endif +} + +/* This function returns ospr's key_revoc values.*/ +static u32 get_key_revoc(void) +{ + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >> + OSPR_KEY_REVOC_SHIFT; +} + +/* This function checks if selected key is revoked or not.*/ +static u32 is_key_revoked(u32 keynum, u32 rev_flag) +{ + if (keynum == UNREVOCABLE_KEY) + return 0; + + if ((u32)(1 << (ALIGN_REVOC_KEY - keynum)) & rev_flag) + return 1; + + return 0; +} + +/* It read validates srk_table key lengths.*/ +static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img) +{ + int i = 0; + u32 ret, key_num, key_revoc_flag, size; + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + + if ((hdr->len_kr.num_srk == 0) || + (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) + return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; + + key_num = hdr->len_kr.srk_sel; + if (key_num == 0 || key_num > hdr->len_kr.num_srk) + return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; + + /* Get revoc key from sfp */ + key_revoc_flag = get_key_revoc(); + ret = is_key_revoked(key_num, key_revoc_flag); + if (ret) + return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; + + size = hdr->len_kr.num_srk * sizeof(struct srk_table); + + memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); + + for (i = 0; i < hdr->len_kr.num_srk; i++) { + if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len)) + return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN; + } + + img->key_len = img->srk_tbl[key_num - 1].key_len; + + memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), + img->key_len); + + return 0; +} +#endif + +#ifndef CONFIG_ESBC_HDR_LS +static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + + /* check key length */ + if (!CHECK_KEY_LEN(hdr->key_len)) + return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; + + memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); + + img->key_len = hdr->key_len; + + return 0; +} +#endif /* CONFIG_ESBC_HDR_LS */ + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + u32 ie_key_len, ie_revoc_flag, ie_num; + struct ie_key_info *ie_info; + + if (get_ie_info_addr(&img->ie_addr)) + return ERROR_IE_TABLE_NOT_FOUND; + ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; + if (ie_info->num_keys == 0 || ie_info->num_keys > 32) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; + + ie_num = hdr->ie_key_sel; + if (ie_num == 0 || ie_num > ie_info->num_keys) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; + + ie_revoc_flag = ie_info->key_revok; + if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) + return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; + + ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; + + if (!CHECK_KEY_LEN(ie_key_len)) + return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; + + memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), + ie_key_len); + + img->key_len = ie_key_len; + return 0; +} +#endif + + +/* This function return length of public key.*/ +static inline u32 get_key_len(struct fsl_secboot_img_priv *img) +{ + return img->key_len; +} + +/* + * Handles the ESBC uboot client header verification failure. + * This function handles all the errors which might occur in the + * parsing and checking of ESBC uboot client header. It will also + * set the error bits in the SEC_MON. + */ +static void fsl_secboot_header_verification_failure(void) +{ + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); + + /* 29th bit of OSPR is ITS */ + u32 its = sfp_in32(&sfp_regs->ospr) >> 2; + + /* + * Read the SEC_MON status register + * Read SSM_ST field + */ + sts = sec_mon_in32(&sec_mon_regs->hp_stat); + if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { + if (its == 1) + change_sec_mon_state(HPSR_SSM_ST_TRUST, + HPSR_SSM_ST_SOFT_FAIL); + else + change_sec_mon_state(HPSR_SSM_ST_TRUST, + HPSR_SSM_ST_NON_SECURE); + } + + printf("Generating reset request\n"); + do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); +} + +/* + * Handles the ESBC uboot client image verification failure. + * This function handles all the errors which might occur in the + * public key hash comparison and signature verification of + * ESBC uboot client image. It will also + * set the error bits in the SEC_MON. + */ +static void fsl_secboot_image_verification_failure(void) +{ + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); + + u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; + + /* + * Read the SEC_MON status register + * Read SSM_ST field + */ + sts = sec_mon_in32(&sec_mon_regs->hp_stat); + if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { + if (its == 1) { + change_sec_mon_state(HPSR_SSM_ST_TRUST, + HPSR_SSM_ST_SOFT_FAIL); + + printf("Generating reset request\n"); + do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); + + } else { + change_sec_mon_state(HPSR_SSM_ST_TRUST, + HPSR_SSM_ST_NON_SECURE); + } + } +} + +static void fsl_secboot_bootscript_parse_failure(void) +{ + fsl_secboot_header_verification_failure(); +} + +/* + * Handles the errors in esbc boot. + * This function handles all the errors which might occur in the + * esbc boot phase. It will call the appropriate api to log the + * errors and set the error bits in the SEC_MON. + */ +void fsl_secboot_handle_error(int error) +{ + const struct fsl_secboot_errcode *e; + + for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX; + e++) { + if (e->errcode == error) + printf("ERROR :: %x :: %s\n", error, e->name); + } + + /* If Boot Mode is secure, transition the SNVS state and issue + * reset based on type of failure and ITS setting. + * If Boot mode is non-secure, return from this function. + */ + if (fsl_check_boot_mode_secure() == 0) + return; + + switch (error) { + case ERROR_ESBC_CLIENT_HEADER_BARKER: + case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE: + case ERROR_ESBC_CLIENT_HEADER_KEY_LEN: + case ERROR_ESBC_CLIENT_HEADER_SIG_LEN: + case ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN: + case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1: + case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2: + case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD: + case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP: + case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD: + case ERROR_KEY_TABLE_NOT_FOUND: +#ifdef CONFIG_KEY_REVOCATION + case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED: + case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY: + case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM: + case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN: +#endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + /*@fallthrough@*/ + case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED: + case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY: + case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM: + case ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN: + case ERROR_IE_TABLE_NOT_FOUND: +#endif + fsl_secboot_header_verification_failure(); + break; + case ERROR_ESBC_SEC_RESET: + case ERROR_ESBC_SEC_DEQ: + case ERROR_ESBC_SEC_ENQ: + case ERROR_ESBC_SEC_DEQ_TO: + case ERROR_ESBC_SEC_JOBQ_STATUS: + case ERROR_ESBC_CLIENT_HASH_COMPARE_KEY: + case ERROR_ESBC_CLIENT_HASH_COMPARE_EM: + fsl_secboot_image_verification_failure(); + break; + case ERROR_ESBC_MISSING_BOOTM: + fsl_secboot_bootscript_parse_failure(); + break; + case ERROR_ESBC_WRONG_CMD: + default: + branch_to_self(); + break; + } +} + +static void fsl_secblk_handle_error(int error) +{ + switch (error) { + case ERROR_ESBC_SEC_ENQ: + fsl_secboot_handle_error(ERROR_ESBC_SEC_ENQ); + break; + case ERROR_ESBC_SEC_DEQ: + fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ); + break; + case ERROR_ESBC_SEC_DEQ_TO: + fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ_TO); + break; + default: + printf("Job Queue Output status %x\n", error); + fsl_secboot_handle_error(ERROR_ESBC_SEC_JOBQ_STATUS); + break; + } +} + +/* + * Calculate hash of key obtained via offset present in ESBC uboot + * client hdr. This function calculates the hash of key which is obtained + * through offset present in ESBC uboot client header. + */ +static int calc_img_key_hash(struct fsl_secboot_img_priv *img) +{ + struct hash_algo *algo; + void *ctx; + int i, srk = 0; + int ret = 0; + const char *algo_name = "sha256"; + + /* Calculate hash of the esbc key */ + ret = hash_progressive_lookup_algo(algo_name, &algo); + if (ret) + return ret; + + ret = algo->hash_init(algo, &ctx); + if (ret) + return ret; + + /* Update hash for ESBC key */ +#ifdef CONFIG_KEY_REVOCATION + if (check_srk(img)) { + ret = algo->hash_update(algo, ctx, + (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), + img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1); + srk = 1; + } +#endif + if (!srk) + ret = algo->hash_update(algo, ctx, + img->img_key, img->key_len, 1); + if (ret) + return ret; + + /* Copy hash at destination buffer */ + ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); + if (ret) + return ret; + + for (i = 0; i < SHA256_BYTES; i++) + img->img_key_hash[i] = hash_val[i]; + + return 0; +} + +/* + * Calculate hash of ESBC hdr and ESBC. This function calculates the + * single hash of ESBC header and ESBC image. If SG flag is on, all + * SG entries are also hashed alongwith the complete SG table. + */ +static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) +{ + struct hash_algo *algo; + void *ctx; + int ret = 0; + int key_hash = 0; + const char *algo_name = "sha256"; + + /* Calculate the hash of the ESBC */ + ret = hash_progressive_lookup_algo(algo_name, &algo); + if (ret) + return ret; + + ret = algo->hash_init(algo, &ctx); + /* Copy hash at destination buffer */ + if (ret) + return ret; + + /* Update hash for CSF Header */ + ret = algo->hash_update(algo, ctx, + (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0); + if (ret) + return ret; + + /* Update the hash with that of srk table if srk flag is 1 + * If IE Table is selected, key is not added in the hash + * If neither srk table nor IE key table available, add key + * from header in the hash calculation + */ +#ifdef CONFIG_KEY_REVOCATION + if (check_srk(img)) { + ret = algo->hash_update(algo, ctx, + (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), + img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0); + key_hash = 1; + } +#endif +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + if (!key_hash && check_ie(img)) + key_hash = 1; +#endif +#ifndef CONFIG_ESBC_HDR_LS +/* No single key support in LS ESBC header */ + if (!key_hash) { + ret = algo->hash_update(algo, ctx, + img->img_key, img->hdr.key_len, 0); + key_hash = 1; + } +#endif + if (ret) + return ret; + if (!key_hash) + return ERROR_KEY_TABLE_NOT_FOUND; + + /* Update hash for actual Image */ + ret = algo->hash_update(algo, ctx, + (u8 *)(*(img->img_addr_ptr)), img->img_size, 1); + if (ret) + return ret; + + /* Copy hash at destination buffer */ + ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); + if (ret) + return ret; + + return 0; +} + +/* + * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the + * pointers for padding, DER value and hash. And finally, constructs EM' + * which includes hash of complete CSF header and ESBC image. If SG flag + * is on, hash of SG table and entries is also included. + */ +static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img) +{ + /* + * RSA PKCSv1.5 encoding format for encoded message is below + * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash + * PS is Padding String + * DER is DER value for SHA-256 + * Hash is SHA-256 hash + * ********************************************************* + * representative points to first byte of EM initially and is + * filled with 0x0 + * representative is incremented by 1 and second byte is filled + * with 0x1 + * padding points to third byte of EM + * digest points to full length of EM - 32 bytes + * hash_id (DER value) points to 19 bytes before pDigest + * separator is one byte which separates padding and DER + */ + + size_t len; + u8 *representative; + u8 *padding, *digest; + u8 *hash_id, *separator; + int i; + + len = (get_key_len(img) / 2) - 1; + representative = img->img_encoded_hash_second; + representative[0] = 0; + representative[1] = 1; /* block type 1 */ + + padding = &representative[2]; + digest = &representative[1] + len - 32; + hash_id = digest - sizeof(hash_identifier); + separator = hash_id - 1; + + /* fill padding area pointed by padding with 0xff */ + memset(padding, 0xff, separator - padding); + + /* fill byte pointed by separator */ + *separator = 0; + + /* fill SHA-256 DER value pointed by HashId */ + memcpy(hash_id, hash_identifier, sizeof(hash_identifier)); + + /* fill hash pointed by Digest */ + for (i = 0; i < SHA256_BYTES; i++) + digest[i] = hash_val[i]; +} + +/* + * Reads and validates the ESBC client header. + * This function reads key and signature from the ESBC client header. + * If Scatter/Gather flag is on, lengths and offsets of images + * present as SG entries are also read. This function also checks + * whether the header is valid or not. + */ +static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + u8 *k, *s; + u32 ret = 0; + + int key_found = 0; + + /* check barker code */ + if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) + return ERROR_ESBC_CLIENT_HEADER_BARKER; + + /* If Image Address is not passed as argument to function, + * then Address and Size must be read from the Header. + */ + if (*(img->img_addr_ptr) == 0) { + #ifdef CONFIG_ESBC_ADDR_64BIT + *(img->img_addr_ptr) = hdr->pimg64; + #else + *(img->img_addr_ptr) = hdr->pimg; + #endif + } + + if (!hdr->img_size) + return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE; + + img->img_size = hdr->img_size; + + /* Key checking*/ +#ifdef CONFIG_KEY_REVOCATION + if (check_srk(img)) { + ret = read_validate_srk_tbl(img); + if (ret != 0) + return ret; + key_found = 1; + } +#endif + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + if (!key_found && check_ie(img)) { + ret = read_validate_ie_tbl(img); + if (ret != 0) + return ret; + key_found = 1; + } +#endif +#ifndef CONFIG_ESBC_HDR_LS +/* Single Key Feature not available in LS ESBC Header */ + if (key_found == 0) { + ret = read_validate_single_key(img); + if (ret != 0) + return ret; + key_found = 1; + } +#endif + if (!key_found) + return ERROR_KEY_TABLE_NOT_FOUND; + + /* check signaure */ + if (get_key_len(img) == 2 * hdr->sign_len) { + /* check signature length */ + if (!((hdr->sign_len == KEY_SIZE_BYTES / 4) || + (hdr->sign_len == KEY_SIZE_BYTES / 2) || + (hdr->sign_len == KEY_SIZE_BYTES))) + return ERROR_ESBC_CLIENT_HEADER_SIG_LEN; + } else { + return ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN; + } + + memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len); +/* No SG support in LS-CH3 */ +#ifndef CONFIG_ESBC_HDR_LS + /* No SG support */ + if (hdr->sg_flag) + return ERROR_ESBC_CLIENT_HEADER_SG; +#endif + + /* modulus most significant bit should be set */ + k = (u8 *)&img->img_key; + + if ((k[0] & 0x80) == 0) + return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1; + + /* modulus value should be odd */ + if ((k[get_key_len(img) / 2 - 1] & 0x1) == 0) + return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2; + + /* Check signature value < modulus value */ + s = (u8 *)&img->img_sign; + + if (!(memcmp(s, k, hdr->sign_len) < 0)) + return ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD; + + return ESBC_VALID_HDR; +} + +static inline int str2longbe(const char *p, ulong *num) +{ + char *endptr; + ulong tmp; + + if (!p) { + return 0; + } else { + tmp = simple_strtoul(p, &endptr, 16); + if (sizeof(ulong) == 4) + *num = cpu_to_be32(tmp); + else + *num = cpu_to_be64(tmp); + } + + return *p != '\0' && *endptr == '\0'; +} +/* Function to calculate the ESBC Image Hash + * and hash from Digital signature. + * The Two hash's are compared to yield the + * result of signature validation. + */ +static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) +{ + int ret; + uint32_t key_len; + struct key_prop prop; +#if !defined(USE_HOSTCC) + struct udevice *mod_exp_dev; +#endif + ret = calc_esbchdr_esbc_hash(img); + if (ret) + return ret; + + /* Construct encoded hash EM' wrt PKCSv1.5 */ + construct_img_encoded_hash_second(img); + + /* Fill prop structure for public key */ + memset(&prop, 0, sizeof(struct key_prop)); + key_len = get_key_len(img) / 2; + prop.modulus = img->img_key; + prop.public_exponent = img->img_key + key_len; + prop.num_bits = key_len * 8; + prop.exp_len = key_len; + + ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); + if (ret) { + printf("RSA: Can't find Modular Exp implementation\n"); + return -EINVAL; + } + + ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, + &prop, img->img_encoded_hash); + if (ret) + return ret; + + /* + * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 + * memcmp returns zero on success + * memcmp returns non-zero on failure + */ + ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, + img->hdr.sign_len); + + if (ret) + return ERROR_ESBC_CLIENT_HASH_COMPARE_EM; + + return 0; +} +/* haddr - Address of the header of image to be validated. + * arg_hash_str - Option hash string. If provided, this + * overrides the key hash in the SFP fuses. + * img_addr_ptr - Optional pointer to address of image to be validated. + * If non zero addr, this overrides the addr of image in header, + * otherwise updated to image addr in header. + * Acts as both input and output of function. + * This pointer shouldn't be NULL. + */ +int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, + uintptr_t *img_addr_ptr) +{ + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + ulong hash[SHA256_BYTES/sizeof(ulong)]; + char hash_str[NUM_HEX_CHARS + 1]; + struct fsl_secboot_img_priv *img; + struct fsl_secboot_img_hdr *hdr; + void *esbc; + int ret, i, hash_cmd = 0; + u32 srk_hash[8]; + + if (arg_hash_str != NULL) { + const char *cp = arg_hash_str; + int i = 0; + + if (*cp == '0' && *(cp + 1) == 'x') + cp += 2; + + /* The input string expected is in hex, where + * each 4 bits would be represented by a hex + * sha256 hash is 256 bits long, which would mean + * num of characters = 256 / 4 + */ + if (strlen(cp) != SHA256_NIBBLES) { + printf("%s is not a 256 bits hex string as expected\n", + arg_hash_str); + return -1; + } + + for (i = 0; i < sizeof(hash)/sizeof(ulong); i++) { + strncpy(hash_str, cp + (i * NUM_HEX_CHARS), + NUM_HEX_CHARS); + hash_str[NUM_HEX_CHARS] = '\0'; + if (!str2longbe(hash_str, &hash[i])) { + printf("%s is not a 256 bits hex string ", + arg_hash_str); + return -1; + } + } + + hash_cmd = 1; + } + + img = malloc(sizeof(struct fsl_secboot_img_priv)); + + if (!img) + return -1; + + memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + + /* Update the information in Private Struct */ + hdr = &img->hdr; + img->ehdrloc = haddr; + img->img_addr_ptr = img_addr_ptr; + esbc = (u8 *)img->ehdrloc; + + memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); + + /* read and validate esbc header */ + ret = read_validate_esbc_client_header(img); + + if (ret != ESBC_VALID_HDR) { + fsl_secboot_handle_error(ret); + goto exit; + } + + /* SRKH present in SFP */ + for (i = 0; i < NUM_SRKH_REGS; i++) + srk_hash[i] = srk_in32(&sfp_regs->srk_hash[i]); + + /* + * Calculate hash of key obtained via offset present in + * ESBC uboot client hdr + */ + ret = calc_img_key_hash(img); + if (ret) { + fsl_secblk_handle_error(ret); + goto exit; + } + + /* Compare hash obtained above with SRK hash present in SFP */ + if (hash_cmd) + ret = memcmp(&hash, &img->img_key_hash, SHA256_BYTES); + else + ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES); + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + if (!hash_cmd && check_ie(img)) + ret = 0; +#endif + + if (ret != 0) { + fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_KEY); + goto exit; + } + + ret = calculate_cmp_img_sig(img); + if (ret) { + fsl_secboot_handle_error(ret); + goto exit; + } + +exit: + return ret; +} diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig index d43dc85..2b18913 100644 --- a/board/scalys/simc-t10xx/Kconfig +++ b/board/scalys/simc-t10xx/Kconfig @@ -57,7 +57,7 @@ config PPC_T1020 config PPC_T1022 bool - prompt "T1040" + prompt "T1022" config PPC_T1040 bool diff --git a/board/scalys/simc-t10xx/ddr.c b/board/scalys/simc-t10xx/ddr.c index ca5407e..f6d04ac 100644 --- a/board/scalys/simc-t10xx/ddr.c +++ b/board/scalys/simc-t10xx/ddr.c @@ -7,7 +7,7 @@ #include #include -#include +//#include #include #include @@ -18,10 +18,7 @@ #include #include #include -#include - -/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ -#define DDR_RST_N MPC8XXX_GPIO_NR(2, 12) +//#include /* MT41K512M8RH-125 */ dimm_params_t ddr_raw_timing = { @@ -91,8 +88,8 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->ddr_cdr1 = 0x800c0000; popts->ddr_cdr2 = 0x00000001; - /* Clock is launched 1/4 applied cycle after address/command */ - popts->clk_adjust = 4; + /* Clock is launched 1/2 applied cycle after address/command */ + popts->clk_adjust = 8; } int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, @@ -114,15 +111,29 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, phys_size_t initdram(int board_type) { phys_size_t dram_size; - + #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + uint32_t regval; + + /* Remove reset of DDR using GPIO pin. We do this manually since + * we have not yet access to the DM gpio at this time */ + /* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ + +#define CONFIG_SYS_MPC85XX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000) +#define DDR_RST_N (12) +/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ +/* #define DDR_RST_N MPC85XX_GPIO_NR(2, 12) */ -#ifdef GPIO_IN_SPL_WORKING - gpio_request(DDR_RST_N, "DDR_RST_N"); - gpio_direction_output(DDR_RST_N, 1); -#else - mpc8xxx_gpio_set(DDR_RST_N,1); -#endif + /* Set output */ + regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8); + regval |= (0x80000000 >> 12); + out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval); + + /* Set direction to acivate gpio pin */ + regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR); + regval |= (0x80000000 >> 12); + out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval); + dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c index 1656054..0ae849c 100644 --- a/board/scalys/simc-t10xx/dragonfruit.c +++ b/board/scalys/simc-t10xx/dragonfruit.c @@ -7,8 +7,6 @@ #include #include -#include -#include #include "dragonfruit.h" @@ -42,10 +40,10 @@ * SERDES H => Slot 4, lane 3 */ -#define MUX_SER0_1_SEL MPC8XXX_GPIO_NR(2, 25) -#define MUX_SER2_3_SEL MPC8XXX_GPIO_NR(2, 26) -#define MUX_SER5_6_SEL MPC8XXX_GPIO_NR(2, 27) -#define SERDES_CLK_OE MPC8XXX_GPIO_NR(2, 29) +#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25) +#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26) +#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27) +#define SERDES_CLK_OE MPC85XX_GPIO_NR(2, 29) int scalys_carrier_setup_muxing(int serdes_config) { diff --git a/board/scalys/simc-t10xx/simc-t10xx.c b/board/scalys/simc-t10xx/simc-t10xx.c index f5b8a2c..46c5677 100644 --- a/board/scalys/simc-t10xx/simc-t10xx.c +++ b/board/scalys/simc-t10xx/simc-t10xx.c @@ -21,8 +21,6 @@ #include #include #include -#include -#include #include #include #include "dragonfruit.h" @@ -43,13 +41,15 @@ int misc_init_r(void) int serdes_config; ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int ret; + + debug("t10xx: misc_init_r\n"); /* * Initialize and set the LED's on the module to indicate u-boot is alive * IFC_A30 : led green : GPIO2_30 * IFC_A31 : led red : GPIO2_31 */ - #define MODULE_LED_RED MPC8XXX_GPIO_NR(2, 31) - #define MODULE_LED_GREEN MPC8XXX_GPIO_NR(2, 30) + #define MODULE_LED_RED MPC85XX_GPIO_NR(2, 31) + #define MODULE_LED_GREEN MPC85XX_GPIO_NR(2, 30) gpio_request(MODULE_LED_RED, "module_led_red"); gpio_request(MODULE_LED_GREEN, "module_led_green"); @@ -74,22 +74,18 @@ int misc_init_r(void) } /* Platform data for the GPIOs */ -static const struct mpc8xxx_gpio_platdata gpio_platdata[] = { - { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO1_ADDR, - .bank_name = "GPIO1_" }, - { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO2_ADDR, - .bank_name = "GPIO2_" }, - { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO3_ADDR, - .bank_name = "GPIO3_" }, - { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO4_ADDR, - .bank_name = "GPIO4_" }, +static const struct mpc85xx_gpio_plat gpio_platdata[] = { + { .addr = 0x130000, .ngpios = 32 }, + { .addr = 0x131000, .ngpios = 32 }, + { .addr = 0x132000, .ngpios = 32 }, + { .addr = 0x133000, .ngpios = 32,}, }; -U_BOOT_DEVICES(mpc8xxx_gpios) = { - { "gpio-mpc8xxx", &gpio_platdata[0] }, - { "gpio-mpc8xxx", &gpio_platdata[1] }, - { "gpio-mpc8xxx", &gpio_platdata[2] }, - { "gpio-mpc8xxx", &gpio_platdata[3] }, +U_BOOT_DEVICES(mpc85xx_gpios) = { + { "gpio_mpc85xx", &gpio_platdata[0] }, + { "gpio_mpc85xx", &gpio_platdata[1] }, + { "gpio_mpc85xx", &gpio_platdata[2] }, + { "gpio_mpc85xx", &gpio_platdata[3] }, }; int ft_board_setup(void *blob, bd_t *bd) @@ -97,7 +93,7 @@ int ft_board_setup(void *blob, bd_t *bd) phys_addr_t base; phys_size_t size; - debug( "ft_board_setup\n" ); + debug( "t10xx: ft_board_setup\n" ); ft_cpu_setup(blob, bd); base = getenv_bootm_low(); @@ -144,4 +140,4 @@ void board_detail(void) { do_bcdinfo(); } -#endif \ No newline at end of file +#endif diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b3991d4..73b862d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -28,13 +28,6 @@ config DWAPB_GPIO help Support for the Designware APB GPIO driver. -config MPC8XXX_GPIO - bool "NXP (Freescale) MPC8xxx driver" - depends on DM_GPIO - default n - help - Support for the NXP (Freescale) MPC/QorIQ GPIO controller - config ATMEL_PIO4 bool "ATMEL PIO4 driver" depends on DM diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c deleted file mode 100644 index c5d72ef..0000000 --- a/drivers/gpio/gpio-mpc8xxx.c +++ /dev/null @@ -1,178 +0,0 @@ - -/* - * GPIOs on MPC512x/8349/8572/8610/T-series and compatible - * - * Driver ported from the linux kernel 4.5 (b562e44f507e863c6792946e4e1b1449fbbac85d) - * and removed the interrupt functionallity. - * - * Copyright (C) 2008 Peter Korsgaard - * Copyright (c) 2016 Scalys B.V. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define MPC8XXX_GPIO_PINS 32 - -static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) -{ - return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); -} - -static int mpc8xxx_dm_gpio_set(struct udevice *dev, unsigned pin, int val) -{ - struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); - -#if defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) - - if (val) { - plat->data |= mpc8xxx_gpio2mask(pin); - } else { - plat->data &= ~mpc8xxx_gpio2mask(pin); - } - - out_be32(&(plat->regs->gpdat), plat->data); -#else - if (val) { - setbits_be32(&(plat->regs->gpdat), mpc8xxx_gpio2mask(pin)); - } else { - clrbits_be32(&(plat->regs->gpdat), mpc8xxx_gpio2mask(pin)); - } -#endif - return 0; -} - -static int mpc8xxx_dm_gpio_dir_in(struct udevice *dev, unsigned int gpio) -{ - struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); - - clrbits_be32(&(plat->regs->gpdir), mpc8xxx_gpio2mask(gpio)); - - return 0; -} - -static int mpc8xxx_dm_gpio_dir_out(struct udevice *dev, unsigned int gpio, - int val) -{ - struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); - - mpc8xxx_dm_gpio_set(dev, gpio, val); - - setbits_be32(&(plat->regs->gpdir), mpc8xxx_gpio2mask(gpio)); - - return 0; -} - -static int mpc8xxx_dm_gpio_get(struct udevice *dev, unsigned int gpio) -{ - int ret = 0; - struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); - -#if defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) - uint32_t data_val, out_mask, out_shadow; - - /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs - * defined as output cannot be determined by reading GPDAT register, - * so we use shadow data register instead. The status of input pins - * is determined by reading GPDAT register. - */ - out_mask = in_be32(&plat->regs->gpdir); - - data_val = in_be32(&plat->regs->gpdat) & ~out_mask; - out_shadow = plat->data & out_mask; - - ret = ! !((data_val | out_shadow) & mpc8xxx_gpio2mask(gpio)); -#else - if (in_be32(&plat->regs->gpdat) & mpc8xxx_gpio2mask(gpio)) { - ret = 1; - } else { - ret = 0; - } -#endif - return ret; -} - -static int mpc8xxx_dm_gpio_get_function(struct udevice *dev, unsigned gpio) -{ - int ret = GPIOF_UNUSED; - struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); - - if (in_be32(&plat->regs->gpdir) & mpc8xxx_gpio2mask(gpio)) { - ret = GPIOF_OUTPUT; - } else { - ret = GPIOF_INPUT; - } - return ret; -} - -static const struct udevice_id mpc8xxx_gpio_ids[] = { - {.compatible = "fsl,mpc8349-gpio",}, - {.compatible = "fsl,mpc8572-gpio",}, - {.compatible = "fsl,mpc8610-gpio",}, - {.compatible = "fsl,mpc5121-gpio",}, - {.compatible = "fsl,mpc5125-gpio",}, - {.compatible = "fsl,pq3-gpio",}, - {.compatible = "fsl,qoriq-gpio",}, - {} -}; - -static const struct dm_gpio_ops mpc8xxx_gpio_ops = { - .direction_input = mpc8xxx_dm_gpio_dir_in, - .direction_output = mpc8xxx_dm_gpio_dir_out, - .get_value = mpc8xxx_dm_gpio_get, - .set_value = mpc8xxx_dm_gpio_set, - .get_function = mpc8xxx_dm_gpio_get_function, -}; - -#ifdef SPL_OF_CONTROL -static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev) -{ - int register_address; - struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); - - register_address = - fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); - if (register_address == -1) { - debug("%s: Invalid register offset %d\n", __func__, - register_address); - return -EINVAL; - } - plat->regs = map_physmem(register_address, sizeof(ccsr_gpio_t), - MAP_NOCACHE); - plat->gpio_count = MPC8XXX_GPIO_PINS; - plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, - "bank-name", NULL); - - return 0; -} -#endif - -static int mpc8xxx_gpio_probe(struct udevice *dev) -{ - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - struct mpc8xxx_gpio_platdata *plat = dev_get_platdata(dev); - - uc_priv->gpio_count = MPC8XXX_GPIO_PINS; - uc_priv->bank_name = plat->bank_name; - - return 0; -} - -U_BOOT_DRIVER(gpio_mpc8xxx) = { - .name = "gpio-mpc8xxx",.id = UCLASS_GPIO,.of_match = - mpc8xxx_gpio_ids,.ops = &mpc8xxx_gpio_ops, -#ifdef SPL_OF_CONTROL - .ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata, -#endif -.platdata_auto_alloc_size = - sizeof(struct mpc8xxx_gpio_platdata),.probe = mpc8xxx_gpio_probe,}; diff --git a/include/common.h b/include/common.h index e9f0dea..ee7a7a0 100644 --- a/include/common.h +++ b/include/common.h @@ -95,6 +95,7 @@ typedef volatile unsigned char vu_char; #define CONFIG_SYS_SUPPORT_64BIT_DATA #endif +#define DEBUG #ifdef DEBUG #define _DEBUG 1 #else diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h index f53c201..49550b7 100644 --- a/include/configs/simc-t10xx.h +++ b/include/configs/simc-t10xx.h @@ -10,6 +10,9 @@ #include "simc-t10x0.h" #include + +#define MPC85XX_GPIO_NR(port, pin) ((((port)-1)*32)+((pin)&31)) + /* * SIMC-T10xx board configuration file */ @@ -186,9 +189,20 @@ */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE 256 << 10 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +/* TODO CLEANUP #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) */ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) + + +/* + * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence + * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address + * (CONFIG_SYS_INIT_L3_VADDR) will be different. + */ +#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) + + #endif /* CONFIG_RAMBOOT_PBL */ #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) @@ -623,8 +637,6 @@ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_BOOTZ - #define CONFIG_SYS_NO_FLASH @@ -666,7 +678,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 3 /*-1 disables auto-boot*/ #define CONFIG_ZERO_BOOTDELAY_CHECK /* Also check for boot interruption, when bootdelay is zero */ #define CONFIG_BAUDRATE 115200 diff --git a/include/dm/platform_data/gpio_mpc8xxx.h b/include/dm/platform_data/gpio_mpc8xxx.h deleted file mode 100644 index 37e5241..0000000 --- a/include/dm/platform_data/gpio_mpc8xxx.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2016 Scalys B.V. - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MPC8XXX_GPIO_H -#define _MPC8XXX_GPIO_H - -struct mpc8xxx_gpio_platdata { - const char *bank_name; - ccsr_gpio_t *regs; - int gpio_count; -#if defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) - /* shadowed data register used to work around errata on - * MPC8572 and MPC8535 where it is not possible to read the - * state of an output pin */ - uint32_t data; -#endif -}; - -#endif -- cgit v0.10.2 From 974b7cc0a83ce4ad84dcb8b2eb12d85311dab35f Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Thu, 22 Sep 2016 10:09:53 +0200 Subject: Add secure boot support for simc-t1040 diff --git a/board/scalys/common/Makefile b/board/scalys/common/Makefile index 92c36e7..df3ebb8 100644 --- a/board/scalys/common/Makefile +++ b/board/scalys/common/Makefile @@ -9,3 +9,4 @@ obj-y += board_configuration_data.o ifdef CONFIG_SECURE_BOOT obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o endif +obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o diff --git a/board/scalys/common/fsl_chain_of_trust.c b/board/scalys/common/fsl_chain_of_trust.c new file mode 100644 index 0000000..dea231b --- /dev/null +++ b/board/scalys/common/fsl_chain_of_trust.c @@ -0,0 +1,158 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) +#include +#endif + +#ifdef CONFIG_ADDR_MAP +#include +#endif + +#ifdef CONFIG_FSL_CORENET +#include +#endif + +#ifdef CONFIG_LS102XA +#include +#endif + +#if defined(CONFIG_MPC85xx) +#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#else +#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR +#endif + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define gur_in32(a) in_le32(a) +#else +#define gur_in32(a) in_be32(a) +#endif + +/* Check the Boot Mode. If Secure, return 1 else return 0 */ +int fsl_check_boot_mode_secure(void) +{ + uint32_t val; + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); + + val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; + if (val == ITS_MASK) + return 1; + +#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) + /* For PBL based platforms check the SB_EN bit in RCWSR */ + val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; + if (val == RCW_SB_EN_MASK) + return 1; +#endif + +#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) + /* For Non-PBL Platforms, check the Device Status register 2*/ + val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; + if (val != MPC85xx_PORDEVSR2_SBC_MASK) + return 1; + +#endif + return 0; +} + +#ifndef CONFIG_SPL_BUILD +int fsl_setenv_chain_of_trust(void) +{ + /* Check Boot Mode + * If Boot Mode is Non-Secure, no changes are required + */ + if (fsl_check_boot_mode_secure() == 0) + return 0; + + /* If Boot mode is Secure, set the environment variables + * bootdelay = 0 (To disable Boot Prompt) + * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) + */ + setenv("bootdelay", "0"); + setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) +{ + int res; + + /* + * Check Boot Mode + * If Boot Mode is Non-Secure, skip validation + */ + if (fsl_check_boot_mode_secure() == 0) + return; + + printf("SPL: Validating U-Boot image\n"); + +#ifdef CONFIG_ADDR_MAP + init_addr_map(); +#endif + +#ifdef CONFIG_FSL_CORENET + if (pamu_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#endif + +#ifdef CONFIG_FSL_CAAM + if (sec_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT); +#endif + +/* + * dm_init_and_scan() is called as part of common SPL framework, so no + * need to call it again but in case of powerpc platforms which currently + * do not use common SPL framework, so need to call this function here. + */ +#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK)) + dm_init_and_scan(true); +#endif + res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH, + &img_addr); + + if (res == 0) + printf("SPL: Validation of U-boot successful\n"); +} + +#ifdef CONFIG_SPL_FRAMEWORK +/* Override weak funtion defined in SPL framework to enable validation + * of main u-boot image before jumping to u-boot image. + */ +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + typedef void __noreturn (*image_entry_noargs_t)(void); + uint32_t hdr_addr; + + image_entry_noargs_t image_entry = + (image_entry_noargs_t)(unsigned long)spl_image->entry_point; + + hdr_addr = (spl_image->entry_point + spl_image->size - + CONFIG_U_BOOT_HDR_SIZE); + spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point); + /* + * In case of failure in validation, spl_validate_uboot would + * not return back in case of Production environment with ITS=1. + * Thus U-Boot will not start. + * In Development environment (ITS=0 and SB_EN=1), the function + * may return back in case of non-fatal failures. + */ + + debug("image entry point: 0x%X\n", spl_image->entry_point); + image_entry(); +} +#endif /* ifdef CONFIG_SPL_FRAMEWORK */ +#endif /* ifdef CONFIG_SPL_BUILD */ diff --git a/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg b/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg new file mode 100644 index 0000000..6a69289 --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +0A0C000C 0C000000 00000000 00000000 +# HOLDOFF E8705000 +# core 0 enabled E8305000 +# PBL disabled F8505000 +# PBL enabled E8705000 + +#Holdoff enabled, PBL enabled No secure boot E8505000 +#Holdoff enabled, PBL enabled with secure boot E8705000 +81000002 00400002 E8305000 21000000 +00000000 CAFEBABE 00000000 00030FFC +00000314 0014500C 00000000 00000000 \ No newline at end of file diff --git a/board/scalys/simc-t10xx/simc-t10xx_nand_secure_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_nand_secure_pbi.cfg new file mode 100644 index 0000000..19dd100 --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10xx_nand_secure_pbi.cfg @@ -0,0 +1,46 @@ +#PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 bffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 (LAW 13) +09000cd0 00000000 +09000cd4 bffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 bf000000 +09000018 81000000 +#Configure IFC controller +#(IFC_CSPR1) +09124010 ff8000c3 +# IFC_CSOR_NAND +09124130 0108a100 +#IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND +091241c0 181c080c +091241c4 3850141a +091241c8 03008028 +091241cc 28000000 +#Set IFC_CCR clkdiv to 6 (IFC clock to platform clock/6=83.3MHz) +0912444c 05008000 +#Flush PBL data (Wait 0xFFFFF cycles ) +091380c0 000fffff +#Write Scratch Registers to setup pointer to ESBC +090e0200 bffd0000 +#Flush PBL data (Wait 0xFFFFF cycles ) +091380c0 000fffff \ No newline at end of file diff --git a/board/scalys/simc-t10xx/tlb.c b/board/scalys/simc-t10xx/tlb.c index 1890034..fa2dccb 100644 --- a/board/scalys/simc-t10xx/tlb.c +++ b/board/scalys/simc-t10xx/tlb.c @@ -31,7 +31,8 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. @@ -39,6 +40,18 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), + +#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot + * the physical address of the SRAM is at 0xbffc0000, + * and virtual address is 0xfffc0000 + */ + + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, + CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h index 49550b7..860a851 100644 --- a/include/configs/simc-t10xx.h +++ b/include/configs/simc-t10xx.h @@ -11,6 +11,8 @@ #include +#define CONFIG_SECURE_BOOT + #define MPC85XX_GPIO_NR(port, pin) ((((port)-1)*32)+((pin)&31)) /* @@ -37,14 +39,30 @@ /* PBI commands are cpu independent for now */ +/*#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg*/ + +#ifdef CONFIG_SECURE_BOOT +/* Secure boot enabled */ +#define CONFIG_SYS_FSL_PBL_PBI \ + $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nand_secure_pbi.cfg +#else +/* Secure boot disabled */ #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg +#endif + + + /* Set the RCW config depending on the CPU type */ #if defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1022_rcw.cfg #elif defined(CONFIG_PPC_T1040) +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg +#else #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_rcw.cfg #endif +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -76,7 +94,12 @@ #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) + + +#define CONFIG_SYS_NAND_U_BOOT_SIZE ( (2048-256) *1024) +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) + + #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) @@ -150,7 +173,7 @@ #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x100000 /* Refer to mtdparts */ +#define CONFIG_ENV_OFFSET 0x200000 /* Refer to mtdparts */ #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -533,11 +556,6 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -/* QE Connector is available on SiMC-T10x but not part of this development */ -#ifdef QE_CONNCECTOR -#define CONFIG_QE -#define CONFIG_U_QE -#endif /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SDCARD) @@ -550,7 +568,7 @@ #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_FMAN_FW_ADDR (0x140000) /* Refer to mtdparts */ +#define CONFIG_SYS_FMAN_FW_ADDR (0x240000) /* Refer to mtdparts: fman_ucode */ #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 @@ -669,12 +687,13 @@ "spi0=spife110000.0" #define MTDPARTS_DEFAULT \ - "mtdparts=fff800000.flash:," \ - "1M@0x0(u-boot)," \ + "mtdparts=fff800000.flash:" \ + "2M@0x0(u-boot)," \ "256k(env)," \ "256k(fman_ucode)," \ - "0x3fdc0000(ubipart)," \ - "1M@0x3ff00000(bbt)ro}" + "256k(qe_ucode)," \ + "0x3fc80000(ubipart)," \ + "1M@0x3ff00000(bbt)ro" /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 @@ -702,7 +721,7 @@ "TFTP_PATH=\0" \ \ "mtdids=nand0=fff800000.flash\0" \ - "mtdparts=mtdparts=fff800000.flash:1M@0x0(u-boot),256k(env),256k(fman_ucode),0x3fdc0000(ubipart),1M@0x3ff00000(bbt)ro\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ \ "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \ "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \ -- cgit v0.10.2 From f1ce322a9ffdbdba879ce2c784c48f196122f9a8 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Thu, 22 Sep 2016 10:32:48 +0200 Subject: Cleanup mtd env settings diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h index 860a851..62a4a0e 100644 --- a/include/configs/simc-t10xx.h +++ b/include/configs/simc-t10xx.h @@ -10,9 +10,6 @@ #include "simc-t10x0.h" #include - -#define CONFIG_SECURE_BOOT - #define MPC85XX_GPIO_NR(port, pin) ((((port)-1)*32)+((pin)&31)) /* @@ -556,7 +553,6 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME - /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SDCARD) /* @@ -683,8 +679,10 @@ #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 -#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ - "spi0=spife110000.0" +#define MTDIDS_DEFAULT \ + "nor0=fe8000000.nor," \ + "nand0=fff800000.flash," \ + "spi0=spife110000.0" #define MTDPARTS_DEFAULT \ "mtdparts=fff800000.flash:" \ @@ -720,7 +718,7 @@ "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \ "TFTP_PATH=\0" \ \ - "mtdids=nand0=fff800000.flash\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ \ "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \ -- cgit v0.10.2 From 8a5268d587c7b565684396dc69f70153cf5fd174 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Thu, 22 Sep 2016 10:33:18 +0200 Subject: Add Quicc Engine firmware loading support diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h index 62a4a0e..09a9d6d 100644 --- a/include/configs/simc-t10xx.h +++ b/include/configs/simc-t10xx.h @@ -553,6 +553,11 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME + +#define CONFIG_QE +#define CONFIG_U_QE +#define CONFIG_SYS_QE_FW_ADDR __stringify(CONFIG_LOADADDR) + /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SDCARD) /* @@ -741,6 +746,17 @@ "nand write ${loadaddr} fman_ucode ${filesize};" \ "\0" \ \ + "update-qe-ucode-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} iram_Type_A_T1040_r1.0.bin;" \ + "nand erase.part qe_ucode;" \ + "nand write ${loadaddr} qe_ucode ${filesize};" \ + "\0" \ + "load_qe_ucode="\ + "nand read ${loadaddr} qe_ucode;" \ + "qe fw ${loadaddr};" \ + "\0" \ + \ "update-ubi-rootfs="\ "dhcp;" \ "ubi part ubipart;" \ -- cgit v0.10.2 From 9e0a6d8408b2408a79686aa6ddd2a48e4a48bfea Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Thu, 22 Sep 2016 10:42:45 +0200 Subject: Remove debug flag diff --git a/include/common.h b/include/common.h index ee7a7a0..e9f0dea 100644 --- a/include/common.h +++ b/include/common.h @@ -95,7 +95,6 @@ typedef volatile unsigned char vu_char; #define CONFIG_SYS_SUPPORT_64BIT_DATA #endif -#define DEBUG #ifdef DEBUG #define _DEBUG 1 #else -- cgit v0.10.2 From 9784a395e8730d706e6e715911b33cf4837b5e6e Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Thu, 22 Sep 2016 15:06:48 +0200 Subject: Fixed default configuration option for simc-t10xx diff --git a/configs/T1_simc-t10xx_nand_defconfig b/configs/T1_simc-t10xx_nand_defconfig index 1f86ae3..b6275f8 100644 --- a/configs/T1_simc-t10xx_nand_defconfig +++ b/configs/T1_simc-t10xx_nand_defconfig @@ -34,6 +34,6 @@ CONFIG_CMD_DM=y CONFIG_SPL_DM=y CONFIG_DM=y CONFIG_DM_GPIO=y -CONFIG_MPC8XXX_GPIO=y +CONFIG_MPC85XX_GPIO=y CONFIG_SYS_MALLOC_F=n -- cgit v0.10.2