From ce9fc2dabf6b3f3853d375460d6bb9d1e8731c26 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Fri, 20 May 2016 10:18:13 +0200 Subject: Add T1040 support for scalys simc-t10xx diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig index 77ebe76..2b8d1a4 100644 --- a/board/scalys/simc-t10xx/Kconfig +++ b/board/scalys/simc-t10xx/Kconfig @@ -11,5 +11,63 @@ config SYS_VENDOR config SYS_CONFIG_NAME string default "simc-t10xx" + +config RAMBOOT_PBL + bool + default y + +config SPL_FSL_PBL + bool + default y + +choice + prompt "Bootsource" + +config NAND + bool + prompt "NAND boot" + default y + help + Select NAND as the bootsource + +endchoice + +choice + prompt "SYSCLK frequency" + default SYS_CLK_FREQ_100 + +config SYS_CLK_FREQ_66 + bool + prompt "66.6 MHz" + +config SYS_CLK_FREQ_100 + bool + prompt "100 MHz" + +endchoice + +choice + prompt "CPU type" + default PPC_T1040 + help + Select the exact type of CPU which is used on the version of the simc-t10xx module + +config PPC_T1020 + bool + prompt "T1020" + +config PPC_T1022 + bool + prompt "T1040" + +config PPC_T1040 + bool + prompt "T1040" + +config PPC_T1042 + bool + prompt "T1042" + +endchoice endif diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c index 5c45020..1656054 100644 --- a/board/scalys/simc-t10xx/dragonfruit.c +++ b/board/scalys/simc-t10xx/dragonfruit.c @@ -68,8 +68,10 @@ int scalys_carrier_setup_muxing(int serdes_config) gpio_direction_output(MUX_SER5_6_SEL, 1); break; + case 0x81: case 0x86: case 0x88: + case 0x89: /* A: PCIe1 (5/2.5G); B: sg.m3; C: sg.m1; D: sg.m2; * E: PCIe2 (5/2.5G); F:PCIe3 (5/2.5G); G: SATA2(3/1.5G); * H: SATA1(3/1.5G) */ diff --git a/board/scalys/simc-t10xx/eth.c b/board/scalys/simc-t10xx/eth.c index 2533137..2f5c401 100644 --- a/board/scalys/simc-t10xx/eth.c +++ b/board/scalys/simc-t10xx/eth.c @@ -13,6 +13,25 @@ #include #include + + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//#include "../common/fman.h" +//#include "../common/qixis.h" + + + + #include "../../freescale/common/fman.h" uint8_t sfp_phy_config[][2] = { @@ -33,6 +52,13 @@ int board_eth_init(bd_t *bis) int ret; int phy_addr = 0; +#ifdef CONFIG_VSC9953 + int lane; + phy_interface_t phy_int; + struct mii_dev *bus; + struct ccsr_scfg *scfg; +#endif + uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; uint32_t regval; @@ -106,7 +132,6 @@ int board_eth_init(bd_t *bis) */ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; - switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) @@ -116,7 +141,8 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(i, phy_addr); break; case PHY_INTERFACE_MODE_QSGMII: - fm_info_set_phy_address(i, 0); + /* TODO, get fixed phy here */ + fm_info_set_phy_address(i, i+2); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); @@ -134,6 +160,44 @@ int board_eth_init(bd_t *bis) fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); } + +#ifdef CONFIG_VSC9953 + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + int lane = -1; + int phy_addr = 0; + int phy_int = PHY_INTERFACE_MODE_NONE; + switch (i) { + case 0: + case 1: + case 2: + vsc9953_port_enable(i); + vsc9953_port_info_set_phy_int(i, PHY_INTERFACE_MODE_SGMII); + break; + case 3: + case 4: + case 5: + case 6: + case 7: + continue; + case 8: + /* FM1@DTSEC1 is connected to SW1@PORT8 */ + vsc9953_port_enable(i); + break; + case 9: + /* Enable L2 On MAC2 using SCFG */ + scfg = (struct ccsr_scfg *) CONFIG_SYS_MPC85xx_SCFG; + + out_be32(&scfg->esgmiiselcr, + in_be32(&scfg->esgmiiselcr) | + (0x80000000)); + vsc9953_port_enable(i); + break; + } + bus = lane; + + } +#endif + cpu_eth_init(bis); #endif return pci_eth_init(bis); diff --git a/board/scalys/simc-t10xx/simc-t1022_rcw.cfg b/board/scalys/simc-t10xx/simc-t1022_rcw.cfg new file mode 100644 index 0000000..1ddbe0c --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t1022_rcw.cfg @@ -0,0 +1,17 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +#120C0015 15000000 00000000 00000000 +#06000000 00C00002 E8104000 21000000 +#00000000 CAFEBABE 00000000 00030ffc +#00000314 0014500C 00000000 00000000 +# +#120C0015 15000000 00000000 00000000 +#06000000 00000002 E8105000 21000000 +#00000000 CAFEBABE 00000000 00230FFC +#00000714 0014500C 00000000 00000000 + +120C0015 15000000 00000000 00000000 +86000000 00000002 E8104000 21000000 +00000000 CAFEBABE 00000000 00030FFC +00000314 0014500C 00000000 00000000 diff --git a/board/scalys/simc-t10xx/simc-t1040_rcw.cfg b/board/scalys/simc-t10xx/simc-t1040_rcw.cfg new file mode 100644 index 0000000..ae0edf3 --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t1040_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +0A0C000C 0C000000 00000000 00000000 +81000002 00000002 E8105000 21000000 +00000000 CAFEBABE 00000000 00030FFC +00000314 0014500C 00000000 00000000 diff --git a/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg index 59e2c66..c5fd95d 100644 --- a/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg +++ b/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg @@ -29,15 +29,14 @@ #Configure IFC controller # (IFC_CSPR1) 09124010 ff8000c3 -# IFC_AMASK1 -#091240A0 C0000000 -#ECC DISABLED: -# 4K pages: 09124130 0110a200 +# IFC_CSOR_NAND 09124130 0108a100 # IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND 091241c0 181c080c 091241c4 3850141a 091241c8 03008028 091241cc 28000000 +# Set IFC_CCR clkdiv to 6 (IFC clock to platform clock/6=83.3MHz) +0912444c 05008000 #Flush PBL data (Wait 0xFFFFF cycles ) 091380c0 000fffff \ No newline at end of file diff --git a/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg b/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg deleted file mode 100644 index 1ddbe0c..0000000 --- a/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg +++ /dev/null @@ -1,17 +0,0 @@ -#PBL preamble and RCW header -AA55AA55 010E0100 -# -#120C0015 15000000 00000000 00000000 -#06000000 00C00002 E8104000 21000000 -#00000000 CAFEBABE 00000000 00030ffc -#00000314 0014500C 00000000 00000000 -# -#120C0015 15000000 00000000 00000000 -#06000000 00000002 E8105000 21000000 -#00000000 CAFEBABE 00000000 00230FFC -#00000714 0014500C 00000000 00000000 - -120C0015 15000000 00000000 00000000 -86000000 00000002 E8104000 21000000 -00000000 CAFEBABE 00000000 00030FFC -00000314 0014500C 00000000 00000000 diff --git a/configs/T1_simc-t10xx_nand_defconfig b/configs/T1_simc-t10xx_nand_defconfig index fb14e16..1f86ae3 100644 --- a/configs/T1_simc-t10xx_nand_defconfig +++ b/configs/T1_simc-t10xx_nand_defconfig @@ -1,5 +1,4 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_SIMC_T10XX=y diff --git a/include/configs/simc-t10x0.h b/include/configs/simc-t10x0.h new file mode 100644 index 0000000..75cae27 --- /dev/null +++ b/include/configs/simc-t10x0.h @@ -0,0 +1,18 @@ +#ifndef _SIMC_T10X0 +#define _SIMC_T10X0 + +#define CONFIG_PHY_VITESSE + +/* Enable VSC9953 L2 Switch driver on T1040 SoC */ +#define CONFIG_VSC9953 +#define CONFIG_CMD_ETHSW +#ifdef CONFIG_T1040RDB +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#else +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c +#endif + + +#endif /* _SIMC_T10X0 */ \ No newline at end of file diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h index 8c6f7be..8a13e92 100644 --- a/include/configs/simc-t10xx.h +++ b/include/configs/simc-t10xx.h @@ -7,6 +7,8 @@ #ifndef __SIMC_T10XX_H #define __SIMC_T10XX_H +#include "simc-t10x0.h" + /* * SIMC-T10xx board configuration file */ @@ -18,12 +20,27 @@ /* * System and DDR clock */ -#define CONFIG_SYS_CLK_FREQ 66666666 /* 66.67MHz */ -#define CONFIG_DDR_CLK_FREQ 133333333 /* 133.33MHz */ +#if defined(CONFIG_SYS_CLK_FREQ_66) +#define CONFIG_SYS_CLK_FREQ 66666666 /* 66.6 MHz */ +#elif defined(CONFIG_SYS_CLK_FREQ_100) +#define CONFIG_SYS_CLK_FREQ 100000000 /* 100 MHz */ +#endif + +#define CONFIG_DDR_CLK_FREQ 133333333 /* 133.33MHz */ #ifdef CONFIG_RAMBOOT_PBL + + + +/* PBI commands are cpu independent for now */ #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg + +/* Set the RCW config depending on the CPU type */ +#if defined(CONFIG_PPC_T1022) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1022_rcw.cfg +#elif defined(CONFIG_PPC_T1040) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_rcw.cfg +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -661,10 +678,12 @@ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ \ - "ethaddr=00:00:00:ca:fe:00\0" \ - "eth1addr=00:00:00:ca:fe:01\0" \ - "eth2addr=00:00:00:ca:fe:02\0" \ - "eth3addr=00:00:00:ca:fe:03\0" \ + "l2switchaddr=02:00:00:ba:be:00\0" \ + "ethaddr=02:00:00:ba:be:01\0" \ + "eth1addr=02:00:00:ba:be:02\0" \ + "eth2addr=02:00:00:ba:be:03\0" \ + "eth3addr=02:00:00:ba:be:04\0" \ + "eth4addr=02:00:00:ba:be:05\0" \ \ "autoload=no\0" \ "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \ -- cgit v0.10.2