From d1d9a153317f2c919d51742e009b55d6f5dde83b Mon Sep 17 00:00:00 2001
From: Evert Pap <evert.pap@sintecs.nl>
Date: Fri, 15 Jul 2016 14:39:04 +0200
Subject: Disable serdes PLL 2 in RCW


diff --git a/board/scalys/simc-t10xx/simc-t1040_rcw.cfg b/board/scalys/simc-t10xx/simc-t1040_rcw.cfg
index ae0edf3..323ea71 100644
--- a/board/scalys/simc-t10xx/simc-t1040_rcw.cfg
+++ b/board/scalys/simc-t10xx/simc-t1040_rcw.cfg
@@ -2,6 +2,6 @@
 AA55AA55 010E0100
 #
 0A0C000C 0C000000 00000000 00000000
-81000002 00000002 E8105000 21000000
+81000002 00400002 E8105000 21000000
 00000000 CAFEBABE 00000000 00030FFC
 00000314 0014500C 00000000 00000000
-- 
cgit v0.10.2