From fe039d31b2c99d09510b1b5ea355b6e658490b02 Mon Sep 17 00:00:00 2001 From: Evert Pap Date: Thu, 31 Mar 2016 17:35:05 +0200 Subject: Add support for the Scalys SimC-t10xx SOM diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index ccdf103..0f01db0 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -400,6 +400,10 @@ config TARGET_CYRUS_P5040 select ARCH_P5040 select PHYS_64BIT +config TARGET_SIMC_T10XX + bool "Support simc-t10xx" + select SUPPORT_SPL + endchoice config ARCH_B4420 @@ -1522,6 +1526,7 @@ source "board/freescale/t4rdb/Kconfig" source "board/gdsys/p1022/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/sbc8548/Kconfig" +source "board/scalys/simc-t10xx/Kconfig" source "board/socrates/Kconfig" source "board/varisys/cyrus/Kconfig" source "board/xes/xpedite520x/Kconfig" diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 184ff5a..bfda47d 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3204,7 +3204,7 @@ struct ccsr_scfg { #if defined(CONFIG_PPC_T1013) || defined(CONFIG_PPC_T1014) ||\ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) ||\ defined(CONFIG_PPC_T1023) || defined(CONFIG_PPC_T1024) ||\ - defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ + defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) #define CONFIG_SYS_MPC8XXX_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x130000) #define CONFIG_SYS_MPC8XXX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000) #define CONFIG_SYS_MPC8XXX_GPIO3_ADDR (CONFIG_SYS_IMMR + 0x132000) diff --git a/arch/powerpc/include/asm/mpc8xxx_gpio.h b/arch/powerpc/include/asm/mpc8xxx_gpio.h index d4a5b7c..1069638 100644 --- a/arch/powerpc/include/asm/mpc8xxx_gpio.h +++ b/arch/powerpc/include/asm/mpc8xxx_gpio.h @@ -6,6 +6,8 @@ #ifndef _POWERPC_ASM_MPC8XXX_GPIO_H #define _POWERPC_ASM_MPC8XXX_GPIO_H +#include + #define MPC8XXX_GPIO_NR(port, pin) ((((port)-1)*32)+((pin)&31)) #define MPC8XXX_GPIO_TO_PORT(gpio) (gpio/32) #define MPC8XXX_GPIO_TO_PIN(gpio) (gpio&31) @@ -86,7 +88,7 @@ static inline int mpc8xxx_gpio_get(uint32_t gpio, int value) break; #endif default: - return; + return -ENODEV; } /* Get inputs */ diff --git a/board/scalys/common/Makefile b/board/scalys/common/Makefile new file mode 100644 index 0000000..dc95801 --- /dev/null +++ b/board/scalys/common/Makefile @@ -0,0 +1,7 @@ +# Copyright 2016 Scalys B.V. +# opensource@scalys.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board_configuration_data.o diff --git a/board/scalys/common/board_configuration_data.c b/board/scalys/common/board_configuration_data.c new file mode 100644 index 0000000..fe96a2e --- /dev/null +++ b/board/scalys/common/board_configuration_data.c @@ -0,0 +1,393 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "board_configuration_data.h" + +DECLARE_GLOBAL_DATA_PTR; + +int add_mac_addressess_to_env(const void* blob) +{ + const char *propname; + const void *value; + int prop_offset, len; + int count = 0; + char mac_string[19], eth_string[10]; + uint8_t mac_address[6]; + + if (fdt_check_header(blob) != 0) { + printf( "Board Configuration Data FDT corrupt\n"); + return -1; + } + + int nodeoff = fdt_path_offset(blob, "/network"); + + if (nodeoff < 0) { + printf("Network node not found\n"); + return -1; + } + for (prop_offset = fdt_first_property_offset(blob, nodeoff); + prop_offset > 0; + prop_offset = fdt_next_property_offset(blob, prop_offset)) { + value = fdt_getprop_by_offset(blob, prop_offset, + &propname, &len); + if (!value) { + return -EINVAL; + } + + memcpy(mac_address, value, 6); + + //ret = fdtdec_get_byte_array( blob, prop_offset, propname, mac_address, 6 ); + + if (count) { + snprintf(eth_string, sizeof(eth_string), "eth%iaddr", count); + } + else { + snprintf(eth_string, sizeof(eth_string), "ethaddr"); + } + + snprintf(mac_string, sizeof(mac_string), + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_address[0], mac_address[1], mac_address[2], + mac_address[3], mac_address[4], mac_address[5] + ); + + printf("%s : [ %s ]\n", propname, mac_string ); + + setenv( eth_string, mac_string); + + count++; + + } + printf("Done reading BCD\n"); + + return 0; +} + +const void* get_boardinfo_eeprom(void) +{ + uint32_t bcd_data_lenght; + uint8_t *bcd_data = NULL; + uint32_t calculated_crc, received_crc; + int dtb_length; + int old_i2c_bus; + int ret = 0; + + old_i2c_bus = i2c_get_bus_num(); + + /* Set the selected I2C interface to the correct bus */ + i2c_set_bus_num(BCD_I2C_BUS); + + /* Read the last 4 bytes to determine the lenght of the DTB data */ + ret = i2c_read(BCD_I2C_ADDRESS, (BCD_EEPROM_SIZE-4), 2, (uint8_t*) &bcd_data_lenght, 4 ); + if (ret != 0) { + debug("Error reading bcd length\n"); + errno = -ENODEV; + goto err_no_free; + } + + /* Convert lenght from big endianess to architecture endianess */ + bcd_data_lenght = ntohl(bcd_data_lenght); + debug("bcd_data_lenght = %i\n", bcd_data_lenght ); + + if (bcd_data_lenght > BCD_EEPROM_SIZE ) { + debug("%02x %02x %02x %02x\n", + ( (uint8_t*) &bcd_data_lenght)[0], + ( (uint8_t*) &bcd_data_lenght)[1], + ( (uint8_t*) &bcd_data_lenght)[2], + ( (uint8_t*) &bcd_data_lenght)[3] ); + errno = -EMSGSIZE; + goto err_no_free; + } + + /* Allocate, and verify memory for the BCD data */ + bcd_data = (uint8_t*) malloc(bcd_data_lenght); + if (bcd_data == NULL) { + debug("Error locating memory for BCD data\n"); + goto err_no_free; + } + debug("Allocated memory for BCD data\n"); + + /* Read the DTB BCD data to memory */ + ret = i2c_read(BCD_I2C_ADDRESS, (BCD_EEPROM_SIZE-bcd_data_lenght), 2, (uint8_t*) bcd_data, bcd_data_lenght ); + debug("Read data from I2C bus\n"); + + if (ret != 0) { + debug("Error reading complete BCD data from EEPROM\n"); + errno = -ENOMEM; + goto err_free; + } + dtb_length = bcd_data_lenght - BCD_LENGTH_SIZE - BCD_HASH_SIZE; + + /* Calculate CRC on read DTB data */ + calculated_crc = crc32( 0, bcd_data, dtb_length); + + /* Received CRC is packed after the DTB data */ + received_crc = *((uint32_t*) &bcd_data[dtb_length]); + + /* Convert CRC from big endianess to architecture endianess */ + received_crc = ntohl(received_crc); + + if (calculated_crc != received_crc) { + debug("Checksum error. expected %08x, got %08x\n", + calculated_crc, received_crc); + free(bcd_data); + errno = -EBADMSG; + goto err_free; + } + + /* Everything checked out, return the BCD data. + * The caller is expected to free this data */ + return bcd_data; + +err_free: + /* free the allocated buffer */ + free(bcd_data); + +err_no_free: + /* Set the selected I2C interface back to the original bus */ + i2c_set_bus_num(old_i2c_bus); + + return NULL; +} + +#ifndef CONFIG_SPL_BUILD + +#ifndef CONFIG_CMD_FDT_MAX_DUMP +#define CONFIG_CMD_FDT_MAX_DUMP 64 +#endif + +/* + * Heuristic to guess if this is a string or concatenated strings. + */ + +static int is_printable_string(const void *data, int len) +{ + const char *s = data; + + /* zero length is not */ + if (len == 0) + return 0; + + /* must terminate with zero or '\n' */ + if (s[len - 1] != '\0' && s[len - 1] != '\n') + return 0; + + /* printable or a null byte (concatenated strings) */ + while (((*s == '\0') || isprint(*s) || isspace(*s)) && (len > 0)) { + /* + * If we see a null, there are three possibilities: + * 1) If len == 1, it is the end of the string, printable + * 2) Next character also a null, not printable. + * 3) Next character not a null, continue to check. + */ + if (s[0] == '\0') { + if (len == 1) + return 1; + if (s[1] == '\0') + return 0; + } + s++; + len--; + } + + /* Not the null termination, or not done yet: not printable */ + if (*s != '\0' || (len != 0)) + return 0; + + return 1; +} + +/* + * Print the property in the best format, a heuristic guess. Print as + * a string, concatenated strings, a byte, word, double word, or (if all + * else fails) it is printed as a stream of bytes. + */ +static void print_data(const void *data, int len) +{ + int j; + + /* no data, don't print */ + if (len == 0) + return; + + /* + * It is a string, but it may have multiple strings (embedded '\0's). + */ + if (is_printable_string(data, len)) { + puts("\""); + j = 0; + while (j < len) { + if (j > 0) + puts("\", \""); + puts(data); + j += strlen(data) + 1; + data += strlen(data) + 1; + } + puts("\""); + return; + } + + if ((len %4) == 0) { + if (len > CONFIG_CMD_FDT_MAX_DUMP) + printf("* 0x%p [0x%08x]", data, len); + else { + const __be32 *p; + + printf("<"); + for (j = 0, p = data; j < len/4; j++) + printf("0x%08x%s", fdt32_to_cpu(p[j]), + j < (len/4 - 1) ? " " : ""); + printf(">"); + } + } else { /* anything else... hexdump */ + if (len > CONFIG_CMD_FDT_MAX_DUMP) + printf("* 0x%p [0x%08x]", data, len); + else { + const u8 *s; + + printf("["); + for (j = 0, s = data; j < len; j++) + printf("%02x%s", s[j], j < len - 1 ? " " : ""); + printf("]"); + } + } +} + +/* + * Recursively print (a portion of) the working_fdt. The depth parameter + * determines how deeply nested the fdt is printed. + */ +#define MAX_LEVEL 4 +static int bcd_fdt_print(const void* address, int depth) +{ + static char tabs[MAX_LEVEL+1] = + "\t\t\t\t\t"; + const void *nodep; /* property node pointer */ + int nodeoffset; /* node offset from libfdt */ + int nextoffset; /* next node offset from libfdt */ + uint32_t tag; /* tag */ + int len; /* length of the property */ + int level = 0; /* keep track of nesting level */ + const struct fdt_property *fdt_prop; + const char *pathp; + + nodeoffset = fdt_path_offset (address, "/"); + if (nodeoffset < 0) { + /* + * Not found or something else bad happened. + */ + printf ("libfdt fdt_path_offset() returned %s\n", + fdt_strerror(nodeoffset)); + return 1; + } + + /* + * The user passed in a node path and no property, + * print the node and all subnodes. + */ + while(level >= 0) { + tag = fdt_next_tag(address, nodeoffset, &nextoffset); + switch(tag) { + case FDT_BEGIN_NODE: + pathp = fdt_get_name(address, nodeoffset, NULL); + if (level <= depth) { + if (pathp == NULL) + pathp = "/* NULL pointer error */"; + if (*pathp == '\0') + pathp = "/"; /* root is nameless */ + printf("%s%s {\n", + &tabs[MAX_LEVEL - level], pathp); + } + level++; + if (level >= MAX_LEVEL) { + printf("Nested too deep, aborting.\n"); + return 1; + } + break; + case FDT_END_NODE: + level--; + if (level <= depth) + printf("%s};\n", &tabs[MAX_LEVEL - level]); + if (level == 0) { + level = -1; /* exit the loop */ + } + break; + case FDT_PROP: + fdt_prop = fdt_offset_ptr(address, nodeoffset, + sizeof(*fdt_prop)); + pathp = fdt_string(address, + fdt32_to_cpu(fdt_prop->nameoff)); + len = fdt32_to_cpu(fdt_prop->len); + nodep = fdt_prop->data; + if (len < 0) { + printf ("libfdt fdt_getprop(): %s\n", + fdt_strerror(len)); + return 1; + } else if (len == 0) { + /* the property has no value */ + if (level <= depth) + printf("%s%s;\n", + &tabs[MAX_LEVEL - level], + pathp); + } else { + if (level <= depth) { + printf("%s%s = ", + &tabs[MAX_LEVEL - level], + pathp); + print_data (nodep, len); + printf(";\n"); + } + } + break; + case FDT_NOP: + printf("%s/* NOP */\n", &tabs[MAX_LEVEL - level]); + break; + case FDT_END: + return 1; + default: + if (level <= depth) + printf("Unknown tag 0x%08X\n", tag); + return 1; + } + nodeoffset = nextoffset; + } + return 0; +} + +int do_bcdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const void* bcd_dtc_blob; + int ret = 0; + + bcd_dtc_blob = get_boardinfo_eeprom(); + + if (bcd_dtc_blob != NULL) { + bcd_fdt_print(bcd_dtc_blob, 4); + } + + return ret; +} + +/* U_BOOT_CMD(name,maxargs,repeatable,command,"usage","help") */ +U_BOOT_CMD( + bcdinfo, + 1, + 1, + do_bcdinfo, + "Show the Board Configuration Data (stored in eeprom)", + "" +); +#endif \ No newline at end of file diff --git a/board/scalys/common/board_configuration_data.h b/board/scalys/common/board_configuration_data.h new file mode 100644 index 0000000..14cbec0 --- /dev/null +++ b/board/scalys/common/board_configuration_data.h @@ -0,0 +1,22 @@ +#ifndef _BCD_H +#define _BCD_H + +#define BCD_LENGTH_SIZE 4 +#define BCD_HASH_SIZE 4 + +#ifndef BCD_I2C_BUS +#define BCD_I2C_BUS 0 +#endif + +#ifndef BCD_I2C_ADDRESS +#define BCD_I2C_ADDRESS 0x51 +#endif + +#ifndef BCD_EEPROM_SIZE +#define BCD_EEPROM_SIZE 0x10000 +#endif + +const void* get_boardinfo_eeprom(void); +int add_mac_addressess_to_env(const void* blob); + +#endif /* _BCD_H */ diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig new file mode 100644 index 0000000..77ebe76 --- /dev/null +++ b/board/scalys/simc-t10xx/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SIMC_T10XX + +config SYS_BOARD + string + default "simc-t10xx" + +config SYS_VENDOR + string + default "scalys" + +config SYS_CONFIG_NAME + string + default "simc-t10xx" + +endif diff --git a/board/scalys/simc-t10xx/Makefile b/board/scalys/simc-t10xx/Makefile new file mode 100644 index 0000000..83ac551 --- /dev/null +++ b/board/scalys/simc-t10xx/Makefile @@ -0,0 +1,19 @@ +# Copyright 2016 Scalys B.V. +# opensource@scalys.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +UBOOTINCLUDE += -I$(srctree)/board/$(VENDOR)/common/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += simc-t10xx.o +obj-y += eth.o +obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o +obj-y += dragonfruit.o \ No newline at end of file diff --git a/board/scalys/simc-t10xx/ddr.c b/board/scalys/simc-t10xx/ddr.c new file mode 100644 index 0000000..ca5407e --- /dev/null +++ b/board/scalys/simc-t10xx/ddr.c @@ -0,0 +1,135 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ +#define DDR_RST_N MPC8XXX_GPIO_NR(2, 12) + +/* MT41K512M8RH-125 */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 0x100000000ULL, + .capacity = 0x200000000ULL, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 1, + .n_row_addr = 16, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = EDC_ECC, + .burst_lengths_bitmask = 0x0c, + .tckmin_x_ps = 1250, + .tckmax_ps = 1499, + .caslat_x = (1 << 11), + .taa_ps = 13750, + .trcd_ps = 13750, + .trp_ps = 13750, + .tras_ps = 35000, + .trc_ps = 48750, + .tfaw_ps = 30000, + .twr_ps = 15000, + .trfc_ps = 260000, + .trrd_ps = 6000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 70200000, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + + if (ctrl_num != 0) { + printf("Only 1 memory controller supported, but %i requested\n", + ctrl_num); + return; + } + + if (pdimm == NULL ) { + printf("Error, no valid dimm pararmeter supplied\n"); + return; + } + + if (!pdimm->n_ranks) { + printf("No ranks in dimm parameters. Configuration error?\n"); + return; + } + + /* set odt_rd_cfg and odt_wr_cfg. */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_wr_cfg = 4; + } + + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 13; + popts->wrlvl_start = 7; /* 7/8 clock delay */ + popts->wrlvl_ctl_2 = 0x06070809; + popts->wrlvl_ctl_3 = 0x0d0f0a09; + + popts->ddr_cdr1 = 0x800c0000; + popts->ddr_cdr2 = 0x00000001; + + /* Clock is launched 1/4 applied cycle after address/command */ + popts->clk_adjust = 4; +} + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Soldered-down discrete DDR3"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + +#ifdef GPIO_IN_SPL_WORKING + gpio_request(DDR_RST_N, "DDR_RST_N"); + gpio_direction_output(DDR_RST_N, 1); +#else + mpc8xxx_gpio_set(DDR_RST_N,1); +#endif + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + /* DDR has been initialised by SPL loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + + return dram_size; +} diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c new file mode 100644 index 0000000..5c45020 --- /dev/null +++ b/board/scalys/simc-t10xx/dragonfruit.c @@ -0,0 +1,89 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include "dragonfruit.h" + + +/* + * SERDER MUX Configuration pins: + * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL + * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL + * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL + * + * MUX_SER0_1_SEL + * 0: SERDES A => Slot1, lane 0 + * SERDES B => Slot1, lane 1 + * 1: SERDES A => CS4315 retimer => SFP+ 0 + * SERDES B => CS4315 retimer => SFP+ 1 + * + * MUX_SER2_3_SEL + * 0: SERDES C => Slot1, lane 2 + * SERDES D => Slot1, lane 3 + * 1: SERDES C => QSFP+ 2 + * SERDES D => QSFP+ 3 + * + * SERDES E => Slot 4, lane 0 + * + * MUX_SER5_6_SEL + * 0: SERDES F => SLOT4, lane 1 + * SERDES G => SLOT4, lane 2 + * 1: SERDES F => SLOT2 + * SERDES G => SLOT3 + * + * SERDES H => Slot 4, lane 3 + */ + +#define MUX_SER0_1_SEL MPC8XXX_GPIO_NR(2, 25) +#define MUX_SER2_3_SEL MPC8XXX_GPIO_NR(2, 26) +#define MUX_SER5_6_SEL MPC8XXX_GPIO_NR(2, 27) +#define SERDES_CLK_OE MPC8XXX_GPIO_NR(2, 29) + +int scalys_carrier_setup_muxing(int serdes_config) +{ + int ret = 0; + + ret = gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel"); + if (ret != 0) { + printf("gpio request failed(%i)\n", ret); + } + gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel"); + gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel"); + gpio_request(SERDES_CLK_OE, "serdes_clk_oe"); + + switch(serdes_config){ + case 0x06: + /* A-D: PCIe1 (5/2.5G); E: PCIe2 (5/2.5G); + * F: PCIe3 (5/2.5G); G: PCIe4 (5/2.5); H: SATA.1 (3/1.5G) */ + gpio_direction_output(MUX_SER0_1_SEL, 0); + gpio_direction_output(MUX_SER2_3_SEL, 0); + gpio_direction_output(MUX_SER5_6_SEL, 1); + + break; + case 0x86: + case 0x88: + /* A: PCIe1 (5/2.5G); B: sg.m3; C: sg.m1; D: sg.m2; + * E: PCIe2 (5/2.5G); F:PCIe3 (5/2.5G); G: SATA2(3/1.5G); + * H: SATA1(3/1.5G) */ + gpio_direction_output(MUX_SER0_1_SEL, 1); + gpio_direction_output(MUX_SER2_3_SEL, 1); + gpio_direction_output(MUX_SER5_6_SEL, 1); + + break; + default: + printf("Unsupported SERDES configuration (%02x)\n", serdes_config); + } + + /* Enable serdes clock */ + gpio_direction_output(SERDES_CLK_OE, 1); + + return ret; +} \ No newline at end of file diff --git a/board/scalys/simc-t10xx/dragonfruit.h b/board/scalys/simc-t10xx/dragonfruit.h new file mode 100644 index 0000000..900b2e4 --- /dev/null +++ b/board/scalys/simc-t10xx/dragonfruit.h @@ -0,0 +1,6 @@ +#ifndef _DRAGON_FRUIT_H +#define _DRAGON_FRUIT_H + +int scalys_carrier_setup_muxing(int serdes_config); + +#endif /* _DRAGON_FRUIT_H */ \ No newline at end of file diff --git a/board/scalys/simc-t10xx/eth.c b/board/scalys/simc-t10xx/eth.c new file mode 100644 index 0000000..2533137 --- /dev/null +++ b/board/scalys/simc-t10xx/eth.c @@ -0,0 +1,140 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../../freescale/common/fman.h" + +uint8_t sfp_phy_config[][2] = { + { 0x1b, 0x90 }, + { 0x1b, 0x84 }, + { 0x09, 0x0F }, + { 0x09, 0x00 }, + { 0x00, 0x81 }, + { 0x00, 0x40 }, +}; + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + uint8_t i2c_data; + int ret; + int phy_addr = 0; + + uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; + uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; + uint32_t regval; + + printf("Initializing Fman\n"); + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* Remove reset from Ethernet PHY's + * IFC_PERR_B : GPIO2_15 : eth1_reset + * IFC_CS_N2 : GPIO2_11 : eth2_reset */ +// gpio_set_value(2, 0); + + /* Clear outputs to activate reset */ + regval = in_be32(gpio2_gpdat); + regval &= ~((0x80000000 >> 11 ) | (0x80000000 >> 15)); + out_be32(gpio2_gpdat, regval); + + /* Set outputs to output mode */ + regval = in_be32(gpio2_gpdir); + regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15)); + out_be32(gpio2_gpdir, regval); + + /* Wait for 10 ms to to meet reset timing */ + mdelay(10); + + /* Set outputs to de-activate reset */ + regval = in_be32(gpio2_gpdat); + regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15)); + out_be32(gpio2_gpdat, regval); + + + /* Remove SFP TX_disable */ + i2c_set_bus_num(0); + i2c_data = 0x3b; + ret = i2c_write(0x22, 0x0E, 1, &i2c_data, 1); + + mdelay(100); + + i2c_set_bus_num(3); + + for (phy_addr=0; phy_addr<4; phy_addr++) { + i2c_data = (1 << phy_addr); + ret = i2c_write(0x70, 0, 1, &i2c_data, 1); + if (ret) { + printf("Error Setting SFP i2c MUX\n"); + break; + } + + for ( i = 0; i < 6; i++) { + ret = i2c_write(0x56, sfp_phy_config[i][0], 1, &(sfp_phy_config[i][1]), 1); + if (ret) { + printf("Error sfp phy(%i:%i):%02x to address %02x\n", phy_addr, i, sfp_phy_config[i][1],sfp_phy_config[i][0]); + break; + } + } + } + + /* Two external pin interfaces + * MAC1|MAC2|MAC3 SGMII interface + * MAC4|MAC5 EC1|EC2 RGMII interface + */ + + /* + * Program on board RGMII, SGMII PHY addresses. + */ + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_RGMII: + if (FM1_DTSEC4 == i) + phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; + if (FM1_DTSEC5 == i) + phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; + case PHY_INTERFACE_MODE_QSGMII: + fm_info_set_phy_address(i, 0); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + case PHY_INTERFACE_MODE_SGMII: + printf("TODO, add phy interface to SGMII\n"); + fm_info_set_phy_address(i, PHY_INTERFACE_MODE_NONE); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + //fm_info_set_phy_address(i, 0); + break; + } + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + } + cpu_eth_init(bis); +#endif + return pci_eth_init(bis); +} diff --git a/board/scalys/simc-t10xx/law.c b/board/scalys/simc-t10xx/law.c new file mode 100644 index 0000000..c3b5e85 --- /dev/null +++ b/board/scalys/simc-t10xx/law.c @@ -0,0 +1,32 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); \ No newline at end of file diff --git a/board/scalys/simc-t10xx/pci.c b/board/scalys/simc-t10xx/pci.c new file mode 100644 index 0000000..ab9edbb --- /dev/null +++ b/board/scalys/simc-t10xx/pci.c @@ -0,0 +1,77 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + + uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000; + uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008; + uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; + uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; + uint32_t regval; + + debug("%s\n", __FUNCTION__); + + //TODO, when present pins are available on the board, use them to enable only active slots + /* + * IRQ[0-3] : PCIe present detect signals + * IRQ[0] : SLOT1_PRSNT2_N : XXX + * IRQ[1] : SLOT2_PRSNT2_N : XXX + * IRQ[2] : SLOT3_PRSNT2_N : XXX + * IRQ[3] : SLOT4_PRSNT2_N : XXX + * + * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 + * IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N + * IFC_CS_N5 : GPIO1_IO10 : PCIe SLOT2_REFCLK_OE_N + * IFC_CS_N6 : GPIO1_IO11 : PCIe SLOT3_REFCLK_OE_N + * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N + */ + + /* Set output to 0 to enable reference clocks */ + regval = in_be32(gpio1_gpdat); + regval &= ~( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) ); + out_be32(gpio1_gpdat, regval); + + /* Set Enable outputs*/ + regval = in_be32(gpio1_gpdir); + regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) ); + out_be32(gpio1_gpdir, regval); + + + + /* Remove reset from PCIe devices */ + + /* Set IFC_PAR0 to output mode */ + regval = in_be32(gpio2_gpdir); + regval |= ( 0x80000000 >> 13 ); + out_be32(gpio2_gpdir, regval); + + /* Set output to 1 to clear reset */ + regval = in_be32(gpio2_gpdat); + regval |= ( 0x80000000 >> 13 ); + out_be32(gpio2_gpdat, regval); + + /* Wait for 100 ms to allow the PCIe device to become ready */ + mdelay(100); + + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/scalys/simc-t10xx/simc-t10xx.c b/board/scalys/simc-t10xx/simc-t10xx.c new file mode 100644 index 0000000..f5b8a2c --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10xx.c @@ -0,0 +1,147 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dragonfruit.h" +#include + + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: simc-t10xx\n" ); + return 0; +} + +int misc_init_r(void) +{ + const void* bcd_dtc_blob; + int serdes_config; + ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int ret; + /* + * Initialize and set the LED's on the module to indicate u-boot is alive + * IFC_A30 : led green : GPIO2_30 + * IFC_A31 : led red : GPIO2_31 + */ + #define MODULE_LED_RED MPC8XXX_GPIO_NR(2, 31) + #define MODULE_LED_GREEN MPC8XXX_GPIO_NR(2, 30) + gpio_request(MODULE_LED_RED, "module_led_red"); + gpio_request(MODULE_LED_GREEN, "module_led_green"); + + gpio_direction_output(MODULE_LED_RED, 0); + gpio_direction_output(MODULE_LED_GREEN, 1); + + /* SERDES configuration is determined boot time through the RCW config. + * It is located in the fourth RCW word (bit 128-135 of the RCW). */ + serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24); + scalys_carrier_setup_muxing(serdes_config); + + bcd_dtc_blob = get_boardinfo_eeprom(); + if (bcd_dtc_blob != NULL) { + /* Board Configuration Data is intact, ready for parsing */ + ret = add_mac_addressess_to_env(bcd_dtc_blob); + if (ret != 0) { + printf("Error adding BCD data to environement\n"); + } + } + + return 0; +} + +/* Platform data for the GPIOs */ +static const struct mpc8xxx_gpio_platdata gpio_platdata[] = { + { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO1_ADDR, + .bank_name = "GPIO1_" }, + { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO2_ADDR, + .bank_name = "GPIO2_" }, + { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO3_ADDR, + .bank_name = "GPIO3_" }, + { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO4_ADDR, + .bank_name = "GPIO4_" }, +}; + +U_BOOT_DEVICES(mpc8xxx_gpios) = { + { "gpio-mpc8xxx", &gpio_platdata[0] }, + { "gpio-mpc8xxx", &gpio_platdata[1] }, + { "gpio-mpc8xxx", &gpio_platdata[2] }, + { "gpio-mpc8xxx", &gpio_platdata[3] }, +}; + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + debug( "ft_board_setup\n" ); + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + debug( "fdt_fixup_memory\n" ); + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + debug( "pci_of_setup\n" ); + FT_FSL_PCI_SETUP; +#endif + debug( "fdt_fixup_liodn\n" ); + fdt_fixup_liodn(blob); + +#ifdef CONFIG_HAS_FSL_DR_USB + debug( "fdt_fixup_dr_usb\n" ); + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + debug( "fdt_fixup_fman_ethernet\n" ); + fdt_fixup_fman_ethernet(blob); +#endif + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + struct fsl_esdhc_cfg *cfg; + + cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); + cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + cfg->sdhc_clk = gd->arch.sdhc_clk; + cfg->max_bus_width = 4; + return fsl_esdhc_initialize(bis, cfg); + + return 0; +} + +#if 0 +void board_detail(void) +{ + do_bcdinfo(); +} +#endif \ No newline at end of file diff --git a/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg new file mode 100644 index 0000000..59e2c66 --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg @@ -0,0 +1,43 @@ +#PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 (LAW 13) +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure IFC controller +# (IFC_CSPR1) +09124010 ff8000c3 +# IFC_AMASK1 +#091240A0 C0000000 +#ECC DISABLED: +# 4K pages: 09124130 0110a200 +09124130 0108a100 +# IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND +091241c0 181c080c +091241c4 3850141a +091241c8 03008028 +091241cc 28000000 +#Flush PBL data (Wait 0xFFFFF cycles ) +091380c0 000fffff \ No newline at end of file diff --git a/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg b/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg new file mode 100644 index 0000000..1ddbe0c --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg @@ -0,0 +1,17 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +#120C0015 15000000 00000000 00000000 +#06000000 00C00002 E8104000 21000000 +#00000000 CAFEBABE 00000000 00030ffc +#00000314 0014500C 00000000 00000000 +# +#120C0015 15000000 00000000 00000000 +#06000000 00000002 E8105000 21000000 +#00000000 CAFEBABE 00000000 00230FFC +#00000714 0014500C 00000000 00000000 + +120C0015 15000000 00000000 00000000 +86000000 00000002 E8104000 21000000 +00000000 CAFEBABE 00000000 00030FFC +00000314 0014500C 00000000 00000000 diff --git a/board/scalys/simc-t10xx/spl.c b/board/scalys/simc-t10xx/spl.c new file mode 100644 index 0000000..3675169 --- /dev/null +++ b/board/scalys/simc-t10xx/spl.c @@ -0,0 +1,112 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + // TODO i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/scalys/simc-t10xx/tlb.c b/board/scalys/simc-t10xx/tlb.c new file mode 100644 index 0000000..1890034 --- /dev/null +++ b/board/scalys/simc-t10xx/tlb.c @@ -0,0 +1,123 @@ +/* + * Copyright 2016 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_PCI + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), +#endif + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/T1_simc-t10xx_nand_defconfig b/configs/T1_simc-t10xx_nand_defconfig new file mode 100644 index 0000000..fb14e16 --- /dev/null +++ b/configs/T1_simc-t10xx_nand_defconfig @@ -0,0 +1,40 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_SIMC_T10XX=y + + +CONFIG_HUSH_PARSER=y + +CONFIG_CMD_ECHO=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_GPIO=y + +CONFIG_CMD_FLASH=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_IMLS=n +CONFIG_CMD_I2C=y + +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB=y + +CONFIG_OF_LIBFDT=y +CONFIG_SPL_OF_LIBFDT=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_OF_BOARD_SETUP=y + +CONFIG_CMD_DM=y +CONFIG_SPL_DM=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_MPC8XXX_GPIO=y + +CONFIG_SYS_MALLOC_F=n diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h new file mode 100644 index 0000000..9e7b54b --- /dev/null +++ b/include/configs/simc-t10xx.h @@ -0,0 +1,722 @@ +/* + * Copyright 2016 Scalys B.V. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SIMC_T10XX_H +#define __SIMC_T10XX_H + +/* + * SIMC-T10xx board configuration file + */ +#define CONFIG_PHYS_64BIT +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) /* MT29F8G08ABBCAH4*/ + +/* + * System and DDR clock + */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* 66.67MHz */ +#define CONFIG_DDR_CLK_FREQ 133333333 /* 133.33MHz */ + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg + +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT + +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x30001000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif /* CONFIG_SPL_BUILD */ + +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif /* CONFIG_NAND */ + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +/* High Level Configuration Options */ +#define CONFIG_E500 /* BOOKE e500 family */ +#include +#define CONFIG_BOOKE +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ + + +/* #define CONFIG_DEEP_SLEEP */ /* support deep sleep */ +#define CONFIG_SILENT_CONSOLE + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif /* CONFIG_RESET_VECTOR_ADDRESS */ + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + + +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCI_INDIRECT_BRIDGE + + +/* The number of available PCI controllers depends on the RCW */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ + +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x100000 /* Refer to mtdparts */ +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif /* CONFIG_SPIFLASH */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC + +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0x0BADC0DE +#endif /* CONFIG_DDR_ECC */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +/* #define CONFIG_SYS_DRAM_TEST Executes a memoty test at U-Boot start */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST + +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif /* CONFIG_RAMBOOT_PBL */ +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR (2) +#define CONFIG_CHIP_SELECTS_PER_CTRL (4) + +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_FSL_DDR3 + +#define CONFIG_SYS_SDRAM_SIZE 8192 /* In MByte, for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) + +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC on encode */ \ + CSOR_NAND_ECC_DEC_EN | /* ECC on decode */ \ + CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \ + CSOR_NAND_RAL_3 | /* RAL = 3Byes */ \ + CSOR_NAND_PGS_2K | /* Page Size = 2K */ \ + CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \ + CSOR_NAND_PB(64)) /* Pages Per Block = 64 */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) + +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) + +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) + +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +/*#define CONFIG_CMD_NAND*/ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +/*#define CONFIG_BOARD_EARLY_INIT_R*/ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +#define CONFIG_SPL_GPIO_SUPPORT + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) + +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif + +/* Use the HUSH parser */ +/*#define CONFIG_SYS_HUSH_PARSER*/ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ + + +/* new uImage format support */ +#if 0 +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#endif + + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C3_SPEED 400000 +#define CONFIG_SYS_FSL_I2C4_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 4, Base address 203000 */ +#ifdef CONFIG_PCIE4 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 +#define CONFIG_E1000_SPI +#define CONFIG_CMD_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 + +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA + +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_DOS_PARTITION +#endif + + +#define CONFIG_USB_EHCI_FSL +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif /* CONFIG_USB_EHCI*/ + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +/* QE Connector is available on SiMC-T10x but not part of this development */ +#ifdef QE_CONNCECTOR +#define CONFIG_QE +#define CONFIG_U_QE +#endif + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (0x140000) /* Refer to mtdparts */ +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif + + +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHY_MARVELL +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x00 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x01 + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#endif + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 1000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +#define CONFIG_CMD_BOOTZ + +#define CONFIG_SYS_NO_FLASH + + +#ifdef CONFIG_SECURE_BOOT +#include +#define CONFIG_CMD_BLOB +#endif + +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +/* #define CONFIG_UBI_SILENCE_MSG */ +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_SPI_FLASH +#define CONFIG_FSL_ESPI + +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION + +/*#define CONFIG_CMD_SF*/ +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ + "spi0=spife110000.0" + +#define MTDPARTS_DEFAULT \ + "mtdparts=fff800000.flash:," \ + "1M@0x0(u-boot)," \ + "256k(env)," \ + "256k(fman_ucode)," \ + "0x3fdc0000(ubipart)," \ + "1M@0x3ff00000(bbt)ro}" + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define CONFIG_BOOTDELAY 3 /*-1 disables auto-boot*/ +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=" \ + "fsl_ddr:bank_intlv=null;"\ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + \ + "ethaddr=00:00:00:ca:fe:00\0" \ + "eth1addr=00:00:00:ca:fe:01\0" \ + "eth2addr=00:00:00:ca:fe:02\0" \ + "eth3addr=00:00:00:ca:fe:03\0" \ + \ + "autoload=no\0" \ + "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \ + "TFTP_PATH=\0" \ + \ + "mtdids=nand0=fff800000.flash\0" \ + "mtdparts=mtdparts=fff800000.flash:1M@0x0(u-boot),256k(env),256k(fman_ucode),0x3fdc0000(ubipart),1M@0x3ff00000(bbt)ro\0" \ + \ + "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \ + "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \ + "i2c mw 0x2e 0x5f 0xc8;i2c mw 0x2e 0x60 0xc8;i2c mw 0x2e 0x61 0xc8;" \ + "i2c mw 0x2e 0x30 0x20;i2c mw 0x2e 0x31 0x20;i2c mw 0x2e 0x32 0x20;\0"\ + \ + "update-uboot=dhcp; tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin; if test $? = \"0\"; then nand erase.part u-boot; nand write ${loadaddr} 0 ${filesize};fi\0" \ + "update-uboot-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin;" \ + "nand erase.part u-boot;" \ + "nand write ${loadaddr} u-boot ${filesize};" \ + "\0" \ + \ + "update-fman-ucode-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} fsl_fman_ucode_t1040_r1.1_106_4_17.bin;" \ + "nand erase.part fman_ucode;" \ + "nand write ${loadaddr} fman_ucode ${filesize};" \ + "\0" \ + \ + "update-ubi-rootfs="\ + "dhcp;" \ + "ubi part ubipart;" \ + "if test $? = \"0\"; then " \ + "tftp ${TFTP_PATH}/fsl-image-core-simc-t1022-tcb-02.ubifs;" \ + "if test $? = \"0\"; then " \ + "ubi write ${loadaddr} rootfs ${filesize};" \ + "fi;" \ + "fi;" \ + "\0" \ + \ + "ubiboot=" \ + "ubi part ubipart;" \ + "ubifsmount ubi0:rootfs;" \ + "ubifsload ${fitaddr} /boot/fitImage.itb;" \ + "run set_ubiboot_args;" \ + "bootm ${fitaddr}#conf@1" \ + "\0" \ + \ + "set_ubiboot_args=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=3 ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0" \ + \ + "netboot=dhcp; tftp ${fitaddr} ${TFTP_PATH}/fitImage.itb; bootm ${fitaddr}#conf@1\0" \ + \ + "bootcmd=run setfans; usb start; run ubiboot\0" \ + \ + "bootargs_sata=rootfstype=ext3 root=/dev/sda1\0" \ + "bootargs=console=ttyS0,115200 rootwait panic=10\0" \ + +#endif /* SIMC_T10XX_H */ -- cgit v0.10.2