From 20bb165c1fb194a940de74ea428b40419ac3fcaa Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 14:26:22 +0800 Subject: ARM: dts: sama5d2: add clock property for uart1 node Add clock property for uart1 node. Signed-off-by: Wenyou Yang diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index a881d9e..d976fd4 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -600,6 +600,8 @@ uart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; + clocks = <&uart1_clk>; + clock-names = "usart"; status = "disabled"; }; -- cgit v0.10.2 From 4529ee3bc5fbb407567ed5e94687162d7e115fb5 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 14:26:23 +0800 Subject: ARM: dts: sama5d2_xplained: update for SPL Add the "u-boot,dm-pre-reloc" property to determine which nodes which are needed by SPL and by the board_init_f stage. Signed-off-by: Wenyou Yang diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts index 3709437..3e624f1 100644 --- a/arch/arm/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/dts/at91-sama5d2_xplained.dts @@ -7,6 +7,7 @@ compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; chosen { + u-boot,dm-pre-reloc; stdout-path = &uart1; }; @@ -28,6 +29,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; status = "okay"; + u-boot,dm-pre-reloc; }; sdmmc1: sdio-host@b0000000 { @@ -35,6 +37,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; status = "okay"; /* conflict with qspi0 */ + u-boot,dm-pre-reloc; }; apb { @@ -67,11 +70,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; status = "okay"; + u-boot,dm-pre-reloc; spi_flash@0 { compatible = "spi-flash"; reg = <0>; spi-max-frequency = <50000000>; + u-boot,dm-pre-reloc; }; }; @@ -90,6 +95,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; status = "okay"; + u-boot,dm-pre-reloc; }; i2c1: i2c@fc028000 { @@ -146,6 +152,7 @@ , ; bias-pull-up; + u-boot,dm-pre-reloc; }; pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { @@ -154,6 +161,7 @@ , ; bias-disable; + u-boot,dm-pre-reloc; }; pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { @@ -163,12 +171,14 @@ , ; bias-pull-up; + u-boot,dm-pre-reloc; }; pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { pinmux = , ; bias-disable; + u-boot,dm-pre-reloc; }; pinctrl_spi0_default: spi0_default { @@ -176,12 +186,14 @@ , ; bias-disable; + u-boot,dm-pre-reloc; }; pinctrl_uart1_default: uart1_default { pinmux = , ; bias-disable; + u-boot,dm-pre-reloc; }; pinctrl_usb_default: usb_default { diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index d976fd4..8d89b83 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -29,6 +29,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + u-boot,dm-pre-reloc; usb1: ohci@00400000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; @@ -66,6 +67,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + u-boot,dm-pre-reloc; pmc: pmc@f0014000 { compatible = "atmel,sama5d2-pmc", "syscon"; @@ -73,10 +75,12 @@ #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; + u-boot,dm-pre-reloc; main: mainck { compatible = "atmel,at91sam9x5-clk-main"; #clock-cells = <0>; + u-boot,dm-pre-reloc; }; plla: pllack@0 { @@ -87,6 +91,7 @@ atmel,clk-input-range = <12000000 12000000>; #atmel,pll-clk-output-range-cells = <4>; atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; + u-boot,dm-pre-reloc; }; plladiv: plladivck { @@ -117,6 +122,7 @@ compatible = "atmel,at91sam9x5-clk-utmi"; #clock-cells = <0>; clocks = <&main>; + u-boot,dm-pre-reloc; }; mck: masterck { @@ -125,12 +131,14 @@ clocks = <&main>, <&plladiv>, <&utmi>; atmel,clk-output-range = <124000000 166000000>; atmel,clk-divisors = <1 2 4 3>; + u-boot,dm-pre-reloc; }; h32ck: h32mxck { #clock-cells = <0>; compatible = "atmel,sama5d4-clk-h32mx"; clocks = <&mck>; + u-boot,dm-pre-reloc; }; usb: usbck { @@ -221,6 +229,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&h32ck>; + u-boot,dm-pre-reloc; macb0_clk: macb0_clk@5 { #clock-cells = <0>; @@ -248,6 +257,7 @@ #clock-cells = <0>; reg = <18>; atmel,clk-output-range = <0 83000000>; + u-boot,dm-pre-reloc; }; flx0_clk: flx0_clk@19 { @@ -290,6 +300,7 @@ #clock-cells = <0>; reg = <25>; atmel,clk-output-range = <0 83000000>; + u-boot,dm-pre-reloc; }; uart2_clk: uart2_clk@26 { @@ -326,6 +337,7 @@ #clock-cells = <0>; reg = <33>; atmel,clk-output-range = <0 83000000>; + u-boot,dm-pre-reloc; }; spi1_clk: spi1_clk@34 { @@ -430,6 +442,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&mck>; + u-boot,dm-pre-reloc; dma0_clk: dma0_clk@6 { #clock-cells = <0>; @@ -469,11 +482,13 @@ sdmmc0_hclk: sdmmc0_hclk@31 { #clock-cells = <0>; reg = <31>; + u-boot,dm-pre-reloc; }; sdmmc1_hclk: sdmmc1_hclk@32 { #clock-cells = <0>; reg = <32>; + u-boot,dm-pre-reloc; }; lcdc_clk: lcdc_clk@45 { @@ -503,15 +518,18 @@ #size-cells = <0>; interrupt-parent = <&pmc>; clocks = <&main>, <&plla>, <&utmi>, <&mck>; + u-boot,dm-pre-reloc; sdmmc0_gclk: sdmmc0_gclk@31 { #clock-cells = <0>; reg = <31>; + u-boot,dm-pre-reloc; }; sdmmc1_gclk: sdmmc1_gclk@32 { #clock-cells = <0>; reg = <32>; + u-boot,dm-pre-reloc; }; tcb0_gclk: tcb0_gclk@35 { @@ -663,9 +681,11 @@ clocks = <&pioA_clk>; gpio-controller; #gpio-cells = <2>; + u-boot,dm-pre-reloc; pinctrl { compatible = "atmel,sama5d2-pinctrl"; + u-boot,dm-pre-reloc; }; }; }; -- cgit v0.10.2 From d4ce9e7bbf91e6b5cd25c93eb165e54e66bbe1ad Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 14:26:24 +0800 Subject: configs: sama5d2_xplained: enable CONFIG_DM_ETH Enable CONFIG_DM_ETH to make MACB to support driver model. Because the USB Ether doesn't support driver model so far, remove this feature. Signed-off-by: Wenyou Yang diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 500f497..8378c4e 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -48,6 +48,8 @@ CONFIG_MMC_SDHCI_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 9fc8aa2..ea51293 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -47,6 +47,8 @@ CONFIG_MMC_SDHCI_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index ea28fce..17384a3 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -38,21 +38,10 @@ /* NAND flash */ #undef CONFIG_CMD_NAND -/* USB device */ -#define CONFIG_USB_ETHER -#define CONFIG_USB_ETH_RNDIS -#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2 XPlained" - /* I2C */ #define AT24MAC_ADDR 0x5c #define AT24MAC_REG 0x9a -/* Ethernet Hardware */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY - /* LCD */ #ifdef CONFIG_LCD -- cgit v0.10.2 From a66e4d00df3e0ff64dc65d9618204a91095c27bb Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 14:26:25 +0800 Subject: board: sama5d2_xplained: clean up macb init code Because the MACB driver supports the driver model and device tree, the pins configuration and clock enabling are handled by the pinctrl driver and clock driver, remove this hardcoded init code. The USB Ether init code is removed as well. Signed-off-by: Wenyou Yang diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index c5337af..5f38ebc 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -12,15 +12,12 @@ #include #include #include -#include -#include #include #include #include #include #include #include -#include #include #include #include @@ -118,22 +115,6 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */ -static void board_gmac_hw_init(void) -{ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ - atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ - - at91_periph_clk_enable(ATMEL_ID_GMAC); -} - static void board_uart1_hw_init(void) { atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ @@ -167,18 +148,12 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_MACB - board_gmac_hw_init(); -#endif #ifdef CONFIG_LCD board_lcd_hw_init(); #endif #ifdef CONFIG_CMD_USB board_usb_hw_init(); #endif -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - at91_udp_hw_init(); -#endif return 0; } @@ -190,24 +165,6 @@ int dram_init(void) return 0; } -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); -#endif - -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif -#endif - - return rc; -} - #ifdef CONFIG_CMD_I2C static int set_ethaddr_from_eeprom(void) { -- cgit v0.10.2 From ed03b1ba3c956648f7b4e42978d797c8f1b9f269 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 14:26:26 +0800 Subject: board: sama5d2_xplained: remove uart1 init Due to the pin configuration and clock enabling is handling by the driver, remove the unneeded hardcode uart1 init during board_early_init_f stage. Signed-off-by: Wenyou Yang diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 5f38ebc..c23cb0e 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -115,6 +115,7 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */ +#ifdef CONFIG_DEBUG_UART_BOARD_INIT static void board_uart1_hw_init(void) { atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ @@ -123,7 +124,6 @@ static void board_uart1_hw_init(void) at91_periph_clk_enable(ATMEL_ID_UART1); } -#ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { board_uart1_hw_init(); @@ -135,8 +135,6 @@ int board_early_init_f(void) { #ifdef CONFIG_DEBUG_UART debug_uart_init(); -#else - board_uart1_hw_init(); #endif return 0; -- cgit v0.10.2 From 5521d9e9e7a9360425088bc7f35b337fcf145b1d Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 14:26:27 +0800 Subject: board: sama5d2_xplained: remove unnecessary header files Remove the unnecessary header files. Signed-off-by: Wenyou Yang diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index c23cb0e..48f45b3 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -11,8 +11,6 @@ #include #include #include -#include -#include #include #include #include -- cgit v0.10.2 From 62904b7346e222208f31e330b2fa1f1deae8fbef Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 14:26:28 +0800 Subject: configs: sama5d2_xplained: update for SPL Enable config options to support the SPL, increase the malloc memory size for the SPL and board_init_f stage and increase the memory space for the SPL binary. Signed-off-by: Wenyou Yang diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 8378c4e..f064a43 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -8,12 +8,15 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -30,8 +33,10 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_AT91=y @@ -51,12 +56,13 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xf8020000 -CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_CLOCK=83000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index ea51293..70a17ed 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -4,9 +4,11 @@ CONFIG_TARGET_SAMA5D2_XPLAINED=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" @@ -29,8 +31,10 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_AT91=y @@ -50,12 +54,13 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xf8020000 -CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_CLOCK=83000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index 17384a3..f044f0e 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -20,10 +20,10 @@ #define CONFIG_SYS_SDRAM_SIZE 0x20000000 #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x210000 +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 #else #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ @@ -73,7 +73,7 @@ /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x200000 -#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x18000 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 @@ -89,7 +89,7 @@ #elif CONFIG_SYS_USE_SERIALFLASH #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 #endif -- cgit v0.10.2 From 0d00f9b6c136634e673a7412d99df68aaa6c9a6a Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Thu, 23 Mar 2017 14:35:33 +0800 Subject: board: sama5d4ek: fix DD2 configuration Fix the DDR2 configuration to make SPL work. Signed-off-by: Wenyou Yang diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h index f6bcecd..803501f 100644 --- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h +++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h @@ -186,9 +186,14 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7 -#define ATMEL_MPDDRC_IO_CALIBR_TZQIO 0x7f +#define ATMEL_MPDDRC_IO_CALIBR_TZQIO (0x7f << 8) #define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x) (((x) & 0x7f) << 8) +#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP (0xf << 16) +#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP_(x) (((x) & 0xf) << 16) +#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN (0xf << 20) +#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN_(x) (((x) & 0xf) << 20) + #define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB (0x1 << 4) /* Bit field in Read Data Path Register */ diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index ffb4a50..b2e7979 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -230,7 +230,6 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) ATMEL_MPDDRC_CR_NR_ROW_14 | ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | ATMEL_MPDDRC_CR_NB_8BANKS | - ATMEL_MPDDRC_CR_NDQS_DISABLED | ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | ATMEL_MPDDRC_CR_UNAL_SUPPORTED); @@ -260,6 +259,8 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2) void mem_init(void) { struct atmel_mpddrc_config ddr2; + const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + u32 tmp; ddr2_conf(&ddr2); @@ -267,6 +268,19 @@ void mem_init(void) at91_periph_clk_enable(ATMEL_ID_MPDDRC); at91_system_clk_enable(AT91_PMC_DDR); + tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE; + writel(tmp, &mpddr->rd_data_path); + + tmp = readl(&mpddr->io_calibr); + tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV | + ATMEL_MPDDRC_IO_CALIBR_TZQIO | + ATMEL_MPDDRC_IO_CALIBR_CALCODEP | + ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) | + ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 | + ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) | + ATMEL_MPDDRC_IO_CALIBR_EN_CALIB; + writel(tmp, &mpddr->io_calibr); + /* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); } -- cgit v0.10.2 From 1c0ac8222a3fe2f4be5fb0a8368cddf4f692193f Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 24 Mar 2017 09:26:16 +0800 Subject: configs: sama5d3xek: add default config for CMP board The sama5d36ek CMP board is the variant of sama5d3xek board. It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and some power rails. The board is mainly used to measure the power consumption. As all those changes are done in at91bootstrap, in U-Boot, only use another device tree file, no code needed to change. As there is additional power consumption when enbling the USB Host and USB device, for the power consumption measurement intention, disable the USB host and device. Signed-off-by: Wenyou Yang diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig new file mode 100644 index 0000000..32a21f9 --- /dev/null +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig new file mode 100644 index 0000000..34c4de1 --- /dev/null +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig new file mode 100644 index 0000000..42c3111 --- /dev/null +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y -- cgit v0.10.2 From 1870d4d7bd229e5e06d660108046656ea24821d4 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 14 Apr 2017 14:36:04 +0800 Subject: net: macb: Add remove callback To avoid the failure of mdio_register(), add the remove callback to unregister the mii_dev when removing the ethernet device. Signed-off-by: Wenyou Yang Acked-by: Joe Hershberger Fixed up unused variable warning, e.g. for gurnard: Signed-off-by: Simon Glass diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 402e866..08d441c 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -111,6 +111,9 @@ struct macb_device { #endif unsigned short phy_addr; struct mii_dev *bus; +#ifdef CONFIG_PHYLIB + struct phy_device *phydev; +#endif #ifdef CONFIG_DM_ETH #ifdef CONFIG_CLK @@ -479,9 +482,6 @@ static int macb_phy_init(struct macb_device *macb, const char *name) #ifdef CONFIG_DM_ETH struct macb_device *macb = dev_get_priv(dev); #endif -#ifdef CONFIG_PHYLIB - struct phy_device *phydev; -#endif u32 ncfgr; u16 phy_id, status, adv, lpa; int media, speed, duplex; @@ -503,19 +503,19 @@ static int macb_phy_init(struct macb_device *macb, const char *name) #ifdef CONFIG_PHYLIB #ifdef CONFIG_DM_ETH - phydev = phy_connect(macb->bus, macb->phy_addr, dev, + macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev, macb->phy_interface); #else /* need to consider other phy interface mode */ - phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev, + macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev, PHY_INTERFACE_MODE_RGMII); #endif - if (!phydev) { + if (!macb->phydev) { printf("phy_connect failed\n"); return -ENODEV; } - phy_config(phydev); + phy_config(macb->phydev); #endif status = macb_mdio_read(macb, MII_BMSR); @@ -1035,6 +1035,7 @@ static int macb_eth_probe(struct udevice *dev) struct eth_pdata *pdata = dev_get_platdata(dev); struct macb_device *macb = dev_get_priv(dev); const char *phy_mode; + __maybe_unused int ret; phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL); @@ -1048,7 +1049,7 @@ static int macb_eth_probe(struct udevice *dev) macb->regs = (void *)pdata->iobase; #ifdef CONFIG_CLK - int ret = macb_enable_clk(dev); + ret = macb_enable_clk(dev); if (ret) return ret; #endif @@ -1056,23 +1057,35 @@ static int macb_eth_probe(struct udevice *dev) _macb_eth_initialize(macb); #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) + macb->bus = mdio_alloc(); + if (!macb->bus) return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = macb_miiphy_read; - mdiodev->write = macb_miiphy_write; + strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN); + macb->bus->read = macb_miiphy_read; + macb->bus->write = macb_miiphy_write; - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; + ret = mdio_register(macb->bus); + if (ret < 0) + return ret; macb->bus = miiphy_get_dev_by_name(dev->name); #endif return 0; } +static int macb_eth_remove(struct udevice *dev) +{ + struct macb_device *macb = dev_get_priv(dev); + +#ifdef CONFIG_PHYLIB + free(macb->phydev); +#endif + mdio_unregister(macb->bus); + mdio_free(macb->bus); + + return 0; +} + static int macb_eth_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); @@ -1092,6 +1105,7 @@ U_BOOT_DRIVER(eth_macb) = { .of_match = macb_eth_ids, .ofdata_to_platdata = macb_eth_ofdata_to_platdata, .probe = macb_eth_probe, + .remove = macb_eth_remove, .ops = &macb_eth_ops, .priv_auto_alloc_size = sizeof(struct macb_device), .platdata_auto_alloc_size = sizeof(struct eth_pdata), -- cgit v0.10.2 From 75460253417213a1b9b21beee20d8f1dc8bbae8f Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 14 Apr 2017 14:36:05 +0800 Subject: net: macb: Align the compatibles with kernel Add the compatibles to align with the kernel. Signed-off-by: Wenyou Yang Acked-by: Joe Hershberger diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 08d441c..21a620c 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -1096,6 +1096,10 @@ static int macb_eth_ofdata_to_platdata(struct udevice *dev) static const struct udevice_id macb_eth_ids[] = { { .compatible = "cdns,macb" }, + { .compatible = "cdns,at91sam9260-macb" }, + { .compatible = "atmel,sama5d2-gem" }, + { .compatible = "atmel,sama5d3-gem" }, + { .compatible = "atmel,sama5d4-gem" }, { } }; -- cgit v0.10.2 From bb1adf294344b54960fb9a5380333a623df79488 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 14 Apr 2017 14:53:22 +0800 Subject: clk: at91: Enhance the peripheral clock Enhance the peripheral clock to support both at9sam9x5's and at91rm9200's peripheral clock via the different compatibles. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index e1ed447..62fabe3 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -16,6 +16,10 @@ #define PERIPHERAL_ID_MAX 31 #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX)) +enum periph_clk_type { + CLK_PERIPH_AT91RM9200 = 0, + CLK_PERIPH_AT91SAM9X5, +}; /** * sam9x5_periph_clk_bind() - for the periph clock driver * Recursively bind its children as clk devices. @@ -28,7 +32,14 @@ static int sam9x5_periph_clk_bind(struct udevice *dev) } static const struct udevice_id sam9x5_periph_clk_match[] = { - { .compatible = "atmel,at91sam9x5-clk-peripheral" }, + { + .compatible = "atmel,at91rm9200-clk-peripheral", + .data = CLK_PERIPH_AT91RM9200, + }, + { + .compatible = "atmel,at91sam9x5-clk-peripheral", + .data = CLK_PERIPH_AT91SAM9X5, + }, {} }; @@ -45,12 +56,24 @@ static int periph_clk_enable(struct clk *clk) { struct pmc_platdata *plat = dev_get_platdata(clk->dev); struct at91_pmc *pmc = plat->reg_base; + enum periph_clk_type clk_type; + void *addr; if (clk->id < PERIPHERAL_ID_MIN) return -1; - writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); - setbits_le32(&pmc->pcr, AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN); + clk_type = dev_get_driver_data(dev_get_parent(clk->dev)); + if (clk_type == CLK_PERIPH_AT91RM9200) { + addr = &pmc->pcer; + if (clk->id > PERIPHERAL_ID_MAX) + addr = &pmc->pcer1; + + setbits_le32(addr, PERIPHERAL_MASK(clk->id)); + } else { + writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); + setbits_le32(&pmc->pcr, + AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN); + } return 0; } -- cgit v0.10.2 From a9513d47dc8dfd765086efb96420feb6daf655c5 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 14 Apr 2017 14:53:23 +0800 Subject: clk: at91: Align clk-master compatibles with kernel Add the compatible "atmel,at91rm9200-clk-master" to align with the kernel. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 284b248..72d0a73 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -21,6 +21,7 @@ static struct clk_ops at91_master_clk_ops = { }; static const struct udevice_id at91_master_clk_match[] = { + { .compatible = "atmel,at91rm9200-clk-master" }, { .compatible = "atmel,at91sam9x5-clk-master" }, {} }; -- cgit v0.10.2 From 3fea809b42cec31b5c179debfc025a2224bb2e70 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 14 Apr 2017 14:53:24 +0800 Subject: clk: at91: Align the at91 pmc's compatibles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align the at91 pmc's compatibles with kernel. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass Reviewed-by: Andreas Bießmann diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index fcd693a..72d52c5 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -16,6 +16,12 @@ DECLARE_GLOBAL_DATA_PTR; static const struct udevice_id at91_pmc_match[] = { + { .compatible = "atmel,at91rm9200-pmc" }, + { .compatible = "atmel,at91sam9260-pmc" }, + { .compatible = "atmel,at91sam9g45-pmc" }, + { .compatible = "atmel,at91sam9n12-pmc" }, + { .compatible = "atmel,at91sam9x5-pmc" }, + { .compatible = "atmel,sama5d3-pmc" }, { .compatible = "atmel,sama5d2-pmc" }, {} }; -- cgit v0.10.2 From 5f29e79915940815a41b1364a213dd2a855cdb6d Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 14 Apr 2017 15:01:27 +0800 Subject: serial: atmel_usart: Fix early debug not work in SPL Add the uart init function to be used on both probe and the early debug uart init. For the latter, the input clock should be from CONFIG_DEBUG_UART_CLOCK. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 7674f97..8b1e0d5 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -25,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_DM_SERIAL static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id, int baudrate) { @@ -66,7 +67,6 @@ static void atmel_serial_activate(atmel_usart3_t *usart) __udelay(100); } -#ifndef CONFIG_DM_SERIAL static void atmel_serial_setbrg(void) { atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE, @@ -138,12 +138,37 @@ struct atmel_serial_priv { atmel_usart3_t *usart; }; +static void _atmel_serial_set_brg(atmel_usart3_t *usart, + ulong usart_clk_rate, int baudrate) +{ + unsigned long divisor; + + divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate; + writel(USART3_BF(CD, divisor), &usart->brgr); +} + +void _atmel_serial_init(atmel_usart3_t *usart, + ulong usart_clk_rate, int baudrate) +{ + writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr); + + writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) | + USART3_BF(USCLKS, USART3_USCLKS_MCK) | + USART3_BF(CHRL, USART3_CHRL_8) | + USART3_BF(PAR, USART3_PAR_NONE) | + USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr); + + _atmel_serial_set_brg(usart, usart_clk_rate, baudrate); + + writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr); + writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr); +} + int atmel_serial_setbrg(struct udevice *dev, int baudrate) { struct atmel_serial_priv *priv = dev_get_priv(dev); - atmel_serial_setbrg_internal(priv->usart, 0 /* ignored */, baudrate); - atmel_serial_activate(priv->usart); + _atmel_serial_set_brg(priv->usart, get_usart_clk_rate(0), baudrate); return 0; } @@ -202,7 +227,8 @@ static int atmel_serial_probe(struct udevice *dev) plat->base_addr = (uint32_t)addr_base; #endif priv->usart = (atmel_usart3_t *)plat->base_addr; - atmel_serial_init_internal(priv->usart); + + _atmel_serial_init(priv->usart, get_usart_clk_rate(0), gd->baudrate); return 0; } @@ -233,7 +259,7 @@ static inline void _debug_uart_init(void) { atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE; - atmel_serial_setbrg_internal(usart, 0, CONFIG_BAUDRATE); + _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); } static inline void _debug_uart_putc(int ch) -- cgit v0.10.2 From f8b7fff1d5c5297d290acab1e398bd410b0c2e68 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 14 Apr 2017 15:01:28 +0800 Subject: serial: atmel_usart: Add clk support Add the clock support. Note that the clock handling of the DBGU peripheral is different from the USART. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 8b1e0d5..453f8eb 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -7,6 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include @@ -133,9 +134,14 @@ __weak struct serial_device *default_serial_console(void) #endif #ifdef CONFIG_DM_SERIAL +enum serial_clk_type { + CLK_TYPE_NORMAL = 0, + CLK_TYPE_DBGU, +}; struct atmel_serial_priv { atmel_usart3_t *usart; + ulong usart_clk_rate; }; static void _atmel_serial_set_brg(atmel_usart3_t *usart, @@ -168,7 +174,7 @@ int atmel_serial_setbrg(struct udevice *dev, int baudrate) { struct atmel_serial_priv *priv = dev_get_priv(dev); - _atmel_serial_set_brg(priv->usart, get_usart_clk_rate(0), baudrate); + _atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate); return 0; } @@ -213,10 +219,39 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, }; +static int atmel_serial_enable_clk(struct udevice *dev) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + struct clk clk; + ulong clk_rate; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return -EINVAL; + + if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) { + ret = clk_enable(&clk); + if (ret) + return ret; + } + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) + return -EINVAL; + + priv->usart_clk_rate = clk_rate; + + clk_free(&clk); + + return 0; +} + static int atmel_serial_probe(struct udevice *dev) { struct atmel_serial_platdata *plat = dev->platdata; struct atmel_serial_priv *priv = dev_get_priv(dev); + int ret; #if CONFIG_IS_ENABLED(OF_CONTROL) fdt_addr_t addr_base; @@ -228,14 +263,25 @@ static int atmel_serial_probe(struct udevice *dev) #endif priv->usart = (atmel_usart3_t *)plat->base_addr; - _atmel_serial_init(priv->usart, get_usart_clk_rate(0), gd->baudrate); + ret = atmel_serial_enable_clk(dev); + if (ret) + return ret; + + _atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate); return 0; } #if CONFIG_IS_ENABLED(OF_CONTROL) static const struct udevice_id atmel_serial_ids[] = { - { .compatible = "atmel,at91sam9260-usart" }, + { + .compatible = "atmel,at91sam9260-dbgu", + .data = CLK_TYPE_DBGU, + }, + { + .compatible = "atmel,at91sam9260-usart", + .data = CLK_TYPE_NORMAL, + }, { } }; #endif -- cgit v0.10.2 From 25e88d406ed065750035a666af553e48b756b16c Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 13:49:34 +0800 Subject: ARM: dts: at91: Add dts files for at91sam9x5ek The device tree source files of at91sam9x5ek board are copied from the Linux v4.10, do the changes below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Add the "u-boot,dm-pre-reloc" property to determine which nodes are used by the board_init_f stage. - Change the compatible of the spi flash to "spi-flash". - Add the spi0 aliases. - Fix the compilation warnings. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4d656ce..092d2aa 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -352,6 +352,13 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2e-evm.dtb \ keystone-k2g-evm.dtb +dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ + at91sam9g15ek.dtb \ + at91sam9g25ek.dtb \ + at91sam9g35ek.dtb \ + at91sam9x25ek.dtb \ + at91sam9x35ek.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ at91-sama5d2_xplained.dtb diff --git a/arch/arm/dts/at91sam9g15.dtsi b/arch/arm/dts/at91sam9g15.dtsi new file mode 100644 index 0000000..27de7dc --- /dev/null +++ b/arch/arm/dts/at91sam9g15.dtsi @@ -0,0 +1,29 @@ +/* + * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2. + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" + +/ { + model = "Atmel AT91SAM9G15 SoC"; + compatible = "atmel,at91sam9g15", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe0399f 0x00000000 /* pioA */ + 0x00040000 0x00047e3f 0x00000000 /* pioB */ + 0xfdffffff 0x00000000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g15ek.dts b/arch/arm/dts/at91sam9g15ek.dts new file mode 100644 index 0000000..9fae925 --- /dev/null +++ b/arch/arm/dts/at91sam9g15ek.dts @@ -0,0 +1,26 @@ +/* + * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9g15.dtsi" +#include "at91sam9x5dm.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9G15-EK"; + compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + hlcdc: hlcdc@f8038000 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g25.dtsi b/arch/arm/dts/at91sam9g25.dtsi new file mode 100644 index 0000000..a7da0dd --- /dev/null +++ b/arch/arm/dts/at91sam9g25.dtsi @@ -0,0 +1,31 @@ +/* + * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2. + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_isi.dtsi" +#include "at91sam9x5_usart3.dtsi" +#include "at91sam9x5_macb0.dtsi" + +/ { + model = "Atmel AT91SAM9G25 SoC"; + compatible = "atmel,at91sam9g25", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe0399f 0xc000001c /* pioA */ + 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */ + 0x80000000 0x07c0ffff 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g25ek.dts b/arch/arm/dts/at91sam9g25ek.dts new file mode 100644 index 0000000..91a7177 --- /dev/null +++ b/arch/arm/dts/at91sam9g25ek.dts @@ -0,0 +1,69 @@ +/* + * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9g25.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9G25-EK"; + compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + spi0: spi@f0000000 { + status = "disabled"; + }; + + mmc1: mmc@f000c000 { + status = "disabled"; + }; + + i2c0: i2c@f8010000 { + ov2640: camera@0x30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; + clocks = <&pck0>; + clock-names = "xvclk"; + assigned-clocks = <&pck0>; + assigned-clock-rates = <25000000>; + status = "okay"; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; + + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + isi: isi@f8048000 { + status = "okay"; + port { + isi_0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g35.dtsi b/arch/arm/dts/at91sam9g35.dtsi new file mode 100644 index 0000000..ff41158 --- /dev/null +++ b/arch/arm/dts/at91sam9g35.dtsi @@ -0,0 +1,30 @@ +/* + * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2. + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" +#include "at91sam9x5_macb0.dtsi" + +/ { + model = "Atmel AT91SAM9G35 SoC"; + compatible = "atmel,at91sam9g35", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe0399f 0xc000000c /* pioA */ + 0x000406ff 0x00047e3f 0x00000000 /* pioB */ + 0xfdffffff 0x00000000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g35ek.dts b/arch/arm/dts/at91sam9g35ek.dts new file mode 100644 index 0000000..0cc084e --- /dev/null +++ b/arch/arm/dts/at91sam9g35ek.dts @@ -0,0 +1,31 @@ +/* + * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9g35.dtsi" +#include "at91sam9x5dm.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9G35-EK"; + compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + hlcdc: hlcdc@f8038000 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x25.dtsi b/arch/arm/dts/at91sam9x25.dtsi new file mode 100644 index 0000000..3c5fa33 --- /dev/null +++ b/arch/arm/dts/at91sam9x25.dtsi @@ -0,0 +1,32 @@ +/* + * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2. + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_usart3.dtsi" +#include "at91sam9x5_macb0.dtsi" +#include "at91sam9x5_macb1.dtsi" +#include "at91sam9x5_can.dtsi" + +/ { + model = "Atmel AT91SAM9X25 SoC"; + compatible = "atmel,at91sam9x25", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe03fff 0xc000001c /* pioA */ + 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ + 0x80000000 0xfffd0000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x25ek.dts b/arch/arm/dts/at91sam9x25ek.dts new file mode 100644 index 0000000..4948648 --- /dev/null +++ b/arch/arm/dts/at91sam9x25ek.dts @@ -0,0 +1,30 @@ +/* + * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9x25.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9X25-EK"; + compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + macb1: ethernet@f8030000 { + phy-mode = "rmii"; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x35.dtsi b/arch/arm/dts/at91sam9x35.dtsi new file mode 100644 index 0000000..d9054e8 --- /dev/null +++ b/arch/arm/dts/at91sam9x35.dtsi @@ -0,0 +1,31 @@ +/* + * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2. + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" +#include "at91sam9x5_macb0.dtsi" +#include "at91sam9x5_can.dtsi" + +/ { + model = "Atmel AT91SAM9X35 SoC"; + compatible = "atmel,at91sam9x35", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe03fff 0xc000000c /* pioA */ + 0x000406ff 0x00047e3f 0x00000000 /* pioB */ + 0xfdffffff 0x00000000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x35ek.dts b/arch/arm/dts/at91sam9x35ek.dts new file mode 100644 index 0000000..3ca70c0 --- /dev/null +++ b/arch/arm/dts/at91sam9x35ek.dts @@ -0,0 +1,30 @@ +/* + * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9x35.dtsi" +#include "at91sam9x5dm.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9X35-EK"; + compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + hlcdc: hlcdc@f8038000 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi new file mode 100644 index 0000000..a422c98 --- /dev/null +++ b/arch/arm/dts/at91sam9x5.dtsi @@ -0,0 +1,1302 @@ +/* + * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC + * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, + * AT91SAM9X25, AT91SAM9X35 SoC + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +#include "skeleton.dtsi" +#include +#include +#include +#include +#include + +/ { + model = "Atmel AT91SAM9x5 family SoC"; + compatible = "atmel,at91sam9x5"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + ssc0 = &ssc0; + pwm0 = &pwm0; + spi0 = &spi0; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + sram: sram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x8000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; + }; + + ramc0: ramc@ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + clocks = <&ddrck>; + clock-names = "ddrck"; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9x5-pmc", "syscon"; + reg = <0xfffffc00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + u-boot,dm-pre-reloc; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; + clock-frequency = <12000000>; + clock-accuracy = <50000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; + clocks = <&main_rc_osc>, <&main_osc>; + }; + + plla: pllack@0 { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <2000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <745000000 800000000 0 0 + 695000000 750000000 1 0 + 645000000 700000000 2 0 + 595000000 650000000 3 0 + 545000000 600000000 0 1 + 495000000 555000000 1 1 + 445000000 500000000 2 1 + 400000000 450000000 3 1>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKU>; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <0 133333333>; + atmel,clk-divisors = <1 2 4 3>; + atmel,master-clk-have-div3-pres; + u-boot,dm-pre-reloc; + + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog@0 { + #clock-cells = <0>; + reg = <0>; + interrupts = ; + }; + + prog1: prog@1 { + #clock-cells = <0>; + reg = <1>; + interrupts = ; + }; + }; + + smd: smdclk { + compatible = "atmel,at91sam9x5-clk-smd"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck@2 { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + smdck: smdck@4 { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + uhpck: uhpck@6 { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck@7 { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0@8 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1@9 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + }; + + periphck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + u-boot,dm-pre-reloc; + + + pioAB_clk: pioAB_clk@2 { + #clock-cells = <0>; + reg = <2>; + }; + + pioCD_clk: pioCD_clk@3 { + #clock-cells = <0>; + reg = <3>; + }; + + smd_clk: smd_clk@4 { + #clock-cells = <0>; + reg = <4>; + }; + + usart0_clk: usart0_clk@5 { + #clock-cells = <0>; + reg = <5>; + }; + + usart1_clk: usart1_clk@6 { + #clock-cells = <0>; + reg = <6>; + }; + + usart2_clk: usart2_clk@7 { + #clock-cells = <0>; + reg = <7>; + }; + + twi0_clk: twi0_clk@9 { + reg = <9>; + #clock-cells = <0>; + }; + + twi1_clk: twi1_clk@10 { + #clock-cells = <0>; + reg = <10>; + }; + + twi2_clk: twi2_clk@11 { + #clock-cells = <0>; + reg = <11>; + }; + + mci0_clk: mci0_clk@12 { + #clock-cells = <0>; + reg = <12>; + }; + + spi0_clk: spi0_clk@13 { + #clock-cells = <0>; + reg = <13>; + }; + + spi1_clk: spi1_clk@14 { + #clock-cells = <0>; + reg = <14>; + }; + + uart0_clk: uart0_clk@15 { + #clock-cells = <0>; + reg = <15>; + }; + + uart1_clk: uart1_clk@16 { + #clock-cells = <0>; + reg = <16>; + }; + + tcb0_clk: tcb0_clk@17 { + #clock-cells = <0>; + reg = <17>; + }; + + pwm_clk: pwm_clk@18 { + #clock-cells = <0>; + reg = <18>; + }; + + adc_clk: adc_clk@19 { + #clock-cells = <0>; + reg = <19>; + }; + + dma0_clk: dma0_clk@20 { + #clock-cells = <0>; + reg = <20>; + }; + + dma1_clk: dma1_clk@21 { + #clock-cells = <0>; + reg = <21>; + }; + + uhphs_clk: uhphs_clk@22 { + #clock-cells = <0>; + reg = <22>; + }; + + udphs_clk: udphs_clk@23 { + #clock-cells = <0>; + reg = <23>; + }; + + mci1_clk: mci1_clk@26 { + #clock-cells = <0>; + reg = <26>; + }; + + ssc0_clk: ssc0_clk@28 { + #clock-cells = <0>; + reg = <28>; + }; + }; + }; + + rstc@fffffe00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; + }; + + shdwc@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; + }; + + sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc>, <&slow_osc>; + }; + }; + + tcb0: timer@f8008000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8008000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + tcb1: timer@f800c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf800c000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + dma0: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + + dma1: dma-controller@ffffee00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffee00 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + reg = <0xfffff400 0x200 /* pioA */ + 0xfffff600 0x200 /* pioB */ + 0xfffff800 0x200 /* pioC */ + 0xfffffa00 0x200 /* pioD */ + >; + u-boot,dm-pre-reloc; + + + /* shared pinctrl settings */ + dbgu { + u-boot,dm-pre-reloc; + pinctrl_dbgu: dbgu-0 { + atmel,pins = + ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; /* PA1 periph A */ + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; /* PA2 periph A */ + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; /* PA3 periph A */ + }; + + pinctrl_usart0_sck: usart0_sck-0 { + atmel,pins = + ; /* PA4 periph A */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; /* PA6 periph A */ + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + ; /* PC27 periph C */ + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + ; /* PC28 periph C */ + }; + + pinctrl_usart1_sck: usart1_sck-0 { + atmel,pins = + ; /* PC29 periph C */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; /* PA8 periph A */ + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; /* PB0 periph B */ + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; /* PB1 periph B */ + }; + + pinctrl_usart2_sck: usart2_sck-0 { + atmel,pins = + ; /* PB2 periph B */ + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; /* PC9 periph C with pullup */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; /* PC17 periph C with pullup */ + }; + }; + + nand { + pinctrl_nand: nand-0 { + atmel,pins = + ; /* PD13 periph A Data bit 7 */ + }; + + pinctrl_nand_16bits: nand_16bits-0 { + atmel,pins = + ; /* PD21 periph A Data bit 15 */ + }; + }; + + mmc0 { + pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { + atmel,pins = + ; /* PA15 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + ; /* PA20 periph A with pullup */ + }; + }; + + mmc1 { + pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { + atmel,pins = + ; /* PA11 periph B with pullup */ + }; + + pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { + atmel,pins = + ; /* PA4 periph B with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + ; /* PA26 periph B */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + ; /* PA29 periph B */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; /* PA13 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; /* PA23 periph B SPI1_SPCK pin */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; /* PA31 periph A I2C0 clock */ + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; /* PC1 periph C I2C1 clock */ + }; + }; + + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + ; /* PB5 periph B I2C2 clock */ + }; + }; + + i2c_gpio0 { + pinctrl_i2c_gpio0: i2c_gpio0-0 { + atmel,pins = + ; /* PA31 gpio multidrive I2C0 clock */ + }; + }; + + i2c_gpio1 { + pinctrl_i2c_gpio1: i2c_gpio1-0 { + atmel,pins = + ; /* PC1 gpio multidrive I2C1 clock */ + }; + }; + + i2c_gpio2 { + pinctrl_i2c_gpio2: i2c_gpio2-0 { + atmel,pins = + ; /* PB5 gpio multidrive I2C2 clock */ + }; + }; + + pwm0 { + pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { + atmel,pins = + ; + }; + + pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { + atmel,pins = + ; + }; + + pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { + atmel,pins = + ; + }; + + pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { + atmel,pins = + ; + }; + pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { + atmel,pins = + ; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = ; + }; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <19>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + }; + + ssc0: ssc@f0010000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + mmc0: mmc@f0008000 { + compatible = "atmel,hsmci"; + reg = <0xf0008000 0x600>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc1: mmc@f000c000 { + compatible = "atmel,hsmci"; + reg = <0xf000c000 0x600>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&mck>; + clock-names = "usart"; + status = "disabled"; + }; + + usart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + i2c0: i2c@f8010000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8010000 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + i2c1: i2c@f8014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8014000 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, + <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + + i2c2: i2c@f8018000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8018000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&twi2_clk>; + status = "disabled"; + }; + + uart0: serial@f8040000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8040000 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart1: serial@f8044000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8044000 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + adc0: adc@f804c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9x5-adc"; + reg = <0xf804c000 0x100>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&adc_clk>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-use-external-triggers; + atmel,adc-channels-used = <0xffff>; + atmel,adc-vref = <3300>; + atmel,adc-startup-time = <40>; + atmel,adc-sample-hold-time = <11>; + atmel,adc-res = <8 10>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-use-res = "highres"; + + trigger0 { + trigger-name = "external-rising"; + trigger-value = <0x1>; + trigger-external; + }; + + trigger1 { + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; + }; + + trigger2 { + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; + }; + + trigger3 { + trigger-name = "continuous"; + trigger-value = <0x6>; + }; + }; + + spi0: spi@f0000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0000000 0x100>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@f0004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0004000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + usb2: gadget@f803c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9g45-udc"; + reg = <0x00500000 0x80000 + 0xf803c000 0x400>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&utmi>, <&udphs_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + + ep@0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep@1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep@2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep@3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep@4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep@5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep@6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + }; + + watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + rtc@fffffeb0 { + compatible = "atmel,at91sam9x5-rtc"; + reg = <0xfffffeb0 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + clocks = <&pwm_clk>; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + 0xffffe000 0x600 /* PMECC Registers */ + 0xffffe600 0x200 /* PMECC Error Location Registers */ + 0x00108000 0x18000 /* PMECC looup table in ROM code */ + >; + atmel,pmecc-lookup-table-offset = <0x0 0x8000>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + gpios = <&pioD 5 GPIO_ACTIVE_HIGH + &pioD 4 GPIO_ACTIVE_HIGH + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb1: ehci@00700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ + &pioA 31 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>; + status = "disabled"; + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ + &pioC 1 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio1>; + status = "disabled"; + }; + + i2c-gpio-2 { + compatible = "i2c-gpio"; + gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ + &pioB 5 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_can.dtsi b/arch/arm/dts/at91sam9x5_can.dtsi new file mode 100644 index 0000000..9727b77 --- /dev/null +++ b/arch/arm/dts/at91sam9x5_can.dtsi @@ -0,0 +1,71 @@ +/* + * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * Ethernet interface. + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include + +/ { + ahb { + apb { + pmc: pmc@fffffc00 { + periphck { + can0_clk: can0_clk@29 { + #clock-cells = <0>; + reg = <29>; + }; + + can1_clk: can1_clk@30 { + #clock-cells = <0>; + reg = <30>; + }; + }; + }; + + can0: can@f8000000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8000000 0x300>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&can0_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8004000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8004000 0x300>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&can1_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + pinctrl@fffff400 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + ; /* CANTX0, conflicts with DTXD */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + ; /* CANTX1, conflicts with TXD1 */ + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_isi.dtsi b/arch/arm/dts/at91sam9x5_isi.dtsi new file mode 100644 index 0000000..2c5075f --- /dev/null +++ b/arch/arm/dts/at91sam9x5_isi.dtsi @@ -0,0 +1,72 @@ +/* + * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an + * Image Sensor Interface. + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff400 { + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + ; /* ISI_VSYNC, conflicts with LCDDAT13 */ + }; + + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + ; /* ISI_D9, conflicts with LCDDAT9 */ + }; + + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + ; /* ISI_D11, conflicts with LCDDAT11 */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + isi_clk: isi_clk@25 { + #clock-cells = <0>; + reg = <25>; + }; + }; + }; + + isi: isi@f8048000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf8048000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_lcd.dtsi b/arch/arm/dts/at91sam9x5_lcd.dtsi new file mode 100644 index 0000000..96b7095 --- /dev/null +++ b/arch/arm/dts/at91sam9x5_lcd.dtsi @@ -0,0 +1,146 @@ +/* + * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an + * LCD controller. + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include + +/ { + ahb { + apb { + hlcdc: hlcdc@f8038000 { + compatible = "atmel,at91sam9x5-hlcdc"; + reg = <0xf8038000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + }; + + pinctrl@fffff400 { + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + lcdc_clk: lcdc_clk@25 { + #clock-cells = <0>; + reg = <25>; + }; + }; + + systemck { + lcdck: lcdck@3 { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_macb0.dtsi b/arch/arm/dts/at91sam9x5_macb0.dtsi new file mode 100644 index 0000000..1540e60 --- /dev/null +++ b/arch/arm/dts/at91sam9x5_macb0.dtsi @@ -0,0 +1,67 @@ +/* + * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * Ethernet interface. + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff400 { + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + ; /* PB10 periph A */ + }; + + pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { + atmel,pins = + ; /* PB17 periph A */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + macb0_clk: macb0_clk@24 { + #clock-cells = <0>; + reg = <24>; + }; + }; + }; + + macb0: ethernet@f802c000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_macb1.dtsi b/arch/arm/dts/at91sam9x5_macb1.dtsi new file mode 100644 index 0000000..be2eab4 --- /dev/null +++ b/arch/arm/dts/at91sam9x5_macb1.dtsi @@ -0,0 +1,55 @@ +/* + * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2 + * Ethernet interfaces. + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include + +/ { + ahb { + apb { + pinctrl@fffff400 { + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + ; /* PC31 periph B */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + macb1_clk: macb1_clk@27 { + #clock-cells = <0>; + reg = <27>; + }; + }; + }; + + macb1: ethernet@f8030000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xf8030000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + clocks = <&macb1_clk>, <&macb1_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_usart3.dtsi b/arch/arm/dts/at91sam9x5_usart3.dtsi new file mode 100644 index 0000000..5259219 --- /dev/null +++ b/arch/arm/dts/at91sam9x5_usart3.dtsi @@ -0,0 +1,69 @@ +/* + * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * 4 USART. + * + * Copyright (C) 2013 Boris BREZILLON + * + * Licensed under GPLv2. + */ + +#include +#include + +/ { + aliases { + serial4 = &usart3; + }; + + ahb { + apb { + pinctrl@fffff400 { + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + ; /* PC23 periph B */ + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + ; /* PC24 periph B */ + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + ; /* PC25 periph B */ + }; + + pinctrl_usart3_sck: usart3_sck-0 { + atmel,pins = + ; /* PC26 periph B */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + usart3_clk: usart3_clk@8 { + #clock-cells = <0>; + reg = <8>; + }; + }; + }; + + usart3: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5cm.dtsi b/arch/arm/dts/at91sam9x5cm.dtsi new file mode 100644 index 0000000..b098ad8 --- /dev/null +++ b/arch/arm/dts/at91sam9x5cm.dtsi @@ -0,0 +1,100 @@ +/* + * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +/ { + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + pinctrl@fffff400 { + 1wire_cm { + pinctrl_1wire_cm: 1wire_cm-0 { + atmel,pins = ; /* PB18 multidrive, conflicts with led */ + }; + }; + }; + + rtc@fffffeb0 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; /* Enable PMECC */ + atmel,pmecc-cap = <2>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "U-Boot Env"; + reg = <0xc0000 0x140000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pb18 { + label = "pb18"; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + pd21 { + label = "pd21"; + gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; + }; + }; + + 1wire_cm { + compatible = "w1-gpio"; + gpios = <&pioB 18 GPIO_ACTIVE_HIGH>; + linux,open-drain; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_1wire_cm>; + status = "okay"; + }; + +}; diff --git a/arch/arm/dts/at91sam9x5dm.dtsi b/arch/arm/dts/at91sam9x5dm.dtsi new file mode 100644 index 0000000..a620366 --- /dev/null +++ b/arch/arm/dts/at91sam9x5dm.dtsi @@ -0,0 +1,66 @@ +/* + * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module + * + * Copyright (C) 2014 Atmel, + * 2014 Free Electrons + * + * Author: Boris Brezillon + * + * Licensed under GPLv2 or later. + */ + +/ { + ahb { + apb { + i2c0: i2c@f8010000 { + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioA>; + interrupts = <7 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; + }; + + hlcdc: hlcdc@f8038000 { + atmel,vl-bpix = <4>; + atmel,guard-time = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb888>; + + display-timings { + u-boot,dm-pre-reloc; + 800x480 { + clock-frequency = <24000000>; + hactive = <800>; + vactive = <480>; + hsync-len = <128>; + hfront-porch = <64>; + hback-porch = <64>; + vfront-porch = <22>; + vback-porch = <21>; + vsync-len = <2>; + u-boot,dm-pre-reloc; + }; + }; + }; + + adc0: adc@f804c000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff400 { + board { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + ; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5ek.dtsi b/arch/arm/dts/at91sam9x5ek.dtsi new file mode 100644 index 0000000..f2a532d --- /dev/null +++ b/arch/arm/dts/at91sam9x5ek.dtsi @@ -0,0 +1,167 @@ +/* + * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +#include "at91sam9x5cm.dtsi" + +/ { + model = "Atmel AT91SAM9X5-EK"; + compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; + stdout-path = "serial0:115200n8"; + u-boot,dm-pre-reloc; + }; + + ahb { + apb { + mmc0: mmc@f0008000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; + }; + }; + + mmc1: mmc@f000c000 { + pinctrl-0 = < + &pinctrl_board_mmc1 + &pinctrl_mmc1_slot0_clk_cmd_dat0 + &pinctrl_mmc1_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; + }; + }; + + dbgu: serial@fffff200 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + usart0: serial@f801c000 { + status = "okay"; + }; + + usb2: gadget@f803c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_board_usb2>; + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + i2c0: i2c@f8010000 { + status = "okay"; + + wm8731: wm8731@1a { + compatible = "wm8731"; + reg = <0x1a>; + }; + }; + + adc0: adc@f804c000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff400 { + camera_sensor { + pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 { + atmel,pins = + ; /* ISI_MCK */ + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + ; + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + ; + }; + }; + + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PD15 gpio CD pin pull up and deglitch */ + }; + }; + + mmc1 { + pinctrl_board_mmc1: mmc1-board { + atmel,pins = + ; /* PD14 gpio CD pin pull up and deglitch */ + }; + }; + + usb2 { + pinctrl_board_usb2: usb2-board { + atmel,pins = + ; /* PB16 gpio vbus sense, deglitch */ + }; + }; + }; + + spi0: spi@f0000000 { + status = "okay"; + cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; + spi_flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + + ssc0: ssc@f0010000 { + status = "okay"; + }; + }; + + usb0: ohci@00600000 { + status = "okay"; + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */ + &pioD 19 GPIO_ACTIVE_LOW + &pioD 20 GPIO_ACTIVE_LOW + >; + }; + + usb1: ehci@00700000 { + status = "okay"; + }; + }; + + sound { + compatible = "atmel,sam9x5-wm8731-audio"; + + atmel,model = "wm8731 @ AT91SAM9X5EK"; + + atmel,audio-routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "LLINEIN", "Line In Jack", + "RLINEIN", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8731>; + }; +}; -- cgit v0.10.2 From cd339347b9660c997fb4d9cd929dd10067e92183 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 13:49:35 +0800 Subject: ARM: dts: at91: Add dts files for at91sam9n12ek The device tree source files of at91sam9n12ek boards are copied from the Linux v4.10, do the changes as below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Change the compatible of the spi flash to "spi-flash". - Add the spi0 aliases. - Fix the pinctrl-names of mmc0 node. - Add the "u-boot,dm-pre-reloc" property to determine which nodes are used by the board_init_f stage. - Fix the compilation warnings. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 092d2aa..2417f1f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -359,6 +359,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ at91sam9x25ek.dtb \ at91sam9x35ek.dtb +dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ at91-sama5d2_xplained.dtb diff --git a/arch/arm/dts/at91sam9n12.dtsi b/arch/arm/dts/at91sam9n12.dtsi new file mode 100644 index 0000000..7ba7116 --- /dev/null +++ b/arch/arm/dts/at91sam9n12.dtsi @@ -0,0 +1,1064 @@ +/* + * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC + * + * Copyright (C) 2012 Atmel, + * 2012 Hong Xu + * + * Licensed under GPLv2 or later. + */ + +#include "skeleton.dtsi" +#include +#include +#include +#include +#include + +/ { + model = "Atmel AT91SAM9N12 SoC"; + compatible = "atmel,at91sam9n12"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + ssc0 = &ssc0; + pwm0 = &pwm0; + spi0 = &spi0; + }; + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + + sram: sram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x8000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; + }; + + ramc0: ramc@ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + clocks = <&ddrck>; + clock-names = "ddrck"; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9n12-pmc", "syscon"; + reg = <0xfffffc00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + u-boot,dm-pre-reloc; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; + clock-frequency = <12000000>; + clock-accuracy = <50000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; + clocks = <&main_rc_osc>, <&main_osc>; + }; + + plla: pllack@0 { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <2000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, + <695000000 750000000 1 0>, + <645000000 700000000 2 0>, + <595000000 650000000 3 0>, + <545000000 600000000 0 1>, + <495000000 555000000 1 1>, + <445000000 500000000 2 1>, + <400000000 450000000 3 1>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + pllb: pllbck@1 { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKB>; + clocks = <&main>; + reg = <1>; + atmel,clk-input-range = <2000000 32000000>; + #atmel,pll-clk-output-range-cells = <3>; + atmel,pll-clk-output-ranges = <30000000 100000000 0>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; + atmel,clk-output-range = <0 133333333>; + atmel,clk-divisors = <1 2 4 3>; + atmel,master-clk-have-div3-pres; + u-boot,dm-pre-reloc; + }; + + usb: usbck { + compatible = "atmel,at91sam9n12-clk-usb"; + #clock-cells = <0>; + clocks = <&pllb>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; + + prog0: prog@0 { + #clock-cells = <0>; + reg = <0>; + interrupts = ; + }; + + prog1: prog@1 { + #clock-cells = <0>; + reg = <1>; + interrupts = ; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck@2 { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + lcdck: lcdck@3 { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + + uhpck: uhpck@6 { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck@7 { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0@8 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1@9 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + }; + + periphck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + u-boot,dm-pre-reloc; + + pioAB_clk: pioAB_clk@2 { + #clock-cells = <0>; + reg = <2>; + u-boot,dm-pre-reloc; + }; + + pioCD_clk: pioCD_clk@3 { + #clock-cells = <0>; + reg = <3>; + u-boot,dm-pre-reloc; + }; + + fuse_clk: fuse_clk@4 { + #clock-cells = <0>; + reg = <4>; + }; + + usart0_clk: usart0_clk@5 { + #clock-cells = <0>; + reg = <5>; + }; + + usart1_clk: usart1_clk@6 { + #clock-cells = <0>; + reg = <6>; + }; + + usart2_clk: usart2_clk@7 { + #clock-cells = <0>; + reg = <7>; + }; + + usart3_clk: usart3_clk@8 { + #clock-cells = <0>; + reg = <8>; + }; + + twi0_clk: twi0_clk@9 { + reg = <9>; + #clock-cells = <0>; + }; + + twi1_clk: twi1_clk@10 { + #clock-cells = <0>; + reg = <10>; + }; + + mci0_clk: mci0_clk@12 { + #clock-cells = <0>; + reg = <12>; + }; + + spi0_clk: spi0_clk@13 { + #clock-cells = <0>; + reg = <13>; + }; + + spi1_clk: spi1_clk@14 { + #clock-cells = <0>; + reg = <14>; + }; + + uart0_clk: uart0_clk@15 { + #clock-cells = <0>; + reg = <15>; + }; + + uart1_clk: uart1_clk@16 { + #clock-cells = <0>; + reg = <16>; + }; + + tcb_clk: tcb_clk@17 { + #clock-cells = <0>; + reg = <17>; + }; + + pwm_clk: pwm_clk@18 { + #clock-cells = <0>; + reg = <18>; + }; + + adc_clk: adc_clk@19 { + #clock-cells = <0>; + reg = <19>; + }; + + dma0_clk: dma0_clk@20 { + #clock-cells = <0>; + reg = <20>; + }; + + uhphs_clk: uhphs_clk@22 { + #clock-cells = <0>; + reg = <22>; + }; + + udphs_clk: udphs_clk@23 { + #clock-cells = <0>; + reg = <23>; + }; + + lcdc_clk: lcdc_clk@25 { + #clock-cells = <0>; + reg = <25>; + }; + + sha_clk: sha_clk@27 { + #clock-cells = <0>; + reg = <27>; + }; + + ssc0_clk: ssc0_clk@28 { + #clock-cells = <0>; + reg = <28>; + }; + + aes_clk: aes_clk@29 { + #clock-cells = <0>; + reg = <29>; + }; + + trng_clk: trng_clk@30 { + #clock-cells = <0>; + reg = <30>; + }; + }; + }; + + rstc@fffffe00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; + }; + + shdwc@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; + }; + + sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc>, <&slow_osc>; + }; + }; + + mmc0: mmc@f0008000 { + compatible = "atmel,hsmci"; + reg = <0xf0008000 0x600>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tcb0: timer@f8008000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8008000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + tcb1: timer@f800c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf800c000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + hlcdc: hlcdc@f8038000 { + compatible = "atmel,at91sam9n12-hlcdc"; + reg = <0xf8038000 0x2000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk", "sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + dma: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + reg = <0xfffff400 0x200 + 0xfffff600 0x200 + 0xfffff800 0x200 + 0xfffffa00 0x200 + >; + + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe07983 0x00000000 /* pioA */ + 0x00040000 0x00047e0f 0x00000000 /* pioB */ + 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + u-boot,dm-pre-reloc; + + /* shared pinctrl settings */ + dbgu { + u-boot,dm-pre-reloc; + pinctrl_dbgu: dbgu-0 { + atmel,pins = + ; + }; + }; + + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + ; /* PA0 periph A */ + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; /* PA2 periph A */ + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; /* PA3 periph A */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + ; /* PA5 periph A */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + ; /* PA7 periph A */ + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; /* PB0 periph B */ + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; /* PB1 periph B */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + ; /* PC22 periph B */ + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + ; /* PC24 periph B */ + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + ; /* PC25 periph B */ + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + ; /* PC8 periph C */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + ; /* PC16 periph C */ + }; + }; + + nand { + pinctrl_nand: nand-0 { + atmel,pins = + ; /* PD4 gpio enable pin pull_up */ + }; + }; + + mmc0 { + pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { + atmel,pins = + ; /* PA15 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + ; /* PA20 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { + atmel,pins = + ; /* PA14 periph B with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + ; /* PA26 periph B */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + ; /* PA29 periph B */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + ; /* PA13 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + ; /* PA23 periph B SPI1_SPCK pin */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = ; + }; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + u-boot,dm-pre-reloc; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + u-boot,dm-pre-reloc; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + u-boot,dm-pre-reloc; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + u-boot,dm-pre-reloc; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@f0010000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, + <&dma 0 AT91_DMA_CFG_PER_ID(22)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + usart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x4000>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x4000>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x4000>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x4000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + i2c0: i2c@f8010000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8010000 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, + <&dma 1 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + i2c1: i2c@f8014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8014000 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, + <&dma 1 AT91_DMA_CFG_PER_ID(16)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + + spi0: spi@f0000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0000000 0x100>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@f0004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0004000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, + <&dma 1 AT91_DMA_CFG_PER_ID(4)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + rtc@fffffeb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffeb0 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + status = "disabled"; + }; + + usb1: gadget@f803c000 { + compatible = "atmel,at91sam9260-udc"; + reg = <0xf803c000 0x4000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&udpck>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = < 0x40000000 0x10000000 + 0xffffe000 0x00000600 + 0xffffe600 0x00000200 + 0x00108000 0x00018000 + >; + atmel,pmecc-lookup-table-offset = <0x0 0x8000>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + gpios = <&pioD 5 GPIO_ACTIVE_HIGH + &pioD 4 GPIO_ACTIVE_HIGH + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x00100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ + &pioA 31 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/at91sam9n12ek.dts b/arch/arm/dts/at91sam9n12ek.dts new file mode 100644 index 0000000..888bda1 --- /dev/null +++ b/arch/arm/dts/at91sam9n12ek.dts @@ -0,0 +1,265 @@ +/* + * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Hong Xu + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9n12.dtsi" + +/ { + model = "Atmel AT91SAM9N12-EK"; + compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9"; + + chosen { + bootargs = "root=/dev/mtdblock1 rw rootfstype=jffs2"; + stdout-path = "serial0:115200n8"; + u-boot,dm-pre-reloc; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <16000000>; + }; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + ssc0: ssc@f0010000 { + status = "okay"; + }; + + i2c0: i2c@f8010000 { + status = "okay"; + + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck0>; + clock-names = "mclk"; + }; + + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioA>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + }; + }; + + mmc0: mmc@f0008000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>; + }; + }; + + pinctrl@fffff400 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PA7 gpio CD pin pull up and deglitch */ + }; + }; + + qt1070 { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + ; + }; + }; + + sound { + pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { + atmel,pins = + ; + }; + }; + + usb1 { + pinctrl_usb1_vbus_sense: usb1_vbus_sense { + atmel,pins = + ; /* PB16 gpio usb vbus sense, no pull up and deglitch */ + }; + }; + }; + + spi0: spi@f0000000 { + status = "okay"; + cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; + spi_flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + hlcdc: hlcdc@f8038000 { + status = "okay"; + + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + usb1: gadget@f803c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus_sense>; + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + + rtc@fffffeb0 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; + atmel,pmecc-cap = <2>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + }; + + usb0: ohci@00500000 { + num-ports = <1>; + atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <&bl_reg>; + status = "okay"; + }; + + bl_reg: backlight_regulator { + compatible = "regulator-fixed"; + regulator-name = "backlight-power-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + d8 { + label = "d8"; + gpios = <&pioB 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + d9 { + label = "d9"; + gpios = <&pioB 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "nand-disk"; + }; + + d10 { + label = "d10"; + gpios = <&pioB 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + enter { + label = "Enter"; + gpios = <&pioB 3 GPIO_ACTIVE_LOW>; + linux,code = <28>; + wakeup-source; + }; + }; + + panel: panel { + compatible = "qiaodian,qd43003c0-40", "simple-panel"; + backlight = <&backlight>; + power-supply = <&panel_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + panel_reg: panel_regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-power-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "okay"; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; + + atmel,model = "wm8904 @ AT91SAM9N12"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; +}; -- cgit v0.10.2 From eb6f87cc074c0d1edbd6acfe76ef18ee107c5dba Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 13:49:36 +0800 Subject: ARM: dts: at91: Add dts files for at91sam9m10g45ek The device tree source files of at91sam9m10g45ek boards are copied from the Linux v4.10, do the changes as below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Add the "u-boot,dm-pre-reloc" property to determine which nodes are used by the board_init_f stage. - Fix the compilation warnings. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2417f1f..129e341 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -352,6 +352,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2e-evm.dtb \ keystone-k2g-evm.dtb +dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb + dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ at91sam9g15ek.dtb \ at91sam9g25ek.dtb \ diff --git a/arch/arm/dts/at91sam9g45.dtsi b/arch/arm/dts/at91sam9g45.dtsi index af8b708..1be1270 100644 --- a/arch/arm/dts/at91sam9g45.dtsi +++ b/arch/arm/dts/at91sam9g45.dtsi @@ -84,12 +84,14 @@ #address-cells = <1>; #size-cells = <1>; ranges; + u-boot,dm-pre-reloc; apb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + u-boot,dm-pre-reloc; aic: interrupt-controller@fffff000 { #interrupt-cells = <3>; @@ -121,6 +123,7 @@ #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; + u-boot,dm-pre-reloc; main_osc: main_osc { compatible = "atmel,at91rm9200-clk-main-osc"; @@ -135,7 +138,7 @@ clocks = <&main_osc>; }; - plla: pllack { + plla: pllack@0 { compatible = "atmel,at91rm9200-clk-pll"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_LOCKA>; @@ -173,6 +176,7 @@ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; atmel,clk-output-range = <0 133333333>; atmel,clk-divisors = <1 2 4 3>; + u-boot,dm-pre-reloc; }; usb: usbck { @@ -188,13 +192,13 @@ interrupt-parent = <&pmc>; clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - prog0: prog0 { + prog0: prog@0 { #clock-cells = <0>; reg = <0>; interrupts = ; }; - prog1: prog1 { + prog1: prog@1 { #clock-cells = <0>; reg = <1>; interrupts = ; @@ -206,25 +210,25 @@ #address-cells = <1>; #size-cells = <0>; - ddrck: ddrck { + ddrck: ddrck@2 { #clock-cells = <0>; reg = <2>; clocks = <&mck>; }; - uhpck: uhpck { + uhpck: uhpck@6 { #clock-cells = <0>; reg = <6>; clocks = <&usb>; }; - pck0: pck0 { + pck0: pck0@8 { #clock-cells = <0>; reg = <8>; clocks = <&prog0>; }; - pck1: pck1 { + pck1: pck1@9 { #clock-cells = <0>; reg = <9>; clocks = <&prog1>; @@ -237,147 +241,147 @@ #size-cells = <0>; clocks = <&mck>; - pioA_clk: pioA_clk { + pioA_clk: pioA_clk@2 { #clock-cells = <0>; reg = <2>; }; - pioB_clk: pioB_clk { + pioB_clk: pioB_clk@3 { #clock-cells = <0>; reg = <3>; }; - pioC_clk: pioC_clk { + pioC_clk: pioC_clk@4 { #clock-cells = <0>; reg = <4>; }; - pioDE_clk: pioDE_clk { + pioDE_clk: pioDE_clk@5 { #clock-cells = <0>; reg = <5>; }; - trng_clk: trng_clk { + trng_clk: trng_clk@6 { #clock-cells = <0>; reg = <6>; }; - usart0_clk: usart0_clk { + usart0_clk: usart0_clk@7 { #clock-cells = <0>; reg = <7>; }; - usart1_clk: usart1_clk { + usart1_clk: usart1_clk@8 { #clock-cells = <0>; reg = <8>; }; - usart2_clk: usart2_clk { + usart2_clk: usart2_clk@9 { #clock-cells = <0>; reg = <9>; }; - usart3_clk: usart3_clk { + usart3_clk: usart3_clk@10 { #clock-cells = <0>; reg = <10>; }; - mci0_clk: mci0_clk { + mci0_clk: mci0_clk@11 { #clock-cells = <0>; reg = <11>; }; - twi0_clk: twi0_clk { + twi0_clk: twi0_clk@12 { #clock-cells = <0>; reg = <12>; }; - twi1_clk: twi1_clk { + twi1_clk: twi1_clk@13 { #clock-cells = <0>; reg = <13>; }; - spi0_clk: spi0_clk { + spi0_clk: spi0_clk@14 { #clock-cells = <0>; reg = <14>; }; - spi1_clk: spi1_clk { + spi1_clk: spi1_clk@15 { #clock-cells = <0>; reg = <15>; }; - ssc0_clk: ssc0_clk { + ssc0_clk: ssc0_clk@16 { #clock-cells = <0>; reg = <16>; }; - ssc1_clk: ssc1_clk { + ssc1_clk: ssc1_clk@17 { #clock-cells = <0>; reg = <17>; }; - tcb0_clk: tcb0_clk { + tcb0_clk: tcb0_clk@18 { #clock-cells = <0>; reg = <18>; }; - pwm_clk: pwm_clk { + pwm_clk: pwm_clk@19 { #clock-cells = <0>; reg = <19>; }; - adc_clk: adc_clk { + adc_clk: adc_clk@20 { #clock-cells = <0>; reg = <20>; }; - dma0_clk: dma0_clk { + dma0_clk: dma0_clk@21 { #clock-cells = <0>; reg = <21>; }; - uhphs_clk: uhphs_clk { + uhphs_clk: uhphs_clk@22 { #clock-cells = <0>; reg = <22>; }; - lcd_clk: lcd_clk { + lcd_clk: lcd_clk@23 { #clock-cells = <0>; reg = <23>; }; - ac97_clk: ac97_clk { + ac97_clk: ac97_clk@24 { #clock-cells = <0>; reg = <24>; }; - macb0_clk: macb0_clk { + macb0_clk: macb0_clk@25 { #clock-cells = <0>; reg = <25>; }; - isi_clk: isi_clk { + isi_clk: isi_clk@26 { #clock-cells = <0>; reg = <26>; }; - udphs_clk: udphs_clk { + udphs_clk: udphs_clk@27 { #clock-cells = <0>; reg = <27>; }; - aestdessha_clk: aestdessha_clk { + aestdessha_clk: aestdessha_clk@28 { #clock-cells = <0>; reg = <28>; }; - mci1_clk: mci1_clk { + mci1_clk: mci1_clk@29 { #clock-cells = <0>; reg = <29>; }; - vdec_clk: vdec_clk { + vdec_clk: vdec_clk@30 { #clock-cells = <0>; reg = <30>; }; @@ -434,6 +438,13 @@ #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff200 0xfffff200 0xa00>; + reg = <0xfffff200 0x200 + 0xfffff400 0x200 + 0xfffff600 0x200 + 0xfffff800 0x200 + 0xfffffa00 0x200 + >; + u-boot,dm-pre-reloc; atmel,mux-mask = < /* A B */ @@ -476,10 +487,11 @@ }; dbgu { + u-boot,dm-pre-reloc; pinctrl_dbgu: dbgu-0 { atmel,pins = - ; /* PB13 periph A */ + ; }; }; @@ -845,61 +857,61 @@ AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ }; }; + }; - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + }; - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioDE_clk>; - }; + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioDE_clk>; + }; - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioDE_clk>; - }; + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioDE_clk>; }; dbgu: serial@ffffee00 { @@ -978,7 +990,7 @@ trng@fffcc000 { compatible = "atmel,at91sam9g45-trng"; - reg = <0xfffcc000 0x4000>; + reg = <0xfffcc000 0x100>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&trng_clk>; }; @@ -1044,28 +1056,24 @@ atmel,adc-res-names = "lowres", "highres"; atmel,adc-use-res = "highres"; - trigger@0 { - reg = <0>; + trigger0 { trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; - trigger@1 { - reg = <1>; + trigger1 { trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; - trigger@2 { - reg = <2>; + trigger2 { trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; - trigger@3 { - reg = <3>; + trigger3 { trigger-name = "continuous"; trigger-value = <0x6>; }; @@ -1169,13 +1177,13 @@ clock-names = "pclk", "hclk"; status = "disabled"; - ep0 { + ep@0 { reg = <0>; atmel,fifo-size = <64>; atmel,nb-banks = <1>; }; - ep1 { + ep@1 { reg = <1>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -1183,7 +1191,7 @@ atmel,can-isoc; }; - ep2 { + ep@2 { reg = <2>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -1191,21 +1199,21 @@ atmel,can-isoc; }; - ep3 { + ep@3 { reg = <3>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep4 { + ep@4 { reg = <4>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep5 { + ep@5 { reg = <5>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -1213,7 +1221,7 @@ atmel,can-isoc; }; - ep6 { + ep@6 { reg = <6>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -1320,7 +1328,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */ &pioA 21 GPIO_ACTIVE_HIGH /* scl */ diff --git a/arch/arm/dts/at91sam9m10g45ek.dts b/arch/arm/dts/at91sam9m10g45ek.dts new file mode 100644 index 0000000..52a76fe --- /dev/null +++ b/arch/arm/dts/at91sam9m10g45ek.dts @@ -0,0 +1,359 @@ +/* + * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board + * + * Copyright (C) 2011 Atmel, + * 2011 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9g45.dtsi" +#include + +/ { + model = "Atmel AT91SAM9M10G45-EK"; + compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2"; + stdout-path = "serial0:115200n8"; + u-boot,dm-pre-reloc; + }; + + memory { + reg = <0x70000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + + usart1: serial@fff90000 { + pinctrl-0 = + <&pinctrl_usart1 + &pinctrl_usart1_rts + &pinctrl_usart1_cts>; + status = "okay"; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + + i2c0: i2c@fff84000 { + status = "okay"; + ov2640: camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; + clocks = <&pck1>; + clock-names = "xvclk"; + assigned-clocks = <&pck1>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; + + i2c1: i2c@fff88000 { + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + mmc0: mmc@fff80000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; + }; + }; + + mmc1: mmc@fffd0000 { + pinctrl-0 = < + &pinctrl_board_mmc1 + &pinctrl_mmc1_slot0_clk_cmd_dat0 + &pinctrl_mmc1_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; + }; + }; + + pinctrl@fffff200 { + camera_sensor { + pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { + atmel,pins = + ; + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + ; + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + ; + }; + }; + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PD10 gpio CD pin pull up and deglitch */ + }; + }; + + mmc1 { + pinctrl_board_mmc1: mmc1-board { + atmel,pins = + ; /* PD29 gpio WP pin pull up */ + }; + }; + + pwm0 { + pinctrl_pwm_leds: pwm-led { + atmel,pins = + ; /* PD31 periph B */ + }; + }; + }; + + spi0: spi@fffa4000{ + status = "okay"; + cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <13000000>; + reg = <0>; + }; + }; + + usb2: gadget@fff78000 { + atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + adc0: adc@fffb0000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7>; + atmel,adc-ts-wires = <4>; + status = "okay"; + }; + + isi@fffb4000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + status = "okay"; + port { + isi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; + + pwm0: pwm@fffb8000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_leds>; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + gpbr: syscon@fffffd60 { + status = "okay"; + }; + + rtc@fffffdb0 { + status = "okay"; + }; + }; + + fb0: fb@0x00500000 { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <32>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <9>; + atmel,lcd-wiring-mode = "RGB"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hback-porch = <1>; + hfront-porch = <1>; + vback-porch = <40>; + vfront-porch = <1>; + hsync-len = <45>; + vsync-len = <1>; + }; + }; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + boot@0 { + label = "bootstrap/uboot/kernel"; + reg = <0x0 0x400000>; + }; + + rootfs@400000 { + label = "rootfs"; + reg = <0x400000 0x3C00000>; + }; + + data@4000000 { + label = "data"; + reg = <0x4000000 0xC000000>; + }; + }; + + usb0: ohci@00700000 { + status = "okay"; + num-ports = <2>; + atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW + &pioD 3 GPIO_ACTIVE_LOW>; + }; + + usb1: ehci@00800000 { + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + d8 { + label = "d8"; + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + d6 { + label = "d6"; + pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "nand-disk"; + }; + + d7 { + label = "d7"; + pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + linux,default-trigger = "mmc0"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + left_click { + label = "left_click"; + gpios = <&pioB 6 GPIO_ACTIVE_LOW>; + linux,code = <272>; + wakeup-source; + }; + + right_click { + label = "right_click"; + gpios = <&pioB 7 GPIO_ACTIVE_LOW>; + linux,code = <273>; + wakeup-source; + }; + + left { + label = "Joystick Left"; + gpios = <&pioB 14 GPIO_ACTIVE_LOW>; + linux,code = <105>; + }; + + right { + label = "Joystick Right"; + gpios = <&pioB 15 GPIO_ACTIVE_LOW>; + linux,code = <106>; + }; + + up { + label = "Joystick Up"; + gpios = <&pioB 16 GPIO_ACTIVE_LOW>; + linux,code = <103>; + }; + + down { + label = "Joystick Down"; + gpios = <&pioB 17 GPIO_ACTIVE_LOW>; + linux,code = <108>; + }; + + enter { + label = "Joystick Press"; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; + linux,code = <28>; + }; + }; +}; -- cgit v0.10.2 From 627e41f12551d2d726361679e3b0940e95cfd7d0 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 13:49:37 +0800 Subject: ARM: dts: at91: Add dts files for at91sam9260ek/9g20ek The device tree source files of at91sam9g20ek and at91sam9260ek boards are copied from the Linux v4.10, do the changes below. - Fix the build error for the usb0 node. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used in board_init_f stage. - Add the clk pinctrl of the mmc0 node. - Fix the compilation warnings. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 129e341..5a22fd3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -352,6 +352,11 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2e-evm.dtb \ keystone-k2g-evm.dtb +dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \ + at91sam9260ek.dtb \ + at91sam9g20ek.dtb \ + at91sam9g20ek_2mmc.dtb + dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi index d4884dd..0f25e33 100644 --- a/arch/arm/dts/at91sam9260.dtsi +++ b/arch/arm/dts/at91sam9260.dtsi @@ -79,12 +79,14 @@ #address-cells = <1>; #size-cells = <1>; ranges; + u-boot,dm-pre-reloc; apb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + u-boot,dm-pre-reloc; aic: interrupt-controller@fffff000 { #interrupt-cells = <3>; @@ -107,6 +109,7 @@ #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; + u-boot,dm-pre-reloc; main_osc: main_osc { compatible = "atmel,at91rm9200-clk-main-osc"; @@ -134,7 +137,7 @@ clocks = <&slow_rc_osc>, <&slow_xtal>; }; - plla: pllack { + plla: pllack@0 { compatible = "atmel,at91rm9200-clk-pll"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_LOCKA>; @@ -146,7 +149,7 @@ <150000000 240000000 2 1>; }; - pllb: pllbck { + pllb: pllbck@1 { compatible = "atmel,at91rm9200-clk-pll"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_LOCKB>; @@ -164,6 +167,7 @@ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; atmel,clk-output-range = <0 105000000>; atmel,clk-divisors = <1 2 4 0>; + u-boot,dm-pre-reloc; }; usb: usbck { @@ -180,13 +184,13 @@ interrupt-parent = <&pmc>; clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; - prog0: prog0 { + prog0: prog@0 { #clock-cells = <0>; reg = <0>; interrupts = ; }; - prog1: prog1 { + prog1: prog@1 { #clock-cells = <0>; reg = <1>; interrupts = ; @@ -198,25 +202,25 @@ #address-cells = <1>; #size-cells = <0>; - uhpck: uhpck { + uhpck: uhpck@6 { #clock-cells = <0>; reg = <6>; clocks = <&usb>; }; - udpck: udpck { + udpck: udpck@7 { #clock-cells = <0>; reg = <7>; clocks = <&usb>; }; - pck0: pck0 { + pck0: pck0@8 { #clock-cells = <0>; reg = <8>; clocks = <&prog0>; }; - pck1: pck1 { + pck1: pck1@9 { #clock-cells = <0>; reg = <9>; clocks = <&prog1>; @@ -228,128 +232,132 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&mck>; + u-boot,dm-pre-reloc; - pioA_clk: pioA_clk { + pioA_clk: pioA_clk@2 { #clock-cells = <0>; reg = <2>; + u-boot,dm-pre-reloc; }; - pioB_clk: pioB_clk { + pioB_clk: pioB_clk@3 { #clock-cells = <0>; reg = <3>; + u-boot,dm-pre-reloc; }; - pioC_clk: pioC_clk { + pioC_clk: pioC_clk@4 { #clock-cells = <0>; reg = <4>; + u-boot,dm-pre-reloc; }; - adc_clk: adc_clk { + adc_clk: adc_clk@5 { #clock-cells = <0>; reg = <5>; }; - usart0_clk: usart0_clk { + usart0_clk: usart0_clk@6 { #clock-cells = <0>; reg = <6>; }; - usart1_clk: usart1_clk { + usart1_clk: usart1_clk@7 { #clock-cells = <0>; reg = <7>; }; - usart2_clk: usart2_clk { + usart2_clk: usart2_clk@8 { #clock-cells = <0>; reg = <8>; }; - mci0_clk: mci0_clk { + mci0_clk: mci0_clk@9 { #clock-cells = <0>; reg = <9>; }; - udc_clk: udc_clk { + udc_clk: udc_clk@10 { #clock-cells = <0>; reg = <10>; }; - twi0_clk: twi0_clk { + twi0_clk: twi0_clk@11 { reg = <11>; #clock-cells = <0>; }; - spi0_clk: spi0_clk { + spi0_clk: spi0_clk@12 { #clock-cells = <0>; reg = <12>; }; - spi1_clk: spi1_clk { + spi1_clk: spi1_clk@13 { #clock-cells = <0>; reg = <13>; }; - ssc0_clk: ssc0_clk { + ssc0_clk: ssc0_clk@14 { #clock-cells = <0>; reg = <14>; }; - tc0_clk: tc0_clk { + tc0_clk: tc0_clk@17 { #clock-cells = <0>; reg = <17>; }; - tc1_clk: tc1_clk { + tc1_clk: tc1_clk@18 { #clock-cells = <0>; reg = <18>; }; - tc2_clk: tc2_clk { + tc2_clk: tc2_clk@19 { #clock-cells = <0>; reg = <19>; }; - ohci_clk: ohci_clk { + ohci_clk: ohci_clk@20 { #clock-cells = <0>; reg = <20>; }; - macb0_clk: macb0_clk { + macb0_clk: macb0_clk@21 { #clock-cells = <0>; reg = <21>; }; - isi_clk: isi_clk { + isi_clk: isi_clk@22 { #clock-cells = <0>; reg = <22>; }; - usart3_clk: usart3_clk { + usart3_clk: usart3_clk@23 { #clock-cells = <0>; reg = <23>; }; - uart0_clk: uart0_clk { + uart0_clk: uart0_clk@24 { #clock-cells = <0>; reg = <24>; }; - uart1_clk: uart1_clk { + uart1_clk: uart1_clk@25 { #clock-cells = <0>; reg = <25>; }; - tc3_clk: tc3_clk { + tc3_clk: tc3_clk@26 { #clock-cells = <0>; reg = <26>; }; - tc4_clk: tc4_clk { + tc4_clk: tc4_clk@27 { #clock-cells = <0>; reg = <27>; }; - tc5_clk: tc5_clk { + tc5_clk: tc5_clk@28 { #clock-cells = <0>; reg = <28>; }; @@ -395,11 +403,51 @@ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + u-boot,dm-pre-reloc; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + u-boot,dm-pre-reloc; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + u-boot,dm-pre-reloc; + }; + pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x600>; + reg = <0xfffff400 0x200 /* pioA */ + 0xfffff600 0x200 /* pioB */ + 0xfffff800 0x200 /* pioC */ + >; atmel,mux-mask = < /* A B */ @@ -407,9 +455,11 @@ 0xffffffff 0x7fff3ccf /* pioB */ 0xffffffff 0x007fffff /* pioC */ >; + u-boot,dm-pre-reloc; /* shared pinctrl settings */ dbgu { + u-boot,dm-pre-reloc; pinctrl_dbgu: dbgu-0 { atmel,pins = ; }; }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; }; dbgu: serial@fffff200 { diff --git a/arch/arm/dts/at91sam9260ek.dts b/arch/arm/dts/at91sam9260ek.dts new file mode 100644 index 0000000..086c8ea --- /dev/null +++ b/arch/arm/dts/at91sam9260ek.dts @@ -0,0 +1,215 @@ +/* + * Device Tree file for Atmel at91sam9260 Evaluation Kit + * + * Copyright (C) 2016 Atmel, + * 2016 Nicolas Ferre + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "at91sam9260.dtsi" + +/ { + model = "Atmel at91sam9260ek"; + compatible = "atmel,at91sam9260ek", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &dbgu; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_board_mmc0_slot1 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot1_cmd_dat0 + &pinctrl_mmc0_slot1_dat1_3>; + status = "okay"; + slot@1 { + reg = <1>; + bus-width = <4>; + cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + ssc0: ssc@fffbc000 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + spi0: spi@fffc8000 { + cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; + }; + + dbgu: serial@fffff200 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + pinctrl@fffff400 { + board { + pinctrl_board_mmc0_slot1: mmc0_slot1-board { + atmel,pins = + ; + }; + }; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + gpbr: syscon@fffffd50 { + status = "okay"; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + btn3 { + label = "Button 3"; + gpios = <&pioA 30 GPIO_ACTIVE_LOW>; + linux,code = <0x103>; + wakeup-source; + }; + + btn4 { + label = "Button 4"; + gpios = <&pioA 31 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + i2c-gpio-0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + 24c512@50 { + compatible = "24c512"; + reg = <0x50>; + }; + }; + + leds { + compatible = "gpio-leds"; + + ds1 { + label = "ds1"; + gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + ds5 { + label = "ds5"; + gpios = <&pioA 6 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g20.dtsi b/arch/arm/dts/at91sam9g20.dtsi index f593016..e88d73c 100644 --- a/arch/arm/dts/at91sam9g20.dtsi +++ b/arch/arm/dts/at91sam9g20.dtsi @@ -40,7 +40,7 @@ }; pmc: pmc@fffffc00 { - plla: pllack { + plla: pllack@0 { atmel,clk-input-range = <2000000 32000000>; atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, <695000000 750000000 1 0>, @@ -52,7 +52,7 @@ <400000000 450000000 3 1>; }; - pllb: pllbck { + pllb: pllbck@1 { compatible = "atmel,at91sam9g20-clk-pllb"; atmel,clk-input-range = <2000000 32000000>; atmel,pll-clk-output-ranges = <30000000 100000000 0 0>; diff --git a/arch/arm/dts/at91sam9g20ek.dts b/arch/arm/dts/at91sam9g20ek.dts new file mode 100644 index 0000000..bbfd753 --- /dev/null +++ b/arch/arm/dts/at91sam9g20ek.dts @@ -0,0 +1,29 @@ +/* + * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "at91sam9g20ek_common.dtsi" + +/ { + model = "Atmel at91sam9g20ek"; + compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9"; + + leds { + compatible = "gpio-leds"; + + ds1 { + label = "ds1"; + gpios = <&pioA 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + ds5 { + label = "ds5"; + gpios = <&pioA 6 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g20ek_2mmc.dts b/arch/arm/dts/at91sam9g20ek_2mmc.dts new file mode 100644 index 0000000..7ea83b6 --- /dev/null +++ b/arch/arm/dts/at91sam9g20ek_2mmc.dts @@ -0,0 +1,56 @@ +/* + * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "at91sam9g20ek_common.dtsi" + +/ { + model = "Atmel at91sam9g20ek 2 mmc"; + compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9"; + + ahb { + apb{ + mmc0: mmc@fffa8000 { + /* clk already mux wuth slot0 */ + pinctrl-0 = < + &pinctrl_board_mmc0_slot0 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot0_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>; + }; + }; + + pinctrl@fffff400 { + mmc0_slot0 { + pinctrl_board_mmc0_slot0: mmc0_slot0-board { + atmel,pins = + ; /* PC2 gpio CD pin pull up and deglitch */ + }; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + ds1 { + label = "ds1"; + gpios = <&pioB 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + ds5 { + label = "ds5"; + gpios = <&pioB 8 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g20ek_common.dtsi b/arch/arm/dts/at91sam9g20ek_common.dtsi new file mode 100644 index 0000000..65ae099 --- /dev/null +++ b/arch/arm/dts/at91sam9g20ek_common.dtsi @@ -0,0 +1,227 @@ +/* + * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2. + */ +#include "at91sam9g20.dtsi" + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &dbgu; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + pinctrl@fffff400 { + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = + ; /* PC1 periph B */ + }; + + }; + + mmc0_slot1 { + pinctrl_board_mmc0_slot1: mmc0_slot1-board { + atmel,pins = + ; /* PC9 gpio CD pin pull up and deglitch */ + }; + }; + }; + + dbgu: serial@fffff200 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_board_mmc0_slot1 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot1_cmd_dat0 + &pinctrl_mmc0_slot1_dat1_3>; + status = "okay"; + slot@1 { + reg = <1>; + bus-width = <4>; + cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>; + }; + }; + + ssc0: ssc@fffbc000 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; + }; + + spi0: spi@fffc8000 { + cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + gpbr: syscon@fffffd50 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + i2c-gpio-0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + 24c512@50 { + compatible = "24c512"; + reg = <0x50>; + }; + + wm8731: wm8731@1b { + compatible = "wm8731"; + reg = <0x1b>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + btn3 { + label = "Button 3"; + gpios = <&pioA 30 GPIO_ACTIVE_LOW>; + linux,code = <0x103>; + wakeup-source; + }; + + btn4 { + label = "Button 4"; + gpios = <&pioA 31 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + sound { + compatible = "atmel,at91sam9g20ek-wm8731-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_mck>; + + atmel,model = "wm8731 @ AT91SAMG20EK"; + + atmel,audio-routing = + "Ext Spk", "LHPOUT", + "Int Mic", "MICIN"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8731>; + }; +}; -- cgit v0.10.2 From 1e315a356b28ab77ec1b854e5943a14bf198d11e Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 13:49:38 +0800 Subject: ARM: dts: at91: Add dts files for at91sam9rlek The device tree source files of at91sam9rlek boards are copied from the Linux v4.10, do the changes as below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used in board_init_f stage. - Fix the compilation warnings. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5a22fd3..916958e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -352,6 +352,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2e-evm.dtb \ keystone-k2g-evm.dtb +dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb + dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \ at91sam9260ek.dtb \ at91sam9g20ek.dtb \ diff --git a/arch/arm/dts/at91sam9rl.dtsi b/arch/arm/dts/at91sam9rl.dtsi new file mode 100644 index 0000000..8249994 --- /dev/null +++ b/arch/arm/dts/at91sam9rl.dtsi @@ -0,0 +1,1139 @@ +/* + * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC + * + * Copyright (C) 2014 Alexandre Belloni + * + * Licensed under GPLv2 or later. + */ + +#include "skeleton.dtsi" +#include +#include +#include +#include +#include + +/ { + model = "Atmel AT91SAM9RL family SoC"; + compatible = "atmel,at91sam9rl", "atmel,at91sam9"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + i2c0 = &i2c0; + i2c1 = &i2c1; + ssc0 = &ssc0; + ssc1 = &ssc1; + pwm0 = &pwm0; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + reg = <0x20000000 0x04000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + sram: sram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x10000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + fb0: fb@00500000 { + compatible = "atmel,at91sam9rl-lcdc"; + reg = <0x00500000 0x1000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + clocks = <&lcd_clk>, <&lcd_clk>; + clock-names = "hclk", "lcdc_clk"; + status = "disabled"; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000>, + <0xffffe800 0x200>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + gpios = <&pioD 17 GPIO_ACTIVE_HIGH>, + <&pioB 6 GPIO_ACTIVE_HIGH>, + <0>; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + tcb0: timer@fffa0000 { + compatible = "atmel,at91rm9200-tcb"; + reg = <0xfffa0000 0x100>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, + <17 IRQ_TYPE_LEVEL_HIGH 0>, + <18 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; + }; + + mmc0: mmc@fffa4000 { + compatible = "atmel,hsmci"; + reg = <0xfffa4000 0x600>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + status = "disabled"; + }; + + i2c0: i2c@fffa8000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfffa8000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + i2c1: i2c@fffac000 { + compatible = "atmel,at91sam9260-i2c"; + reg = <0xfffac000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usart0: serial@fffb0000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb0000 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@fffb4000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb4000 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fffb8000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffb8000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fffbc000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffbc000 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; + atmel,use-dma-rx; + atmel,use-dma-tx; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@fffc0000 { + compatible = "atmel,at91sam9rl-ssc"; + reg = <0xfffc0000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + status = "disabled"; + }; + + ssc1: ssc@fffc4000 { + compatible = "atmel,at91sam9rl-ssc"; + reg = <0xfffc4000 0x4000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + status = "disabled"; + }; + + pwm0: pwm@fffc8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffc8000 0x300>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + clock-names = "pwm_clk"; + status = "disabled"; + }; + + spi0: spi@fffcc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + adc0: adc@fffd0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-adc"; + reg = <0xfffd0000 0x100>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&adc_clk>, <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-use-external-triggers; + atmel,adc-channels-used = <0x3f>; + atmel,adc-vref = <3300>; + atmel,adc-startup-time = <40>; + atmel,adc-res = <8 10>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-use-res = "highres"; + + trigger0 { + trigger-name = "timer-counter-0"; + trigger-value = <0x1>; + }; + trigger1 { + trigger-name = "timer-counter-1"; + trigger-value = <0x3>; + }; + + trigger2 { + trigger-name = "timer-counter-2"; + trigger-value = <0x5>; + }; + + trigger3 { + trigger-name = "external"; + trigger-value = <0x13>; + trigger-external; + }; + }; + + usb0: gadget@fffd4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-udc"; + reg = <0x00600000 0x100000>, + <0xfffd4000 0x4000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + ep@0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep@1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep@2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep@3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep@4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep@5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep@6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + }; + + dma0: dma-controller@ffffe600 { + compatible = "atmel,at91sam9rl-dma"; + reg = <0xffffe600 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; + status = "disabled"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + reg = <0xfffff400 0x200 + 0xfffff600 0x200 + 0xfffff800 0x200 + 0xfffffa00 0x200 + >; + + atmel,mux-mask = + /* A B */ + <0xffffffff 0xe05c6738>, /* pioA */ + <0xffffffff 0x0000c780>, /* pioB */ + <0xffffffff 0xe3ffff0e>, /* pioC */ + <0x003fffff 0x0001ff3c>; /* pioD */ + u-boot,dm-pre-reloc; + + /* shared pinctrl settings */ + adc0 { + pinctrl_adc0_ts: adc0_ts-0 { + atmel,pins = + , + , + , + ; + }; + + pinctrl_adc0_ad0: adc0_ad0-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad1: adc0_ad1-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad2: adc0_ad2-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad3: adc0_ad3-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad4: adc0_ad4-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad5: adc0_ad5-0 { + atmel,pins = ; + }; + + pinctrl_adc0_adtrg: adc0_adtrg-0 { + atmel,pins = ; + }; + }; + + dbgu { + u-boot,dm-pre-reloc; + pinctrl_dbgu: dbgu-0 { + atmel,pins = + , + ; + }; + }; + + fb { + pinctrl_fb: fb-0 { + atmel,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + i2c_gpio0 { + pinctrl_i2c_gpio0: i2c_gpio0-0 { + atmel,pins = + , + ; + }; + }; + + i2c_gpio1 { + pinctrl_i2c_gpio1: i2c_gpio1-0 { + atmel,pins = + , + ; + }; + }; + + mmc0 { + pinctrl_mmc0_clk: mmc0_clk-0 { + atmel,pins = + ; + }; + + pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { + atmel,pins = + , + ; + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + , + , + ; + }; + }; + + nand { + pinctrl_nand: nand-0 { + atmel,pins = + , + ; + }; + + pinctrl_nand0_ale_cle: nand_ale_cle-0 { + atmel,pins = + , + ; + }; + + pinctrl_nand0_oe_we: nand_oe_we-0 { + atmel,pins = + , + ; + }; + + pinctrl_nand0_cs: nand_cs-0 { + atmel,pins = + ; + }; + }; + + pwm0 { + pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { + atmel,pins = ; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + , + , + ; + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + , + , + ; + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + , + , + ; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = ; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = ; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart0_dcd: usart0_dcd-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_ri: usart0_ri-0 { + atmel,pins = + ; + }; + + pinctrl_usart0_sck: usart0_sck-0 { + atmel,pins = + ; + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart1_sck: usart1_sck-0 { + atmel,pins = + ; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart2_sck: usart2_sck-0 { + atmel,pins = + ; + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + , + ; + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + ; + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + ; + }; + + pinctrl_usart3_sck: usart3_sck-0 { + atmel,pins = + ; + }; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + u-boot,dm-pre-reloc; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + u-boot,dm-pre-reloc; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + u-boot,dm-pre-reloc; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + u-boot,dm-pre-reloc; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9g45-pmc", "syscon"; + reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + u-boot,dm-pre-reloc; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + plla: pllack@0 { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <1000000 32000000>; + #atmel,pll-clk-output-range-cells = <3>; + atmel,pll-clk-output-ranges = <80000000 200000000 0>, + <190000000 240000000 2>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91rm9200-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plla>, <&utmi>; + atmel,clk-output-range = <0 94000000>; + atmel,clk-divisors = <1 2 4 0>; + u-boot,dm-pre-reloc; + }; + + prog: progck { + compatible = "atmel,at91rm9200-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>; + + prog0: prog@0 { + #clock-cells = <0>; + reg = <0>; + interrupts = ; + }; + + prog1: prog@1 { + #clock-cells = <0>; + reg = <1>; + interrupts = ; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + pck0: pck0@8 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1@9 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + }; + + periphck { + compatible = "atmel,at91rm9200-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + u-boot,dm-pre-reloc; + + pioA_clk: pioA_clk@2 { + #clock-cells = <0>; + reg = <2>; + u-boot,dm-pre-reloc; + }; + + pioB_clk: pioB_clk@3 { + #clock-cells = <0>; + reg = <3>; + u-boot,dm-pre-reloc; + }; + + pioC_clk: pioC_clk@4 { + #clock-cells = <0>; + reg = <4>; + u-boot,dm-pre-reloc; + }; + + pioD_clk: pioD_clk@5 { + #clock-cells = <0>; + reg = <5>; + u-boot,dm-pre-reloc; + }; + + usart0_clk: usart0_clk@6 { + #clock-cells = <0>; + reg = <6>; + }; + + usart1_clk: usart1_clk@7 { + #clock-cells = <0>; + reg = <7>; + }; + + usart2_clk: usart2_clk@8 { + #clock-cells = <0>; + reg = <8>; + }; + + usart3_clk: usart3_clk@9 { + #clock-cells = <0>; + reg = <9>; + }; + + mci0_clk: mci0_clk@10 { + #clock-cells = <0>; + reg = <10>; + }; + + twi0_clk: twi0_clk@11 { + #clock-cells = <0>; + reg = <11>; + }; + + twi1_clk: twi1_clk@12 { + #clock-cells = <0>; + reg = <12>; + }; + + spi0_clk: spi0_clk@13 { + #clock-cells = <0>; + reg = <13>; + }; + + ssc0_clk: ssc0_clk@14 { + #clock-cells = <0>; + reg = <14>; + }; + + ssc1_clk: ssc1_clk@15 { + #clock-cells = <0>; + reg = <15>; + }; + + tc0_clk: tc0_clk@16 { + #clock-cells = <0>; + reg = <16>; + }; + + tc1_clk: tc1_clk@17 { + #clock-cells = <0>; + reg = <17>; + }; + + tc2_clk: tc2_clk@18 { + #clock-cells = <0>; + reg = <18>; + }; + + pwm_clk: pwm_clk@19 { + #clock-cells = <0>; + reg = <19>; + }; + + adc_clk: adc_clk@20 { + #clock-cells = <0>; + reg = <20>; + }; + + dma0_clk: dma0_clk@21 { + #clock-cells = <0>; + reg = <21>; + }; + + udphs_clk: udphs_clk@22 { + #clock-cells = <0>; + reg = <22>; + }; + + lcd_clk: lcd_clk@23 { + #clock-cells = <0>; + reg = <23>; + }; + }; + }; + + rstc@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; + }; + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; + }; + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + sckc@fffffd50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffd50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <1200000>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <75>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x10>; + status = "disabled"; + }; + + rtc@fffffe00 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffe00 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ + <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>; + status = "disabled"; + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ + <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio1>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/at91sam9rlek.dts b/arch/arm/dts/at91sam9rlek.dts new file mode 100644 index 0000000..ae42697 --- /dev/null +++ b/arch/arm/dts/at91sam9rlek.dts @@ -0,0 +1,239 @@ +/* + * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board + * + * Copyright (C) 2014 Alexandre Belloni + * + * Licensed under GPLv2 only + */ +/dts-v1/; +#include "at91sam9rl.dtsi" + +/ { + model = "Atmel at91sam9rlek"; + compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9"; + + chosen { + bootargs = "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw"; + stdout-path = "serial0:115200n8"; + u-boot,dm-pre-reloc; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + fb0: fb@00500000 { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + atmel,lcd-wiring-mode = "RGB"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt = <1>; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + + apb { + mmc0: mmc@fffa4000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot0_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = < + &pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts>; + status = "okay"; + }; + + adc0: adc@fffd0000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_adtrg>; + atmel,adc-ts-wires = <4>; + status = "okay"; + }; + + usb0: gadget@fffd4000 { + atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + spi0: spi@fffcc000 { + status = "okay"; + cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <15000000>; + reg = <0>; + }; + }; + + pwm0: pwm@fffc8000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm1_2>, + <&pinctrl_pwm0_pwm2_2>; + }; + + dbgu: serial@fffff200 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + pinctrl@fffff400 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; + }; + }; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + rtc@fffffe00 { + status = "okay"; + }; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + ds1 { + label = "ds1"; + pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + }; + + ds2 { + label = "ds2"; + pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; + }; + }; + + leds { + compatible = "gpio-leds"; + + ds3 { + label = "ds3"; + gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + right_click { + label = "right_click"; + gpios = <&pioB 0 GPIO_ACTIVE_LOW>; + linux,code = <273>; + wakeup-source; + }; + + left_click { + label = "left_click"; + gpios = <&pioB 1 GPIO_ACTIVE_LOW>; + linux,code = <272>; + wakeup-source; + }; + }; + + i2c-gpio-0 { + status = "okay"; + }; + + i2c-gpio-1 { + status = "okay"; + }; +}; -- cgit v0.10.2 From 6cb2a7fe81c024fe88ea5e83927c1cc2ff26ee59 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 13:49:39 +0800 Subject: ARM: dts: at91: Add dts files for at91sam9263ek The device tree source files of at91sam9263ek boards are copied from the Linux v4.10, do the changes as below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used in board_init_f stage. - Fix the compilation warnings. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 916958e..02836f1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -352,6 +352,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2e-evm.dtb \ keystone-k2g-evm.dtb +dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb + dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \ diff --git a/arch/arm/dts/at91sam9263.dtsi b/arch/arm/dts/at91sam9263.dtsi index 9344642..e899fd3 100644 --- a/arch/arm/dts/at91sam9263.dtsi +++ b/arch/arm/dts/at91sam9263.dtsi @@ -77,12 +77,14 @@ #address-cells = <1>; #size-cells = <1>; ranges; + u-boot,dm-pre-reloc; apb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + u-boot,dm-pre-reloc; aic: interrupt-controller@fffff000 { #interrupt-cells = <3>; @@ -100,6 +102,7 @@ #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; + u-boot,dm-pre-reloc; main_osc: main_osc { compatible = "atmel,at91rm9200-clk-main-osc"; @@ -114,7 +117,7 @@ clocks = <&main_osc>; }; - plla: pllack { + plla: pllack@0 { compatible = "atmel,at91rm9200-clk-pll"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_LOCKA>; @@ -126,7 +129,7 @@ <190000000 240000000 2 1>; }; - pllb: pllbck { + pllb: pllbck@1 { compatible = "atmel,at91rm9200-clk-pll"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_LOCKB>; @@ -145,6 +148,7 @@ clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; atmel,clk-output-range = <0 120000000>; atmel,clk-divisors = <1 2 4 0>; + u-boot,dm-pre-reloc; }; usb: usbck { @@ -161,25 +165,25 @@ interrupt-parent = <&pmc>; clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - prog0: prog0 { + prog0: prog@0 { #clock-cells = <0>; reg = <0>; interrupts = ; }; - prog1: prog1 { + prog1: prog@1 { #clock-cells = <0>; reg = <1>; interrupts = ; }; - prog2: prog2 { + prog2: prog@2 { #clock-cells = <0>; reg = <2>; interrupts = ; }; - prog3: prog3 { + prog3: prog@3 { #clock-cells = <0>; reg = <3>; interrupts = ; @@ -191,37 +195,37 @@ #address-cells = <1>; #size-cells = <0>; - uhpck: uhpck { + uhpck: uhpck@6 { #clock-cells = <0>; reg = <6>; clocks = <&usb>; }; - udpck: udpck { + udpck: udpck@7 { #clock-cells = <0>; reg = <7>; clocks = <&usb>; }; - pck0: pck0 { + pck0: pck0@8 { #clock-cells = <0>; reg = <8>; clocks = <&prog0>; }; - pck1: pck1 { + pck1: pck1@9 { #clock-cells = <0>; reg = <9>; clocks = <&prog1>; }; - pck2: pck2 { + pck2: pck2@10 { #clock-cells = <0>; reg = <10>; clocks = <&prog2>; }; - pck3: pck3 { + pck3: pck3@11 { #clock-cells = <0>; reg = <11>; clocks = <&prog3>; @@ -233,123 +237,127 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&mck>; + u-boot,dm-pre-reloc; - pioA_clk: pioA_clk { + pioA_clk: pioA_clk@2 { #clock-cells = <0>; reg = <2>; + u-boot,dm-pre-reloc; }; - pioB_clk: pioB_clk { + pioB_clk: pioB_clk@3 { #clock-cells = <0>; reg = <3>; + u-boot,dm-pre-reloc; }; - pioCDE_clk: pioCDE_clk { + pioCDE_clk: pioCDE_clk@4 { #clock-cells = <0>; reg = <4>; + u-boot,dm-pre-reloc; }; - usart0_clk: usart0_clk { + usart0_clk: usart0_clk@7 { #clock-cells = <0>; reg = <7>; }; - usart1_clk: usart1_clk { + usart1_clk: usart1_clk@8 { #clock-cells = <0>; reg = <8>; }; - usart2_clk: usart2_clk { + usart2_clk: usart2_clk@9 { #clock-cells = <0>; reg = <9>; }; - mci0_clk: mci0_clk { + mci0_clk: mci0_clk@10 { #clock-cells = <0>; reg = <10>; }; - mci1_clk: mci1_clk { + mci1_clk: mci1_clk@11 { #clock-cells = <0>; reg = <11>; }; - can_clk: can_clk { + can_clk: can_clk@12 { #clock-cells = <0>; reg = <12>; }; - twi0_clk: twi0_clk { + twi0_clk: twi0_clk@13 { #clock-cells = <0>; reg = <13>; }; - spi0_clk: spi0_clk { + spi0_clk: spi0_clk@14 { #clock-cells = <0>; reg = <14>; }; - spi1_clk: spi1_clk { + spi1_clk: spi1_clk@15 { #clock-cells = <0>; reg = <15>; }; - ssc0_clk: ssc0_clk { + ssc0_clk: ssc0_clk@16 { #clock-cells = <0>; reg = <16>; }; - ssc1_clk: ssc1_clk { + ssc1_clk: ssc1_clk@17 { #clock-cells = <0>; reg = <17>; }; - ac97_clk: ac97_clk { + ac97_clk: ac97_clk@18 { #clock-cells = <0>; reg = <18>; }; - tcb_clk: tcb_clk { + tcb_clk: tcb_clk@19 { #clock-cells = <0>; reg = <19>; }; - pwm_clk: pwm_clk { + pwm_clk: pwm_clk@20 { #clock-cells = <0>; reg = <20>; }; - macb0_clk: macb0_clk { + macb0_clk: macb0_clk@21 { #clock-cells = <0>; reg = <21>; }; - g2de_clk: g2de_clk { + g2de_clk: g2de_clk@23 { #clock-cells = <0>; reg = <23>; }; - udc_clk: udc_clk { + udc_clk: udc_clk@24 { #clock-cells = <0>; reg = <24>; }; - isi_clk: isi_clk { + isi_clk: isi_clk@25 { #clock-cells = <0>; reg = <25>; }; - lcd_clk: lcd_clk { + lcd_clk: lcd_clk@26 { #clock-cells = <0>; reg = <26>; }; - dma_clk: dma_clk { + dma_clk: dma_clk@27 { #clock-cells = <0>; reg = <27>; }; - ohci_clk: ohci_clk { + ohci_clk: ohci_clk@29 { #clock-cells = <0>; reg = <29>; }; @@ -398,6 +406,12 @@ #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff200 0xfffff200 0xa00>; + reg = <0xfffff200 0x200 + 0xfffff400 0x200 + 0xfffff600 0x200 + 0xfffff800 0x200 + 0xfffffa00 0x200 + >; atmel,mux-mask = < /* A B */ @@ -412,8 +426,8 @@ dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = - ; /* PC31 periph with pullup */ + ; }; }; @@ -707,60 +721,66 @@ }; }; - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; + }; - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + u-boot,dm-pre-reloc; + }; - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - }; + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + u-boot,dm-pre-reloc; + }; - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - }; + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + u-boot,dm-pre-reloc; + }; - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - }; + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + u-boot,dm-pre-reloc; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + u-boot,dm-pre-reloc; }; dbgu: serial@ffffee00 { @@ -1019,7 +1039,7 @@ }; }; - i2c@0 { + i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ &pioB 5 GPIO_ACTIVE_HIGH /* scl */ diff --git a/arch/arm/dts/at91sam9263ek.dts b/arch/arm/dts/at91sam9263ek.dts new file mode 100644 index 0000000..8cd7fad --- /dev/null +++ b/arch/arm/dts/at91sam9263ek.dts @@ -0,0 +1,229 @@ +/* + * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD + * + * Licensed under GPLv2 only + */ +/dts-v1/; +#include "at91sam9263.dtsi" + +/ { + model = "Atmel at91sam9263ek"; + compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; + stdout-path = "serial0:115200n8"; + u-boot,dm-pre-reloc; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <16367660>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + usart0: serial@fff8c000 { + pinctrl-0 = < + &pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts>; + status = "okay"; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fff78000 { + atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fff80000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot0_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>; + wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>; + }; + }; + + pinctrl@fffff200 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PE19 gpio WP pin pull up */ + }; + }; + }; + + spi0: spi@fffa4000 { + status = "okay"; + cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + }; + + fb0: fb@0x00700000 { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt = <1>; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + + usb0: ohci@00a00000 { + num-ports = <2>; + status = "okay"; + atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH + &pioA 21 GPIO_ACTIVE_HIGH + >; + }; + }; + + leds { + compatible = "gpio-leds"; + + d3 { + label = "d3"; + gpios = <&pioB 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + d2 { + label = "d2"; + gpios = <&pioC 29 GPIO_ACTIVE_LOW>; + linux,default-trigger = "nand-disk"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + left_click { + label = "left_click"; + gpios = <&pioC 5 GPIO_ACTIVE_LOW>; + linux,code = <272>; + wakeup-source; + }; + + right_click { + label = "right_click"; + gpios = <&pioC 4 GPIO_ACTIVE_LOW>; + linux,code = <273>; + wakeup-source; + }; + }; + + i2c-gpio-0 { + status = "okay"; + + 24c512@50 { + compatible = "24c512"; + reg = <0x50>; + pagesize = <128>; + }; + }; +}; -- cgit v0.10.2 From 74631b69d6658738e2bbb39f896d622144f4c654 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 14:51:54 +0800 Subject: configs: at91sam9x5ek: Update to support DM/DT Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Because the limitation of internal SRAM size, the SPL with driver model can't be supported, disable the SPL option. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index cc81776..0ae42dd 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -205,6 +205,7 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */ +#ifndef CONFIG_DM_SPI /* SPI chip select control */ #ifdef CONFIG_ATMEL_SPI int spi_cs_is_valid(unsigned int bus, unsigned int cs) @@ -238,6 +239,7 @@ void spi_cs_deactivate(struct spi_slave *slave) } } #endif /* CONFIG_ATMEL_SPI */ +#endif #ifdef CONFIG_GENERIC_ATMEL_MCI int board_mmc_init(bd_t *bd) diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index e07e217..7850b99 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -21,9 +23,28 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 9a95a04..5990778 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -21,9 +23,28 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index d93f687..816fe69 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -1,17 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y @@ -27,9 +23,28 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 5fc512b..8574525 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -1,18 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y @@ -28,9 +23,28 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index ff0a78b..52a051a 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -26,12 +26,6 @@ /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS /* LCD */ #define LCD_BPP LCD_COLOR16 @@ -67,11 +61,10 @@ #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) /* DataFlash */ #ifdef CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI #define CONFIG_SF_DEFAULT_SPEED 30000000 #endif @@ -104,23 +97,9 @@ #define CONFIG_CMD_UBIFS #endif -/* MMC */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY - /* USB */ #ifdef CONFIG_CMD_USB -#ifdef CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ATMEL -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 -#else +#ifndef CONFIG_USB_EHCI #define CONFIG_USB_ATMEL #define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_OHCI_NEW @@ -139,7 +118,7 @@ #ifdef CONFIG_SYS_USE_NANDFLASH /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET 0x120000 #define CONFIG_ENV_OFFSET_REDUND 0x100000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ #define CONFIG_BOOTCOMMAND "nand read " \ -- cgit v0.10.2 From 154de5ad0e6c5d66010c1dceb2ec8ca25de06aae Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 14:51:55 +0800 Subject: board: at91sam9x5ek: Clean up code Since the introduction of the pinctrl and clock driver and the device tree files, remove unneeded hard coded related code from the board file. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 0ae42dd..235b337 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -14,18 +14,10 @@ #include #include #include -#include -#ifdef CONFIG_MACB -#include -#endif -#include #ifdef CONFIG_LCD_INFO #include #include #endif -#ifdef CONFIG_ATMEL_SPI -#include -#endif DECLARE_GLOBAL_DATA_PTR; @@ -92,21 +84,6 @@ static void at91sam9x5ek_nand_hw_init(void) } #endif -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_MACB - if (has_emac0()) - rc = macb_eth_initialize(0, - (void *)ATMEL_BASE_EMAC0, 0x00); - if (has_emac1()) - rc = macb_eth_initialize(1, - (void *)ATMEL_BASE_EMAC1, 0x00); -#endif - return rc; -} - #ifdef CONFIG_LCD vidinfo_t panel_info = { .vl_col = 800, @@ -205,51 +182,6 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */ -#ifndef CONFIG_DM_SPI -/* SPI chip select control */ -#ifdef CONFIG_ATMEL_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < 2; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - switch (slave->cs) { - case 1: - at91_set_pio_output(AT91_PIO_PORTA, 7, 0); - break; - case 0: - default: - at91_set_pio_output(AT91_PIO_PORTA, 14, 0); - break; - } -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - switch (slave->cs) { - case 1: - at91_set_pio_output(AT91_PIO_PORTA, 7, 1); - break; - case 0: - default: - at91_set_pio_output(AT91_PIO_PORTA, 14, 1); - break; - } -} -#endif /* CONFIG_ATMEL_SPI */ -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(bd_t *bd) -{ - at91_mci_hw_init(); - - return atmel_mci_init((void *)ATMEL_BASE_HSMCI0); -} -#endif - int board_early_init_f(void) { at91_seriald_hw_init(); @@ -268,14 +200,6 @@ int board_init(void) at91sam9x5ek_nand_hw_init(); #endif -#ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 4); -#endif - -#ifdef CONFIG_MACB - at91_macb_hw_init(); -#endif - #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) at91_uhp_hw_init(); #endif @@ -302,8 +226,6 @@ void at91_spl_board_init(void) at91_mci_hw_init(); #elif CONFIG_SYS_USE_NANDFLASH at91sam9x5ek_nand_hw_init(); -#elif CONFIG_SYS_USE_SPIFLASH - at91_spi0_hw_init(1 << 4); #endif } -- cgit v0.10.2 From 9daf89cb682bfa2aac037b7fa425eab7ad67b9b9 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 14:51:56 +0800 Subject: board: at91sam9x5ek: Enable early debug UART Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 235b337..c661c77 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_LCD_INFO @@ -182,11 +183,22 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */ -int board_early_init_f(void) +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) { at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 7850b99..64707db 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -40,6 +40,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 5990778..ddeeeef 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -40,6 +40,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 816fe69..a26b38f 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -40,6 +40,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 8574525..75d25d8 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -40,6 +40,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y -- cgit v0.10.2 From 0ab5433da27005d50e186618eef5c91a81cd300d Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 14:54:51 +0800 Subject: configs: at91sam9n12ek: Update for DT and DM support Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Because the limitation of internal SRAM size, the SPL with driver model can't be supported, disable the SPL option. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 58da2d2..e3f9cbb 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -133,6 +133,7 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD */ /* SPI chip select control */ +#ifndef CONFIG_DM_SPI #ifdef CONFIG_ATMEL_SPI #include int spi_cs_is_valid(unsigned int bus, unsigned int cs) @@ -164,6 +165,7 @@ void spi_cs_deactivate(struct spi_slave *slave) } } #endif /* CONFIG_ATMEL_SPI */ +#endif #ifdef CONFIG_GENERIC_ATMEL_MCI int board_mmc_init(bd_t *bd) diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index ef9250b..abb0726 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -19,9 +21,24 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index db88973..1b420e6 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -1,17 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y @@ -25,9 +21,24 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 4e5d102..9048b14 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -1,18 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y @@ -26,9 +21,24 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index dd49f4e..e7b9ad2 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -28,14 +28,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT -/* general purpose I/O */ -#define CONFIG_AT91_GPIO - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - /* LCD */ #define LCD_BPP LCD_COLOR16 #define LCD_OUTPUT_BPP 24 @@ -45,7 +37,6 @@ #define CONFIG_ATMEL_HLCD #define CONFIG_ATMEL_LCD_RGB565 - /* * BOOTP options */ @@ -69,14 +60,11 @@ * that address while providing maximum stack area below. */ # define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE) + (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) /* DataFlash */ #ifdef CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_3 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 #endif /* NAND flash */ @@ -115,11 +103,6 @@ "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" -/* MMC */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - /* Ethernet */ #define CONFIG_KS8851_MLL #define CONFIG_KS8851_MLL_BASEADDR 0x30000000 /* use NCS2 */ @@ -156,7 +139,7 @@ /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET 0x120000 #define CONFIG_ENV_OFFSET_REDUND 0x100000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ #define CONFIG_BOOTCOMMAND \ -- cgit v0.10.2 From adc6b2863e49c6140932d4d8f36ee2cacc157728 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 14:54:52 +0800 Subject: board: at91sam9n12ek: Clean up code Since the introduction of the pinctrl and clk driver and the device tree files, remove unneeded related code from the board file. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index e3f9cbb..02b7790 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #ifdef CONFIG_LCD_INFO @@ -132,50 +131,6 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */ -/* SPI chip select control */ -#ifndef CONFIG_DM_SPI -#ifdef CONFIG_ATMEL_SPI -#include -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < 2; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - switch (slave->cs) { - case 0: - at91_set_pio_output(AT91_PIO_PORTA, 14, 0); - break; - case 1: - at91_set_pio_output(AT91_PIO_PORTA, 7, 0); - break; - } -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - switch (slave->cs) { - case 0: - at91_set_pio_output(AT91_PIO_PORTA, 14, 1); - break; - case 1: - at91_set_pio_output(AT91_PIO_PORTA, 7, 1); - break; - } -} -#endif /* CONFIG_ATMEL_SPI */ -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(bd_t *bd) -{ - at91_mci_hw_init(); - - return atmel_mci_init((void *)ATMEL_BASE_HSMCI0); -} -#endif - #ifdef CONFIG_KS8851_MLL void at91sam9n12ek_ks8851_hw_init(void) { @@ -209,10 +164,6 @@ void at91sam9n12ek_usb_hw_init(void) int board_early_init_f(void) { - at91_periph_clk_enable(ATMEL_ID_PIOAB); - at91_periph_clk_enable(ATMEL_ID_PIOCD); - - at91_seriald_hw_init(); return 0; } @@ -225,10 +176,6 @@ int board_init(void) at91sam9n12ek_nand_hw_init(); #endif -#ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 0); -#endif - #ifdef CONFIG_LCD at91_lcd_hw_init(); #endif -- cgit v0.10.2 From c1868adf6444e8fb600575affb634cad2f2ff8f5 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 14:54:53 +0800 Subject: board: at91sam9n12ek: Enable early debug UART Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 02b7790..1105428 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -162,10 +163,22 @@ void at91sam9n12ek_usb_hw_init(void) } #endif +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index abb0726..e7e8a01 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -35,6 +35,12 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index 1b420e6..e626805 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -35,6 +35,12 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 9048b14..a5abcd1 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -35,6 +35,12 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y -- cgit v0.10.2 From 59b37122b10b1d5d1d8c2b6833cc1075e7275892 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:15:48 +0800 Subject: configs: at91sam9m10g45ek: Update to support DM/DT Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Because the limitation of internal SRAM size, the SPL with driver model can't be supported, disable the SPL option. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9m10g45ek/Makefile b/board/atmel/at91sam9m10g45ek/Makefile index e5448ec..55cd946 100644 --- a/board/atmel/at91sam9m10g45ek/Makefile +++ b/board/atmel/at91sam9m10g45ek/Makefile @@ -10,4 +10,4 @@ # obj-y += at91sam9m10g45ek.o -obj-y += led.o +obj-(CONFIG_AT91_LED) += led.o diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index 342fc8a..b093340 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -1,19 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9M10G45EK=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set @@ -29,7 +23,23 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index 7164d82..e8324e7 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -1,17 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9M10G45EK=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set @@ -27,7 +23,23 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index a62b70b..010ebdb 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -30,13 +30,6 @@ /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS /* LCD */ #define LCD_BPP LCD_COLOR8 @@ -49,12 +42,6 @@ /* board specific(not enough SRAM) */ #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 -/* LED */ -#define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ -#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ - - /* * BOOTP options */ @@ -75,7 +62,7 @@ #define CONFIG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -92,24 +79,10 @@ #endif -/* MMC */ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - /* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R #define CONFIG_AT91_WANTS_COMMON_PHY -/* USB */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ATMEL -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 - #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE @@ -118,7 +91,7 @@ #ifdef CONFIG_SYS_USE_NANDFLASH /* bootstrap + u-boot + env in nandflash */ #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET 0x120000 #define CONFIG_ENV_OFFSET_REDUND 0x100000 #define CONFIG_ENV_SIZE 0x20000 -- cgit v0.10.2 From e95a29e4e5091c01afdfc7754d3d2e3d874abffc Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:15:49 +0800 Subject: board: at91sam9m10g45ek: Clean up code Since the introduction of the pinctrl and clk drivers and the device tree files, remove unneeded hard coded related code from the board file. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 6871916..2e8ea05 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -17,11 +17,6 @@ #include #include #include -#include -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include -#endif -#include DECLARE_GLOBAL_DATA_PTR; @@ -149,39 +144,6 @@ static void at91sam9m10g45ek_usb_hw_init(void) } #endif -#ifdef CONFIG_MACB -static void at91sam9m10g45ek_macb_hw_init(void) -{ - struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - - at91_periph_clk_enable(ATMEL_ID_EMAC); - - /* - * Disable pull-up on: - * RXDV (PA15) => PHY normal mode (not Test mode) - * ERX0 (PA12) => PHY ADDR0 - * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA12) | - pin_to_mask(AT91_PIN_PA13), - &pioa->pudr); - - at91_phy_reset(); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA12) | - pin_to_mask(AT91_PIN_PA13), - &pioa->puer); - - /* And the pins. */ - at91_macb_hw_init(); -} -#endif - #ifdef CONFIG_LCD vidinfo_t panel_info = { @@ -280,18 +242,8 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(bd_t *bis) -{ - at91_mci_hw_init(); - - return atmel_mci_init((void *)ATMEL_BASE_MCI0); -} -#endif - int board_early_init_f(void) { - at91_seriald_hw_init(); return 0; } @@ -313,15 +265,6 @@ int board_init(void) #ifdef CONFIG_CMD_USB at91sam9m10g45ek_usb_hw_init(); #endif -#ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); -#endif -#ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 4); -#endif -#ifdef CONFIG_MACB - at91sam9m10g45ek_macb_hw_init(); -#endif #ifdef CONFIG_LCD at91sam9m10g45ek_lcd_hw_init(); #endif @@ -340,48 +283,3 @@ void reset_phy(void) { } #endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); -#endif - return rc; -} - -/* SPI chip select control */ -#ifdef CONFIG_ATMEL_SPI -#include - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < 2; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - switch(slave->cs) { - case 1: - at91_set_gpio_output(AT91_PIN_PB18, 0); - break; - case 0: - default: - at91_set_gpio_output(AT91_PIN_PB3, 0); - break; - } -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - switch(slave->cs) { - case 1: - at91_set_gpio_output(AT91_PIN_PB18, 1); - break; - case 0: - default: - at91_set_gpio_output(AT91_PIN_PB3, 1); - break; - } -} -#endif /* CONFIG_ATMEL_SPI */ -- cgit v0.10.2 From 6a991af2d1ba386c1be95af084bf51a250ed5fea Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:15:50 +0800 Subject: board: at91sam9m10g45ek: Enable early debug UART Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 2e8ea05..d3bc5c6 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -242,10 +243,22 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index b093340..18b6ddf7 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -37,6 +37,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index e8324e7..eda54a4 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -37,6 +37,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_DM_USB=y -- cgit v0.10.2 From 83f1c2ef30072c0672bc81cef9e7ee557c7ee61b Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:18:47 +0800 Subject: configs: at91sam9260ek/9g20ek: Update for DT and DM Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9260ek/Makefile b/board/atmel/at91sam9260ek/Makefile index c6edbee..07c6184 100644 --- a/board/atmel/at91sam9260ek/Makefile +++ b/board/atmel/at91sam9260ek/Makefile @@ -10,5 +10,5 @@ # obj-y += at91sam9260ek.o -obj-y += led.o +obj-$(CONFIG_AT91_LED) += led.o obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index e00c4c4..6d34e21 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,7 +19,18 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y # CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index 7b81775..85f01f3 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,7 +19,18 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y # CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index ca71891..d9a7a48 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,7 +19,18 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y # CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index 67c8232..ef7bd40 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -18,6 +20,20 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index 6d2bfa1..398be7e 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek_2mmc" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -18,6 +20,20 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index 5bb0cb2..b810573 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,7 +19,18 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y # CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index fb6a0ac..18e2a17 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,7 +19,18 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y # CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index 79ec2e4..daa41dc 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,7 +19,18 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y # CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index e29b3cd..e38b718 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,7 +19,18 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y # CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index 2e32ca8..bc7eb03 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,7 +19,18 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y # CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index 2ef459b..7e59335 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set @@ -17,7 +19,18 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y # CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 379f234..48d7f6a 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -45,19 +45,6 @@ /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* LED */ -#define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PA9 /* this is the power led */ -#define CONFIG_GREEN_LED AT91_PIN_PA6 /* this is the user led */ - /* * BOOTP options @@ -87,10 +74,10 @@ */ #ifdef CONFIG_AT91SAM9XE # define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE) + (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #else # define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) + (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif /* @@ -142,18 +129,6 @@ #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 #endif -/* MMC */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - -/* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 -#define CONFIG_AT91_WANTS_COMMON_PHY - /* USB */ #define CONFIG_USB_ATMEL #define CONFIG_USB_ATMEL_CLK_SEL_PLLB @@ -200,7 +175,7 @@ /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET 0x120000 #define CONFIG_ENV_OFFSET_REDUND 0x100000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" -- cgit v0.10.2 From c97c2eb1fe4e18fbf6c81e250953b0cbec4fb154 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:18:48 +0800 Subject: board: at91sam9260ek: Clean up code Since the introduction of the pinctrl and clk drivers and the device tree files, remove unneeded hard coded related code from the board file. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 98193bf..e28242f 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -13,12 +13,6 @@ #include #include #include -#include - -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -# include -#endif -#include DECLARE_GLOBAL_DATA_PTR; @@ -67,63 +61,8 @@ static void at91sam9260ek_nand_hw_init(void) } #endif -#ifdef CONFIG_MACB -static void at91sam9260ek_macb_hw_init(void) -{ - struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - - at91_periph_clk_enable(ATMEL_ID_EMAC0); - - /* - * Disable pull-up on: - * RXDV (PA17) => PHY normal mode (not Test mode) - * ERX0 (PA14) => PHY ADDR0 - * ERX1 (PA15) => PHY ADDR1 - * ERX2 (PA25) => PHY ADDR2 - * ERX3 (PA26) => PHY ADDR3 - * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - &pioa->pudr); - - at91_phy_reset(); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - &pioa->puer); - - /* Initialize EMAC=MACB hardware */ - at91_macb_hw_init(); -} -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(bd_t *bd) -{ - at91_mci_hw_init(); - - return atmel_mci_init((void *)ATMEL_BASE_MCI); -} -#endif - int board_early_init_f(void) { - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - return 0; } @@ -132,16 +71,12 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9260ek_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH at91_spi0_hw_init((1 << 0) | (1 << 1)); #endif -#ifdef CONFIG_MACB - at91sam9260ek_macb_hw_init(); -#endif return 0; } @@ -159,12 +94,3 @@ void reset_phy(void) { } #endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); -#endif - return rc; -} -- cgit v0.10.2 From 2510be1d21fdfb389cf4a528fd72838aedf616d3 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:18:49 +0800 Subject: board: at91sam9260ek/9g20ek: Enable early debug UART Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index e28242f..b087fce 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -61,10 +62,22 @@ static void at91sam9260ek_nand_hw_init(void) } #endif +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index 6d34e21..cc3f0a8 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -31,6 +31,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index 85f01f3..cb621df 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -31,6 +31,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index d9a7a48..20d3565 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -31,6 +31,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index ef7bd40..18e88a7 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -33,6 +33,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index 398be7e..fb0d87a 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -33,6 +33,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index b810573..27c1c10 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -31,6 +31,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index 18e2a17..1826e6c 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -31,6 +31,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index daa41dc..1ac8863 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -31,6 +31,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index e38b718..80673d2 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -31,6 +31,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index bc7eb03..8922065 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -31,6 +31,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index 7e59335..9c28a59 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -31,6 +31,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_USB_STORAGE=y -- cgit v0.10.2 From 2011dca2c1d19fd561c77d3e851247444c3b11e1 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:28:27 +0800 Subject: configs: at91sam9rlek: Update for DT and DM support Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9rlek/Makefile b/board/atmel/at91sam9rlek/Makefile index 51daf8d..7acfee5 100644 --- a/board/atmel/at91sam9rlek/Makefile +++ b/board/atmel/at91sam9rlek/Makefile @@ -10,5 +10,5 @@ # obj-y += at91sam9rlek.o -obj-y += led.o +obj-$(CONFIG_AT91_LED) += led.o obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index 49e1353..24fbfe6 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -20,5 +22,17 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index 483d9b6..a46deac 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -20,5 +22,17 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index d7f2d7f..b6400d0 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -20,5 +22,17 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 31a7cb1..7dcf791 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -29,18 +29,11 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_ATMEL_LEGACY -#define CONFIG_AT91_GPIO 1 -#define CONFIG_AT91_GPIO_PULLUP 1 /* * Hardware drivers */ -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - /* LCD */ #define LCD_BPP LCD_COLOR8 #define CONFIG_LCD_LOGO 1 @@ -52,13 +45,6 @@ /* Let board_init_f handle the framebuffer allocation */ #undef CONFIG_FB_ADDR -/* LED */ -#define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PD14 /* this is the power led */ -#define CONFIG_GREEN_LED AT91_PIN_PD15 /* this is the user1 led */ -#define CONFIG_YELLOW_LED AT91_PIN_PD16 /* this is the user2 led */ - - /* * Command line configuration. */ @@ -71,7 +57,7 @@ #define CONFIG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE) + (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI @@ -97,12 +83,6 @@ #endif -/* MMC */ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - /* Ethernet - not present */ /* USB - not supported */ @@ -130,7 +110,7 @@ /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET 0x120000 #define CONFIG_ENV_OFFSET_REDUND 0x100000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x600000; " \ -- cgit v0.10.2 From 104c752f8409d969274810a64712b5c27721299b Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:28:28 +0800 Subject: board: at91sam9rlek: Clean up code Since the introduction of the pinctrl and clk drivers and the device tree files, remove unneeded hard coded related code from the board file. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 994f246..0c4d517 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -18,10 +18,6 @@ #include #include -#include -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include -#endif DECLARE_GLOBAL_DATA_PTR; @@ -159,22 +155,8 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(bd_t *bis) -{ - at91_mci_hw_init(); - - return atmel_mci_init((void *)ATMEL_BASE_MCI); -} -#endif - int board_early_init_f(void) { - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - return 0; } @@ -185,7 +167,6 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9rlek_nand_hw_init(); #endif -- cgit v0.10.2 From 84a9b80dba6d1206814f4b3ff72ce1ba49004dd5 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:28:29 +0800 Subject: board: at91sam9rlek: Enable early debug UART Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 0c4d517..0b603ed 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -155,10 +156,22 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index 24fbfe6..d4abb2a 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -34,5 +34,11 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_LCD=y diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index a46deac..9a40c41 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -34,5 +34,11 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_LCD=y diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index b6400d0..d68b562 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -34,5 +34,11 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_LCD=y -- cgit v0.10.2 From 0b8908f9c3b8af7e1619e0f2190ccc5d308f0347 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:31:00 +0800 Subject: configs: at91sam9263ek: Update for DT and DM support Update the configuration files to support the device tree and driver model. The device clock and pins configuration are handled by the clock and the pinctrl drivers respectively. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile index 7b31f18..f3cd9d5 100644 --- a/board/atmel/at91sam9263ek/Makefile +++ b/board/atmel/at91sam9263ek/Makefile @@ -10,5 +10,5 @@ # obj-y += at91sam9263ek.o -obj-y += led.o +obj-$(CONFIG_AT91_LED) += led.o obj-$(CONFIG_HAS_DATAFLASH) += partition.o diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index 6605a0e..701a49b 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -21,7 +23,21 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index 6605a0e..701a49b 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -21,7 +23,21 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index 9c6bab9..951f08d 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -21,7 +23,21 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 5a4324f..4f8d19b 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -21,8 +23,22 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 78ce6bd..a39d096 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -21,8 +23,22 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 663c193..e45e4db 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -45,13 +45,6 @@ * Hardware drivers */ #define CONFIG_ATMEL_LEGACY -#define CONFIG_AT91_GPIO 1 -#define CONFIG_AT91_GPIO_PULLUP 1 - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS /* LCD */ #define LCD_BPP LCD_COLOR8 @@ -62,13 +55,6 @@ #define CONFIG_ATMEL_LCD 1 #define CONFIG_ATMEL_LCD_BGR555 1 -/* LED */ -#define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ -#define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ -#define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ - - /* * BOOTP options */ @@ -88,7 +74,7 @@ #define CONFIG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) + (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI @@ -99,11 +85,6 @@ #define DATAFLASH_TCSS (0x1a << 16) #define DATAFLASH_TCHS (0x1 << 24) -/* MMC */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - /* NOR flash, if populated */ #ifdef CONFIG_SYS_USE_NORFLASH #define CONFIG_SYS_FLASH_CFI 1 @@ -249,9 +230,6 @@ #endif /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R 1 #define CONFIG_AT91_WANTS_COMMON_PHY @@ -287,7 +265,7 @@ /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET 0x120000 #define CONFIG_ENV_OFFSET_REDUND 0x100000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" -- cgit v0.10.2 From bbd76227dc37377c170b6ab26ae6e594906a323f Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:31:01 +0800 Subject: board: at91sam9263ek: Clean up code Because the introduction of the pinctrl and clk drivers and the device tree files, remove unneeded hard coded related code from the board file. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index e4e32f6..2aafafe 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -19,11 +19,6 @@ #include #include #include -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include -#endif -#include -#include DECLARE_GLOBAL_DATA_PTR; @@ -77,34 +72,6 @@ static void at91sam9263ek_nand_hw_init(void) } #endif -#ifdef CONFIG_MACB -static void at91sam9263ek_macb_hw_init(void) -{ - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - - at91_periph_clk_enable(ATMEL_ID_EMAC); - - /* - * Disable pull-up on: - * RXDV (PC25) => PHY normal mode (not Test mode) - * ERX0 (PE25) => PHY ADDR0 - * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(1 << 25, &pio->pioc.pudr); - writel((1 << 25) | (1 <<26), &pio->pioe.pudr); - - at91_phy_reset(); - - /* Re-enable pull-up */ - writel(1 << 25, &pio->pioc.puer); - writel((1 << 25) | (1 <<26), &pio->pioe.puer); - - at91_macb_hw_init(); -} -#endif - #ifdef CONFIG_LCD vidinfo_t panel_info = { .vl_col = 240, @@ -209,22 +176,8 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(bd_t *bd) -{ - at91_mci_hw_init(); - - return atmel_mci_init((void *)ATMEL_BASE_MCI1); -} -#endif - int board_early_init_f(void) { - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOCDE); - - at91_seriald_hw_init(); return 0; } @@ -242,9 +195,6 @@ int board_init(void) at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */ at91_spi0_hw_init(1 << 0); #endif -#ifdef CONFIG_MACB - at91sam9263ek_macb_hw_init(); -#endif #ifdef CONFIG_USB_OHCI_NEW at91_uhp_hw_init(); #endif @@ -267,12 +217,3 @@ void reset_phy(void) { } #endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00); -#endif - return rc; -} -- cgit v0.10.2 From eaa59b3404cdcfc190810d5083c164ac18eb8ab7 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 18 Apr 2017 15:31:02 +0800 Subject: board: at91sam9263ek: Enable early debug UART Enable the early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 2aafafe..3de9783 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -176,10 +177,22 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index 701a49b..02e9114 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -36,6 +36,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index 701a49b..02e9114 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -36,6 +36,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index 951f08d..2ddcf2b 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -36,6 +36,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 4f8d19b..21480c5 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -36,6 +36,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index a39d096..824c366 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -36,6 +36,12 @@ CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y -- cgit v0.10.2 From d52063b84f422caa2aad15fc981299ffd843e910 Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Mon, 24 Apr 2017 11:51:26 +0200 Subject: scsi: dm: split scsi_scan() The DM version of scsi_scan() is becoming a bit long, it can be split: scsi_scan() iterates over the IDs and LUNs and for each id/lun pair calls do_scsi_scan_one() to do the work of: - detecting an attached drive - creating the associated block device if a drive is found. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass diff --git a/common/scsi.c b/common/scsi.c index d37222c..c456f5a 100644 --- a/common/scsi.c +++ b/common/scsi.c @@ -549,6 +549,52 @@ removable: * to the user if mode = 1 */ #if defined(CONFIG_DM_SCSI) +static int do_scsi_scan_one(struct udevice *dev, int id, int lun, int mode) +{ + int ret; + struct udevice *bdev; + struct blk_desc bd; + struct blk_desc *bdesc; + char str[10]; + + /* + * detect the scsi driver to get information about its geometry (block + * size, number of blocks) and other parameters (ids, type, ...) + */ + scsi_init_dev_desc_priv(&bd); + if (scsi_detect_dev(id, lun, &bd)) + return -ENODEV; + + /* + * Create only one block device and do detection + * to make sure that there won't be a lot of + * block devices created + */ + snprintf(str, sizeof(str), "id%dlun%d", id, lun); + ret = blk_create_devicef(dev, "scsi_blk", str, IF_TYPE_SCSI, -1, + bd.blksz, bd.blksz * bd.lba, &bdev); + if (ret) { + debug("Can't create device\n"); + return ret; + } + + bdesc = dev_get_uclass_platdata(bdev); + bdesc->target = id; + bdesc->lun = lun; + bdesc->removable = bd.removable; + bdesc->type = bd.type; + memcpy(&bdesc->vendor, &bd.vendor, sizeof(bd.vendor)); + memcpy(&bdesc->product, &bd.product, sizeof(bd.product)); + memcpy(&bdesc->revision, &bd.revision, sizeof(bd.revision)); + part_init(bdesc); + + if (mode == 1) { + printf(" Device %d: ", 0); + dev_print(bdesc); + } + return 0; +} + int scsi_scan(int mode) { unsigned char i, lun; @@ -576,59 +622,9 @@ int scsi_scan(int mode) /* Get controller platdata */ plat = dev_get_platdata(dev); - for (i = 0; i < plat->max_id; i++) { - for (lun = 0; lun < plat->max_lun; lun++) { - struct udevice *bdev; /* block device */ - /* block device description */ - struct blk_desc _bd; - struct blk_desc *bdesc; - char str[10]; - - scsi_init_dev_desc_priv(&_bd); - ret = scsi_detect_dev(i, lun, &_bd); - if (ret) - /* - * no device detected? - * check the next lun. - */ - continue; - - /* - * Create only one block device and do detection - * to make sure that there won't be a lot of - * block devices created - */ - snprintf(str, sizeof(str), "id%dlun%d", i, lun); - ret = blk_create_devicef(dev, "scsi_blk", - str, IF_TYPE_SCSI, - -1, - _bd.blksz, - _bd.blksz * _bd.lba, - &bdev); - if (ret) { - debug("Can't create device\n"); - return ret; - } - - bdesc = dev_get_uclass_platdata(bdev); - bdesc->target = i; - bdesc->lun = lun; - bdesc->removable = _bd.removable; - bdesc->type = _bd.type; - memcpy(&bdesc->vendor, &_bd.vendor, - sizeof(_bd.vendor)); - memcpy(&bdesc->product, &_bd.product, - sizeof(_bd.product)); - memcpy(&bdesc->revision, &_bd.revision, - sizeof(_bd.revision)); - part_init(bdesc); - - if (mode == 1) { - printf(" Device %d: ", 0); - dev_print(bdesc); - } /* if mode */ - } /* next LUN */ - } + for (i = 0; i < plat->max_id; i++) + for (lun = 0; lun < plat->max_lun; lun++) + do_scsi_scan_one(dev, i, lun, mode); } return 0; -- cgit v0.10.2 From 72e5016f878d142e925f0016cee4ee7cbf42ae5b Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Mon, 24 Apr 2017 11:51:27 +0200 Subject: drivers: phy: add generic PHY framework The PHY framework provides a set of APIs to control a PHY. This API is derived from the linux version of the generic PHY framework. Currently the API supports init(), deinit(), power_on, power_off() and reset(). The framework provides a way to get a reference to a phy from the device-tree. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass diff --git a/drivers/Kconfig b/drivers/Kconfig index a096dad..a5f24d7 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -54,6 +54,8 @@ source "drivers/pci/Kconfig" source "drivers/pcmcia/Kconfig" +source "drivers/phy/Kconfig" + source "drivers/phy/marvell/Kconfig" source "drivers/pinctrl/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 4a4b237..6916420 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM) += core/ obj-$(CONFIG_$(SPL_)CLK) += clk/ obj-$(CONFIG_$(SPL_)LED) += led/ +obj-$(CONFIG_$(SPL_)PHY) += phy/ obj-$(CONFIG_$(SPL_)PINCTRL) += pinctrl/ obj-$(CONFIG_$(SPL_)RAM) += ram/ diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig new file mode 100644 index 0000000..0a74920 --- /dev/null +++ b/drivers/phy/Kconfig @@ -0,0 +1,36 @@ + +menu "PHY Subsystem" + +config PHY + bool "PHY Core" + depends on DM + help + PHY support. + + This framework is designed to provide a generic interface for PHY + devices. PHY devices are dedicated hardware that handle the physical + layer of the protocols in the OSI model. + PHYs are commonly used for high speed interfaces such as Serial-ATA + or PCI express. + The API provides functions to initialize/deinitialize the + PHY, power on/off the PHY, and reset the PHY. It's meant to be as + compatible as possible with the equivalent framework found in the + linux kernel. + +config SPL_PHY + bool "PHY Core in SPL" + depends on DM + help + PHY support in SPL. + + This framework is designed to provide a generic interface for PHY + devices. PHY devices are dedicated hardware that handle the physical + layer of the protocols (https://en.wikipedia.org/wiki/OSI_model). + PHYs are commonly used for high speed interfaces such as Serial-ATA + or PCI express. + The API provides functions to initialize/deinitialize the + PHY, power on/off the PHY, and reset the PHY. It's meant to be as + compatible as possible with the equivalent framework found in the + linux kernel. + +endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile new file mode 100644 index 0000000..45f786a --- /dev/null +++ b/drivers/phy/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ +# Written by Jean-Jacques Hiblot +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c new file mode 100644 index 0000000..0d8bef7 --- /dev/null +++ b/drivers/phy/phy-uclass.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Written by Jean-Jacques Hiblot + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static inline struct phy_ops *phy_dev_ops(struct udevice *dev) +{ + return (struct phy_ops *)dev->driver->ops; +} + +static int generic_phy_xlate_offs_flags(struct phy *phy, + struct fdtdec_phandle_args *args) +{ + debug("%s(phy=%p)\n", __func__, phy); + + if (args->args_count > 1) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args_count) + phy->id = args->args[0]; + else + phy->id = 0; + + + return 0; +} + +int generic_phy_get_by_index(struct udevice *dev, int index, + struct phy *phy) +{ + struct fdtdec_phandle_args args; + struct phy_ops *ops; + int ret; + struct udevice *phydev; + + debug("%s(dev=%p, index=%d, phy=%p)\n", __func__, dev, index, phy); + + assert(phy); + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev), + "phys", "#phy-cells", 0, index, + &args); + if (ret) { + debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_of_offset(UCLASS_PHY, args.node, &phydev); + if (ret) { + debug("%s: uclass_get_device_by_of_offset failed: err=%d\n", + __func__, ret); + return ret; + } + + phy->dev = phydev; + + ops = phy_dev_ops(phydev); + + if (ops->of_xlate) + ret = ops->of_xlate(phy, &args); + else + ret = generic_phy_xlate_offs_flags(phy, &args); + if (ret) { + debug("of_xlate() failed: %d\n", ret); + goto err; + } + + return 0; + +err: + return ret; +} + +int generic_phy_get_by_name(struct udevice *dev, const char *phy_name, + struct phy *phy) +{ + int index; + + debug("%s(dev=%p, name=%s, phy=%p)\n", __func__, dev, phy_name, phy); + + index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev), + "phy-names", phy_name); + if (index < 0) { + debug("fdt_stringlist_search() failed: %d\n", index); + return index; + } + + return generic_phy_get_by_index(dev, index, phy); +} + +int generic_phy_init(struct phy *phy) +{ + struct phy_ops const *ops = phy_dev_ops(phy->dev); + + return ops->init ? ops->init(phy) : 0; +} + +int generic_phy_reset(struct phy *phy) +{ + struct phy_ops const *ops = phy_dev_ops(phy->dev); + + return ops->reset ? ops->reset(phy) : 0; +} + +int generic_phy_exit(struct phy *phy) +{ + struct phy_ops const *ops = phy_dev_ops(phy->dev); + + return ops->exit ? ops->exit(phy) : 0; +} + +int generic_phy_power_on(struct phy *phy) +{ + struct phy_ops const *ops = phy_dev_ops(phy->dev); + + return ops->power_on ? ops->power_on(phy) : 0; +} + +int generic_phy_power_off(struct phy *phy) +{ + struct phy_ops const *ops = phy_dev_ops(phy->dev); + + return ops->power_off ? ops->power_off(phy) : 0; +} + +UCLASS_DRIVER(phy) = { + .id = UCLASS_PHY, + .name = "phy", +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 4e7cc93..1f7e32c 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -56,6 +56,7 @@ enum uclass_id { UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ + UCLASS_PHY, /* Physical Layer (PHY) device */ UCLASS_PINCONFIG, /* Pin configuration node device */ UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */ UCLASS_PMIC, /* PMIC I/O device */ diff --git a/include/generic-phy.h b/include/generic-phy.h new file mode 100644 index 0000000..d8cf0c9 --- /dev/null +++ b/include/generic-phy.h @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Written by Jean-Jacques Hiblot + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __GENERIC_PHY_H +#define __GENERIC_PHY_H + + +/** + * struct phy - A handle to (allowing control of) a single phy port. + * + * Clients provide storage for phy handles. The content of the structure is + * managed solely by the PHY API and PHY drivers. A phy struct is + * initialized by "get"ing the phy struct. The phy struct is passed to all + * other phy APIs to identify which PHY port to operate upon. + * + * @dev: The device which implements the PHY port. + * @id: The PHY ID within the provider. + * + */ +struct phy { + struct udevice *dev; + unsigned long id; +}; + +/* + * struct udevice_ops - set of function pointers for phy operations + * @init: operation to be performed for initializing phy (optional) + * @exit: operation to be performed while exiting (optional) + * @reset: reset the phy (optional). + * @power_on: powering on the phy (optional) + * @power_off: powering off the phy (optional) + */ +struct phy_ops { + /** + * of_xlate - Translate a client's device-tree (OF) phy specifier. + * + * The PHY core calls this function as the first step in implementing + * a client's generic_phy_get_by_*() call. + * + * If this function pointer is set to NULL, the PHY core will use a + * default implementation, which assumes #phy-cells = <0> or + * #phy-cells = <1>, and in the later case that the DT cell + * contains a simple integer PHY port ID. + * + * @phy: The phy struct to hold the translation result. + * @args: The phy specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct phy *phy, + struct fdtdec_phandle_args *args); + + /** + * init - initialize the hardware. + * + * Hardware intialization should not be done in during probe() but + * should be implemented in this init() function. It could be starting + * PLL, taking a controller out of reset, routing, etc. This function + * is typically called only once per PHY port. + * If power_on() is not implemented, it must power up the phy. + * + * @phy: the PHY port to initialize + * @return 0 if OK, or a negative error code. + */ + int (*init)(struct phy *phy); + + /** + * exit - de-initialize the PHY device + * + * Hardware de-intialization should be done here. Every step done in + * init() should be undone here. + * This could be used to suspend the phy to reduce power consumption or + * to put the phy in a known condition before booting the OS (though it + * is NOT called automatically before booting the OS) + * If power_off() is not implemented, it must power down the phy. + * + * @phy: PHY port to be de-initialized + * @return 0 if OK, or a negative error code + */ + int (*exit)(struct phy *phy); + + /** + * reset - resets a PHY device without shutting down + * + * @phy: PHY port to be reset + * + * During runtime, the PHY may need to be reset in order to + * re-establish connection etc without being shut down or exit. + * + * @return 0 if OK, or a negative error code + */ + int (*reset)(struct phy *phy); + + /** + * power_on - power on a PHY device + * + * @phy: PHY port to be powered on + * + * During runtime, the PHY may need to be powered on or off several + * times. This function is used to power on the PHY. It relies on the + * setup done in init(). If init() is not implemented, it must take care + * of setting up the context (PLLs, ...) + * + * @return 0 if OK, or a negative error code + */ + int (*power_on)(struct phy *phy); + + /** + * power_off - power off a PHY device + * + * @phy: PHY port to be powered off + * + * During runtime, the PHY may need to be powered on or off several + * times. This function is used to power off the PHY. Except if + * init()/deinit() are not implemented, it must not de-initialize + * everything. + * + * @return 0 if OK, or a negative error code + */ + int (*power_off)(struct phy *phy); +}; + + +/** + * generic_phy_init() - initialize the PHY port + * + * @phy: the PHY port to initialize + * @return 0 if OK, or a negative error code + */ +int generic_phy_init(struct phy *phy); + +/** + * generic_phy_init() - de-initialize the PHY device + * + * @phy: PHY port to be de-initialized + * @return 0 if OK, or a negative error code + */ +int generic_phy_exit(struct phy *phy); + +/** + * generic_phy_reset() - resets a PHY device without shutting down + * + * @phy: PHY port to be reset + *@return 0 if OK, or a negative error code + */ +int generic_phy_reset(struct phy *phy); + +/** + * generic_phy_power_on() - power on a PHY device + * + * @phy: PHY port to be powered on + * @return 0 if OK, or a negative error code + */ +int generic_phy_power_on(struct phy *phy); + +/** + * generic_phy_power_off() - power off a PHY device + * + * @phy: PHY port to be powered off + * @return 0 if OK, or a negative error code + */ +int generic_phy_power_off(struct phy *phy); + + +/** + * generic_phy_get_by_index() - Get a PHY device by integer index. + * + * @user: the client device + * @index: The index in the list of available PHYs + * @phy: A pointer to the PHY port + * + * This looks up a PHY device for a client device based on its position in the + * list of the possible PHYs. + * + * example: + * usb1: usb_otg_ss@xxx { + * compatible = "xxx"; + * reg = ; + * . + * . + * phys = <&usb2_phy>, <&usb3_phy>; + * . + * . + * }; + * the USB2 phy can be accessed by passing index '0' and the USB3 phy can + * be accessed by passing index '1' + * + * @return 0 if OK, or a negative error code + */ +int generic_phy_get_by_index(struct udevice *user, int index, + struct phy *phy); + +/** + * generic_phy_get_by_name() - Get a PHY device by its name. + * + * @user: the client device + * @phy_name: The name of the PHY in the list of possible PHYs + * @phy: A pointer to the PHY port + * + * This looks up a PHY device for a client device in the + * list of the possible PHYs based on its name. + * + * example: + * usb1: usb_otg_ss@xxx { + * compatible = "xxx"; + * reg = ; + * . + * . + * phys = <&usb2_phy>, <&usb3_phy>; + * phy-names = "usb2phy", "usb3phy"; + * . + * . + * }; + * the USB3 phy can be accessed using "usb3phy", and USB2 by using "usb2phy" + * + * @return 0 if OK, or a negative error code + */ +int generic_phy_get_by_name(struct udevice *user, const char *phy_name, + struct phy *phy); + +#endif /*__GENERIC_PHY_H */ -- cgit v0.10.2 From 86322f5982206f431ee4678a74182859c249aac4 Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Mon, 24 Apr 2017 11:51:28 +0200 Subject: dm: test: Add tests for the generic PHY uclass Those tests check: - the ability for a phy-user to get a phy based on its name or its index - the ability of a phy device (provider) to manage multiple ports - the ability to perform operations on the phy (init,deinit,on,off) - the behavior of the uclass when optional operations are not implemented Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 094c5aa..9077a82 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -59,6 +59,23 @@ ping-add = <3>; }; + phy_provider0: gen_phy@0 { + compatible = "sandbox,phy"; + #phy-cells = <1>; + }; + + phy_provider1: gen_phy@1 { + compatible = "sandbox,phy"; + #phy-cells = <0>; + broken; + }; + + gen_phy_user: gen_phy_user { + compatible = "simple-bus"; + phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>; + phy-names = "phy1", "phy2", "phy3"; + }; + some-bus { #address-cells = <1>; #size-cells = <0>; diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 64bb923..95630fc 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -172,6 +172,8 @@ CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y +CONFIG_PHY=y +CONFIG_PHY_SANDBOX=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index fb98ab8..26183af 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -174,6 +174,8 @@ CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y +CONFIG_PHY=y +CONFIG_PHY_SANDBOX=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 9b7b1fe..9324353 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -178,6 +178,8 @@ CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y +CONFIG_PHY=y +CONFIG_PHY_SANDBOX=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 0a74920..75f459d 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -33,4 +33,12 @@ config SPL_PHY compatible as possible with the equivalent framework found in the linux kernel. +config PHY_SANDBOX + bool "Sandbox PHY support" + depends on SANDBOX + depends on PHY + help + This select a dummy sandbox PHY driver. It used only to implement + the unit tests for the phy framework + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 45f786a..fd037c3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -6,3 +6,4 @@ # obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o +obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c new file mode 100644 index 0000000..9ad820c --- /dev/null +++ b/drivers/phy/sandbox-phy.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Written by Jean-Jacques Hiblot + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct sandbox_phy_priv { + bool initialized; + bool on; + bool broken; +}; + +static int sandbox_phy_power_on(struct phy *phy) +{ + struct sandbox_phy_priv *priv = dev_get_priv(phy->dev); + + if (!priv->initialized) + return -EIO; + + if (priv->broken) + return -EIO; + + priv->on = true; + + return 0; +} + +static int sandbox_phy_power_off(struct phy *phy) +{ + struct sandbox_phy_priv *priv = dev_get_priv(phy->dev); + + if (!priv->initialized) + return -EIO; + + if (priv->broken) + return -EIO; + + /* + * for validation purpose, let's says that power off + * works only for PHY 0 + */ + if (phy->id) + return -EIO; + + priv->on = false; + + return 0; +} + +static int sandbox_phy_init(struct phy *phy) +{ + struct sandbox_phy_priv *priv = dev_get_priv(phy->dev); + + priv->initialized = true; + priv->on = true; + + return 0; +} + +static int sandbox_phy_exit(struct phy *phy) +{ + struct sandbox_phy_priv *priv = dev_get_priv(phy->dev); + + priv->initialized = false; + priv->on = false; + + return 0; +} + +static int sandbox_phy_probe(struct udevice *dev) +{ + struct sandbox_phy_priv *priv = dev_get_priv(dev); + + priv->initialized = false; + priv->on = false; + priv->broken = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "broken"); + + return 0; +} + +static struct phy_ops sandbox_phy_ops = { + .power_on = sandbox_phy_power_on, + .power_off = sandbox_phy_power_off, + .init = sandbox_phy_init, + .exit = sandbox_phy_exit, +}; + +static const struct udevice_id sandbox_phy_ids[] = { + { .compatible = "sandbox,phy" }, + { } +}; + +U_BOOT_DRIVER(phy_sandbox) = { + .name = "phy_sandbox", + .id = UCLASS_PHY, + .of_match = sandbox_phy_ids, + .ops = &sandbox_phy_ops, + .probe = sandbox_phy_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_phy_priv), +}; diff --git a/test/dm/Makefile b/test/dm/Makefile index b15f1d0..513c456 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_LED) += led.o obj-$(CONFIG_DM_MAILBOX) += mailbox.o obj-$(CONFIG_DM_MMC) += mmc.o obj-$(CONFIG_DM_PCI) += pci.o +obj-$(CONFIG_PHY) += phy.o obj-$(CONFIG_POWER_DOMAIN) += power-domain.o obj-$(CONFIG_DM_PWM) += pwm.o obj-$(CONFIG_RAM) += ram.o diff --git a/test/dm/phy.c b/test/dm/phy.c new file mode 100644 index 0000000..811045f --- /dev/null +++ b/test/dm/phy.c @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Written by Jean-Jacques Hiblot + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Base test of the phy uclass */ +static int dm_test_phy_base(struct unit_test_state *uts) +{ + struct udevice *dev; + struct phy phy1_method1; + struct phy phy1_method2; + struct phy phy2; + struct phy phy3; + struct udevice *parent; + + /* Get the device using the phy device*/ + ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, + "gen_phy_user", &parent)); + /* + * Get the same phy port in 2 different ways and compare. + */ + ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method1)) + ut_assertok(generic_phy_get_by_index(parent, 0, &phy1_method2)) + ut_asserteq(phy1_method1.id, phy1_method2.id); + + /* + * Get the second phy port. Check that the same phy provider (device) + * provides this 2nd phy port, but that the IDs are different + */ + ut_assertok(generic_phy_get_by_name(parent, "phy2", &phy2)) + ut_asserteq_ptr(phy1_method2.dev, phy2.dev); + ut_assert(phy1_method1.id != phy2.id); + + /* + * Get the third phy port. Check that the phy provider is different + */ + ut_assertok(generic_phy_get_by_name(parent, "phy3", &phy3)) + ut_assert(phy2.dev != phy3.dev); + + /* Try to get a non-existing phy */ + ut_asserteq(-ENODEV, uclass_get_device(UCLASS_PHY, 3, &dev)); + ut_assert(generic_phy_get_by_name(parent, "phy_not_existing", + &phy1_method1) < 0) + + return 0; +} +DM_TEST(dm_test_phy_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test of the phy uclass using the sandbox phy driver operations */ +static int dm_test_phy_ops(struct unit_test_state *uts) +{ + struct phy phy1; + struct phy phy2; + struct phy phy3; + struct udevice *parent; + + ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, + "gen_phy_user", &parent)); + + ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1)); + ut_assertok(generic_phy_get_by_name(parent, "phy2", &phy2)); + ut_assertok(generic_phy_get_by_name(parent, "phy3", &phy3)); + + /* test normal operations */ + ut_assertok(generic_phy_init(&phy1)); + ut_assertok(generic_phy_power_on(&phy1)); + ut_assertok(generic_phy_power_off(&phy1)); + + /* + * test operations after exit(). + * The sandbox phy driver does not allow it. + */ + ut_assertok(generic_phy_exit(&phy1)); + ut_assert(generic_phy_power_on(&phy1) != 0); + ut_assert(generic_phy_power_off(&phy1) != 0); + + /* + * test normal operations again (after re-init) + */ + ut_assertok(generic_phy_init(&phy1)); + ut_assertok(generic_phy_power_on(&phy1)); + ut_assertok(generic_phy_power_off(&phy1)); + + /* + * test calling unimplemented feature. + * The call is expected to succeed + */ + ut_assertok(generic_phy_reset(&phy1)); + + /* PHY2 has a known problem with power off */ + ut_assertok(generic_phy_init(&phy2)); + ut_assertok(generic_phy_power_on(&phy2)); + ut_assert(generic_phy_power_off(&phy2) == -EIO); + + /* PHY3 has a known problem with power off and power on*/ + ut_assertok(generic_phy_init(&phy3)); + ut_assert(generic_phy_power_off(&phy3) == -EIO); + ut_assert(generic_phy_power_off(&phy3) == -EIO); + + return 0; +} +DM_TEST(dm_test_phy_ops, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -- cgit v0.10.2 From 982082d9ce7365e2680639d3764ba0f09d82fa2a Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Mon, 24 Apr 2017 11:51:29 +0200 Subject: drivers: phy: add PIPE3 phy driver This phy is found on omap platforms with sata capabilities. Except for the part related to the DM and the PHY framework, the code is basically a copy paste from arch/arm/mach-omap2/pipe3-phy.c Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Tom Rini Reviewed-by: Simon Glass diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 75f459d..a91a694 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -41,4 +41,22 @@ config PHY_SANDBOX This select a dummy sandbox PHY driver. It used only to implement the unit tests for the phy framework +config PIPE3_PHY + bool "Support omap's PIPE3 PHY" + depends on PHY && ARCH_OMAP2 + help + Support for the omap PIPE3 phy for sata + + This PHY is found on omap devices supporting SATA such as dra7, am57x + and omap5 + +config SPL_PIPE3_PHY + bool "Support omap's PIPE3 PHY in SPL" + depends on SPL_PHY && ARCH_OMAP2 + help + Support for the omap PIPE3 phy for sata in SPL + + This PHY is found on omap devices supporting SATA such as dra7, am57x + and omap5 + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index fd037c3..6ce96d2 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o +obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c new file mode 100644 index 0000000..ed80f0f --- /dev/null +++ b/drivers/phy/ti-pipe3-phy.c @@ -0,0 +1,373 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Written by Jean-Jacques Hiblot + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* PLLCTRL Registers */ +#define PLL_STATUS 0x00000004 +#define PLL_GO 0x00000008 +#define PLL_CONFIGURATION1 0x0000000C +#define PLL_CONFIGURATION2 0x00000010 +#define PLL_CONFIGURATION3 0x00000014 +#define PLL_CONFIGURATION4 0x00000020 + +#define PLL_REGM_MASK 0x001FFE00 +#define PLL_REGM_SHIFT 9 +#define PLL_REGM_F_MASK 0x0003FFFF +#define PLL_REGM_F_SHIFT 0 +#define PLL_REGN_MASK 0x000001FE +#define PLL_REGN_SHIFT 1 +#define PLL_SELFREQDCO_MASK 0x0000000E +#define PLL_SELFREQDCO_SHIFT 1 +#define PLL_SD_MASK 0x0003FC00 +#define PLL_SD_SHIFT 10 +#define SET_PLL_GO 0x1 +#define PLL_TICOPWDN BIT(16) +#define PLL_LDOPWDN BIT(15) +#define PLL_LOCK 0x2 +#define PLL_IDLE 0x1 + +/* Software rest for the SATA PLL (in CTRL_CORE_SMA_SW_0 register)*/ +#define SATA_PLL_SOFT_RESET (1<<18) + +/* PHY POWER CONTROL Register */ +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE + +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 + +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 + + +#define PLL_IDLE_TIME 100 /* in milliseconds */ +#define PLL_LOCK_TIME 100 /* in milliseconds */ + +struct omap_pipe3 { + void __iomem *pll_ctrl_base; + void __iomem *power_reg; + void __iomem *pll_reset_reg; + struct pipe3_dpll_map *dpll_map; +}; + + +struct pipe3_dpll_params { + u16 m; + u8 n; + u8 freq:3; + u8 sd; + u32 mf; +}; + +struct pipe3_dpll_map { + unsigned long rate; + struct pipe3_dpll_params params; +}; + +static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) +{ + return readl(addr + offset); +} + +static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset, + u32 data) +{ + writel(data, addr + offset); +} + +static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 + *pipe3) +{ + u32 rate; + struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; + + rate = get_sys_clk_freq(); + + for (; dpll_map->rate; dpll_map++) { + if (rate == dpll_map->rate) + return &dpll_map->params; + } + + printf("%s: No DPLL configuration for %u Hz SYS CLK\n", + __func__, rate); + return NULL; +} + +static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3) +{ + u32 val; + int timeout = PLL_LOCK_TIME; + + do { + mdelay(1); + val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS); + if (val & PLL_LOCK) + break; + } while (--timeout); + + if (!(val & PLL_LOCK)) { + printf("%s: DPLL failed to lock\n", __func__); + return -EBUSY; + } + + return 0; +} + +static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3) +{ + u32 val; + struct pipe3_dpll_params *dpll_params; + + dpll_params = omap_pipe3_get_dpll_params(pipe3); + if (!dpll_params) { + printf("%s: Invalid DPLL parameters\n", __func__); + return -EINVAL; + } + + val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1); + val &= ~PLL_REGN_MASK; + val |= dpll_params->n << PLL_REGN_SHIFT; + omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val); + + val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2); + val &= ~PLL_SELFREQDCO_MASK; + val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; + omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val); + + val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1); + val &= ~PLL_REGM_MASK; + val |= dpll_params->m << PLL_REGM_SHIFT; + omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val); + + val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4); + val &= ~PLL_REGM_F_MASK; + val |= dpll_params->mf << PLL_REGM_F_SHIFT; + omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val); + + val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3); + val &= ~PLL_SD_MASK; + val |= dpll_params->sd << PLL_SD_SHIFT; + omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val); + + omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO); + + return omap_pipe3_wait_lock(pipe3); +} + +static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on) +{ + u32 val, rate; + + val = readl(pipe3->power_reg); + + rate = get_sys_clk_freq(); + rate = rate/1000000; + + if (on) { + val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + val |= rate << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; + } else { + val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + } + + writel(val, pipe3->power_reg); +} + +static int pipe3_init(struct phy *phy) +{ + int ret; + u32 val; + struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev); + + /* Program the DPLL only if not locked */ + val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS); + if (!(val & PLL_LOCK)) { + ret = omap_pipe3_dpll_program(pipe3); + if (ret) + return ret; + } else { + /* else just bring it out of IDLE mode */ + val = omap_pipe3_readl(pipe3->pll_ctrl_base, + PLL_CONFIGURATION2); + if (val & PLL_IDLE) { + val &= ~PLL_IDLE; + omap_pipe3_writel(pipe3->pll_ctrl_base, + PLL_CONFIGURATION2, val); + ret = omap_pipe3_wait_lock(pipe3); + if (ret) + return ret; + } + } + return 0; +} + +static int pipe3_power_on(struct phy *phy) +{ + struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev); + + /* Power up the PHY */ + omap_control_pipe3_power(pipe3, 1); + + return 0; +} + +static int pipe3_power_off(struct phy *phy) +{ + struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev); + + /* Power down the PHY */ + omap_control_pipe3_power(pipe3, 0); + + return 0; +} + +static int pipe3_exit(struct phy *phy) +{ + u32 val; + int timeout = PLL_IDLE_TIME; + struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev); + + pipe3_power_off(phy); + + /* Put DPLL in IDLE mode */ + val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2); + val |= PLL_IDLE; + omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val); + + /* wait for LDO and Oscillator to power down */ + do { + mdelay(1); + val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS); + if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) + break; + } while (--timeout); + + if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { + error("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n", + __func__, val); + return -EBUSY; + } + + val = readl(pipe3->pll_reset_reg); + writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg); + mdelay(1); + writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg); + return 0; +} + +static void *get_reg(struct udevice *dev, const char *name) +{ + struct udevice *syscon; + struct regmap *regmap; + const fdt32_t *cell; + int len, err; + void *base; + + err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, + name, &syscon); + if (err) { + error("unable to find syscon device for %s (%d)\n", + name, err); + return NULL; + } + + regmap = syscon_get_regmap(syscon); + if (IS_ERR(regmap)) { + error("unable to find regmap for %s (%ld)\n", + name, PTR_ERR(regmap)); + return NULL; + } + + cell = fdt_getprop(gd->fdt_blob, dev->of_offset, name, + &len); + if (len < 2*sizeof(fdt32_t)) { + error("offset not available for %s\n", name); + return NULL; + } + + base = regmap_get_range(regmap, 0); + if (!base) + return NULL; + + return fdtdec_get_number(cell + 1, 1) + base; +} + +static int pipe3_phy_probe(struct udevice *dev) +{ + fdt_addr_t addr; + fdt_size_t sz; + struct omap_pipe3 *pipe3 = dev_get_priv(dev); + + addr = dev_get_addr_size_index(dev, 2, &sz); + if (addr == FDT_ADDR_T_NONE) { + error("missing pll ctrl address\n"); + return -EINVAL; + } + + pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE); + if (!pipe3->pll_ctrl_base) { + error("unable to remap pll ctrl\n"); + return -EINVAL; + } + + pipe3->power_reg = get_reg(dev, "syscon-phy-power"); + if (!pipe3->power_reg) + return -EINVAL; + + pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset"); + if (!pipe3->pll_reset_reg) + return -EINVAL; + + pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev); + + return 0; +} + +static struct pipe3_dpll_map dpll_map_sata[] = { + {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ + {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ + {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ + {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ + {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ + {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ + { }, /* Terminator */ +}; + +static const struct udevice_id pipe3_phy_ids[] = { + { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata }, + { } +}; + +static struct phy_ops pipe3_phy_ops = { + .init = pipe3_init, + .power_on = pipe3_power_on, + .power_off = pipe3_power_off, + .exit = pipe3_exit, +}; + +U_BOOT_DRIVER(pipe3_phy) = { + .name = "pipe3_phy", + .id = UCLASS_PHY, + .of_match = pipe3_phy_ids, + .ops = &pipe3_phy_ops, + .probe = pipe3_phy_probe, + .priv_auto_alloc_size = sizeof(struct omap_pipe3), +}; -- cgit v0.10.2 From 33a5e2c5e7048136e242c08fd804136cdfda3501 Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Mon, 24 Apr 2017 11:51:30 +0200 Subject: dra7: dtsi: mark ocp2scp bus compatible with "simple-bus" This is needed to probe devices under that bus such as the SATA PHY. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Tom Rini Reviewed-by: Simon Glass diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi index 6305f57..9247314 100644 --- a/arch/arm/dts/omap5-u-boot.dtsi +++ b/arch/arm/dts/omap5-u-boot.dtsi @@ -10,6 +10,10 @@ /{ ocp { u-boot,dm-pre-reloc; + + ocp2scp@4a090000 { + compatible = "ti,omap-ocp2scp", "simple-bus"; + }; }; }; -- cgit v0.10.2 From 02a4b4297901e5bc2d478fab5b3bbfac3d1adeac Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Mon, 24 Apr 2017 11:51:31 +0200 Subject: drivers: block: dwc_ahci: Implement a driver for Synopsys DWC sata device Implement a sata driver for Synopsys DWC sata device based on U-boot driver model. Signed-off-by: Mugunthan V N Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Tom Rini Reviewed-by: Simon Glass diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 88e66e2..6cbe145 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -48,4 +48,14 @@ config SATA_CEVA ZynqMP. Support up to 2 external devices. Complient with SATA 3.1 and AHCI 1.3 specifications with hot-plug detect feature. + +config DWC_AHCI + bool "Enable Synopsys DWC AHCI driver support" + select SCSI_AHCI + select PHY + depends on DM_SCSI + help + Enable this driver to support Sata devices through + Synopsys DWC AHCI module. + endmenu diff --git a/drivers/block/Makefile b/drivers/block/Makefile index f415b33..d89c8b0 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -11,6 +11,7 @@ ifndef CONFIG_BLK obj-y += blk_legacy.o endif +obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o obj-$(CONFIG_AHCI) += ahci-uclass.o obj-$(CONFIG_DM_SCSI) += scsi-uclass.o obj-$(CONFIG_SCSI_AHCI) += ahci.o diff --git a/drivers/block/dwc_ahci.c b/drivers/block/dwc_ahci.c new file mode 100644 index 0000000..d5bb0b8 --- /dev/null +++ b/drivers/block/dwc_ahci.c @@ -0,0 +1,101 @@ +/* + * DWC SATA platform driver + * + * (C) Copyright 2016 + * Texas Instruments Incorporated, + * + * Author: Mugunthan V N + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct dwc_ahci_priv { + void *base; + void *wrapper_base; +}; + +static int dwc_ahci_ofdata_to_platdata(struct udevice *dev) +{ + struct dwc_ahci_priv *priv = dev_get_priv(dev); + struct scsi_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr; + + plat->max_id = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "max-id", + CONFIG_SYS_SCSI_MAX_SCSI_ID); + plat->max_lun = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "max-lun", CONFIG_SYS_SCSI_MAX_LUN); + + priv->base = map_physmem(dev_get_addr(dev), sizeof(void *), + MAP_NOCACHE); + + addr = dev_get_addr_index(dev, 1); + if (addr != FDT_ADDR_T_NONE) { + priv->wrapper_base = map_physmem(addr, sizeof(void *), + MAP_NOCACHE); + } else { + priv->wrapper_base = NULL; + } + + return 0; +} + +static int dwc_ahci_probe(struct udevice *dev) +{ + struct dwc_ahci_priv *priv = dev_get_priv(dev); + int ret; + struct phy phy; + + ret = generic_phy_get_by_name(dev, "sata-phy", &phy); + if (ret) { + error("can't get the phy from DT\n"); + return ret; + } + + ret = generic_phy_init(&phy); + if (ret) { + error("unable to initialize the sata phy\n"); + return ret; + } + + ret = generic_phy_power_on(&phy); + if (ret) { + error("unable to power on the sata phy\n"); + return ret; + } + + if (priv->wrapper_base) { + u32 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; + + /* Enable SATA module, No Idle, No Standby */ + writel(val, priv->wrapper_base + TI_SATA_SYSCONFIG); + } + + return ahci_init(priv->base); +} + +static const struct udevice_id dwc_ahci_ids[] = { + { .compatible = "snps,dwc-ahci" }, + { } +}; + +U_BOOT_DRIVER(dwc_ahci) = { + .name = "dwc_ahci", + .id = UCLASS_SCSI, + .of_match = dwc_ahci_ids, + .ofdata_to_platdata = dwc_ahci_ofdata_to_platdata, + .probe = dwc_ahci_probe, + .priv_auto_alloc_size = sizeof(struct dwc_ahci_priv), + .platdata_auto_alloc_size = sizeof(struct scsi_platdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; -- cgit v0.10.2 From 9d0c4decfeaa7e312f50e0debb677f60ad170f61 Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Mon, 24 Apr 2017 11:51:32 +0200 Subject: defconfig: dra7xx_evm: enable CONFIG_BLK and disk driver model for SCSI Enable disk driver model for dra7xx_evm as dwc_ahci supports driver model. As a consequence we must also enable CONFIG_BLK and CONFIG_DM_USB. Signed-off-by: Mugunthan V N Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Tom Rini Reviewed-by: Simon Glass Dropped CONFIG_SPL_PHY=y in sandbox_spl to fix build error: Signed-off-by: Simon Glass diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index b50a762..9f96f15 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -38,7 +38,13 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm" CONFIG_DM=y CONFIG_SPL_DM=y -# CONFIG_BLK is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_BLK=y +CONFIG_DM_SCSI=y +CONFIG_DWC_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -68,6 +74,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DRA7XX_INDEX=1 @@ -81,3 +88,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 +CONFIG_SPL_PHY=y +CONFIG_PIPE3_PHY=y +CONFIG_SPL_PIPE3_PHY=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 568c3f6..84dd26b 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -43,7 +43,12 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm" CONFIG_DM=y CONFIG_SPL_DM=y -# CONFIG_BLK is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_DM_SCSI=y +CONFIG_DWC_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -73,6 +78,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DRA7XX_INDEX=1 @@ -86,3 +92,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 +CONFIG_SPL_PHY=y +CONFIG_PIPE3_PHY=y +CONFIG_SPL_PIPE3_PHY=y -- cgit v0.10.2