From 4f0b8efa50a543efd407fb8b2e9ad0de49467a15 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Fri, 12 Aug 2016 17:57:05 +0800
Subject: clk: rk3288: add PWM clock get rate

This patch add clk_get_rate for PWM device.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index c07203d..bd71a96 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -695,6 +695,8 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
 	case PCLK_I2C4:
 	case PCLK_I2C5:
 		return gclk_rate;
+	case PCLK_PWM:
+		return PD_BUS_PCLK_HZ;
 	default:
 		return -ENOENT;
 	}
-- 
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