From 4c90234586833c0bb4a5d9d3f69a69c8ab09e01f Mon Sep 17 00:00:00 2001
From: Vladimir Zapolskiy <vz@mleia.com>
Date: Sun, 4 Oct 2015 23:18:45 +0100
Subject: lpc32xx: fix calculation of HCLK PLL output clock

Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
index 1ef8a36..f5e2103 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -54,12 +54,12 @@ unsigned int get_hclk_pll_rate(void)
 	if (fref > 27000000ULL || fref < 1000000ULL)
 		return 0;
 
-	fout = fref * m_div;
-	if (val & CLK_HCLK_PLL_FEEDBACK) {
-		fcco = fout;
+	fcco = fref * m_div;
+	fout = fcco;
+	if (val & CLK_HCLK_PLL_FEEDBACK)
+		fcco *= p_div;
+	else
 		do_div(fout, p_div);
-	} else
-		fcco = fout * p_div;
 
 	if (fcco > 320000000ULL || fcco < 156000000ULL)
 		return 0;
-- 
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