From af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 11 Nov 2015 17:58:34 +0800 Subject: pci/layerscape: add support for LS1043A PCIe LUT register access The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 82991d5..5ce916c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -50,6 +50,7 @@ #define CONFIG_SYS_FSL_CCSR_SCFG_LE #define CONFIG_SYS_FSL_ESDHC_LE #define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN @@ -119,6 +120,7 @@ #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_PEX_LUT_BE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d941437..f52815d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -60,6 +60,10 @@ #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x10000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 134061c..cd96604 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -78,6 +78,10 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x80000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC /* Device Configuration */ #define DCFG_BASE 0x01e00000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 5ed456e..8691906 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -23,6 +23,14 @@ #define scfg_out32(a, v) out_be32(a, v) #endif +#ifdef CONFIG_SYS_FSL_PEX_LUT_LE +#define pex_lut_in32(a) in_le32(a) +#define pex_lut_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) +#define pex_lut_in32(a) in_be32(a) +#define pex_lut_out32(a, v) out_be32(a, v) +#endif + struct cpu_type { char name[15]; u32 soc_ver; diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index c1e3627..58e88ae 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -11,8 +11,9 @@ #include #include #include -#ifdef CONFIG_FSL_LAYERSCAPE +#ifndef CONFIG_LS102XA #include +#include #endif #ifndef CONFIG_SYS_PCI_MEMORY_BUS @@ -57,11 +58,6 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C -/* LUT registers */ -#define PCIE_LUT_BASE 0x80000 -#define PCIE_LUT_LCTRL0 0x7F8 -#define PCIE_LUT_DBG 0x7FC - #define PCIE_DBI_RO_WR_EN 0x8bc #define PCIE_LINK_CAP 0x7c @@ -162,7 +158,7 @@ static int ls_pcie_link_state(struct ls_pcie *pcie) { u32 state; - state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & + state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & LTSSM_STATE_MASK; if (state < LTSSM_PCIE_L0) { debug("....PCIe link error. LTSSM=0x%02x.\n", state); @@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info) for (pf = 0; pf < PCIE_PF_NUM; pf++) { for (vf = 0; vf <= PCIE_VF_NUM; vf++) { +#ifndef CONFIG_LS102XA writel(PCIE_LCTRL0_VAL(pf, vf), pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif ls_pcie_ep_setup_bars(pcie->dbi); ls_pcie_ep_setup_atu(pcie, info); } } /* Disable CFG2 */ +#ifndef CONFIG_LS102XA writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); +#endif } else { ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); ls_pcie_ep_setup_atu(pcie, info); -- cgit v0.10.2