From 2d41046531fb2421f2dd3f43a16f3d2f6484dad2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 10 Oct 2014 07:30:12 -0600 Subject: x86: config: Enable dhcp on link The dhcp option is required to get bootp to work on the Chromebook Pixel, so enable it. Signed-off-by: Simon Glass diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 936be14..f03a768 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -297,6 +297,12 @@ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_TFTP_TSIZE +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME #define CONFIG_CMD_USB -- cgit v0.10.2 From 6ddc4fd82283056a65d61ef38398ffbd06fd3c7b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 10 Oct 2014 07:30:13 -0600 Subject: x86: Add device tree information for Chrome OS EC Add the required node describing how to find the EC on link. Signed-off-by: Simon Glass diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index 4a37dac..67ce52a 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -32,4 +32,22 @@ memory-map = <0xff800000 0x00800000>; }; }; + + lpc { + compatible = "intel,lpc"; + #address-cells = <1>; + #size-cells = <1>; + cros-ec@200 { + compatible = "google,cros-ec"; + reg = <0x204 1 0x200 1 0x880 0x80>; + + /* This describes the flash memory within the EC */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0xff>; + }; + }; + }; }; -- cgit v0.10.2 From ca42d3f7eeacd62ecd4c04ac2598a973b54d7c2d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 10 Oct 2014 07:30:14 -0600 Subject: x86: dts: Add device tree compatible string for Intel IPC Add this to the table so that it can be recognised. Signed-off-by: Simon Glass diff --git a/include/fdtdec.h b/include/fdtdec.h index 2590d30..3814f82 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -96,6 +96,7 @@ enum fdt_compat_id { COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ + COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 06d4542..65db739 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -72,6 +72,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"), COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), COMPAT(PARADE_PS8625, "parade,ps8625"), + COMPAT(COMPAT_INTEL_LPC, "intel,lpc"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- cgit v0.10.2 From f1269925f9f2797d5a98afb50990540754db8d1e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 10 Oct 2014 07:30:15 -0600 Subject: x86: cros_ec: Update LPC driver for new cros_ec header There was a minor rename of one of the defines, so update the driver. Signed-off-by: Simon Glass diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c index 0e02671..07624a1 100644 --- a/drivers/misc/cros_ec_lpc.c +++ b/drivers/misc/cros_ec_lpc.c @@ -54,7 +54,7 @@ int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, int csum; int i; - if (dout_len > EC_HOST_PARAM_SIZE) { + if (dout_len > EC_PROTO2_MAX_PARAM_SIZE) { debug("%s: Cannot send %d bytes\n", __func__, dout_len); return -1; } @@ -159,7 +159,7 @@ int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob) byte = 0xff; byte &= inb(EC_LPC_ADDR_HOST_CMD); byte &= inb(EC_LPC_ADDR_HOST_DATA); - for (i = 0; i < EC_HOST_PARAM_SIZE && (byte == 0xff); i++) + for (i = 0; i < EC_PROTO2_MAX_PARAM_SIZE && (byte == 0xff); i++) byte &= inb(EC_LPC_ADDR_HOST_PARAM + i); if (byte == 0xff) { debug("%s: CROS_EC device not found on LPC bus\n", -- cgit v0.10.2 From 14db950945cfd8dd05c60476696be08425acdc5a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 10 Oct 2014 07:30:16 -0600 Subject: x86: cros_ec: Enable cros_ec for link Add defines to enable the Chrome OS EC interface and set it up on init. Signed-off-by: Simon Glass diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile index 4f2ac89..27ebe78 100644 --- a/board/chromebook-x86/coreboot/Makefile +++ b/board/chromebook-x86/coreboot/Makefile @@ -12,4 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += coreboot_start.o +obj-y += coreboot_start.o coreboot.o diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c new file mode 100644 index 0000000..0240c34 --- /dev/null +++ b/board/chromebook-x86/coreboot/coreboot.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int arch_early_init_r(void) +{ + if (cros_ec_board_init()) + return -1; + + return 0; +} diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index f03a768..ce614c8 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -283,6 +283,11 @@ */ #define CONFIG_PCI +#define CONFIG_CROS_EC +#define CONFIG_CROS_EC_LPC +#define CONFIG_CMD_CROS_EC +#define CONFIG_ARCH_EARLY_INIT_R + /*----------------------------------------------------------------------- * USB configuration */ -- cgit v0.10.2 From e731707e4e5c186e6c677a8bb68008802c1b7666 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 10 Oct 2014 07:30:17 -0600 Subject: doc: Remove note about auto-complete not working with hush It does seem to work (tested on link), so update the docs. Signed-off-by: Simon Glass diff --git a/README b/README index 19abe20..6cf096c 100644 --- a/README +++ b/README @@ -2830,10 +2830,6 @@ CBFS (Coreboot Filesystem) support Enable auto completion of commands using TAB. - Note that this feature has NOT been implemented yet - for the "hush" shell. - - CONFIG_SYS_HUSH_PARSER Define this variable to enable the "hush" shell (from -- cgit v0.10.2 From 39c0b633c010b5c4dcb35b9bb73152a1b6f43ae2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 10 Oct 2014 07:30:18 -0600 Subject: x86: link: Tidy up the command lines options We may as well use hush. The auto-complete option was incorrect so this was not enabled. Also expand the command line size a little and go back to the default prompt since "boot>" doesn't seem any more useful. Signed-off-by: Simon Glass diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index ce614c8..f55b332 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -109,7 +109,8 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTOCOMPLETE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SUPPORT_VFAT /************************************************************ @@ -208,8 +209,7 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "boot > " -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + \ 16) -- cgit v0.10.2 From c67161c1f1965efc5934697f5947cf65a2ea0a62 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 10 Oct 2014 07:30:19 -0600 Subject: x86: config: link: Display the board model on the screen To get a display in U-Boot on link you must either build a coreboot that always sets it up, or use Esc-Refresh-Power to reset the machine. When we do have a display, it is nice to display the model at the top, so enable this option. Signed-off-by: Simon Glass diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index f55b332..5a006be 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -25,6 +25,7 @@ #define CONFIG_ZBOOT_32 #define CONFIG_PHYSMEM #define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_LMB #define CONFIG_OF_LIBFDT -- cgit v0.10.2 From c0561d14c5c0adb57bc84f071225a8e742c9a30b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 10 Oct 2014 07:30:20 -0600 Subject: x86: Enable FIT, ELF on coreboot Enable FIT support and the bootelf command. Also change the default load address to somewhere other than the normal load address of the kernel, to allow for decompression without overwriting the original file. Signed-off-by: Simon Glass diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 5a006be..200b744 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -40,6 +40,7 @@ #define CONFIG_BOOTSTAGE_USER_COUNT 60 #define CONFIG_LZO +#define CONFIG_FIT #undef CONFIG_ZLIB #undef CONFIG_GZIP @@ -194,6 +195,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_ZBOOT +#define CONFIG_CMD_ELF #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS \ @@ -219,7 +221,7 @@ #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x100000 +#define CONFIG_SYS_LOAD_ADDR 0x02000000 /*----------------------------------------------------------------------- * SDRAM Configuration -- cgit v0.10.2 From 8104f546296a8e1fc1dd6129041e22f508b314f9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 10 Oct 2014 07:30:21 -0600 Subject: net: Display the size when tftpboot finishes If we know the file size, display it after loading the file. Signed-off-by: Simon Glass diff --git a/net/tftp.c b/net/tftp.c index 966d1cf..0a2c533 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -299,6 +299,8 @@ static void tftp_complete(void) putc('#'); TftpNumchars++; } + puts(" "); + print_size(TftpTsize, ""); #endif time_start = get_timer(time_start); if (time_start > 0) { -- cgit v0.10.2