From 5fb0151697088e257e0190d414cc7b2e2793b485 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 15 Aug 2015 14:37:50 -0600
Subject: x86: baytrail: Support multiple microcode copies

Intel FSP has the capability to walk through the microcode blocks
which are passed as the TempRamInit() parameter from U-Boot and
finds the most appropriate microcode which is suitable for the cpu
on which it is running. Now we've seen several steppings for Intel
BayTrail series processors, adding those microcodes to the Intel
BayleyBay and MinnowMax board device tree files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 8f0e192..d646987 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -230,6 +230,12 @@
 		update@0 {
 #include "microcode/m0230671117.dtsi"
 		};
+		update@1 {
+#include "microcode/m0130673322.dtsi"
+		};
+		update@2 {
+#include "microcode/m0130679901.dtsi"
+		};
 	};
 
 };
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index daac24e..f4e0a35 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -256,6 +256,9 @@
 		update@0 {
 #include "microcode/m0130673322.dtsi"
 		};
+		update@1 {
+#include "microcode/m0130679901.dtsi"
+		};
 	};
 
 };
-- 
cgit v0.10.2