From 95c2fb371a2155925005d76dfc09c1c067aa912b Mon Sep 17 00:00:00 2001
From: Chander Kashyap <chander.kashyap@linaro.org>
Date: Fri, 2 Mar 2012 03:25:34 +0000
Subject: EXYNOS: Add structure for Exynos4 DMC

Add exynos4_dmc structure in dmc.h for exynos4 dram controllor(DMC).

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h
index debbe50..bd52d16 100644
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -2,6 +2,115 @@
 #define __DMC_H__
 
 #ifndef __ASSEMBLY__
+struct exynos4_dmc {
+	unsigned int concontrol;
+	unsigned int memcontrol;
+	unsigned int memconfig0;
+	unsigned int memconfig1;
+	unsigned int directcmd;
+	unsigned int prechconfig;
+	unsigned int phycontrol0;
+	unsigned int phycontrol1;
+	unsigned int phycontrol2;
+	unsigned int phycontrol3;
+	unsigned int pwrdnconfig;
+	unsigned char res1[0x4];
+	unsigned int timingref;
+	unsigned int timingrow;
+	unsigned int timingdata;
+	unsigned int timingpower;
+	unsigned int phystatus;
+	unsigned int phyzqcontrol;
+	unsigned int chip0status;
+	unsigned int chip1status;
+	unsigned int arefstatus;
+	unsigned int mrstatus;
+	unsigned int phytest0;
+	unsigned int phytest1;
+	unsigned int qoscontrol0;
+	unsigned int qosconfig0;
+	unsigned int qoscontrol1;
+	unsigned int qosconfig1;
+	unsigned int qoscontrol2;
+	unsigned int qosconfig2;
+	unsigned int qoscontrol3;
+	unsigned int qosconfig3;
+	unsigned int qoscontrol4;
+	unsigned int qosconfig4;
+	unsigned int qoscontrol5;
+	unsigned int qosconfig5;
+	unsigned int qoscontrol6;
+	unsigned int qosconfig6;
+	unsigned int qoscontrol7;
+	unsigned int qosconfig7;
+	unsigned int qoscontrol8;
+	unsigned int qosconfig8;
+	unsigned int qoscontrol9;
+	unsigned int qosconfig9;
+	unsigned int qoscontrol10;
+	unsigned int qosconfig10;
+	unsigned int qoscontrol11;
+	unsigned int qosconfig11;
+	unsigned int qoscontrol12;
+	unsigned int qosconfig12;
+	unsigned int qoscontrol13;
+	unsigned int qosconfig13;
+	unsigned int qoscontrol14;
+	unsigned int qosconfig14;
+	unsigned int qoscontrol15;
+	unsigned int qosconfig15;
+	unsigned int qostimeout0;
+	unsigned int qostimeout1;
+	unsigned char res2[0x8];
+	unsigned int ivcontrol;
+	unsigned char res3[0x8];
+	unsigned int perevconfig;
+	unsigned char res4[0xDF00];
+	unsigned int pmnc_ppc_a;
+	unsigned char res5[0xC];
+	unsigned int cntens_ppc_a;
+	unsigned char res6[0xC];
+	unsigned int cntenc_ppc_a;
+	unsigned char res7[0xC];
+	unsigned int intens_ppc_a;
+	unsigned char res8[0xC];
+	unsigned int intenc_ppc_a;
+	unsigned char res9[0xC];
+	unsigned int flag_ppc_a;
+	unsigned char res10[0xAC];
+	unsigned int ccnt_ppc_a;
+	unsigned char res11[0xC];
+	unsigned int pmcnt0_ppc_a;
+	unsigned char res12[0xC];
+	unsigned int pmcnt1_ppc_a;
+	unsigned char res13[0xC];
+	unsigned int pmcnt2_ppc_a;
+	unsigned char res14[0xC];
+	unsigned int pmcnt3_ppc_a;
+	unsigned char res15[0xEBC];
+	unsigned int pmnc_ppc_m;
+	unsigned char res16[0xC];
+	unsigned int cntens_ppc_m;
+	unsigned char res17[0xC];
+	unsigned int cntenc_ppc_m;
+	unsigned char res18[0xC];
+	unsigned int intens_ppc_m;
+	unsigned char res19[0xC];
+	unsigned int intenc_ppc_m;
+	unsigned char res20[0xC];
+	unsigned int flag_ppc_m;
+	unsigned char res21[0xAC];
+	unsigned int ccnt_ppc_m;
+	unsigned char res22[0xC];
+	unsigned int pmcnt0_ppc_m;
+	unsigned char res23[0xC];
+	unsigned int pmcnt1_ppc_m;
+	unsigned char res24[0xC];
+	unsigned int pmcnt2_ppc_m;
+	unsigned char res25[0xC];
+	unsigned int pmcnt3_ppc_m;
+};
+
 struct exynos5_dmc {
 	unsigned int concontrol;
 	unsigned int memcontrol;
-- 
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