From 7cbe638e41cd4cf199bfb7798fe572ddf3a39f0a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 14 Dec 2013 05:55:26 +0100 Subject: ARM: armv7: Make indirect vector addresses globl Make indirect vectors addresses global, so they can be replaced by various code that needs to do so. For example the MX6 PCI express driver needs to temporarily replace data abort handler when reading the config space. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Eric Nelson Cc: Fabio Estevam Cc: Stefano Babic diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 6c9b11a..5aac773 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -38,12 +38,19 @@ _irq: .word _irq _fiq: .word _fiq _pad: .word 0x12345678 /* now 16*4=64 */ #else +.globl _undefined_instruction _undefined_instruction: .word undefined_instruction +.globl _software_interrupt _software_interrupt: .word software_interrupt +.globl _prefetch_abort _prefetch_abort: .word prefetch_abort +.globl _data_abort _data_abort: .word data_abort +.globl _not_used _not_used: .word not_used +.globl _irq _irq: .word irq +.globl _fiq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ #endif /* CONFIG_SPL_BUILD */ -- cgit v0.10.2 From 798144928011ca3baca55b51c43d5e17fedbb4e0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 14 Dec 2013 06:27:26 +0100 Subject: ARM: mx6: Add PCI express clock configuration Split the SATA clock enabling function and add PCI express clock enabling function. The SATA clock enabling function starts up the 100MHz SATA reference PLL in ENET_PLL register, but the code can be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull this code into separate function. Moreover, add the PCIe clock enabling code. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Eric Nelson Cc: Fabio Estevam Cc: Stefano Babic Acked-by: Jagannadha Sutradharudu Teki diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 5617a41..61f71cf 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -412,17 +412,12 @@ u32 imx_get_fecclk(void) return decode_pll(PLL_ENET, MXC_HCLK); } -int enable_sata_clock(void) +static int enable_enet_pll(uint32_t en) { - u32 reg = 0; - s32 timeout = 100000; struct mxc_ccm_reg *const imx_ccm = (struct mxc_ccm_reg *) CCM_BASE_ADDR; - - /* Enable sata clock */ - reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ - reg |= MXC_CCM_CCGR5_SATA_MASK; - writel(reg, &imx_ccm->CCGR5); + s32 timeout = 100000; + u32 reg = 0; /* Enable PLLs */ reg = readl(&imx_ccm->analog_pll_enet); @@ -437,10 +432,70 @@ int enable_sata_clock(void) return -EIO; reg &= ~BM_ANADIG_PLL_SYS_BYPASS; writel(reg, &imx_ccm->analog_pll_enet); - reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; + reg |= en; writel(reg, &imx_ccm->analog_pll_enet); + return 0; +} - return 0 ; +static void ungate_sata_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable SATA clock. */ + setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); +} + +static void ungate_pcie_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable PCIe clock. */ + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); +} + +int enable_sata_clock(void) +{ + ungate_sata_clock(); + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); +} + +int enable_pcie_clock(void) +{ + struct anatop_regs *anatop_regs = + (struct anatop_regs *)ANATOP_BASE_ADDR; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* + * Here be dragons! + * + * The register ANATOP_MISC1 is not documented in the Freescale + * MX6RM. The register that is mapped in the ANATOP space and + * marked as ANATOP_MISC1 is actually documented in the PMU section + * of the datasheet as PMU_MISC1. + * + * Switch LVDS clock source to SATA (0xb), disable clock INPUT and + * enable clock OUTPUT. This is important for PCI express link that + * is clocked from the i.MX6. + */ +#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) +#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) +#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F + clrsetbits_le32(&anatop_regs->ana_misc1, + ANADIG_ANA_MISC1_LVDSCLK1_IBEN | + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); + + /* PCIe reference clock sourced from AXI. */ + clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); + + /* Party time! Ungate the clock to the PCIe. */ + ungate_sata_clock(); + ungate_pcie_clock(); + + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | + BM_ANADIG_PLL_ENET_ENABLE_PCIE); } unsigned int mxc_get_clock(enum mxc_clock clk) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index e31ba0a..1b4ded7 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -55,6 +55,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk); void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); +int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); -- cgit v0.10.2 From e9be4292e4f32bcdfb88c19407da281e36447498 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 14 Dec 2013 05:55:28 +0100 Subject: ARM: mx6: Add PCI express driver Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the PCIe block in RC mode only, the EP mode is NOT supported. The driver is tested with the Intel e1000 NIC driver. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Eric Nelson Cc: Fabio Estevam Cc: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index fe4675e..f9ee0d9 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -15,6 +15,33 @@ #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) #define IOMUXC_GPR1_OTG_ID_MASK (1<<13) +#define IOMUXC_GPR1_REF_SSP_EN (1 << 16) +#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) + +/* + * IOMUXC_GPR8 bit fields + */ +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25 + +/* + * IOMUXC_GPR12 bit fields + */ +#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) +#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) +#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) +#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) + /* * IOMUXC_GPR13 bit fields */ diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 6182a59..18458d3 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PCI) += pci.o pci_auto.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o obj-$(CONFIG_PCI_MSC01) += pci_msc01.o +obj-$(CONFIG_PCIE_IMX) += pcie_imx.o obj-$(CONFIG_FTPCI100) += pci_ftpci100.o obj-$(CONFIG_IXP_PCI) += pci_ixp.o obj-$(CONFIG_SH4_PCI) += pci_sh4.o diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c new file mode 100644 index 0000000..0a74867 --- /dev/null +++ b/drivers/pci/pcie_imx.c @@ -0,0 +1,565 @@ +/* + * Freescale i.MX6 PCI Express Root-Complex driver + * + * Copyright (C) 2013 Marek Vasut + * + * Based on upstream Linux kernel driver: + * pci-imx6.c: Sean Cross + * pcie-designware.c: Jingoo Han + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define MX6_DBI_ADDR 0x01ffc000 +#define MX6_DBI_SIZE 0x4000 +#define MX6_IO_ADDR 0x01000000 +#define MX6_IO_SIZE 0x100000 +#define MX6_MEM_ADDR 0x01100000 +#define MX6_MEM_SIZE 0xe00000 +#define MX6_ROOT_ADDR 0x01f00000 +#define MX6_ROOT_SIZE 0xfc000 + +/* PCIe Port Logic registers (memory-mapped) */ +#define PL_OFFSET 0x700 +#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) +#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29) + +#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) +#define PCIE_PHY_CTRL_DATA_LOC 0 +#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 +#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 +#define PCIE_PHY_CTRL_WR_LOC 18 +#define PCIE_PHY_CTRL_RD_LOC 19 + +#define PCIE_PHY_STAT (PL_OFFSET + 0x110) +#define PCIE_PHY_STAT_DATA_LOC 0 +#define PCIE_PHY_STAT_ACK_LOC 16 + +/* PHY registers (not memory-mapped) */ +#define PCIE_PHY_RX_ASIC_OUT 0x100D + +#define PHY_RX_OVRD_IN_LO 0x1005 +#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) +#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) + +/* iATU registers */ +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C + +/* + * PHY access functions + */ +static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) +{ + u32 val; + u32 max_iterations = 10; + u32 wait_counter = 0; + + do { + val = readl(dbi_base + PCIE_PHY_STAT); + val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; + wait_counter++; + + if (val == exp_val) + return 0; + + udelay(1); + } while (wait_counter < max_iterations); + + return -ETIMEDOUT; +} + +static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) +{ + u32 val; + int ret; + + val = addr << PCIE_PHY_CTRL_DATA_LOC; + writel(val, dbi_base + PCIE_PHY_CTRL); + + val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); + writel(val, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + val = addr << PCIE_PHY_CTRL_DATA_LOC; + writel(val, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + return 0; +} + +/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ +static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) +{ + u32 val, phy_ctl; + int ret; + + ret = pcie_phy_wait_ack(dbi_base, addr); + if (ret) + return ret; + + /* assert Read signal */ + phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; + writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + val = readl(dbi_base + PCIE_PHY_STAT); + *data = val & 0xffff; + + /* deassert Read signal */ + writel(0x00, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + return 0; +} + +static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) +{ + u32 var; + int ret; + + /* write addr */ + /* cap addr */ + ret = pcie_phy_wait_ack(dbi_base, addr); + if (ret) + return ret; + + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* capture data */ + var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); + writel(var, dbi_base + PCIE_PHY_CTRL); + + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + /* deassert cap data */ + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack de-assertion */ + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + /* assert wr signal */ + var = 0x1 << PCIE_PHY_CTRL_WR_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack */ + ret = pcie_phy_poll_ack(dbi_base, 1); + if (ret) + return ret; + + /* deassert wr signal */ + var = data << PCIE_PHY_CTRL_DATA_LOC; + writel(var, dbi_base + PCIE_PHY_CTRL); + + /* wait for ack de-assertion */ + ret = pcie_phy_poll_ack(dbi_base, 0); + if (ret) + return ret; + + writel(0x0, dbi_base + PCIE_PHY_CTRL); + + return 0; +} + +static int imx6_pcie_link_up(void) +{ + u32 rc, ltssm; + int rx_valid, temp; + + /* link is debug bit 36, debug register 1 starts at bit 32 */ + rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1); + if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) && + !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)) + return -EAGAIN; + + /* + * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. + * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). + * If (MAC/LTSSM.state == Recovery.RcvrLock) + * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition + * to gen2 is stuck + */ + pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid); + ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F; + + if (rx_valid & 0x01) + return 0; + + if (ltssm != 0x0d) + return 0; + + printf("transition to gen2 is stuck, reset PHY!\n"); + + pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); + temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); + pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); + + udelay(3000); + + pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp); + temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); + pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp); + + return 0; +} + +/* + * iATU region setup + */ +static int imx_pcie_regions_setup(void) +{ + /* + * i.MX6 defines 16MB in the AXI address map for PCIe. + * + * That address space excepted the pcie registers is + * split and defined into different regions by iATU, + * with sizes and offsets as follows: + * + * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO + * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM + * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers + */ + + /* CMD reg:I/O space, MEM space, and Bus Master Enable */ + setbits_le32(MX6_DBI_ADDR | PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ + setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION, + PCI_CLASS_BRIDGE_PCI << 16); + + /* Region #0 is used for Outbound CFG space access. */ + writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); + + writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE); + writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE); + writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT); + + writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); + writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET); + writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); + writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2); + + return 0; +} + +/* + * PCI Express accessors + */ +static uint32_t get_bus_address(pci_dev_t d, int where) +{ + uint32_t va_address; + + /* Reconfigure Region #0 */ + writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT); + + if (PCI_BUS(d) < 2) + writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1); + else + writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1); + + if (PCI_BUS(d) == 0) { + va_address = MX6_DBI_ADDR; + } else { + writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET); + va_address = MX6_IO_ADDR + SZ_16M - SZ_1M; + } + + va_address += (where & ~0x3); + + return va_address; +} + +static int imx_pcie_addr_valid(pci_dev_t d) +{ + if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1)) + return -EINVAL; + if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0)) + return -EINVAL; + return 0; +} + +/* + * Replace the original ARM DABT handler with a simple jump-back one. + * + * The problem here is that if we have a PCIe bridge attached to this PCIe + * controller, but no PCIe device is connected to the bridges' downstream + * port, the attempt to read/write from/to the config space will produce + * a DABT. This is a behavior of the controller and can not be disabled + * unfortuatelly. + * + * To work around the problem, we backup the current DABT handler address + * and replace it with our own DABT handler, which only bounces right back + * into the code. + */ +static void imx_pcie_fix_dabt_handler(bool set) +{ + extern uint32_t *_data_abort; + uint32_t *data_abort_addr = (uint32_t *)&_data_abort; + + static const uint32_t data_abort_bounce_handler = 0xe25ef004; + uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler; + + static uint32_t data_abort_backup; + + if (set) { + data_abort_backup = *data_abort_addr; + *data_abort_addr = data_abort_bounce_addr; + } else { + *data_abort_addr = data_abort_backup; + } +} + +static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d, + int where, u32 *val) +{ + uint32_t va_address; + int ret; + + ret = imx_pcie_addr_valid(d); + if (ret) { + *val = 0xffffffff; + return ret; + } + + va_address = get_bus_address(d, where); + + /* + * Read the PCIe config space. We must replace the DABT handler + * here in case we got data abort from the PCIe controller, see + * imx_pcie_fix_dabt_handler() description. Note that writing the + * "val" with valid value is also imperative here as in case we + * did got DABT, the val would contain random value. + */ + imx_pcie_fix_dabt_handler(true); + writel(0xffffffff, val); + *val = readl(va_address); + imx_pcie_fix_dabt_handler(false); + + return 0; +} + +static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, + int where, u32 val) +{ + uint32_t va_address = 0; + int ret; + + ret = imx_pcie_addr_valid(d); + if (ret) + return ret; + + va_address = get_bus_address(d, where); + + /* + * Write the PCIe config space. We must replace the DABT handler + * here in case we got data abort from the PCIe controller, see + * imx_pcie_fix_dabt_handler() description. + */ + imx_pcie_fix_dabt_handler(true); + writel(val, va_address); + imx_pcie_fix_dabt_handler(false); + + return 0; +} + +/* + * Initial bus setup + */ +static int imx6_pcie_assert_core_reset(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); + + return 0; +} + +static int imx6_pcie_init_phy(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); + + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_DEVICE_TYPE_MASK, + IOMUXC_GPR12_DEVICE_TYPE_RC); + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_LOS_LEVEL_MASK, + IOMUXC_GPR12_LOS_LEVEL_9); + + writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) | + (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) | + (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) | + (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) | + (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET), + &iomuxc_regs->gpr[8]); + + return 0; +} + +static int imx6_pcie_deassert_core_reset(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* FIXME: Power-up GPIO goes here. */ + + /* Enable PCIe */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); + + enable_pcie_clock(); + + /* + * Wait for the clock to settle a bit, when the clock are sourced + * from the CPU, we need about 30mS to settle. + */ + mdelay(30); + + /* FIXME: GPIO reset goes here */ + mdelay(100); + + return 0; +} + +static int imx_pcie_link_up(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + uint32_t tmp; + int count = 0; + + imx6_pcie_assert_core_reset(); + imx6_pcie_init_phy(); + imx6_pcie_deassert_core_reset(); + + imx_pcie_regions_setup(); + + /* + * FIXME: Force the PCIe RC to Gen1 operation + * The RC must be forced into Gen1 mode before bringing the link + * up, otherwise no downstream devices are detected. After the + * link is up, a managed Gen1->Gen2 transition can be initiated. + */ + tmp = readl(MX6_DBI_ADDR + 0x7c); + tmp &= ~0xf; + tmp |= 0x1; + writel(tmp, MX6_DBI_ADDR + 0x7c); + + /* LTSSM enable, starting link. */ + setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); + + while (!imx6_pcie_link_up()) { + udelay(10); + count++; + if (count >= 2000) { + debug("phy link never came up\n"); + debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", + readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0), + readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1)); + return -EINVAL; + } + } + + return 0; +} + +void imx_pcie_init(void) +{ + /* Static instance of the controller. */ + static struct pci_controller pcc; + struct pci_controller *hose = &pcc; + int ret; + + memset(&pcc, 0, sizeof(pcc)); + + /* PCI I/O space */ + pci_set_region(&hose->regions[0], + MX6_IO_ADDR, MX6_IO_ADDR, + MX6_IO_SIZE, PCI_REGION_IO); + + /* PCI memory space */ + pci_set_region(&hose->regions[1], + MX6_MEM_ADDR, MX6_MEM_ADDR, + MX6_MEM_SIZE, PCI_REGION_MEM); + + /* System memory space */ + pci_set_region(&hose->regions[2], + MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR, + 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 3; + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + imx_pcie_read_config, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + imx_pcie_write_config); + + /* Start the controller. */ + ret = imx_pcie_link_up(); + + if (!ret) { + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); + } +} + +/* Probe function. */ +void pci_init_board(void) +{ + imx_pcie_init(); +} -- cgit v0.10.2 From 147f8fa3c55451949f90624a091c34f433df1d99 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 14 Dec 2013 05:55:29 +0100 Subject: ARM: mx6: Enable PCIe on Sabrelite Enable PCI express on MX6 Sabrelite. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Eric Nelson Cc: Fabio Estevam Cc: Stefano Babic diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index f4ff5cd..e656551 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -352,4 +352,15 @@ #define CONFIG_SUPPORT_RAW_INITRD #define CONFIG_CMD_FS_GENERIC +/* + * PCI express + */ +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#endif + #endif /* __CONFIG_H */ -- cgit v0.10.2 From 7aa378ec00ddabe0dee39b69e1c0820420289ea9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 24 Jan 2014 09:15:47 -0200 Subject: nitrogen6x: README: Only calling 'make' is enough No need to pass 'u-boot.imx' as parameter for 'make' because u-boot.imx is built by default. Signed-off-by: Fabio Estevam Acked-by: Eric Nelson diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README index 5049093..6f449be 100644 --- a/board/boundary/nitrogen6x/README +++ b/board/boundary/nitrogen6x/README @@ -67,7 +67,7 @@ override auto-detection and force activation of the specified panel. To build U-Boot for one of the Nitrogen6x or SabreLite board: make nitrogen6x_config - make u-boot.imx + make Note that 'nitrogen6x' is a placeholder. The complete list of supported board configurations is shown in tha MAINTAINERS file: -- cgit v0.10.2 From fd5cc218fdcd650436b0f92a227116bc0fccd103 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 24 Jan 2014 09:27:37 -0200 Subject: nitrogen6x: README: Do not refer to MAINTAINERS file MAINTAINERS file has been removed from the project. Replace its reference with 'boards.cfg' file instead. Signed-off-by: Fabio Estevam Acked-by: Eric Nelson diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README index 6f449be..9d84265 100644 --- a/board/boundary/nitrogen6x/README +++ b/board/boundary/nitrogen6x/README @@ -70,7 +70,7 @@ To build U-Boot for one of the Nitrogen6x or SabreLite board: make Note that 'nitrogen6x' is a placeholder. The complete list of supported -board configurations is shown in tha MAINTAINERS file: +board configurations is shown in the boards.cfg file: nitrogen6q i.MX6Q/6D 1GB nitrogen6dl i.MX6DL 1GB nitrogen6s i.MX6S 512MB -- cgit v0.10.2 From 8331273ca95a76cb89bfeaa2729622e91db885ff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 Jan 2014 22:00:10 +0100 Subject: ARM: m53evk: Rename mxc-nand to mxc_nand The name the Linux kernel expects is 'mxc_nand' , not 'mxc-nand' . This patch renames the driver name. Signed-off-by: Marek Vasut Cc: Stefano Babic Acked-by: Stefano Babic diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index a344af4..a5ab381 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -128,9 +128,9 @@ #define CONFIG_LZO #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nand0=mxc-nand" +#define MTDIDS_DEFAULT "nand0=mxc_nand" #define MTDPARTS_DEFAULT \ - "mtdparts=mxc-nand:" \ + "mtdparts=mxc_nand:" \ "1m(bootloader)ro," \ "512k(environment)," \ "512k(redundant-environment)," \ -- cgit v0.10.2 From 9a12fcd0c995e8a47971778cf31e19a44a605c0c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 Jan 2014 22:00:11 +0100 Subject: ARM: m53evk: Enable CONFIG_REGEX Enable CONFIG_REGEX on M53EVK to allow usage of regular expressions on environment variables. Signed-off-by: Marek Vasut Cc: Stefano Babic diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index a5ab381..bd67603 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -39,6 +39,8 @@ #define CONFIG_CMD_USB #define CONFIG_VIDEO +#define CONFIG_REGEX /* Enable regular expression support */ + /* * Memory configurations */ -- cgit v0.10.2 From 4ac0c2bfba3f2681e89a5f756cab019a58445b3c Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:57:56 -0200 Subject: cgtqmx6eval: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 29a023c..b189bf1 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -75,7 +75,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "boot_dir=/boot\0" \ "console=ttymxc1\0" \ @@ -92,24 +92,24 @@ "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${boot_dir}/${uimage}\0" \ + "loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${boot_dir}/${image}\0" \ "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \ "${boot_dir}/${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -118,7 +118,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else "\ "echo ERR: Fail to boot from mmc; " \ -- cgit v0.10.2 From 1e373dffa4e1f57383eed20a68529e835c70e7c6 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:57:57 -0200 Subject: hummingboard: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/hummingboard.h b/include/configs/hummingboard.h index 4055af5..ac65620 100644 --- a/include/configs/hummingboard.h +++ b/include/configs/hummingboard.h @@ -92,7 +92,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ "fdt_high=0xffffffff\0" \ @@ -124,22 +124,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -151,19 +151,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -171,7 +171,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ -- cgit v0.10.2 From 04585b063800f1153128356dabeb7bbb19d16dad Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:57:58 -0200 Subject: mx23evk: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 1b40a36..b496892 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -84,7 +84,7 @@ "fi ; " \ "fi\0" \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttyAMA0\0" \ "fdt_file=imx23-evk.dtb\0" \ "fdt_addr=0x41000000\0" \ @@ -98,22 +98,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -121,7 +121,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else " \ "echo ERR: Fail to boot from MMC; " \ -- cgit v0.10.2 From fb3f9170210f39eea3e6f77dbba09c349d79129c Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:57:59 -0200 Subject: mx28evk: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 4fd67eb..9b9124a 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -198,7 +198,7 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "nand write ${loadaddr} kernel ${filesize}\0" \ "update_nand_fdt=" /* Update fdt */ \ "mtdparts default; " \ @@ -230,10 +230,10 @@ "nand read ${loadaddr} kernel 0x00400000; " \ "if test ${boot_fdt} = yes; then " \ "nand read ${fdt_addr} fdt 0x00080000; " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = no; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo \"ERROR: Set boot_fdt to yes or no.\"; " \ "fi; " \ @@ -248,7 +248,7 @@ "fi ; " \ "fi\0" \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console_fsl=ttyAM0\0" \ "console_mainline=ttyAMA0\0" \ "fdt_file=imx28-evk.dtb\0" \ @@ -264,22 +264,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ "root=/dev/nfs " \ @@ -291,19 +291,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi;" \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -311,7 +311,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ -- cgit v0.10.2 From 20f233bb664b03cf732b6e914d1fd692459fc6ec Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:58:00 -0200 Subject: mx51evk: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 1cff171..b389475 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -143,7 +143,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=imx51-babbage.dtb\0" \ "fdt_addr=0x91000000\0" \ "boot_fdt=try\0" \ @@ -157,22 +157,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ "root=/dev/nfs " \ @@ -184,20 +184,20 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo ERROR: Cannot load the DT; " \ "exit; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -205,7 +205,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ -- cgit v0.10.2 From f28154b5b56270a0c684d14df135392e7ad95443 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:58:01 -0200 Subject: mx53loco: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index ae43ea3..77f8567 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -103,7 +103,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=imx53-qsb.dtb\0" \ "fdt_addr=0x71000000\0" \ "boot_fdt=try\0" \ @@ -116,22 +116,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ "root=/dev/nfs " \ @@ -143,20 +143,20 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo ERROR: Cannot load the DT; " \ "exit; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -164,7 +164,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ -- cgit v0.10.2 From 124f196af287483e56b3a70c77a83c6ccb74554f Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:58:02 -0200 Subject: mx6qarm2: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index f0a82d1..fd651cf 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -72,7 +72,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc3\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -85,16 +85,16 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "bootm\0" \ + "bootz\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ + "dhcp ${image}; bootz\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev};" \ @@ -102,7 +102,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ -- cgit v0.10.2 From f2e4288acb72c197d3d6a2439dbd707b24754495 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:58:03 -0200 Subject: mx6sabre_common: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 5ee7fa5..4efcebf 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -119,7 +119,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ @@ -150,22 +150,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -177,19 +177,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -198,7 +198,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ -- cgit v0.10.2 From 8e184a53b3441a36bdb8dac68b1dcba7fb9c887f Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:58:04 -0200 Subject: mx6slevk: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index b29f78c..5d88dc4 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -76,7 +76,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -93,22 +93,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -120,19 +120,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -141,7 +141,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ -- cgit v0.10.2 From 5ef142498ed98d8399cf695bc6e622d9ccdc4de6 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:58:05 -0200 Subject: udoo: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 614e1fe..7f09489 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -100,7 +100,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc1\0" \ "splashpos=m,m\0" \ "fdt_high=0xffffffff\0" \ @@ -132,22 +132,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -159,19 +159,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -179,7 +179,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ -- cgit v0.10.2 From c0a5b0816f545938bd8dccc1e775d0ea6e49b286 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 16 Jan 2014 19:58:06 -0200 Subject: vf610twr: Set default environment to use zImage Change the default environment to use zImage instead of uImage, this requires changes to the default environment to load a file named zImage instead of uImage, and to use the 'bootz' command instead of 'bootm' when booting the kernel. Signed-off-by: Otavio Salvador diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 8d0a00d..500fd2f 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -81,7 +81,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttyLP1\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -112,22 +112,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -139,19 +139,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -159,7 +159,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ -- cgit v0.10.2 From 6fc049bef6900a9eb258d8cf77e540fa06a2efae Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 22 Jan 2014 12:23:32 -0200 Subject: mx6sl: Adjust fdt_addr to avoid address overlapping Similarly as it was done on commit 6584a1b526 (ARM: mx6: Change the FDT loading address to avoid overlaping), we need to adjust the fdt_addr in order to be able to boot FSL 3.10 kernel. Signed-off-by: Fabio Estevam Acked-by: Otavio Salvador diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 5d88dc4..e5bdcc2 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -81,7 +81,7 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=imx6sl-evk.dtb\0" \ - "fdt_addr=0x81000000\0" \ + "fdt_addr=0x88000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev=0\0" \ -- cgit v0.10.2 From 5c92edc21c3e12873cd3de5ed73d85d48b8828ac Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 23 Jan 2014 14:00:18 +0800 Subject: imx6: ensure AHB clock is 132MHz in low freq boot mode For low freq boot mode(ARM boot up with 396MHz), ROM will not set AHB clock to 132MHz, and the reset value of AHB divider is incorrect which will lead to wrong AHB rate, need to correct it. To enable low freq boot mode, need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL SabreSD board and i.MX6SL EVK board. Reviewed-by: Fabio Estevam Signed-off-by: Anson Huang diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 0208cba..33a2939 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -177,10 +177,30 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } +static void set_ahb_rate(u32 val) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg, div; + + div = get_periph_clk() / val - 1; + reg = readl(&mxc_ccm->cbcdr); + + writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | + (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); +} + int arch_cpu_init(void) { init_aips(); + /* + * When low freq boot is enabled, ROM will not set AHB + * freq, so we need to ensure AHB freq is 132MHz in such + * scenario. + */ + if (mxc_get_clock(MXC_ARM_CLK) == 396000000) + set_ahb_rate(132000000); + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ #ifdef CONFIG_APBH_DMA -- cgit v0.10.2 From 16197bb8ba5962ab3a9c065c06c91c8c288c0f8e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 23 Jan 2014 14:00:19 +0800 Subject: imx6: make sure MMDC_CHx_MASK is clear to avoid warm reset failure Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2), it will cause warm reset fail, need to clear this MMDC_CHx_MASK field to make sure all the i.MX6 series SOCs reset function work. Otherwise, uboot "reset" command will fail, tested on i.MX6SL EVK board with TO1.2. Signed-off-by: Anson Huang diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 33a2939..2aad0a1 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -189,10 +189,21 @@ static void set_ahb_rate(u32 val) (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); } +static void clear_mmdc_ch_mask(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Clear MMDC channel mask */ + writel(0, &mxc_ccm->ccdr); +} + int arch_cpu_init(void) { init_aips(); + /* Need to clear MMDC_CHx_MASK to make warm reset work. */ + clear_mmdc_ch_mask(); + /* * When low freq boot is enabled, ROM will not set AHB * freq, so we need to ensure AHB freq is 132MHz in such -- cgit v0.10.2 From c0da86225fb501eea26318e7f3760cdee25ee83d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 25 Jan 2014 14:08:24 -0200 Subject: hummingboard: Return from cpu_eth_init() directly There is no need to print an error message when cpu_eth_init() fails because net/eth.c already prints it. In order to simplify the code, just return the value from cpu_eth_init(bis) directly. Signed-off-by: Fabio Estevam diff --git a/board/solidrun/hummingboard/hummingboard.c b/board/solidrun/hummingboard/hummingboard.c index 8b309b4..2e2fb2a 100644 --- a/board/solidrun/hummingboard/hummingboard.c +++ b/board/solidrun/hummingboard/hummingboard.c @@ -156,11 +156,7 @@ int board_eth_init(bd_t *bis) setup_iomux_enet(); - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); - - return ret; + return cpu_eth_init(bis); } #endif -- cgit v0.10.2 From 6a99f03d696ee51e584a9c95b9fb065ebf0d46b4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 26 Jan 2014 15:06:40 -0200 Subject: imx: Introduce a header for the imx cpu versions Instead of duplicating the CPU definitions at mx5 and mx6 sys_proto.h header files, introduce a common header to centralize such definitions. Signed-off-by: Fabio Estevam diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h new file mode 100644 index 0000000..8c725e2 --- /dev/null +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MXC_CPU_MX51 0x51 +#define MXC_CPU_MX53 0x53 +#define MXC_CPU_MX6SL 0x60 +#define MXC_CPU_MX6DL 0x61 +#define MXC_CPU_MX6SOLO 0x62 +#define MXC_CPU_MX6Q 0x63 diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 9949ad1..ac7705b 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -8,12 +8,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 +#include "../arch-imx/cpu.h" #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 17125a6..38851a1 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -9,13 +9,7 @@ #define _SYS_PROTO_H_ #include - -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 +#include "../arch-imx/cpu.h" #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); -- cgit v0.10.2 From 94db66557997a929313e0f5020c83368b1c6627f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 26 Jan 2014 15:06:41 -0200 Subject: mx6: Distinguish mx6dual from mx6quad Currently when we boot a mx6dual U-boot reports that it is a mx6quad. Report it as MX6D instead: CPU: Freescale i.MX6D rev1.2 at 792 MHz Signed-off-by: Fabio Estevam Acked-by: Stefano babic Acked-by: Otavio Salvador diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 2aad0a1..4c5c367 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -41,14 +41,19 @@ u32 get_cpu_rev(void) if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + u32 cfg = readl(&scu->config) & 3; type = ((reg >> 16) & 0xff); if (type == MXC_CPU_MX6DL) { - struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; - u32 cfg = readl(&scu->config) & 3; - if (!cfg) type = MXC_CPU_MX6SOLO; } + + if (type == MXC_CPU_MX6Q) { + if (cfg == 1) + type = MXC_CPU_MX6D; + } + } reg &= 0xff; /* mx6 silicon revision */ return (type << 12) | (reg + 0x10); @@ -62,6 +67,9 @@ u32 __weak get_board_rev(void) if (type == MXC_CPU_MX6SOLO) cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); + if (type == MXC_CPU_MX6D) + cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); + return cpurev; } #endif diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 9231649..a77c4de 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype) switch (imxtype) { case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ + case MXC_CPU_MX6D: + return "6D"; /* Dual-core version of the mx6 */ case MXC_CPU_MX6DL: return "6DL"; /* Dual Lite version of the mx6 */ case MXC_CPU_MX6SOLO: diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 8c725e2..a35940e 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -10,3 +10,4 @@ #define MXC_CPU_MX6DL 0x61 #define MXC_CPU_MX6SOLO 0x62 #define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6D 0x64 -- cgit v0.10.2 From 4702c62dce3e2e2648ae3c8d002202211de8c92a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 27 Jan 2014 14:05:47 -0200 Subject: mx6qsabreauto: Update imximage.cfg Use the latest DDR and clock settings as the one from Freescale BSP. Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg index 6d192a6..16bf473 100644 --- a/board/freescale/mx6qsabreauto/imximage.cfg +++ b/board/freescale/mx6qsabreauto/imximage.cfg @@ -29,119 +29,101 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 DATA 4 0x020e05a8 0x00000028 DATA 4 0x020e05b0 0x00000028 DATA 4 0x020e0524 0x00000028 DATA 4 0x020e051c 0x00000028 - DATA 4 0x020e0518 0x00000028 DATA 4 0x020e050c 0x00000028 DATA 4 0x020e05b8 0x00000028 DATA 4 0x020e05c0 0x00000028 - -DATA 4 0x020e05ac 0x00000028 -DATA 4 0x020e05b4 0x00000028 -DATA 4 0x020e0528 0x00000028 -DATA 4 0x020e0520 0x00000028 - -DATA 4 0x020e0514 0x00000028 -DATA 4 0x020e0510 0x00000028 -DATA 4 0x020e05bc 0x00000028 -DATA 4 0x020e05c4 0x00000028 - -DATA 4 0x020e056c 0x00000030 -DATA 4 0x020e0578 0x00000030 -DATA 4 0x020e0588 0x00000030 -DATA 4 0x020e0594 0x00000030 - -DATA 4 0x020e057c 0x00000030 -DATA 4 0x020e0590 0x00000030 -DATA 4 0x020e0598 0x00000030 -DATA 4 0x020e058c 0x00000000 - -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e0774 0x00020000 DATA 4 0x020e0784 0x00000028 DATA 4 0x020e0788 0x00000028 - DATA 4 0x020e0794 0x00000028 DATA 4 0x020e079c 0x00000028 DATA 4 0x020e07a0 0x00000028 DATA 4 0x020e07a4 0x00000028 - DATA 4 0x020e07a8 0x00000028 DATA 4 0x020e0748 0x00000028 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0750 0x00020000 - -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0798 0x000C0000 - +DATA 4 0x020e05ac 0x00000028 +DATA 4 0x020e05b4 0x00000028 +DATA 4 0x020e0528 0x00000028 +DATA 4 0x020e0520 0x00000028 +DATA 4 0x020e0514 0x00000028 +DATA 4 0x020e0510 0x00000028 +DATA 4 0x020e05bc 0x00000028 +DATA 4 0x020e05c4 0x00000028 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x43260335 +DATA 4 0x021b0840 0x031A030B +DATA 4 0x021b483c 0x4323033B +DATA 4 0x021b4840 0x0323026F +DATA 4 0x021b0848 0x483D4545 +DATA 4 0x021b4848 0x44433E48 +DATA 4 0x021b0850 0x41444840 +DATA 4 0x021b4850 0x4835483E DATA 4 0x021b081c 0x33333333 DATA 4 0x021b0820 0x33333333 DATA 4 0x021b0824 0x33333333 DATA 4 0x021b0828 0x33333333 - DATA 4 0x021b481c 0x33333333 DATA 4 0x021b4820 0x33333333 DATA 4 0x021b4824 0x33333333 DATA 4 0x021b4828 0x33333333 - +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x8A8F7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b0018 0x00001740 - DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x8A8F7975 -DATA 4 0x021b0010 0xFF538E64 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b002c 0x000026D2 - -DATA 4 0x021b0030 0x008F0E21 -DATA 4 0x021b0008 0x09444040 -DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008F1023 DATA 4 0x021b0040 0x00000047 DATA 4 0x021b0000 0x841A0000 - DATA 4 0x021b001c 0x04088032 DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00048031 DATA 4 0x021b001c 0x09408030 - DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b0800 0xA1380003 DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00000007 -DATA 4 0x021b4818 0x00000007 - -/* Calibration values based on ARD and 528MHz */ -DATA 4 0x021b083c 0x434B0358 -DATA 4 0x021b0840 0x033D033C -DATA 4 0x021b483c 0x03520362 -DATA 4 0x021b4840 0x03480318 -DATA 4 0x021b0848 0x41383A3C -DATA 4 0x021b4848 0x3F3C374A -DATA 4 0x021b0850 0x42434444 -DATA 4 0x021b4850 0x4932473A - -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F - -DATA 4 0x021b480c 0x001F001F -DATA 4 0x021b4810 0x001F001F - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 DATA 4 0x021b0004 0x00025576 - +DATA 4 0x021b0404 0x00011006 DATA 4 0x021b001c 0x00000000 +/* set the default clock gate to save power */ DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03 DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF +DATA 4 0x020c4078 0xFFFFF300 +DATA 4 0x020c407c 0x0F0000F3 +DATA 4 0x020c4080 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F -- cgit v0.10.2 From 6d73c23410cd0f8a54227dd0361fb8b9eadcb4b2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 29 Jan 2014 17:39:49 -0200 Subject: mx6: Enable L2 cache support Add L2 cache support and enable it by default. Configure the L2 cache in the same way as done by FSL kernel: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam Acked-by: Dirk Behme Acked-by: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 4c5c367..1725279 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -8,6 +8,8 @@ */ #include +#include +#include #include #include #include @@ -375,3 +377,59 @@ void imx_setup_hdmi(void) writel(reg, &mxc_ccm->chsccdr); } #endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 +void v7_outer_cache_enable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + unsigned int val; + +#if defined CONFIG_MX6SL + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + val = readl(&iomux->gpr[11]); + if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { + /* L2 cache configured as OCRAM, reset it */ + val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; + writel(val, &iomux->gpr[11]); + } +#endif + + writel(0x132, &pl310->pl310_tag_latency_ctrl); + writel(0x132, &pl310->pl310_data_latency_ctrl); + + val = readl(&pl310->pl310_prefetch_ctrl); + + /* Turn on the L2 I/D prefetch */ + val |= 0x30000000; + + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + +#ifndef CONFIG_MX6Q + val |= 0x40800000; +#endif + writel(val, &pl310->pl310_prefetch_ctrl); + + val = readl(&pl310->pl310_power_ctrl); + val |= L2X0_DYNAMIC_CLK_GATING_EN; + val |= L2X0_STNDBY_MODE_EN; + writel(val, &pl310->pl310_power_ctrl); + + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} +#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index f2ad6e9..c2d210a 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -53,6 +53,7 @@ #define GLOBAL_TIMER_BASE_ADDR 0x00A00200 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 +#define L2_PL310_BASE 0x00A02000 #define GPV0_BASE_ADDR 0x00B00000 #define GPV1_BASE_ADDR 0x00C00000 #define PCIE_ARB_BASE_ADDR 0x01000000 diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index f41ad8c..ddc245b 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -12,6 +12,9 @@ /* Register bit fields */ #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) +#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) +#define L2X0_STNDBY_MODE_EN (1 << 0) +#define L2X0_CTRL_EN 1 struct pl310_regs { u32 pl310_cache_id; @@ -47,6 +50,24 @@ struct pl310_regs { u32 pad9[1]; u32 pl310_clean_inv_line_idx; u32 pl310_clean_inv_way; + u32 pad10[64]; + u32 pl310_lockdown_dbase; + u32 pl310_lockdown_ibase; + u32 pad11[190]; + u32 pl310_addr_filter_start; + u32 pl310_addr_filter_end; + u32 pad12[190]; + u32 pl310_test_operation; + u32 pad13[3]; + u32 pl310_line_data; + u32 pad14[7]; + u32 pl310_line_tag; + u32 pad15[3]; + u32 pl310_debug_ctrl; + u32 pad16[7]; + u32 pl310_prefetch_ctrl; + u32 pad17[7]; + u32 pl310_power_ctrl; }; void pl310_inval_all(void); diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 514d634..eb107d3 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -22,4 +22,9 @@ #define CONFIG_ARM_ERRATA_751472 #define CONFIG_BOARD_POSTCLK_INIT +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#endif + #endif -- cgit v0.10.2 From bb01956344da904463870104d3a66ecfffea7c7a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Feb 2014 21:46:22 +0100 Subject: pci: mx6: Implement reset callback Add a callback so that a board can implement it's own specific routine to toggle the port's #PERST line or #define a GPIO to do so. Signed-off-by: Marek Vasut diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 0a74867..34377e9 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -450,6 +451,47 @@ static int imx6_pcie_init_phy(void) return 0; } +__weak int imx6_pcie_toggle_reset(void) +{ + /* + * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1' + * for detailed understanding of the PCIe CR reset logic. + * + * The PCIe #PERST reset line _MUST_ be connected, otherwise your + * design does not conform to the specification. You must wait at + * least 20 mS after de-asserting the #PERST so the EP device can + * do self-initialisation. + * + * In case your #PERST pin is connected to a plain GPIO pin of the + * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's + * configuration file and the condition below will handle the rest + * of the reset toggling. + * + * In case your #PERST toggling logic is more complex, for example + * connected via CPLD or somesuch, you can override this function + * in your board file and implement reset logic as needed. You must + * not forget to wait at least 20 mS after de-asserting #PERST in + * this case either though. + * + * In case your #PERST line of the PCIe EP device is not connected + * at all, your design is broken and you should fix your design, + * otherwise you will observe problems like for example the link + * not coming up after rebooting the system back from running Linux + * that uses the PCIe as well OR the PCIe link might not come up in + * Linux at all in the first place since it's in some non-reset + * state due to being previously used in U-Boot. + */ +#ifdef CONFIG_PCIE_IMX_PERST_GPIO + gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0); + mdelay(20); + gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1); + mdelay(20); +#else + puts("WARNING: Make sure the PCIe #PERST line is connected!\n"); +#endif + return 0; +} + static int imx6_pcie_deassert_core_reset(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -466,10 +508,9 @@ static int imx6_pcie_deassert_core_reset(void) * Wait for the clock to settle a bit, when the clock are sourced * from the CPU, we need about 30mS to settle. */ - mdelay(30); + mdelay(50); - /* FIXME: GPIO reset goes here */ - mdelay(100); + imx6_pcie_toggle_reset(); return 0; } -- cgit v0.10.2 From adadc915b31c4d55561c2703849f92cddfa8ad24 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Wed, 5 Feb 2014 10:51:25 +0100 Subject: ARM: imx6: fix wrong fec clk imx_get_fecclk() returns enet_ref instead of ipg. Since the clock is used to calculate the prescaler for the MDIO interface wrong values can be calculated. Tested on a custom MX6S board with 100MBit interface Signed-off-by: Markus Niebel diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 61f71cf..bd65a08 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -409,7 +409,7 @@ u32 imx_get_uartclk(void) u32 imx_get_fecclk(void) { - return decode_pll(PLL_ENET, MXC_HCLK); + return mxc_get_clock(MXC_IPG_CLK); } static int enable_enet_pll(uint32_t en) -- cgit v0.10.2 From 6ba45cc0f8b46533965219cfd90864a60ec1009b Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Wed, 5 Feb 2014 10:54:11 +0100 Subject: NET: fec_mxc: fix MDIO clock prescaler calculation The prescaler value for MDC is calculated wrong for MX6S. Implement the same logic as linux here which handles ENET_MAC different then original FEC. Tested on a custom board with i.MX6S and 100MBit PHY Signed-off-by: Markus Niebel diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 3b2b995..4cefda4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -128,8 +128,12 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ - writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, - ð->mii_speed); + register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000); +#ifdef FEC_QUIRK_ENET_MAC + speed--; +#endif + speed <<= 1; + writel(speed, ð->mii_speed); debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); } -- cgit v0.10.2 From 9b986fdd92217ca567d7498c5063b5102f6b9e52 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 10 Feb 2014 10:22:41 -0700 Subject: i.MX6: nitrogen6x: pedantic: BOOT_FROM==spi, not sd Signed-off-by: Eric Nelson Acked-by: Stefano Babic diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg index 97ae0c2..1cdccad 100644 --- a/board/boundary/nitrogen6x/nitrogen6dl.cfg +++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg index 82f837e..516d67e 100644 --- a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg index b6f1518..b6642e6 100644 --- a/board/boundary/nitrogen6x/nitrogen6q.cfg +++ b/board/boundary/nitrogen6x/nitrogen6q.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg index 8d7ff25..fe6dfc1 100644 --- a/board/boundary/nitrogen6x/nitrogen6q2g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg index 34fb9d0..ca30cd6 100644 --- a/board/boundary/nitrogen6x/nitrogen6s.cfg +++ b/board/boundary/nitrogen6x/nitrogen6s.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg index d61453c..b1489fb 100644 --- a/board/boundary/nitrogen6x/nitrogen6s1g.cfg +++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg @@ -16,7 +16,7 @@ IMAGE_VERSION 2 * Boot Device : one of * spi, sd (the board has no nand neither onenand) */ -BOOT_FROM sd +BOOT_FROM spi #define __ASSEMBLY__ #include -- cgit v0.10.2 From da781c60e5d55904d77931fcb63f25e65e2228be Mon Sep 17 00:00:00 2001 From: Andy Ng Date: Wed, 12 Feb 2014 14:31:15 +0000 Subject: imx6 SION bit has to be on for the pins that are used as ENET_REF_CLK Signed-off-by: Andy Ng diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 55cc9ad..2e414ad 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -647,7 +647,7 @@ MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x05BC, 0x01EC, 2, 0x083C, 0, 0) MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x05BC, 0x01EC, 4, 0x0000, 0, 0) MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x05BC, 0x01EC, 5, 0x0000, 0, 0) MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x05BC, 0x01EC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x05C0, 0x01F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x05C0, 0x01F0, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x05C0, 0x01F0, 2, 0x082C, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x05C0, 0x01F0, 5, 0x0000, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x05C0, 0x01F0, 6, 0x0000, 0, 0) @@ -695,7 +695,7 @@ MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05E0, 0x0210, 5, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x05E4, 0x0214, 0, 0x0850, 1, 0) MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x05E4, 0x0214, 2, 0x080C, 0, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0) MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x05E4, 0x0214, 3, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x05E4, 0x0214, 4, 0x08F0, 2, 0) MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x05E4, 0x0214, 5, 0x0000, 0, 0) @@ -934,7 +934,7 @@ MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SI MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x06BC, 0x02D4, 7, 0x080C, 1, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0) MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x06C0, 0x02D8, 2, 0x08F4, 1, 0) diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index ad31c33..a8456a2 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -53,7 +53,7 @@ MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0384, 0x0070, 5, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x0388, 0x0074, 0, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x0388, 0x0074, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x0388, 0x0074, 7, 0x083C, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x0388, 0x0074, 7 | IOMUX_CONFIG_SION, 0x083C, 0, 0) MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x038C, 0x0078, 0, 0x0000, 0, 0) MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0, 0) MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x038C, 0x0078, 5, 0x0000, 0, 0) @@ -523,7 +523,7 @@ MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x04E4, 0x01D0, 2, 0x086C, 0, 0) MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x04E4, 0x01D0, 4, 0x0000, 0, 0) MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x04E4, 0x01D0, 5, 0x0000, 0, 0) MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x04E4, 0x01D0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x04E8, 0x01D4, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x04E8, 0x01D4, 2, 0x085C, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x04E8, 0x01D4, 5, 0x0000, 0, 0) MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0, 0) @@ -703,7 +703,7 @@ MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x0614, 0x0244, 6, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x0614, 0x0244, 7, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x0618, 0x0248, 0, 0x0880, 1, 0) MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x0618, 0x0248, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x0618, 0x0248, 2, 0x083C, 1, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0) MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x0618, 0x0248, 3, 0x0000, 0, 0) MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x0618, 0x0248, 4, 0x0914, 3, 0) MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x0618, 0x0248, 5, 0x0000, 0, 0) -- cgit v0.10.2