From a65c5768e5537530bd1780af3d3fddc3113a163c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Apr 2007 10:09:30 +0200 Subject: ppc4xx: Change SysACE address on Katmai With this new base address of the Xilinx SystemACE controller the Linux driver will be easier to adapt, since it can now be mapped via the "normal" ioremap() call. Signed-off-by: Stefan Roese diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index 6b024ee..5202ae6 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -103,7 +103,7 @@ tlbtabB: tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 1606d0d..7f55366 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -78,7 +78,7 @@ #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) -#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */ +#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) -- cgit v0.10.2 From 2ad3aba01d37b72e7c957b07e102fccd64fe6d13 Mon Sep 17 00:00:00 2001 From: Jeffrey Mann Date: Thu, 12 Apr 2007 14:15:59 +0200 Subject: ppc4xx: Fix i2c divisor calcularion for PPC4xx This patch fixes changes the i2c_init(...) function to use the function get_OPB_freq() rather than calculating the OPB speed by sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is specific per processor. The prior method was not and so was calculating the wrong speed for some PPC4xx processors. Signed-off-by: Jeffrey Mann Signed-off-by: Stefan Roese diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index 8f4da86..47c264e 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -91,7 +91,6 @@ static void _i2c_bus_reset(void) void i2c_init(int speed, int slaveadd) { - sys_info_t sysInfo; unsigned long freqOPB; int val, divisor; int bus; @@ -124,8 +123,7 @@ void i2c_init(int speed, int slaveadd) /* Clock divide Register */ /* get OPB frequency */ - get_sys_info(&sysInfo); - freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; + freqOPB = get_OPB_freq(); /* set divisor according to freqOPB */ divisor = (freqOPB - 1) / 10000000; if (divisor == 0) -- cgit v0.10.2 From 0b94504d22e70f537c17a0d38c87edb6e370977d Mon Sep 17 00:00:00 2001 From: Greg Lopp Date: Fri, 13 Apr 2007 08:02:24 +0200 Subject: [PATCH] Fix use of "void *" for block dev read/write buffer pointers Signed-of-by: Greg Lopp Acked-by: Grant Likely diff --git a/common/cmd_ide.c b/common/cmd_ide.c index b4119f3..28797a9 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -1344,7 +1344,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer) ++n; ++blknr; - buffer += ATA_SECTORWORDS; + buffer += ATA_BLOCKSIZE; } IDE_READ_E: ide_led (DEVICE_LED(device), 0); /* LED off */ @@ -1428,7 +1428,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer) c = ide_inb (device, ATA_STATUS); /* clear IRQ */ ++n; ++blknr; - buffer += ATA_SECTORWORDS; + buffer += ATA_BLOCKSIZE; } WR_OUT: ide_led (DEVICE_LED(device), 0); /* LED off */ @@ -2052,7 +2052,7 @@ ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer) n+=cnt; blkcnt-=cnt; blknr+=cnt; - buffer+=cnt*(ATAPI_READ_BLOCK_SIZE/4); /* ulong blocksize in ulong */ + buffer+=(cnt*ATAPI_READ_BLOCK_SIZE); } while (blkcnt > 0); return (n); } -- cgit v0.10.2 From 7882751c78b7ecabfd49b0eff8de27661c71f16c Mon Sep 17 00:00:00 2001 From: Denis Peter Date: Fri, 13 Apr 2007 09:13:33 +0200 Subject: [PATCH] Fix bugs in cmd_ide.c and cmd_scsi.c Fix bug introduced by "Fix get_partition_info() parameter error in all other calls" from 2005-03-04 in cmd_ide.c and cmd_scsi.c, which prevented to use diskboot or scsiboot form another device than 0. Signed-off-by: Denis Peter diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 28797a9..ce99a41 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -423,7 +423,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } part = simple_strtoul(++ep, NULL, 16); } - if (get_partition_info (ide_dev_desc, part, &info)) { + if (get_partition_info (&ide_dev_desc[dev], part, &info)) { SHOW_BOOT_PROGRESS (-1); return 1; } diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index da36ed9..00b84fa 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -248,7 +248,7 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } part = simple_strtoul(++ep, NULL, 16); } - if (get_partition_info (scsi_dev_desc, part, &info)) { + if (get_partition_info (&scsi_dev_desc[dev], part, &info)) { printf("error reading partinfo\n"); return 1; } -- cgit v0.10.2 From d3832e8fe1b214ec62424eac36cfda9fc56d21b3 Mon Sep 17 00:00:00 2001 From: Domen Puncer Date: Mon, 16 Apr 2007 14:00:13 +0200 Subject: [PATCH] icecube/lite5200b: wakeup from low-power support U-Boot part of Lite5200b low power mode support. Puts SDRAM out of self-refresh and transfers control to address saved at physical 0x0. Signed-off-by: Domen Puncer Acked-by: Grant Likely diff --git a/Makefile b/Makefile index 84b49fe..8e551eb 100644 --- a/Makefile +++ b/Makefile @@ -430,6 +430,7 @@ inka4x0_config: unconfig @$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0 lite5200b_config \ +lite5200b_PM_config \ lite5200b_LOWBOOT_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/icecube @@ -438,6 +439,10 @@ lite5200b_LOWBOOT_config: unconfig @ echo "... DDR memory revision" @ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h @ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h + @[ -z "$(findstring _PM_,$@)" ] || \ + { echo "#define CONFIG_LITE5200B_PM" >>$(obj)include/config.h ; \ + echo "... with power management (low-power mode) support" ; \ + } @[ -z "$(findstring LOWBOOT_,$@)" ] || \ { echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \ echo "... with LOWBOOT configuration" ; \ diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 700c9d9..2960998 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -42,6 +42,53 @@ #include "mt48lc16m16a2-75.h" # endif #endif + +#ifdef CONFIG_LITE5200B_PM +/* u-boot part of low-power mode implementation */ +#define SAVED_ADDR (*(void **)0x00000000) +#define PSC2_4 0x02 + +void lite5200b_wakeup(void) +{ + unsigned char wakeup_pin; + void (*linux_wakeup)(void); + + /* check PSC2_4, if it's down "QT" is signaling we have a wakeup + * from low power mode */ + *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4; + __asm__ volatile ("sync"); + + wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I; + if (wakeup_pin & PSC2_4) + return; + + /* acknowledge to "QT" + * by holding pin at 1 for 10 uS */ + *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4; + __asm__ volatile ("sync"); + *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4; + __asm__ volatile ("sync"); + udelay(10); + + /* put ram out of self-refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */ + __asm__ volatile ("sync"); + *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */ + __asm__ volatile ("sync"); + *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */ + __asm__ volatile ("sync"); + udelay(10); /* wait a bit */ + + /* jump back to linux kernel code */ + linux_wakeup = SAVED_ADDR; + printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n", + linux_wakeup); + linux_wakeup(); +} +#else +#define lite5200b_wakeup() +#endif + #ifndef CFG_RAMBOOT static void sdram_start (int hi_addr) { @@ -208,6 +255,8 @@ long int initdram (int board_type) __asm__ volatile ("sync"); } + lite5200b_wakeup(); + return dramsize + dramsize2; } -- cgit v0.10.2 From 90e6f41cf09fc98f6ccb510e183d53ab8546cf2f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 18 Apr 2007 12:05:59 +0200 Subject: ppc4xx: Add output for bootrom location to 405EZ ports Now 405EZ ports also show upon bootup from which boot device they are configured to boot: U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05) CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz) Bootstrap Option E - Boot ROM Location EBC (32 bits) 16 kB I-Cache 16 kB D-Cache Board: Acadia - AMCC PPC405EZ Evaluation Board Signed-off-by: Stefan Roese diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 2d8740c..8e6bc84 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -125,6 +125,7 @@ int i2c_bootrom_enabled(void) return (val & SDR0_SDCS_SDD); #endif } +#endif #if defined(CONFIG_440GX) #define SDR0_PINSTP_SHIFT 29 @@ -178,16 +179,37 @@ static char *bootstrap_str[] = { }; #endif +#if defined(CONFIG_405EZ) +#define SDR0_PINSTP_SHIFT 28 +static char *bootstrap_str[] = { + "EBC (8 bits)", + "SPI (fast)", + "NAND (512 page, 4 addr cycle)", + "I2C (Addr 0x50)", + "EBC (32 bits)", + "I2C (Addr 0x50)", + "NAND (2K page, 5 addr cycle)", + "I2C (Addr 0x50)", + "EBC (16 bits)", + "Reserved", + "NAND (2K page, 4 addr cycle)", + "I2C (Addr 0x50)", + "NAND (512 page, 3 addr cycle)", + "I2C (Addr 0x50)", + "SPI (slow)", + "I2C (Addr 0x50)", +}; +#endif + #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) { unsigned long val; - mfsdr(sdr_pinstp, val); - return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT); + mfsdr(SDR_PINSTP, val); + return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT); } #endif /* SDR0_PINSTP_SHIFT */ -#endif #if defined(CONFIG_440) @@ -403,11 +425,11 @@ int checkcpu (void) #if defined(I2C_BOOTROM) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); +#endif /* I2C_BOOTROM */ #if defined(SDR0_PINSTP_SHIFT) printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A'); printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); #endif /* SDR0_PINSTP_SHIFT */ -#endif /* I2C_BOOTROM */ #if defined(CONFIG_PCI) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); diff --git a/include/ppc405.h b/include/ppc405.h index 08f10d2..a2503a9 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -570,6 +570,8 @@ #define SDR_ICTX0_STAT 0x40000000 #define SDR_ICTX1_STAT 0x20000000 +#define SDR_PINSTP 0x40 + /****************************************************************************** * Control ******************************************************************************/ diff --git a/include/ppc440.h b/include/ppc440.h index 51e6b9b..bc1d7aa 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -148,7 +148,7 @@ #define sdrcfgd (SDR_DCR_BASE+0x1) #define sdr_sdstp0 0x0020 /* */ #define sdr_sdstp1 0x0021 /* */ -#define sdr_pinstp 0x0040 +#define SDR_PINSTP 0x0040 #define sdr_sdcs 0x0060 #define sdr_ecid0 0x0080 #define sdr_ecid1 0x0081 -- cgit v0.10.2 From e673226ff9d6aa91b47ceac74b8c13770b06bb37 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 18 Apr 2007 12:07:47 +0200 Subject: ppc4xx: Update Acadia to not setup PLL when booting via bootstrap EEPROM Signed-off-by: Stefan Roese diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 7d0046a..baf598c 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -26,7 +26,7 @@ extern void board_pll_init_f(void); -void liveoak_gpio_init(void) +static void acadia_gpio_init(void) { /* * GPIO0 setup (select GPIO or alternate function) @@ -55,8 +55,12 @@ int board_early_init_f(void) { unsigned int reg; - board_pll_init_f(); - liveoak_gpio_init(); + /* don't reinit PLL when booting via I2C bootstrap option */ + mfsdr(SDR_PINSTP, reg); + if (reg != 0xf0000000) + board_pll_init_f(); + + acadia_gpio_init(); /* USB Host core needs this bit set */ mfsdr(sdrultra1, reg); -- cgit v0.10.2 From 3747a3f010b2b1442dec3e871c69788b6017aaae Mon Sep 17 00:00:00 2001 From: Domen Puncer Date: Wed, 18 Apr 2007 12:11:05 +0200 Subject: [PATCH] icecube/lite5200b: document wakeup from low-power support Signed-off-by: Domen Puncer diff --git a/doc/README.Lite5200B_low_power b/doc/README.Lite5200B_low_power new file mode 100644 index 0000000..5b04fbb --- /dev/null +++ b/doc/README.Lite5200B_low_power @@ -0,0 +1,22 @@ +Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM) +---------------------------------------------------------- + +Low-power mode as described in Lite5200B User's Manual, means that +with support of MC68HLC908QT1 microcontroller (refered to as QT), +everything but the SDRAM can be powered down. This brings +maximum power saving, while one can still restore previous state +quickly. + +Quick overview where U-Boot comes into the picture: +- OS saves device states +- OS saves wakeup handler address to physical 0x0, puts SDRAM into + self-refresh and signals to QT, it should power down the board +- / board is sleeping here / +- someone presses SW4 (connected to QT) +- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up, + so get SDRAM out of self-refresh and transfer control to OS + wakeup handler +- OS restores device states + +This was tested on Linux with USB and Ethernet in use. Adding +support for other devices is an OS issue. -- cgit v0.10.2