From 85164e0c54f4beaee592f9d25d3f1ed61995bf0f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 1 Nov 2013 08:12:24 -0200 Subject: configs: imx: Make CONFIG_SYS_PROMPT uniform across FSL boards There is no real benefit in adding the board name into U-boot's prompt, so remove the custom CONFIG_SYS_PROMPT definitions so that the standard "=> " prompt is used across FSL boards. Signed-off-by: Fabio Estevam diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index a64bafe..fb564b0 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -68,7 +68,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* U-Boot general configuration */ -#define CONFIG_SYS_PROMPT "MX25PDK U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print buffer sz */ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 07f88ca..22fdb3a 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -14,7 +14,6 @@ /* System configurations */ #define CONFIG_MX28 /* i.MX28 SoC */ #define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK -#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > " /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 8a11461..f223788 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -120,7 +120,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "MX31PDK U-Boot > " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 0fb8320..4b4503c 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -135,7 +135,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "MX35 U-Boot > " #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 10c7ee9..1cff171 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -219,7 +219,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "MX51EVK U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 623bf97..d0b5258 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -135,7 +135,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "MX53EVK U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index ab55fbe..7b735ab 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -177,7 +177,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "MX53LOCO U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 818d7e7..c9618b4 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -120,7 +120,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "MX53SMD U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 2f91a6c..f0a82d1 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -114,7 +114,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "MX6QARM2 U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index f97a37c..79d1f34 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -171,7 +171,6 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT "U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 -- cgit v0.10.2 From ac135f66992f65959fcf8245f2ea8a9109a4a913 Mon Sep 17 00:00:00 2001 From: Michael Heimpold Date: Sun, 3 Nov 2013 22:59:26 +0100 Subject: mxs_gpio: fix the handling in gpio_direction_output() Setting the direction and an output value should be done by 1) set the desired output value, 2) switch to output. If this is done in the inverse order, there can be a glitch on the GPIO line. This patch fixes this by using the order as described above. Signed-off-by: Michael Heimpold Acked-by: Stefano Babic diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index d9a7a3a..da0199b 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -95,10 +95,10 @@ int gpio_direction_output(unsigned gpio, int value) struct mxs_register_32 *reg = (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); - writel(1 << PAD_PIN(gpio), ®->reg_set); - gpio_set_value(gpio, value); + writel(1 << PAD_PIN(gpio), ®->reg_set); + return 0; } -- cgit v0.10.2 From cffe815a7656420884e816bb9110ad052889405a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 3 Nov 2013 22:03:03 -0200 Subject: wandboard: Return the error immediately when ipuv3_fb_init() fails If ipuv3_fb_init() fails, we should return the error immediately. Signed-off-by: Fabio Estevam diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 23a78c1..99150f9 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -230,8 +230,10 @@ int board_video_skip(void) ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); - if (ret) + if (ret) { printf("HDMI cannot be configured: %d\n", ret); + return ret; + } imx_enable_hdmi_phy(); -- cgit v0.10.2 From c243a832c85d832151f647b1f83e6d6120527f34 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 3 Nov 2013 22:03:04 -0200 Subject: wandboard: Return the error when cpu_eth_init() fails When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 99150f9..bf9898c 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -265,7 +265,7 @@ int board_eth_init(bd_t *bis) if (ret) printf("FEC MXC: %s:failed\n", __func__); - return 0; + return ret; } int board_early_init_f(void) -- cgit v0.10.2 From 90fb985863670afd70b7a534df12fd451476a964 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 3 Nov 2013 22:12:56 -0200 Subject: titanium: Return the error when cpu_eth_init() fails When cpu_eth_init() fails we should not return success. Signed-off-by: Fabio Estevam Acked-by: Stefan Roese diff --git a/board/freescale/titanium/titanium.c b/board/freescale/titanium/titanium.c index 6025eb7..9a317bc 100644 --- a/board/freescale/titanium/titanium.c +++ b/board/freescale/titanium/titanium.c @@ -272,7 +272,7 @@ int board_eth_init(bd_t *bis) if (ret) printf("FEC MXC: %s:failed\n", __func__); - return 0; + return ret; } int board_early_init_f(void) -- cgit v0.10.2 From c2cde27d58cfa0b09b8ed4577fa313fdfaa57660 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 4 Nov 2013 08:35:28 +0100 Subject: mx6: titanium: Move BSP code to barco board directory Since the titanium board is not a Freescale board, move its BSP code from the freescale board directory to the newly created barco board directory. Signed-off-by: Stefan Roese Cc: Peter Korsgaard Cc: Stefano Babic Acked-by: Peter Korsgaard diff --git a/board/barco/titanium/Makefile b/board/barco/titanium/Makefile new file mode 100644 index 0000000..0ad4cb9 --- /dev/null +++ b/board/barco/titanium/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := titanium.o diff --git a/board/barco/titanium/imximage.cfg b/board/barco/titanium/imximage.cfg new file mode 100644 index 0000000..7219256 --- /dev/null +++ b/board/barco/titanium/imximage.cfg @@ -0,0 +1,167 @@ +/* + * Projectiondesign AS + * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * sd, nand + */ +BOOT_FROM nand + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c new file mode 100644 index 0000000..9a317bc --- /dev/null +++ b/board/barco/titanium/titanium.c @@ -0,0 +1,323 @@ +/* + * Copyright (C) 2013 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, + ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +static void setup_iomux_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + udelay(1000 * 10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + return 0; +} + +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[1] = { + { USDHC3_BASE_ADDR }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(IMX_GPIO_NR(7, 0)); + return !gpio_get_value(IMX_GPIO_NR(7, 0)); + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + /* + * Only one USDHC controller on titianium + */ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_enet(); + + ret = cpu_eth_init(bis); + if (ret) + printf("FEC MXC: %s:failed\n", __func__); + + return ret; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + setup_gpmi_nand(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: Titanium\n"); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* NAND */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + /* 4 bit bus width */ + { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, + { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, + { NULL, 0 }, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} diff --git a/board/freescale/titanium/Makefile b/board/freescale/titanium/Makefile deleted file mode 100644 index 0ad4cb9..0000000 --- a/board/freescale/titanium/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := titanium.o diff --git a/board/freescale/titanium/imximage.cfg b/board/freescale/titanium/imximage.cfg deleted file mode 100644 index 7219256..0000000 --- a/board/freescale/titanium/imximage.cfg +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Projectiondesign AS - * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg - * - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * Jason Liu - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer docs/README.imxmage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * sd, nand - */ -BOOT_FROM nand - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -#define __ASSEMBLY__ -#include -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 - -DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 - -DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 - -DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 - -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 - -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 - -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 - -/* (differential input) */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* disable ddr pullups */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -/* (differential input) */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* Read data DQ Byte0-3 delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 - -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 -DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/freescale/titanium/titanium.c b/board/freescale/titanium/titanium.c deleted file mode 100644 index 9a317bc..0000000 --- a/board/freescale/titanium/titanium.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright (C) 2013 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, - .gp = IMX_GPIO_NR(7, 11) - } -}; - -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t const enet_pads1[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -iomux_v3_cfg_t nfc_pads[] = { - MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nfc_pads, - ARRAY_SIZE(nfc_pads)); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} - -static void setup_iomux_enet(void) -{ - gpio_direction_output(IMX_GPIO_NR(3, 23), 0); - gpio_direction_output(IMX_GPIO_NR(6, 30), 1); - gpio_direction_output(IMX_GPIO_NR(6, 25), 1); - gpio_direction_output(IMX_GPIO_NR(6, 27), 1); - gpio_direction_output(IMX_GPIO_NR(6, 28), 1); - gpio_direction_output(IMX_GPIO_NR(6, 29), 1); - imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); - gpio_direction_output(IMX_GPIO_NR(6, 24), 1); - - /* Need delay 10ms according to KSZ9021 spec */ - udelay(1000 * 10); - gpio_set_value(IMX_GPIO_NR(3, 23), 1); - - imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); -} - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); -} - -#ifdef CONFIG_USB_EHCI_MX6 -int board_ehci_hcd_init(int port) -{ - return 0; -} - -#endif - -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[1] = { - { USDHC3_BASE_ADDR }, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(IMX_GPIO_NR(7, 0)); - return !gpio_get_value(IMX_GPIO_NR(7, 0)); - } - - return 0; -} - -int board_mmc_init(bd_t *bis) -{ - /* - * Only one USDHC controller on titianium - */ - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif - -int board_phy_config(struct phy_device *phydev) -{ - /* min rx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); - /* min tx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); - /* max rx/tx clock delay, min rx/tx control */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int ret; - - setup_iomux_enet(); - - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); - - return ret; -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - - setup_gpmi_nand(); - - return 0; -} - -int checkboard(void) -{ - puts("Board: Titanium\n"); - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* NAND */ - { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, - /* 4 bit bus width */ - { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, - { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, - { NULL, 0 }, -}; -#endif - -int misc_init_r(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - return 0; -} diff --git a/boards.cfg b/boards.cfg index 36f0924..7a32d3f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -302,7 +302,7 @@ Active arm armv7 mx6 freescale mx6qsabreauto Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam -Active arm armv7 mx6 freescale titanium titanium titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg Stefan Roese +Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat -- cgit v0.10.2 From 10fda48779fc86e74e4482cbc7667431237cf60c Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 4 Nov 2013 17:00:51 -0700 Subject: i.MX6DQ/DLS: replace pad names with their Linux kernel equivalents Signed-off-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 7373407..94f49c0 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -10,399 +10,399 @@ #include enum { - MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_RXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0), MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__SIMBA_TRACE_7 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), + MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__SIMBA_TRACE_8 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 = IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0), MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__SIMBA_TRACE_9 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 = IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_TXD = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0), + MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0), MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__SIMBA_TRACE_10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 = IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_RXD = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0), MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__SIMBA_TRACE_11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 = IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_TXD = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0), + MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0), MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__SIMBA_TRACE_12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 = IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0), + MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0), MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__SIMBA_TRACE_13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 = IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_RTS = IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0), + MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0), MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__SIMBA_TRACE_14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 = IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0), + MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0), MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__SIMBA_TRACE_15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 = IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_RTS = IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0), + MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0), MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0384, 0x0070, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 = IOMUX_PAD(0x0384, 0x0070, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0), - MX6_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0), - MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0), + MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__SIMBA_TRACE_1 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0), - MX6_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0), - MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0), + MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__SIMBA_TRACE_2 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0), - MX6_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0), - MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0), + MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__SIMBA_TRACE_3 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0), - MX6_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0), - MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0), + MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__SIMBA_TRACE_4 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0), - MX6_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0), + MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0), MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0), - MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__SIMBA_TRACE_5 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0), - MX6_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0), + MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0), MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0), - MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__SIMBA_TRACE_6 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 = IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 = IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__SIMBA_TRCLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__SIMBA_TRCTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 = IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__SIMBA_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 = IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__SIMBA_TRACE_0 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_DISP_CLK__LCDIF_CLK = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__LCD_CLK = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__LCD_WR_RWN = IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN15__LCDIF_ENABLE = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__LCD_ENABLE = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0 = IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__LCDIF_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN2__LCDIF_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0), - MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__LCD_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN2__LCD_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0), + MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 = IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__LCDIF_RS = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN3__LCDIF_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__LCD_RS = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN3__LCD_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__LCDIF_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__LCDIF_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), - MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), + MX6_PAD_DI0_PIN3__LCD_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__LCD_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), + MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__LCDIF_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__LCDIF_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__LCD_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT0__LCD_DATA00 = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT1__LCDIF_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT1__LCD_DATA01 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__LCDIF_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__LCD_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21 = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__LCDIF_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT11__LCD_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__LCDIF_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT12__LCD_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__LCDIF_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0), + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT13__LCD_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0), MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__LCDIF_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0), + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT14__LCD_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0), MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__LCDIF_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT15__LCD_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0), MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__LCDIF_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT16__LCD_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0), - MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0), - MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0), + MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0), + MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__LCDIF_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT17__LCD_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0), - MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0), - MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0), + MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0), + MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__LCDIF_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT18__LCD_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0), - MX6_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0), + MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0), + MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__LCDIF_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT19__LCD_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0), - MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0), + MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0), + MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT2__LCDIF_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__LCD_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__LCDIF_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT20__LCD_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0), - MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0), + MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0), MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__LCDIF_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT21__LCD_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0), - MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0), + MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0), MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__LCDIF_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT22__LCD_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0), - MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0), + MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0), MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__LCDIF_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT23__LCD_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0), - MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0), + MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0), MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT3__LCDIF_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT3__LCD_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 = IOMUX_PAD(0x0408, 0x00F4, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__GPIO4_IO24 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT4__LCDIF_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT4__LCD_DATA04 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 = IOMUX_PAD(0x040C, 0x00F8, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__GPIO4_IO25 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15 = IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT5__LCDIF_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT5__LCD_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16 = IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT6__LCDIF_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT6__LCD_DATA06 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17 = IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT7__LCDIF_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT7__LCD_DATA07 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 = IOMUX_PAD(0x0418, 0x0104, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__GPIO4_IO28 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT8__LCDIF_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT8__LCD_DATA08 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT9__LCDIF_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT9__LCD_DATA09 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, 0), @@ -516,635 +516,635 @@ enum { MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x04D4, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x04D8, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x04DC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0), MX6_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 = IOMUX_PAD(0x04E0, 0x0110, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0), MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x04E0, 0x0110, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__EPDC_SDDO_0 = IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_CSI1_D_12 = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0), + MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A16__EPDC_DATA00 = IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A17__IPU1_CSI1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0), MX6_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 = IOMUX_PAD(0x04E4, 0x0114, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0), MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x04E4, 0x0114, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__EPDC_PWRSTAT = IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_CSI1_D_13 = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0), + MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A17__EPDC_PWR_STAT = IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A18__IPU1_CSI1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0), MX6_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 = IOMUX_PAD(0x04E8, 0x0118, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0), MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x04E8, 0x0118, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__EPDC_PWRCTRL_0 = IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_CSI1_D_14 = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0), + MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A18__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A19__IPU1_CSI1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0), MX6_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 = IOMUX_PAD(0x04EC, 0x011C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0), MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x04EC, 0x011C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__EPDC_PWRCTRL_1 = IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_CSI1_D_15 = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0), + MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A19__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0), MX6_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 = IOMUX_PAD(0x04F0, 0x0120, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0), MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x04F0, 0x0120, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__EPDC_PWRCTRL_2 = IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_CSI1_D_16 = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0), + MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A20__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A21__IPU1_CSI1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0), MX6_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 = IOMUX_PAD(0x04F4, 0x0124, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0), MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x04F4, 0x0124, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0), MX6_PAD_EIM_A21__EPDC_GDCLK = IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_CSI1_D_17 = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0), - MX6_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A22__IPU1_CSI1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0), + MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0), MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x04F8, 0x0128, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0), MX6_PAD_EIM_A22__EPDC_GDSP = IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_CSI1_D_18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0), - MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU1_CSI1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0), + MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0), MX6_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3 = IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0), MX6_PAD_EIM_A23__EPDC_GDOE = IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_CSI1_D_19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0), - MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU1_CSI1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0), + MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0), MX6_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2 = IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0), MX6_PAD_EIM_A24__EPDC_GDRL = IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, 0), MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, 0), MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0), MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0), MX6_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0 = IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A25__EPDC_SDDO_15 = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A25__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A25__EPDC_DATA15 = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0), + MX6_PAD_EIM_A25__EIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x0508, 0x0138, 6, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EPDC_SDCE_9 = IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__EPDC_SDCE9 = IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0), MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 = IOMUX_PAD(0x050C, 0x013C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0), MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x050C, 0x013C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__EPDC_SDDO_6 = IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__EPDC_DATA06 = IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0), MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 = IOMUX_PAD(0x0510, 0x0140, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0), MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0510, 0x0140, 6, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__EPDC_SDDO_8 = IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__EPDC_DATA08 = IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0), MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0), - MX6_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU1_CSI1_D_18 = IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0), + MX6_PAD_EIM_D16__IPU1_DI0_PIN05 = IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D16__IPU1_CSI1_DATA18 = IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0), MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0), - MX6_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0), MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0), MX6_PAD_EIM_D16__TPSMP_HTRANS_0 = IOMUX_PAD(0x0514, 0x0144, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D16__EPDC_SDDO_10 = IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D16__EPDC_DATA10 = IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0), MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0), - MX6_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D17__IPU1_DI0_PIN06 = IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0), MX6_PAD_EIM_D17__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, 0), - MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0), MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0), MX6_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1 = IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D17__EPDC_VCOM_0 = IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D17__EPDC_VCOM0 = IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0), - MX6_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU1_CSI1_D_17 = IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0), + MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D18__IPU1_CSI1_DATA17 = IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0), MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0), MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0), MX6_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2 = IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D18__EPDC_VCOM_1 = IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D18__EPDC_VCOM1 = IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0), MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0), - MX6_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU1_CSI1_D_16 = IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0), - MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D19__UART1_RTS = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0), - MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D19__IPU1_CSI1_DATA16 = IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0), + MX6_PAD_EIM_D19__UART1_CTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0), + MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0), MX6_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP = IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPDC_SDDO_12 = IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EPDC_DATA12 = IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0), MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0), MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU1_CSI1_D_15 = IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0), - MX6_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0), - MX6_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0), + MX6_PAD_EIM_D20__UART1_CTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0), + MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D20__EPIT2_OUT = IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0), MX6_PAD_EIM_D20__TPSMP_HTRANS_1 = IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0), MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_CSI1_D_11 = IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0), - MX6_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0), - MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D21__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0), + MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0), + MX6_PAD_EIM_D21__GPIO3_IO21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0), - MX6_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0), - MX6_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D21__SPDIF_IN = IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0), + MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_CSI1_D_10 = IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0), - MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU1_DI0_PIN01 = IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU1_CSI1_DATA10 = IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0), + MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0), MX6_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE = IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D22__EPDC_SDCE_6 = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D22__EPDC_SDCE6 = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_RTS = IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, 0), - MX6_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D23__UART3_CTS_B = IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D23__UART3_RTS_B = IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, 0), + MX6_PAD_EIM_D23__UART1_DCD_B = IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, 0), - MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D23__GPIO3_IO23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D23__IPU1_DI1_PIN02 = IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D23__EPDC_SDDO_11 = IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D23__EPDC_DATA11 = IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D24__EIM_DATA24 = IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, 0), MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_RXD = IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, 0), + MX6_PAD_EIM_D24__UART3_TX_DATA = IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D24__UART3_RX_DATA = IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, 0), MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0), MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0), - MX6_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__EPDC_SDCE_7 = IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D24__GPIO3_IO24 = IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0), + MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D24__EPDC_SDCE7 = IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0), MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_TXD = IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, 0), + MX6_PAD_EIM_D25__UART3_TX_DATA = IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D25__UART3_RX_DATA = IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, 0), MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0), MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0), - MX6_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__EPDC_SDCE_8 = IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D25__GPIO3_IO25 = IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0), + MX6_PAD_EIM_D25__UART1_DSR_B = IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D25__EPDC_SDCE8 = IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI1_D_14 = IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0), - MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D26__UART2_RXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0), - MX6_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_CSI1_DATA14 = IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0), + MX6_PAD_EIM_D26__UART2_TX_DATA = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D26__UART2_RX_DATA = IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0), + MX6_PAD_EIM_D26__GPIO3_IO26 = IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_SISG2 = IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 = IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0), MX6_PAD_EIM_D26__EPDC_SDOED = IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI1_D_13 = IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0), - MX6_PAD_EIM_D27__UART2_TXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), - MX6_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_CSI1_DATA13 = IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0), + MX6_PAD_EIM_D27__UART2_TX_DATA = IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), + MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_SISG3 = IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 = IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0), MX6_PAD_EIM_D27__EPDC_SDOE = IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0), MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0), MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_CSI1_D_12 = IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0), - MX6_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D28__UART2_RTS = IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0), - MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D28__IPU1_CSI1_DATA12 = IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0), + MX6_PAD_EIM_D28__UART2_DTE_RTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0), + MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__EPDC_PWRCTRL_3 = IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D28__EPDC_PWR_CTRL3 = IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D29__EIM_DATA29 = IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, 0), MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, 0), MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, 0), - MX6_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, 0), - MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D29__UART2_CTS_B = IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D29__UART2_RTS_B = IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, 0), + MX6_PAD_EIM_D29__GPIO3_IO29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0), MX6_PAD_EIM_D29__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, 0), MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__EPDC_PWRWAKE = IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D29__EPDC_PWR_WAKE = IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0), MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_RTS = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0), - MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0), + MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D30__UART3_CTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0), + MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0), MX6_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0 = IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0), MX6_PAD_EIM_D30__EPDC_SDOEZ = IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0), MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0), - MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D31__UART3_CTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0), + MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0), MX6_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1 = IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D31__EPDC_SDCLK = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D31__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_CSI1_D_9 = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D31__EPDC_SDCLK_P = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0), + MX6_PAD_EIM_D31__EIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU1_CSI1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 = IOMUX_PAD(0x0554, 0x0184, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0554, 0x0184, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EPDC_SDCLKN = IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_CSI1_D_8 = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__EPDC_SDCLK_N = IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU1_CSI1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 = IOMUX_PAD(0x0558, 0x0188, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE = IOMUX_PAD(0x0558, 0x0188, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x0558, 0x0188, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA1__EPDC_SDLE = IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0), MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 = IOMUX_PAD(0x055C, 0x018C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x055C, 0x018C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EPDC_SDDO_1 = IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__EPDC_DATA01 = IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC = IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0), MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 = IOMUX_PAD(0x0560, 0x0190, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 = IOMUX_PAD(0x0560, 0x0190, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0560, 0x0190, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EPDC_SDDO_3 = IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__EPDC_DATA03 = IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0), MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 = IOMUX_PAD(0x0564, 0x0194, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 = IOMUX_PAD(0x0564, 0x0194, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0564, 0x0194, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EPDC_SDDO_2 = IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__EPDC_DATA02 = IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x0568, 0x0198, 2, 0x07D0, 0, 0), MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 = IOMUX_PAD(0x0568, 0x0198, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 = IOMUX_PAD(0x0568, 0x0198, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x0568, 0x0198, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EPDC_SDDO_13 = IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__EPDC_DATA13 = IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x056C, 0x019C, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 = IOMUX_PAD(0x056C, 0x019C, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 = IOMUX_PAD(0x056C, 0x019C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x056C, 0x019C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EPDC_SDDO_14 = IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__EPDC_DATA14 = IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 = IOMUX_PAD(0x0570, 0x01A0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0570, 0x01A0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EPDC_SDDO_9 = IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_CSI1_D_7 = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__EPDC_DATA09 = IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU1_CSI1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 = IOMUX_PAD(0x0574, 0x01A4, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE = IOMUX_PAD(0x0574, 0x01A4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0574, 0x01A4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EPDC_BDR_0 = IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_CSI1_D_6 = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__EPDC_BDR0 = IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU1_CSI1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 = IOMUX_PAD(0x0578, 0x01A8, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ = IOMUX_PAD(0x0578, 0x01A8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0578, 0x01A8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EPDC_BDR_1 = IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_CSI1_D_5 = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__EPDC_BDR1 = IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU1_CSI1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 = IOMUX_PAD(0x057C, 0x01AC, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN = IOMUX_PAD(0x057C, 0x01AC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x057C, 0x01AC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EPDC_SDCE_0 = IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_CSI1_D_4 = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__EPDC_SDCE0 = IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU1_CSI1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 = IOMUX_PAD(0x0580, 0x01B0, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP = IOMUX_PAD(0x0580, 0x01B0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x0580, 0x01B0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EPDC_SDCE_1 = IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_CSI1_D_3 = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__EPDC_SDCE1 = IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU1_CSI1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 = IOMUX_PAD(0x0584, 0x01B4, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN = IOMUX_PAD(0x0584, 0x01B4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0584, 0x01B4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EPDC_SDCE_2 = IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_CSI1_D_2 = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__EPDC_SDCE2 = IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU1_CSI1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 = IOMUX_PAD(0x0588, 0x01B8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0588, 0x01B8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EPDC_SDCE_3 = IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_CSI1_D_1 = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__EPDC_SDCE3 = IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU1_CSI1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 = IOMUX_PAD(0x058C, 0x01BC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x058C, 0x01BC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EPDC_SDCE_4 = IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_CSI1_D_0 = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__EPDC_SDCE4 = IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU1_CSI1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 = IOMUX_PAD(0x0590, 0x01C0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x0590, 0x01C0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EPDC_SDCE_5 = IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_CSI1_D_11 = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0), + MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__EPDC_SDCE5 = IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0), MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 = IOMUX_PAD(0x0594, 0x01C4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0), - MX6_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0), + MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0594, 0x01C4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__EPDC_PWRCOM = IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_CSI1_D_10 = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0), + MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__EPDC_PWR_COM = IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__IPU1_CSI1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0), MX6_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 = IOMUX_PAD(0x0598, 0x01C8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0598, 0x01C8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0), MX6_PAD_EIM_EB1__EPDC_SDSHR = IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, 0), MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x059C, 0x01CC, 2, 0x07D0, 1, 0), - MX6_PAD_EIM_EB2__IPU1_CSI1_D_19 = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0), + MX6_PAD_EIM_EB2__IPU1_CSI1_DATA19 = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0), MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0), - MX6_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0), - MX6_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__EPDC_SDDO_5 = IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__SRC_BOOT_CFG30 = IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__EPDC_DATA05 = IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__EIM_EB3_B = IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, 0), - MX6_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__UART3_CTS_B = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__UART3_RTS_B = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, 0), + MX6_PAD_EIM_EB3__UART1_RI_B = IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, 0), MX6_PAD_EIM_EB3__IPU1_CSI1_HSYNC = IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, 0), - MX6_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EPDC_SDCE_0 = IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__WEIM_ACLK_FREERUN = IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__GPIO2_IO31 = IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__IPU1_DI1_PIN03 = IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__SRC_BOOT_CFG31 = IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__EPDC_SDCE0 = IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__EIM_ACLK_FREERUN = IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__EIM_LBA_B = IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0), MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0), MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0), - MX6_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0), MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x05A4, 0x01D4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__EPDC_SDDO_4 = IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__EPDC_DATA04 = IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0), + MX6_PAD_EIM_OE__EIM_OE_B = IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0), MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0), MX6_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 = IOMUX_PAD(0x05A8, 0x01D8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0), MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x05A8, 0x01D8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_OE__EPDC_PWRIRQ = IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_OE__EPDC_PWR_IRQ = IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0), + MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0), MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0), MX6_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 = IOMUX_PAD(0x05AC, 0x01DC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0), MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x05AC, 0x01DC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EPDC_SDDO_7 = IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_RW__EPDC_DATA07 = IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x05B0, 0x01E0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0), - MX6_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0), - MX6_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0), - MX6_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0), + MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0), + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x05B4, 0x01E4, 6, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD = IOMUX_PAD(0x05B4, 0x01E4, 7, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0), + MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0), MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0), + MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0), MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET = IOMUX_PAD(0x05B8, 0x01E8, 7, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0), - MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0), + MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0), MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x05BC, 0x01EC, 3, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0), + MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0), MX6_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x05C0, 0x01F0, 3, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH = IOMUX_PAD(0x05C0, 0x01F0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ANATOP_USBOTG_ID = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0), + MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0), MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0), - MX6_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0), + MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0), + MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0), MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT = IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x05C4, 0x01F4, 6, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD = IOMUX_PAD(0x05C4, 0x01F4, 7, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0), - MX6_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0), - MX6_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0), + MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0), + MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0), - MX6_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0), + MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0), + MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0), MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0), - MX6_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0), + MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__I2C4_SCL = IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0), - MX6_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0), + MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0), + MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0), MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__I2C4_SDA = IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0), - MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0), - MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0), - MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0), - MX6_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0), + MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0), + MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0), + MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0), + MX6_PAD_GPIO_0__EPIT1_OUT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_0__GPIO1_IO00 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_1__ESAI_RX_CLK = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0), + MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_1__KEY_ROW5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0), MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0), - MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0), + MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0), MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0), - MX6_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0), - MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0), + MX6_PAD_GPIO_16__SD1_LCTL = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_16__SPDIF_IN = IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0), + MX6_PAD_GPIO_16__GPIO7_IO11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0), - MX6_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, 0), + MX6_PAD_GPIO_16__JTAG_DE_B = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_17__ESAI_TX0 = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, 0), MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0), - MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0), - MX6_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_17__CCM_PMIC_READY = IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0), + MX6_PAD_GPIO_17__SDMA_EXT_EVENT0 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0), + MX6_PAD_GPIO_17__SPDIF_OUT = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0), + MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0), MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0), - MX6_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0), - MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0), - MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0), + MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0), + MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0), + MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0), MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_19__CCM_CLKO1 = IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0), MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_19__GPIO4_IO05 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0), + MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0), MX6_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0), + MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0), MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0), - MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0), + MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0), + MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0), MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0), - MX6_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0), - MX6_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0), - MX6_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0), + MX6_PAD_GPIO_3__GPIO1_IO03 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0), + MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0), + MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0), MX6_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0), + MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0), MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_4__SD2_CD_B = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0), MX6_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0), + MX6_PAD_GPIO_5__ESAI_TX2_RX3 = IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0), MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0), - MX6_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_5__KEY_ROW7 = IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0), + MX6_PAD_GPIO_5__CCM_CLKO1 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_5__GPIO1_IO05 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0), - MX6_PAD_GPIO_5__SIMBA_EVENTI = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0), + MX6_PAD_GPIO_5__ARM_EVENTI = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0), MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0), MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0), - MX6_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0), - MX6_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_RXD = IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, 0), - MX6_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0), + MX6_PAD_GPIO_7__ESAI_TX4_RX1 = IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0), + MX6_PAD_GPIO_7__EPIT1_OUT = IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_7__FLEXCAN1_TX = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_7__UART2_TX_DATA = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_7__UART2_RX_DATA = IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, 0), + MX6_PAD_GPIO_7__GPIO1_IO07 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_7__SPDIF_LOCK = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_7__USB_OTG_HOST_MODE = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), MX6_PAD_GPIO_7__I2C4_SCL = IOMUX_PAD(0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0), - MX6_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0), - MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0), - MX6_PAD_GPIO_8__UART2_TXD = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, 0), - MX6_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_8__ESAI_TX5_RX0 = IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0), + MX6_PAD_GPIO_8__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_8__EPIT2_OUT = IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_8__FLEXCAN1_RX = IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0), + MX6_PAD_GPIO_8__UART2_TX_DATA = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_8__UART2_RX_DATA = IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, 0), + MX6_PAD_GPIO_8__GPIO1_IO08 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_8__SPDIF_SR_CLK = IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), MX6_PAD_GPIO_8__I2C4_SDA = IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0), - MX6_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0), + MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0), + MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0), MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0), + MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0), MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x0614, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0618, NO_MUX_I, 0, 0x0000, 0, 0), @@ -1153,89 +1153,89 @@ enum { MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0624, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0628, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0), - MX6_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0), - MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0), - MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_RXD = IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0), - MX6_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0), + MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0), + MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART4_TX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0), + MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x062C, 0x0244, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0), MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, 0), - MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0), - MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_RXD = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0), - MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0), + MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART5_TX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0), + MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1 = IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0), - MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0), - MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0), + MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP = IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3 = IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0), MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0), MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, 0), - MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0), - MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0), + MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0), MX6_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5 = IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0), - MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0), - MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0), + MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0), + MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 = IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7 = IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0), - MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0), - MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_TXD = IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0), - MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0), + MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__UART4_TX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0), + MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0 = IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0), MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0), - MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_TXD = IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0), - MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0), + MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__UART5_TX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0), + MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2 = IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0), - MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0), - MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0), + MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0), MX6_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4 = IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0), + MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0), MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0), - MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), - MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6 = IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0), - MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_RTS = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0), - MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0), + MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0), + MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 = IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8 = IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0), MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), @@ -1248,117 +1248,117 @@ enum { MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 = IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 = IOMUX_PAD(0x0654, 0x026C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 = IOMUX_PAD(0x0654, 0x026C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 = IOMUX_PAD(0x0654, 0x026C, 6, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__USDHC3_CLKI = IOMUX_PAD(0x0654, 0x026C, 8, 0x0934, 0, 0), - MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__NAND_CLE = IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 = IOMUX_PAD(0x0658, 0x0270, 2, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 = IOMUX_PAD(0x0658, 0x0270, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 = IOMUX_PAD(0x0658, 0x0270, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__GPIO6_IO07 = IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 = IOMUX_PAD(0x0658, 0x0270, 6, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__USDHC3_CLKO = IOMUX_PAD(0x0658, 0x0270, 8, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 = IOMUX_PAD(0x065C, 0x0274, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 = IOMUX_PAD(0x065C, 0x0274, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__USDHC1_CLKO = IOMUX_PAD(0x065C, 0x0274, 8, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 = IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT = IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__USDHC1_CLKI = IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, 0), - MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0), - MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0), + MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__USDHC2_CLKO = IOMUX_PAD(0x0664, 0x027C, 8, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0), - MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0), + MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 = IOMUX_PAD(0x0668, 0x0280, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x0668, 0x0280, 7, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__USDHC2_CLKI = IOMUX_PAD(0x0668, 0x0280, 8, 0x0930, 0, 0), MX6_PAD_NANDF_CS3__I2C4_SDA = IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0), - MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__SD1_DATA4 = IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x066C, 0x0284, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 = IOMUX_PAD(0x066C, 0x0284, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 = IOMUX_PAD(0x066C, 0x0284, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__GPIO2_IO00 = IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x066C, 0x0284, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__NAND_DATA01 = IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__SD1_DATA5 = IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x0670, 0x0288, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 = IOMUX_PAD(0x0670, 0x0288, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 = IOMUX_PAD(0x0670, 0x0288, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__GPIO2_IO01 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x0670, 0x0288, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__NAND_DATA02 = IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__SD1_DATA6 = IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x0674, 0x028C, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 = IOMUX_PAD(0x0674, 0x028C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 = IOMUX_PAD(0x0674, 0x028C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__GPIO2_IO02 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x0674, 0x028C, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__NAND_DATA03 = IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__SD1_DATA7 = IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x0678, 0x0290, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 = IOMUX_PAD(0x0678, 0x0290, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 = IOMUX_PAD(0x0678, 0x0290, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__GPIO2_IO03 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x0678, 0x0290, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__NAND_DATA04 = IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__SD2_DATA4 = IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x067C, 0x0294, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 = IOMUX_PAD(0x067C, 0x0294, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 = IOMUX_PAD(0x067C, 0x0294, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__GPIO2_IO04 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x067C, 0x0294, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__NAND_DATA05 = IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__SD2_DATA5 = IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x0680, 0x0298, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 = IOMUX_PAD(0x0680, 0x0298, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 = IOMUX_PAD(0x0680, 0x0298, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__GPIO2_IO05 = IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x0680, 0x0298, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__NAND_DATA06 = IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__SD2_DATA6 = IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x0684, 0x029C, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 = IOMUX_PAD(0x0684, 0x029C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 = IOMUX_PAD(0x0684, 0x029C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__GPIO2_IO06 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x0684, 0x029C, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x0688, 0x02A0, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 = IOMUX_PAD(0x0688, 0x02A0, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 = IOMUX_PAD(0x0688, 0x02A0, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0688, 0x02A0, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 = IOMUX_PAD(0x068C, 0x02A4, 2, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 = IOMUX_PAD(0x068C, 0x02A4, 3, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 = IOMUX_PAD(0x068C, 0x02A4, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 = IOMUX_PAD(0x068C, 0x02A4, 6, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__USDHC4_CLKI = IOMUX_PAD(0x068C, 0x02A4, 8, 0x0938, 0, 0), - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USDHC4_CLKO = IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__I2C4_SCL = IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0), @@ -1366,305 +1366,305 @@ enum { MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), - MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), + MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), - MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), + MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), - MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), + MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), - MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), + MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0), - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE_START = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), - MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), + MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), + MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), + MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0), - MX6_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0), - MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0), + MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0), + MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0), + MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0), MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO1_IO20 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__PWM4_OUT = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO1_IO18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__SD1_DATA0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS = IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__GPT_CAPTURE1 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__GPIO1_IO16 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x06CC, 0x02E4, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__PWM3_OUT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__GPT_CAPTURE2 = IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__GPIO1_IO17 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x06D0, 0x02E8, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__SD1_DATA2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__GPT_COMPARE2 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__PWM2_OUT = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__WDOG1_B = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__GPIO1_IO19 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__WDOG1_RESET_B_DEB = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 = IOMUX_PAD(0x06D4, 0x02EC, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__SD1_DATA3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPT_COMPARE3 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__PWM1_OUT = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__WDOG2_B = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPIO1_IO21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0), - MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0), - MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0), + MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0), + MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0), + MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0), MX6_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x06DC, 0x02F4, 6, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0), - MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0), + MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0), + MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0), MX6_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0), - MX6_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0), - MX6_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0), + MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0), + MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0), - MX6_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0), - MX6_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0), + MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0), + MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0), - MX6_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0), - MX6_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0), + MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0), + MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0), - MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0), + MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0), + MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0), MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), - MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0), - MX6_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0), + MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), + MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__UART2_RTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0), + MX6_PAD_SD3_CLK__FLEXCAN1_RX = IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0), MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__GPIO7_IO03 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), MX6_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_RTS = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0), - MX6_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__UART2_CTS_B = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0), + MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__GPIO7_IO02 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), MX6_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_RTS = IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0), - MX6_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__UART1_CTS_B = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0), + MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__GPIO7_IO04 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0), - MX6_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0), + MX6_PAD_SD3_DAT1__SD3_DATA1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__UART1_CTS_B = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__UART1_RTS_B = IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0), + MX6_PAD_SD3_DAT1__FLEXCAN2_RX = IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0), MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__GPIO7_IO05 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__SD3_DATA2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__GPIO7_IO06 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_RTS = IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0), + MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__UART3_CTS_B = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0), MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__GPIO7_IO07 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_TXD = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0), + MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__UART2_TX_DATA = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0), MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__GPIO7_IO01 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_RXD = IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0), + MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0), MX6_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 = IOMUX_PAD(0x0710, 0x0328, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_TXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), + MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__UART1_TX_DATA = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), MX6_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 = IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_RXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0), + MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0), MX6_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0), + MX6_PAD_SD3_RST__SD3_RESET = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), + MX6_PAD_SD3_RST__UART3_CTS_B = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), + MX6_PAD_SD3_RST__UART3_RTS_B = IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0), MX6_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 = IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0), MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), - MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), + MX6_PAD_SD3_RST__GPIO7_IO08 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), MX6_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), - MX6_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0), + MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), + MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__UART3_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0), MX6_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_RXD = IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0), + MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__NAND_RE_B = IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__UART3_TX_DATA = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__UART3_RX_DATA = IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0), MX6_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__GPIO7_IO09 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__SD4_DATA0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__NAND_DQS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__GPIO2_IO08 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__SD4_DATA1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__PWM3_OUT = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__GPIO2_IO09 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x0730, 0x0348, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__SD4_DATA2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__PWM4_OUT = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 = IOMUX_PAD(0x0730, 0x0348, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__GPIO2_IO10 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x0730, 0x0348, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__SD4_DATA3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__GPIO2_IO11 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_TXD = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0), + MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__UART2_TX_DATA = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0), MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 = IOMUX_PAD(0x0738, 0x0350, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__GPIO2_IO12 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0), + MX6_PAD_SD4_DAT5__SD4_DATA5 = IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__UART2_CTS_B = IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__UART2_RTS_B = IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0), MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 = IOMUX_PAD(0x073C, 0x0354, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__GPIO2_IO13 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x0740, 0x0358, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_RTS = IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0), + MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__UART2_CTS_B = IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0), MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 = IOMUX_PAD(0x0740, 0x0358, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x0740, 0x0358, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_RXD = IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0), + MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0), MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 = IOMUX_PAD(0x0744, 0x035C, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index fe9a8c3..a85a5fd 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -12,772 +12,772 @@ #include enum { - MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0), - MX6_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), - MX6_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), - MX6_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), + MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), + MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0), - MX6_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), - MX6_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), - MX6_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), + MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), + MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0), - MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), - MX6_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), - MX6_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), + MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), + MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), - MX6_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), + MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0), - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), - MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), + MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), - MX6_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), - MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), + MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), + MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), - MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), + MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), - MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), + MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), - MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), + MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0), MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0), MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0), MX6_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0), MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0), - MX6_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), + MX6_PAD_EIM_EB2__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0), - MX6_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0), - MX6_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__SRC_BOOT_CFG30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0), - MX6_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), + MX6_PAD_EIM_D16__IPU1_DI0_PIN05 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D16__IPU2_CSI1_DATA18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0), - MX6_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0), - MX6_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0), - MX6_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D17__IPU1_DI0_PIN06 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0), - MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0), MX6_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0), - MX6_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), + MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D18__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0), MX6_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), - MX6_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), - MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), - MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D19__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), + MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), + MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), MX6_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0), MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), - MX6_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), - MX6_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), + MX6_PAD_EIM_D20__UART1_CTS_B = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), + MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D20__EPIT2_OUT = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0), MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), - MX6_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), - MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D21__IPU2_CSI1_DATA11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), + MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), + MX6_PAD_EIM_D21__GPIO3_IO21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0), - MX6_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), - MX6_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D21__SPDIF_IN = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), + MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), - MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU1_DI0_PIN01 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU2_CSI1_DATA10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), + MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), - MX6_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D23__UART3_RTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), + MX6_PAD_EIM_D23__UART1_DCD_B = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0), - MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D23__GPIO3_IO23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D23__IPU1_DI1_PIN02 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__EIM_EB3_B = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), - MX6_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__UART3_CTS_B = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__UART3_RTS_B = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), + MX6_PAD_EIM_EB3__UART1_RI_B = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), MX6_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0), - MX6_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__GPIO2_IO31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__IPU1_DI1_PIN03 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__SRC_BOOT_CFG31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D24__EIM_DATA24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), + MX6_PAD_EIM_D24__UART3_TX_DATA = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D24__UART3_RX_DATA = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0), MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), - MX6_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D24__GPIO3_IO24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), + MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), + MX6_PAD_EIM_D25__UART3_RX_DATA = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0), MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), - MX6_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D25__GPIO3_IO25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), + MX6_PAD_EIM_D25__UART1_DSR_B = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), - MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), - MX6_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), + MX6_PAD_EIM_D26__UART2_TX_DATA = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D26__UART2_RX_DATA = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), + MX6_PAD_EIM_D26__GPIO3_IO26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_SISG2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), - MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), - MX6_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU2_CSI1_DATA13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), + MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), + MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_SISG3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0), MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), - MX6_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), - MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D28__IPU2_CSI1_DATA12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), + MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), + MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D29__EIM_DATA29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0), - MX6_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), - MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D29__UART2_CTS_B = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D29__UART2_RTS_B = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), + MX6_PAD_EIM_D29__GPIO3_IO29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0), MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), - MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), + MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), + MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), MX6_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), - MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D31__UART3_CTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), + MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), MX6_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), - MX6_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), + MX6_PAD_EIM_A24__IPU2_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), MX6_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), - MX6_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU2_CSI1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), + MX6_PAD_EIM_A23__IPU2_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), MX6_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), - MX6_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A22__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), + MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), + MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A21__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), MX6_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), MX6_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), + MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), MX6_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0), MX6_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), + MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A19__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), MX6_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0), MX6_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), + MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A18__IPU2_CSI1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), MX6_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0), MX6_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), + MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A17__IPU2_CSI1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), MX6_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0), MX6_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0), MX6_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0), MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0), MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), - MX6_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_EIM_OE__EIM_OE_B = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0), MX6_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), - MX6_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), - MX6_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), - MX6_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0), MX6_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), - MX6_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), - MX6_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__EIM_LBA_B = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0), - MX6_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), + MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__IPU2_CSI1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), - MX6_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), + MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), + MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__IPU2_CSI1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), MX6_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU2_CSI1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU2_CSI1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU2_CSI1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU2_CSI1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU2_CSI1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU2_CSI1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU2_CSI1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU2_CSI1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU2_CSI1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU2_CSI1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0), MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0), MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0), MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__IPU2_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT3__GPIO4_IO24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT4__GPIO4_IO25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT7__GPIO4_IO28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), MX6_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), MX6_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), MX6_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0), - MX6_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), - MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), - MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), + MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), + MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0), - MX6_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), - MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), - MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), + MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), + MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), - MX6_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), - MX6_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), + MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), + MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), - MX6_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), - MX6_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), + MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), + MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), + MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), MX6_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), + MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), MX6_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), + MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), MX6_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), + MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), MX6_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0), - MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), + MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), + MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), MX6_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), - MX6_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), - MX6_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), + MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), + MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), - MX6_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), - MX6_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), - MX6_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), + MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), - MX6_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), - MX6_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), + MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), + MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), + MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), - MX6_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), - MX6_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), + MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), + MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), + MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), - MX6_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), + MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), + MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), - MX6_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), + MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), + MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), + MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0), MX6_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0), MX6_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), @@ -892,357 +892,357 @@ enum { MX6_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), - MX6_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), - MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), - MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), - MX6_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), + MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), + MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART4_TX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), + MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0), - MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), - MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), - MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), + MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), + MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0), MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0), - MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), - MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), - MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), + MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART5_TX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), + MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0), MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), - MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), - MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), + MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), + MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0), - MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), - MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), + MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0), - MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), - MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), + MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0), MX6_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0), MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0), - MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0), - MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), + MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), MX6_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), + MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0), - MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0), - MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), - MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), - MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), + MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), + MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), - MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), - MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), + MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), + MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), - MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), - MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), - MX6_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), - MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), + MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), + MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), + MX6_PAD_GPIO_0__EPIT1_OUT = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_0__GPIO1_IO00 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_1__ESAI_RX_CLK = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), + MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_1__KEY_ROW5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), + MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), + MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), + MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), + MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), + MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), MX6_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0), - MX6_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), - MX6_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), - MX6_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), + MX6_PAD_GPIO_3__GPIO1_IO03 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), + MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), + MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), MX6_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0), MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), - MX6_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), + MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), + MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), MX6_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), + MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), - MX6_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), + MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), + MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), MX6_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), + MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_4__SD2_CD_B = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), MX6_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), + MX6_PAD_GPIO_5__ESAI_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), MX6_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), - MX6_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_5__KEY_ROW7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), + MX6_PAD_GPIO_5__CCM_CLKO1 = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_5__GPIO1_IO05 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0), - MX6_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0), + MX6_PAD_GPIO_5__ARM_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_7__ESAI_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0), MX6_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0), - MX6_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0), - MX6_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), - MX6_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), - MX6_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), + MX6_PAD_GPIO_7__EPIT1_OUT = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_7__FLEXCAN1_TX = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_7__UART2_TX_DATA = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_7__UART2_RX_DATA = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0), + MX6_PAD_GPIO_7__GPIO1_IO07 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_7__SPDIF_LOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_7__USB_OTG_HOST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_8__ESAI_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0), + MX6_PAD_GPIO_8__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_8__EPIT2_OUT = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_8__FLEXCAN1_RX = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), + MX6_PAD_GPIO_8__UART2_RX_DATA = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), + MX6_PAD_GPIO_8__GPIO1_IO08 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_8__SPDIF_SR_CLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), - MX6_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), - MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), + MX6_PAD_GPIO_16__SD1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_16__SPDIF_IN = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), + MX6_PAD_GPIO_16__GPIO7_IO11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0), - MX6_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0), + MX6_PAD_GPIO_16__JTAG_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_17__ESAI_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0), MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0), - MX6_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), - MX6_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_17__CCM_PMIC_READY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0), + MX6_PAD_GPIO_17__SDMA_EXT_EVENT0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), + MX6_PAD_GPIO_17__SPDIF_OUT = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), + MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0), - MX6_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), - MX6_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), - MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), + MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), + MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), + MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_19__CCM_CLKO1 = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0), MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), + MX6_PAD_GPIO_19__GPIO4_IO05 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0), MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0), - MX6_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), - MX6_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), + MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0), - MX6_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), - MX6_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), + MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0), - MX6_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), - MX6_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), + MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0), - MX6_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), - MX6_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), + MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0), - MX6_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), + MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0), - MX6_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0), - MX6_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), + MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0), - MX6_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), - MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), - MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), + MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), + MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), + MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), + MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), + MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), + MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0), MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0), @@ -1269,362 +1269,362 @@ enum { MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), + MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), MX6_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), + MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), MX6_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), + MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), MX6_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), + MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), MX6_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__GPIO7_IO01 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), - MX6_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), + MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0), MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__GPIO7_IO02 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), MX6_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), - MX6_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), + MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__UART2_RTS_B = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), + MX6_PAD_SD3_CLK__FLEXCAN1_RX = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0), MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__GPIO7_IO03 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), MX6_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), - MX6_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), + MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__GPIO7_IO04 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), - MX6_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), + MX6_PAD_SD3_DAT1__SD3_DATA1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__UART1_CTS_B = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__UART1_RTS_B = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), + MX6_PAD_SD3_DAT1__FLEXCAN2_RX = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__GPIO7_IO05 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__SD3_DATA2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__GPIO7_IO06 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), + MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), MX6_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__GPIO7_IO07 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), + MX6_PAD_SD3_RST__SD3_RESET = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), + MX6_PAD_SD3_RST__UART3_CTS_B = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), + MX6_PAD_SD3_RST__UART3_RTS_B = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), MX6_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0), MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0), MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0), - MX6_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), + MX6_PAD_SD3_RST__GPIO7_IO08 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), MX6_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__NAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__IPU2_SISG4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CLE__GPIO6_IO07 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__IPU2_SISG5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__IPU2_DI0_PIN01 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), - MX6_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), + MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU2_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), - MX6_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__IPU2_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), + MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__IPU2_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), + MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__NAND_RE_B = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__UART3_TX_DATA = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__UART3_RX_DATA = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), MX6_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), + MX6_PAD_SD4_CMD__GPIO7_IO09 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), + MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), MX6_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__SD1_DATA4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D0__GPIO2_IO00 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__NAND_DATA01 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__SD1_DATA5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D1__GPIO2_IO01 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__NAND_DATA02 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__SD1_DATA6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D2__GPIO2_IO02 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__NAND_DATA03 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__SD1_DATA7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D3__GPIO2_IO03 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__NAND_DATA04 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__SD2_DATA4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D4__GPIO2_IO04 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__NAND_DATA05 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__SD2_DATA5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D5__GPIO2_IO05 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__NAND_DATA06 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__SD2_DATA6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D6__GPIO2_IO06 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0), MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), + MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__SD4_DATA0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__NAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT0__GPIO2_IO08 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__SD4_DATA1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__PWM3_OUT = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT1__GPIO2_IO09 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__SD4_DATA2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__PWM4_OUT = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT2__GPIO2_IO10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__SD4_DATA3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT3__GPIO2_IO11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), + MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__GPIO2_IO12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), + MX6_PAD_SD4_DAT5__SD4_DATA5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__UART2_CTS_B = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__UART2_RTS_B = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT5__GPIO2_IO13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), + MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), + MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), + MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0), - MX6_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__PWM3_OUT = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__GPT_CAPTURE2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__GPIO1_IO17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__SD1_DATA0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0), MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__GPT_CAPTURE1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__GPIO1_IO16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__SD1_DATA3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPT_COMPARE3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__PWM1_OUT = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__WDOG2_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__GPIO1_IO21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), MX6_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0), - MX6_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__PWM4_OUT = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO1_IO18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), MX6_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__SD1_DATA2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0), - MX6_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__GPT_COMPARE2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__PWM2_OUT = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__WDOG1_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__GPIO1_IO19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__WDOG1_RESET_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), MX6_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0), MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO1_IO20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), MX6_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0), - MX6_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), - MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), + MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), + MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), MX6_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), MX6_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0), - MX6_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), - MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), + MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), + MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), MX6_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), - MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), + MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), + MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), MX6_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0), }; diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c index 9a317bc..c3775ef 100644 --- a/board/barco/titanium/titanium.c +++ b/board/barco/titanium/titanium.c @@ -45,18 +45,18 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -64,12 +64,12 @@ iomux_v3_cfg_t const uart4_pads[] = { struct i2c_pads_info i2c_pad_info0 = { .scl = { .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, .gp = IMX_GPIO_NR(5, 27) }, .sda = { .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, .gp = IMX_GPIO_NR(5, 26) } }; @@ -77,81 +77,81 @@ struct i2c_pads_info i2c_pad_info0 = { struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, .gp = IMX_GPIO_NR(1, 3) }, .sda = { .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, .gp = IMX_GPIO_NR(7, 11) } }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const enet_pads1[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; iomux_v3_cfg_t nfc_pads[] = { - MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_gpmi_nand(void) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 53cb8df..616ad55 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -71,13 +71,13 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -86,12 +86,12 @@ iomux_v3_cfg_t const uart2_pads[] = { struct i2c_pads_info i2c_pad_info0 = { .scl = { .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, .gp = IMX_GPIO_NR(3, 21) }, .sda = { .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, .gp = IMX_GPIO_NR(3, 28) } }; @@ -100,12 +100,12 @@ struct i2c_pads_info i2c_pad_info0 = { struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, .gp = IMX_GPIO_NR(4, 12) }, .sda = { .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; @@ -114,87 +114,87 @@ struct i2c_pads_info i2c_pad_info1 = { struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, .gp = IMX_GPIO_NR(1, 5) }, .sda = { .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, .gp = IMX_GPIO_NR(7, 11) } }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const enet_pads1[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; static iomux_v3_cfg_t const misc_pads[] = { MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP), /* OTG Power enable */ - MX6_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(OUTPUT_40OHM), + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM), }; /* wl1271 pads on nitrogen6x */ iomux_v3_cfg_t const wl12xx_pads[] = { - (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK) + (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(WEAK_PULLDOWN), - (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK) + (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(OUTPUT_40OHM), - (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK) + (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(OUTPUT_40OHM), }; #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) @@ -204,17 +204,17 @@ iomux_v3_cfg_t const wl12xx_pads[] = { /* Button assignments for J14 */ static iomux_v3_cfg_t const button_pads[] = { /* Menu */ - MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Back */ - MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Labelled Search (mapped to Power under Android) */ - MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Home */ - MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Down */ - MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), /* Volume Up */ - MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -238,7 +238,7 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usb_pads[] = { - MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) @@ -330,7 +330,7 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ - MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -431,44 +431,44 @@ int setup_sata(void) static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight on RGB connector: J15 */ - MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) /* Backlight on LVDS connector: J6 */ - MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) }; static iomux_v3_cfg_t const rgb_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, - MX6_PAD_DI0_PIN4__GPIO_4_20, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, + MX6_PAD_DI0_PIN4__GPIO4_IO20, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, }; struct display_info_t { diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 1ea68f4..7492534 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -35,32 +35,32 @@ int dram_init(void) } iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; static void setup_iomux_uart(void) diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 05c938f..1b4791c 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -38,52 +38,52 @@ int dram_init(void) } iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index c55ee87..1cf649c 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -51,25 +51,25 @@ int dram_init(void) } iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; @@ -77,12 +77,12 @@ iomux_v3_cfg_t const enet_pads[] = { struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, .gp = IMX_GPIO_NR(2, 30) }, .sda = { .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; @@ -94,22 +94,22 @@ struct i2c_pads_info i2c_pad_info1 = { struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, .gp = IMX_GPIO_NR(1, 3) }, .sda = { .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, .gp = IMX_GPIO_NR(3, 18) } }; iomux_v3_cfg_t const i2c3_pads[] = { - MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), }; iomux_v3_cfg_t const port_exp[] = { - MX6_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -118,18 +118,18 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 9dbe605..1ecedac 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -45,28 +45,28 @@ int dram_init(void) } iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8031 PHY Reset */ - MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -80,44 +80,44 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; static void setup_iomux_uart(void) diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index e9d6375..ab7b655 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -40,22 +40,22 @@ int dram_init(void) } static iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; static iomux_v3_cfg_t const wdog_pads[] = { - MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D19__GPIO_3_19, + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO3_IO19, }; static void setup_iomux_uart(void) diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index bf9898c..0043bc6 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -51,50 +51,50 @@ int dram_init(void) } static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* Carrier MicroSD Card Detect */ - MX6_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* SOM MicroSD Card Detect */ - MX6_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8031 PHY Reset */ - MX6_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_uart(void) -- cgit v0.10.2 From 066b2d68a03a2d591ac0ffe48d56ca1df30a992a Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 4 Nov 2013 17:00:52 -0700 Subject: i.MX6DQ/DLS: remove useless mux/pad declarations Signed-off-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 94f49c0..63ea4da 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -424,70 +424,6 @@ enum { MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x0474, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0478, NO_MUX_I, 0, 0x0000, 0, 0), @@ -1238,16 +1174,6 @@ enum { MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 = IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8 = IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0), - MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 = IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, 0), @@ -1362,10 +1288,6 @@ enum { MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__USDHC4_CLKO = IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__I2C4_SCL = IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0), - MX6_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index a85a5fd..437ea31 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -780,45 +780,13 @@ enum { MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0), MX6_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0), - MX6_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0), @@ -851,46 +819,14 @@ enum { MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), @@ -1251,24 +1187,6 @@ enum { MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), -- cgit v0.10.2 From 6001c11abc106ed6e3ddb178f223e186bd51fc65 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 4 Nov 2013 17:00:53 -0700 Subject: i.MX6DQ: Add Pinmux settings that are present in mainline and Dual-Lite/Solo Signed-off-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index 437ea31..ec1bbdd 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -132,6 +132,7 @@ enum { MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), MX6_PAD_EIM_D19__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), + MX6_PAD_EIM_D19__UART1_CTS_B = IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0), MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), @@ -162,6 +163,7 @@ enum { MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D23__UART3_CTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), MX6_PAD_EIM_D23__UART3_RTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), MX6_PAD_EIM_D23__UART1_DCD_B = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0), @@ -188,6 +190,7 @@ enum { MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D25__UART3_TX_DATA = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0), MX6_PAD_EIM_D25__UART3_RX_DATA = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0), MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), @@ -207,6 +210,7 @@ enum { MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU2_CSI1_DATA13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), + MX6_PAD_EIM_D27__UART2_TX_DATA = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0), MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU1_SISG3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), @@ -216,6 +220,7 @@ enum { MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU2_CSI1_DATA12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), + MX6_PAD_EIM_D28__UART2_DTE_RTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0), MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), @@ -231,6 +236,7 @@ enum { MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D30__UART3_CTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0), MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), @@ -726,6 +732,7 @@ enum { MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x04EC, 0x01D8, 0, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), @@ -840,6 +847,7 @@ enum { MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__UART4_TX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), @@ -857,6 +865,7 @@ enum { MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__UART5_TX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), @@ -906,6 +915,7 @@ enum { MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), @@ -986,6 +996,7 @@ enum { MX6_PAD_GPIO_8__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), MX6_PAD_GPIO_8__EPIT2_OUT = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), MX6_PAD_GPIO_8__FLEXCAN1_RX = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), + MX6_PAD_GPIO_8__UART2_TX_DATA = IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0), MX6_PAD_GPIO_8__UART2_RX_DATA = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), MX6_PAD_GPIO_8__GPIO1_IO08 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), MX6_PAD_GPIO_8__SPDIF_SR_CLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), @@ -1108,6 +1119,7 @@ enum { MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), + MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), @@ -1125,6 +1137,7 @@ enum { MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), @@ -1142,6 +1155,7 @@ enum { MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), @@ -1159,6 +1173,7 @@ enum { MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), @@ -1176,6 +1191,7 @@ enum { MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), @@ -1197,6 +1213,7 @@ enum { MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT6__UART1_TX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), MX6_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0), @@ -1214,6 +1231,7 @@ enum { MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT4__UART2_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), MX6_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0), @@ -1222,6 +1240,7 @@ enum { MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0), MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__UART2_CTS_B = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0000, 0, 0), MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0), @@ -1239,6 +1258,7 @@ enum { MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), MX6_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__UART1_CTS_B = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0), @@ -1263,6 +1283,7 @@ enum { MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__UART3_CTS_B = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), MX6_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0), @@ -1346,6 +1367,7 @@ enum { MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0), MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), + MX6_PAD_SD4_CLK__UART3_TX_DATA = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0), MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), MX6_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), @@ -1446,6 +1468,7 @@ enum { MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT4__UART2_TX_DATA = IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), @@ -1463,6 +1486,7 @@ enum { MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), + MX6_PAD_SD4_DAT6__UART2_CTS_B = IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), -- cgit v0.10.2 From 38d8219801c9614f0a1b4c81f55725f3909cfffe Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 4 Nov 2013 17:00:54 -0700 Subject: i.MX6DQ/DLS: remove unused pad declarations Signed-off-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 63ea4da..47d704b 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -15,98 +15,68 @@ enum { MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0), MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0), - MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0360, 0x004C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0), MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), - MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0364, 0x0050, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 = IOMUX_PAD(0x0368, 0x0054, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0), - MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0368, 0x0054, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 = IOMUX_PAD(0x036C, 0x0058, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0), - MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x036C, 0x0058, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 = IOMUX_PAD(0x0370, 0x005C, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0), - MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0370, 0x005C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 = IOMUX_PAD(0x0374, 0x0060, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0), - MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0374, 0x0060, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 = IOMUX_PAD(0x0378, 0x0064, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0), - MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0378, 0x0064, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 = IOMUX_PAD(0x037C, 0x0068, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0), - MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x037C, 0x0068, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 = IOMUX_PAD(0x0380, 0x006C, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0), - MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0380, 0x006C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 = IOMUX_PAD(0x0384, 0x0070, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0), - MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0384, 0x0070, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 = IOMUX_PAD(0x0384, 0x0070, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0), MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0), MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0), @@ -114,7 +84,6 @@ enum { MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0), MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0), @@ -122,7 +91,6 @@ enum { MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0), MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0), @@ -130,7 +98,6 @@ enum { MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0), MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0), @@ -138,7 +105,6 @@ enum { MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0), MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0), MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), @@ -146,160 +112,95 @@ enum { MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0), MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0), MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x039C, 0x0088, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 = IOMUX_PAD(0x03A0, 0x008C, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 = IOMUX_PAD(0x03A0, 0x008C, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x03A4, 0x0090, 6, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 = IOMUX_PAD(0x03A8, 0x0094, 6, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 = IOMUX_PAD(0x03AC, 0x0098, 6, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_DISP_CLK__LCD_CLK = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__LCD_WR_RWN = IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN15__LCD_ENABLE = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0 = IOMUX_PAD(0x03B4, 0x00A0, 7, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__LCD_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN2__LCD_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0), MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 = IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__LCD_RS = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN3__LCD_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__LCD_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN4__LCD_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), - MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__LCD_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT0__LCD_DATA00 = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT1__LCD_DATA01 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__LCD_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21 = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT11__LCD_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT12__LCD_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT13__LCD_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0), - MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT14__LCD_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0), - MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT15__LCD_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0), - MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT16__LCD_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0), MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0), MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0), MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT17__LCD_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0), MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0), MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0), MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT18__LCD_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0), MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0), MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0), MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT19__LCD_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), @@ -307,204 +208,103 @@ enum { MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0), MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0), MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__LCD_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT20__LCD_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0), MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0), - MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT21__LCD_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0), MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0), - MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT22__LCD_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0), MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0), - MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT23__LCD_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0), MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0), - MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT3__LCD_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 = IOMUX_PAD(0x0408, 0x00F4, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__GPIO4_IO24 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT4__LCD_DATA04 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 = IOMUX_PAD(0x040C, 0x00F8, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__GPIO4_IO25 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15 = IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT5__LCD_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16 = IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT6__LCD_DATA06 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17 = IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT7__LCD_DATA07 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 = IOMUX_PAD(0x0418, 0x0104, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__GPIO4_IO28 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT8__LCD_DATA08 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x041C, 0x0108, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT9__LCD_DATA09 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x0420, 0x010C, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), - MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x0424, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0428, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x042C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0430, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x0434, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0438, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x043C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0440, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0444, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0448, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x044C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0450, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0454, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0458, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x0474, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0478, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x047C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0480, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0484, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x0488, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x048C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0490, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x0494, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0498, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x049C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x04A0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x04A4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x04A8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x04AC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x04B0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x04B4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x04B8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x04BC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x04C0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x04C4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x04C8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x04CC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x04D0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x04D4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x04D8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x04DC, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0), - MX6_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 = IOMUX_PAD(0x04E0, 0x0110, 4, 0x0000, 0, 0), MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x04E0, 0x0110, 6, 0x0000, 0, 0), MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0), MX6_PAD_EIM_A16__EPDC_DATA00 = IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0), MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0), MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0), MX6_PAD_EIM_A17__IPU1_CSI1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0), - MX6_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 = IOMUX_PAD(0x04E4, 0x0114, 4, 0x0000, 0, 0), MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x04E4, 0x0114, 6, 0x0000, 0, 0), MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0), MX6_PAD_EIM_A17__EPDC_PWR_STAT = IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0), MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0), MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0), MX6_PAD_EIM_A18__IPU1_CSI1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0), - MX6_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 = IOMUX_PAD(0x04E8, 0x0118, 4, 0x0000, 0, 0), MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x04E8, 0x0118, 6, 0x0000, 0, 0), MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0), MX6_PAD_EIM_A18__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0), MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0), MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0), MX6_PAD_EIM_A19__IPU1_CSI1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0), - MX6_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 = IOMUX_PAD(0x04EC, 0x011C, 4, 0x0000, 0, 0), MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x04EC, 0x011C, 6, 0x0000, 0, 0), MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0), MX6_PAD_EIM_A19__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0), MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0), MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0), MX6_PAD_EIM_A20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0), - MX6_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 = IOMUX_PAD(0x04F0, 0x0120, 4, 0x0000, 0, 0), MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x04F0, 0x0120, 6, 0x0000, 0, 0), MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0), MX6_PAD_EIM_A20__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0), MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0), MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0), MX6_PAD_EIM_A21__IPU1_CSI1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0), - MX6_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 = IOMUX_PAD(0x04F4, 0x0124, 4, 0x0000, 0, 0), MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x04F4, 0x0124, 6, 0x0000, 0, 0), MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0), MX6_PAD_EIM_A21__EPDC_GDCLK = IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0), MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0), MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0), MX6_PAD_EIM_A22__IPU1_CSI1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0), MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x04F8, 0x0128, 6, 0x0000, 0, 0), MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0), MX6_PAD_EIM_A22__EPDC_GDSP = IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0), MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0), @@ -512,7 +312,6 @@ enum { MX6_PAD_EIM_A23__IPU1_CSI1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0), MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0), MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3 = IOMUX_PAD(0x04FC, 0x012C, 6, 0x0000, 0, 0), MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0), MX6_PAD_EIM_A23__EPDC_GDOE = IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0), MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0), @@ -520,7 +319,6 @@ enum { MX6_PAD_EIM_A24__IPU1_CSI1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0), MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0), MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2 = IOMUX_PAD(0x0500, 0x0130, 6, 0x0000, 0, 0), MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0), MX6_PAD_EIM_A24__EPDC_GDRL = IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0), MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0), @@ -530,27 +328,21 @@ enum { MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0), MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0), MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0), - MX6_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0 = IOMUX_PAD(0x0504, 0x0134, 7, 0x0000, 0, 0), MX6_PAD_EIM_A25__EPDC_DATA15 = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0), MX6_PAD_EIM_A25__EIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x0508, 0x0138, 6, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__EPDC_SDCE9 = IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0), MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0), MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0), - MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 = IOMUX_PAD(0x050C, 0x013C, 4, 0x0000, 0, 0), MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x050C, 0x013C, 6, 0x0000, 0, 0), MX6_PAD_EIM_CS0__EPDC_DATA06 = IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0), MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0), MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0), - MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 = IOMUX_PAD(0x0510, 0x0140, 4, 0x0000, 0, 0), MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0510, 0x0140, 6, 0x0000, 0, 0), MX6_PAD_EIM_CS1__EPDC_DATA08 = IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0), MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0), MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0), @@ -559,7 +351,6 @@ enum { MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0), MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0), MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0), - MX6_PAD_EIM_D16__TPSMP_HTRANS_0 = IOMUX_PAD(0x0514, 0x0144, 7, 0x0000, 0, 0), MX6_PAD_EIM_D16__EPDC_DATA10 = IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0), MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0), MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0), @@ -568,7 +359,6 @@ enum { MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0), MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0), MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0), - MX6_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1 = IOMUX_PAD(0x0518, 0x0148, 7, 0x0000, 0, 0), MX6_PAD_EIM_D17__EPDC_VCOM0 = IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0), MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0), @@ -577,7 +367,6 @@ enum { MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0), MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0), MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0), - MX6_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2 = IOMUX_PAD(0x051C, 0x014C, 7, 0x0000, 0, 0), MX6_PAD_EIM_D18__EPDC_VCOM1 = IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0), MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0), MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0), @@ -587,7 +376,6 @@ enum { MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0), MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP = IOMUX_PAD(0x0520, 0x0150, 7, 0x0000, 0, 0), MX6_PAD_EIM_D19__EPDC_DATA12 = IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0), MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0), MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0), @@ -597,7 +385,6 @@ enum { MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0), MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0), MX6_PAD_EIM_D20__EPIT2_OUT = IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D20__TPSMP_HTRANS_1 = IOMUX_PAD(0x0524, 0x0154, 7, 0x0000, 0, 0), MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0), MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0), @@ -613,7 +400,6 @@ enum { MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0), MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0), MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE = IOMUX_PAD(0x052C, 0x015C, 7, 0x0000, 0, 0), MX6_PAD_EIM_D22__EPDC_SDCE6 = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0), MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0), @@ -692,7 +478,6 @@ enum { MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0), MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0), MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0), - MX6_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0 = IOMUX_PAD(0x054C, 0x017C, 7, 0x0000, 0, 0), MX6_PAD_EIM_D30__EPDC_SDOEZ = IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0), MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0), MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0), @@ -702,167 +487,117 @@ enum { MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0), MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0), MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1 = IOMUX_PAD(0x0550, 0x0180, 7, 0x0000, 0, 0), MX6_PAD_EIM_D31__EPDC_SDCLK_P = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0), MX6_PAD_EIM_D31__EIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0), MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA0__IPU1_CSI1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 = IOMUX_PAD(0x0554, 0x0184, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0554, 0x0184, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA0__EPDC_SDCLK_N = IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA1__IPU1_CSI1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 = IOMUX_PAD(0x0558, 0x0188, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE = IOMUX_PAD(0x0558, 0x0188, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x0558, 0x0188, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA1__EPDC_SDLE = IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0), - MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 = IOMUX_PAD(0x055C, 0x018C, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x055C, 0x018C, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA10__EPDC_DATA01 = IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC = IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0), - MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 = IOMUX_PAD(0x0560, 0x0190, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 = IOMUX_PAD(0x0560, 0x0190, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0560, 0x0190, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA11__EPDC_DATA03 = IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0), - MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 = IOMUX_PAD(0x0564, 0x0194, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 = IOMUX_PAD(0x0564, 0x0194, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0564, 0x0194, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA12__EPDC_DATA02 = IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x0568, 0x0198, 2, 0x07D0, 0, 0), - MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 = IOMUX_PAD(0x0568, 0x0198, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 = IOMUX_PAD(0x0568, 0x0198, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x0568, 0x0198, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA13__EPDC_DATA13 = IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x056C, 0x019C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 = IOMUX_PAD(0x056C, 0x019C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 = IOMUX_PAD(0x056C, 0x019C, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x056C, 0x019C, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA14__EPDC_DATA14 = IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 = IOMUX_PAD(0x0570, 0x01A0, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0570, 0x01A0, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA15__EPDC_DATA09 = IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA2__IPU1_CSI1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 = IOMUX_PAD(0x0574, 0x01A4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE = IOMUX_PAD(0x0574, 0x01A4, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0574, 0x01A4, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA2__EPDC_BDR0 = IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA3__IPU1_CSI1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 = IOMUX_PAD(0x0578, 0x01A8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ = IOMUX_PAD(0x0578, 0x01A8, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0578, 0x01A8, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA3__EPDC_BDR1 = IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA4__IPU1_CSI1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 = IOMUX_PAD(0x057C, 0x01AC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN = IOMUX_PAD(0x057C, 0x01AC, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x057C, 0x01AC, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA4__EPDC_SDCE0 = IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA5__IPU1_CSI1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 = IOMUX_PAD(0x0580, 0x01B0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP = IOMUX_PAD(0x0580, 0x01B0, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x0580, 0x01B0, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA5__EPDC_SDCE1 = IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA6__IPU1_CSI1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 = IOMUX_PAD(0x0584, 0x01B4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN = IOMUX_PAD(0x0584, 0x01B4, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0584, 0x01B4, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA6__EPDC_SDCE2 = IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA7__IPU1_CSI1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 = IOMUX_PAD(0x0588, 0x01B8, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0588, 0x01B8, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA7__EPDC_SDCE3 = IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA8__IPU1_CSI1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 = IOMUX_PAD(0x058C, 0x01BC, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x058C, 0x01BC, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA8__EPDC_SDCE4 = IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0), MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA9__IPU1_CSI1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 = IOMUX_PAD(0x0590, 0x01C0, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x0590, 0x01C0, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA9__EPDC_SDCE5 = IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0), MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0), MX6_PAD_EIM_EB0__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0), - MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 = IOMUX_PAD(0x0594, 0x01C4, 3, 0x0000, 0, 0), MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0), MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0594, 0x01C4, 6, 0x0000, 0, 0), MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0), MX6_PAD_EIM_EB0__EPDC_PWR_COM = IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0), MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0), MX6_PAD_EIM_EB1__IPU1_CSI1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0), - MX6_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 = IOMUX_PAD(0x0598, 0x01C8, 3, 0x0000, 0, 0), MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0598, 0x01C8, 6, 0x0000, 0, 0), MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0), MX6_PAD_EIM_EB1__EPDC_SDSHR = IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0), MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, 0), - MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x059C, 0x01CC, 2, 0x07D0, 1, 0), MX6_PAD_EIM_EB2__IPU1_CSI1_DATA19 = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0), MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0), MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0), @@ -884,90 +619,68 @@ enum { MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0), MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0), MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x05A4, 0x01D4, 6, 0x0000, 0, 0), MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0), MX6_PAD_EIM_LBA__EPDC_DATA04 = IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0), MX6_PAD_EIM_OE__EIM_OE_B = IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0), MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0), MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0), - MX6_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 = IOMUX_PAD(0x05A8, 0x01D8, 4, 0x0000, 0, 0), MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x05A8, 0x01D8, 6, 0x0000, 0, 0), MX6_PAD_EIM_OE__EPDC_PWR_IRQ = IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0), MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0), MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0), MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0), - MX6_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 = IOMUX_PAD(0x05AC, 0x01DC, 4, 0x0000, 0, 0), MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x05AC, 0x01DC, 6, 0x0000, 0, 0), MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0), MX6_PAD_EIM_RW__EPDC_DATA07 = IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x05B0, 0x01E0, 6, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0), MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0), MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0), MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x05B4, 0x01E4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD = IOMUX_PAD(0x05B4, 0x01E4, 7, 0x0000, 0, 0), MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0), MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0), MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0), MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0), MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET = IOMUX_PAD(0x05B8, 0x01E8, 7, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0), MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0), - MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x05BC, 0x01EC, 3, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0), - MX6_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x05C0, 0x01F0, 3, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH = IOMUX_PAD(0x05C0, 0x01F0, 7, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0), MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0), MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0), MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT = IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x05C4, 0x01F4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD = IOMUX_PAD(0x05C4, 0x01F4, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0), MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0), MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0), MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0), MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0), MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0), MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__I2C4_SCL = IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0), MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0), MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0), MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0), MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__I2C4_SDA = IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0), MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0), MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0), @@ -983,7 +696,6 @@ enum { MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0), MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0), MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0), @@ -998,7 +710,6 @@ enum { MX6_PAD_GPIO_17__SDMA_EXT_EVENT0 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0), MX6_PAD_GPIO_17__SPDIF_OUT = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0), MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0), MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), @@ -1006,7 +717,6 @@ enum { MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0), MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0), MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0), MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0), @@ -1014,17 +724,12 @@ enum { MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), MX6_PAD_GPIO_19__GPIO4_IO05 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0), - MX6_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0), - MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0), MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0), - MX6_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0), MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), @@ -1032,26 +737,17 @@ enum { MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0), MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0), MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0), - MX6_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0), - MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), MX6_PAD_GPIO_4__SD2_CD_B = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0000, 0, 0), MX6_PAD_GPIO_5__ESAI_TX2_RX3 = IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0), - MX6_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), MX6_PAD_GPIO_5__KEY_ROW7 = IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0), MX6_PAD_GPIO_5__CCM_CLKO1 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), MX6_PAD_GPIO_5__GPIO1_IO05 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0), MX6_PAD_GPIO_5__ARM_EVENTI = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0), MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0), - MX6_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0), - MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0), @@ -1081,13 +777,6 @@ enum { MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0), - MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x0614, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0618, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x061C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x0620, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0624, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0628, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0), MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0), MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0), @@ -1096,7 +785,6 @@ enum { MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0), MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x062C, 0x0244, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0), MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, 0), MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0), @@ -1105,7 +793,6 @@ enum { MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0), MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1 = IOMUX_PAD(0x0630, 0x0248, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0), MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0), MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0), @@ -1113,7 +800,6 @@ enum { MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, 0), MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3 = IOMUX_PAD(0x0634, 0x024C, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0), MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0), MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, 0), @@ -1121,7 +807,6 @@ enum { MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0), MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0), - MX6_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5 = IOMUX_PAD(0x0638, 0x0250, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0), MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0), @@ -1129,8 +814,6 @@ enum { MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0), MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0), MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 = IOMUX_PAD(0x063C, 0x0254, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7 = IOMUX_PAD(0x063C, 0x0254, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0), MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0), @@ -1139,7 +822,6 @@ enum { MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0), MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0 = IOMUX_PAD(0x0640, 0x0258, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0), MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0), @@ -1148,7 +830,6 @@ enum { MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0), MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2 = IOMUX_PAD(0x0644, 0x025C, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0), MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0), @@ -1156,15 +837,12 @@ enum { MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0), - MX6_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4 = IOMUX_PAD(0x0648, 0x0260, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x064C, 0x0264, 0, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0), MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0), MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6 = IOMUX_PAD(0x064C, 0x0264, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0), MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0), @@ -1172,421 +850,234 @@ enum { MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0), MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 = IOMUX_PAD(0x0650, 0x0268, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8 = IOMUX_PAD(0x0650, 0x0268, 7, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 = IOMUX_PAD(0x0654, 0x026C, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 = IOMUX_PAD(0x0654, 0x026C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 = IOMUX_PAD(0x0654, 0x026C, 4, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 = IOMUX_PAD(0x0654, 0x026C, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USDHC3_CLKI = IOMUX_PAD(0x0654, 0x026C, 8, 0x0934, 0, 0), MX6_PAD_NANDF_CLE__NAND_CLE = IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 = IOMUX_PAD(0x0658, 0x0270, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 = IOMUX_PAD(0x0658, 0x0270, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 = IOMUX_PAD(0x0658, 0x0270, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__GPIO6_IO07 = IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 = IOMUX_PAD(0x0658, 0x0270, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__USDHC3_CLKO = IOMUX_PAD(0x0658, 0x0270, 8, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 = IOMUX_PAD(0x065C, 0x0274, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 = IOMUX_PAD(0x065C, 0x0274, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__USDHC1_CLKO = IOMUX_PAD(0x065C, 0x0274, 8, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 = IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT = IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__USDHC1_CLKI = IOMUX_PAD(0x0660, 0x0278, 8, 0x0928, 0, 0), MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0), MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__USDHC2_CLKO = IOMUX_PAD(0x0664, 0x027C, 8, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0), MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 = IOMUX_PAD(0x0668, 0x0280, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x0668, 0x0280, 7, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__USDHC2_CLKI = IOMUX_PAD(0x0668, 0x0280, 8, 0x0930, 0, 0), MX6_PAD_NANDF_CS3__I2C4_SDA = IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0), MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D0__SD1_DATA4 = IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x066C, 0x0284, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 = IOMUX_PAD(0x066C, 0x0284, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 = IOMUX_PAD(0x066C, 0x0284, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D0__GPIO2_IO00 = IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x066C, 0x0284, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D1__NAND_DATA01 = IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D1__SD1_DATA5 = IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x0670, 0x0288, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 = IOMUX_PAD(0x0670, 0x0288, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 = IOMUX_PAD(0x0670, 0x0288, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D1__GPIO2_IO01 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x0670, 0x0288, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D2__NAND_DATA02 = IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D2__SD1_DATA6 = IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x0674, 0x028C, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 = IOMUX_PAD(0x0674, 0x028C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 = IOMUX_PAD(0x0674, 0x028C, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D2__GPIO2_IO02 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x0674, 0x028C, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D3__NAND_DATA03 = IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D3__SD1_DATA7 = IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x0678, 0x0290, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 = IOMUX_PAD(0x0678, 0x0290, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 = IOMUX_PAD(0x0678, 0x0290, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D3__GPIO2_IO03 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x0678, 0x0290, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D4__NAND_DATA04 = IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D4__SD2_DATA4 = IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x067C, 0x0294, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 = IOMUX_PAD(0x067C, 0x0294, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 = IOMUX_PAD(0x067C, 0x0294, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D4__GPIO2_IO04 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x067C, 0x0294, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D5__NAND_DATA05 = IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D5__SD2_DATA5 = IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x0680, 0x0298, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 = IOMUX_PAD(0x0680, 0x0298, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 = IOMUX_PAD(0x0680, 0x0298, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D5__GPIO2_IO05 = IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x0680, 0x0298, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D6__NAND_DATA06 = IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D6__SD2_DATA6 = IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x0684, 0x029C, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 = IOMUX_PAD(0x0684, 0x029C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 = IOMUX_PAD(0x0684, 0x029C, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D6__GPIO2_IO06 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x0684, 0x029C, 6, 0x0000, 0, 0), MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x0688, 0x02A0, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 = IOMUX_PAD(0x0688, 0x02A0, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 = IOMUX_PAD(0x0688, 0x02A0, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0688, 0x02A0, 6, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 = IOMUX_PAD(0x068C, 0x02A4, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 = IOMUX_PAD(0x068C, 0x02A4, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 = IOMUX_PAD(0x068C, 0x02A4, 4, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 = IOMUX_PAD(0x068C, 0x02A4, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__USDHC4_CLKI = IOMUX_PAD(0x068C, 0x02A4, 8, 0x0938, 0, 0), MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__USDHC4_CLKO = IOMUX_PAD(0x0690, 0x02A8, 8, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__I2C4_SCL = IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0), MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0), MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0), MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0), MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0), - MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), MX6_PAD_SD1_CLK__GPIO1_IO20 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_SD1_CMD__PWM4_OUT = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), MX6_PAD_SD1_CMD__GPIO1_IO18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__SD1_DATA0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS = IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__GPT_CAPTURE1 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__GPIO1_IO16 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x06CC, 0x02E4, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__PWM3_OUT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__GPT_CAPTURE2 = IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__GPIO1_IO17 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x06D0, 0x02E8, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__SD1_DATA2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__GPT_COMPARE2 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__PWM2_OUT = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__WDOG1_B = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__GPIO1_IO19 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__WDOG1_RESET_B_DEB = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 = IOMUX_PAD(0x06D4, 0x02EC, 7, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__SD1_DATA3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__GPT_COMPARE3 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__PWM1_OUT = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__WDOG2_B = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__GPIO1_IO21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0), MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0), MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0), - MX6_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x06DC, 0x02F4, 6, 0x0000, 0, 0), MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0), MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0), - MX6_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0), MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0), MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0), MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0), MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0), MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0), MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0), MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0), - MX6_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), MX6_PAD_SD3_CLK__UART2_RTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0), MX6_PAD_SD3_CLK__FLEXCAN1_RX = IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0), - MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), MX6_PAD_SD3_CLK__GPIO7_IO03 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_SD3_CMD__UART2_CTS_B = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0), MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), MX6_PAD_SD3_CMD__GPIO7_IO02 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__UART1_CTS_B = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0), MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__GPIO7_IO04 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__SD3_DATA1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__UART1_CTS_B = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__UART1_RTS_B = IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0), MX6_PAD_SD3_DAT1__FLEXCAN2_RX = IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0), - MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__GPIO7_IO05 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__SD3_DATA2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__GPIO7_IO06 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__UART3_CTS_B = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0), - MX6_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__GPIO7_IO07 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__UART2_TX_DATA = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0), - MX6_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__GPIO7_IO01 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0), - MX6_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 = IOMUX_PAD(0x0710, 0x0328, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__UART1_TX_DATA = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), - MX6_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 = IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0), - MX6_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), MX6_PAD_SD3_RST__SD3_RESET = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), MX6_PAD_SD3_RST__UART3_CTS_B = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), MX6_PAD_SD3_RST__UART3_RTS_B = IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0), - MX6_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 = IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), MX6_PAD_SD3_RST__GPIO7_IO08 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), - MX6_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), - MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), MX6_PAD_SD4_CLK__UART3_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0), - MX6_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_SD4_CMD__NAND_RE_B = IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0), MX6_PAD_SD4_CMD__UART3_TX_DATA = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), MX6_PAD_SD4_CMD__UART3_RX_DATA = IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0), - MX6_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), MX6_PAD_SD4_CMD__GPIO7_IO09 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__SD4_DATA0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__NAND_DQS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__GPIO2_IO08 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__SD4_DATA1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__PWM3_OUT = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__GPIO2_IO09 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x0730, 0x0348, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__SD4_DATA2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__PWM4_OUT = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 = IOMUX_PAD(0x0730, 0x0348, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__GPIO2_IO10 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x0730, 0x0348, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__SD4_DATA3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__GPIO2_IO11 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__UART2_TX_DATA = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0), - MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 = IOMUX_PAD(0x0738, 0x0350, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__GPIO2_IO12 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__SD4_DATA5 = IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__UART2_CTS_B = IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__UART2_RTS_B = IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0), - MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 = IOMUX_PAD(0x073C, 0x0354, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__GPIO2_IO13 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x0740, 0x0358, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__UART2_CTS_B = IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0), - MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 = IOMUX_PAD(0x0740, 0x0358, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x0740, 0x0358, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0), - MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 = IOMUX_PAD(0x0744, 0x035C, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index ec1bbdd..5e38556 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -18,77 +18,57 @@ enum { MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0), MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0), MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0), MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0), MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0), @@ -96,10 +76,8 @@ enum { MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0), - MX6_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0), - MX6_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0), MX6_PAD_EIM_EB2__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0), MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), @@ -119,7 +97,6 @@ enum { MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0), - MX6_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0), MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), @@ -127,7 +104,6 @@ enum { MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0), - MX6_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), @@ -136,7 +112,6 @@ enum { MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0), MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0), MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), @@ -160,7 +135,6 @@ enum { MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), MX6_PAD_EIM_D23__UART3_CTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), @@ -240,7 +214,6 @@ enum { MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), - MX6_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0), MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), @@ -249,14 +222,12 @@ enum { MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0), MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), MX6_PAD_EIM_A24__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), MX6_PAD_EIM_A24__IPU2_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0), MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), @@ -264,419 +235,264 @@ enum { MX6_PAD_EIM_A23__IPU2_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0), MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), MX6_PAD_EIM_A22__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0), MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), MX6_PAD_EIM_A21__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), - MX6_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0), MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0), MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), MX6_PAD_EIM_A20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), - MX6_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0), MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0), MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), MX6_PAD_EIM_A19__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), - MX6_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0), MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0), MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), MX6_PAD_EIM_A18__IPU2_CSI1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), - MX6_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0), MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0), MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), MX6_PAD_EIM_A17__IPU2_CSI1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), - MX6_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0), MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0), MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0), - MX6_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0), MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0), MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0), - MX6_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0), MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0), MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0), - MX6_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0), MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0), MX6_PAD_EIM_OE__EIM_OE_B = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0), - MX6_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0), MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0), MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0), - MX6_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0), MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0), MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), MX6_PAD_EIM_LBA__EIM_LBA_B = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0), MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0), MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), MX6_PAD_EIM_EB0__IPU2_CSI1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), - MX6_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0), MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), MX6_PAD_EIM_EB1__IPU2_CSI1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), - MX6_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0), MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0), MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA0__IPU2_CSI1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA1__IPU2_CSI1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA2__IPU2_CSI1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA3__IPU2_CSI1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA4__IPU2_CSI1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA5__IPU2_CSI1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA6__IPU2_CSI1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA7__IPU2_CSI1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA8__IPU2_CSI1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA9__IPU2_CSI1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), - MX6_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0), - MX6_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0), - MX6_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0), - MX6_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0), MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0), MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0), MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__IPU2_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), - MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__GPIO4_IO24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT4__GPIO4_IO25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__GPIO4_IO28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), - MX6_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), - MX6_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), - MX6_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0), MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0), MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), @@ -684,156 +500,71 @@ enum { MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0), MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), - MX6_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0), MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), - MX6_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0), MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), - MX6_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), - MX6_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0), MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), - MX6_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), - MX6_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x04EC, 0x01D8, 0, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0), MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0), MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0), MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), @@ -842,7 +573,6 @@ enum { MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0), MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), @@ -851,7 +581,6 @@ enum { MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0), MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0), MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), @@ -860,7 +589,6 @@ enum { MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0), MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), @@ -869,7 +597,6 @@ enum { MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0), MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), @@ -877,7 +604,6 @@ enum { MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0), MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), @@ -885,7 +611,6 @@ enum { MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0), - MX6_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0), MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0), @@ -893,15 +618,12 @@ enum { MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0), MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), - MX6_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0), MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0), MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), @@ -909,8 +631,6 @@ enum { MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), @@ -918,8 +638,6 @@ enum { MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0), MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), @@ -934,7 +652,6 @@ enum { MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0), MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), @@ -942,9 +659,7 @@ enum { MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), - MX6_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0), MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), - MX6_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0), MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0), MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), @@ -952,34 +667,22 @@ enum { MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), - MX6_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0), MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0), - MX6_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0), MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), - MX6_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0), MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), - MX6_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0), MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), - MX6_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0), MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), - MX6_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), MX6_PAD_GPIO_4__SD2_CD_B = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), MX6_PAD_GPIO_5__ESAI_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), - MX6_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), MX6_PAD_GPIO_5__KEY_ROW7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), MX6_PAD_GPIO_5__CCM_CLKO1 = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), MX6_PAD_GPIO_5__GPIO1_IO05 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0), MX6_PAD_GPIO_5__ARM_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), @@ -1015,7 +718,6 @@ enum { MX6_PAD_GPIO_17__SDMA_EXT_EVENT0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), MX6_PAD_GPIO_17__SPDIF_OUT = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0), MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0), MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), @@ -1023,7 +725,6 @@ enum { MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0), MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0), MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), @@ -1031,33 +732,20 @@ enum { MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0), MX6_PAD_GPIO_19__GPIO4_IO05 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), @@ -1065,7 +753,6 @@ enum { MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), @@ -1073,7 +760,6 @@ enum { MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), @@ -1081,7 +767,6 @@ enum { MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), @@ -1089,7 +774,6 @@ enum { MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), @@ -1097,7 +781,6 @@ enum { MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0), MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), @@ -1105,244 +788,132 @@ enum { MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0), MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), - MX6_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), - MX6_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), - MX6_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), - MX6_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), - MX6_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), - MX6_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), - MX6_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), - MX6_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), - MX6_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), - MX6_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0), - MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0), - MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), - MX6_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__UART1_TX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), - MX6_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), - MX6_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__UART2_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), - MX6_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__GPIO7_IO01 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0), MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), MX6_PAD_SD3_CMD__UART2_CTS_B = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0000, 0, 0), MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0), MX6_PAD_SD3_CMD__GPIO7_IO02 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0), MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), MX6_PAD_SD3_CLK__UART2_RTS_B = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), MX6_PAD_SD3_CLK__FLEXCAN1_RX = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), - MX6_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0), MX6_PAD_SD3_CLK__GPIO7_IO03 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__UART1_CTS_B = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT0__GPIO7_IO04 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__SD3_DATA1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__UART1_CTS_B = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__UART1_RTS_B = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), MX6_PAD_SD3_DAT1__FLEXCAN2_RX = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), - MX6_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT1__GPIO7_IO05 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__SD3_DATA2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT2__GPIO7_IO06 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__UART3_CTS_B = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), - MX6_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0), MX6_PAD_SD3_DAT3__GPIO7_IO07 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0), MX6_PAD_SD3_RST__SD3_RESET = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), MX6_PAD_SD3_RST__UART3_CTS_B = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), MX6_PAD_SD3_RST__UART3_RTS_B = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), - MX6_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0), - MX6_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0), MX6_PAD_SD3_RST__GPIO7_IO08 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), - MX6_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0), - MX6_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__NAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__IPU2_SISG4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CLE__GPIO6_IO07 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__IPU2_SISG5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__IPU2_DI0_PIN01 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), @@ -1354,170 +925,78 @@ enum { MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__IPU2_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0), MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), MX6_PAD_SD4_CMD__NAND_RE_B = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), MX6_PAD_SD4_CMD__UART3_TX_DATA = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), MX6_PAD_SD4_CMD__UART3_RX_DATA = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), - MX6_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0), MX6_PAD_SD4_CMD__GPIO7_IO09 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0), MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), MX6_PAD_SD4_CLK__UART3_TX_DATA = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0), MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), - MX6_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0), MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D0__SD1_DATA4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D0__GPIO2_IO00 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0), MX6_PAD_NANDF_D1__NAND_DATA01 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D1__SD1_DATA5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D1__GPIO2_IO01 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0), MX6_PAD_NANDF_D2__NAND_DATA02 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D2__SD1_DATA6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D2__GPIO2_IO02 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0), MX6_PAD_NANDF_D3__NAND_DATA03 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D3__SD1_DATA7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D3__GPIO2_IO03 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0), MX6_PAD_NANDF_D4__NAND_DATA04 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D4__SD2_DATA4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D4__GPIO2_IO04 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0), MX6_PAD_NANDF_D5__NAND_DATA05 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D5__SD2_DATA5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D5__GPIO2_IO05 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0), MX6_PAD_NANDF_D6__NAND_DATA06 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D6__SD2_DATA6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D6__GPIO2_IO06 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0), MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0), MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__SD4_DATA0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__NAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT0__GPIO2_IO08 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__SD4_DATA1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__PWM3_OUT = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT1__GPIO2_IO09 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__SD4_DATA2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__PWM4_OUT = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT2__GPIO2_IO10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__SD4_DATA3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT3__GPIO2_IO11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__UART2_TX_DATA = IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), - MX6_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT4__GPIO2_IO12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__SD4_DATA5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__UART2_CTS_B = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__UART2_RTS_B = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), - MX6_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT5__GPIO2_IO13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__UART2_CTS_B = IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), - MX6_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), - MX6_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0), MX6_PAD_SD1_DAT1__PWM3_OUT = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__GPT_CAPTURE2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__GPIO1_IO17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__SD1_DATA0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0), - MX6_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__GPT_CAPTURE1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0), MX6_PAD_SD1_DAT0__GPIO1_IO16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__SD1_DATA3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__GPT_COMPARE3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), @@ -1525,13 +1004,11 @@ enum { MX6_PAD_SD1_DAT3__WDOG2_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__GPIO1_IO21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0), MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), MX6_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0), MX6_PAD_SD1_CMD__PWM4_OUT = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), MX6_PAD_SD1_CMD__GPIO1_IO18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__SD1_DATA2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0), MX6_PAD_SD1_DAT2__GPT_COMPARE2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), @@ -1539,36 +1016,25 @@ enum { MX6_PAD_SD1_DAT2__WDOG1_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__GPIO1_IO19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT2__WDOG1_RESET_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0), MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), MX6_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0), - MX6_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), MX6_PAD_SD1_CLK__GPIO1_IO20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0), MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0), MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), - MX6_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0), MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0), MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0), MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), - MX6_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0), MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), - MX6_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */ -- cgit v0.10.2 From a31d3efae108f9ec97f2be22e17d8eaf1e2f48e8 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 4 Nov 2013 17:00:55 -0700 Subject: i.MX6DQ/DLS: whitespace: Align IOMUX_PAD column in declarations Signed-off-by: Eric Nelson diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 47d704b..d194eb0 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -11,145 +11,145 @@ enum { MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0), MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), + MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0), + MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0), MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0), + MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0), MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0), + MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0), MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0), + MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0), MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0), MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0), MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0), MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0), MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0), MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0), - MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0), MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0), - MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0), MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0), - MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0), MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0), - MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0), MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0), MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0), MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0), MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0), MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0), MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_DISP_CLK__LCD_CLK = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__LCD_WR_RWN = IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN15__LCD_ENABLE = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__LCD_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN2__LCD_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0), - MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__LCD_RS = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN3__LCD_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__LCD_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN4__LCD_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), - MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__LCD_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0), @@ -162,76 +162,76 @@ enum { MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__LCD_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DISP0_DAT10__LCD_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__LCD_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT11__LCD_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__LCD_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT12__LCD_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__LCD_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0), + MX6_PAD_DISP0_DAT13__LCD_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0), MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__LCD_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0), + MX6_PAD_DISP0_DAT14__LCD_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0), MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__LCD_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT15__LCD_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0), MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0), MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__LCD_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT16__LCD_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0), + MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0), MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0), MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__LCD_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT17__LCD_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0), + MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0), MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0), MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__LCD_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__LCD_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0), - MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0), + MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0), + MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0), MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__LCD_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__LCD_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0), - MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0), + MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0), + MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0), MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__LCD_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__LCD_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT20__LCD_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0), - MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0), + MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0), MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__LCD_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT21__LCD_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0), - MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0), + MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0), MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__LCD_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT22__LCD_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0), - MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0), + MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0), MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__LCD_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT23__LCD_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0), - MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0), + MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0), MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT3__LCD_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), @@ -244,12 +244,12 @@ enum { MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT5__LCD_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT6__LCD_DATA06 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT7__LCD_DATA07 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), @@ -258,12 +258,12 @@ enum { MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT8__LCD_DATA08 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT9__LCD_DATA09 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0), @@ -273,50 +273,50 @@ enum { MX6_PAD_EIM_A16__EPDC_DATA00 = IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0), MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0), MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_CSI1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0), + MX6_PAD_EIM_A17__IPU1_CSI1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0), MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0), MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0), MX6_PAD_EIM_A17__EPDC_PWR_STAT = IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0), MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0), MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_CSI1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0), + MX6_PAD_EIM_A18__IPU1_CSI1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0), MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0), MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0), MX6_PAD_EIM_A18__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0), MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0), MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_CSI1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0), + MX6_PAD_EIM_A19__IPU1_CSI1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0), MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0), MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0), MX6_PAD_EIM_A19__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0), MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0), MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0), + MX6_PAD_EIM_A20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0), MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0), MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0), MX6_PAD_EIM_A20__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0), MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0), MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_CSI1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0), + MX6_PAD_EIM_A21__IPU1_CSI1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0), MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0), MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0), MX6_PAD_EIM_A21__EPDC_GDCLK = IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0), MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0), MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_CSI1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0), + MX6_PAD_EIM_A22__IPU1_CSI1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0), MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0), MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0), MX6_PAD_EIM_A22__EPDC_GDSP = IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0), MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0), MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_CSI1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0), + MX6_PAD_EIM_A23__IPU1_CSI1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0), MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0), MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0), MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0), MX6_PAD_EIM_A23__EPDC_GDOE = IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0), MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0), MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_CSI1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0), + MX6_PAD_EIM_A24__IPU1_CSI1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0), MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0), MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0), MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0), @@ -330,7 +330,7 @@ enum { MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0), MX6_PAD_EIM_A25__EPDC_DATA15 = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0), MX6_PAD_EIM_A25__EIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__EPDC_SDCE9 = IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0), @@ -347,7 +347,7 @@ enum { MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0), MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0), MX6_PAD_EIM_D16__IPU1_DI0_PIN05 = IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU1_CSI1_DATA18 = IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0), + MX6_PAD_EIM_D16__IPU1_CSI1_DATA18 = IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0), MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0), MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0), MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0), @@ -363,7 +363,7 @@ enum { MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0), MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU1_CSI1_DATA17 = IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0), + MX6_PAD_EIM_D18__IPU1_CSI1_DATA17 = IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0), MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0), MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0), MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0), @@ -371,7 +371,7 @@ enum { MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0), MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0), MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU1_CSI1_DATA16 = IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0), + MX6_PAD_EIM_D19__IPU1_CSI1_DATA16 = IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0), MX6_PAD_EIM_D19__UART1_CTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0), MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0), MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), @@ -380,7 +380,7 @@ enum { MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0), MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0), MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0), + MX6_PAD_EIM_D20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0), MX6_PAD_EIM_D20__UART1_CTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0), MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0), MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0), @@ -388,16 +388,16 @@ enum { MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0), MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0), - MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0), + MX6_PAD_EIM_D21__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0), + MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0), MX6_PAD_EIM_D21__GPIO3_IO21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0), MX6_PAD_EIM_D21__SPDIF_IN = IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0), MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0), MX6_PAD_EIM_D22__IPU1_DI0_PIN01 = IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_CSI1_DATA10 = IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0), - MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D22__IPU1_CSI1_DATA10 = IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0), + MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0), MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0), MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0), MX6_PAD_EIM_D22__EPDC_SDCE6 = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0), @@ -418,7 +418,7 @@ enum { MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0), MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0), MX6_PAD_EIM_D24__GPIO3_IO24 = IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0), + MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0), MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0), MX6_PAD_EIM_D24__EPDC_SDCE7 = IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0), MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0), @@ -428,13 +428,13 @@ enum { MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0), MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0), MX6_PAD_EIM_D25__GPIO3_IO25 = IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0), + MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0), MX6_PAD_EIM_D25__UART1_DSR_B = IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0), MX6_PAD_EIM_D25__EPDC_SDCE8 = IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0), MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI1_DATA14 = IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0), + MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_CSI1_DATA14 = IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0), MX6_PAD_EIM_D26__UART2_TX_DATA = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), MX6_PAD_EIM_D26__UART2_RX_DATA = IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0), MX6_PAD_EIM_D26__GPIO3_IO26 = IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0), @@ -443,8 +443,8 @@ enum { MX6_PAD_EIM_D26__EPDC_SDOED = IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0), MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI1_DATA13 = IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0), + MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_CSI1_DATA13 = IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0), MX6_PAD_EIM_D27__UART2_TX_DATA = IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0), MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0), @@ -454,9 +454,9 @@ enum { MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0), MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0), MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_CSI1_DATA12 = IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0), - MX6_PAD_EIM_D28__UART2_DTE_RTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0), + MX6_PAD_EIM_D28__IPU1_CSI1_DATA12 = IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0), + MX6_PAD_EIM_D28__UART2_DTE_RTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0), MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0), @@ -473,132 +473,132 @@ enum { MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0), MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0), MX6_PAD_EIM_D30__UART3_CTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0), MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0), MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0), + MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0), MX6_PAD_EIM_D30__EPDC_SDOEZ = IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0), MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0), MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0), MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0), MX6_PAD_EIM_D31__UART3_CTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0), MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0), MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0), + MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0), MX6_PAD_EIM_D31__EPDC_SDCLK_P = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0), MX6_PAD_EIM_D31__EIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_CSI1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU1_CSI1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA0__EPDC_SDCLK_N = IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_CSI1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU1_CSI1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA1__EPDC_SDLE = IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0), MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA10__EPDC_DATA01 = IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC = IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0), MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA11__EPDC_DATA03 = IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0), MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA12__EPDC_DATA02 = IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA13__EPDC_DATA13 = IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA14__EPDC_DATA14 = IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA15__EPDC_DATA09 = IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_CSI1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU1_CSI1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA2__EPDC_BDR0 = IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_CSI1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU1_CSI1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA3__EPDC_BDR1 = IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_CSI1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU1_CSI1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA4__EPDC_SDCE0 = IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_CSI1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU1_CSI1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA5__EPDC_SDCE1 = IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_CSI1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU1_CSI1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA6__EPDC_SDCE2 = IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_CSI1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU1_CSI1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA7__EPDC_SDCE3 = IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_CSI1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU1_CSI1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA8__EPDC_SDCE4 = IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_CSI1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU1_CSI1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0), MX6_PAD_EIM_DA9__EPDC_SDCE5 = IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0), MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0), + MX6_PAD_EIM_EB0__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0), MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0), MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0), MX6_PAD_EIM_EB0__EPDC_PWR_COM = IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0), MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_CSI1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0), + MX6_PAD_EIM_EB1__IPU1_CSI1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0), MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0), MX6_PAD_EIM_EB1__EPDC_SDSHR = IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0), MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, 0), - MX6_PAD_EIM_EB2__IPU1_CSI1_DATA19 = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0), + MX6_PAD_EIM_EB2__IPU1_CSI1_DATA19 = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0), MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0), MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0), @@ -626,18 +626,18 @@ enum { MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0), MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0), MX6_PAD_EIM_OE__EPDC_PWR_IRQ = IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0), MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0), MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0), MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0), MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0), MX6_PAD_EIM_RW__EPDC_DATA07 = IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0), MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0), - MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0), + MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0), MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0), MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0), @@ -651,21 +651,21 @@ enum { MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0), + MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0), MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0), + MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0), MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0), + MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0), MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0), - MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT = IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT= IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0), - MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0), + MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0), MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0), MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0), MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), @@ -673,24 +673,24 @@ enum { MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0), MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__I2C4_SCL = IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0), MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0), + MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0), MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__I2C4_SDA = IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0), MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0), MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0), - MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0), + MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0), MX6_PAD_GPIO_0__EPIT1_OUT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), MX6_PAD_GPIO_0__GPIO1_IO00 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), MX6_PAD_GPIO_1__ESAI_RX_CLK = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), MX6_PAD_GPIO_1__KEY_ROW5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0), MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0), MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), @@ -698,7 +698,7 @@ enum { MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0), MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0), + MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0), MX6_PAD_GPIO_16__SD1_LCTL = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), MX6_PAD_GPIO_16__SPDIF_IN = IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0), MX6_PAD_GPIO_16__GPIO7_IO11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), @@ -714,9 +714,9 @@ enum { MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0), MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0), - MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0), + MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0), MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0), MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0), MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0), @@ -727,7 +727,7 @@ enum { MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0), MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0), MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0), MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0), MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0), @@ -735,7 +735,7 @@ enum { MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), MX6_PAD_GPIO_3__GPIO1_IO03 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0), - MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0), + MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0), MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0), MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0), MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), @@ -750,7 +750,7 @@ enum { MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0), MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0), + MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0), MX6_PAD_GPIO_7__ESAI_TX4_RX1 = IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0), MX6_PAD_GPIO_7__EPIT1_OUT = IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0), MX6_PAD_GPIO_7__FLEXCAN1_TX = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), @@ -771,28 +771,28 @@ enum { MX6_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), MX6_PAD_GPIO_8__I2C4_SDA = IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0), MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0), MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0), + MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0), MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0), MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0), - MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0), + MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0), MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL0__UART4_TX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0), MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0), MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0), MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, 0), - MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0), + MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0), MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL1__UART5_TX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0), MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0), MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0), MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0), MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0), @@ -809,43 +809,43 @@ enum { MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0), MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0), + MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0), MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0), MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0), MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0), MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0), + MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0), MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__UART4_TX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0), MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0), MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0), + MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0), MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__UART5_TX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0), MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0), MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0), MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0), - MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0), + MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0), MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0), MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0), MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0), @@ -858,19 +858,19 @@ enum { MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0), - MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0), - MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__I2C4_SDA = IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0), MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0), @@ -897,49 +897,49 @@ enum { MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0), MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0), MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__I2C4_SCL = IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0), - MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), + MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), + MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), + MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), + MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0), - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), - MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), + MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0), - MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0), MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), @@ -971,30 +971,30 @@ enum { MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0), MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0), - MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0), + MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0), MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0), - MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0), + MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0), MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0), + MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0), MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0), MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0), + MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0), MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0), MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0), + MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0), MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0), MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0), - MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0), + MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0), MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index 5e38556..f01f2e0 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -14,97 +14,97 @@ enum { MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0), - MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), + MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0), - MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), + MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0), - MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), + MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0), MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), + MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), - MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), + MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), + MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), + MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), + MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), + MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), + MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0), + MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0), - MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0), MX6_PAD_EIM_EB2__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0), MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0), MX6_PAD_EIM_EB2__SRC_BOOT_CFG30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0), MX6_PAD_EIM_D16__IPU1_DI0_PIN05 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), MX6_PAD_EIM_D16__IPU2_CSI1_DATA18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0), MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0), - MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0), MX6_PAD_EIM_D17__IPU1_DI0_PIN06 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0), - MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0), - MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0), MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), MX6_PAD_EIM_D18__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), - MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0), - MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), MX6_PAD_EIM_D19__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), @@ -112,39 +112,39 @@ enum { MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0), - MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), MX6_PAD_EIM_D20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), MX6_PAD_EIM_D20__UART1_CTS_B = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), MX6_PAD_EIM_D20__EPIT2_OUT = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), MX6_PAD_EIM_D21__IPU2_CSI1_DATA11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), - MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), + MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), MX6_PAD_EIM_D21__GPIO3_IO21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0), MX6_PAD_EIM_D21__SPDIF_IN = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), - MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), MX6_PAD_EIM_D22__IPU1_DI0_PIN01 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), MX6_PAD_EIM_D22__IPU2_CSI1_DATA10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), - MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), + MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), MX6_PAD_EIM_D23__UART3_CTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), MX6_PAD_EIM_D23__UART3_RTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), MX6_PAD_EIM_D23__UART1_DCD_B = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0), MX6_PAD_EIM_D23__GPIO3_IO23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), MX6_PAD_EIM_D23__IPU1_DI1_PIN02 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EIM_EB3_B = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), + MX6_PAD_EIM_EB3__EIM_EB3_B = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), MX6_PAD_EIM_EB3__UART3_CTS_B = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), MX6_PAD_EIM_EB3__UART3_RTS_B = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), @@ -153,129 +153,129 @@ enum { MX6_PAD_EIM_EB3__GPIO2_IO31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB3__IPU1_DI1_PIN03 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), MX6_PAD_EIM_EB3__SRC_BOOT_CFG31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__EIM_DATA24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D24__EIM_DATA24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), MX6_PAD_EIM_D24__UART3_TX_DATA = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), MX6_PAD_EIM_D24__UART3_RX_DATA = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0), MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), MX6_PAD_EIM_D24__GPIO3_IO24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), + MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0), MX6_PAD_EIM_D25__UART3_TX_DATA = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0), MX6_PAD_EIM_D25__UART3_RX_DATA = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0), MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), MX6_PAD_EIM_D25__GPIO3_IO25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), + MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), MX6_PAD_EIM_D25__UART1_DSR_B = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), MX6_PAD_EIM_D26__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), MX6_PAD_EIM_D26__UART2_TX_DATA = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), MX6_PAD_EIM_D26__UART2_RX_DATA = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), MX6_PAD_EIM_D26__GPIO3_IO26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), MX6_PAD_EIM_D26__IPU1_SISG2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU2_CSI1_DATA13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), MX6_PAD_EIM_D27__UART2_TX_DATA = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0), MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU1_SISG3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0), MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU2_CSI1_DATA12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), - MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), + MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), MX6_PAD_EIM_D28__UART2_DTE_RTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0), MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__EIM_DATA29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D29__EIM_DATA29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0), MX6_PAD_EIM_D29__UART2_CTS_B = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), MX6_PAD_EIM_D29__UART2_RTS_B = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), MX6_PAD_EIM_D29__GPIO3_IO29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), + MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), MX6_PAD_EIM_D30__UART3_CTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0), MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), - MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), + MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), + MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), MX6_PAD_EIM_D31__UART3_CTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), + MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), MX6_PAD_EIM_A24__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), MX6_PAD_EIM_A24__IPU2_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), MX6_PAD_EIM_A23__IPU2_CSI1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), MX6_PAD_EIM_A23__IPU2_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), MX6_PAD_EIM_A22__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), MX6_PAD_EIM_A21__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), MX6_PAD_EIM_A20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), MX6_PAD_EIM_A19__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), MX6_PAD_EIM_A18__IPU2_CSI1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), MX6_PAD_EIM_A17__IPU2_CSI1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0), MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0), MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), + MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0), MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), @@ -283,143 +283,143 @@ enum { MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0), MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0), MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), MX6_PAD_EIM_LBA__EIM_LBA_B = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0), MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), MX6_PAD_EIM_EB0__IPU2_CSI1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), MX6_PAD_EIM_EB1__IPU2_CSI1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU2_CSI1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA0__IPU2_CSI1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU2_CSI1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA1__IPU2_CSI1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU2_CSI1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA2__IPU2_CSI1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU2_CSI1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA3__IPU2_CSI1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU2_CSI1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA4__IPU2_CSI1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU2_CSI1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA5__IPU2_CSI1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU2_CSI1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA6__IPU2_CSI1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU2_CSI1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA7__IPU2_CSI1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU2_CSI1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA8__IPU2_CSI1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU2_CSI1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), + MX6_PAD_EIM_DA9__IPU2_CSI1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), + MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0), MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0), MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__IPU2_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), + MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), @@ -432,12 +432,12 @@ enum { MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), @@ -446,12 +446,12 @@ enum { MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), @@ -464,62 +464,62 @@ enum { MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), + MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), + MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), - MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), + MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), + MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0), - MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), + MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0), - MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), + MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), - MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), - MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), + MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), + MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), + MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0), - MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), - MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), + MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), + MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), + MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), + MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), + MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), + MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), + MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), + MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0), MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), @@ -532,11 +532,11 @@ enum { MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x04EC, 0x01D8, 0, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), + MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), - MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), + MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT= IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), @@ -546,7 +546,7 @@ enum { MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), - MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), + MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0), @@ -554,61 +554,61 @@ enum { MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), + MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0), MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), + MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), + MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0), MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), - MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), + MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL0__UART4_TX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), + MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0), MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), + MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__UART4_TX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0), MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0), - MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), + MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL1__UART5_TX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), + MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0), MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), + MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__UART5_TX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0), MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0), MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0), MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0), @@ -618,63 +618,63 @@ enum { MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0), MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), - MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), + MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0), MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0), MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), + MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), - MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), + MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), MX6_PAD_GPIO_0__EPIT1_OUT = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), MX6_PAD_GPIO_0__GPIO1_IO00 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), + MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), MX6_PAD_GPIO_1__ESAI_RX_CLK = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), MX6_PAD_GPIO_1__KEY_ROW5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), - MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), + MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), + MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0), - MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), + MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), MX6_PAD_GPIO_3__GPIO1_IO03 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), - MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), + MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), + MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0), MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), + MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), @@ -706,7 +706,7 @@ enum { MX6_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), + MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), MX6_PAD_GPIO_16__SD1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), MX6_PAD_GPIO_16__SPDIF_IN = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), MX6_PAD_GPIO_16__GPIO7_IO11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), @@ -720,11 +720,11 @@ enum { MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0), - MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), - MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), + MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), + MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), + MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0), MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), @@ -734,7 +734,7 @@ enum { MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0), MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), @@ -744,115 +744,115 @@ enum { MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0), MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), - MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0), MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), - MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0), MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), - MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0), MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), - MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0), MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0), MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0), MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0), MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), - MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), + MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), + MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT6__UART1_TX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0), @@ -860,7 +860,7 @@ enum { MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), + MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), MX6_PAD_SD3_DAT4__UART2_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0), @@ -902,29 +902,29 @@ enum { MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__IPU2_SISG5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_WP_B__IPU2_SISG5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__IPU2_DI0_PIN01 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), + MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), - MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS2__IPU2_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), - MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), + MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), MX6_PAD_NANDF_CS3__IPU2_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), @@ -986,7 +986,7 @@ enum { MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), + MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0), @@ -1023,17 +1023,17 @@ enum { MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0), MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), - MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), + MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0), MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), - MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), + MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), - MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), + MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), }; -- cgit v0.10.2 From 79e5f27b09023410916e71c281259aa097982514 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 12 Oct 2013 20:36:25 +0200 Subject: Net: FEC: Fix huge memory leak The fec_halt() never free'd both RX and TX DMA descriptors that were allocated in fec_init(), nor did it free the RX buffers. Rework the FEC driver so that these descriptors and buffers are allocated only once in fec_probe(). Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 107cd6e..3b2b995 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -270,49 +270,34 @@ static int fec_tx_task_disable(struct fec_priv *fec) * @param[in] dsize desired size of each receive buffer * @return 0 on success * - * For this task we need additional memory for the data buffers. And each - * data buffer requires some alignment. Thy must be aligned to a specific - * boundary each. + * Init all RX descriptors to default values. */ -static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) +static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) { uint32_t size; + uint8_t *data; int i; /* - * Allocate memory for the buffers. This allocation respects the - * alignment + * Reload the RX descriptors with default values and wipe + * the RX buffers. */ size = roundup(dsize, ARCH_DMA_MINALIGN); for (i = 0; i < count; i++) { - uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); - if (data_ptr == 0) { - uint8_t *data = memalign(ARCH_DMA_MINALIGN, - size); - if (!data) { - printf("%s: error allocating rxbuf %d\n", - __func__, i); - goto err; - } - writel((uint32_t)data, &fec->rbd_base[i].data_pointer); - } /* needs allocation */ - writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); - writew(0, &fec->rbd_base[i].data_length); + data = (uint8_t *)fec->rbd_base[i].data_pointer; + memset(data, 0, dsize); + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; } /* Mark the last RBD to close the ring. */ - writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; fec->rbd_index = 0; - return 0; - -err: - for (; i >= 0; i--) { - uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); - free((void *)data_ptr); - } - - return -ENOMEM; + flush_dcache_range((unsigned)fec->rbd_base, + (unsigned)fec->rbd_base + size); } /** @@ -332,10 +317,12 @@ static void fec_tbd_init(struct fec_priv *fec) unsigned addr = (unsigned)fec->tbd_base; unsigned size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); - writew(0x0000, &fec->tbd_base[0].status); - writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); + + memset(fec->tbd_base, 0, size); + fec->tbd_base[0].status = 0; + fec->tbd_base[1].status = FEC_TBD_WRAP; fec->tbd_index = 0; - flush_dcache_range(addr, addr+size); + flush_dcache_range(addr, addr + size); } /** @@ -527,51 +514,18 @@ static int fec_init(struct eth_device *dev, bd_t* bd) { struct fec_priv *fec = (struct fec_priv *)dev->priv; uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; - uint32_t size; - int i, ret; + int i; /* Initialize MAC address */ fec_set_hwaddr(dev); /* - * Allocate transmit descriptors, there are two in total. This - * allocation respects cache alignment. + * Setup transmit descriptors, there are two in total. */ - if (!fec->tbd_base) { - size = roundup(2 * sizeof(struct fec_bd), - ARCH_DMA_MINALIGN); - fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); - if (!fec->tbd_base) { - ret = -ENOMEM; - goto err1; - } - memset(fec->tbd_base, 0, size); - fec_tbd_init(fec); - } + fec_tbd_init(fec); - /* - * Allocate receive descriptors. This allocation respects cache - * alignment. - */ - if (!fec->rbd_base) { - size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), - ARCH_DMA_MINALIGN); - fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); - if (!fec->rbd_base) { - ret = -ENOMEM; - goto err2; - } - memset(fec->rbd_base, 0, size); - /* - * Initialize RxBD ring - */ - if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { - ret = -ENOMEM; - goto err3; - } - flush_dcache_range((unsigned)fec->rbd_base, - (unsigned)fec->rbd_base + size); - } + /* Setup receive descriptors. */ + fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); fec_reg_setup(fec); @@ -608,13 +562,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd) #endif fec_open(dev); return 0; - -err3: - free(fec->rbd_base); -err2: - free(fec->tbd_base); -err1: - return ret; } /** @@ -907,6 +854,74 @@ static void fec_set_dev_name(char *dest, int dev_id) sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); } +static int fec_alloc_descs(struct fec_priv *fec) +{ + unsigned int size; + int i; + uint8_t *data; + + /* Allocate TX descriptors. */ + size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->tbd_base) + goto err_tx; + + /* Allocate RX descriptors. */ + size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->rbd_base) + goto err_rx; + + memset(fec->rbd_base, 0, size); + + /* Allocate RX buffers. */ + + /* Maximum RX buffer size. */ + size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN); + for (i = 0; i < FEC_RBD_NUM; i++) { + data = memalign(ARCH_DMA_MINALIGN, size); + if (!data) { + printf("%s: error allocating rxbuf %d\n", __func__, i); + goto err_ring; + } + + memset(data, 0, size); + + fec->rbd_base[i].data_pointer = (uint32_t)data; + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; + /* Flush the buffer to memory. */ + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + } + + /* Mark the last RBD to close the ring. */ + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; + + fec->rbd_index = 0; + fec->tbd_index = 0; + + return 0; + +err_ring: + for (; i >= 0; i--) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); +err_rx: + free(fec->tbd_base); +err_tx: + return -ENOMEM; +} + +static void fec_free_descs(struct fec_priv *fec) +{ + int i; + + for (i = 0; i < FEC_RBD_NUM; i++) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); + free(fec->tbd_base); +} + #ifdef CONFIG_PHYLIB int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, struct mii_dev *bus, struct phy_device *phydev) @@ -939,6 +954,10 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, memset(edev, 0, sizeof(*edev)); memset(fec, 0, sizeof(*fec)); + ret = fec_alloc_descs(fec); + if (ret) + goto err3; + edev->priv = fec; edev->init = fec_init; edev->send = fec_send; @@ -957,7 +976,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { printf("FEC MXC: Timeout reseting chip\n"); - goto err3; + goto err4; } udelay(10); } @@ -984,6 +1003,8 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, eth_setenv_enetaddr("ethaddr", ethaddr); } return ret; +err4: + fec_free_descs(fec); err3: free(fec); err2: -- cgit v0.10.2 From 782478c181cb4ca8e1f7b9ac7b6eb0b3332d525d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 8 Nov 2013 11:08:37 -0200 Subject: nitrogen6x: Remove unused OCOTP options OCOTP driver is currently selected via CONFIG_MXC_OCOTP option. Remove the old OCOTP related options, as they are not used anymore. Signed-off-by: Fabio Estevam Acked-by: Eric Nelson diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 3df8de0..957dabe 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -62,16 +62,6 @@ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 -/* OCOTP Configs */ -#define CONFIG_CMD_IMXOTP -#ifdef CONFIG_CMD_IMXOTP -#define CONFIG_IMX_OTP -#define IMX_OTP_BASE OCOTP_BASE_ADDR -#define IMX_OTP_ADDR_MAX 0x7F -#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA -#define IMX_OTPWRITE_ENABLED -#endif - /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -- cgit v0.10.2 From 3e9cbbbb2b0787abf3e000e09886bff8c003d66f Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Fri, 8 Nov 2013 16:50:53 -0700 Subject: imx-common: remove extraneous semicolon from macro Signed-off-by: Eric Nelson diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 0cd2538..9231649 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -51,9 +51,9 @@ char *get_reset_cause(void) #if defined(CONFIG_MX53) || defined(CONFIG_MX6) #if defined(CONFIG_MX53) -#define MEMCTL_BASE ESDCTL_BASE_ADDR; +#define MEMCTL_BASE ESDCTL_BASE_ADDR #else -#define MEMCTL_BASE MMDC_P0_BASE_ADDR; +#define MEMCTL_BASE MMDC_P0_BASE_ADDR #endif static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; static const unsigned char bank_lookup[] = {3, 2}; -- cgit v0.10.2 From 56f9cfbb48b56dfc08debaa78624aa7522520c0b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 20:26:03 -0200 Subject: mx51evk: Fix pmic_init() argument On mx51evk board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index d01465e..9b43c84 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -174,7 +174,7 @@ static void power_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(CONFIG_FSL_PMIC_BUS); if (ret) return; -- cgit v0.10.2 From 4e785c6ae90724b8e0b9610a61e6afc0a8f4379d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 20:26:04 -0200 Subject: mx31pdk: Fix pmic_init() argument On mx31pdk board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 148b4f4..13b9d51 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -85,7 +85,7 @@ int board_late_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(CONFIG_FSL_PMIC_BUS); if (ret) return ret; -- cgit v0.10.2 From d74b331f2ff083252d53b136f3cec9cb1ca2fc9e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 20:26:05 -0200 Subject: efikamx: Fix pmic_init() argument On efikamx board the PMIC is connected via SPI interface, so it does not make sense to pass I2C_PMIC into the pmic_init() interface. Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead. Signed-off-by: Fabio Estevam diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 76753f9..16769e5 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -159,7 +159,7 @@ static void power_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(CONFIG_FSL_PMIC_BUS); if (ret) return; -- cgit v0.10.2 From 839f4d4e87f40e68de5d57ccff502fe97513d1fa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 20:26:06 -0200 Subject: power: power_fsl: Pass p->bus in the same way for SPI and I2C cases There is no need to pass p->bus differently when the PMIC is connected via SPI or via I2C. Handle the both cases in the same way. Signed-off-by: Fabio Estevam diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index ed778f3..ac0b541 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -36,10 +36,10 @@ int pmic_init(unsigned char bus) p->name = name; p->number_of_regs = PMIC_NUM_OF_REGS; + p->bus = bus; #if defined(CONFIG_POWER_SPI) p->interface = PMIC_SPI; - p->bus = CONFIG_FSL_PMIC_BUS; p->hw.spi.cs = CONFIG_FSL_PMIC_CS; p->hw.spi.clk = CONFIG_FSL_PMIC_CLK; p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; @@ -50,7 +50,6 @@ int pmic_init(unsigned char bus) p->interface = PMIC_I2C; p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR; p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH; - p->bus = bus; #else #error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C" #endif -- cgit v0.10.2 From b48e3b04101eaae7a40107c447ed377561021997 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Nov 2013 10:34:26 -0200 Subject: mx6sabresd: Fix wrong colors in LVDS splash Currently HDMI splash screen is selected by default on mx6sabresd boards. As LVDS is also enabled, this causes incorrect colors to be displayed im the LVDS panel. Fix this by selecting the LVDS panel as the default splash output and only keep HDMI or LVDS turned on at the same time. Acked-by: Liu Ying Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 1ecedac..db9fdff 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -249,8 +249,22 @@ static int detect_hdmi(struct display_info_t const *dev) return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; } + +static void disable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + int reg = readl(&iomux->gpr[2]); + + reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_MASK); + + writel(reg, &iomux->gpr[2]); +} + static void do_enable_hdmi(struct display_info_t const *dev) { + disable_lvds(dev); imx_enable_hdmi_phy(); } @@ -263,14 +277,15 @@ static void enable_lvds(struct display_info_t const *dev) IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT; writel(reg, &iomux->gpr[2]); } + static struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = do_enable_hdmi, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = NULL, + .enable = enable_lvds, .mode = { - .name = "HDMI", + .name = "Hannstar-XGA", .refresh = 60, .xres = 1024, .yres = 768, @@ -286,11 +301,11 @@ static struct display_info_t const displays[] = {{ } }, { .bus = -1, .addr = 0, - .pixfmt = IPU_PIX_FMT_LVDS666, - .detect = NULL, - .enable = enable_lvds, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, .mode = { - .name = "Hannstar-XGA", + .name = "HDMI", .refresh = 60, .xres = 1024, .yres = 768, -- cgit v0.10.2 From 8bfa9c692e024bcf2b0b95be33adfa710301f83f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 8 Nov 2013 16:20:54 -0200 Subject: mx6sabresd: Add SPI NOR support mx6sabre board has a m25p32 SPI NOR connected to ECSPI1 port. Add support for it. This patch allows the SPI NOR flash to be succesfully detected: => sf probe SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index db9fdff..851cbe9 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -37,6 +37,9 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -120,6 +123,18 @@ iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -455,6 +470,10 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + return 0; } diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 79d1f34..d52c9a8 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -18,6 +18,7 @@ #define CONFIG_DISPLAY_BOARDINFO #include +#include #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS @@ -60,6 +61,17 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 9) << 8)) +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -- cgit v0.10.2 From 953ab736afa0fca087b9e7626daa28ca7adc9fa8 Mon Sep 17 00:00:00 2001 From: Giuseppe Pagano Date: Fri, 15 Nov 2013 17:42:50 +0100 Subject: udoo: Move and optimize platform register setting. Previous uDoo configuration adopts register settings for DDR3, clock, muxing, etc. taken from Nitrogen6x. uDoo schematics is rather different from that board, and it needs customized setting for most of the registers. All this changes can be considered atomical since it is part of initial support of the board. Patch changes uDoo configuration files path to a specific one, and adopt optimized value for every configured register. Signed-off-by: Giuseppe Pagano Tested-by: Fabio Estevam CC: Stefano Babic CC: Fabio Estevam diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg new file mode 100644 index 0000000..1ac0aec --- /dev/null +++ b/board/udoo/1066mhz_4x256mx16.cfg @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB + +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 + +DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg new file mode 100644 index 0000000..9cd1af1 --- /dev/null +++ b/board/udoo/clocks.cfg @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg new file mode 100644 index 0000000..78cbe17 --- /dev/null +++ b/board/udoo/ddr-setup.cfg @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + diff --git a/board/udoo/udoo.cfg b/board/udoo/udoo.cfg new file mode 100644 index 0000000..8d7ff25 --- /dev/null +++ b/board/udoo/udoo.cfg @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/boards.cfg b/boards.cfg index 7a32d3f..87740de 100644 --- a/boards.cfg +++ b/boards.cfg @@ -285,7 +285,7 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic -Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam -- cgit v0.10.2 From 078813d21db0600d440625327a1728c32e9fcc90 Mon Sep 17 00:00:00 2001 From: Giuseppe Pagano Date: Fri, 15 Nov 2013 17:42:51 +0100 Subject: udoo: Add ethernet support (FEC + Micrel KSZ9031). Add Ethernet and networking support on uDoo board (FEC +phy Micrel KSZ9031). Ethernet speed is currently limited to 10/100Mbps. Signed-off-by: Giuseppe Pagano Tested-by: Fabio Estevam CC: Stefano Babic CC: Fabio Estevam diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index ab7b655..3257aaf 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,9 @@ #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +29,9 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -58,6 +65,99 @@ static iomux_v3_cfg_t const wdog_pads[] = { MX6_PAD_EIM_D19__GPIO3_IO19, }; +int mx6_rgmii_rework(struct phy_device *phydev) +{ + /* + * Bug: Apparently uDoo does not works with Gigabit switches... + * Limiting speed to 10/100Mbps, and setting master mode, seems to + * be the only way to have a successfull PHY auto negotiation. + * How to fix: Understand why Linux kernel do not have this issue. + */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); + + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); + return 0; +} + +static iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* RGMII reset */ + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Ethernet power supply */ + MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + udelay(20); + gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */ + + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */ + + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + udelay(1000); + + gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */ + + /* Need 100ms delay to exit from reset. */ + udelay(1000 * 100); + + gpio_free(IMX_GPIO_NR(6, 24)); + gpio_free(IMX_GPIO_NR(6, 25)); + gpio_free(IMX_GPIO_NR(6, 27)); + gpio_free(IMX_GPIO_NR(6, 28)); + gpio_free(IMX_GPIO_NR(6, 29)); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); @@ -77,6 +177,37 @@ int board_mmc_getcd(struct mmc *mmc) return 1; /* Always present */ } +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + + if (!phydev) { + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + int board_mmc_init(bd_t *bis) { imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); @@ -94,6 +225,15 @@ int board_early_init_f(void) return 0; } +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + int board_init(void) { /* address of boot parameters */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 78df071..b9a493c 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -34,6 +34,22 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +/* Network support */ + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 diff --git a/include/micrel.h b/include/micrel.h index e1c62d8..1d72b50 100644 --- a/include/micrel.h +++ b/include/micrel.h @@ -15,6 +15,11 @@ #define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000 #define MII_KSZ9031_MOD_DATA_POST_INC_W 0xC000 +#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW 0x4 +#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5 +#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6 +#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8 + struct phy_device; int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val); int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum); -- cgit v0.10.2 From db6801dec36c9e0703c47ec065ee17278edbe904 Mon Sep 17 00:00:00 2001 From: Giuseppe Pagano Date: Fri, 15 Nov 2013 17:42:54 +0100 Subject: udoo: Fix watchdog during kernel boot. uDoo uses APX823-31W5 watchdog chip. Timeout is about 1.2 seconds. To disabled watchdog during kernel boot, WDI pin of that chip needs to be in "high impedance" state. I.mx6 gpio configuration does not contemplate tristate, so pin is set as input in high impedance. Signed-off-by: Giuseppe Pagano Reviewed-by: Fabio Estevam CC: Stefano Babic CC: Fabio Estevam diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index 3257aaf..081d517 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -168,6 +168,7 @@ static void setup_iomux_wdog(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); gpio_direction_output(WDT_TRG, 0); gpio_direction_output(WDT_EN, 1); + gpio_direction_input(WDT_TRG); } static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; -- cgit v0.10.2 From bd851c7a26b39309052b2359dc1994127f518534 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 8 Nov 2013 22:37:33 +0100 Subject: Revert "ARM: move interrupt_init to before relocation" Revert commit 0f5141e9 which causes boards starting in FLASH to try and write to a FLASH location. Signed-off-by: Albert ARIBAUD diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 34f50b0..9c72a53 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -435,7 +435,6 @@ void board_init_f(ulong bootflag) addr_sp += 128; /* leave 32 words for abort-stack */ gd->irq_sp = addr_sp; #endif - interrupt_init(); debug("New Stack Pointer is: %08lx\n", addr_sp); @@ -637,6 +636,8 @@ void board_init_r(gd_t *id, ulong dest_addr) misc_init_r(); #endif + /* set up exceptions */ + interrupt_init(); /* enable exceptions */ enable_interrupts(); -- cgit v0.10.2 From a5a42eec8ed64cbc72d2e59199819e48f904e38f Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Thu, 21 Nov 2013 22:32:51 +0100 Subject: ARM: fix the standalone programs The standalone programs do not use the api calls, but rely directly on u-boot variable gd->jt for the jump table. Commit fe1378a - "ARM: use r9 for gd" changed the register holding the address of gd, but the assembly code in the standalone examples was not updated accordingly. This broke the programs on ARM relying on the jumptable in the v2013.10 release. This patch unbricks them by using the correct register. Cc: Michal Simek Cc: Albert ARIBAUD Signed-off-by: Jeroen Hofstee diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 8fb1765..5d2ab56 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -40,14 +40,14 @@ gd_t *global_data; : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r11"); #elif defined(CONFIG_ARM) /* - * r8 holds the pointer to the global_data, ip is a call-clobbered + * r9 holds the pointer to the global_data, ip is a call-clobbered * register */ #define EXPORT_FUNC(x) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ -" ldr ip, [r8, %0]\n" \ +" ldr ip, [r9, %0]\n" \ " ldr pc, [ip, %1]\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "ip"); #elif defined(CONFIG_MIPS) -- cgit v0.10.2 From 12115c6ad3b91e60b874afd29ce041ef552ed1e1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 23 Aug 2013 12:26:49 -0400 Subject: am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches. Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 803aa9c..c7dad66 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -241,3 +241,11 @@ void s_init(void) sdram_init(); #endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif /* !CONFIG_SYS_DCACHE_OFF */ diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 32d2ee4..7e8731b 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -159,13 +159,4 @@ U_BOOT_CMD( "Sends U-Boot into infinite loop", "" ); - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - printf("Enable d-cache\n"); - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* CONFIG_SYS_DCACHE_OFF */ #endif /* !CONFIG_SPL_BUILD */ -- cgit v0.10.2 From dcc23576384dbb875a4427dcfa9ac8d237230d42 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 4 Dec 2013 12:22:55 +0530 Subject: ARM: OMAP4: Move TEXT_BASE down to non-HS limit With the current scenario SPL size is being overlapped with the public stack and not allowing any OMAP4 device to boot. So the suggestion came up was to move the TEXT_BASE down to non-HS limit. Fixing the same and also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image downloadable area. Discussion on this can be seen here: https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html Tested on OMAP4460 PANDA. Reported-by: Chao Xu Signed-off-by: Lokesh Vutla diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index e35f51c..f66da0d 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -116,7 +116,7 @@ struct s32ktimer { */ #define NON_SECURE_SRAM_START 0x40304000 #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4030D000 diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index ea56eeb..d099bfd 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -148,9 +148,14 @@ "fi; " \ "fi" -/* Defines for SPL */ -#define CONFIG_SPL_TEXT_BASE 0x40304350 -#define CONFIG_SPL_MAX_SIZE (38 * 1024) +/* + * Defines for SPL + * It is known that this will break HS devices. Since the current size of + * SPL is overlapped with public stack and breaking non HS devices to boot. + * So moving TEXT_BASE down to non-HS limit. + */ +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -- cgit v0.10.2 From 550e3756c52ae1c93df2a5528ab5ff6d69c7dcdc Mon Sep 17 00:00:00 2001 From: Tapani Utriainen Date: Wed, 4 Dec 2013 09:27:33 +0100 Subject: arm, omap3: Add support for TechNexion modules Add support for TechNexion TAO3530 SoM This patch has been posted quite a long time ago. I ported it to the latest mainline U-Boot version. With some additional cleanup and enhancements. Signed-off-by: Tapani Utriainen CC: Sandeep Paulraj Signed-off-by: Stefan Roese Cc: Thorsten Eisbein Cc: Tom Rini diff --git a/board/technexion/tao3530/Makefile b/board/technexion/tao3530/Makefile new file mode 100644 index 0000000..2aff383 --- /dev/null +++ b/board/technexion/tao3530/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := tao3530.o diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c new file mode 100644 index 0000000..0668c25 --- /dev/null +++ b/board/technexion/tao3530/tao3530.c @@ -0,0 +1,170 @@ +/* + * Maintainer : + * Tapani Utriainen + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "tao3530.h" + +DECLARE_GLOBAL_DATA_PTR; + +int tao3530_revision(void) +{ + int ret = 0; + + /* char *label argument is unused in gpio_request() */ + ret = gpio_request(65, ""); + if (ret) { + puts("Error: GPIO 65 not available\n"); + goto out; + } + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); + + ret = gpio_request(1, ""); + if (ret) { + puts("Error: GPIO 1 not available\n"); + goto out2; + } + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4)); + + ret = gpio_direction_input(65); + if (ret) { + puts("Error: GPIO 65 not available for input\n"); + goto out3; + } + + ret = gpio_direction_input(1); + if (ret) { + puts("Error: GPIO 1 not available for input\n"); + goto out3; + } + + ret = gpio_get_value(65) << 1 | gpio_get_value(1); + +out3: + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0)); + gpio_free(1); +out2: + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); + gpio_free(65); +out: + + return ret; +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; + struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; + + twl4030_power_init(); + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); + + /* Configure GPIOs to output */ + /* GPIO23 */ + writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); + writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); + + /* Set GPIOs */ + writel(GPIO10 | GPIO8 | GPIO2 | GPIO1, + &gpio6_base->setdataout); + writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + + dieid_num_r(); + + /* Set memory size environment variable, depending on revision */ + switch (tao3530_revision()) { + case 0x2: /* Rev C1 -- 256MB */ + setenv("mem_size", "mem=256M"); + break; + case 0x3: /* Rev A2/B2 -- 128MB */ + setenv("mem_size", "mem=128M"); + break; + default: + printf("Warning: Unknown TAO3530 rev, setting mem=128M\n"); + } + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_TAO3530(); +} + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + + return 0; +} +#endif + +#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) +/* Call usb_stop() before starting the kernel */ +void show_boot_progress(int val) +{ + if (val == BOOTSTAGE_ID_RUN_OS) + usb_stop(); +} + +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED +}; + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(int index) +{ + return omap_ehci_hcd_stop(); +} +#endif /* CONFIG_USB_EHCI */ diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h new file mode 100644 index 0000000..1ea767d --- /dev/null +++ b/board/technexion/tao3530/tao3530.h @@ -0,0 +1,364 @@ +/* + * (C) Copyright TechNexion 2010 + * Edward Lin + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _TAO3530_H_ +#define _TAO3530_H_ + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "OMAP3 TAO-3530 board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_TAO3530() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) \ + /* - CAM_RESET*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) \ + /* MMC2 WLAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ + /*LocalBus LAN Reset*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \ + /*LocalBus LAN IRQ*/\ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) \ + /* USB EHCI (port 2) */\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) \ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) \ + /* - VIO_1V8*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M1)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN|PTU|DIS|M3)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) \ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) + +#endif diff --git a/boards.cfg b/boards.cfg index 2128996..e9d3324 100644 --- a/boards.cfg +++ b/boards.cfg @@ -328,6 +328,7 @@ Active arm armv7 omap3 logicpd zoom1 Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár +Active arm armv7 omap3 technexion tao3530 tao3530 - Tapani Utriainen Active arm armv7 omap3 technexion twister twister - Stefano Babic Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h new file mode 100644 index 0000000..cf20ae7 --- /dev/null +++ b/include/configs/tao3530.h @@ -0,0 +1,301 @@ +/* + * Configuration settings for the TechNexion TAO-3530 SOM + * equipped on Thunder baseboard. + * + * Edward Lin + * Tapani Utriainen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ + +#define CONFIG_OMAP_GPIO +#define CONFIG_OMAP_COMMON + +#define MACH_TYPE_OMAP3_TAO3530 2836 + +#define CONFIG_SDRC /* Has an SDRC controller */ + +#include /* get chip and board defs */ +#include + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_OF_LIBFDT + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* commands to include */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ + "1920k(u-boot),128k(u-boot-env),"\ + "4m(kernel),-(fs)" + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_OMAP34XX +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_I2C_MULTI_BUS + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +/* Environment information */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mpurate=600\0" \ + "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ + "tv_mode=omapfb.mode=tv:ntsc\0" \ + "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ + "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ + "extra_options= \0" \ + "mem_size=mem=128M \0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=ubi0:rootfs ubi.mtd=4\0" \ + "nandrootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${mem_size} " \ + "mpurate=${mpurate} " \ + "${video_mode} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype} " \ + "${extra_options}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${mem_size} " \ + "mpurate=${mpurate} " \ + "${video_mode} " \ + "${network_setting} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype} "\ + "${extra_options}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "TAO-3530 # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* turn on command-line edit/hist/auto */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_COMMAND_HISTORY +#define CONFIG_AUTO_COMPLETE + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_ALT_MEMTEST 1 +#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ + /* defaults */ +#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ +#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ + /* load address */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_OMAP3_SPI + +/* + * USB + * + * Currently only EHCI is enabled, the MUSB OTG controller + * is not enabled. + */ + +/* USB EHCI */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 + +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETHER_RNDIS +#define CONFIG_USB_STORAGE +#define CONGIG_CMD_STORAGE + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From a9f524904730a0f722483938bf7eb8baedbc2448 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Dec 2013 09:27:34 +0100 Subject: arm: omap3: Add SPL support to tao3530 Add SPL support for the Technexion TAO3530 SOM to replace x-loader. Tested with the Thunder baseboard. Currently this is only tested with the TAO3530 SOM revision (Ax/Bx). Tested by booting via MMC and NAND. Signed-off-by: Stefan Roese Cc: Tapani Utriainen Cc: Thorsten Eisbein Cc: Tom Rini diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index 0668c25..9268d38 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -67,6 +67,31 @@ out: return ret; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + if (tao3530_revision() < 3) { + /* 256MB / Bank */ + timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */ + timings->ctrla = HYNIX_V_ACTIMA_165; + timings->ctrlb = HYNIX_V_ACTIMB_165; + } else { + /* 128MB / Bank */ + timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */ + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + } + + timings->mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; +} +#endif + /* * Routine: board_init * Description: Early hardware init. @@ -134,7 +159,7 @@ void set_muxconf_regs(void) MUX_TAO3530(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0, -1, -1); diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index cf20ae7..fdc6c06 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -5,6 +5,8 @@ * Edward Lin * Tapani Utriainen * + * Copyright (C) 2013 Stefan Roese + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -298,4 +300,67 @@ #define CONFIG_USB_STORAGE #define CONGIG_CMD_STORAGE +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_SIMPLE + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +/* + * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: + * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT + */ +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13 } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* + * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the + * older x-loader implementations. And move the BSS area so that it + * doesn't overlap with TEXT_BASE. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */ -- cgit v0.10.2 From b36f457c1bc726f4452fdc55230a067c1704eaf8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Dec 2013 09:27:35 +0100 Subject: arm: omap3: Remove bootargs mem_size handling The memory size is autodetected and is passed to the Linux kernel either via ATAGs or device-tree (dtb). So there is no need to pass it via the bootargs. Signed-off-by: Stefan Roese Cc: Tapani Utriainen Cc: Thorsten Eisbein Cc: Tom Rini diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index 9268d38..814537b 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -133,18 +133,6 @@ int misc_init_r(void) dieid_num_r(); - /* Set memory size environment variable, depending on revision */ - switch (tao3530_revision()) { - case 0x2: /* Rev C1 -- 256MB */ - setenv("mem_size", "mem=256M"); - break; - case 0x3: /* Rev A2/B2 -- 128MB */ - setenv("mem_size", "mem=128M"); - break; - default: - printf("Warning: Unknown TAO3530 rev, setting mem=128M\n"); - } - return 0; } diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index fdc6c06..9abfe82 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -146,21 +146,18 @@ "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ "extra_options= \0" \ - "mem_size=mem=128M \0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext3 rootwait\0" \ "nandroot=ubi0:rootfs ubi.mtd=4\0" \ "nandrootfstype=ubifs\0" \ "mmcargs=setenv bootargs console=${console} " \ - "${mem_size} " \ "mpurate=${mpurate} " \ "${video_mode} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype} " \ "${extra_options}\0" \ "nandargs=setenv bootargs console=${console} " \ - "${mem_size} " \ "mpurate=${mpurate} " \ "${video_mode} " \ "${network_setting} " \ -- cgit v0.10.2 From fcd9adc3c698349cf23b2561cdb58ca805fc9817 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Dec 2013 09:27:36 +0100 Subject: arm: omap3: Add board revision output to tao3530 Signed-off-by: Stefan Roese Cc: Tapani Utriainen Cc: Thorsten Eisbein Cc: Tom Rini diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index 814537b..5041eaf 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -131,6 +131,23 @@ int misc_init_r(void) writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + switch (tao3530_revision()) { + case 0: + puts("TAO-3530 REV Reserve 1\n"); + break; + case 1: + puts("TAO-3530 REV Reserve 2\n"); + break; + case 2: + puts("TAO-3530 REV Cx\n"); + break; + case 3: + puts("TAO-3530 REV Ax/Bx\n"); + break; + default: + puts("Unknown board revision\n"); + } + dieid_num_r(); return 0; -- cgit v0.10.2 From 8f0cbd62edb6fad4d62272ef3f76b3dd74c3a1ad Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Dec 2013 09:27:37 +0100 Subject: arm: omap3: Add HEAD acoustics (HA) board variant omap3_ha to tao3530 The Head acoustics (HA) baseboard used the Technexion TAO3530 SOM and has only some minor differences to the Technexion Thunder baseboard. This patch adds support for this HA baseboard / TAO3530 as the "omap3_ha" build target. Signed-off-by: Stefan Roese Cc: Tapani Utriainen Cc: Thorsten Eisbein Cc: Tom Rini diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index 5041eaf..44a8240 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -75,6 +75,18 @@ out: */ void get_board_mem_timings(struct board_sdrc_timings *timings) { +#if defined(CONFIG_SYS_BOARD_OMAP3_HA) + /* + * Switch baseboard LED to red upon power-on + */ + MUX_OMAP3_HA(); + + /* Request a gpio before using it */ + gpio_request(111, ""); + /* Sets the gpio as output and its value to 1, switch LED to red */ + gpio_direction_output(111, 1); +#endif + if (tao3530_revision() < 3) { /* 256MB / Bank */ timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */ @@ -162,6 +174,9 @@ int misc_init_r(void) void set_muxconf_regs(void) { MUX_TAO3530(); +#if defined(CONFIG_SYS_BOARD_OMAP3_HA) + MUX_OMAP3_HA(); +#endif } #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h index 1ea767d..daff109 100644 --- a/board/technexion/tao3530/tao3530.h +++ b/board/technexion/tao3530/tao3530.h @@ -9,7 +9,11 @@ const omap3_sysinfo sysinfo = { DDR_STACKED, +#if defined(CONFIG_SYS_BOARD_OMAP3_HA) + "HEAD acoustics OMAP3-HA", +#else "OMAP3 TAO-3530 board", +#endif "NAND", }; @@ -361,4 +365,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) \ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) +#define MUX_OMAP3_HA() \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M4)) /* GPIO_111 */ + #endif diff --git a/boards.cfg b/boards.cfg index e9d3324..b662149 100644 --- a/boards.cfg +++ b/boards.cfg @@ -328,6 +328,7 @@ Active arm armv7 omap3 logicpd zoom1 Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár +Active arm armv7 omap3 technexion tao3530 omap3_ha tao3530:SYS_BOARD_OMAP3_HA Stefan Roese Active arm armv7 omap3 technexion tao3530 tao3530 - Tapani Utriainen Active arm armv7 omap3 technexion twister twister - Stefano Babic Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic -- cgit v0.10.2 From 3e51b7c8b8b076dc5115ca4b6a457f55f6de3cae Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Dec 2013 13:54:18 +0100 Subject: arm: omap3: Add SPL support to cm_t35 Add SPL U-Boot support to replace x-loader on the Compulab cm_t35 board. Currently only the 256MiB SDRAM board versions are supported. Tested by booting via MMC and NAND. Signed-off-by: Stefan Roese Cc: Tom Rini Cc: Igor Grinberg Cc: Nikita Kiryanov Acked-by: Igor Grinberg diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index bc8e0ca..00bcf41 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -105,6 +105,22 @@ static inline int splash_load_from_nand(void) } #endif /* CONFIG_CMD_NAND */ +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + timings->mr = MICRON_V_MR_165; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; +} +#endif + int splash_screen_prepare(void) { char *env_splashimage_value; @@ -440,7 +456,7 @@ void set_muxconf_regs(void) cm_t3730_set_muxconf(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_getcd(struct mmc *mmc) { u8 val; diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index e72187e..2917819 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -27,8 +27,6 @@ #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ #define CONFIG_OMAP_COMMON -#define CONFIG_SYS_TEXT_BASE 0x80008000 - #define CONFIG_SDRC /* The chip has SDRC controller */ #include /* get chip and board defs */ @@ -330,4 +328,67 @@ #define CONFIG_OMAP3_SPI +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_SIMPLE + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +/* + * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: + * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT + */ +#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12 } +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* + * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the + * older x-loader implementations. And move the BSS area so that it + * doesn't overlap with TEXT_BASE. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */ -- cgit v0.10.2 From ba481c58dff1dcfa6adb8b69bbf11ffef8ccdaa0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 4 Dec 2013 09:14:20 -0500 Subject: am335x_evm: Consolidate DFU environment parts into the DFU part of the file To make managing the environment easier, add DFUARGS to CONFIG_EXTRA_ENV_SETTINGS. Then we set DFUARGS down in the DFU part of the file, and include (or not) the NAND part, based on if NAND is set. Signed-off-by: Tom Rini diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 8af4d6a..73a9adb 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -39,7 +39,6 @@ "${optargs} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ - "dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ "nandrootfstype=ubifs rootwait=1\0" \ "nandboot=echo Booting from nand ...; " \ @@ -66,8 +65,6 @@ "fdtfile=undefined\0" \ "console=ttyO0,115200n8\0" \ "optargs=\0" \ - "dfu_alt_info_mmc=" DFU_ALT_INFO_MMC "\0" \ - "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ @@ -99,7 +96,6 @@ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ - "dfu_alt_info_ram=" DFU_ALT_INFO_RAM "\0" \ "ramargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${ramroot} " \ @@ -162,7 +158,8 @@ "setenv fdtfile am335x-evmsk.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ - NANDARGS + NANDARGS \ + DFUARGS #endif #define CONFIG_BOOTCOMMAND \ @@ -309,6 +306,7 @@ #define CONFIG_DFU_MMC #define CONFIG_CMD_DFU #define DFU_ALT_INFO_MMC \ + "dfu_alt_info_mmc=" \ "boot part 0 1;" \ "rootfs part 0 2;" \ "MLO fat 0 1;" \ @@ -319,10 +317,11 @@ "spl-os-args fat 0 1;" \ "spl-os-image fat 0 1;" \ "u-boot.img fat 0 1;" \ - "uEnv.txt fat 0 1" + "uEnv.txt fat 0 1\0" #ifdef CONFIG_NAND #define CONFIG_DFU_NAND #define DFU_ALT_INFO_NAND \ + "dfu_alt_info_nand=" \ "SPL part 0 1;" \ "SPL.backup1 part 0 2;" \ "SPL.backup2 part 0 3;" \ @@ -330,13 +329,21 @@ "u-boot part 0 5;" \ "u-boot-spl-os part 0 6;" \ "kernel part 0 8;" \ - "rootfs part 0 9" + "rootfs part 0 9\0" +#else +#define DFU_ALT_INFO_NAND "" #endif #define CONFIG_DFU_RAM #define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ "kernel ram 0x80200000 0xD80000;" \ "fdt ram 0x80F80000 0x80000;" \ - "ramdisk ram 0x81000000 0x4000000" + "ramdisk ram 0x81000000 0x4000000\0" +#define DFUARGS \ + "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_NAND /* * Default to using SPI for environment, etc. -- cgit v0.10.2 From 052fb1960349aa975ad6a5eab26ec9713cdb3649 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Thu, 5 Dec 2013 07:19:17 -0600 Subject: arm: am437: Fix offset for USB registers Fix the offset for the USB clock registers Signed-off-by: Dan Murphy diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 3b665e6..3fb2479 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -54,11 +54,11 @@ /* USB Clock Control */ #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) -#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 2) +#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) -#define USBPHYOCPSCP_MODULE_EN (1 << 2) +#define USBPHYOCPSCP_MODULE_EN (1 << 1) #endif /* __AM43XX_HARDWARE_AM43XX_H */ -- cgit v0.10.2 From 47b4bcf785cc5e505f38be10d16230e8f54e29ae Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Sun, 8 Dec 2013 14:29:19 +0200 Subject: arm: omap: abb: add missing include ABB code uses LDELAY but does not include the header that provides its definition. Include the header. Cc: Tom Rini Signed-off-by: Nikita Kiryanov Acked-by: Nishanth Menon diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c index a46783f..423aeb9 100644 --- a/arch/arm/cpu/armv7/omap-common/abb.c +++ b/arch/arm/cpu/armv7/omap-common/abb.c @@ -11,6 +11,7 @@ #include #include +#include #include #include -- cgit v0.10.2 From dc427369b1b0407baa0db1e2e365e42d4dde486d Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 10 Dec 2013 11:56:53 +0100 Subject: am335x, siemens boards: adapt default environment setting commit 16297cfb2a20c9d89834cd9e31edac5184a777a1 Author: Mateusz Zalega Date: Fri Oct 4 19:22:26 2013 +0200 usb: new board-specific USB init interface introduced a new parameter to the dfu command. Adapt the default environment for the siemens boards. Signed-off-by: Heiko Schocher Cc: Tom Rini Cc: Lukasz Majewski Cc: Mateusz Zalega diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 4569fd4..2863042 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -401,7 +401,7 @@ "dfu_args=run bootargs_defaults;" \ "setenv bootargs ${bootargs} ;" \ "mtdparts default; " \ - "dfu nand 0; \0" \ + "dfu 0 nand 0; \0" \ "dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \ "net_args=run bootargs_defaults;" \ "mtdparts default;" \ -- cgit v0.10.2 From 6a1df37349d6a01c505ffe5e11e5f623f3d9652e Mon Sep 17 00:00:00 2001 From: Yegor Yefremov Date: Wed, 11 Dec 2013 15:41:11 +0100 Subject: am3517_evm: activate Ethernet PHY Pin 30 is connected to PHY's RESET# signal, so it must be put to high. Otherwise PHY won't be found via MDIO interface. Signed-off-by: Yegor Yefremov diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 1569905..24be6ea 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define AM3517_IP_SW_RESET 0x48002598 +#define CPGMACSS_SW_RST (1 << 1) + /* * Routine: board_init * Description: Early hardware init. @@ -98,6 +102,9 @@ static void am3517_evm_musb_init(void) */ int misc_init_r(void) { + volatile unsigned int ctr; + u32 reset; + #ifdef CONFIG_SYS_I2C_OMAP34XX i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif @@ -106,6 +113,31 @@ int misc_init_r(void) am3517_evm_musb_init(); + /* activate PHY reset */ + gpio_direction_output(30, 0); + gpio_set_value(30, 0); + + ctr = 0; + do { + udelay(1000); + ctr++; + } while (ctr < 300); + + /* deactivate PHY reset */ + gpio_set_value(30, 1); + + /* allow the PHY to stabilize and settle down */ + ctr = 0; + do { + udelay(1000); + ctr++; + } while (ctr < 300); + + /* ensure that the module is out of reset */ + reset = readl(AM3517_IP_SW_RESET); + reset &= (~CPGMACSS_SW_RST); + writel(reset,AM3517_IP_SW_RESET); + return 0; } diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index 704af84..d407d66 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -315,7 +315,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ /*SYS_nRESWARM */\ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \ /* - GPIO30 */\ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ /* - PEN_IRQ */\ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 1fa477a..b8b99c8 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -58,6 +58,11 @@ */ /* + * OMAP GPIO configuration + */ +#define CONFIG_OMAP_GPIO + +/* * NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -- cgit v0.10.2 From f3ef3609dbb5a9693b2ccdfd4545e73cd273d684 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 11 Dec 2013 18:04:40 +0200 Subject: arm: omap: cm_t35: update config file This patch makes the following updates to the cm_t35 config file: - Replace "ttyS" in default environment kernel bootargs with the new "ttyO" notation. - Remove "omapfb.debug=y" from default environment kernel bootargs. - Define a minimal power-on delay for USB hub ports so that slow-to-power-on USB sticks will have enough time to become responsive. - Add support for bootz command - ulpi_reset is not necessary and always fails with the following error message: "ULPI: ulpi_reset: failed writing reset bit" So, remove it. Cc: Tom Rini Signed-off-by: Nikita Kiryanov Acked-by: Igor Grinberg Acked-by: Stefan Roese diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 2917819..4640c43 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -102,8 +102,6 @@ #define CONFIG_USB_OMAP3 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT_OMAP #define CONFIG_USB_STORAGE #define CONFIG_MUSB_UDC #define CONFIG_TWL4030_USB @@ -113,6 +111,8 @@ #define CONFIG_USB_DEVICE #define CONFIG_USB_TTY #define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* This delay is really for slow-to-power-on USB sticks, not the hub */ +#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 500 /* commands to include */ #include @@ -174,7 +174,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ - "console=ttyS2,115200n8\0" \ + "console=ttyO2,115200n8\0" \ "mpurate=500\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ @@ -188,7 +188,6 @@ "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ @@ -196,7 +195,6 @@ "mpurate=${mpurate} " \ "vram=${vram} " \ "omapfb.mode=dvi:${dvimode} " \ - "omapfb.debug=y " \ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ @@ -212,6 +210,7 @@ "nand read ${loadaddr} 2a0000 400000; " \ "bootm ${loadaddr}\0" \ +#define CONFIG_CMD_BOOTZ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ -- cgit v0.10.2 From 5298f21ab3781a8cb7fecd5ef559c81e7605d1f5 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 12 Dec 2013 15:34:56 +0530 Subject: ARM: DRA7xx: Change clk divider setting Commit "armv7: hw_data: change clock divider setting" updates the setting for m6 divider for 20MHz sys_clk frequency. But missed to update for other sys_clk frequencies. Doing the same. Reported-by: Rajendran, Vinothkumar Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 82910e8..a0d69a7 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -169,13 +169,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { }; static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { - {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ + {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */ - {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ + {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ + {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ }; static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { -- cgit v0.10.2 From d2c7074b9593d822e2359a09c21747248fdf5fac Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 12 Dec 2013 15:36:21 +0530 Subject: ARM: OMAP5: clocks: Update MPU settings for OPP_NOM As per the latest 0.6 version of DM for OMAP5430 ES2.0, MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU should be locked at 2000MHz. Fixing the same and cleaning the previously used dpll values. Reported-by: Nishanth Menon Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index a0d69a7..5268a1f 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -39,17 +39,6 @@ static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */ -static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { - {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - /* OPP NOM FREQUENCY for ES1.0 */ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -83,6 +72,7 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ @@ -272,7 +262,7 @@ struct dplls omap5_dplls_es1 = { }; struct dplls omap5_dplls_es2 = { - .mpu = mpu_dpll_params_1100mhz, + .mpu = mpu_dpll_params_1ghz, .core = core_dpll_params_2128mhz_ddr532_es2, .per = per_dpll_params_768mhz_es2, .iva = iva_dpll_params_2330mhz, -- cgit v0.10.2 From 570aa2fac3322e2e8c9dc5b4c1ac4ac95c22f9f6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 21:17:36 -0200 Subject: imx: Explicitly pass the I2C bus number in pmic_init() The pmic_init() function has the I2C or SPI bus number that is connected to the PMIC. Instead of passing I2C_PMIC, explicitly pass the I2C bus number via I2C_x definition. The motivation for doing this is to avoid people just doing a copy and paste of I2C_PMIC into their board file when another I2C bus is actually used to interface to their PMIC. This also makes more obvious which is the I2C bus connected to the PMIC, without having to search in the source code for the meaning of the 'I2C_PMIC' number. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index ebe3bcb..71a395c 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -138,7 +138,7 @@ int board_late_init(void) mx25pdk_fec_init(); - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return ret; diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 9fabef5..12467a9 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -213,7 +213,7 @@ int board_late_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return ret; diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 3b398b6..13519e2 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -81,7 +81,7 @@ void power_init(void) struct pmic *p; int ret; - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return; diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index ae7eca8..db0bf17 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -258,7 +258,7 @@ static int power_init(void) } if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { - ret = pmic_init(I2C_PMIC); + ret = pmic_init(I2C_0); if (ret) return ret; -- cgit v0.10.2 From b47abc36aaa4695ed50226ca1f3bd8f0b58bdaa6 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Wed, 13 Nov 2013 16:36:19 -0700 Subject: i.MX6 (DQ/DLS): use macros for mux and pad declarations This allows the use of either or both declarations from the files mx6q_pins.h and mx6dl_pins.h. All board files should include with one of the following defined in boards.cfg MX6Q - for boards targeting i.MX6Q or i.MX6D MX6DL - for boards targeting i.MX6DL MX6S - for boards targeting i.MX6S MX6QDL - for boards that support any of the above with run-time detection Pad declarations will be MX6_PAD_x for single-variant boards and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both processor classes. Signed-off-by: Eric Nelson Acked-by: Stefano Babic diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h index 1c9e3fe..dcd7f8f 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h @@ -6,18 +6,37 @@ #ifndef __ASM_ARCH_MX6_PINS_H__ #define __ASM_ARCH_MX6_PINS_H__ -#ifdef CONFIG_MX6Q +#include + +#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \ + prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc) + +#ifdef CONFIG_MX6QDL +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc), #include "mx6q_pins.h" -#else -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#undef MX6_PAD_DECL +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc), #include "mx6dl_pins.h" -#else -#if defined(CONFIG_MX6SL) +}; +#elif defined(CONFIG_MX6Q) +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), +#include "mx6q_pins.h" +}; +#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +enum { +#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ + MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), +#include "mx6dl_pins.h" +}; +#elif defined(CONFIG_MX6SL) #include "mx6sl_pins.h" #else #error "Please select cpu" -#endif /* CONFIG_MX6SL */ -#endif /* CONFIG_MX6DL or CONFIG_MX6S */ #endif /* CONFIG_MX6Q */ #endif /*__ASM_ARCH_MX6_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index d194eb0..55cc9ad 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -7,1077 +7,1074 @@ #ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__ #define __ASM_ARCH_MX6_MX6DL_PINS_H__ -#include +MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0360, 0x004C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0360, 0x004C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0360, 0x004C, 2, 0x07F8, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0360, 0x004C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0360, 0x004C, 3, 0x08FC, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0360, 0x004C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0360, 0x004C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0364, 0x0050, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0364, 0x0050, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0364, 0x0050, 2, 0x0800, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0364, 0x0050, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0364, 0x0050, 3, 0x08FC, 1, 0) +MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0364, 0x0050, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0364, 0x0050, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0368, 0x0054, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0368, 0x0054, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0368, 0x0054, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0368, 0x0054, 3, 0x0914, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0368, 0x0054, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0368, 0x0054, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x036C, 0x0058, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x036C, 0x0058, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x036C, 0x0058, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x036C, 0x0058, 3, 0x0914, 1, 0) +MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x036C, 0x0058, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x036C, 0x0058, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0370, 0x005C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0370, 0x005C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0370, 0x005C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0370, 0x005C, 3, 0x091C, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0370, 0x005C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0370, 0x005C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0374, 0x0060, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0374, 0x0060, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0374, 0x0060, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0374, 0x0060, 3, 0x091C, 1, 0) +MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0374, 0x0060, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0374, 0x0060, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0378, 0x0064, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0378, 0x0064, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0378, 0x0064, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0378, 0x0064, 3, 0x0910, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0378, 0x0064, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0378, 0x0064, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x037C, 0x0068, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x037C, 0x0068, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x037C, 0x0068, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x037C, 0x0068, 3, 0x0910, 1, 0) +MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x037C, 0x0068, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x037C, 0x0068, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0380, 0x006C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0380, 0x006C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0380, 0x006C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0380, 0x006C, 3, 0x0918, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0380, 0x006C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0380, 0x006C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0384, 0x0070, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0384, 0x0070, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0384, 0x0070, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0384, 0x0070, 3, 0x0918, 1, 0) +MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0384, 0x0070, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0388, 0x0074, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0388, 0x0074, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0388, 0x0074, 2, 0x07D8, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0388, 0x0074, 3, 0x08C0, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0388, 0x0074, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0388, 0x0074, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0388, 0x0074, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x038C, 0x0078, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x038C, 0x0078, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x038C, 0x0078, 2, 0x07E0, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x038C, 0x0078, 3, 0x08CC, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x038C, 0x0078, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x038C, 0x0078, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x038C, 0x0078, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0390, 0x007C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0390, 0x007C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0390, 0x007C, 2, 0x07DC, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0390, 0x007C, 3, 0x08C4, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0390, 0x007C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0390, 0x007C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0390, 0x007C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0394, 0x0080, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0394, 0x0080, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0394, 0x0080, 2, 0x07E4, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0394, 0x0080, 3, 0x08D0, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0394, 0x0080, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0394, 0x0080, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0394, 0x0080, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0398, 0x0084, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0398, 0x0084, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0398, 0x0084, 2, 0x07F4, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0398, 0x0084, 3, 0x08C8, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0398, 0x0084, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0398, 0x0084, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x039C, 0x0088, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x039C, 0x0088, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x039C, 0x0088, 2, 0x07FC, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x039C, 0x0088, 3, 0x08D4, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x039C, 0x0088, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x039C, 0x0088, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x03A0, 0x008C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x03A0, 0x008C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x03A0, 0x008C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x03A0, 0x008C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x03A4, 0x0090, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x03A4, 0x0090, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x03A4, 0x0090, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x03A4, 0x0090, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x03A8, 0x0094, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x03A8, 0x0094, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x03A8, 0x0094, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x03AC, 0x0098, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x03AC, 0x0098, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x03AC, 0x0098, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x03AC, 0x0098, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_DISP_CLK__LCD_CLK, 0x03B0, 0x009C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x03B0, 0x009C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__LCD_WR_RWN, 0x03B0, 0x009C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN15__LCD_ENABLE, 0x03B4, 0x00A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__LCD_RD_E, 0x03B4, 0x00A0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN2__LCD_HSYNC, 0x03B8, 0x00A4, 1, 0x08D8, 0, 0) +MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__LCD_RS, 0x03B8, 0x00A4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN3__LCD_VSYNC, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__LCD_CS, 0x03BC, 0x00A8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN4__LCD_BUSY, 0x03C0, 0x00AC, 1, 0x08D8, 1, 0) +MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x03C0, 0x00AC, 3, 0x092C, 0, 0) +MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__LCD_RESET, 0x03C0, 0x00AC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__LCD_DATA00, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x03CC, 0x00B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10, 0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT11__LCD_DATA11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT12__LCD_DATA12, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT13__LCD_DATA13, 0x03D8, 0x00C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x03D8, 0x00C4, 3, 0x07BC, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT14__LCD_DATA14, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x03DC, 0x00C8, 3, 0x07B8, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT15__LCD_DATA15, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x03E0, 0x00CC, 2, 0x07E8, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x03E0, 0x00CC, 3, 0x0804, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT16__LCD_DATA16, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x03E4, 0x00D0, 2, 0x07FC, 1, 0) +MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x03E4, 0x00D0, 3, 0x07C0, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x03E4, 0x00D0, 4, 0x08E8, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT17__LCD_DATA17, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x03E8, 0x00D4, 2, 0x07F8, 1, 0) +MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x03E8, 0x00D4, 3, 0x07B4, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x03E8, 0x00D4, 4, 0x08EC, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT18__LCD_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x03EC, 0x00D8, 2, 0x0800, 1, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x03EC, 0x00D8, 3, 0x07C4, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x03EC, 0x00D8, 4, 0x07A4, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT19__LCD_DATA19, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x03F0, 0x00DC, 2, 0x07F4, 1, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x03F0, 0x00DC, 3, 0x07B0, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x03F0, 0x00DC, 4, 0x07A0, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x03F4, 0x00E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x03F4, 0x00E0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT20__LCD_DATA20, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x03F8, 0x00E4, 2, 0x07D8, 1, 0) +MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x03F8, 0x00E4, 3, 0x07A8, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT21__LCD_DATA21, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x03FC, 0x00E8, 2, 0x07E0, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x03FC, 0x00E8, 3, 0x079C, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT22__LCD_DATA22, 0x0400, 0x00EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x0400, 0x00EC, 2, 0x07DC, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x0400, 0x00EC, 3, 0x07AC, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x0400, 0x00EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT23__LCD_DATA23, 0x0404, 0x00F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x0404, 0x00F0, 2, 0x07E4, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x0404, 0x00F0, 3, 0x0798, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x0404, 0x00F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT3__LCD_DATA03, 0x0408, 0x00F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0408, 0x00F4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0408, 0x00F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT4__LCD_DATA04, 0x040C, 0x00F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x040C, 0x00F8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x040C, 0x00F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT5__LCD_DATA05, 0x0410, 0x00FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0410, 0x00FC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0410, 0x00FC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0410, 0x00FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT6__LCD_DATA06, 0x0414, 0x0100, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x0414, 0x0100, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x0414, 0x0100, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x0414, 0x0100, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT7__LCD_DATA07, 0x0418, 0x0104, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x0418, 0x0104, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x0418, 0x0104, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT8__LCD_DATA08, 0x041C, 0x0108, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x041C, 0x0108, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x041C, 0x0108, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x041C, 0x0108, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT9__LCD_DATA09, 0x0420, 0x010C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x0420, 0x010C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x0420, 0x010C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x0420, 0x010C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x04E0, 0x0110, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x04E0, 0x0110, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_CSI1_PIXCLK, 0x04E0, 0x0110, 2, 0x08B8, 0, 0) +MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x04E0, 0x0110, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x04E0, 0x0110, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EPDC_DATA00, 0x04E0, 0x0110, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x04E4, 0x0114, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x04E4, 0x0114, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_CSI1_DATA12, 0x04E4, 0x0114, 2, 0x0890, 0, 0) +MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x04E4, 0x0114, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x04E4, 0x0114, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EPDC_PWR_STAT, 0x04E4, 0x0114, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x04E8, 0x0118, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x04E8, 0x0118, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_CSI1_DATA13, 0x04E8, 0x0118, 2, 0x0894, 0, 0) +MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x04E8, 0x0118, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x04E8, 0x0118, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EPDC_PWR_CTRL0, 0x04E8, 0x0118, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x04EC, 0x011C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x04EC, 0x011C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_CSI1_DATA14, 0x04EC, 0x011C, 2, 0x0898, 0, 0) +MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x04EC, 0x011C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x04EC, 0x011C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EPDC_PWR_CTRL1, 0x04EC, 0x011C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x04F0, 0x0120, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x04F0, 0x0120, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_CSI1_DATA15, 0x04F0, 0x0120, 2, 0x089C, 0, 0) +MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x04F0, 0x0120, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x04F0, 0x0120, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EPDC_PWR_CTRL2, 0x04F0, 0x0120, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x04F4, 0x0124, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x04F4, 0x0124, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_CSI1_DATA16, 0x04F4, 0x0124, 2, 0x08A0, 0, 0) +MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x04F4, 0x0124, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x04F4, 0x0124, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EPDC_GDCLK, 0x04F4, 0x0124, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x04F8, 0x0128, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x04F8, 0x0128, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_CSI1_DATA17, 0x04F8, 0x0128, 2, 0x08A4, 0, 0) +MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x04F8, 0x0128, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x04F8, 0x0128, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EPDC_GDSP, 0x04F8, 0x0128, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x04FC, 0x012C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x04FC, 0x012C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_CSI1_DATA18, 0x04FC, 0x012C, 2, 0x08A8, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x04FC, 0x012C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x04FC, 0x012C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x04FC, 0x012C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EPDC_GDOE, 0x04FC, 0x012C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x0500, 0x0130, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x0500, 0x0130, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_CSI1_DATA19, 0x0500, 0x0130, 2, 0x08AC, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x0500, 0x0130, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x0500, 0x0130, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x0500, 0x0130, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EPDC_GDRL, 0x0500, 0x0130, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x0504, 0x0134, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x0504, 0x0134, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x0504, 0x0134, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x0504, 0x0134, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x0504, 0x0134, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x0504, 0x0134, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x0504, 0x0134, 6, 0x085C, 0, 0) +MX6_PAD_DECL(EIM_A25__EPDC_DATA15, 0x0504, 0x0134, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ACLK_FREERUN, 0x0504, 0x0134, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x0508, 0x0138, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x0508, 0x0138, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x0508, 0x0138, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EPDC_SDCE9, 0x0508, 0x0138, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x050C, 0x013C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x050C, 0x013C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x050C, 0x013C, 2, 0x07F4, 2, 0) +MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x050C, 0x013C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EPDC_DATA06, 0x050C, 0x013C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0510, 0x0140, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0510, 0x0140, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0510, 0x0140, 2, 0x07FC, 2, 0) +MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0510, 0x0140, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EPDC_DATA08, 0x0510, 0x0140, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x0514, 0x0144, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x0514, 0x0144, 1, 0x07D8, 2, 0) +MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x0514, 0x0144, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU1_CSI1_DATA18, 0x0514, 0x0144, 3, 0x08A8, 1, 0) +MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x0514, 0x0144, 4, 0x0864, 0, 0) +MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x0514, 0x0144, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0) +MX6_PAD_DECL(EIM_D16__EPDC_DATA10, 0x0514, 0x0144, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x0518, 0x0148, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x0518, 0x0148, 1, 0x07DC, 2, 0) +MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x0518, 0x0148, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU1_CSI1_PIXCLK, 0x0518, 0x0148, 3, 0x08B8, 1, 0) +MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x0518, 0x0148, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x0518, 0x0148, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0) +MX6_PAD_DECL(EIM_D17__EPDC_VCOM0, 0x0518, 0x0148, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x051C, 0x014C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x051C, 0x014C, 1, 0x07E0, 2, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x051C, 0x014C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_CSI1_DATA17, 0x051C, 0x014C, 3, 0x08A4, 1, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x051C, 0x014C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x051C, 0x014C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0) +MX6_PAD_DECL(EIM_D18__EPDC_VCOM1, 0x051C, 0x014C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x0520, 0x0150, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x0520, 0x0150, 1, 0x07E8, 1, 0) +MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x0520, 0x0150, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU1_CSI1_DATA16, 0x0520, 0x0150, 3, 0x08A0, 1, 0) +MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x0520, 0x0150, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x0520, 0x0150, 4, 0x08F8, 0, 0) +MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x0520, 0x0150, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x0520, 0x0150, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPDC_DATA12, 0x0520, 0x0150, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x0524, 0x0154, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x0524, 0x0154, 1, 0x0808, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x0524, 0x0154, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_CSI1_DATA15, 0x0524, 0x0154, 3, 0x089C, 1, 0) +MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x0524, 0x0154, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x0524, 0x0154, 4, 0x08F8, 1, 0) +MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x0524, 0x0154, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x0524, 0x0154, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x0528, 0x0158, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x0528, 0x0158, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x0528, 0x0158, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_CSI1_DATA11, 0x0528, 0x0158, 3, 0x088C, 0, 0) +MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x0528, 0x0158, 4, 0x0920, 0, 0) +MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x0528, 0x0158, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0) +MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x0528, 0x0158, 7, 0x08F0, 0, 0) +MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x052C, 0x015C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x052C, 0x015C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x052C, 0x015C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_CSI1_DATA10, 0x052C, 0x015C, 3, 0x0888, 0, 0) +MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x052C, 0x015C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x052C, 0x015C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x052C, 0x015C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__EPDC_SDCE6, 0x052C, 0x015C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x0530, 0x0160, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x0530, 0x0160, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x0530, 0x0160, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x0530, 0x0160, 2, 0x0908, 0, 0) +MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x0530, 0x0160, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_CSI1_DATA_EN, 0x0530, 0x0160, 4, 0x08B0, 0, 0) +MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x0530, 0x0160, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x0530, 0x0160, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x0530, 0x0160, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EPDC_DATA11, 0x0530, 0x0160, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x0534, 0x0164, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x0534, 0x0164, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x0534, 0x0164, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x0534, 0x0164, 2, 0x090C, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x0534, 0x0164, 3, 0x07EC, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x0534, 0x0164, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x0534, 0x0164, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x0534, 0x0164, 6, 0x07BC, 1, 0) +MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x0534, 0x0164, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EPDC_SDCE7, 0x0534, 0x0164, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x0538, 0x0168, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x0538, 0x0168, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x0538, 0x0168, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x0538, 0x0168, 2, 0x090C, 1, 0) +MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x0538, 0x0168, 3, 0x07F0, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x0538, 0x0168, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x0538, 0x0168, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x0538, 0x0168, 6, 0x07B8, 1, 0) +MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x0538, 0x0168, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EPDC_SDCE8, 0x0538, 0x0168, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x053C, 0x016C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x053C, 0x016C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x053C, 0x016C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI1_DATA14, 0x053C, 0x016C, 3, 0x0898, 1, 0) +MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x053C, 0x016C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x053C, 0x016C, 4, 0x0904, 0, 0) +MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x053C, 0x016C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x053C, 0x016C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x053C, 0x016C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EPDC_SDOED, 0x053C, 0x016C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x0540, 0x0170, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x0540, 0x0170, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x0540, 0x0170, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI1_DATA13, 0x0540, 0x0170, 3, 0x0894, 1, 0) +MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x0540, 0x0170, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x0540, 0x0170, 4, 0x0904, 1, 0) +MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x0540, 0x0170, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x0540, 0x0170, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x0540, 0x0170, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EPDC_SDOE, 0x0540, 0x0170, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x0544, 0x0174, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0) +MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x0544, 0x0174, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_CSI1_DATA12, 0x0544, 0x0174, 3, 0x0890, 1, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x0544, 0x0174, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x0544, 0x0174, 4, 0x0900, 0, 0) +MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x0544, 0x0174, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x0544, 0x0174, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x0544, 0x0174, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EPDC_PWR_CTRL3, 0x0544, 0x0174, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x0548, 0x0178, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x0548, 0x0178, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x0548, 0x0178, 2, 0x0808, 1, 0) +MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x0548, 0x0178, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x0548, 0x0178, 4, 0x0900, 1, 0) +MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x0548, 0x0178, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_CSI1_VSYNC, 0x0548, 0x0178, 6, 0x08BC, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x0548, 0x0178, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EPDC_PWR_WAKE, 0x0548, 0x0178, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x054C, 0x017C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x054C, 0x017C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x054C, 0x017C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x054C, 0x017C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x054C, 0x017C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x054C, 0x017C, 4, 0x0908, 1, 0) +MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x054C, 0x017C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x054C, 0x017C, 6, 0x0924, 0, 0) +MX6_PAD_DECL(EIM_D30__EPDC_SDOEZ, 0x054C, 0x017C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x0550, 0x0180, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x0550, 0x0180, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x0550, 0x0180, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x0550, 0x0180, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x0550, 0x0180, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x0550, 0x0180, 4, 0x0908, 2, 0) +MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x0550, 0x0180, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x0550, 0x0180, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EPDC_SDCLK_P, 0x0550, 0x0180, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_ACLK_FREERUN, 0x0550, 0x0180, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0554, 0x0184, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0554, 0x0184, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_CSI1_DATA09, 0x0554, 0x0184, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0554, 0x0184, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0554, 0x0184, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EPDC_SDCLK_N, 0x0554, 0x0184, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x0558, 0x0188, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x0558, 0x0188, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_CSI1_DATA08, 0x0558, 0x0188, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x0558, 0x0188, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x0558, 0x0188, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EPDC_SDLE, 0x0558, 0x0188, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x055C, 0x018C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x055C, 0x018C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_CSI1_DATA_EN, 0x055C, 0x018C, 2, 0x08B0, 1, 0) +MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x055C, 0x018C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x055C, 0x018C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EPDC_DATA01, 0x055C, 0x018C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0560, 0x0190, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0560, 0x0190, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_CSI1_HSYNC, 0x0560, 0x0190, 2, 0x08B4, 0, 0) +MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0560, 0x0190, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0560, 0x0190, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EPDC_DATA03, 0x0560, 0x0190, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0564, 0x0194, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0564, 0x0194, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_CSI1_VSYNC, 0x0564, 0x0194, 2, 0x08BC, 1, 0) +MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0564, 0x0194, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0564, 0x0194, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EPDC_DATA02, 0x0564, 0x0194, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x0568, 0x0198, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x0568, 0x0198, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x0568, 0x0198, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x0568, 0x0198, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EPDC_DATA13, 0x0568, 0x0198, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x056C, 0x019C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x056C, 0x019C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x056C, 0x019C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x056C, 0x019C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EPDC_DATA14, 0x056C, 0x019C, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0570, 0x01A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0570, 0x01A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0570, 0x01A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0570, 0x01A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0570, 0x01A0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EPDC_DATA09, 0x0570, 0x01A0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0574, 0x01A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0574, 0x01A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_CSI1_DATA07, 0x0574, 0x01A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0574, 0x01A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0574, 0x01A4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EPDC_BDR0, 0x0574, 0x01A4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0578, 0x01A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0578, 0x01A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_CSI1_DATA06, 0x0578, 0x01A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0578, 0x01A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0578, 0x01A8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EPDC_BDR1, 0x0578, 0x01A8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x057C, 0x01AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x057C, 0x01AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_CSI1_DATA05, 0x057C, 0x01AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x057C, 0x01AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x057C, 0x01AC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EPDC_SDCE0, 0x057C, 0x01AC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x0580, 0x01B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x0580, 0x01B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_CSI1_DATA04, 0x0580, 0x01B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x0580, 0x01B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x0580, 0x01B0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EPDC_SDCE1, 0x0580, 0x01B0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0584, 0x01B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0584, 0x01B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_CSI1_DATA03, 0x0584, 0x01B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0584, 0x01B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0584, 0x01B4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EPDC_SDCE2, 0x0584, 0x01B4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0588, 0x01B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0588, 0x01B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_CSI1_DATA02, 0x0588, 0x01B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0588, 0x01B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0588, 0x01B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EPDC_SDCE3, 0x0588, 0x01B8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x058C, 0x01BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x058C, 0x01BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_CSI1_DATA01, 0x058C, 0x01BC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x058C, 0x01BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x058C, 0x01BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EPDC_SDCE4, 0x058C, 0x01BC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x0590, 0x01C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x0590, 0x01C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_CSI1_DATA00, 0x0590, 0x01C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x0590, 0x01C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x0590, 0x01C0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EPDC_SDCE5, 0x0590, 0x01C0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0594, 0x01C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0594, 0x01C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_CSI1_DATA11, 0x0594, 0x01C4, 2, 0x088C, 1, 0) +MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0594, 0x01C4, 4, 0x07D4, 0, 0) +MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0594, 0x01C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0594, 0x01C4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EPDC_PWR_COM, 0x0594, 0x01C4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0598, 0x01C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0598, 0x01C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_CSI1_DATA10, 0x0598, 0x01C8, 2, 0x0888, 1, 0) +MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0598, 0x01C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0598, 0x01C8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EPDC_SDSHR, 0x0598, 0x01C8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x059C, 0x01CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x059C, 0x01CC, 1, 0x07E4, 2, 0) +MX6_PAD_DECL(EIM_EB2__IPU1_CSI1_DATA19, 0x059C, 0x01CC, 3, 0x08AC, 1, 0) +MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x059C, 0x01CC, 4, 0x0860, 0, 0) +MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x059C, 0x01CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0) +MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x059C, 0x01CC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__EPDC_DATA05, 0x059C, 0x01CC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x05A0, 0x01D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x05A0, 0x01D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x05A0, 0x01D0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x05A0, 0x01D0, 2, 0x0908, 3, 0) +MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x05A0, 0x01D0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_CSI1_HSYNC, 0x05A0, 0x01D0, 4, 0x08B4, 1, 0) +MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x05A0, 0x01D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x05A0, 0x01D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x05A0, 0x01D0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EPDC_SDCE0, 0x05A0, 0x01D0, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_ACLK_FREERUN, 0x05A0, 0x01D0, 9, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x05A4, 0x01D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x05A4, 0x01D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x05A4, 0x01D4, 2, 0x0804, 1, 0) +MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x05A4, 0x01D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x05A4, 0x01D4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EPDC_DATA04, 0x05A4, 0x01D4, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x05A8, 0x01D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x05A8, 0x01D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x05A8, 0x01D8, 2, 0x07F8, 2, 0) +MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x05A8, 0x01D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EPDC_PWR_IRQ, 0x05A8, 0x01D8, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EIM_RW, 0x05AC, 0x01DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x05AC, 0x01DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x05AC, 0x01DC, 2, 0x0800, 2, 0) +MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x05AC, 0x01DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x05AC, 0x01DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EPDC_DATA07, 0x05AC, 0x01DC, 8, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x05B0, 0x01E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x05B0, 0x01E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x05B0, 0x01E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x05B0, 0x01E0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x05B4, 0x01E4, 1, 0x0828, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x05B4, 0x01E4, 2, 0x0840, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x05B4, 0x01E4, 3, 0x08F4, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x05B4, 0x01E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x05B8, 0x01E8, 0, 0x08E0, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x05B8, 0x01E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x05B8, 0x01E8, 2, 0x0858, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x05B8, 0x01E8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x05B8, 0x01E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x05BC, 0x01EC, 1, 0x0810, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x05BC, 0x01EC, 2, 0x083C, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x05BC, 0x01EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x05BC, 0x01EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x05BC, 0x01EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x05C0, 0x01F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x05C0, 0x01F0, 2, 0x082C, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x05C0, 0x01F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x05C0, 0x01F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x05C4, 0x01F4, 0, 0x0790, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x05C4, 0x01F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x05C4, 0x01F4, 2, 0x0834, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x05C4, 0x01F4, 3, 0x08F0, 1, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x05C4, 0x01F4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x05C4, 0x01F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x05C8, 0x01F8, 1, 0x0818, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x05C8, 0x01F8, 2, 0x0838, 0, 0) +MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x05CC, 0x01FC, 0, 0x08E4, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x05CC, 0x01FC, 1, 0x081C, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x05CC, 0x01FC, 2, 0x0830, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x05D0, 0x0200, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x05D0, 0x0200, 2, 0x0850, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x05D0, 0x0200, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__I2C4_SCL, 0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x05D4, 0x0204, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x05D4, 0x0204, 2, 0x0854, 0, 0) +MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x05D4, 0x0204, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x05D8, 0x0208, 0, 0x08DC, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x05D8, 0x0208, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x05D8, 0x0208, 2, 0x084C, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x05D8, 0x0208, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x05D8, 0x0208, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__I2C4_SDA, 0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0) +MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05DC, 0x020C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05DC, 0x020C, 2, 0x08C0, 1, 0) +MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05DC, 0x020C, 3, 0x0794, 0, 0) +MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05DC, 0x020C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05DC, 0x020C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05DC, 0x020C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05E0, 0x0210, 0, 0x083C, 1, 0) +MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05E0, 0x0210, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05E0, 0x0210, 2, 0x08CC, 1, 0) +MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05E0, 0x0210, 3, 0x0790, 1, 0) +MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05E0, 0x0210, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05E0, 0x0210, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x05E4, 0x0214, 0, 0x0850, 1, 0) +MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x05E4, 0x0214, 2, 0x080C, 0, 0) +MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x05E4, 0x0214, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x05E4, 0x0214, 4, 0x08F0, 2, 0) +MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x05E4, 0x0214, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0) +MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x05E4, 0x0214, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x05E8, 0x0218, 0, 0x0844, 0, 0) +MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x05E8, 0x0218, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x05E8, 0x0218, 2, 0x07D4, 1, 0) +MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x05E8, 0x0218, 3, 0x08E8, 1, 0) +MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x05E8, 0x0218, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x05E8, 0x0218, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x05EC, 0x021C, 0, 0x0848, 0, 0) +MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x05EC, 0x021C, 1, 0x0814, 0, 0) +MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x05EC, 0x021C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x05EC, 0x021C, 3, 0x08EC, 1, 0) +MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x05EC, 0x021C, 4, 0x0794, 1, 0) +MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x05EC, 0x021C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x05EC, 0x021C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x05F0, 0x0220, 0, 0x08C0, 2, 0) +MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x05F0, 0x0220, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x05F0, 0x0220, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x05F0, 0x0220, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x05F0, 0x0220, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x05F0, 0x0220, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x05F0, 0x0220, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x05F4, 0x0224, 0, 0x0830, 1, 0) +MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x05F4, 0x0224, 2, 0x08D0, 1, 0) +MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x05F4, 0x0224, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__SD2_WP, 0x05F4, 0x0224, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x05F4, 0x0224, 7, 0x08E0, 1, 0) +MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05F8, 0x0228, 0, 0x0834, 1, 0) +MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0) +MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05F8, 0x0228, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05F8, 0x0228, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05F8, 0x0228, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05F8, 0x0228, 6, 0x0924, 1, 0) +MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05F8, 0x0228, 7, 0x08DC, 1, 0) +MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x05FC, 0x022C, 0, 0x0838, 1, 0) +MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x05FC, 0x022C, 2, 0x08C8, 1, 0) +MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x05FC, 0x022C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x05FC, 0x022C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x0600, 0x0230, 0, 0x084C, 1, 0) +MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x0600, 0x0230, 2, 0x08D4, 1, 0) +MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x0600, 0x0230, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x0600, 0x0230, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0) +MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x0600, 0x0230, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0604, 0x0234, 0, 0x0840, 1, 0) +MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0) +MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0604, 0x0234, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0604, 0x0234, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0604, 0x0234, 7, 0x08E4, 1, 0) +MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0608, 0x0238, 0, 0x0854, 1, 0) +MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0608, 0x0238, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0608, 0x0238, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0608, 0x0238, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0608, 0x0238, 4, 0x0904, 2, 0) +MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0608, 0x0238, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0608, 0x0238, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0608, 0x0238, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__I2C4_SCL, 0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0) +MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x060C, 0x023C, 0, 0x0858, 1, 0) +MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x060C, 0x023C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x060C, 0x023C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x060C, 0x023C, 3, 0x07C8, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x060C, 0x023C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x060C, 0x023C, 4, 0x0904, 3, 0) +MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x060C, 0x023C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x060C, 0x023C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x060C, 0x023C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__I2C4_SDA, 0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0) +MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x0610, 0x0240, 0, 0x082C, 1, 0) +MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x0610, 0x0240, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x0610, 0x0240, 2, 0x08C4, 1, 0) +MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x0610, 0x0240, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x0610, 0x0240, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x0610, 0x0240, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__SD1_WP, 0x0610, 0x0240, 6, 0x092C, 1, 0) +MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x062C, 0x0244, 0, 0x07D8, 3, 0) +MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x062C, 0x0244, 1, 0x0824, 0, 0) +MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x062C, 0x0244, 2, 0x07C0, 1, 0) +MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x062C, 0x0244, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x062C, 0x0244, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x062C, 0x0244, 4, 0x0914, 2, 0) +MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x062C, 0x0244, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x062C, 0x0244, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x0630, 0x0248, 0, 0x07DC, 3, 0) +MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x0630, 0x0248, 1, 0x0810, 1, 0) +MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x0630, 0x0248, 2, 0x07C4, 1, 0) +MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x0630, 0x0248, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x0630, 0x0248, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x0630, 0x0248, 4, 0x091C, 2, 0) +MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x0630, 0x0248, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x0630, 0x0248, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x0634, 0x024C, 0, 0x07E8, 2, 0) +MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x0634, 0x024C, 1, 0x0820, 0, 0) +MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x0634, 0x024C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x0634, 0x024C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x0634, 0x024C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x0634, 0x024C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x0634, 0x024C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x0638, 0x0250, 0, 0x07F0, 1, 0) +MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x0638, 0x0250, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x0638, 0x0250, 2, 0x0860, 1, 0) +MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x0638, 0x0250, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0) +MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x0638, 0x0250, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x0638, 0x0250, 6, 0x08F0, 3, 0) +MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x063C, 0x0254, 0, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x063C, 0x0254, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x063C, 0x0254, 2, 0x0920, 1, 0) +MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x063C, 0x0254, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x063C, 0x0254, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x063C, 0x0254, 4, 0x0918, 2, 0) +MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x063C, 0x0254, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x0640, 0x0258, 0, 0x07E0, 3, 0) +MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x0640, 0x0258, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x0640, 0x0258, 2, 0x07B4, 1, 0) +MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x0640, 0x0258, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x0640, 0x0258, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x0640, 0x0258, 4, 0x0914, 3, 0) +MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x0640, 0x0258, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x0640, 0x0258, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x0644, 0x025C, 0, 0x07E4, 3, 0) +MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x0644, 0x025C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x0644, 0x025C, 2, 0x07B0, 1, 0) +MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x0644, 0x025C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x0644, 0x025C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x0644, 0x025C, 4, 0x091C, 3, 0) +MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x0644, 0x025C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x0644, 0x025C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x0648, 0x0260, 0, 0x07EC, 1, 0) +MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x0648, 0x0260, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x0648, 0x0260, 2, 0x07C8, 1, 0) +MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x0648, 0x0260, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x0648, 0x0260, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x0648, 0x0260, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x0648, 0x0260, 6, 0x085C, 1, 0) +MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x064C, 0x0264, 1, 0x0794, 2, 0) +MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x064C, 0x0264, 2, 0x0864, 1, 0) +MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x064C, 0x0264, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0) +MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x064C, 0x0264, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x064C, 0x0264, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x0650, 0x0268, 0, 0x07CC, 0, 0) +MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x0650, 0x0268, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x0650, 0x0268, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x0650, 0x0268, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x0650, 0x0268, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x0650, 0x0268, 4, 0x0918, 3, 0) +MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x0650, 0x0268, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x0654, 0x026C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x0654, 0x026C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x0654, 0x026C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x0658, 0x0270, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x0658, 0x0270, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x065C, 0x0274, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x065C, 0x0274, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x0660, 0x0278, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x0660, 0x0278, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x0660, 0x0278, 2, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x0660, 0x0278, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x0664, 0x027C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x0664, 0x027C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x0664, 0x027C, 2, 0x0844, 1, 0) +MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x0664, 0x027C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x0664, 0x027C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x0664, 0x027C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x0668, 0x0280, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x0668, 0x0280, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x0668, 0x0280, 2, 0x0848, 1, 0) +MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x0668, 0x0280, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x0668, 0x0280, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__I2C4_SDA, 0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0) +MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x066C, 0x0284, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x066C, 0x0284, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x066C, 0x0284, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x0670, 0x0288, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x0670, 0x0288, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x0670, 0x0288, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x0674, 0x028C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x0674, 0x028C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x0674, 0x028C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x0678, 0x0290, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x0678, 0x0290, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x0678, 0x0290, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x067C, 0x0294, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x067C, 0x0294, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x067C, 0x0294, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x0680, 0x0298, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x0680, 0x0298, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x0680, 0x0298, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x0684, 0x029C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x0684, 0x029C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x0684, 0x029C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0688, 0x02A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0688, 0x02A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0688, 0x02A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x068C, 0x02A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x068C, 0x02A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x0690, 0x02A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x0690, 0x02A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__I2C4_SCL, 0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0) +MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0694, 0x02AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0694, 0x02AC, 1, 0x0818, 1, 0) +MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0694, 0x02AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x0698, 0x02B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x0698, 0x02B0, 1, 0x081C, 1, 0) +MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x0698, 0x02B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x069C, 0x02B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x069C, 0x02B4, 1, 0x0820, 1, 0) +MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x069C, 0x02B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x06A0, 0x02B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x06A0, 0x02B8, 1, 0x0824, 1, 0) +MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x06A4, 0x02BC, 1, 0x0828, 1, 0) +MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USBOH3_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) +MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x06A8, 0x02C0, 1, 0x0814, 1, 0) +MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x06B0, 0x02C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) +MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x06BC, 0x02D4, 7, 0x080C, 1, 0) +MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x06C0, 0x02D8, 2, 0x08F4, 1, 0) +MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x06C0, 0x02D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x06C4, 0x02DC, 0, 0x0928, 1, 0) +MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x06C4, 0x02DC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x06C8, 0x02E0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x06C8, 0x02E0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x06CC, 0x02E4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x06D0, 0x02E8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x06D4, 0x02EC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x06D8, 0x02F0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x06D8, 0x02F0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x06DC, 0x02F4, 0, 0x0930, 1, 0) +MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x06DC, 0x02F4, 2, 0x08C0, 3, 0) +MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x06DC, 0x02F4, 3, 0x07A4, 1, 0) +MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x06E0, 0x02F8, 2, 0x08CC, 2, 0) +MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x06E0, 0x02F8, 3, 0x07A0, 1, 0) +MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x06E4, 0x02FC, 3, 0x0798, 1, 0) +MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x06E4, 0x02FC, 4, 0x08D4, 2, 0) +MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x06E4, 0x02FC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x06E8, 0x0300, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x06E8, 0x0300, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x06E8, 0x0300, 3, 0x07AC, 1, 0) +MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x06E8, 0x0300, 4, 0x08C8, 2, 0) +MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x06E8, 0x0300, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x06EC, 0x0304, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x06EC, 0x0304, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x06EC, 0x0304, 3, 0x079C, 1, 0) +MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x06EC, 0x0304, 4, 0x08D0, 2, 0) +MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x06EC, 0x0304, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x06F0, 0x0308, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x06F0, 0x0308, 2, 0x08C4, 2, 0) +MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x06F0, 0x0308, 3, 0x07A8, 1, 0) +MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x06F0, 0x0308, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06F4, 0x030C, 0, 0x0934, 1, 0) +MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06F4, 0x030C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06F4, 0x030C, 1, 0x0900, 2, 0) +MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06F4, 0x030C, 2, 0x07C8, 2, 0) +MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06F4, 0x030C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06F8, 0x0310, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06F8, 0x0310, 1, 0x0900, 3, 0) +MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06F8, 0x0310, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06F8, 0x0310, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06FC, 0x0314, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06FC, 0x0314, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06FC, 0x0314, 1, 0x08F8, 2, 0) +MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06FC, 0x0314, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06FC, 0x0314, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x0700, 0x0318, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x0700, 0x0318, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x0700, 0x0318, 1, 0x08F8, 3, 0) +MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x0700, 0x0318, 2, 0x07CC, 1, 0) +MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x0700, 0x0318, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x0704, 0x031C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x0704, 0x031C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x0708, 0x0320, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x0708, 0x0320, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x0708, 0x0320, 1, 0x0908, 4, 0) +MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x0708, 0x0320, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x070C, 0x0324, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x070C, 0x0324, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x070C, 0x0324, 1, 0x0904, 4, 0) +MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x070C, 0x0324, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0710, 0x0328, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0710, 0x0328, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0710, 0x0328, 1, 0x0904, 5, 0) +MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0710, 0x0328, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0714, 0x032C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0714, 0x032C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0714, 0x032C, 1, 0x08FC, 2, 0) +MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0714, 0x032C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0718, 0x0330, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0718, 0x0330, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0718, 0x0330, 1, 0x08FC, 3, 0) +MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0718, 0x0330, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x071C, 0x0334, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x071C, 0x0334, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x071C, 0x0334, 1, 0x0908, 5, 0) +MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x071C, 0x0334, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x0720, 0x0338, 0, 0x0938, 1, 0) +MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x0720, 0x0338, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x0720, 0x0338, 2, 0x090C, 2, 0) +MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x0720, 0x0338, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x0724, 0x033C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x0724, 0x033C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x0724, 0x033C, 2, 0x090C, 3, 0) +MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x0724, 0x033C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0728, 0x0340, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0728, 0x0340, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0728, 0x0340, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x072C, 0x0344, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x072C, 0x0344, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x072C, 0x0344, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x0730, 0x0348, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x0730, 0x0348, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0734, 0x034C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0734, 0x034C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0738, 0x0350, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0738, 0x0350, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0738, 0x0350, 2, 0x0904, 6, 0) +MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0738, 0x0350, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x073C, 0x0354, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x073C, 0x0354, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x073C, 0x0354, 2, 0x0900, 4, 0) +MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x073C, 0x0354, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x0740, 0x0358, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x0740, 0x0358, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x0740, 0x0358, 2, 0x0900, 5, 0) +MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x0740, 0x0358, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0744, 0x035C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0744, 0x035C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0744, 0x035C, 2, 0x0904, 7, 0) +MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0744, 0x035C, 5, 0x0000, 0, 0) -enum { - MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0360, 0x004C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0360, 0x004C, 2, 0x07F8, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0360, 0x004C, 3, 0x08FC, 0, 0), - MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0364, 0x0050, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0800, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), - MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0368, 0x0054, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0368, 0x0054, 3, 0x0914, 0, 0), - MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x036C, 0x0058, 3, 0x0914, 1, 0), - MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0370, 0x005C, 3, 0x091C, 0, 0), - MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0370, 0x005C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0374, 0x0060, 3, 0x091C, 1, 0), - MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0378, 0x0064, 3, 0x0910, 0, 0), - MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x037C, 0x0068, 3, 0x0910, 1, 0), - MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x037C, 0x0068, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0380, 0x006C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0380, 0x006C, 3, 0x0918, 0, 0), - MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0380, 0x006C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0384, 0x0070, 3, 0x0918, 1, 0), - MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0388, 0x0074, 2, 0x07D8, 0, 0), - MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0388, 0x0074, 3, 0x08C0, 0, 0), - MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0388, 0x0074, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0388, 0x0074, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x038C, 0x0078, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x038C, 0x0078, 2, 0x07E0, 0, 0), - MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x038C, 0x0078, 3, 0x08CC, 0, 0), - MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x038C, 0x0078, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0390, 0x007C, 2, 0x07DC, 0, 0), - MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0390, 0x007C, 3, 0x08C4, 0, 0), - MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0390, 0x007C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0390, 0x007C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0394, 0x0080, 2, 0x07E4, 0, 0), - MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0394, 0x0080, 3, 0x08D0, 0, 0), - MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0394, 0x0080, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0394, 0x0080, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0398, 0x0084, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0398, 0x0084, 2, 0x07F4, 0, 0), - MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0398, 0x0084, 3, 0x08C8, 0, 0), - MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0), - MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0398, 0x0084, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x039C, 0x0088, 2, 0x07FC, 0, 0), - MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x039C, 0x0088, 3, 0x08D4, 0, 0), - MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0), - MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x03A4, 0x0090, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x03AC, 0x0098, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_DISP_CLK__LCD_CLK = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__LCD_WR_RWN = IOMUX_PAD(0x03B0, 0x009C, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN15__LCD_ENABLE = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__LCD_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN2__LCD_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x08D8, 0, 0), - MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__LCD_RS = IOMUX_PAD(0x03B8, 0x00A4, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN3__LCD_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__LCD_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN4__LCD_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), - MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), - MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__LCD_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__LCD_DATA00 = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT1__LCD_DATA01 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__LCD_DATA10 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__LCD_DATA11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__LCD_DATA12 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__LCD_DATA13 = IOMUX_PAD(0x03D8, 0x00C4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x07BC, 0, 0), - MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__LCD_DATA14 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3, 0x07B8, 0, 0), - MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__LCD_DATA15 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x07E8, 0, 0), - MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0804, 0, 0), - MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__LCD_DATA16 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x07C0, 0, 0), - MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x08E8, 0, 0), - MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__LCD_DATA17 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x07B4, 0, 0), - MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x08EC, 0, 0), - MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__LCD_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x07C4, 0, 0), - MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x07A4, 0, 0), - MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__LCD_DATA19 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x03F0, 0x00DC, 3, 0x07B0, 0, 0), - MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x03F0, 0x00DC, 4, 0x07A0, 0, 0), - MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__LCD_DATA02 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__LCD_DATA20 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x07D8, 1, 0), - MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x07A8, 0, 0), - MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__LCD_DATA21 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x07E0, 1, 0), - MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x079C, 0, 0), - MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__LCD_DATA22 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x00EC, 2, 0x07DC, 1, 0), - MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x0400, 0x00EC, 3, 0x07AC, 0, 0), - MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__LCD_DATA23 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x07E4, 1, 0), - MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0798, 0, 0), - MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT3__LCD_DATA03 = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0408, 0x00F4, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__GPIO4_IO24 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT4__LCD_DATA04 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__GPIO4_IO25 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT5__LCD_DATA05 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0410, 0x00FC, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT6__LCD_DATA06 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x0414, 0x0100, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x0414, 0x0100, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT7__LCD_DATA07 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x0418, 0x0104, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__GPIO4_IO28 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT8__LCD_DATA08 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x041C, 0x0108, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x041C, 0x0108, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT9__LCD_DATA09 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x0420, 0x010C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x04E0, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x04E0, 0x0110, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x04E0, 0x0110, 2, 0x08B8, 0, 0), - MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x04E0, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x04E0, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__EPDC_DATA00 = IOMUX_PAD(0x04E0, 0x0110, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x04E4, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_CSI1_DATA12 = IOMUX_PAD(0x04E4, 0x0114, 2, 0x0890, 0, 0), - MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x04E4, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x04E4, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__EPDC_PWR_STAT = IOMUX_PAD(0x04E4, 0x0114, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x04E8, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_CSI1_DATA13 = IOMUX_PAD(0x04E8, 0x0118, 2, 0x0894, 0, 0), - MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x04E8, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x04E8, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04E8, 0x0118, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x04EC, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_CSI1_DATA14 = IOMUX_PAD(0x04EC, 0x011C, 2, 0x0898, 0, 0), - MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x04EC, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x04EC, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04EC, 0x011C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x04F0, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x04F0, 0x0120, 2, 0x089C, 0, 0), - MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x04F0, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x04F0, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04F0, 0x0120, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x04F4, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_CSI1_DATA16 = IOMUX_PAD(0x04F4, 0x0124, 2, 0x08A0, 0, 0), - MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x04F4, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x04F4, 0x0124, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A21__EPDC_GDCLK = IOMUX_PAD(0x04F4, 0x0124, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x04F8, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_CSI1_DATA17 = IOMUX_PAD(0x04F8, 0x0128, 2, 0x08A4, 0, 0), - MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x04F8, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x04F8, 0x0128, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A22__EPDC_GDSP = IOMUX_PAD(0x04F8, 0x0128, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x04FC, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_CSI1_DATA18 = IOMUX_PAD(0x04FC, 0x012C, 2, 0x08A8, 0, 0), - MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x04FC, 0x012C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x04FC, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x04FC, 0x012C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A23__EPDC_GDOE = IOMUX_PAD(0x04FC, 0x012C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x0500, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_CSI1_DATA19 = IOMUX_PAD(0x0500, 0x0130, 2, 0x08AC, 0, 0), - MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x0500, 0x0130, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x0500, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x0500, 0x0130, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A24__EPDC_GDRL = IOMUX_PAD(0x0500, 0x0130, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x0504, 0x0134, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x0504, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x0504, 0x0134, 2, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x0504, 0x0134, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x0504, 0x0134, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x0504, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0504, 0x0134, 6, 0x085C, 0, 0), - MX6_PAD_EIM_A25__EPDC_DATA15 = IOMUX_PAD(0x0504, 0x0134, 8, 0x0000, 0, 0), - MX6_PAD_EIM_A25__EIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x0508, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x0508, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EPDC_SDCE9 = IOMUX_PAD(0x0508, 0x0138, 8, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x050C, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x050C, 0x013C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x050C, 0x013C, 2, 0x07F4, 2, 0), - MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x050C, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__EPDC_DATA06 = IOMUX_PAD(0x050C, 0x013C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0510, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0510, 0x0140, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0510, 0x0140, 2, 0x07FC, 2, 0), - MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0510, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__EPDC_DATA08 = IOMUX_PAD(0x0510, 0x0140, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x0514, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0), - MX6_PAD_EIM_D16__IPU1_DI0_PIN05 = IOMUX_PAD(0x0514, 0x0144, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU1_CSI1_DATA18 = IOMUX_PAD(0x0514, 0x0144, 3, 0x08A8, 1, 0), - MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x0514, 0x0144, 4, 0x0864, 0, 0), - MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x0514, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0), - MX6_PAD_EIM_D16__EPDC_DATA10 = IOMUX_PAD(0x0514, 0x0144, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x0518, 0x0148, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0), - MX6_PAD_EIM_D17__IPU1_DI0_PIN06 = IOMUX_PAD(0x0518, 0x0148, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D17__IPU1_CSI1_PIXCLK = IOMUX_PAD(0x0518, 0x0148, 3, 0x08B8, 1, 0), - MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x0518, 0x0148, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x0518, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0), - MX6_PAD_EIM_D17__EPDC_VCOM0 = IOMUX_PAD(0x0518, 0x0148, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x051C, 0x014C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0), - MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x051C, 0x014C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU1_CSI1_DATA17 = IOMUX_PAD(0x051C, 0x014C, 3, 0x08A4, 1, 0), - MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x051C, 0x014C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x051C, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0), - MX6_PAD_EIM_D18__EPDC_VCOM1 = IOMUX_PAD(0x051C, 0x014C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x0520, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x0520, 0x0150, 1, 0x07E8, 1, 0), - MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x0520, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU1_CSI1_DATA16 = IOMUX_PAD(0x0520, 0x0150, 3, 0x08A0, 1, 0), - MX6_PAD_EIM_D19__UART1_CTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x0520, 0x0150, 4, 0x08F8, 0, 0), - MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x0520, 0x0150, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPDC_DATA12 = IOMUX_PAD(0x0520, 0x0150, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x0524, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x0524, 0x0154, 1, 0x0808, 0, 0), - MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x0524, 0x0154, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU1_CSI1_DATA15 = IOMUX_PAD(0x0524, 0x0154, 3, 0x089C, 1, 0), - MX6_PAD_EIM_D20__UART1_CTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x0524, 0x0154, 4, 0x08F8, 1, 0), - MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x0524, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EPIT2_OUT = IOMUX_PAD(0x0524, 0x0154, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x0528, 0x0158, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x0528, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x0528, 0x0158, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0528, 0x0158, 3, 0x088C, 0, 0), - MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x0528, 0x0158, 4, 0x0920, 0, 0), - MX6_PAD_EIM_D21__GPIO3_IO21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0), - MX6_PAD_EIM_D21__SPDIF_IN = IOMUX_PAD(0x0528, 0x0158, 7, 0x08F0, 0, 0), - MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x052C, 0x015C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x052C, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_DI0_PIN01 = IOMUX_PAD(0x052C, 0x015C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_CSI1_DATA10 = IOMUX_PAD(0x052C, 0x015C, 3, 0x0888, 0, 0), - MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x052C, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x052C, 0x015C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D22__EPDC_SDCE6 = IOMUX_PAD(0x052C, 0x015C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x0530, 0x0160, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x0530, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_CTS_B = IOMUX_PAD(0x0530, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_RTS_B = IOMUX_PAD(0x0530, 0x0160, 2, 0x0908, 0, 0), - MX6_PAD_EIM_D23__UART1_DCD_B = IOMUX_PAD(0x0530, 0x0160, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x0530, 0x0160, 4, 0x08B0, 0, 0), - MX6_PAD_EIM_D23__GPIO3_IO23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN02 = IOMUX_PAD(0x0530, 0x0160, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x0530, 0x0160, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D23__EPDC_DATA11 = IOMUX_PAD(0x0530, 0x0160, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D24__EIM_DATA24 = IOMUX_PAD(0x0534, 0x0164, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x0534, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TX_DATA = IOMUX_PAD(0x0534, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_RX_DATA = IOMUX_PAD(0x0534, 0x0164, 2, 0x090C, 0, 0), - MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x0534, 0x0164, 3, 0x07EC, 0, 0), - MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x0534, 0x0164, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D24__GPIO3_IO24 = IOMUX_PAD(0x0534, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x0534, 0x0164, 6, 0x07BC, 1, 0), - MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x0534, 0x0164, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__EPDC_SDCE7 = IOMUX_PAD(0x0534, 0x0164, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x0538, 0x0168, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x0538, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_TX_DATA = IOMUX_PAD(0x0538, 0x0168, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_RX_DATA = IOMUX_PAD(0x0538, 0x0168, 2, 0x090C, 1, 0), - MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x0538, 0x0168, 3, 0x07F0, 0, 0), - MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x0538, 0x0168, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D25__GPIO3_IO25 = IOMUX_PAD(0x0538, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x0538, 0x0168, 6, 0x07B8, 1, 0), - MX6_PAD_EIM_D25__UART1_DSR_B = IOMUX_PAD(0x0538, 0x0168, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__EPDC_SDCE8 = IOMUX_PAD(0x0538, 0x0168, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x053C, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x053C, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x053C, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI1_DATA14 = IOMUX_PAD(0x053C, 0x016C, 3, 0x0898, 1, 0), - MX6_PAD_EIM_D26__UART2_TX_DATA = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D26__UART2_RX_DATA = IOMUX_PAD(0x053C, 0x016C, 4, 0x0904, 0, 0), - MX6_PAD_EIM_D26__GPIO3_IO26 = IOMUX_PAD(0x053C, 0x016C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_SISG2 = IOMUX_PAD(0x053C, 0x016C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 = IOMUX_PAD(0x053C, 0x016C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D26__EPDC_SDOED = IOMUX_PAD(0x053C, 0x016C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x0540, 0x0170, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x0540, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x0540, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI1_DATA13 = IOMUX_PAD(0x0540, 0x0170, 3, 0x0894, 1, 0), - MX6_PAD_EIM_D27__UART2_TX_DATA = IOMUX_PAD(0x0540, 0x0170, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), - MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x0540, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_SISG3 = IOMUX_PAD(0x0540, 0x0170, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 = IOMUX_PAD(0x0540, 0x0170, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D27__EPDC_SDOE = IOMUX_PAD(0x0540, 0x0170, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x0544, 0x0174, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0), - MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x0544, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_CSI1_DATA12 = IOMUX_PAD(0x0544, 0x0174, 3, 0x0890, 1, 0), - MX6_PAD_EIM_D28__UART2_DTE_RTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x0544, 0x0174, 4, 0x0900, 0, 0), - MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x0544, 0x0174, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x0544, 0x0174, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__EPDC_PWR_CTRL3 = IOMUX_PAD(0x0544, 0x0174, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D29__EIM_DATA29 = IOMUX_PAD(0x0548, 0x0178, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x0548, 0x0178, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x0548, 0x0178, 2, 0x0808, 1, 0), - MX6_PAD_EIM_D29__UART2_CTS_B = IOMUX_PAD(0x0548, 0x0178, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D29__UART2_RTS_B = IOMUX_PAD(0x0548, 0x0178, 4, 0x0900, 1, 0), - MX6_PAD_EIM_D29__GPIO3_IO29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0548, 0x0178, 6, 0x08BC, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x0548, 0x0178, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__EPDC_PWR_WAKE = IOMUX_PAD(0x0548, 0x0178, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x054C, 0x017C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x054C, 0x017C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x054C, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x054C, 0x017C, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_CTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x054C, 0x017C, 4, 0x0908, 1, 0), - MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x054C, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x054C, 0x017C, 6, 0x0924, 0, 0), - MX6_PAD_EIM_D30__EPDC_SDOEZ = IOMUX_PAD(0x054C, 0x017C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x0550, 0x0180, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x0550, 0x0180, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x0550, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x0550, 0x0180, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_CTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x0550, 0x0180, 4, 0x0908, 2, 0), - MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x0550, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x0550, 0x0180, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D31__EPDC_SDCLK_P = IOMUX_PAD(0x0550, 0x0180, 8, 0x0000, 0, 0), - MX6_PAD_EIM_D31__EIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0554, 0x0184, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_CSI1_DATA09 = IOMUX_PAD(0x0554, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0554, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0554, 0x0184, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EPDC_SDCLK_N = IOMUX_PAD(0x0554, 0x0184, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x0558, 0x0188, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_CSI1_DATA08 = IOMUX_PAD(0x0558, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x0558, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x0558, 0x0188, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__EPDC_SDLE = IOMUX_PAD(0x0558, 0x0188, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x055C, 0x018C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x055C, 0x018C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU1_CSI1_DATA_EN = IOMUX_PAD(0x055C, 0x018C, 2, 0x08B0, 1, 0), - MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x055C, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x055C, 0x018C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EPDC_DATA01 = IOMUX_PAD(0x055C, 0x018C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0560, 0x0190, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0560, 0x0190, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_CSI1_HSYNC = IOMUX_PAD(0x0560, 0x0190, 2, 0x08B4, 0, 0), - MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0560, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0560, 0x0190, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EPDC_DATA03 = IOMUX_PAD(0x0560, 0x0190, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0564, 0x0194, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0564, 0x0194, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_CSI1_VSYNC = IOMUX_PAD(0x0564, 0x0194, 2, 0x08BC, 1, 0), - MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0564, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0564, 0x0194, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EPDC_DATA02 = IOMUX_PAD(0x0564, 0x0194, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x0568, 0x0198, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x0568, 0x0198, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x0568, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0568, 0x0198, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EPDC_DATA13 = IOMUX_PAD(0x0568, 0x0198, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x056C, 0x019C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x056C, 0x019C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x056C, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x056C, 0x019C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EPDC_DATA14 = IOMUX_PAD(0x056C, 0x019C, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0570, 0x01A0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0570, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0570, 0x01A0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0570, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0570, 0x01A0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EPDC_DATA09 = IOMUX_PAD(0x0570, 0x01A0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0574, 0x01A4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_CSI1_DATA07 = IOMUX_PAD(0x0574, 0x01A4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0574, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0574, 0x01A4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EPDC_BDR0 = IOMUX_PAD(0x0574, 0x01A4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0578, 0x01A8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_CSI1_DATA06 = IOMUX_PAD(0x0578, 0x01A8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0578, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0578, 0x01A8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EPDC_BDR1 = IOMUX_PAD(0x0578, 0x01A8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x057C, 0x01AC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_CSI1_DATA05 = IOMUX_PAD(0x057C, 0x01AC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x057C, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x057C, 0x01AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EPDC_SDCE0 = IOMUX_PAD(0x057C, 0x01AC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x0580, 0x01B0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_CSI1_DATA04 = IOMUX_PAD(0x0580, 0x01B0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x0580, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x0580, 0x01B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EPDC_SDCE1 = IOMUX_PAD(0x0580, 0x01B0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0584, 0x01B4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_CSI1_DATA03 = IOMUX_PAD(0x0584, 0x01B4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0584, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0584, 0x01B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EPDC_SDCE2 = IOMUX_PAD(0x0584, 0x01B4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0588, 0x01B8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_CSI1_DATA02 = IOMUX_PAD(0x0588, 0x01B8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0588, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0588, 0x01B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EPDC_SDCE3 = IOMUX_PAD(0x0588, 0x01B8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x058C, 0x01BC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_CSI1_DATA01 = IOMUX_PAD(0x058C, 0x01BC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x058C, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x058C, 0x01BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EPDC_SDCE4 = IOMUX_PAD(0x058C, 0x01BC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x0590, 0x01C0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_CSI1_DATA00 = IOMUX_PAD(0x0590, 0x01C0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x0590, 0x01C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EPDC_SDCE5 = IOMUX_PAD(0x0590, 0x01C0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0594, 0x01C4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_CSI1_DATA11 = IOMUX_PAD(0x0594, 0x01C4, 2, 0x088C, 1, 0), - MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0594, 0x01C4, 4, 0x07D4, 0, 0), - MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0594, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0594, 0x01C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__EPDC_PWR_COM = IOMUX_PAD(0x0594, 0x01C4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0598, 0x01C8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_CSI1_DATA10 = IOMUX_PAD(0x0598, 0x01C8, 2, 0x0888, 1, 0), - MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0598, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0598, 0x01C8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__EPDC_SDSHR = IOMUX_PAD(0x0598, 0x01C8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x059C, 0x01CC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x059C, 0x01CC, 1, 0x07E4, 2, 0), - MX6_PAD_EIM_EB2__IPU1_CSI1_DATA19 = IOMUX_PAD(0x059C, 0x01CC, 3, 0x08AC, 1, 0), - MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x059C, 0x01CC, 4, 0x0860, 0, 0), - MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x059C, 0x01CC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0), - MX6_PAD_EIM_EB2__SRC_BOOT_CFG30 = IOMUX_PAD(0x059C, 0x01CC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__EPDC_DATA05 = IOMUX_PAD(0x059C, 0x01CC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EIM_EB3_B = IOMUX_PAD(0x05A0, 0x01D0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x05A0, 0x01D0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_CTS_B = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_RTS_B = IOMUX_PAD(0x05A0, 0x01D0, 2, 0x0908, 3, 0), - MX6_PAD_EIM_EB3__UART1_RI_B = IOMUX_PAD(0x05A0, 0x01D0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_CSI1_HSYNC = IOMUX_PAD(0x05A0, 0x01D0, 4, 0x08B4, 1, 0), - MX6_PAD_EIM_EB3__GPIO2_IO31 = IOMUX_PAD(0x05A0, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_DI1_PIN03 = IOMUX_PAD(0x05A0, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__SRC_BOOT_CFG31 = IOMUX_PAD(0x05A0, 0x01D0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EPDC_SDCE0 = IOMUX_PAD(0x05A0, 0x01D0, 8, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EIM_ACLK_FREERUN = IOMUX_PAD(0x05A0, 0x01D0, 9, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__EIM_LBA_B = IOMUX_PAD(0x05A4, 0x01D4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x05A4, 0x01D4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x05A4, 0x01D4, 2, 0x0804, 1, 0), - MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x05A4, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x05A4, 0x01D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__EPDC_DATA04 = IOMUX_PAD(0x05A4, 0x01D4, 8, 0x0000, 0, 0), - MX6_PAD_EIM_OE__EIM_OE_B = IOMUX_PAD(0x05A8, 0x01D8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x05A8, 0x01D8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x05A8, 0x01D8, 2, 0x07F8, 2, 0), - MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x05A8, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_OE__EPDC_PWR_IRQ = IOMUX_PAD(0x05A8, 0x01D8, 8, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x05AC, 0x01DC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x05AC, 0x01DC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x05AC, 0x01DC, 2, 0x0800, 2, 0), - MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x05AC, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x05AC, 0x01DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EPDC_DATA07 = IOMUX_PAD(0x05AC, 0x01DC, 8, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x05B0, 0x01E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x05B0, 0x01E0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x05B0, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x05B0, 0x01E0, 7, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x05B4, 0x01E4, 1, 0x0828, 0, 0), - MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x05B4, 0x01E4, 2, 0x0840, 0, 0), - MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x05B4, 0x01E4, 3, 0x08F4, 0, 0), - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x05B4, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x05B8, 0x01E8, 0, 0x08E0, 0, 0), - MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x05B8, 0x01E8, 2, 0x0858, 0, 0), - MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x05B8, 0x01E8, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x05B8, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0), - MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x05BC, 0x01EC, 2, 0x083C, 0, 0), - MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x05BC, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x05BC, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x05BC, 0x01EC, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x05C0, 0x01F0, 2, 0x082C, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x05C0, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x05C0, 0x01F0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x05C4, 0x01F4, 0, 0x0790, 0, 0), - MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x05C4, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x05C4, 0x01F4, 2, 0x0834, 0, 0), - MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x05C4, 0x01F4, 3, 0x08F0, 1, 0), - MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT= IOMUX_PAD(0x05C4, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x05C4, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0818, 0, 0), - MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x0838, 0, 0), - MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x08E4, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x081C, 0, 0), - MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x0830, 0, 0), - MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x05D0, 0x0200, 2, 0x0850, 0, 0), - MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__I2C4_SCL = IOMUX_PAD(0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x05D4, 0x0204, 2, 0x0854, 0, 0), - MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x05D8, 0x0208, 0, 0x08DC, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x05D8, 0x0208, 2, 0x084C, 0, 0), - MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__I2C4_SDA = IOMUX_PAD(0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0), - MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0000, 0, 0), - MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05DC, 0x020C, 2, 0x08C0, 1, 0), - MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0794, 0, 0), - MX6_PAD_GPIO_0__EPIT1_OUT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_0__GPIO1_IO00 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05DC, 0x020C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_1__ESAI_RX_CLK = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_1__KEY_ROW5 = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0), - MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0), - MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0850, 1, 0), - MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x05E4, 0x0214, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x05E4, 0x0214, 2, 0x080C, 0, 0), - MX6_PAD_GPIO_16__SD1_LCTL = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_16__SPDIF_IN = IOMUX_PAD(0x05E4, 0x0214, 4, 0x08F0, 2, 0), - MX6_PAD_GPIO_16__GPIO7_IO11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0), - MX6_PAD_GPIO_16__JTAG_DE_B = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_17__ESAI_TX0 = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0844, 0, 0), - MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_17__CCM_PMIC_READY = IOMUX_PAD(0x05E8, 0x0218, 2, 0x07D4, 1, 0), - MX6_PAD_GPIO_17__SDMA_EXT_EVENT0 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x08E8, 1, 0), - MX6_PAD_GPIO_17__SPDIF_OUT = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x05EC, 0x021C, 0, 0x0848, 0, 0), - MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0814, 0, 0), - MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x08EC, 1, 0), - MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0794, 1, 0), - MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x08C0, 2, 0), - MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x05F0, 0x0220, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x05F0, 0x0220, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_19__CCM_CLKO1 = IOMUX_PAD(0x05F0, 0x0220, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_19__GPIO4_IO05 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x05F4, 0x0224, 0, 0x0830, 1, 0), - MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08D0, 1, 0), - MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x05F4, 0x0224, 7, 0x08E0, 1, 0), - MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05F8, 0x0228, 0, 0x0834, 1, 0), - MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0), - MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_3__GPIO1_IO03 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05F8, 0x0228, 6, 0x0924, 1, 0), - MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05F8, 0x0228, 7, 0x08DC, 1, 0), - MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0838, 1, 0), - MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x05FC, 0x022C, 2, 0x08C8, 1, 0), - MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_4__SD2_CD_B = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_5__ESAI_TX2_RX3 = IOMUX_PAD(0x0600, 0x0230, 0, 0x084C, 1, 0), - MX6_PAD_GPIO_5__KEY_ROW7 = IOMUX_PAD(0x0600, 0x0230, 2, 0x08D4, 1, 0), - MX6_PAD_GPIO_5__CCM_CLKO1 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_5__GPIO1_IO05 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0), - MX6_PAD_GPIO_5__ARM_EVENTI = IOMUX_PAD(0x0600, 0x0230, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0604, 0x0234, 0, 0x0840, 1, 0), - MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0), - MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0604, 0x0234, 7, 0x08E4, 1, 0), - MX6_PAD_GPIO_7__ESAI_TX4_RX1 = IOMUX_PAD(0x0608, 0x0238, 0, 0x0854, 1, 0), - MX6_PAD_GPIO_7__EPIT1_OUT = IOMUX_PAD(0x0608, 0x0238, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_7__FLEXCAN1_TX = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TX_DATA = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_RX_DATA = IOMUX_PAD(0x0608, 0x0238, 4, 0x0904, 2, 0), - MX6_PAD_GPIO_7__GPIO1_IO07 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_7__SPDIF_LOCK = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_7__USB_OTG_HOST_MODE = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_7__I2C4_SCL = IOMUX_PAD(0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0), - MX6_PAD_GPIO_8__ESAI_TX5_RX0 = IOMUX_PAD(0x060C, 0x023C, 0, 0x0858, 1, 0), - MX6_PAD_GPIO_8__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_8__EPIT2_OUT = IOMUX_PAD(0x060C, 0x023C, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_8__FLEXCAN1_RX = IOMUX_PAD(0x060C, 0x023C, 3, 0x07C8, 0, 0), - MX6_PAD_GPIO_8__UART2_TX_DATA = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_8__UART2_RX_DATA = IOMUX_PAD(0x060C, 0x023C, 4, 0x0904, 3, 0), - MX6_PAD_GPIO_8__GPIO1_IO08 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_8__SPDIF_SR_CLK = IOMUX_PAD(0x060C, 0x023C, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_8__I2C4_SDA = IOMUX_PAD(0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0), - MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x0610, 0x0240, 0, 0x082C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x0610, 0x0240, 2, 0x08C4, 1, 0), - MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x0610, 0x0240, 6, 0x092C, 1, 0), - MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x062C, 0x0244, 0, 0x07D8, 3, 0), - MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x062C, 0x0244, 1, 0x0824, 0, 0), - MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x062C, 0x0244, 2, 0x07C0, 1, 0), - MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x062C, 0x0244, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x062C, 0x0244, 4, 0x0914, 2, 0), - MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x062C, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x062C, 0x0244, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x0630, 0x0248, 0, 0x07DC, 3, 0), - MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x0630, 0x0248, 1, 0x0810, 1, 0), - MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x0630, 0x0248, 2, 0x07C4, 1, 0), - MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x0630, 0x0248, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x0630, 0x0248, 4, 0x091C, 2, 0), - MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x0630, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x0634, 0x024C, 0, 0x07E8, 2, 0), - MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x0634, 0x024C, 1, 0x0820, 0, 0), - MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x0634, 0x024C, 2, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x0634, 0x024C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x0634, 0x024C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x0634, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x0634, 0x024C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x0638, 0x0250, 0, 0x07F0, 1, 0), - MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x0638, 0x0250, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x0638, 0x0250, 2, 0x0860, 1, 0), - MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x0638, 0x0250, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0), - MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x0638, 0x0250, 6, 0x08F0, 3, 0), - MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x063C, 0x0254, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x063C, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x063C, 0x0254, 2, 0x0920, 1, 0), - MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x063C, 0x0254, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x063C, 0x0254, 4, 0x0918, 2, 0), - MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x063C, 0x0254, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0640, 0x0258, 0, 0x07E0, 3, 0), - MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x0640, 0x0258, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2, 0x07B4, 1, 0), - MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x0640, 0x0258, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_TX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x0640, 0x0258, 4, 0x0914, 3, 0), - MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x0640, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x0640, 0x0258, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x025C, 0, 0x07E4, 3, 0), - MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x0644, 0x025C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2, 0x07B0, 1, 0), - MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x0644, 0x025C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_TX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x0644, 0x025C, 4, 0x091C, 3, 0), - MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x0644, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x0648, 0x0260, 0, 0x07EC, 1, 0), - MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x0648, 0x0260, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x0648, 0x0260, 2, 0x07C8, 1, 0), - MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x0648, 0x0260, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x0648, 0x0260, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0648, 0x0260, 6, 0x085C, 1, 0), - MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1, 0x0794, 2, 0), - MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x064C, 0x0264, 2, 0x0864, 1, 0), - MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x064C, 0x0264, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0), - MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x0650, 0x0268, 0, 0x07CC, 0, 0), - MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x0650, 0x0268, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x0650, 0x0268, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x0650, 0x0268, 4, 0x0918, 3, 0), - MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x0650, 0x0268, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x0654, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x0654, 0x026C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x0654, 0x026C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__NAND_CLE = IOMUX_PAD(0x0658, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__GPIO6_IO07 = IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x065C, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x065C, 0x0274, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x0660, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x0660, 0x0278, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x0664, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x0664, 0x027C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x0664, 0x027C, 2, 0x0844, 1, 0), - MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x0664, 0x027C, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x0664, 0x027C, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x0668, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x0668, 0x0280, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x0668, 0x0280, 2, 0x0848, 1, 0), - MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x0668, 0x0280, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__I2C4_SDA = IOMUX_PAD(0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0), - MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x066C, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__SD1_DATA4 = IOMUX_PAD(0x066C, 0x0284, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPIO2_IO00 = IOMUX_PAD(0x066C, 0x0284, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__NAND_DATA01 = IOMUX_PAD(0x0670, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__SD1_DATA5 = IOMUX_PAD(0x0670, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPIO2_IO01 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__NAND_DATA02 = IOMUX_PAD(0x0674, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__SD1_DATA6 = IOMUX_PAD(0x0674, 0x028C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPIO2_IO02 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__NAND_DATA03 = IOMUX_PAD(0x0678, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__SD1_DATA7 = IOMUX_PAD(0x0678, 0x0290, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPIO2_IO03 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__NAND_DATA04 = IOMUX_PAD(0x067C, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__SD2_DATA4 = IOMUX_PAD(0x067C, 0x0294, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPIO2_IO04 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__NAND_DATA05 = IOMUX_PAD(0x0680, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__SD2_DATA5 = IOMUX_PAD(0x0680, 0x0298, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPIO2_IO05 = IOMUX_PAD(0x0680, 0x0298, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__NAND_DATA06 = IOMUX_PAD(0x0684, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__SD2_DATA6 = IOMUX_PAD(0x0684, 0x029C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPIO2_IO06 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0688, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0688, 0x02A0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0688, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x068C, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x068C, 0x02A4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__I2C4_SCL = IOMUX_PAD(0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0), - MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0), - MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0), - MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0), - MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x06A0, 0x02B8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0), - MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0), - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), - MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0), - MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x080C, 1, 0), - MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x08F4, 1, 0), - MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0), - MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO1_IO20 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__PWM4_OUT = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO1_IO18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__SD1_DATA0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPT_CAPTURE1 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPIO1_IO16 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__PWM3_OUT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPT_CAPTURE2 = IOMUX_PAD(0x06D0, 0x02E8, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPIO1_IO17 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__SD1_DATA2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPT_COMPARE2 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__PWM2_OUT = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_B = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPIO1_IO19 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_RESET_B_DEB = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__SD1_DATA3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPT_COMPARE3 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__PWM1_OUT = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_B = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPIO1_IO21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x06DC, 0x02F4, 0, 0x0930, 1, 0), - MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x08C0, 3, 0), - MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x06DC, 0x02F4, 3, 0x07A4, 1, 0), - MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x08CC, 2, 0), - MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x06E0, 0x02F8, 3, 0x07A0, 1, 0), - MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0798, 1, 0), - MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x08D4, 2, 0), - MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x06E8, 0x0300, 3, 0x07AC, 1, 0), - MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x08C8, 2, 0), - MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x06EC, 0x0304, 3, 0x079C, 1, 0), - MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x08D0, 2, 0), - MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x08C4, 2, 0), - MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x06F0, 0x0308, 3, 0x07A8, 1, 0), - MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0), - MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_RTS_B = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0900, 2, 0), - MX6_PAD_SD3_CLK__FLEXCAN1_RX = IOMUX_PAD(0x06F4, 0x030C, 2, 0x07C8, 2, 0), - MX6_PAD_SD3_CLK__GPIO7_IO03 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_CTS_B = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0900, 3, 0), - MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__GPIO7_IO02 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_CTS_B = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06FC, 0x0314, 1, 0x08F8, 2, 0), - MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__GPIO7_IO04 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__SD3_DATA1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_CTS_B = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_RTS_B = IOMUX_PAD(0x0700, 0x0318, 1, 0x08F8, 3, 0), - MX6_PAD_SD3_DAT1__FLEXCAN2_RX = IOMUX_PAD(0x0700, 0x0318, 2, 0x07CC, 1, 0), - MX6_PAD_SD3_DAT1__GPIO7_IO05 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__SD3_DATA2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__GPIO7_IO06 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_CTS_B = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x0708, 0x0320, 1, 0x0908, 4, 0), - MX6_PAD_SD3_DAT3__GPIO7_IO07 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_TX_DATA = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x070C, 0x0324, 1, 0x0904, 4, 0), - MX6_PAD_SD3_DAT4__GPIO7_IO01 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0710, 0x0328, 1, 0x0904, 5, 0), - MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_TX_DATA = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0), - MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0718, 0x0330, 1, 0x08FC, 3, 0), - MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), - MX6_PAD_SD3_RST__SD3_RESET = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_CTS_B = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_RTS_B = IOMUX_PAD(0x071C, 0x0334, 1, 0x0908, 5, 0), - MX6_PAD_SD3_RST__GPIO7_IO08 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0), - MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x090C, 2, 0), - MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__NAND_RE_B = IOMUX_PAD(0x0724, 0x033C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TX_DATA = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_RX_DATA = IOMUX_PAD(0x0724, 0x033C, 2, 0x090C, 3, 0), - MX6_PAD_SD4_CMD__GPIO7_IO09 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__SD4_DATA0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__NAND_DQS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__GPIO2_IO08 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__SD4_DATA1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__PWM3_OUT = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__GPIO2_IO09 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__SD4_DATA2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__PWM4_OUT = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__GPIO2_IO10 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__SD4_DATA3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__GPIO2_IO11 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0738, 0x0350, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_TX_DATA = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0738, 0x0350, 2, 0x0904, 6, 0), - MX6_PAD_SD4_DAT4__GPIO2_IO12 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__SD4_DATA5 = IOMUX_PAD(0x073C, 0x0354, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_CTS_B = IOMUX_PAD(0x073C, 0x0354, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_RTS_B = IOMUX_PAD(0x073C, 0x0354, 2, 0x0900, 4, 0), - MX6_PAD_SD4_DAT5__GPIO2_IO13 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x0740, 0x0358, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_CTS_B = IOMUX_PAD(0x0740, 0x0358, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x0740, 0x0358, 2, 0x0900, 5, 0), - MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0744, 0x035C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0744, 0x035C, 2, 0x0904, 7, 0), - MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), -}; #endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index f01f2e0..ad31c33 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -9,1032 +9,1028 @@ #ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__ #define __ASM_ARCH_MX6_MX6Q_PINS_H__ -#include - -enum { - MX6_PAD_SD2_DAT1__SD2_DATA1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0), - MX6_PAD_SD2_DAT1__EIM_CS2_B = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0), - MX6_PAD_SD2_DAT1__KEY_COL7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0), - MX6_PAD_SD2_DAT1__GPIO1_IO14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__SD2_DATA2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0), - MX6_PAD_SD2_DAT2__EIM_CS3_B = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0), - MX6_PAD_SD2_DAT2__KEY_ROW6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0), - MX6_PAD_SD2_DAT2__GPIO1_IO13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__SD2_DATA0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0), - MX6_PAD_SD2_DAT0__AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0), - MX6_PAD_SD2_DAT0__KEY_ROW7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0), - MX6_PAD_SD2_DAT0__GPIO1_IO15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__DCIC2_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__USB_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__SPDIF_EXT_CLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0), - MX6_PAD_RGMII_TXC__GPIO6_IO19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__HSI_TX_READY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD0__GPIO6_IO20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__HSI_RX_FLAG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD1__GPIO6_IO21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__HSI_RX_DATA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD2__GPIO6_IO22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__HSI_RX_WAKE = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TD3__GPIO6_IO23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__USB_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0), - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__HSI_RX_READY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD0__RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0), - MX6_PAD_RGMII_RD0__GPIO6_IO25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__USB_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__GPIO6_IO26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_TX_CTL__ENET_REF_CLK = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0), - MX6_PAD_RGMII_RD1__HSI_TX_FLAG = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD1__RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0), - MX6_PAD_RGMII_RD1__GPIO6_IO27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__HSI_TX_DATA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD2__RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0), - MX6_PAD_RGMII_RD2__GPIO6_IO28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__HSI_TX_WAKE = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RD3__RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0), - MX6_PAD_RGMII_RD3__GPIO6_IO29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__USB_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0), - MX6_PAD_RGMII_RXC__RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0), - MX6_PAD_RGMII_RXC__GPIO6_IO30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A25__EIM_ADDR25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A25__GPIO5_IO02 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0), - MX6_PAD_EIM_EB2__EIM_EB2_B = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0), - MX6_PAD_EIM_EB2__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0), - MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0), - MX6_PAD_EIM_EB2__GPIO2_IO30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0), - MX6_PAD_EIM_EB2__SRC_BOOT_CFG30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D16__EIM_DATA16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0), - MX6_PAD_EIM_D16__IPU1_DI0_PIN05 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D16__IPU2_CSI1_DATA18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0), - MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0), - MX6_PAD_EIM_D16__GPIO3_IO16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0), - MX6_PAD_EIM_D17__EIM_DATA17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0), - MX6_PAD_EIM_D17__IPU1_DI0_PIN06 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0), - MX6_PAD_EIM_D17__DCIC1_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D17__GPIO3_IO17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0), - MX6_PAD_EIM_D18__EIM_DATA18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0), - MX6_PAD_EIM_D18__IPU1_DI0_PIN07 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D18__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0), - MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D18__GPIO3_IO18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0), - MX6_PAD_EIM_D19__EIM_DATA19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0), - MX6_PAD_EIM_D19__IPU1_DI0_PIN08 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D19__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0), - MX6_PAD_EIM_D19__UART1_CTS_B = IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D19__UART1_RTS_B = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0), - MX6_PAD_EIM_D19__GPIO3_IO19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D19__EPIT1_OUT = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EIM_DATA20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0), - MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0), - MX6_PAD_EIM_D20__UART1_CTS_B = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D20__UART1_RTS_B = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0), - MX6_PAD_EIM_D20__GPIO3_IO20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D20__EPIT2_OUT = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D21__EIM_DATA21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D21__IPU2_CSI1_DATA11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0), - MX6_PAD_EIM_D21__USB_OTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0), - MX6_PAD_EIM_D21__GPIO3_IO21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0), - MX6_PAD_EIM_D21__SPDIF_IN = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0), - MX6_PAD_EIM_D22__EIM_DATA22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU1_DI0_PIN01 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D22__IPU2_CSI1_DATA10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0), - MX6_PAD_EIM_D22__USB_OTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D22__GPIO3_IO22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D22__SPDIF_OUT = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D23__EIM_DATA23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_CTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D23__UART3_RTS_B = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0), - MX6_PAD_EIM_D23__UART1_DCD_B = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0), - MX6_PAD_EIM_D23__GPIO3_IO23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN02 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__EIM_EB3_B = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_CTS_B = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__UART3_RTS_B = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0), - MX6_PAD_EIM_EB3__UART1_RI_B = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0), - MX6_PAD_EIM_EB3__GPIO2_IO31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__IPU1_DI1_PIN03 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_EB3__SRC_BOOT_CFG31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D24__EIM_DATA24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_TX_DATA = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D24__UART3_RX_DATA = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0), - MX6_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0), - MX6_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D24__GPIO3_IO24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D24__AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0), - MX6_PAD_EIM_D24__UART1_DTR_B = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D25__EIM_DATA25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_TX_DATA = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D25__UART3_RX_DATA = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0), - MX6_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0), - MX6_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D25__GPIO3_IO25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D25__AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0), - MX6_PAD_EIM_D25__UART1_DSR_B = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D26__EIM_DATA26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_CSI0_DATA01 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0), - MX6_PAD_EIM_D26__UART2_TX_DATA = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D26__UART2_RX_DATA = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0), - MX6_PAD_EIM_D26__GPIO3_IO26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_SISG2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D27__EIM_DATA27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_CSI0_DATA00 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU2_CSI1_DATA13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0), - MX6_PAD_EIM_D27__UART2_TX_DATA = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D27__UART2_RX_DATA = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0), - MX6_PAD_EIM_D27__GPIO3_IO27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_SISG3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D28__EIM_DATA28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0), - MX6_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU2_CSI1_DATA12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0), - MX6_PAD_EIM_D28__UART2_DTE_CTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0), - MX6_PAD_EIM_D28__UART2_DTE_RTS_B = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D28__GPIO3_IO28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0), - MX6_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D29__EIM_DATA29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0), - MX6_PAD_EIM_D29__UART2_CTS_B = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D29__UART2_RTS_B = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0), - MX6_PAD_EIM_D29__GPIO3_IO29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0), - MX6_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_D30__EIM_DATA30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D30__IPU1_CSI0_DATA03 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_CTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D30__UART3_RTS_B = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0), - MX6_PAD_EIM_D30__GPIO3_IO30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D30__USB_H1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0), - MX6_PAD_EIM_D31__EIM_DATA31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0), - MX6_PAD_EIM_D31__IPU1_CSI0_DATA02 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_CTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0), - MX6_PAD_EIM_D31__UART3_RTS_B = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0), - MX6_PAD_EIM_D31__GPIO3_IO31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_D31__USB_H1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0), - MX6_PAD_EIM_A24__EIM_ADDR24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU2_CSI1_DATA19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0), - MX6_PAD_EIM_A24__IPU2_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A24__IPU1_SISG2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A24__GPIO5_IO04 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A24__SRC_BOOT_CFG24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A23__EIM_ADDR23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU2_CSI1_DATA18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0), - MX6_PAD_EIM_A23__IPU2_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0), - MX6_PAD_EIM_A23__IPU1_SISG3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0), - MX6_PAD_EIM_A23__GPIO6_IO06 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A23__SRC_BOOT_CFG23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A22__EIM_ADDR22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A22__IPU2_CSI1_DATA17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0), - MX6_PAD_EIM_A22__GPIO2_IO16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A22__SRC_BOOT_CFG22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A21__EIM_ADDR21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A21__IPU2_CSI1_DATA16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0), - MX6_PAD_EIM_A21__GPIO2_IO17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A21__SRC_BOOT_CFG21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A20__EIM_ADDR20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A20__IPU2_CSI1_DATA15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0), - MX6_PAD_EIM_A20__GPIO2_IO18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A20__SRC_BOOT_CFG20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A19__EIM_ADDR19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A19__IPU2_CSI1_DATA14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0), - MX6_PAD_EIM_A19__GPIO2_IO19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A19__SRC_BOOT_CFG19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A18__EIM_ADDR18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A18__IPU2_CSI1_DATA13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0), - MX6_PAD_EIM_A18__GPIO2_IO20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A17__EIM_ADDR17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A17__IPU2_CSI1_DATA12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0), - MX6_PAD_EIM_A17__GPIO2_IO21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A17__SRC_BOOT_CFG17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0), - MX6_PAD_EIM_A16__EIM_ADDR16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0), - MX6_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0), - MX6_PAD_EIM_A16__GPIO2_IO22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0), - MX6_PAD_EIM_A16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__EIM_CS0_B = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__IPU1_DI1_PIN05 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0), - MX6_PAD_EIM_CS0__GPIO2_IO23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__EIM_CS1_B = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__IPU1_DI1_PIN06 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0), - MX6_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0), - MX6_PAD_EIM_CS1__GPIO2_IO24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0), - MX6_PAD_EIM_OE__EIM_OE_B = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0), - MX6_PAD_EIM_OE__IPU1_DI1_PIN07 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0), - MX6_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0), - MX6_PAD_EIM_OE__GPIO2_IO25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__EIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0), - MX6_PAD_EIM_RW__IPU1_DI1_PIN08 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0), - MX6_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0), - MX6_PAD_EIM_RW__GPIO2_IO26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0), - MX6_PAD_EIM_RW__SRC_BOOT_CFG29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__EIM_LBA_B = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0), - MX6_PAD_EIM_LBA__GPIO2_IO27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0), - MX6_PAD_EIM_LBA__SRC_BOOT_CFG26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__EIM_EB0_B = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__IPU2_CSI1_DATA11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0), - MX6_PAD_EIM_EB0__CCM_PMIC_READY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0), - MX6_PAD_EIM_EB0__GPIO2_IO28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB0__SRC_BOOT_CFG27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__EIM_EB1_B = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__IPU2_CSI1_DATA10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0), - MX6_PAD_EIM_EB1__GPIO2_IO29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0), - MX6_PAD_EIM_EB1__SRC_BOOT_CFG28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__EIM_AD00 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__IPU2_CSI1_DATA09 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__GPIO3_IO00 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA0__SRC_BOOT_CFG00 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__EIM_AD01 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__IPU2_CSI1_DATA08 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__GPIO3_IO01 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA1__SRC_BOOT_CFG01 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__EIM_AD02 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__IPU2_CSI1_DATA07 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__GPIO3_IO02 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA2__SRC_BOOT_CFG02 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__EIM_AD03 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__IPU2_CSI1_DATA06 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__GPIO3_IO03 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA3__SRC_BOOT_CFG03 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__EIM_AD04 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__IPU2_CSI1_DATA05 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__GPIO3_IO04 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA4__SRC_BOOT_CFG04 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__EIM_AD05 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__IPU2_CSI1_DATA04 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__GPIO3_IO05 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA5__SRC_BOOT_CFG05 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__EIM_AD06 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__IPU2_CSI1_DATA03 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__GPIO3_IO06 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA6__SRC_BOOT_CFG06 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__EIM_AD07 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__IPU2_CSI1_DATA02 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__GPIO3_IO07 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA7__SRC_BOOT_CFG07 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__EIM_AD08 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__IPU2_CSI1_DATA01 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__GPIO3_IO08 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA8__SRC_BOOT_CFG08 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__EIM_AD09 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__IPU2_CSI1_DATA00 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__GPIO3_IO09 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA9__SRC_BOOT_CFG09 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__EIM_AD10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0), - MX6_PAD_EIM_DA10__GPIO3_IO10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__EIM_AD11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0), - MX6_PAD_EIM_DA11__GPIO3_IO11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__EIM_AD12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0), - MX6_PAD_EIM_DA12__GPIO3_IO12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__EIM_AD13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__GPIO3_IO13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__EIM_AD14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__GPIO3_IO14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__EIM_AD15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN01 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__IPU1_DI1_PIN04 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__GPIO3_IO15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0), - MX6_PAD_EIM_DA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_WAIT_B = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__EIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__GPIO5_IO00 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0), - MX6_PAD_EIM_WAIT__SRC_BOOT_CFG25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__EIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), - MX6_PAD_EIM_BCLK__GPIO6_IO31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_DISP_CLK__GPIO4_IO16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN15__GPIO4_IO17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN2__GPIO4_IO18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN3__GPIO4_IO19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU2_DI0_PIN04 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__SD1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0), - MX6_PAD_DI0_PIN4__GPIO4_IO20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT0__GPIO4_IO21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT1__GPIO4_IO22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT2__GPIO4_IO23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT3__GPIO4_IO24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT4__GPIO4_IO25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT5__GPIO4_IO26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT6__GPIO4_IO27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT7__GPIO4_IO28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__PWM1_OUT = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__WDOG1_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT8__GPIO4_IO29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__PWM2_OUT = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__WDOG2_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT9__GPIO4_IO30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT10__GPIO4_IO31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT11__GPIO5_IO05 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT12__GPIO5_IO06 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT13__AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0), - MX6_PAD_DISP0_DAT13__GPIO5_IO07 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT14__AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0), - MX6_PAD_DISP0_DAT14__GPIO5_IO08 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0), - MX6_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0), - MX6_PAD_DISP0_DAT15__GPIO5_IO09 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0), - MX6_PAD_DISP0_DAT16__AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0), - MX6_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0), - MX6_PAD_DISP0_DAT16__GPIO5_IO10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0), - MX6_PAD_DISP0_DAT17__AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0), - MX6_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0), - MX6_PAD_DISP0_DAT17__GPIO5_IO11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0), - MX6_PAD_DISP0_DAT18__AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0), - MX6_PAD_DISP0_DAT18__AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0), - MX6_PAD_DISP0_DAT18__GPIO5_IO12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT18__EIM_CS2_B = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0), - MX6_PAD_DISP0_DAT19__AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0), - MX6_PAD_DISP0_DAT19__AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0), - MX6_PAD_DISP0_DAT19__GPIO5_IO13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT19__EIM_CS3_B = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0), - MX6_PAD_DISP0_DAT20__AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0), - MX6_PAD_DISP0_DAT20__GPIO5_IO14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0), - MX6_PAD_DISP0_DAT21__AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0), - MX6_PAD_DISP0_DAT21__GPIO5_IO15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0), - MX6_PAD_DISP0_DAT22__AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0), - MX6_PAD_DISP0_DAT22__GPIO5_IO16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), - MX6_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0), - MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0), - MX6_PAD_DISP0_DAT23__AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0), - MX6_PAD_DISP0_DAT23__GPIO5_IO17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0), - MX6_PAD_ENET_MDIO__ESAI_RX_CLK = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0), - MX6_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__GPIO1_IO22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDIO__SPDIF_LOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__ESAI_RX_FS = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0), - MX6_PAD_ENET_REF_CLK__GPIO1_IO23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_REF_CLK__SPDIF_SR_CLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__USB_OTG_ID = IOMUX_PAD(0x04EC, 0x01D8, 0, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__ESAI_RX_HF_CLK = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0), - MX6_PAD_ENET_RX_ER__SPDIF_IN = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0), - MX6_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT= IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RX_ER__GPIO1_IO24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0), - MX6_PAD_ENET_CRS_DV__ESAI_TX_CLK = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0), - MX6_PAD_ENET_CRS_DV__SPDIF_EXT_CLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0), - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__MLB_SIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0), - MX6_PAD_ENET_RXD1__ESAI_TX_FS = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0), - MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0), - MX6_PAD_ENET_RXD1__GPIO1_IO26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0), - MX6_PAD_ENET_RXD0__ESAI_TX_HF_CLK = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0), - MX6_PAD_ENET_RXD0__SPDIF_OUT = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0), - MX6_PAD_ENET_RXD0__GPIO1_IO27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TX_EN__ESAI_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0), - MX6_PAD_ENET_TX_EN__GPIO1_IO28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__MLB_CLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__ESAI_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0), - MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0), - MX6_PAD_ENET_TXD1__GPIO1_IO29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0), - MX6_PAD_ENET_TXD0__ESAI_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0), - MX6_PAD_ENET_TXD0__GPIO1_IO30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__MLB_DATA = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0), - MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__ESAI_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0), - MX6_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0), - MX6_PAD_ENET_MDC__GPIO1_IO31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0), - MX6_PAD_KEY_COL0__ENET_RX_DATA3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0), - MX6_PAD_KEY_COL0__AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0), - MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_TX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__UART4_RX_DATA = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0), - MX6_PAD_KEY_COL0__GPIO4_IO06 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL0__DCIC1_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0), - MX6_PAD_KEY_ROW0__ENET_TX_DATA3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0), - MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_TX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__UART4_RX_DATA = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0), - MX6_PAD_KEY_ROW0__GPIO4_IO07 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW0__DCIC2_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0), - MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0), - MX6_PAD_KEY_COL1__AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0), - MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_TX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__UART5_RX_DATA = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0), - MX6_PAD_KEY_COL1__GPIO4_IO08 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL1__SD1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0), - MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0), - MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_TX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__UART5_RX_DATA = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0), - MX6_PAD_KEY_ROW1__GPIO4_IO09 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW1__SD2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0), - MX6_PAD_KEY_COL2__ENET_RX_DATA2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0), - MX6_PAD_KEY_COL2__FLEXCAN1_TX = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__GPIO4_IO10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0), - MX6_PAD_KEY_ROW2__ENET_TX_DATA2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__FLEXCAN1_RX = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0), - MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__SD2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__GPIO4_IO11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0), - MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0), - MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0), - MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0), - MX6_PAD_KEY_COL3__GPIO4_IO12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0), - MX6_PAD_KEY_COL3__SPDIF_IN = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0), - MX6_PAD_KEY_ROW3__ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0), - MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0), - MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0), - MX6_PAD_KEY_ROW3__GPIO4_IO13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__FLEXCAN2_TX = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__IPU1_SISG4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__USB_OTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0), - MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_CTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__UART5_RTS_B = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0), - MX6_PAD_KEY_COL4__GPIO4_IO14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__FLEXCAN2_RX = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0), - MX6_PAD_KEY_ROW4__IPU1_SISG5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__USB_OTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_CTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 0, 0), - MX6_PAD_KEY_ROW4__UART5_RTS_B = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0), - MX6_PAD_KEY_ROW4__GPIO4_IO15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__CCM_CLKO1 = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0), - MX6_PAD_GPIO_0__KEY_COL5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0), - MX6_PAD_GPIO_0__ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0), - MX6_PAD_GPIO_0__EPIT1_OUT = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_0__GPIO1_IO00 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_0__USB_H1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_0__SNVS_VIO_5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_1__ESAI_RX_CLK = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0), - MX6_PAD_GPIO_1__WDOG2_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_1__KEY_ROW5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0), - MX6_PAD_GPIO_1__USB_OTG_ID = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_1__PWM2_OUT = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_1__GPIO1_IO01 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_1__SD1_CD_B = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_9__ESAI_RX_FS = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0), - MX6_PAD_GPIO_9__WDOG1_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_9__KEY_COL6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0), - MX6_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_9__PWM1_OUT = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_9__GPIO1_IO09 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_9__SD1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0), - MX6_PAD_GPIO_3__ESAI_RX_HF_CLK = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0), - MX6_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0), - MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_3__GPIO1_IO03 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_3__USB_H1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0), - MX6_PAD_GPIO_3__MLB_CLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0), - MX6_PAD_GPIO_6__ESAI_TX_CLK = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0), - MX6_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0), - MX6_PAD_GPIO_6__GPIO1_IO06 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_6__SD2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_6__MLB_SIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0), - MX6_PAD_GPIO_2__ESAI_TX_FS = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0), - MX6_PAD_GPIO_2__KEY_ROW6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0), - MX6_PAD_GPIO_2__GPIO1_IO02 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_2__SD2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_2__MLB_DATA = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0), - MX6_PAD_GPIO_4__ESAI_TX_HF_CLK = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0), - MX6_PAD_GPIO_4__KEY_COL7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0), - MX6_PAD_GPIO_4__GPIO1_IO04 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_4__SD2_CD_B = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_5__ESAI_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0), - MX6_PAD_GPIO_5__KEY_ROW7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0), - MX6_PAD_GPIO_5__CCM_CLKO1 = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_5__GPIO1_IO05 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0), - MX6_PAD_GPIO_5__ARM_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_7__ESAI_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0), - MX6_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_7__EPIT1_OUT = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_7__FLEXCAN1_TX = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_TX_DATA = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_7__UART2_RX_DATA = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0), - MX6_PAD_GPIO_7__GPIO1_IO07 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_7__SPDIF_LOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_7__USB_OTG_HOST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_8__ESAI_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0), - MX6_PAD_GPIO_8__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_8__EPIT2_OUT = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_8__FLEXCAN1_RX = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0), - MX6_PAD_GPIO_8__UART2_TX_DATA = IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_8__UART2_RX_DATA = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0), - MX6_PAD_GPIO_8__GPIO1_IO08 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_8__SPDIF_SR_CLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ESAI_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0), - MX6_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_16__ENET_REF_CLK = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0), - MX6_PAD_GPIO_16__SD1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_16__SPDIF_IN = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0), - MX6_PAD_GPIO_16__GPIO7_IO11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0), - MX6_PAD_GPIO_16__JTAG_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0), - MX6_PAD_GPIO_17__ESAI_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0), - MX6_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_17__CCM_PMIC_READY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0), - MX6_PAD_GPIO_17__SDMA_EXT_EVENT0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0), - MX6_PAD_GPIO_17__SPDIF_OUT = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_17__GPIO7_IO12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__ESAI_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0), - MX6_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0), - MX6_PAD_GPIO_18__SD3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0), - MX6_PAD_GPIO_18__ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0), - MX6_PAD_GPIO_18__GPIO7_IO13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_18__SNVS_VIO_5_CTL = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0), - MX6_PAD_GPIO_19__KEY_COL5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0), - MX6_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0), - MX6_PAD_GPIO_19__SPDIF_OUT = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0), - MX6_PAD_GPIO_19__CCM_CLKO1 = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0), - MX6_PAD_GPIO_19__GPIO4_IO05 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0), - MX6_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_PIXCLK__ARM_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__CCM_CLKO1 = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__GPIO5_IO19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_MCLK__ARM_TRACE_CTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__EIM_DATA00 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DATA_EN__ARM_TRACE_CLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__EIM_DATA01 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__GPIO5_IO21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_VSYNC__ARM_TRACE00 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__EIM_DATA02 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0), - MX6_PAD_CSI0_DAT4__KEY_COL5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0), - MX6_PAD_CSI0_DAT4__AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__GPIO5_IO22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT4__ARM_TRACE01 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__EIM_DATA03 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0), - MX6_PAD_CSI0_DAT5__KEY_ROW5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0), - MX6_PAD_CSI0_DAT5__AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__GPIO5_IO23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT5__ARM_TRACE02 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__EIM_DATA04 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0), - MX6_PAD_CSI0_DAT6__KEY_COL6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0), - MX6_PAD_CSI0_DAT6__AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__GPIO5_IO24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT6__ARM_TRACE03 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__EIM_DATA05 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0), - MX6_PAD_CSI0_DAT7__KEY_ROW6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0), - MX6_PAD_CSI0_DAT7__AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__GPIO5_IO25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT7__ARM_TRACE04 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__EIM_DATA06 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0), - MX6_PAD_CSI0_DAT8__KEY_COL7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0), - MX6_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0), - MX6_PAD_CSI0_DAT8__GPIO5_IO26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT8__ARM_TRACE05 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__EIM_DATA07 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0), - MX6_PAD_CSI0_DAT9__KEY_ROW7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0), - MX6_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0), - MX6_PAD_CSI0_DAT9__GPIO5_IO27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT9__ARM_TRACE06 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0), - MX6_PAD_CSI0_DAT10__UART1_TX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__UART1_RX_DATA = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0), - MX6_PAD_CSI0_DAT10__GPIO5_IO28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT10__ARM_TRACE07 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0), - MX6_PAD_CSI0_DAT11__UART1_TX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0), - MX6_PAD_CSI0_DAT11__GPIO5_IO29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT11__ARM_TRACE08 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__EIM_DATA08 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_TX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__UART4_RX_DATA = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0), - MX6_PAD_CSI0_DAT12__GPIO5_IO30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT12__ARM_TRACE09 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__EIM_DATA09 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_TX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__UART4_RX_DATA = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0), - MX6_PAD_CSI0_DAT13__GPIO5_IO31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT13__ARM_TRACE10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__EIM_DATA10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_TX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__UART5_RX_DATA = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0), - MX6_PAD_CSI0_DAT14__GPIO6_IO00 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT14__ARM_TRACE11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__EIM_DATA11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_TX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__UART5_RX_DATA = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0), - MX6_PAD_CSI0_DAT15__GPIO6_IO01 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT15__ARM_TRACE12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__EIM_DATA12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_CTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__UART4_RTS_B = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0), - MX6_PAD_CSI0_DAT16__GPIO6_IO02 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT16__ARM_TRACE13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__EIM_DATA13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_CTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__UART4_RTS_B = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0), - MX6_PAD_CSI0_DAT17__GPIO6_IO03 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT17__ARM_TRACE14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__EIM_DATA14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_CTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__UART5_RTS_B = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0), - MX6_PAD_CSI0_DAT18__GPIO6_IO04 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT18__ARM_TRACE15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__EIM_DATA15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_CTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x0000, 0, 0), - MX6_PAD_CSI0_DAT19__UART5_RTS_B = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0), - MX6_PAD_CSI0_DAT19__GPIO6_IO05 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__SD3_DATA7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_TX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT7__UART1_RX_DATA = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0), - MX6_PAD_SD3_DAT7__GPIO6_IO17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__SD3_DATA6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_TX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT6__UART1_RX_DATA = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0), - MX6_PAD_SD3_DAT6__GPIO6_IO18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__SD3_DATA5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_TX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT5__UART2_RX_DATA = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0), - MX6_PAD_SD3_DAT5__GPIO7_IO00 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__SD3_DATA4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_TX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT4__UART2_RX_DATA = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0), - MX6_PAD_SD3_DAT4__GPIO7_IO01 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_CTS_B = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__UART2_RTS_B = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0), - MX6_PAD_SD3_CMD__FLEXCAN1_TX = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0), - MX6_PAD_SD3_CMD__GPIO7_IO02 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_CTS_B = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0), - MX6_PAD_SD3_CLK__UART2_RTS_B = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0), - MX6_PAD_SD3_CLK__FLEXCAN1_RX = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0), - MX6_PAD_SD3_CLK__GPIO7_IO03 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__SD3_DATA0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_CTS_B = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__UART1_RTS_B = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0), - MX6_PAD_SD3_DAT0__FLEXCAN2_TX = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0), - MX6_PAD_SD3_DAT0__GPIO7_IO04 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__SD3_DATA1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_CTS_B = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT1__UART1_RTS_B = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0), - MX6_PAD_SD3_DAT1__FLEXCAN2_RX = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0), - MX6_PAD_SD3_DAT1__GPIO7_IO05 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__SD3_DATA2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT2__GPIO7_IO06 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__SD3_DATA3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_CTS_B = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0), - MX6_PAD_SD3_DAT3__UART3_RTS_B = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0), - MX6_PAD_SD3_DAT3__GPIO7_IO07 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0), - MX6_PAD_SD3_RST__SD3_RESET = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_CTS_B = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0), - MX6_PAD_SD3_RST__UART3_RTS_B = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0), - MX6_PAD_SD3_RST__GPIO7_IO08 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__NAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__IPU2_SISG4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CLE__GPIO6_IO07 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__NAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__SD4_RESET = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_ALE__GPIO6_IO08 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__NAND_WP_B = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__IPU2_SISG5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_WP_B__GPIO6_IO09 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__NAND_READY_B = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__IPU2_DI0_PIN01 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_RB0__GPIO6_IO10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__NAND_CE0_B = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS0__GPIO6_IO11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__NAND_CE1_B = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__SD3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0), - MX6_PAD_NANDF_CS1__GPIO6_IO14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__NAND_CE2_B = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU1_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__ESAI_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0), - MX6_PAD_NANDF_CS2__EIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__GPIO6_IO15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS2__IPU2_SISG0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__NAND_CE3_B = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU1_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__ESAI_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0), - MX6_PAD_NANDF_CS3__EIM_ADDR26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__GPIO6_IO16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_CS3__IPU2_SISG1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__SD4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__NAND_RE_B = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_TX_DATA = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CMD__UART3_RX_DATA = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0), - MX6_PAD_SD4_CMD__GPIO7_IO09 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__SD4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__NAND_WE_B = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_TX_DATA = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0), - MX6_PAD_SD4_CLK__UART3_RX_DATA = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0), - MX6_PAD_SD4_CLK__GPIO7_IO10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__NAND_DATA00 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__SD1_DATA4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D0__GPIO2_IO00 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__NAND_DATA01 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__SD1_DATA5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D1__GPIO2_IO01 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__NAND_DATA02 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__SD1_DATA6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D2__GPIO2_IO02 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__NAND_DATA03 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__SD1_DATA7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D3__GPIO2_IO03 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__NAND_DATA04 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__SD2_DATA4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D4__GPIO2_IO04 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__NAND_DATA05 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__SD2_DATA5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D5__GPIO2_IO05 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__NAND_DATA06 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__SD2_DATA6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D6__GPIO2_IO06 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__NAND_DATA07 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__SD2_DATA7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0), - MX6_PAD_NANDF_D7__GPIO2_IO07 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__SD4_DATA0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__NAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT0__GPIO2_IO08 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__SD4_DATA1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__PWM3_OUT = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT1__GPIO2_IO09 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__SD4_DATA2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__PWM4_OUT = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT2__GPIO2_IO10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__SD4_DATA3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT3__GPIO2_IO11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__SD4_DATA4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_TX_DATA = IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT4__UART2_RX_DATA = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0), - MX6_PAD_SD4_DAT4__GPIO2_IO12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__SD4_DATA5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_CTS_B = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT5__UART2_RTS_B = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0), - MX6_PAD_SD4_DAT5__GPIO2_IO13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__SD4_DATA6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_CTS_B = IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT6__UART2_RTS_B = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0), - MX6_PAD_SD4_DAT6__GPIO2_IO14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__SD4_DATA7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_TX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0), - MX6_PAD_SD4_DAT7__UART2_RX_DATA = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0), - MX6_PAD_SD4_DAT7__GPIO2_IO15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__SD1_DATA1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0), - MX6_PAD_SD1_DAT1__PWM3_OUT = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPT_CAPTURE2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT1__GPIO1_IO17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__SD1_DATA0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0), - MX6_PAD_SD1_DAT0__GPT_CAPTURE1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT0__GPIO1_IO16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__SD1_DATA3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPT_COMPARE3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__PWM1_OUT = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__GPIO1_IO21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT3__WDOG2_RESET_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0), - MX6_PAD_SD1_CMD__PWM4_OUT = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPT_COMPARE1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CMD__GPIO1_IO18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__SD1_DATA2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0), - MX6_PAD_SD1_DAT2__GPT_COMPARE2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__PWM2_OUT = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__GPIO1_IO19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0), - MX6_PAD_SD1_DAT2__WDOG1_RESET_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0), - MX6_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0), - MX6_PAD_SD1_CLK__GPIO1_IO20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0), - MX6_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0), - MX6_PAD_SD2_CLK__KEY_COL5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0), - MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0), - MX6_PAD_SD2_CLK__GPIO1_IO10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0), - MX6_PAD_SD2_CMD__KEY_ROW5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0), - MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0), - MX6_PAD_SD2_CMD__GPIO1_IO11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__SD2_DATA3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__KEY_COL6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0), - MX6_PAD_SD2_DAT3__AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0), - MX6_PAD_SD2_DAT3__GPIO1_IO12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0), -}; +MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x0360, 0x004C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__ECSPI5_SS0, 0x0360, 0x004C, 1, 0x0834, 0, 0) +MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x0360, 0x004C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x0360, 0x004C, 3, 0x07C8, 0, 0) +MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x0360, 0x004C, 4, 0x08F0, 0, 0) +MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x0360, 0x004C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x0364, 0x0050, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__ECSPI5_SS1, 0x0364, 0x0050, 1, 0x0838, 0, 0) +MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x0364, 0x0050, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x0364, 0x0050, 3, 0x07B8, 0, 0) +MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x0364, 0x0050, 4, 0x08F8, 0, 0) +MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x0364, 0x0050, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x0368, 0x0054, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__ECSPI5_MISO, 0x0368, 0x0054, 1, 0x082C, 0, 0) +MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x0368, 0x0054, 3, 0x07B4, 0, 0) +MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x0368, 0x0054, 4, 0x08FC, 0, 0) +MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x0368, 0x0054, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x0368, 0x0054, 6, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x036C, 0x0058, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x036C, 0x0058, 2, 0x0918, 0, 0) +MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x036C, 0x0058, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x036C, 0x0058, 7, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x0370, 0x005C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x0370, 0x005C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x0374, 0x0060, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x0374, 0x0060, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x0378, 0x0064, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x0378, 0x0064, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x037C, 0x0068, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x037C, 0x0068, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x0380, 0x006C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0, 0) +MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x0380, 0x006C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0384, 0x0070, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0, 0) +MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0384, 0x0070, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x0388, 0x0074, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x0388, 0x0074, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x0388, 0x0074, 7, 0x083C, 0, 0) +MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x038C, 0x0078, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0, 0) +MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x038C, 0x0078, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x0390, 0x007C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0, 0) +MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x0390, 0x007C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x0394, 0x0080, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0, 0) +MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x0394, 0x0080, 5, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x0398, 0x0084, 0, 0x0000, 0, 0) +MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0, 0) +MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x0398, 0x0084, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x039C, 0x0088, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x039C, 0x0088, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x039C, 0x0088, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x039C, 0x0088, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x039C, 0x0088, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x039C, 0x0088, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x039C, 0x0088, 6, 0x088C, 0, 0) +MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x03A0, 0x008C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x03A0, 0x008C, 1, 0x0800, 0, 0) +MX6_PAD_DECL(EIM_EB2__IPU2_CSI1_DATA19, 0x03A0, 0x008C, 3, 0x08D4, 0, 0) +MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x03A0, 0x008C, 4, 0x0890, 0, 0) +MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x03A0, 0x008C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x03A0, 0x008C, 22, 0x08A0, 0, 0) +MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x03A0, 0x008C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x03A4, 0x0090, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x03A4, 0x0090, 1, 0x07F4, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x03A4, 0x0090, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__IPU2_CSI1_DATA18, 0x03A4, 0x0090, 3, 0x08D0, 0, 0) +MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x03A4, 0x0090, 4, 0x0894, 0, 0) +MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x03A4, 0x0090, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x03A4, 0x0090, 22, 0x08A4, 0, 0) +MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x03A8, 0x0094, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x03A8, 0x0094, 1, 0x07F8, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x03A8, 0x0094, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__IPU2_CSI1_PIXCLK, 0x03A8, 0x0094, 3, 0x08E0, 0, 0) +MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x03A8, 0x0094, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x03A8, 0x0094, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x03A8, 0x0094, 22, 0x08A8, 0, 0) +MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x03AC, 0x0098, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x03AC, 0x0098, 1, 0x07FC, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x03AC, 0x0098, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU2_CSI1_DATA17, 0x03AC, 0x0098, 3, 0x08CC, 0, 0) +MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x03AC, 0x0098, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x03AC, 0x0098, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x03AC, 0x0098, 22, 0x08AC, 0, 0) +MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x03B0, 0x009C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x03B0, 0x009C, 1, 0x0804, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x03B0, 0x009C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__IPU2_CSI1_DATA16, 0x03B0, 0x009C, 3, 0x08C8, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x03B0, 0x009C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x03B0, 0x009C, 4, 0x091C, 0, 0) +MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x03B0, 0x009C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x03B0, 0x009C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x03B4, 0x00A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x03B4, 0x00A0, 1, 0x0824, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__IPU2_CSI1_DATA15, 0x03B4, 0x00A0, 3, 0x08C4, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x03B4, 0x00A0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x03B4, 0x00A0, 4, 0x091C, 1, 0) +MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x03B4, 0x00A0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x03B8, 0x00A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x03B8, 0x00A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__IPU2_CSI1_DATA11, 0x03B8, 0x00A4, 3, 0x08B4, 0, 0) +MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x03B8, 0x00A4, 4, 0x0944, 0, 0) +MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x03B8, 0x00A4, 22, 0x0898, 0, 0) +MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x03B8, 0x00A4, 7, 0x0914, 0, 0) +MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x03BC, 0x00A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__IPU2_CSI1_DATA10, 0x03BC, 0x00A8, 3, 0x08B0, 0, 0) +MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x03BC, 0x00A8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x03BC, 0x00A8, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x03C0, 0x00AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x03C0, 0x00AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x03C0, 0x00AC, 2, 0x092C, 0, 0) +MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x03C0, 0x00AC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU2_CSI1_DATA_EN, 0x03C0, 0x00AC, 4, 0x08D8, 0, 0) +MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x03C0, 0x00AC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x03C0, 0x00AC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x03C4, 0x00B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x03C4, 0x00B0, 2, 0x092C, 1, 0) +MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x03C4, 0x00B0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU2_CSI1_HSYNC, 0x03C4, 0x00B0, 4, 0x08DC, 0, 0) +MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x03C4, 0x00B0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x03C4, 0x00B0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x03C8, 0x00B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x03C8, 0x00B4, 2, 0x0930, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x03C8, 0x00B4, 3, 0x0808, 0, 0) +MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x03C8, 0x00B4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x03C8, 0x00B4, 6, 0x07D8, 0, 0) +MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x03C8, 0x00B4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x03CC, 0x00B8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x03CC, 0x00B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x03CC, 0x00B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x03CC, 0x00B8, 2, 0x0930, 1, 0) +MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x03CC, 0x00B8, 3, 0x080C, 0, 0) +MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x03CC, 0x00B8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x03CC, 0x00B8, 6, 0x07D4, 0, 0) +MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x03CC, 0x00B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x03D0, 0x00BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x03D0, 0x00BC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU2_CSI1_DATA14, 0x03D0, 0x00BC, 3, 0x08C0, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x03D0, 0x00BC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x03D0, 0x00BC, 4, 0x0928, 0, 0) +MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x03D0, 0x00BC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x03D0, 0x00BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x03D4, 0x00C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x03D4, 0x00C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU2_CSI1_DATA13, 0x03D4, 0x00C0, 3, 0x08BC, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x03D4, 0x00C0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x03D4, 0x00C0, 4, 0x0928, 1, 0) +MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x03D4, 0x00C0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x03D4, 0x00C0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x03D8, 0x00C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x03D8, 0x00C4, 17, 0x089C, 0, 0) +MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x03D8, 0x00C4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU2_CSI1_DATA12, 0x03D8, 0x00C4, 3, 0x08B8, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x03D8, 0x00C4, 4, 0x0924, 0, 0) +MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x03D8, 0x00C4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x03D8, 0x00C4, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x03D8, 0x00C4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x03DC, 0x00C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x03DC, 0x00C8, 2, 0x0824, 1, 0) +MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x03DC, 0x00C8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x03DC, 0x00C8, 4, 0x0924, 1, 0) +MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU2_CSI1_VSYNC, 0x03DC, 0x00C8, 6, 0x08E4, 0, 0) +MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x03DC, 0x00C8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x03E0, 0x00CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x03E0, 0x00CC, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x03E0, 0x00CC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x03E0, 0x00CC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x03E0, 0x00CC, 4, 0x092C, 2, 0) +MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x03E0, 0x00CC, 6, 0x0948, 0, 0) +MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x03E4, 0x00D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x03E4, 0x00D0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x03E4, 0x00D0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x03E4, 0x00D0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x03E4, 0x00D0, 4, 0x092C, 3, 0) +MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x03E4, 0x00D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x03E8, 0x00D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU2_CSI1_DATA19, 0x03E8, 0x00D4, 2, 0x08D4, 1, 0) +MX6_PAD_DECL(EIM_A24__IPU2_SISG2, 0x03E8, 0x00D4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x03E8, 0x00D4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x03E8, 0x00D4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x03EC, 0x00D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU2_CSI1_DATA18, 0x03EC, 0x00D8, 2, 0x08D0, 1, 0) +MX6_PAD_DECL(EIM_A23__IPU2_SISG3, 0x03EC, 0x00D8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x03EC, 0x00D8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x03F0, 0x00DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__IPU2_CSI1_DATA17, 0x03F0, 0x00DC, 2, 0x08CC, 1, 0) +MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x03F4, 0x00E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__IPU2_CSI1_DATA16, 0x03F4, 0x00E0, 2, 0x08C8, 1, 0) +MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x03F4, 0x00E0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x03F8, 0x00E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__IPU2_CSI1_DATA15, 0x03F8, 0x00E4, 2, 0x08C4, 1, 0) +MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x03F8, 0x00E4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x03FC, 0x00E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__IPU2_CSI1_DATA14, 0x03FC, 0x00E8, 2, 0x08C0, 1, 0) +MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x03FC, 0x00E8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x0400, 0x00EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x0400, 0x00EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__IPU2_CSI1_DATA13, 0x0400, 0x00EC, 2, 0x08BC, 1, 0) +MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x0400, 0x00EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x0400, 0x00EC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x0404, 0x00F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x0404, 0x00F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__IPU2_CSI1_DATA12, 0x0404, 0x00F0, 2, 0x08B8, 1, 0) +MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x0404, 0x00F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x0404, 0x00F0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x0408, 0x00F4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x0408, 0x00F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__IPU2_CSI1_PIXCLK, 0x0408, 0x00F4, 2, 0x08E0, 1, 0) +MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x0408, 0x00F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x0408, 0x00F4, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x040C, 0x00F8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x040C, 0x00F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x040C, 0x00F8, 2, 0x0810, 0, 0) +MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x040C, 0x00F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0410, 0x00FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0410, 0x00FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0410, 0x00FC, 2, 0x0818, 0, 0) +MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0410, 0x00FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x0414, 0x0100, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x0414, 0x0100, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x0414, 0x0100, 2, 0x0814, 0, 0) +MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x0414, 0x0100, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x0418, 0x0104, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x0418, 0x0104, 2, 0x081C, 0, 0) +MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x0418, 0x0104, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x0418, 0x0104, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x041C, 0x0108, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x041C, 0x0108, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x041C, 0x0108, 2, 0x0820, 0, 0) +MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x041C, 0x0108, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x041C, 0x0108, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0420, 0x010C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0420, 0x010C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__IPU2_CSI1_DATA11, 0x0420, 0x010C, 2, 0x08B4, 1, 0) +MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0420, 0x010C, 4, 0x07F0, 0, 0) +MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0420, 0x010C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0420, 0x010C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0424, 0x0110, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0424, 0x0110, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__IPU2_CSI1_DATA10, 0x0424, 0x0110, 2, 0x08B0, 1, 0) +MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0424, 0x0110, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0424, 0x0110, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0428, 0x0114, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0428, 0x0114, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__IPU2_CSI1_DATA09, 0x0428, 0x0114, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0428, 0x0114, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0428, 0x0114, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x042C, 0x0118, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x042C, 0x0118, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__IPU2_CSI1_DATA08, 0x042C, 0x0118, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x042C, 0x0118, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x042C, 0x0118, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0430, 0x011C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0430, 0x011C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__IPU2_CSI1_DATA07, 0x0430, 0x011C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0430, 0x011C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0430, 0x011C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0434, 0x0120, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0434, 0x0120, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__IPU2_CSI1_DATA06, 0x0434, 0x0120, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0434, 0x0120, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0434, 0x0120, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x0438, 0x0124, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x0438, 0x0124, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__IPU2_CSI1_DATA05, 0x0438, 0x0124, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x0438, 0x0124, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x0438, 0x0124, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x043C, 0x0128, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x043C, 0x0128, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__IPU2_CSI1_DATA04, 0x043C, 0x0128, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x043C, 0x0128, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x043C, 0x0128, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0440, 0x012C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0440, 0x012C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__IPU2_CSI1_DATA03, 0x0440, 0x012C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0440, 0x012C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0440, 0x012C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0444, 0x0130, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0444, 0x0130, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__IPU2_CSI1_DATA02, 0x0444, 0x0130, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0444, 0x0130, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0444, 0x0130, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x0448, 0x0134, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x0448, 0x0134, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__IPU2_CSI1_DATA01, 0x0448, 0x0134, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x0448, 0x0134, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x0448, 0x0134, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x044C, 0x0138, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x044C, 0x0138, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__IPU2_CSI1_DATA00, 0x044C, 0x0138, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x044C, 0x0138, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x044C, 0x0138, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x0450, 0x013C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x0450, 0x013C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__IPU2_CSI1_DATA_EN, 0x0450, 0x013C, 2, 0x08D8, 1, 0) +MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x0450, 0x013C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x0450, 0x013C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0454, 0x0140, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0454, 0x0140, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__IPU2_CSI1_HSYNC, 0x0454, 0x0140, 2, 0x08DC, 1, 0) +MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0454, 0x0140, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0454, 0x0140, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0458, 0x0144, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0458, 0x0144, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__IPU2_CSI1_VSYNC, 0x0458, 0x0144, 2, 0x08E4, 1, 0) +MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0458, 0x0144, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0458, 0x0144, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x045C, 0x0148, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x045C, 0x0148, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x045C, 0x0148, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x045C, 0x0148, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x0460, 0x014C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x0460, 0x014C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x0460, 0x014C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x0460, 0x014C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0464, 0x0150, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0464, 0x0150, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0464, 0x0150, 2, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0464, 0x0150, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0464, 0x0150, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x0468, 0x0154, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x0468, 0x0154, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x0468, 0x0154, 5, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x0468, 0x0154, 7, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x046C, 0x0158, 1, 0x0000, 0, 0) +MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x046C, 0x0158, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_DISP_CLK__IPU2_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x0470, 0x015C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN15__IPU2_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x0474, 0x0160, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x0474, 0x0160, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN2__IPU2_DI0_PIN02, 0x0478, 0x0164, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x0478, 0x0164, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x0478, 0x0164, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DI0_PIN3__IPU2_DI0_PIN03, 0x047C, 0x0168, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x047C, 0x0168, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x047C, 0x0168, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x0480, 0x016C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__IPU2_DI0_PIN04, 0x0480, 0x016C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x0480, 0x016C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x0480, 0x016C, 3, 0x094C, 0, 0) +MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT0__IPU2_DISP0_DATA00, 0x0484, 0x0170, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x0484, 0x0170, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x0484, 0x0170, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT1__IPU2_DISP0_DATA01, 0x0488, 0x0174, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x0488, 0x0174, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x0488, 0x0174, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT2__IPU2_DISP0_DATA02, 0x048C, 0x0178, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x048C, 0x0178, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x048C, 0x0178, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT3__IPU2_DISP0_DATA03, 0x0490, 0x017C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0490, 0x017C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0490, 0x017C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT4__IPU2_DISP0_DATA04, 0x0494, 0x0180, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x0494, 0x0180, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x0494, 0x0180, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT5__IPU2_DISP0_DATA05, 0x0498, 0x0184, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0498, 0x0184, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0498, 0x0184, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0498, 0x0184, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT6__IPU2_DISP0_DATA06, 0x049C, 0x0188, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x049C, 0x0188, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x049C, 0x0188, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x049C, 0x0188, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT7__IPU2_DISP0_DATA07, 0x04A0, 0x018C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x04A0, 0x018C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x04A0, 0x018C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT8__IPU2_DISP0_DATA08, 0x04A4, 0x0190, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x04A4, 0x0190, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x04A4, 0x0190, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x04A4, 0x0190, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT9__IPU2_DISP0_DATA09, 0x04A8, 0x0194, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x04A8, 0x0194, 2, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x04A8, 0x0194, 3, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x04A8, 0x0194, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT10__IPU2_DISP0_DATA10, 0x04AC, 0x0198, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x04AC, 0x0198, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT11__IPU2_DISP0_DATA11, 0x04B0, 0x019C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x04B0, 0x019C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT12__IPU2_DISP0_DATA12, 0x04B4, 0x01A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x04B4, 0x01A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT13__IPU2_DISP0_DATA13, 0x04B8, 0x01A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x04B8, 0x01A4, 3, 0x07D8, 1, 0) +MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x04B8, 0x01A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT14__IPU2_DISP0_DATA14, 0x04BC, 0x01A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x04BC, 0x01A8, 3, 0x07D4, 1, 0) +MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x04BC, 0x01A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT15__IPU2_DISP0_DATA15, 0x04C0, 0x01AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x04C0, 0x01AC, 2, 0x0804, 1, 0) +MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x04C0, 0x01AC, 3, 0x0820, 1, 0) +MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x04C0, 0x01AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT16__IPU2_DISP0_DATA16, 0x04C4, 0x01B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x04C4, 0x01B0, 2, 0x0818, 1, 0) +MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x04C4, 0x01B0, 3, 0x07DC, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x04C4, 0x01B0, 4, 0x090C, 0, 0) +MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x04C4, 0x01B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT17__IPU2_DISP0_DATA17, 0x04C8, 0x01B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x04C8, 0x01B4, 2, 0x0814, 1, 0) +MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x04C8, 0x01B4, 3, 0x07D0, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x04C8, 0x01B4, 4, 0x0910, 0, 0) +MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x04C8, 0x01B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT18__IPU2_DISP0_DATA18, 0x04CC, 0x01B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x04CC, 0x01B8, 2, 0x081C, 1, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x04CC, 0x01B8, 3, 0x07E0, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x04CC, 0x01B8, 4, 0x07C0, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x04CC, 0x01B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x04CC, 0x01B8, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT19__IPU2_DISP0_DATA19, 0x04D0, 0x01BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x04D0, 0x01BC, 2, 0x0810, 1, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x04D0, 0x01BC, 3, 0x07CC, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x04D0, 0x01BC, 4, 0x07BC, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x04D0, 0x01BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x04D0, 0x01BC, 7, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT20__IPU2_DISP0_DATA20, 0x04D4, 0x01C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x04D4, 0x01C0, 2, 0x07F4, 1, 0) +MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x04D4, 0x01C0, 3, 0x07C4, 0, 0) +MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x04D4, 0x01C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT21__IPU2_DISP0_DATA21, 0x04D8, 0x01C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x04D8, 0x01C4, 2, 0x07FC, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x04D8, 0x01C4, 3, 0x07B8, 1, 0) +MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x04D8, 0x01C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT22__IPU2_DISP0_DATA22, 0x04DC, 0x01C8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x04DC, 0x01C8, 2, 0x07F8, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x04DC, 0x01C8, 3, 0x07C8, 1, 0) +MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x04DC, 0x01C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) +MX6_PAD_DECL(DISP0_DAT23__IPU2_DISP0_DATA23, 0x04E0, 0x01CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x04E0, 0x01CC, 2, 0x0800, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x04E0, 0x01CC, 3, 0x07B4, 1, 0) +MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x04E0, 0x01CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x04E4, 0x01D0, 2, 0x086C, 0, 0) +MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x04E4, 0x01D0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x04E4, 0x01D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x04E4, 0x01D0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x04E8, 0x01D4, 2, 0x085C, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x04E8, 0x01D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x04EC, 0x01D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x04EC, 0x01D8, 2, 0x0864, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x04EC, 0x01D8, 3, 0x0914, 1, 0) +MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x04EC, 0x01D8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x04EC, 0x01D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x04F0, 0x01DC, 1, 0x0858, 1, 0) +MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x04F0, 0x01DC, 2, 0x0870, 0, 0) +MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x04F0, 0x01DC, 3, 0x0918, 1, 0) +MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x04F0, 0x01DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x04F4, 0x01E0, 0, 0x0908, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x04F4, 0x01E0, 1, 0x084C, 1, 0) +MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x04F4, 0x01E0, 2, 0x0860, 0, 0) +MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x04F4, 0x01E0, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x04F4, 0x01E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x04F8, 0x01E4, 1, 0x0848, 1, 0) +MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x04F8, 0x01E4, 2, 0x0868, 0, 0) +MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x04F8, 0x01E4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x04F8, 0x01E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x04FC, 0x01E8, 2, 0x0880, 0, 0) +MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x04FC, 0x01E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x0500, 0x01EC, 0, 0x0900, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x0500, 0x01EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x0500, 0x01EC, 2, 0x087C, 0, 0) +MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x0500, 0x01EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x0500, 0x01EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x0504, 0x01F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x0504, 0x01F0, 2, 0x0884, 0, 0) +MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x0504, 0x01F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x0508, 0x01F4, 0, 0x0904, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x0508, 0x01F4, 2, 0x0888, 0, 0) +MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x0508, 0x01F4, 4, 0x0000, 0, 0) +MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x0508, 0x01F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x05C8, 0x01F8, 0, 0x07F4, 2, 0) +MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x05C8, 0x01F8, 1, 0x0854, 1, 0) +MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x05C8, 0x01F8, 2, 0x07DC, 1, 0) +MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x05C8, 0x01F8, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x05C8, 0x01F8, 4, 0x0938, 0, 0) +MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x05C8, 0x01F8, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x05CC, 0x01FC, 0, 0x07FC, 2, 0) +MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x05CC, 0x01FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x05CC, 0x01FC, 2, 0x07D0, 1, 0) +MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x05CC, 0x01FC, 4, 0x0938, 1, 0) +MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x05CC, 0x01FC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x05D0, 0x0200, 0, 0x07F8, 2, 0) +MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x05D0, 0x0200, 1, 0x0840, 1, 0) +MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x05D0, 0x0200, 2, 0x07E0, 1, 0) +MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x05D0, 0x0200, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x05D0, 0x0200, 4, 0x0940, 0, 0) +MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x05D0, 0x0200, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x05D0, 0x0200, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x05D4, 0x0204, 0, 0x0800, 2, 0) +MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x05D4, 0x0204, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x05D4, 0x0204, 2, 0x07CC, 1, 0) +MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x05D4, 0x0204, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x05D4, 0x0204, 4, 0x0940, 1, 0) +MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x05D4, 0x0204, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x05D4, 0x0204, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x05D8, 0x0208, 0, 0x0804, 2, 0) +MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x05D8, 0x0208, 1, 0x0850, 1, 0) +MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x05D8, 0x0208, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x05D8, 0x0208, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x05D8, 0x0208, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x05D8, 0x0208, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x05DC, 0x020C, 0, 0x0808, 1, 0) +MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x05DC, 0x020C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x05DC, 0x020C, 2, 0x07E4, 0, 0) +MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x05DC, 0x020C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x05DC, 0x020C, 6, 0x088C, 1, 0) +MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x05E0, 0x0210, 0, 0x080C, 1, 0) +MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x05E0, 0x0210, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x05E0, 0x0210, 2, 0x0890, 1, 0) +MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x05E0, 0x0210, 20, 0x08A0, 1, 0) +MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x05E0, 0x0210, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x05E0, 0x0210, 6, 0x0914, 2, 0) +MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x05E4, 0x0214, 1, 0x07B0, 0, 0) +MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x05E4, 0x0214, 2, 0x0894, 1, 0) +MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x05E4, 0x0214, 20, 0x08A4, 1, 0) +MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x05E4, 0x0214, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x05E4, 0x0214, 6, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x05E8, 0x0218, 0, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x05E8, 0x0218, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x05E8, 0x0218, 2, 0x0944, 1, 0) +MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x05E8, 0x0218, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x05E8, 0x0218, 4, 0x093C, 0, 0) +MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x05E8, 0x0218, 5, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x05EC, 0x021C, 0, 0x07E8, 0, 0) +MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x05EC, 0x021C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x05EC, 0x021C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x05EC, 0x021C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x05EC, 0x021C, 4, 0x093C, 1, 0) +MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x05EC, 0x021C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05F0, 0x0220, 0, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05F0, 0x0220, 2, 0x08E8, 0, 0) +MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05F0, 0x0220, 3, 0x07B0, 1, 0) +MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05F0, 0x0220, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05F0, 0x0220, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05F0, 0x0220, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05F0, 0x0220, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05F4, 0x0224, 0, 0x086C, 1, 0) +MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05F4, 0x0224, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05F4, 0x0224, 2, 0x08F4, 0, 0) +MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05F4, 0x0224, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05F4, 0x0224, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05F4, 0x0224, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05F4, 0x0224, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x05F8, 0x0228, 0, 0x085C, 1, 0) +MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x05F8, 0x0228, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x05F8, 0x0228, 2, 0x08EC, 0, 0) +MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x05F8, 0x0228, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x05F8, 0x0228, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x05F8, 0x0228, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_9__SD1_WP, 0x05F8, 0x0228, 6, 0x094C, 1, 0) +MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05FC, 0x022C, 0, 0x0864, 1, 0) +MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05FC, 0x022C, 18, 0x08A8, 1, 0) +MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05FC, 0x022C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05FC, 0x022C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05FC, 0x022C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05FC, 0x022C, 6, 0x0948, 1, 0) +MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05FC, 0x022C, 7, 0x0900, 1, 0) +MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0600, 0x0230, 0, 0x0870, 1, 0) +MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0600, 0x0230, 18, 0x08AC, 1, 0) +MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0600, 0x0230, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0600, 0x0230, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0600, 0x0230, 7, 0x0908, 1, 0) +MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x0604, 0x0234, 0, 0x0860, 1, 0) +MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x0604, 0x0234, 2, 0x08F8, 1, 0) +MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x0604, 0x0234, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__SD2_WP, 0x0604, 0x0234, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x0604, 0x0234, 7, 0x0904, 1, 0) +MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x0608, 0x0238, 0, 0x0868, 1, 0) +MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x0608, 0x0238, 2, 0x08F0, 1, 0) +MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x0608, 0x0238, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x0608, 0x0238, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x060C, 0x023C, 0, 0x087C, 1, 0) +MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x060C, 0x023C, 2, 0x08FC, 1, 0) +MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x060C, 0x023C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x060C, 0x023C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x060C, 0x023C, 22, 0x08A8, 2, 0) +MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x060C, 0x023C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0610, 0x0240, 0, 0x0884, 1, 0) +MX6_PAD_DECL(GPIO_7__ECSPI5_RDY, 0x0610, 0x0240, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0610, 0x0240, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0610, 0x0240, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0610, 0x0240, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0610, 0x0240, 4, 0x0928, 2, 0) +MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0610, 0x0240, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0610, 0x0240, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0610, 0x0240, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x0614, 0x0244, 0, 0x0888, 1, 0) +MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x0614, 0x0244, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x0614, 0x0244, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x0614, 0x0244, 3, 0x07E4, 1, 0) +MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x0614, 0x0244, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x0614, 0x0244, 4, 0x0928, 3, 0) +MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x0614, 0x0244, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x0614, 0x0244, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x0614, 0x0244, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x0618, 0x0248, 0, 0x0880, 1, 0) +MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x0618, 0x0248, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x0618, 0x0248, 2, 0x083C, 1, 0) +MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x0618, 0x0248, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x0618, 0x0248, 4, 0x0914, 3, 0) +MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x0618, 0x0248, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x0618, 0x0248, 22, 0x08AC, 2, 0) +MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x0618, 0x0248, 7, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x061C, 0x024C, 0, 0x0874, 0, 0) +MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x061C, 0x024C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x061C, 0x024C, 2, 0x07F0, 1, 0) +MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x061C, 0x024C, 3, 0x090C, 1, 0) +MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x061C, 0x024C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x061C, 0x024C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x0620, 0x0250, 0, 0x0878, 0, 0) +MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x0620, 0x0250, 1, 0x0844, 1, 0) +MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x0620, 0x0250, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x0620, 0x0250, 3, 0x0910, 1, 0) +MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x0620, 0x0250, 4, 0x07B0, 2, 0) +MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x0620, 0x0250, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x0620, 0x0250, 6, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x0624, 0x0254, 0, 0x08E8, 1, 0) +MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x0624, 0x0254, 1, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x0624, 0x0254, 2, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x0624, 0x0254, 3, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x0624, 0x0254, 4, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x0624, 0x0254, 5, 0x0000, 0, 0) +MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x0624, 0x0254, 6, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x0628, 0x0258, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x0628, 0x0258, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x062C, 0x025C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x062C, 0x025C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x062C, 0x025C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x062C, 0x025C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x0630, 0x0260, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x0630, 0x0260, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x0630, 0x0260, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x0634, 0x0264, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x0634, 0x0264, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x0634, 0x0264, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0638, 0x0268, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0638, 0x0268, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0638, 0x0268, 2, 0x07F4, 3, 0) +MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0638, 0x0268, 3, 0x08E8, 2, 0) +MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0638, 0x0268, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0638, 0x0268, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0638, 0x0268, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x063C, 0x026C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x063C, 0x026C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x063C, 0x026C, 2, 0x07FC, 3, 0) +MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x063C, 0x026C, 3, 0x08F4, 1, 0) +MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x063C, 0x026C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x063C, 0x026C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x063C, 0x026C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0640, 0x0270, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0640, 0x0270, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0640, 0x0270, 2, 0x07F8, 3, 0) +MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0640, 0x0270, 3, 0x08EC, 1, 0) +MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0640, 0x0270, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0640, 0x0270, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0640, 0x0270, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0644, 0x0274, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0644, 0x0274, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0644, 0x0274, 2, 0x0800, 3, 0) +MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0644, 0x0274, 3, 0x08F8, 2, 0) +MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0644, 0x0274, 4, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0644, 0x0274, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0644, 0x0274, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0648, 0x0278, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0648, 0x0278, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0648, 0x0278, 2, 0x0810, 2, 0) +MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0648, 0x0278, 3, 0x08F0, 2, 0) +MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0648, 0x0278, 20, 0x089C, 1, 0) +MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0648, 0x0278, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0648, 0x0278, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x064C, 0x027C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x064C, 0x027C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x064C, 0x027C, 2, 0x0818, 2, 0) +MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x064C, 0x027C, 3, 0x08FC, 2, 0) +MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x064C, 0x027C, 20, 0x0898, 1, 0) +MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x064C, 0x027C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x064C, 0x027C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0650, 0x0280, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0650, 0x0280, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0650, 0x0280, 2, 0x0814, 2, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0650, 0x0280, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0650, 0x0280, 3, 0x0920, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0650, 0x0280, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0650, 0x0280, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0654, 0x0284, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0654, 0x0284, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0654, 0x0284, 2, 0x081C, 2, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0654, 0x0284, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0654, 0x0284, 3, 0x0920, 1, 0) +MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0654, 0x0284, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0654, 0x0284, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0658, 0x0288, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0658, 0x0288, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0658, 0x0288, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0658, 0x0288, 3, 0x0938, 2, 0) +MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0658, 0x0288, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0658, 0x0288, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x065C, 0x028C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x065C, 0x028C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x065C, 0x028C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x065C, 0x028C, 3, 0x0938, 3, 0) +MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x065C, 0x028C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x065C, 0x028C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0660, 0x0290, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0660, 0x0290, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0660, 0x0290, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0660, 0x0290, 3, 0x0940, 2, 0) +MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0660, 0x0290, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0660, 0x0290, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0664, 0x0294, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0664, 0x0294, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0664, 0x0294, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0664, 0x0294, 3, 0x0940, 3, 0) +MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0664, 0x0294, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0664, 0x0294, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0668, 0x0298, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0668, 0x0298, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0668, 0x0298, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0668, 0x0298, 3, 0x0934, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0668, 0x0298, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0668, 0x0298, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x066C, 0x029C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x066C, 0x029C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x066C, 0x029C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x066C, 0x029C, 3, 0x0934, 1, 0) +MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x066C, 0x029C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x066C, 0x029C, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0670, 0x02A0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0670, 0x02A0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0670, 0x02A0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0670, 0x02A0, 3, 0x093C, 2, 0) +MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0670, 0x02A0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0670, 0x02A0, 7, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0674, 0x02A4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0674, 0x02A4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0674, 0x02A4, 3, 0x0000, 0, 0) +MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0674, 0x02A4, 3, 0x093C, 3, 0) +MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0674, 0x02A4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0690, 0x02A8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0690, 0x02A8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0690, 0x02A8, 1, 0x0920, 2, 0) +MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0690, 0x02A8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0694, 0x02AC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0694, 0x02AC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0694, 0x02AC, 1, 0x0920, 3, 0) +MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0694, 0x02AC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0698, 0x02B0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0698, 0x02B0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0698, 0x02B0, 1, 0x0928, 4, 0) +MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0698, 0x02B0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x069C, 0x02B4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x069C, 0x02B4, 1, 0x0928, 5, 0) +MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0) +MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06A4, 0x02BC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06A4, 0x02BC, 1, 0x0924, 3, 0) +MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06A4, 0x02BC, 2, 0x07E4, 2, 0) +MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06A8, 0x02C0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06A8, 0x02C0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06A8, 0x02C0, 1, 0x091C, 2, 0) +MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06A8, 0x02C0, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x06AC, 0x02C4, 1, 0x091C, 3, 0) +MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x06AC, 0x02C4, 2, 0x07E8, 1, 0) +MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x06B4, 0x02CC, 1, 0x092C, 4, 0) +MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x06B8, 0x02D0, 1, 0x092C, 5, 0) +MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__IPU2_SISG4, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__IPU2_SISG5, 0x06C4, 0x02DC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x06C8, 0x02E0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__IPU2_DI0_PIN01, 0x06C8, 0x02E0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x06D0, 0x02E8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x06D4, 0x02EC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x06D4, 0x02EC, 2, 0x0874, 1, 0) +MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS2__IPU2_SISG0, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x06D8, 0x02F0, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 0x0878, 1, 0) +MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0) +MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x06E0, 0x02F8, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x06E0, 0x02F8, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x06E0, 0x02F8, 2, 0x0930, 3, 0) +MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x06E4, 0x02FC, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x06E8, 0x0300, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x06E8, 0x0300, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x06E8, 0x0300, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x06EC, 0x0304, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x06EC, 0x0304, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x06EC, 0x0304, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x06F0, 0x0308, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x06F0, 0x0308, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x06F0, 0x0308, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x06F4, 0x030C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x06F4, 0x030C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x06F4, 0x030C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x06F8, 0x0310, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x06F8, 0x0310, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x06F8, 0x0310, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x06FC, 0x0314, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x06FC, 0x0314, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x06FC, 0x0314, 5, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0700, 0x0318, 0, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0700, 0x0318, 1, 0x0000, 0, 0) +MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0700, 0x0318, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0704, 0x031C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0704, 0x031C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0704, 0x031C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x0708, 0x0320, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x0708, 0x0320, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x0708, 0x0320, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x070C, 0x0324, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x070C, 0x0324, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x070C, 0x0324, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0710, 0x0328, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0710, 0x0328, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0714, 0x032C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0714, 0x032C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0714, 0x032C, 2, 0x0928, 6, 0) +MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0714, 0x032C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x0718, 0x0330, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x0718, 0x0330, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x0718, 0x0330, 2, 0x0924, 4, 0) +MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x0718, 0x0330, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x071C, 0x0334, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x071C, 0x0334, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x071C, 0x0334, 2, 0x0924, 5, 0) +MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x071C, 0x0334, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0720, 0x0338, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0720, 0x0338, 2, 0x0928, 7, 0) +MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0720, 0x0338, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x0724, 0x033C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__ECSPI5_SS0, 0x0724, 0x033C, 1, 0x0834, 1, 0) +MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x0724, 0x033C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x0724, 0x033C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x0724, 0x033C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x0728, 0x0340, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__ECSPI5_MISO, 0x0728, 0x0340, 1, 0x082C, 1, 0) +MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x0728, 0x0340, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x0728, 0x0340, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x072C, 0x0344, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__ECSPI5_SS2, 0x072C, 0x0344, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x072C, 0x0344, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x072C, 0x0344, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x072C, 0x0344, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x072C, 0x0344, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0) +MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x0730, 0x0348, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x0730, 0x0348, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x0734, 0x034C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__ECSPI5_SS1, 0x0734, 0x034C, 1, 0x0838, 1, 0) +MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x0734, 0x034C, 2, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x0734, 0x034C, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x0734, 0x034C, 4, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x0734, 0x034C, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x0734, 0x034C, 6, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__ECSPI5_SCLK, 0x0738, 0x0350, 1, 0x0828, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x0738, 0x0350, 3, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x0738, 0x0350, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK, 0x073C, 0x0354, 1, 0x0828, 1, 0) +MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x073C, 0x0354, 2, 0x08E8, 3, 0) +MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0) +MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x073C, 0x0354, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0) +MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x0740, 0x0358, 2, 0x08F4, 2, 0) +MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x0740, 0x0358, 3, 0x07BC, 1, 0) +MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x0740, 0x0358, 5, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x0744, 0x035C, 0, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__ECSPI5_SS3, 0x0744, 0x035C, 1, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x0744, 0x035C, 2, 0x08EC, 2, 0) +MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x0744, 0x035C, 3, 0x07C4, 1, 0) +MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x0744, 0x035C, 5, 0x0000, 0, 0) #endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */ diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c index c3775ef..6db4488 100644 --- a/board/barco/titanium/titanium.c +++ b/board/barco/titanium/titanium.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 1b4791c..e063407 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 1cf649c..fc75eae 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include -- cgit v0.10.2 From 8d7b3638e97bb1393b4ecf835efead38ea5c1a34 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Tue, 17 Dec 2013 17:34:43 +0800 Subject: arm: atmel: at91sam9x5: cleanup cs configure for spi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As the cs for spi is worked in gpio mode, so no need to configure it as peripheral and then configure to gpio. Configure it to gpio directly. Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 6f67c34..17a2a40 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -271,7 +271,6 @@ int board_init(void) #endif #ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 0); at91_spi0_hw_init(1 << 4); #endif -- cgit v0.10.2 From 1ae37be7822858dead80c53ffa65733948ecda32 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Tue, 10 Dec 2013 16:14:01 +0800 Subject: arm: atmel: at91sam9x5: cleanup unneeded undef MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit remove unneeded #undef for at91sam9x5ek board. Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index ea9a50e..4eeaf3b 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -44,7 +44,6 @@ #define LCD_BPP LCD_COLOR16 #define LCD_OUTPUT_BPP 24 #define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO #define CONFIG_SYS_WHITE_ON_BLACK @@ -244,8 +243,4 @@ */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - #endif -- cgit v0.10.2 From d51a2a2d63d83207b56a7aef7a191d081058d6ae Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Tue, 10 Dec 2013 16:14:02 +0800 Subject: arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper position MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In config_cmd_default.h, it will use CONFIG_SYS_NO_FLASH to decide whether include CONFIG_CMD_FLASH and CONFIG_CMD_IMLS. So, move the CONFIG_SYS_NO_FLASH to proper position, then we don't need to undef these two commands. Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 4eeaf3b..f0a6757 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -61,14 +61,15 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH + /* * Command line configuration. */ #include #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP @@ -100,9 +101,6 @@ #define CONFIG_SF_DEFAULT_SPEED 30000000 #endif -/* no NOR flash */ -#define CONFIG_SYS_NO_FLASH - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL -- cgit v0.10.2 From 164d98466103a46b7c881149e92ec2a28a6375be Mon Sep 17 00:00:00 2001 From: Giuseppe Pagano Date: Thu, 28 Nov 2013 12:32:48 +0100 Subject: nitrogen6x: Move setup_sata to common part Move setup_sata function definition from platform file nitrogen6x.c to arch/arm/imx-common/sata.c to avoid code duplication. Signed-off-by: Giuseppe Pagano CC: Stefano Babic CC: Fabio Estevam CC: Eric Nelson diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 2c80441..68f0f52 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -17,6 +17,9 @@ endif ifeq ($(SOC),$(filter $(SOC),mx6 mxs)) obj-y += misc.o endif +ifeq ($(SOC),$(filter $(SOC),mx6)) +objs-$(CONFIG_CMD_SATA) += sata.o +endif obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c new file mode 100644 index 0000000..1b4c502 --- /dev/null +++ b/arch/arm/imx-common/sata.c @@ -0,0 +1,33 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3< #include #include +#include #include #include #include @@ -401,32 +402,6 @@ static void setup_buttons(void) ARRAY_SIZE(button_pads)); } -#ifdef CONFIG_CMD_SATA - -int setup_sata(void) -{ - struct iomuxc_base_regs *const iomuxc_regs - = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; - int ret = enable_sata_clock(); - if (ret) - return ret; - - clrsetbits_le32(&iomuxc_regs->gpr[13], - IOMUXC_GPR13_SATA_MASK, - IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB - |IOMUXC_GPR13_SATA_PHY_7_SATA2M - |IOMUXC_GPR13_SATA_SPEED_3G - |(3< Date: Thu, 28 Nov 2013 12:32:49 +0100 Subject: udoo: Add SATA support on uDoo Board. Add SATA support on uDoo Board. Signed-off-by: Giuseppe Pagano CC: Stefano Babic CC: Fabio Estevam diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index 081d517..e9236d4 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -240,6 +241,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif return 0; } diff --git a/include/configs/udoo.h b/include/configs/udoo.h index b9a493c..a1a1750 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -34,6 +34,18 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +/* SATA Configs */ + +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + /* Network support */ #define CONFIG_CMD_PING -- cgit v0.10.2 From 015999584167b946dbc8f0c4fee96cc806dd10cc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 20:38:10 -0200 Subject: configs: imx: Remove CONFIG_SYS_SPD_BUS_NUM option According to the README: "- CONFIG_SYS_SPD_BUS_NUM If SPD EEPROM is on an I2C bus other than the first one, specify here. Note that the value must resolve to something your driver can deal with." There is no SPD EEPROM on the imx boards, so ged rid of this option. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 7b55695..ffb67c2 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -37,7 +37,6 @@ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */ #define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET #define CONFIG_MXC_UART diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index fb564b0..af6aafa 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -115,7 +115,6 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C1 */ /* RTC */ #define CONFIG_RTC_IMXDI diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 4b4503c..0a46f4c 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -42,7 +42,6 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C1 */ #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 60c40c8..797a637 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -46,7 +46,6 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */ /* MMC Configs */ #define CONFIG_FSL_ESDHC diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index d0b5258..3f0d80a 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -39,7 +39,6 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */ /* PMIC Configs */ #define CONFIG_POWER diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 7b735ab..ae43ea3 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -73,7 +73,6 @@ /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C1 */ /* PMIC Controller */ #define CONFIG_POWER diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index c9618b4..a04e7c7 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -36,7 +36,6 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_SPD_BUS_NUM 1 /* I2C2 */ /* MMC Configs */ #define CONFIG_FSL_ESDHC -- cgit v0.10.2 From 02824dc78642b3057cc8c1ab7dc32203f55a17fa Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 26 Nov 2013 17:40:30 -0700 Subject: ARM: mx6: Update non-Freescale boards to include CPU errata. The CPU errata expressed in include/configs/mx6_common.h apply to all i.MX6DQ and i.MX6DLS parts. Signed-off-by: Eric Nelson Reviewed-by: Fabio Estevam Acked-by: Stefan Roese diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 957dabe..9c9f8f7 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -10,6 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "mx6_common.h" #define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/titanium.h b/include/configs/titanium.h index 0bb6731..f9e00c5 100644 --- a/include/configs/titanium.h +++ b/include/configs/titanium.h @@ -13,6 +13,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "mx6_common.h" #include #include diff --git a/include/configs/udoo.h b/include/configs/udoo.h index a1a1750..4d96f18 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -9,6 +9,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "mx6_common.h" #include #include #include diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index e9c7e64..8ce2d6e 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -9,6 +9,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "mx6_common.h" #include #include #include -- cgit v0.10.2 From 1230743731cb8a2e3348044e2535e890d16fb2e6 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Fri, 29 Nov 2013 22:38:39 +0800 Subject: MX6 SabreSD: Use readl() to read the CCM_CCGR3 register Align with the context to use readl() to read the CCM_CCGR3 register with memory barrier instead of __raw_readl(). Signed-off-by: Liu Ying Reviewed-by: Fabio Estevam diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 851cbe9..3a1fb20 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -390,7 +390,7 @@ static void setup_display(void) imx_setup_hdmi(); /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ - reg = __raw_readl(&mxc_ccm->CCGR3); + reg = readl(&mxc_ccm->CCGR3); reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; writel(reg, &mxc_ccm->CCGR3); -- cgit v0.10.2 From 502a710f5b54bbb966db4c4516abf5d82f46dd47 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 2 Dec 2013 17:01:42 +0100 Subject: ARM: mx53: video: Add IPUv3 LCD support for M53EVK This patch adds support for the AMPIRE 800x480 LCD panel that is available for M53EVK. Signed-off-by: Marek Vasut Cc: Stefano Babic diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c index 3275170..0f71a16 100644 --- a/board/denx/m53evk/m53evk.c +++ b/board/denx/m53evk/m53evk.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,11 @@ #include #include #include +#include +#include + +/* Special MXCFB sync flags are here. */ +#include "../drivers/video/mxcfb.h" DECLARE_GLOBAL_DATA_PTR; @@ -166,6 +172,32 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_VIDEO +static struct fb_videomode const ampire_wvga = { + .name = "Ampire", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29851, /* picosecond (33.5 MHz) */ + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_CLK_LAT_FALL, +}; + +int board_video_skip(void) +{ + int ret; + ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666); + if (ret) + printf("Ampire LCD cannot be configured: %d\n", ret); + return ret; +} +#endif + #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) @@ -179,6 +211,46 @@ static void setup_iomux_i2c(void) imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); } +static void setup_iomux_video(void) +{ + static const iomux_v3_cfg_t lcd_pads[] = { + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0, + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1, + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2, + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3, + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4, + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5, + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6, + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7, + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8, + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9, + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10, + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11, + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12, + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13, + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14, + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15, + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16, + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17, + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18, + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19, + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20, + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21, + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22, + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23, + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK, + MX53_PAD_EIM_DA13__IPU_DI1_D0_CS, + MX53_PAD_EIM_DA14__IPU_DI1_D1_CS, + MX53_PAD_EIM_DA15__IPU_DI1_PIN1, + MX53_PAD_EIM_DA11__IPU_DI1_PIN2, + MX53_PAD_EIM_DA12__IPU_DI1_PIN3, + MX53_PAD_EIM_A25__IPU_DI1_PIN12, + MX53_PAD_EIM_DA10__IPU_DI1_PIN15, + }; + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); +} + static void setup_iomux_nand(void) { static const iomux_v3_cfg_t nand_pads[] = { @@ -269,6 +341,7 @@ int board_early_init_f(void) setup_iomux_fec(); setup_iomux_i2c(); setup_iomux_nand(); + setup_iomux_video(); m53_set_clock(); diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 8c54549..a344af4 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -37,6 +37,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SATA #define CONFIG_CMD_USB +#define CONFIG_VIDEO /* * Memory configurations @@ -201,6 +202,21 @@ #endif /* + * LCD + */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 200000000 +#endif + +/* * Boot Linux */ #define CONFIG_CMDLINE_TAG -- cgit v0.10.2 From 89cfd0f5757413093ad179478b80367d7bd34ecc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 Dec 2013 18:26:13 -0200 Subject: mx6: clock: Fix the calculation of PLL_ENET frequency According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury Signed-off-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 873d9d0..20c7e70 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -94,7 +94,7 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) div = __raw_readl(&imx_ccm->analog_pll_enet); div &= BM_ANADIG_PLL_ENET_DIV_SELECT; - return (div == 3 ? 125000000 : 25000000 * (div << 1)); + return 25000000 * (div + (div >> 1) + 1); default: return 0; } -- cgit v0.10.2 From be4ab3dd05504e771fb743d39f88186c4d8b1165 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 4 Dec 2013 01:08:16 -0200 Subject: mx6sabresd: Allow probing HSYNC, VSYNC and DISP_CLK signals HSYNC, VSYNC and DISP_CLK are very useful display signals for debugging. Configure them as active pins. Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 3a1fb20..ecd2eab 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -135,6 +135,12 @@ static void setup_spi(void) imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); } +iomux_v3_cfg_t const di0_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ +}; + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -386,6 +392,9 @@ static void setup_display(void) struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; int reg; + /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ + imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); + enable_ipu_clock(); imx_setup_hdmi(); -- cgit v0.10.2 From 119e9909869ee3e2a994a01130014b93fade3bcc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 4 Dec 2013 01:08:17 -0200 Subject: mx6sabresd: Fix LVDS width and color format mx6sabresd boards have a 18-bit LVDS data width and the correct color format is RGB666. Suggested-by: Liu Ying Signed-off-by: Fabio Estevam diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index ecd2eab..2ffc3b8 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -294,15 +294,15 @@ static void enable_lvds(struct display_info_t const *dev) struct iomuxc *iomux = (struct iomuxc *) IOMUXC_BASE_ADDR; u32 reg = readl(&iomux->gpr[2]); - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | - IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT; + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; writel(reg, &iomux->gpr[2]); } static struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, - .pixfmt = IPU_PIX_FMT_LVDS666, + .pixfmt = IPU_PIX_FMT_RGB666, .detect = NULL, .enable = enable_lvds, .mode = { -- cgit v0.10.2 From 5b5a82eb7054869e869c2aa3c7018fe50a84c47a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 4 Dec 2013 14:27:40 +0100 Subject: ARM: mxs: tools: Fix errno handling in strtoul() invocation According to NOTE in strtoul(3), the errno must be zeroed before strtoul() is called. Zero the errno. The NOTE reads as such: Since strtoul() can legitimately return 0 or ULONG_MAX (ULLONG_MAX for strtoull()) on both success and failure, the calling program should set errno to 0 before the call, and then determine if an error occurred by checking whether errno has a nonzero value after the call. This issue was detected on Fedora 19 with glibc 2.17 . Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Tom Rini diff --git a/tools/mxsimage.c b/tools/mxsimage.c index 5db19b2..7bd9dee 100644 --- a/tools/mxsimage.c +++ b/tools/mxsimage.c @@ -502,6 +502,7 @@ static int sb_token_to_long(char *tok, uint32_t *rid) tok += 2; + errno = 0; id = strtoul(tok, &endptr, 16); if ((errno == ERANGE && id == ULONG_MAX) || (errno != 0 && id == 0)) { fprintf(stderr, "ERR: Value can't be decoded!\n"); -- cgit v0.10.2 From ebaf6b26bc12bd470188f3149a75397f112ab09d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 14 Nov 2013 00:58:46 +0800 Subject: imx6: fix random hang when download by usb ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai Signed-off-by: Frank Li diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index a390296..335706a 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -150,6 +150,8 @@ int arch_cpu_init(void) #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { + /* Avoid random hang when download by usb */ + invalidate_dcache_all(); /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } -- cgit v0.10.2 From 36da5f84a90df444bbac0c3197d4945383075b76 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 10 Dec 2013 14:52:20 +0900 Subject: arm: rmobile: Update README.rmobile Add infomation of Lager and Koelsh board, and R-Car. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu diff --git a/doc/README.rmobile b/doc/README.rmobile index 7ec63f1..4fbbcb3 100644 --- a/doc/README.rmobile +++ b/doc/README.rmobile @@ -2,13 +2,15 @@ Summary ======= This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1] -family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9. +and R-Car[2]family of SoCs. Renesas's RMOBILE/R-Car SoC family contains an ARM +Cortex-A9. Currently the following boards are supported: -* KMC KZM-A9-GT [2] - -* Atmark-Techno Armadillo-800-EVA [3] +* KMC KZM-A9-GT [3] +* Atmark-Techno Armadillo-800-EVA [4] +* Renesas Electronics Lager +* Renesas Electronics Koelsch Toolchain ========= @@ -17,7 +19,7 @@ ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a). But currently we compile with -march=armv5 to allow more compilers to work. (For U-Boot code this has no performance impact.) Because there was no compiler which is supporting armv7a not much before. -Currently, ELDK[4], Linaro[5], CodeSourcey[6] and Emdebian[7] supports -march=armv7a +Currently, ELDK[5], Linaro[6], CodeSourcey[7] and Emdebian[8] supports -march=armv7a and you can get. Build @@ -25,13 +27,26 @@ Build * KZM-A9-GT -make kzm9g_config -make + make kzm9g_config + make * Armadillo-800-EVA -make armadillo-800eva_config -make + make armadillo-800eva_config + make + + Note: Armadillo-800-EVA's U-Boot supports booting from SDcard only. + Please see "B.2 Appendix B Boot Specifications" in hardware manual. + +* Lager + + make lager_config + make + +* Koelsch + + make koelsch_config + make Links ===== @@ -40,26 +55,30 @@ Links http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp -[2] KZM-A9-GT +[2] Renesas R-Car: + +http://am.renesas.com/products/soc/assp/automotive/index.jsp + +[3] KZM-A9-GT http://www.kmckk.co.jp/kzma9-gt/index.html -[3] Armadillo-800-EVA +[4] Armadillo-800-EVA http://armadillo.atmark-techno.com/armadillo-800-EVA -[4] ELDK +[5] ELDK http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6. -[5] Linaro +[6] Linaro http://www.linaro.org/downloads/ -[6] CodeSourcey +[7] CodeSourcey http://www.mentor.com/embedded-software/codesourcery -[7] Emdebian +[8] Emdebian http://www.emdebian.org/crosstools.html -- cgit v0.10.2 From 23565c6bccf098418a03405bedda6f7d3e68da36 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 20 Oct 2013 20:28:24 +0900 Subject: arm: lager: Add support Ethernet The lager board has one sh-ether device. This supports sh-ether. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 5c99fc9..ba923d5 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "qos.h" DECLARE_GLOBAL_DATA_PTR; @@ -207,6 +208,10 @@ void s_init(void) #define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) +#define MSTPSR8 0xE61509A0 +#define SMSTPCR8 0xE6150990 +#define ETHER_MSTP813 (1 << 13) + #define PMMR 0xE6060000 #define GPSR4 0xE6060014 #define IPSR14 0xE6060058 @@ -242,6 +247,9 @@ int board_early_init_f(void) mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + return 0; } @@ -256,6 +264,68 @@ int board_init(void) /* Init PFC controller */ r8a7790_pinmux_init(); + /* ETHER Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REF_CLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_MAGIC, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ + gpio_direction_output(GPIO_GP_5_31, 0); + mdelay(20); + gpio_set_value(GPIO_GP_5_31, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ + int ret = -ENODEV; + +#ifdef CONFIG_SH_ETHER + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + +#endif + + return ret; +} + +/* lager has KSZ8041NL/RNL */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) +{ + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); + return 0; } diff --git a/include/configs/lager.h b/include/configs/lager.h index 7819edd..e4a5cca 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -28,6 +28,11 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_RUN #define CONFIG_CMD_LOADS +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_FLASH @@ -127,6 +132,20 @@ #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + /* Board Clock */ #define CONFIG_BASE_CLK_FREQ 20000000u #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */ -- cgit v0.10.2 From b9107adf0bda7725184de7ab8bac56f3aa9cb553 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 30 Sep 2013 10:08:40 +0900 Subject: arm: lager: Add support I2C The lager board has I2C for rcar. This supports I2C for rcar on lager board. Signed-off-by: Nobuhiro Iwamatsu diff --git a/include/configs/lager.h b/include/configs/lager.h index e4a5cca..dd61ca0 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -146,12 +146,26 @@ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_RCAR +#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 +#define CONFIG_SYS_RCAR_I2C0_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 +#define CONFIG_SYS_RCAR_I2C1_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 +#define CONFIG_SYS_RCAR_I2C2_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 +#define CONFIG_SYS_RCAR_I2C3_SPEED 400000 +#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 + /* Board Clock */ #define CONFIG_BASE_CLK_FREQ 20000000u #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */ #define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2) #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) +#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 -- cgit v0.10.2 From b9986be0840d7945f760204bfb1a4b565ba235ff Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 10 Oct 2013 09:13:41 +0900 Subject: arm: lager: Add support reset function The lager board uses I2C for reset. ned-off-by: Nobuhiro Iwamatsu diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index ba923d5..cdd5b32 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "qos.h" DECLARE_GLOBAL_DATA_PTR; @@ -354,4 +355,11 @@ int board_late_init(void) void reset_cpu(ulong addr) { + u8 val; + + i2c_set_bus_num(3); /* PowerIC connected to ch3 */ + i2c_init(400000, 0); + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); } diff --git a/include/configs/lager.h b/include/configs/lager.h index dd61ca0..8932825 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -159,6 +159,8 @@ #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + /* Board Clock */ #define CONFIG_BASE_CLK_FREQ 20000000u #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */ -- cgit v0.10.2 From 90362c0c04a9b7ec7d251ddf208ec411be456b6c Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 20 Oct 2013 20:37:17 +0900 Subject: arm: koelsch: Add support Ethernet The koelsch board has one sh-ether device. This supports sh-ether. Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 7153f65..73cad66 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include "qos.h" @@ -207,6 +209,10 @@ void s_init(void) #define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) +#define MSTPSR8 0xE61509A0 +#define SMSTPCR8 0xE6150990 +#define ETHER_MSTP813 (1 << 13) + #define PMMR 0xE6060000 #define GPSR4 0xE6060014 #define IPSR14 0xE6060058 @@ -241,9 +247,16 @@ int board_early_init_f(void) mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + return 0; } +/* LSI pin pull-up control */ +#define PUPR5 0xe6060114 +#define PUPR5_ETH 0x3FFC0000 +#define PUPR5_ETH_MAGIC (1 << 27) int board_init(void) { /* adress of boot parameters */ @@ -252,7 +265,57 @@ int board_init(void) /* Init PFC controller */ r8a7791_pinmux_init(); + /* ETHER Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); + gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); + + gpio_direction_output(GPIO_GP_5_22, 0); + mdelay(20); + gpio_set_value(GPIO_GP_5_22, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + + return ret; +#else return 0; +#endif } int dram_init(void) @@ -263,6 +326,20 @@ int dram_init(void) return 0; } +/* koelsch has KSZ8041NL/RNL */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) +{ + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); + + return 0; +} + const struct rmobile_sysinfo sysinfo = { CONFIG_RMOBILE_BOARD_STRING }; diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 59c4948..32ceff3 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -18,13 +18,18 @@ #include -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_MEMORY #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM #define CONFIG_CMD_RUN #define CONFIG_CMD_LOADS +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_FLASH @@ -123,6 +128,20 @@ #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 + /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 10000000 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ -- cgit v0.10.2 From bb611cce32338bc35b49538ca23d90a8f3e977c4 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Wed, 11 Sep 2013 15:04:33 +0900 Subject: arm: koelsch: Add support I2C This supports sh_i2c on koelsch board. Signed-off-by: Nobuhiro Iwamatsu diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 32ceff3..f410a8f 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -149,4 +149,20 @@ #define CONFIG_SYS_TMU_CLK_DIV 4 #define CONFIG_SYS_HZ 1000 +/* i2c */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + #endif /* __KOELSCH_H */ -- cgit v0.10.2 From b8f383b86bc748382cc7cb5b3602c0c2ff9cb60c Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 10 Oct 2013 10:48:20 +0900 Subject: arm: koelsch: Add support reset function Signed-off-by: Nobuhiro Iwamatsu diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 73cad66..89f5c91 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -357,4 +357,10 @@ int board_late_init(void) void reset_cpu(ulong addr) { + u8 val; + + i2c_set_bus_num(2); /* PowerIC connected to ch2 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); } diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index f410a8f..f8cca5b 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -165,4 +165,6 @@ #define CONFIG_SH_I2C_DATA_LOW 5 #define CONFIG_SH_I2C_CLOCK 10000000 +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + #endif /* __KOELSCH_H */ -- cgit v0.10.2 From 23f00caf6ebb9bcb804e48f5a4630629f64af471 Mon Sep 17 00:00:00 2001 From: Sergei Ianovich Date: Tue, 17 Dec 2013 05:03:40 +0400 Subject: ARM: pxa: prevent PXA270 occasional reboot freezes Erratum 71 of PXA270M Processor Family Specification Update (April 19, 2010) explains that watchdog reset time is just 8us insead of 10ms in EMTS. If SDRAM is not reset, it causes memory bus congestion and the device hangs. We put SDRAM in selfresh mode before watchdog reset, removing potential freezes. Signed-off-by: Sergei Ianovich CC: Marek Vasut diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index c9a7d45..7e861e2 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -279,6 +279,7 @@ void reset_cpu(ulong ignored) tmp = readl(OSCR); tmp += 0x1000; writel(tmp, OSMR3); + writel(MDREFR_SLFRSH, MDREFR); for (;;) ; -- cgit v0.10.2 From a3d6ca432303bc19926a885c83149401abc24d0d Mon Sep 17 00:00:00 2001 From: Sergei Ianovich Date: Wed, 18 Dec 2013 20:19:20 +0400 Subject: arm: pxa: fix LP-8x4x USB support Signed-off-by: Sergei Ianovich CC: Marek Vasut diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c index 92dd4ff..5eee18a 100644 --- a/board/icpdas/lp8x4x/lp8x4x.c +++ b/board/icpdas/lp8x4x/lp8x4x.c @@ -61,15 +61,24 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_CMD_USB int board_usb_init(int index, enum usb_init_type init) { - writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), - UHCHR); + if (index !=0 || init != USB_INIT_HOST) + return -1; + + writel(readl(CKEN) | CKEN10_USBHOST, CKEN); + + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); + udelay(11); + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); while (readl(UHCHR) & UHCHR_FSBIR) continue; /* required by checkpath.pl */ + writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); + writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA); + writel(readl(UHCRHDA) | 0x800, UHCRHDA); + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); @@ -83,19 +92,10 @@ int board_usb_init(int index, enum usb_init_type init) /* Set port power control mask bits, only 3 ports. */ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); - /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - return 0; } -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} - -void usb_board_stop(void) +int usb_board_stop(void) { writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); @@ -104,9 +104,19 @@ void usb_board_stop(void) writel(readl(UHCCOMS) | 1, UHCCOMS); udelay(10); + writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR); + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); - return; + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + if (index !=0 || init != USB_INIT_HOST) + return -1; + + return usb_board_stop(); } #endif diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h index 68e1a97..324cc4d 100644 --- a/include/configs/lp8x4x.h +++ b/include/configs/lp8x4x.h @@ -184,7 +184,7 @@ #define CONFIG_SYS_GAFR1_L_VAL 0x999a955a #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402 +#define CONFIG_SYS_GAFR2_U_VAL 0x55f9a402 #define CONFIG_SYS_GAFR3_L_VAL 0x540a950c #define CONFIG_SYS_GAFR3_U_VAL 0x00001599 @@ -232,7 +232,6 @@ */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_BOARD_INIT #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 -- cgit v0.10.2 From bf92349b41fb61364f2ea3b93d547eb68ade0946 Mon Sep 17 00:00:00 2001 From: Sergei Ianovich Date: Tue, 17 Dec 2013 05:03:42 +0400 Subject: arm: pxa: fix 2nd flash chip address on LP-8x4x Initial configuration has worng address of the second chip. There is an alias for the 1st chip at 0x02000000 in earlier verions of LP-8x4x, so the boot normally. However, new LP-8x4xs have a bigger 1st flash chip, and hang on boot without this patch. Signed-off-by: Sergei Ianovich CC: Marek Vasut diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h index 324cc4d..c5bf2fa 100644 --- a/include/configs/lp8x4x.h +++ b/include/configs/lp8x4x.h @@ -144,7 +144,7 @@ #define CONFIG_ENV_SECT_SIZE 0x40000 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER 1 -- cgit v0.10.2 From 7cd5441eb3b4fb30e6502ede0b80ae09674bdabf Mon Sep 17 00:00:00 2001 From: Sergei Ianovich Date: Tue, 17 Dec 2013 05:03:43 +0400 Subject: arm: pxa: update LP-8x4x to boot DT kernel DT kernel requires CONFIG_OF_LIBFDT. 'bootm' needs to know DT location. In addition, fix kernel console device and enable U-Boot long help. Signed-off-by: Sergei Ianovich CC: Marek Vasut diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h index c5bf2fa..8e58fea 100644 --- a/include/configs/lp8x4x.h +++ b/include/configs/lp8x4x.h @@ -20,18 +20,18 @@ #define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ - "bootm 80000;" + "bootm 80000 - 240000;" #define CONFIG_BOOTARGS \ - "console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \ - "init=/sbin/init rootfstype=ext3" + "console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \ + "init=/sbin/init rootfstype=ext4 rootwait" #define CONFIG_TIMESTAMP #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_LZMA /* LZMA compression support */ -#undef CONFIG_OF_LIBFDT +#define CONFIG_OF_LIBFDT /* * Serial Console Configuration @@ -101,7 +101,7 @@ */ #define CONFIG_SYS_HUSH_PARSER 1 -#undef CONFIG_SYS_LONGHELP +#define CONFIG_SYS_LONGHELP #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " #else -- cgit v0.10.2 From 914f2bd1f07fba93639ad1273d4cd458b0ee99cc Mon Sep 17 00:00:00 2001 From: Sergei Ianovich Date: Tue, 17 Dec 2013 05:03:44 +0400 Subject: arm: pxa: init ethaddr for LP-8x4x using DT When DT define aliases for etherner0 and ethernet1, U-Boot automatically patched MAC addresses using ethaddr and eth1addr environment variables respectively. Custom initialization is no longer needed. Signed-off-by: Sergei Ianovich CC: Marek Vasut diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c index 5eee18a..a136dc4 100644 --- a/board/icpdas/lp8x4x/lp8x4x.c +++ b/board/icpdas/lp8x4x/lp8x4x.c @@ -121,25 +121,8 @@ int board_usb_cleanup(int index, enum usb_init_type init) #endif #ifdef CONFIG_DRIVER_DM9000 -void lp8x4x_eth1_mac_init(void) -{ - u8 eth1addr[8]; - int i; - u8 reg; - - eth_getenv_enetaddr_by_index("eth", 1, eth1addr); - if (!is_valid_ether_addr(eth1addr)) - return; - - for (i = 0, reg = 0x10; i < 6; i++, reg++) { - writeb(reg, (u8 *)(DM9000_IO_2)); - writeb(eth1addr[i], (u8 *)(DM9000_DATA_2)); - } -} - int board_eth_init(bd_t *bis) { - lp8x4x_eth1_mac_init(); return dm9000_initialize(bis); } #endif -- cgit v0.10.2 From 44de8e22ecfc0106c0aea7f39b9aa85aebf46b9c Mon Sep 17 00:00:00 2001 From: Jimmy Zhang Date: Mon, 23 Sep 2013 22:07:49 +0200 Subject: Tegra114: Fix PLLX M, N, P init settings The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly. Signed-off-by: Jimmy Zhang Reviewed-by: Tom Warren Signed-off-by: Thierry Reding Acked-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 9294611..aa1e04f 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -49,33 +49,68 @@ int get_num_cpus(void) * Timing tables for each SOC for all four oscillator options. */ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { - /* T20: 1 GHz */ - /* n, m, p, cpcon */ - {{ 1000, 13, 0, 12}, /* OSC 13M */ - { 625, 12, 0, 8}, /* OSC 19.2M */ - { 1000, 12, 0, 12}, /* OSC 12M */ - { 1000, 26, 0, 12}, /* OSC 26M */ + /* + * T20: 1 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, - - /* T25: 1.2 GHz */ - {{ 923, 10, 0, 12}, - { 750, 12, 0, 8}, - { 600, 6, 0, 12}, - { 600, 13, 0, 12}, + /* + * T25: 1.2 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, - - /* T30: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 700, 6, 0, 8}, - { 700, 13, 0, 8}, + /* + * T30: 1.4 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */ + { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ }, - - /* T114: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 696, 12, 0, 8}, - { 700, 13, 0, 8}, + /* + * T114: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ }, }; -- cgit v0.10.2 From 4475c7752d054050ffb5e844a32ab1a6881d7aa0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 1 Oct 2013 17:04:45 +0200 Subject: Tegra114: Do not program CPCON field for PLLX PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index aa1e04f..72c69b9 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void) int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, u32 divp, u32 cpcon) { + int chip = tegra_get_chip(); u32 reg; /* If PLLX is already enabled, just return */ @@ -151,7 +152,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, writel(reg, &pll->pll_base); /* Set cpcon to PLLX_MISC */ - reg = (cpcon << PLL_CPCON_SHIFT); + if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) + reg = (cpcon << PLL_CPCON_SHIFT); + else + reg = 0; /* Set dccon to PLLX_MISC if freq > 600MHz */ if (divn > 600) -- cgit v0.10.2 From e4e251a94a8477d36fa61a9c219430fa4c83fb6b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 23 Sep 2013 11:52:41 +0200 Subject: Change maintainer for Avionic Design boards I no longer work for Avionic Design and don't have access to hardware, so I'll pass on maintainership to Alban. Acked-by: Alban Bedel Signed-off-by: Thierry Reding Signed-off-by: Tom Warren diff --git a/boards.cfg b/boards.cfg index b662149..c99d648 100644 --- a/boards.cfg +++ b/boards.cfg @@ -359,9 +359,9 @@ Active arm armv7 vf610 freescale vf610twr Active arm armv7 zynq xilinx zynq zynq - Michal Simek Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren -Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding -Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding -Active arm armv7:arm720t tegra20 avionic-design tec tec - Thierry Reding +Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel +Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel +Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren -- cgit v0.10.2 From 7dcd3a21ff556a196d60227fa04c9cdc5f9faa9c Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Thu, 31 Oct 2013 14:51:38 +0530 Subject: tegra: allow build to succeed with SPL disabled u-boot-dtb-tegra.bin and u-boot-nodtb-tegra.bin binaries are generated only if the SPL build is enabled as they have dependency on SPL build Signed-off-by: Vidya Sagar Signed-off-by: Tom Warren diff --git a/Makefile b/Makefile index 7310c4e..0d86b55 100644 --- a/Makefile +++ b/Makefile @@ -350,12 +350,14 @@ endif # enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) +ifeq ($(CONFIG_SPL),y) ifeq ($(CONFIG_OF_SEPARATE),y) ALL-y += $(obj)u-boot-dtb-tegra.bin else ALL-y += $(obj)u-boot-nodtb-tegra.bin endif endif +endif build := -f $(TOPDIR)/scripts/Makefile.build -C -- cgit v0.10.2 From 81d21e98b00c45372aaa9f47a6e9035f8daf843f Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 6 Nov 2013 14:03:44 +0800 Subject: ARM: config: USB: Tegra30/114: Fix EHCI timeout issue on "bootp" Fix the timeout issue after running "bootp" command in u-boot console. For example you see "EHCI timed out on TD- token=0x...". TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10 after a controller reset and before RUN bit is set (per technical reference manual). Signed-off-by: Jim Lin Tested-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index c3de9a9..a4e8a5f 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -82,5 +82,6 @@ /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 99acbfd..b5550d7 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -79,5 +79,6 @@ /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA30_COMMON_H_ */ -- cgit v0.10.2 From 3346cbb8e878bf5c774835ced7e3916da78e9b74 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Wed, 13 Nov 2013 17:27:18 +0100 Subject: ARM: tegra: support SKU b1 of Tegra30 Add the Tegra30 SKU b1 and treat it like other Tegra30 chips. Signed-off-by: Alban Bedel Reviewed-by: Julian Scheel Signed-off-by: Tom Warren diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 6fb11cb..60d71a6 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -71,6 +71,7 @@ int tegra_get_chip_sku(void) switch (sku_id) { case SKU_ID_T33: case SKU_ID_T30: + case SKU_ID_TM30MQS_P_A3: return TEGRA_SOC_T30; } break; diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 25d1fc4..e99f681 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -65,6 +65,7 @@ enum { SKU_ID_T25E = 0x1c, SKU_ID_T33 = 0x80, SKU_ID_T30 = 0x81, /* Cardhu value */ + SKU_ID_TM30MQS_P_A3 = 0xb1, SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ SKU_ID_T114_1 = 0x01, }; -- cgit v0.10.2 From ac2ff538cde458a100da71974bdca8c2142e9e19 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Wed, 13 Nov 2013 17:27:19 +0100 Subject: i2c: tegra: Add the fifth bus on SoC with more than 4 buses Create the i2c adapter object for the fifth bus on SoC with more than 4 buses. This allow using all the bus available on T30. Signed-off-by: Alban Bedel Acked-by: Heiko Schocher Signed-off-by: Tom Warren diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 9847cf1..594e5dd 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -629,3 +629,8 @@ U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe, U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe, tegra_i2c_read, tegra_i2c_write, tegra_i2c_set_bus_speed, 100000, 0, 3) +#if TEGRA_I2C_NUM_CONTROLLERS > 4 +U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe, + tegra_i2c_read, tegra_i2c_write, + tegra_i2c_set_bus_speed, 100000, 0, 4) +#endif -- cgit v0.10.2 From 8f38038193752d3719f39ccd562f7ffdf83989d5 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Thu, 14 Nov 2013 10:58:30 +0100 Subject: =?UTF-8?q?ARM:=20tegra:=20Add=20the=20Tamonten=E2=84=A2=20NG=20Ev?= =?UTF-8?q?aluation=20Carrier=20board?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for the new Tamonten™ NG platform from Avionic Design. Currently only I2C, MMC, USB and ethernet have been tested. Signed-off-by: Alban Bedel Reviewed-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h b/board/avionic-design/common/pinmux-config-tamonten-ng.h new file mode 100644 index 0000000..39df731 --- /dev/null +++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h @@ -0,0 +1,385 @@ +/* + * (C) Copyright 2013 + * Avionic Design GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_ +#define _PINMUX_CONFIG_TAMONTEN_NG_H_ + +#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = PINGRP_##_pingroup, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PGRP_LPMD_##_lpmd, \ + .schmt = PGRP_SCHMT_##_schmt, \ + .hsm = PGRP_HSM_##_hsm, \ + } + +static struct pingroup_config tamonten_ng_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS6_N, RSVD1, UP, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* UART1 */ + DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT), + + /* UART2 */ + DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), + + /* UART3 */ + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + + /* UART4 */ + DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR, UARTD, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT), + + /* DAP */ + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), + + /* I2S1 */ + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + + /* SPDIF */ + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT), + + /* I2S2 */ + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + + /* DAP4 */ + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + + /* Tamonten GPIO */ + DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS1_N, RSVD1, NORMAL, NORMAL, INPUT), + + /* LCD */ + DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT), + + /* BT656 */ + LV_PINMUX(VI_MCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D11, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* GPIOs */ + DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, INPUT), + + /* LCD BL */ + DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD10, RSVD4, NORMAL, NORMAL, OUTPUT), + + /* SPI4 */ + DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT), + + /* Video input GPIO */ + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT), + + /* Sensor GPIO */ + DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT), + + /* JTAG */ + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), + + /* Power controls */ + DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT), + + /* SPI1 */ + DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), + + /* PMU */ + DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT), + + /* PCI */ + DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + + /* HDMI */ + DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT), +}; + +static struct pingroup_config unused_pins_lowpower[] = { + /* UART1 - NC */ + DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT), + + /* UART2 - NC */ + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), + + /* DAP - NC */ + DEFAULT_PINMUX(CLK1_REQ, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_OUT, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, NORMAL, INPUT), + + /* DAP4 - NC */ + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + + /* Tamonten GPIO - NC */ + DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT), + + /* BT656 - NC */ + LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + + /* GPIO - NC */ + DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, INPUT), + + /* Video input - NC */ + DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB5, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11, RSVD1, NORMAL, NORMAL, INPUT), + + /* KBC keys - NC */ + DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT), + + /* PMU - NC */ + DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, NORMAL, INPUT), + + /* Power rails GPIO - NC */ + DEFAULT_PINMUX(SPI2_SCK, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB4, RSVD1, NORMAL, NORMAL, INPUT), + + /* Others - NC */ + DEFAULT_PINMUX(GMI_WP_N, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT), +}; + +static struct padctrl_config tamonten_ng_padctrl[] = { + /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_TAMONTEN_NG_H_ */ diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c new file mode 100644 index 0000000..9d395c6 --- /dev/null +++ b/board/avionic-design/common/tamonten-ng.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2013 + * Avionic Design GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "pinmux-config-tamonten-ng.h" +#include + +#define PMU_I2C_ADDRESS 0x2D + +#define PMU_REG_LDO5 0x32 + +#define PMU_REG_LDO_HIGH_POWER 1 + +/* Voltage selection for the LDOs with 100mV resolution */ +#define PMU_REG_LDO_SEL_100(mV) ((((mV - 1000) / 100) + 2) << 2) + +#define PMU_REG_LDO_100(st, mV) (PMU_REG_LDO_##st | PMU_REG_LDO_SEL_100(mV)) + +#define PMU_LDO5(st, mV) PMU_REG_LDO_100(st, mV) + +void pinmux_init(void) +{ + pinmux_config_table(tamonten_ng_pinmux_common, + ARRAY_SIZE(tamonten_ng_pinmux_common)); + pinmux_config_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + padgrp_config_table(tamonten_ng_padctrl, + ARRAY_SIZE(tamonten_ng_padctrl)); +} + +void gpio_early_init(void) +{ + /* Turn on the alive signal */ + gpio_request(GPIO_PV2, "ALIVE"); + gpio_direction_output(GPIO_PV2, 1); + + /* Remove the reset on the external periph */ + gpio_request(GPIO_PI4, "nRST_PERIPH"); + gpio_direction_output(GPIO_PI4, 1); +} + +void pmu_write(uchar reg, uchar data) +{ + i2c_set_bus_num(4); /* PMU is on bus 4 */ + i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1); +} + +/* + * Do I2C/PMU writes to bring up SD card bus power + * + */ +void board_sdmmc_voltage_init(void) +{ + /* Enable LDO5 with 3.3v for SDMMC3 */ + pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300)); + + /* Switch the power on */ + gpio_request(GPIO_PJ2, "EN_3V3_EMMC"); + gpio_direction_output(GPIO_PJ2, 1); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* + * NOTE: We don't do mmc-specific pin muxes here. + * They were done globally in pinmux_init(). + */ + + /* Bring up the SDIO1 power rail */ + board_sdmmc_voltage_init(); +} diff --git a/board/avionic-design/dts/tegra30-tamonten.dtsi b/board/avionic-design/dts/tegra30-tamonten.dtsi new file mode 100644 index 0000000..50d5762 --- /dev/null +++ b/board/avionic-design/dts/tegra30-tamonten.dtsi @@ -0,0 +1,69 @@ +#include "tegra30.dtsi" + +/ { + model = "Avionic Design Tamonten NG"; + compatible = "ad,tamonten-ng", "nvidia,tegra30"; + + memory { + reg = <0x80000000 0x40000000>; + }; + + aliases { + i2c0 = "/i2c@7000c000"; + i2c1 = "/i2c@7000c700"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000d000"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000400"; + sdhci2 = "/sdhci@78000000"; + usb0 = "/usb@7d008000"; + }; + + /* GEN1 */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* GEN2 */ + i2c@7000c400 { + clock-frequency = <100000>; + }; + + /* CAM */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* DDC */ + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* PWR */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* SD slot on the base board */ + sdhci@78000400 { + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + wp-gpios = <&gpio 67 0>; /* gpio PI3 */ + bus-width = <4>; + }; + + /* EMMC on the COM module */ + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; + + usb@7d008000 { + status = "okay"; + }; + +}; diff --git a/board/avionic-design/dts/tegra30-tec-ng.dts b/board/avionic-design/dts/tegra30-tec-ng.dts new file mode 100644 index 0000000..8a69e81 --- /dev/null +++ b/board/avionic-design/dts/tegra30-tec-ng.dts @@ -0,0 +1,18 @@ +/dts-v1/; + +#include "tegra30-tamonten.dtsi" + +/ { + model = "Avionic Design Tamonten™ NG Evaluation Carrier"; + compatible = "ad,tec-ng", "nvidia,tegra30"; + + /* GEN2 */ + i2c@7000c400 { + status = "okay"; + }; + + /* SD card slot */ + sdhci@78000400 { + status = "okay"; + }; +}; diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile new file mode 100644 index 0000000..f41eb30 --- /dev/null +++ b/board/avionic-design/tec-ng/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2013 +# Avionic Design GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) + +obj-y := ../common/tamonten-ng.o + +include ../../nvidia/common/common.mk diff --git a/boards.cfg b/boards.cfg index c99d648..152d85e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -362,6 +362,7 @@ Active arm armv7:arm720t tegra114 nvidia dalmore Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel +Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren :Stephen Warren Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h new file mode 100644 index 0000000..13baa76 --- /dev/null +++ b/include/configs/tec-ng.h @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2013 + * Avionic Design GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra30-common.h" + +/* Enable fdt support for tec-ng. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra30-tec-ng +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra30 (TEC-NG) # " +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 + +/* SPI */ +#define CONFIG_TEGRA20_SLINK +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +/* Tag support */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +/* support the new (FDT-based) image format */ +#define CONFIG_FIT + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ -- cgit v0.10.2 From 766afc3dff35f8f257deb0373735a328c8206880 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Wed, 20 Nov 2013 17:42:46 +0100 Subject: arm: tegra: Fix the CPU complex reset masks The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel Acked-by: Stephen Warren Tested-by: Stephen Warren Signed-off-by: Tom Warren diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index c3174bd..e7d0fd4 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -113,9 +113,9 @@ void reset_set_enable(enum periph_id periph_id, int enable); enum crc_reset_id { /* Things we can hold in reset for each CPU */ crc_rst_cpu = 1, - crc_rst_de = 1 << 2, /* What is de? */ - crc_rst_watchdog = 1 << 3, - crc_rst_debug = 1 << 4, + crc_rst_de = 1 << 4, /* What is de? */ + crc_rst_watchdog = 1 << 8, + crc_rst_debug = 1 << 12, }; /** -- cgit v0.10.2 From f90aea2a65e71a37ff029849d908538ae9e98283 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 4 Nov 2013 20:50:21 +0100 Subject: ARM: pxa: Fix CONFIG_SYS_HZ on PXA The PXA incorrectly uses CONFIG_SYS_HZ, which should be 1000 across U-Boot. Fix this. Signed-off-by: Marek Vasut Cc: Tom Rini Cc: Albert Aribaud diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index 12df45b..d3d6274 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -85,7 +85,7 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ /* @@ -128,10 +128,10 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_ENV_IS_IN_FLASH #else diff --git a/include/configs/palmld.h b/include/configs/palmld.h index 84bc9ed..a5b6e3a 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -116,7 +116,7 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ /* @@ -159,10 +159,10 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (25*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index 661101c..7303e1c 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -118,7 +118,7 @@ * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3686400 /* Timer @ 3686400 Hz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ /* @@ -156,10 +156,10 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index a09310c..c0048ac 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -69,7 +69,7 @@ #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ #define CONFIG_SYS_MEMTEST_END 0x08F00000 -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ #define CONFIG_BAUDRATE 115200 @@ -143,8 +143,8 @@ now.*/ #undef CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */ #define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 52a745e..904f3b0 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -139,7 +139,7 @@ unsigned char zipitz2_spi_read(void); * Clock Configuration */ #undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ /* @@ -186,10 +186,10 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 +#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 +#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 #define CONFIG_SYS_FLASH_PROTECTION /* -- cgit v0.10.2 From ce23b18bbb9531faf9a4526cc6c28a3e8e559847 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 17 Dec 2013 14:14:06 +0100 Subject: arm: omap3: Fix beagleboard SPL boot hangup (GPIO clocks not enabled) Patch f33b9bd3 [arm: omap3: Enable clocks for peripherals only if they are used] breaks SPL booting on Beagleboard. Since some gpio input's are read to detect the board revision. But with this patch above, the clocks to the GPIO subsystems are not enabled per default any more. The GPIO banks need to be configured specifically now. Signed-off-by: Stefan Roese Cc: Tom Rini Cc: Michael Trimarchi diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 3acb854..1b566c0 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -123,6 +123,9 @@ #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ /* commands to include */ #include -- cgit v0.10.2 From 7ca1b2a210daeb6782de9db11b7b1bec95624446 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:11 +0530 Subject: ARM: AM43xx: Update the base addresses of modules PRCM, timer base addresses and offsets are different from AM33xx. Updating the same. Signed-off-by: Lokesh Vutla diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 05752ce..19b8469 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -237,6 +237,14 @@ struct cm_perpll { unsigned int cpswclkstctrl; /* offset 0x144 */ unsigned int lcdcclkstctrl; /* offset 0x148 */ }; + +/* Encapsulating Display pll registers */ +struct cm_dpll { + unsigned int resv1[2]; + unsigned int clktimer2clk; /* offset 0x08 */ + unsigned int resv2[10]; + unsigned int clklcdcpixelclk; /* offset 0x34 */ +}; #else /* Encapsulating core pll registers */ struct cm_wkuppll { @@ -392,15 +400,12 @@ struct cm_perpll { unsigned int resv40[7]; unsigned int cpgmac0clkctrl; /* offset 0xB20 */ }; -#endif /* CONFIG_AM43XX */ -/* Encapsulating Display pll registers */ struct cm_dpll { - unsigned int resv1[2]; - unsigned int clktimer2clk; /* offset 0x08 */ - unsigned int resv2[10]; - unsigned int clklcdcpixelclk; /* offset 0x34 */ + unsigned int resv1; + unsigned int clktimer2clk; /* offset 0x04 */ }; +#endif /* CONFIG_AM43XX */ /* Control Module RTC registers */ struct cm_rtc { diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index ee5fce0..dd950e5 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -48,13 +48,6 @@ #define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_1_CFG_BASE 0x4D000000 -/* PLL related registers */ -#define CM_DPLL 0x44E00500 -#define CM_DEVICE 0x44E00700 -#define CM_RTC 0x44E00800 -#define CM_CEFUSE 0x44E00A00 -#define PRM_DEVICE 0x44E00F00 - /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index e4231c8..c67a080 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -30,6 +30,8 @@ #define PRCM_BASE 0x44E00000 #define CM_PER 0x44E00000 #define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800 #define PRM_RSTCTRL (PRCM_BASE + 0x0F00) #define PRM_RSTST (PRM_RSTCTRL + 8) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 3fb2479..0a3f8ee 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -30,6 +30,8 @@ #define PRCM_BASE 0x44DF0000 #define CM_WKUP 0x44DF2800 #define CM_PER 0x44DF8800 +#define CM_DPLL 0x44DF4200 +#define CM_RTC 0x44DF8500 #define PRM_RSTCTRL (PRCM_BASE + 0x4000) #define PRM_RSTST (PRM_RSTCTRL + 4) -- cgit v0.10.2 From 369cbe1e1ec6e2f0761438e7cef717a78b8905b1 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:12 +0530 Subject: ARM: AM43xx: Adapt to ti_armv7_common.h config file Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: Lokesh Vutla diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 2250721..cf5f8b2 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -26,6 +26,6 @@ #elif defined(CONFIG_AM43XX) #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 -#define SRAM_SCRATCH_SPACE_ADDR 0x4033C000 +#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 #endif #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 51b2576..dcd8cbb 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -44,7 +44,7 @@ void sdram_init(void) int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index d9b6c16..cad6979 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -10,127 +10,52 @@ #define __CONFIG_AM43XX_EVM_H #define CONFIG_AM43XX -#define CONFIG_OMAP -#define CONFIG_OMAP_COMMON -#include - -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) - -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "U-Boot# " -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* commands to include */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_VERSION_VARIABLE - -/* set to negative value for no autoboot */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_CMD_ECHO - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - - /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) -/* Platform/Board specific defs */ -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ - #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +#include /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ -4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_CONSOLE_INFO_QUIET - -#define CONFIG_ENV_IS_NOWHERE +/* SPL defines. */ +#define CONFIG_SPL_TEXT_BASE 0x40300350 +#define CONFIG_SPL_MAX_SIZE (0x40337C00 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_YMODEM_SUPPORT /* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. */ -#define CONFIG_SYS_TEXT_BASE 0x80800000 - -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) #define CONFIG_SKIP_LOWLEVEL_INIT #endif -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (101 * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +/* Now bring in the rest of the common code. */ +#include -#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_YMODEM_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SYS_SPL_MALLOC_START 0x80a08000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) -/* Unsupported features */ -#undef CONFIG_USE_IRQ +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ + +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_CMD_USB #define CONFIG_USB_HOST -- cgit v0.10.2 From 573b020ecb3cd5a2d3f47dc87e83486e3ad57d3d Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:13 +0530 Subject: ARM: AM43xx: Add L2 Support AM4372 uses PL310 L2 Cache. Enable the configs for the same. Signed-off-by: Lokesh Vutla diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index cad6979..833e5fa 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -30,6 +30,11 @@ #define CONFIG_SPL_MAX_SIZE (0x40337C00 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_YMODEM_SUPPORT +/* Enabling L2 Cache */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. -- cgit v0.10.2 From 1564dba7d919e27d9e9c43b3277dfc3da14701d3 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:14 +0530 Subject: ARM: AM43xx: Add extra ENV settings Add Extra env settings. This is derived from am335x Extra ENV settings. Signed-off-by: Lokesh Vutla diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 833e5fa..0f34078 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -72,4 +72,67 @@ #define CONFIG_OMAP_USB_PHY #define CONFIG_AM437X_USB2PHY2_HOST +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "fdt_high=0xffffffff\0" \ + "rdaddr=0x81000000\0" \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi;" \ + "fi;\0" \ + "findfdt="\ + "if test $board_name = AM43EPOS; then " \ + "setenv fdtfile am43x-epos-evm.dtb; fi; " \ + "if test $board_name = AM43__GP; then " \ + "setenv fdtfile am437x-gp-evm.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree; fi; \0" + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run mmcboot;" + +#endif #endif /* __CONFIG_AM43XX_EVM_H */ -- cgit v0.10.2 From 9f1a8cd33fec83c5e04c8d1103fb3ee2857ff2f0 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 10 Dec 2013 15:02:15 +0530 Subject: ARM: AM43XX: board: add support for reading onboard EEPROM Add support for reading onboard EEPROM to enable board detection. Signed-off-by: Sekhar Nori Signed-off-by: Lokesh Vutla diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index cf5f8b2..7a7d91b 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -27,5 +27,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 #define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 +#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR +#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC #endif #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index dcd8cbb..4fc1a40 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -9,6 +9,8 @@ */ #include +#include +#include #include #include #include @@ -17,6 +19,50 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(struct am43xx_board_id *header) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM at 0x%x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, + sizeof(struct am43xx_board_id))) { + printf("Could not read the EEPROM\n"); + return -EIO; + } + + if (header->magic != 0xEE3355AA) { + /* + * read the eeprom using i2c again, + * but use only a 1 byte address + */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct am43xx_board_id))) { + printf("Could not read the EEPROM at 0x%x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return -EIO; + } + + if (header->magic != 0xEE3355AA) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header->magic); + return -EINVAL; + } + } + + strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); + am43xx_board_name[sizeof(header->name)] = 0; + + return 0; +} + #ifdef CONFIG_SPL_BUILD const struct dpll_params dpll_ddr = { diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 8ca098b..9268895 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -12,6 +12,38 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#include + +static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; + +/* + * TI AM437x EVMs define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct am43xx_board_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +static inline int board_is_eposevm(void) +{ + return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN); +} + +static inline int board_is_gpevm(void) +{ + return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN); +} + void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); #endif diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 0f34078..4de495a 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -25,6 +25,13 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 +/* I2C Configuration */ +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + /* SPL defines. */ #define CONFIG_SPL_TEXT_BASE 0x40300350 #define CONFIG_SPL_MAX_SIZE (0x40337C00 - CONFIG_SPL_TEXT_BASE) -- cgit v0.10.2 From f4af163e6c8efbc768c2c0962c7823d6363e30fe Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 10 Dec 2013 15:02:16 +0530 Subject: ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the board. These variables are used by findfdt. Signed-off-by: Sekhar Nori Signed-off-by: Lokesh Vutla diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 4fc1a40..723d0ca 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -98,6 +98,22 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + char safe_string[HDR_NAME_LEN + 1]; + struct am43xx_board_id header; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + /* Now set variables based on the header. */ + strncpy(safe_string, (char *)header.name, sizeof(header.name)); + safe_string[sizeof(header.name)] = 0; + setenv("board_name", safe_string); + + strncpy(safe_string, (char *)header.version, sizeof(header.version)); + safe_string[sizeof(header.version)] = 0; + setenv("board_rev", safe_string); +#endif return 0; } #endif -- cgit v0.10.2 From 0d54cb924e0b6d3832fb1daa7d465e4648c57b7b Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:17 +0530 Subject: ARM: AM43xx: Select clk source for Timer2 Selecting the Master osc clk as Timer2 clock source. Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index c4890f2..22963b7 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -18,6 +18,7 @@ struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; const struct dpll_regs dpll_mpu_regs = { .cm_clkmode_dpll = CM_WKUP + 0x560, @@ -107,4 +108,7 @@ void enable_basic_clocks(void) }; do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + + /* Select the Master osc clk as Timer2 clock source */ + writel(0x1, &cmdpll->clktimer2clk); } -- cgit v0.10.2 From 1fb68b842e37ed6c0bec8567dc99cb66bd027484 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:18 +0530 Subject: ARM: AM43xx: Update Current Booting devices list Current Booting devices list is different from that of AM33xx. Updating the same. Signed-off-by: Lokesh Vutla diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 95de9aa..5cd1e95 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -13,11 +13,18 @@ #define BOOT_DEVICE_MMC1 6 #define BOOT_DEVICE_MMC2 5 #define BOOT_DEVICE_UART 0x43 -#define BOOT_DEVICE_MMC2_2 0xFF +#elif defined(CONFIG_AM43XX) +#define BOOT_DEVICE_NOR 1 +#define BOOT_DEVICE_NAND 5 +#define BOOT_DEVICE_MMC1 7 +#define BOOT_DEVICE_MMC2 8 +#define BOOT_DEVICE_SPI 10 +#define BOOT_DEVICE_UART 65 +#define BOOT_DEVICE_CPGMAC 71 #else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 -#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) +#if defined(CONFIG_AM33XX) #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #elif defined(CONFIG_TI814X) @@ -28,8 +35,8 @@ #define BOOT_DEVICE_UART 65 #define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 -#define BOOT_DEVICE_MMC2_2 0xFF #endif +#define BOOT_DEVICE_MMC2_2 0xFF #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -- cgit v0.10.2 From 4892495e368da9462cd5c1c0d6498fe95b45192e Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:19 +0530 Subject: ARM: AM43xx: mux: Update mux data Updating the mux data for UART, adding data for i2c0 and mmc. And also updating pad_signals structure. Signed-off-by: Lokesh Vutla diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index 0206912..98fc2b5 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -137,6 +137,51 @@ struct pad_signals { int mcasp0_fsr; int mcasp0_axr1; int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; }; #endif /* _MUX_AM43XX_H_ */ diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 700e9a7..46bad01 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -12,8 +12,24 @@ #include "board.h" static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */ - {OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */ + {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, {-1}, }; @@ -24,4 +40,6 @@ void enable_uart0_pin_mux(void) void enable_board_pin_mux(void) { + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); } -- cgit v0.10.2 From cf04d0326bd1e24909cfe644c0c8676440a915b1 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:20 +0530 Subject: ARM: AM43xx: clocks: Update DPLL details Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 8e5f3c6..0672798 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs, static void setup_dplls(void) { const struct dpll_params *params; - do_setup_dpll(&dpll_core_regs, &dpll_core); - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu); - do_setup_dpll(&dpll_per_regs, &dpll_per); + + params = get_dpll_core_params(); + do_setup_dpll(&dpll_core_regs, params); + + params = get_dpll_mpu_params(); + do_setup_dpll(&dpll_mpu_regs, params); + + params = get_dpll_per_params(); + do_setup_dpll(&dpll_per_regs, params); writel(0x300, &cmwkup->clkdcoldodpllper); params = get_dpll_ddr_params(); diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index fabe259..92142c8 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -62,6 +62,21 @@ const struct dpll_params dpll_core = { const struct dpll_params dpll_per = { 960, OSC-1, 5, -1, -1, -1, -1}; +const struct dpll_params *get_dpll_mpu_params(void) +{ + return &dpll_mpu; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + return &dpll_core; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + return &dpll_per; +} + void setup_clocks_for_console(void) { clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 22963b7..97c00b4 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -48,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = { .cm_idlest_dpll = CM_WKUP + 0x5A4, .cm_clksel_dpll = CM_WKUP + 0x5AC, .cm_div_m2_dpll = CM_WKUP + 0x5B0, + .cm_div_m4_dpll = CM_WKUP + 0x5B8, }; -const struct dpll_params dpll_mpu = { - -1, -1, -1, -1, -1, -1, -1}; -const struct dpll_params dpll_core = { - -1, -1, -1, -1, -1, -1, -1}; -const struct dpll_params dpll_per = { - -1, -1, -1, -1, -1, -1, -1}; - void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 519249e..7637457 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs; extern const struct dpll_regs dpll_core_regs; extern const struct dpll_regs dpll_per_regs; extern const struct dpll_regs dpll_ddr_regs; -extern const struct dpll_params dpll_mpu; -extern const struct dpll_params dpll_core; -extern const struct dpll_params dpll_per; -extern const struct dpll_params dpll_ddr; extern struct cm_wkuppll *const cmwkup; +const struct dpll_params *get_dpll_mpu_params(void); +const struct dpll_params *get_dpll_core_params(void); +const struct dpll_params *get_dpll_per_params(void); const struct dpll_params *get_dpll_ddr_params(void); void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); void prcm_init(void); diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 19b8469..3ee37dc 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -480,6 +480,8 @@ struct ctrl_stat { unsigned int statusreg; /* ofset 0x40 */ unsigned int resv2[51]; unsigned int secure_emif_sdram_config; /* offset 0x0110 */ + unsigned int resv3[319]; + unsigned int dev_attr; }; /* AM33XX GPIO registers */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 0a3f8ee..468521b 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -63,4 +63,17 @@ #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) #define USBPHYOCPSCP_MODULE_EN (1 << 1) +/* Control status register */ +#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) +#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 +#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) +#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 +#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) +#define CTRL_SYSBOOT_15_14_SHIFT 22 + +#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 +#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 + +#define NUM_CRYSTAL_FREQ 0x4 + #endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 723d0ca..5c92ac7 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -65,12 +65,144 @@ static int read_eeprom(struct am43xx_board_id *header) #ifdef CONFIG_SPL_BUILD -const struct dpll_params dpll_ddr = { - -1, -1, -1, -1, -1, -1, -1}; +#define NUM_OPPS 6 + +const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { + { /* 19.2 MHz */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */ + {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 24 MHz */ + {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 25 MHz */ + {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 26 MHz */ + {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ + }, +}; + +const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { + {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ + {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ + {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ +}; + +const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { + {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */ + {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */ + {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params epos_evm_dpll_ddr = { + 266, 24, 1, -1, 1, -1, -1}; + +const struct dpll_params gp_evm_dpll_ddr = { + 400, 23, 1, -1, 1, -1, -1}; const struct dpll_params *get_dpll_ddr_params(void) { - return &dpll_ddr; + struct am43xx_board_id header; + + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); + + if (board_is_eposevm()) + return &epos_evm_dpll_ddr; + else if (board_is_gpevm()) + return &gp_evm_dpll_ddr; + + puts(" Board not supported\n"); + return NULL; +} + +/* + * get_sys_clk_index : returns the index of the sys_clk read from + * ctrl status register. This value is either + * read from efuse or sysboot pins. + */ +static u32 get_sys_clk_index(void) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + u32 ind = readl(&ctrl->statusreg), src; + + src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; + if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ + return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> + CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); + else /* Value read from SYS BOOT pins */ + return ((ind & CTRL_SYSBOOT_15_14_MASK) >> + CTRL_SYSBOOT_15_14_SHIFT); +} + +/* + * get_opp_offset: + * Returns the index for safest OPP of the device to boot. + * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. + * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. + * This data is read from dev_attribute register which is e-fused. + * A'1' in bit indicates OPP disabled and not available, a '0' indicates + * OPP available. Lowest OPP starts with min_off. So returning the + * bit with rightmost '0'. + */ +static int get_opp_offset(int max_off, int min_off) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + int opp = readl(&ctrl->dev_attr), offset, i; + + for (i = max_off; i >= min_off; i--) { + offset = opp & (1 << i); + if (!offset) + return i; + } + + return min_off; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); + u32 ind = get_sys_clk_index(); + + return &dpll_mpu[ind][opp]; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_core[ind]; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_per[ind]; } void set_uart_mux_conf(void) diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 9268895..091162e 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -25,6 +25,9 @@ static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; #define HDR_ETH_ALEN 6 #define HDR_NAME_LEN 8 +#define DEV_ATTR_MAX_OFFSET 5 +#define DEV_ATTR_MIN_OFFSET 0 + struct am43xx_board_id { unsigned int magic; char name[HDR_NAME_LEN]; @@ -46,4 +49,5 @@ static inline int board_is_gpevm(void) void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); #endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 46bad01..a2d72dd 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -43,3 +43,8 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); } + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} -- cgit v0.10.2 From 965de8b91bddd1f5967240d1d44005719b09dd5e Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:21 +0530 Subject: ARM: AM33xx+: Update ioregs to pass different values Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 5b0454c..255f333 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -88,6 +88,9 @@ void config_ddr_phy(const struct emif_regs *regs, int nr) */ void config_cmd_ctrl(const struct cmd_control *cmd, int nr) { + if (!cmd) + return; + writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); @@ -105,6 +108,9 @@ void config_ddr_data(const struct ddr_data *data, int nr) { int i; + if (!data) + return; + for (i = 0; i < DDR_DATA_REGS_NR; i++) { writel(data->datardsratio0, &(ddr_data_reg[nr]+i)->dt0rdsratio0); @@ -121,11 +127,20 @@ void config_ddr_data(const struct ddr_data *data, int nr) } } -void config_io_ctrl(unsigned long val) +void config_io_ctrl(const struct ctrl_ioregs *ioregs) { - writel(val, &ioctrl_reg->cm0ioctl); - writel(val, &ioctrl_reg->cm1ioctl); - writel(val, &ioctrl_reg->cm2ioctl); - writel(val, &ioctrl_reg->dt0ioctl); - writel(val, &ioctrl_reg->dt1ioctl); + if (!ioregs) + return; + + writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl); + writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl); + writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl); + writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl); + writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl); +#ifdef CONFIG_AM43XX + writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl); + writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl); + writel(ioregs->emif_sdram_config_ext, + &ioctrl_reg->emif_sdram_config_ext); +#endif } diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 59ad25c..adda650 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -87,7 +87,7 @@ void __weak ddr_pll_config(unsigned int ddrpll_m) { } -void config_ddr(unsigned int pll, unsigned int ioctrl, +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) { @@ -99,12 +99,11 @@ void config_ddr(unsigned int pll, unsigned int ioctrl, config_ddr_data(data, nr); #ifdef CONFIG_AM33XX - config_io_ctrl(ioctrl); + config_io_ctrl(ioregs); /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); #endif - /* Program EMIF instance */ config_ddr_phy(regs, nr); set_sdram_timings(regs, nr); diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c index 99f3a86..b3b150a 100644 --- a/board/compulab/cm_t335/spl.c +++ b/board/compulab/cm_t335/spl.c @@ -20,6 +20,14 @@ #include #include +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, +}; + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J128MJT125_RD_DQS, .datawdsratio0 = MT41J128MJT125_WR_DQS, @@ -89,7 +97,7 @@ static void probe_sdram_size(long size) reset_cpu(0); } debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); - config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, + config_ddr(303, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 6a8ca2b..089a835 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -77,9 +77,17 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } +const struct ctrl_ioregs ioregs = { + .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, +}; + void sdram_init(void) { - config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data, + config_ddr(400, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } #endif diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 68463e7..7e5e07f 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -50,6 +50,14 @@ const struct dpll_params *get_dpll_ddr_params(void) } #ifdef CONFIG_REV1 +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, + .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, +}; + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J256M8HX15E_RD_DQS, .datawdsratio0 = MT41J256M8HX15E_WR_DQS, @@ -81,10 +89,18 @@ static struct emif_regs ddr3_emif_reg_data = { void sdram_init(void) { - config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, + config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } #else +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, .datawdsratio0 = MT41K256M16HA125E_WR_DQS, @@ -116,7 +132,7 @@ static struct emif_regs ddr3_emif_reg_data = { void sdram_init(void) { - config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data, + config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } #endif diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 3a5e11d..6c316fa 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -144,6 +144,10 @@ struct ddr_data dxr2_ddr3_data = { struct cmd_control dxr2_ddr3_cmd_ctrl_data = { }; + +struct ctrl_ioregs dxr2_ddr3_ioregs = { +}; + /* pass values from eeprom */ dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; @@ -165,7 +169,13 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = { dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; - config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data, + dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, + + config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data, &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0); } diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 0a25b4b..ef3d6cc 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -69,7 +69,15 @@ struct cmd_control pxm2_ddr3_cmd_ctrl_data = { .cmd2iclkout = 0, }; - config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data, +const struct ctrl_ioregs ioregs = { + .cm0ioctl = DXR2_IOCTRL_VAL, + .cm1ioctl = DXR2_IOCTRL_VAL, + .cm2ioctl = DXR2_IOCTRL_VAL, + .dt0ioctl = DXR2_IOCTRL_VAL, + .dt1ioctl = DXR2_IOCTRL_VAL, +}; + + config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data, &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0); } diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index 77592db..25ab54d 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -74,7 +74,15 @@ struct cmd_control rut_ddr3_cmd_ctrl_data = { .cmd2iclkout = 1, }; - config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data, +const struct ctrl_ioregs ioregs = { + .cm0ioctl = RUT_IOCTRL_VAL, + .cm1ioctl = RUT_IOCTRL_VAL, + .cm2ioctl = RUT_IOCTRL_VAL, + .dt0ioctl = RUT_IOCTRL_VAL, + .dt1ioctl = RUT_IOCTRL_VAL, +}; + + config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data, &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0); } diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 33693e4..5721768 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -426,6 +426,38 @@ void set_mux_conf_regs(void) enable_board_pin_mux(&header); } +const struct ctrl_ioregs ioregs_evmsk = { + .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_bonelt = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_evm15 = { + .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + void sdram_init(void) { __maybe_unused struct am335x_baseboard_id header; @@ -443,18 +475,18 @@ void sdram_init(void) } if (board_is_evm_sk(&header)) - config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, + config_ddr(303, &ioregs_evmsk, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); else if (board_is_bone_lt(&header)) - config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, + config_ddr(400, &ioregs_bonelt, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data, 0); else if (board_is_evm_15_or_later(&header)) - config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, + config_ddr(303, &ioregs_evm15, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); else - config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, + config_ddr(266, &ioregs, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); } #endif diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 0b76a77..140ad71 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -95,9 +95,9 @@ void sdram_init(void) { config_dmm(&evm_lisa_map_regs); - config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, + config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif0_regs, 0); - config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, + config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif1_regs, 1); } #endif diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index a53859e..b6bf162 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -191,22 +191,26 @@ void sdram_init(void) if (CONFIG_TI816X_USE_EMIF0) { ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); - config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0); + config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, + 0); } if (CONFIG_TI816X_USE_EMIF1) { ddr2_emif1_regs.emif_ddr_phy_ctlr_1 = (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); - config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1); + config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, + 1); } #endif #ifdef CONFIG_TI816X_EVM_DDR3 if (CONFIG_TI816X_USE_EMIF0) - config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0); + config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, + 0); if (CONFIG_TI816X_USE_EMIF1) - config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1); + config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, + 1); #endif } #endif /* CONFIG_SPL_BUILD */ -- cgit v0.10.2 From d3daba10f159cca7e9d24c6f154926a9b92c75e3 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:22 +0530 Subject: ARM: AM43xx: EPOS_EVM: Add support for LPDDR2 AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 255f333..1abbb07 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -36,6 +36,71 @@ static struct ddr_data_regs *ddr_data_reg[2] = { static struct ddr_cmdtctrl *ioctrl_reg = { (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; +static inline u32 get_mr(int nr, u32 cs, u32 mr_addr) +{ + u32 mr; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); + + mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); + debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr); + if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && + ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && + ((mr & 0xff000000) >> 24) == (mr & 0xff)) + return mr & 0xff; + else + return mr; +} + +static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val) +{ + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data); +} + +static void configure_mr(int nr, u32 cs) +{ + u32 mr_addr; + + while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) + ; + set_mr(nr, cs, LPDDR2_MR10, 0x56); + + set_mr(nr, cs, LPDDR2_MR1, 0x43); + set_mr(nr, cs, LPDDR2_MR2, 0x2); + + mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; + set_mr(nr, cs, mr_addr, 0x2); +} + +/* + * Configure EMIF4D5 registers and MR registers + */ +void config_sdram_emif4d5(const struct emif_regs *regs, int nr) +{ + writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); + writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); + writel(0x1, &emif_reg[nr]->emif_iodft_tlgc); + writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); + + writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config); + writel(regs->emif_rd_wr_lvl_rmp_win, + &emif_reg[nr]->emif_rd_wr_lvl_rmp_win); + writel(regs->emif_rd_wr_lvl_rmp_ctl, + &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); + writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + writel(regs->emif_rd_wr_exec_thresh, + &emif_reg[nr]->emif_rd_wr_exec_thresh); + + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + + configure_mr(nr, 0); + configure_mr(nr, 1); +} + /** * Configure SDRAM */ @@ -72,15 +137,67 @@ void set_sdram_timings(const struct emif_regs *regs, int nr) writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); } +void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ +} + +/* + * Configure EXT PHY registers + */ +static void ext_phy_settings(const struct emif_regs *regs, int nr) +{ + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + const u32 *ext_phy_ctrl_const_regs; + u32 i = 0; + u32 size; + + ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = + (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size); + + if (!size) + return; + + for (i = 0; i < size; i++) { + writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); + } +} + /** * Configure DDR PHY */ void config_ddr_phy(const struct emif_regs *regs, int nr) { + /* + * disable initialization and refreshes for now until we + * finish programming EMIF regs. + */ + setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, + EMIF_REG_INITREF_DIS_MASK); + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); + + if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) + ext_phy_settings(regs, nr); } /** diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index adda650..d28fceb 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -48,6 +48,11 @@ static struct vtp_reg *vtpreg[2] = { #ifdef CONFIG_AM33XX static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; #endif +#ifdef CONFIG_AM43XX +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; +static struct cm_device_inst *cm_device = + (struct cm_device_inst *)CM_DEVICE_INST; +#endif #ifdef CONFIG_TI81XX void config_dmm(const struct dmm_lisa_map_regs *regs) @@ -104,9 +109,24 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); #endif +#ifdef CONFIG_AM43XX + writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); + while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0) + ; + writel(0x0, &ddrctrl->ddrioctrl); + + config_io_ctrl(ioregs); + + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); +#endif + /* Program EMIF instance */ config_ddr_phy(regs, nr); set_sdram_timings(regs, nr); - config_sdram(regs, nr); + if (get_emif_rev(EMIF1_BASE) == EMIF_4D5) + config_sdram_emif4d5(regs, nr); + else + config_sdram(regs, nr); } #endif diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 02ed595..4c9352a 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -28,6 +28,9 @@ #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3) +#define CM_DLL_CTRL_NO_OVERRIDE 0x0 +#define CM_DLL_READYST 0x4 + extern void enable_dmm_clocks(void); extern const struct dpll_params dpll_core_opp100; extern struct dpll_params dpll_mpu_opp100; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 3ee37dc..9febfa2 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -401,6 +401,11 @@ struct cm_perpll { unsigned int cpgmac0clkctrl; /* offset 0xB20 */ }; +struct cm_device_inst { + unsigned int cm_clkout1_ctrl; + unsigned int cm_dll_ctrl; +}; + struct cm_dpll { unsigned int resv1; unsigned int clktimer2clk; /* offset 0x04 */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 2278358..6af4b84 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -18,7 +18,11 @@ #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) #define VTP_CTRL_START_EN (0x1) +#ifdef CONFIG_AM43XX +#define DDR_CKE_CTRL_NORMAL 0x3 +#else #define DDR_CKE_CTRL_NORMAL 0x1 +#endif #define PHY_EN_DYN_PWRDN (0x1 << 20) /* Micron MT47H128M16RT-25E */ @@ -124,6 +128,14 @@ #define K4B2G1646EBIH9_PHY_WR_DATA 0x76 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B +#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 +#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 + /** * Configure DMM */ @@ -133,6 +145,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs); * Configure SDRAM */ void config_sdram(const struct emif_regs *regs, int nr); +void config_sdram_emif4d5(const struct emif_regs *regs, int nr); /** * Set SDRAM timings @@ -278,12 +291,27 @@ struct ddr_cmdtctrl { unsigned int resv2[12]; unsigned int dt0ioctl; unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int resv3[4]; + unsigned int emif_sdram_config_ext; +}; + +struct ctrl_ioregs { + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int dt0ioctl; + unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int emif_sdram_config_ext; }; /** * Configure DDR io control registers */ -void config_io_ctrl(unsigned long val); +void config_io_ctrl(const struct ctrl_ioregs *ioregs); struct ddr_ctrl { unsigned int ddrioctrl; @@ -291,8 +319,9 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; -void config_ddr(unsigned int pll, unsigned int ioctrl, +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr); +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 468521b..15399dc 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -62,6 +62,7 @@ #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) #define USBPHYOCPSCP_MODULE_EN (1 << 1) +#define CM_DEVICE_INST 0x44df4100 /* Control status register */ #define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index d9d521a..e68c113 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -14,11 +14,15 @@ #define _EMIF_H_ #include #include +#include /* Base address */ #define EMIF1_BASE 0x4c000000 #define EMIF2_BASE 0x4d000000 +#define EMIF_4D 0x4 +#define EMIF_4D5 0x5 + /* Registers shifts, masks and values */ /* EMIF_MOD_ID_REV */ @@ -1148,6 +1152,14 @@ struct read_write_regs { u32 write_reg; }; +static inline u32 get_emif_rev(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK) + >> EMIF_REG_MAJOR_REVISION_SHIFT; +} + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) for (;;); }) diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 5c92ac7..5a013e3 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -122,6 +124,69 @@ const struct dpll_params epos_evm_dpll_ddr = { const struct dpll_params gp_evm_dpll_ddr = { 400, 23, 1, -1, 1, -1, -1}; +const struct ctrl_ioregs ioregs_lpddr2 = { + .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x1, +}; + +const struct emif_regs emif_regs_lpddr2 = { + .sdram_config = 0x808012BA, + .ref_ctrl = 0x0000040D, + .sdram_tim1 = 0xEA86B411, + .sdram_tim2 = 0x103A094A, + .sdram_tim3 = 0x0F6BA37F, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E084006, + .emif_rd_wr_exec_thresh = 0x00000405, + .emif_ddr_ext_phy_ctrl_1 = 0x04010040, + .emif_ddr_ext_phy_ctrl_2 = 0x00500050, + .emif_ddr_ext_phy_ctrl_3 = 0x00500050, + .emif_ddr_ext_phy_ctrl_4 = 0x00500050, + .emif_ddr_ext_phy_ctrl_5 = 0x00500050 +}; + +const u32 ext_phy_ctrl_const_base_lpddr2[] = { + 0x00500050, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40001000, + 0x08102040 +}; + +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + *regs = ext_phy_ctrl_const_base_lpddr2; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + + return; +} + const struct dpll_params *get_dpll_ddr_params(void) { struct am43xx_board_id header; @@ -217,6 +282,7 @@ void set_mux_conf_regs(void) void sdram_init(void) { + config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); } #endif -- cgit v0.10.2 From b5e01eecc89e3e5c2ed3c17b803529be3c3702fb Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:23 +0530 Subject: ARM: AM43xx: GP_EVM: Add support for DDR3 GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 1abbb07..d05e666 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -97,8 +97,10 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); - configure_mr(nr, 0); - configure_mr(nr, 1); + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) { + configure_mr(nr, 0); + configure_mr(nr, 1); + } } /** diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 5a3f285..cd6289b 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -50,20 +50,6 @@ inline u32 emif_num(u32 base) return 0; } -/* - * Get SDRAM type connected to EMIF. - * Assuming similar SDRAM parts are connected to both EMIF's - * which is typically the case. So it is sufficient to get - * SDRAM type from EMIF1. - */ -u32 emif_sdram_type() -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - - return (readl(&emif->emif_sdram_config) & - EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; -} - static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) { u32 mr; diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 6af4b84..c1777df 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -136,6 +136,14 @@ #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 +#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84 + /** * Configure DMM */ diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h index 13a047f..a1ffd49 100644 --- a/arch/arm/include/asm/arch-am33xx/gpio.h +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -13,4 +13,16 @@ #define AM33XX_GPIO2_BASE 0x481AC000 #define AM33XX_GPIO3_BASE 0x481AE000 +#define GPIO_22 22 + +/* GPIO CTRL register */ +#define GPIO_CTRL_DISABLEMODULE_SHIFT 0 +#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0) +#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK + +/* GPIO OUTPUT ENABLE register */ +#define GPIO_OE_ENABLE(x) (1 << x) + +/* GPIO SETDATAOUT register */ +#define GPIO_SETDATAOUT(x) (1 << x) #endif /* _GPIO_AM33xx_H */ diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index e68c113..45668ca 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1160,6 +1160,20 @@ static inline u32 get_emif_rev(u32 base) >> EMIF_REG_MAJOR_REVISION_SHIFT; } +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +static inline u32 emif_sdram_type(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + return (readl(&emif->emif_sdram_config) & + EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; +} + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) for (;;); }) diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 5a013e3..ed87cd9 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "board.h" @@ -179,10 +180,70 @@ const u32 ext_phy_ctrl_const_base_lpddr2[] = { 0x08102040 }; +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x0043, +}; + +const struct emif_regs ddr3_emif_regs_400Mhz = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E084008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00400040, + .emif_ddr_ext_phy_ctrl_3 = 0x00400040, + .emif_ddr_ext_phy_ctrl_4 = 0x00400040, + .emif_ddr_ext_phy_ctrl_5 = 0x00400040, + .emif_rd_wr_lvl_rmp_win = 0x0, + .emif_rd_wr_lvl_rmp_ctl = 0x0, + .emif_rd_wr_lvl_ctl = 0x0, + .emif_rd_wr_exec_thresh = 0x00000405 +}; + +const u32 ext_phy_ctrl_const_base_ddr3[] = { + 0x00400040, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00340034, + 0x00340034, + 0x00340034, + 0x00340034, + 0x00340034, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { - *regs = ext_phy_ctrl_const_base_lpddr2; - *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + if (board_is_eposevm()) { + *regs = ext_phy_ctrl_const_base_lpddr2; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } else if (board_is_gpevm()) { + *regs = ext_phy_ctrl_const_base_ddr3; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); + } return; } @@ -280,9 +341,35 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } +static void enable_vtt_regulator(void) +{ + u32 temp; + + /* enable module */ + writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL); + + /* enable output for GPIO0_22 */ + writel(GPIO_SETDATAOUT(GPIO_22), + AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT); + temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE); + temp = temp & ~(GPIO_OE_ENABLE(GPIO_22)); + writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE); +} + void sdram_init(void) { - config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); + /* + * EPOS EVM has 1GB LPDDR2 connected to EMIF. + * GP EMV has 1GB DDR3 connected to EMIF + * along with VTT regulator. + */ + if (board_is_eposevm()) { + config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); + } else if (board_is_gpevm()) { + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400Mhz, 0); + } } #endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index a2d72dd..810b194 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -33,6 +33,11 @@ static struct module_pin_mux i2c0_pin_mux[] = { {-1}, }; +static struct module_pin_mux gpio0_22_pin_mux[] = { + {OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */ + {-1}, +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -42,6 +47,9 @@ void enable_board_pin_mux(void) { configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); + + if (board_is_gpevm()) + configure_module_pin_mux(gpio0_22_pin_mux); } void enable_i2c0_pin_mux(void) -- cgit v0.10.2 From 2931fa4db349c97f882ffda42e901208654b5ca9 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:24 +0530 Subject: ARM: AM43xx: Add Maintainer Adding Maintainer for AM43xx. Signed-off-by: Lokesh Vutla diff --git a/boards.cfg b/boards.cfg index 152d85e..d85d4dd 100644 --- a/boards.cfg +++ b/boards.cfg @@ -266,7 +266,7 @@ Active arm armv7 am33xx ti am335x Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini -Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 - +Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter Active arm armv7 am33xx ti ti816x ti816x_evm - - Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen -- cgit v0.10.2 From f5514e47c4086d342e81219bb9cbd8956961fa0e Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 19 Dec 2013 11:04:33 +0100 Subject: MX6: fix sata compilation for i.MX6 Commit 164d98466103a46b7c881149e92ec2a28a6375be breaks board with SATA support, because sata is not compiled. Signed-off-by: Stefano Babic diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 68f0f52..ee5c872 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -18,7 +18,7 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mxs)) obj-y += misc.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) -objs-$(CONFIG_CMD_SATA) += sata.o +obj-$(CONFIG_CMD_SATA) += sata.o endif obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c index 1b4c502..2e69486 100644 --- a/arch/arm/imx-common/sata.c +++ b/arch/arm/imx-common/sata.c @@ -7,6 +7,7 @@ #include #include #include +#include int setup_sata(void) { -- cgit v0.10.2 From 71ebb33559696ca41fe0db5fa882112464ade9c0 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:17 +0530 Subject: EXYNOS5: Create a common board file Create a common board.c file for all functions which are common across all EXYNOS5 platforms. exynos_init function is provided for platform specific code. Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/include/asm/arch-exynos/board.h b/arch/arm/include/asm/arch-exynos/board.h new file mode 100644 index 0000000..243fb12 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/board.h @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2013 Samsung Electronics + * Rajeshwari Shinde + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EXYNOS_BOARD_H +#define _EXYNOS_BOARD_H + +/* + * Exynos baord specific changes for + * board_init + */ +int exynos_init(void); + +#endif /* EXYNOS_BOARD_H */ diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 501d974..22bd6b1 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -8,3 +8,7 @@ obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o obj-$(CONFIG_THOR_FUNCTION) += thor.o obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o + +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_BOARD_COMMON) += board.o +endif diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c new file mode 100644 index 0000000..dc68e3a --- /dev/null +++ b/board/samsung/common/board.c @@ -0,0 +1,409 @@ +/* + * (C) Copyright 2013 SAMSUNG Electronics + * Rajeshwari Shinde + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct local_info { + struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ + int cros_ec_err; /* Error for cros_ec, 0 if ok */ +}; + +static struct local_info local; + +#if defined CONFIG_EXYNOS_TMU +/* Boot Time Thermal Analysis for SoC temperature threshold breach */ +static void boot_temp_check(void) +{ + int temp; + + switch (tmu_monitor(&temp)) { + case TMU_STATUS_NORMAL: + break; + case TMU_STATUS_TRIPPED: + /* + * Status TRIPPED ans WARNING means corresponding threshold + * breach + */ + puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); + set_ps_hold_ctrl(); + hang(); + break; + case TMU_STATUS_WARNING: + puts("EXYNOS_TMU: WARNING! Temperature very high\n"); + break; + case TMU_STATUS_INIT: + /* + * TMU_STATUS_INIT means something is wrong with temperature + * sensing and TMU status was changed back from NORMAL to INIT. + */ + puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); + break; + default: + debug("EXYNOS_TMU: Unknown TMU state\n"); + } +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); +#if defined CONFIG_EXYNOS_TMU + if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { + debug("%s: Failed to init TMU\n", __func__); + return -1; + } + boot_temp_check(); +#endif + +#ifdef CONFIG_EXYNOS_SPI + spi_init(); +#endif + return exynos_init(); +} + +int dram_init(void) +{ + int i; + u32 addr; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); + } + return 0; +} + +void dram_init_banksize(void) +{ + int i; + u32 addr, size; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); + + gd->bd->bi_dram[i].start = addr; + gd->bd->bi_dram[i].size = size; + } +} + +static int board_uart_init(void) +{ + int err, uart_id, ret = 0; + + for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { + err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); + if (err) { + debug("UART%d not configured\n", + (uart_id - PERIPH_ID_UART0)); + ret |= err; + } + } + return ret; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int err; + + err = board_uart_init(); + if (err) { + debug("UART init failed\n"); + return err; + } + +#ifdef CONFIG_SYS_I2C_INIT_BOARD + board_i2c_init(gd->fdt_blob); +#endif + + return err; +} +#endif + +struct cros_ec_dev *board_get_cros_ec_dev(void) +{ + return local.cros_ec_dev; +} + +static int board_init_cros_ec_devices(const void *blob) +{ + local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); + if (local.cros_ec_err) + return -1; /* Will report in board_late_init() */ + + return 0; +} + +#if defined(CONFIG_POWER) +#ifdef CONFIG_POWER_MAX77686 +static int pmic_reg_update(struct pmic *p, int reg, uint regval) +{ + u32 val; + int ret = 0; + + ret = pmic_reg_read(p, reg, &val); + if (ret) { + debug("%s: PMIC %d register read failed\n", __func__, reg); + return -1; + } + val |= regval; + ret = pmic_reg_write(p, reg, val); + if (ret) { + debug("%s: PMIC %d register write failed\n", __func__, reg); + return -1; + } + return 0; +} + +static int max77686_init(void) +{ + struct pmic *p; + + if (pmic_init(I2C_PMIC)) + return -1; + + p = pmic_get("MAX77686_PMIC"); + if (!p) + return -ENODEV; + + if (pmic_probe(p)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, + MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) + return -1; + + /* VDD_MIF */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, + MAX77686_BUCK1OUT_1V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK1OUT); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, + MAX77686_BUCK1CTRL_EN)) + return -1; + + /* VDD_ARM */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, + MAX77686_BUCK2DVS1_1_3V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK2DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, + MAX77686_BUCK2CTRL_ON)) + return -1; + + /* VDD_INT */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, + MAX77686_BUCK3DVS1_1_0125V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK3DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_G3D */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, + MAX77686_BUCK4DVS1_1_2V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK4DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_LDO2 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, + MAX77686_LD02CTRL1_1_5V | EN_LDO)) + return -1; + + /* VDD_LDO3 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, + MAX77686_LD03CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO5 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, + MAX77686_LD05CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO10 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, + MAX77686_LD10CTRL1_1_8V | EN_LDO)) + return -1; + + return 0; +} +#endif + +int power_init_board(void) +{ + int ret = 0; + + set_ps_hold_ctrl(); + +#ifdef CONFIG_POWER_MAX77686 + ret = max77686_init(); +#endif + + return ret; +} +#endif + +#ifdef CONFIG_OF_CONTROL +static int decode_sromc(const void *blob, struct fdt_sromc *config) +{ + int err; + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); + if (node < 0) { + debug("Could not find SROMC node\n"); + return node; + } + + config->bank = fdtdec_get_int(blob, node, "bank", 0); + config->width = fdtdec_get_int(blob, node, "width", 2); + + err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, + FDT_SROM_TIMING_COUNT); + if (err < 0) { + debug("Could not decode SROMC configuration Error: %s\n", + fdt_strerror(err)); + return -FDT_ERR_NOTFOUND; + } + return 0; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SMC911X + u32 smc_bw_conf, smc_bc_conf; + struct fdt_sromc config; + fdt_addr_t base_addr; + int node; + + node = decode_sromc(gd->fdt_blob, &config); + if (node < 0) { + debug("%s: Could not find sromc configuration\n", __func__); + return 0; + } + node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); + if (node < 0) { + debug("%s: Could not find lan9215 configuration\n", __func__); + return 0; + } + + /* We now have a node, so any problems from now on are errors */ + base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); + if (base_addr == FDT_ADDR_T_NONE) { + debug("%s: Could not find lan9215 address\n", __func__); + return -1; + } + + /* Ethernet needs data bus width of 16 bits */ + if (config.width != 2) { + debug("%s: Unsupported bus width %d\n", __func__, + config.width); + return -1; + } + smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) + | SROMC_BYTE_ENABLE(config.bank); + + smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | + SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | + SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | + SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | + SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | + SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | + SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); + + /* Select and configure the SROMC bank */ + exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); + s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); + return smc911x_initialize(0, base_addr); +#endif + return 0; +} + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* dwmmc initializattion for available channels */ + ret = exynos_dwmmc_init(gd->fdt_blob); + if (ret) + debug("dwmmc init failed\n"); + + return ret; +} +#endif +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + stdio_print_current_devices(); + + if (local.cros_ec_err) { + /* Force console on */ + gd->flags &= ~GD_FLG_SILENT; + + printf("cros-ec communications failure %d\n", + local.cros_ec_err); + puts("\nPlease reset with Power+Refresh\n\n"); + panic("Cannot init cros-ec device"); + return -1; + } + return 0; +} +#endif + +int arch_early_init_r(void) +{ +#ifdef CONFIG_CROS_EC + if (board_init_cros_ec_devices(gd->fdt_blob)) { + printf("%s: Failed to init EC\n", __func__); + return 0; + } +#endif + + return 0; +} diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index 6aa0509..5fb8664 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -25,44 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined CONFIG_EXYNOS_TMU -/* - * Boot Time Thermal Analysis for SoC temperature threshold breach - */ -static void boot_temp_check(void) -{ - int temp; - - switch (tmu_monitor(&temp)) { - /* Status TRIPPED ans WARNING means corresponding threshold breach */ - case TMU_STATUS_TRIPPED: - puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); - set_ps_hold_ctrl(); - hang(); - break; - case TMU_STATUS_WARNING: - puts("EXYNOS_TMU: WARNING! Temperature very high\n"); - break; - /* - * TMU_STATUS_INIT means something is wrong with temperature sensing - * and TMU status was changed back from NORMAL to INIT. - */ - case TMU_STATUS_INIT: - default: - debug("EXYNOS_TMU: Unknown TMU state\n"); - } -} -#endif - -struct local_info { - struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ - int cros_ec_err; /* Error for cros_ec, 0 if ok */ -}; - -static struct local_info local; - #ifdef CONFIG_SOUND_MAX98095 -static void board_enable_audio_codec(void) +static void board_enable_audio_codec(void) { struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); @@ -73,261 +37,14 @@ static void board_enable_audio_codec(void) } #endif -struct cros_ec_dev *board_get_cros_ec_dev(void) -{ - return local.cros_ec_dev; -} - -static int board_init_cros_ec_devices(const void *blob) +int exynos_init(void) { - local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); - if (local.cros_ec_err) - return -1; /* Will report in board_late_init() */ - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); - -#if defined CONFIG_EXYNOS_TMU - if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { - debug("%s: Failed to init TMU\n", __func__); - return -1; - } - boot_temp_check(); -#endif - -#ifdef CONFIG_EXYNOS_SPI - spi_init(); -#endif - - if (board_init_cros_ec_devices(gd->fdt_blob)) - return -1; - #ifdef CONFIG_SOUND_MAX98095 board_enable_audio_codec(); #endif return 0; } -int dram_init(void) -{ - int i; - u32 addr; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); - } - return 0; -} - -#if defined(CONFIG_POWER) -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -int power_init_board(void) -{ - struct pmic *p; - - set_ps_hold_ctrl(); - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif - -void dram_init_banksize(void) -{ - int i; - u32 addr, size; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; - } -} - -static int decode_sromc(const void *blob, struct fdt_sromc *config) -{ - int err; - int node; - - node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); - if (node < 0) { - debug("Could not find SROMC node\n"); - return node; - } - - config->bank = fdtdec_get_int(blob, node, "bank", 0); - config->width = fdtdec_get_int(blob, node, "width", 2); - - err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, - FDT_SROM_TIMING_COUNT); - if (err < 0) { - debug("Could not decode SROMC configuration Error: %s\n", - fdt_strerror(err)); - return -FDT_ERR_NOTFOUND; - } - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SMC911X - u32 smc_bw_conf, smc_bc_conf; - struct fdt_sromc config; - fdt_addr_t base_addr; - int node; - - node = decode_sromc(gd->fdt_blob, &config); - if (node < 0) { - debug("%s: Could not find sromc configuration\n", __func__); - return 0; - } - node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); - if (node < 0) { - debug("%s: Could not find lan9215 configuration\n", __func__); - return 0; - } - - /* We now have a node, so any problems from now on are errors */ - base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); - if (base_addr == FDT_ADDR_T_NONE) { - debug("%s: Could not find lan9215 address\n", __func__); - return -1; - } - - /* Ethernet needs data bus width of 16 bits */ - if (config.width != 2) { - debug("%s: Unsupported bus width %d\n", __func__, - config.width); - return -1; - } - smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) - | SROMC_BYTE_ENABLE(config.bank); - - smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | - SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | - SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | - SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | - SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | - SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | - SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); - - /* Select and configure the SROMC bank */ - exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); - s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); - return smc911x_initialize(0, base_addr); -#endif - return 0; -} - #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { @@ -343,50 +60,6 @@ int checkboard(void) } #endif -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int ret; - /* dwmmc initializattion for available channels */ - ret = exynos_dwmmc_init(gd->fdt_blob); - if (ret) - debug("dwmmc init failed\n"); - - return ret; -} -#endif - -static int board_uart_init(void) -{ - int err, uart_id, ret = 0; - - for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { - err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); - if (err) { - debug("UART%d not configured\n", - (uart_id - PERIPH_ID_UART0)); - ret |= err; - } - } - return ret; -} - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } -#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_i2c_init(gd->fdt_blob); -#endif - return err; -} -#endif - #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { @@ -410,22 +83,3 @@ void exynos_set_dp_phy(unsigned int onoff) set_dp_phy_ctrl(onoff); } #endif - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - stdio_print_current_devices(); - - if (local.cros_ec_err) { - /* Force console on */ - gd->flags &= ~GD_FLG_SILENT; - - printf("cros-ec communications failure %d\n", - local.cros_ec_err); - puts("\nPlease reset with Power+Refresh\n\n"); - panic("Cannot init cros-ec device"); - return -1; - } - return 0; -} -#endif diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 97fe0ad..943c29a 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -26,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_USB_EHCI_EXYNOS -int board_usb_vbus_init(void) +static int board_usb_vbus_init(void) { struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); @@ -53,13 +54,8 @@ static void board_enable_audio_codec(void) } #endif -int board_init(void) +int exynos_init(void) { - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); - -#ifdef CONFIG_EXYNOS_SPI - spi_init(); -#endif #ifdef CONFIG_USB_EHCI_EXYNOS board_usb_vbus_init(); #endif @@ -69,147 +65,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - u32 addr; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); - } - return 0; -} - -#if defined(CONFIG_POWER) -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -int power_init_board(void) -{ - struct pmic *p; - - set_ps_hold_ctrl(); - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1_05V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif - -void dram_init_banksize(void) -{ - int i; - u32 addr, size; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; - } -} - int board_eth_init(bd_t *bis) { #ifdef CONFIG_SMC911X @@ -301,21 +156,6 @@ int board_mmc_init(bd_t *bis) } #endif -static int board_uart_init(void) -{ - int err, uart_id, ret = 0; - - for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { - err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); - if (err) { - debug("UART%d not configured\n", - (uart_id - PERIPH_ID_UART0)); - ret |= err; - } - } - return ret; -} - void board_i2c_init(const void *blob) { int i; @@ -326,22 +166,6 @@ void board_i2c_init(const void *blob) } } -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } -#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_i2c_init(NULL); -#endif - return err; -} -#endif - #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 8fb904c..79e85db 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -21,6 +21,8 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R /* Enable fdt support for Exynos5250 */ #define CONFIG_OF_CONTROL -- cgit v0.10.2 From e69847ab8dfc6db908e74f137642e2568ad23000 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:18 +0530 Subject: Exynos5420: Add base addresses for 5420 Adds base addresses of various IPs and controllers required for Exynos5420. Signed-off-by: Rajeshwari S Shinde Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index b4ef03e..2b44210 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -92,7 +92,7 @@ #define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE -/* EXYNOS5 Common*/ +/* EXYNOS5 */ #define EXYNOS5_I2C_SPACING 0x10000 #define EXYNOS5_AUDIOSS_BASE 0x03810000 @@ -130,6 +130,46 @@ #define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE +/* EXYNOS5420 */ +#define EXYNOS5420_AUDIOSS_BASE 0x03810000 +#define EXYNOS5420_GPIO_PART5_BASE 0x03860000 +#define EXYNOS5420_PRO_ID 0x10000000 +#define EXYNOS5420_CLOCK_BASE 0x10010000 +#define EXYNOS5420_POWER_BASE 0x10040000 +#define EXYNOS5420_SWRESET 0x10040400 +#define EXYNOS5420_SYSREG_BASE 0x10050000 +#define EXYNOS5420_TZPC_BASE 0x100E0000 +#define EXYNOS5420_WATCHDOG_BASE 0x101D0000 +#define EXYNOS5420_ACE_SFR_BASE 0x10830000 +#define EXYNOS5420_DMC_PHY_BASE 0x10C00000 +#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000 +#define EXYNOS5420_DMC_TZASC0_BASE 0x10D40000 +#define EXYNOS5420_DMC_TZASC1_BASE 0x10D50000 +#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000 +#define EXYNOS5420_MMC_BASE 0x12200000 +#define EXYNOS5420_SROMC_BASE 0x12250000 +#define EXYNOS5420_UART_BASE 0x12C00000 +#define EXYNOS5420_I2C_BASE 0x12C60000 +#define EXYNOS5420_I2C_8910_BASE 0x12E00000 +#define EXYNOS5420_SPI_BASE 0x12D20000 +#define EXYNOS5420_I2S_BASE 0x12D60000 +#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 +#define EXYNOS5420_SPI_ISP_BASE 0x131A0000 +#define EXYNOS5420_GPIO_PART2_BASE 0x13400000 +#define EXYNOS5420_GPIO_PART3_BASE 0x13410000 +#define EXYNOS5420_GPIO_PART4_BASE 0x14000000 +#define EXYNOS5420_GPIO_PART1_BASE 0x14010000 +#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 +#define EXYNOS5420_DP_BASE 0x145B0000 + +#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE + #ifndef __ASSEMBLY__ #include /* CPU detection macros */ @@ -163,6 +203,10 @@ static inline void s5p_set_cpu_id(void) /* Exynos5250 */ s5p_cpu_id = 0x5250; break; + case 0x420: + /* Exynos5420 */ + s5p_cpu_id = 0x5420; + break; } } @@ -190,6 +234,7 @@ static inline int __attribute__((no_instrument_function)) \ IS_EXYNOS_TYPE(exynos4210, 0x4210) IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250) +IS_EXYNOS_TYPE(exynos5420, 0x5420) #define SAMSUNG_BASE(device, base) \ static inline unsigned int __attribute__((no_instrument_function)) \ @@ -200,6 +245,8 @@ static inline unsigned int __attribute__((no_instrument_function)) \ return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ } else if (cpu_is_exynos5()) { \ + if (proid_is_exynos5420()) \ + return EXYNOS5420_##base; \ return EXYNOS5_##base; \ } \ return 0; \ -- cgit v0.10.2 From 3e976357643290ea708f9f905a04a3337d05f430 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:19 +0530 Subject: EXYNOS5420: Add power register structure. Add structure for power register for Exynos5420 Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 2bfee18..c9609a2 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -831,6 +831,843 @@ struct exynos5_power { unsigned int cmu_reset_mau_option; unsigned char res163[0x24]; }; + +struct exynos5420_power { + unsigned int om_stat; + unsigned int lpi_mask0; + unsigned int lpi_mask1; + unsigned char res1[0x10]; + unsigned int rtc_clko_sel; + unsigned char res2[0x1e0]; + unsigned int central_seq_configuration; + unsigned int central_seq_status; + unsigned int central_seq_option; + unsigned char res3[0x14]; + unsigned int seq_transition0; + unsigned int seq_transition1; + unsigned int seq_transition2; + unsigned int seq_transition3; + unsigned int seq_transition4; + unsigned int seq_transition5; + unsigned int seq_transition6; + unsigned int seq_transition7; + unsigned int central_seq_coreblk_configuration; + unsigned int central_seq_coreblk_status; + unsigned int central_seq_coreblk_option; + unsigned char res4[0x14]; + unsigned int seq_coreblk_transition0; + unsigned int seq_coreblk_transition1; + unsigned int seq_coreblk_transition2; + unsigned int seq_coreblk_transition3; + unsigned int seq_coreblk_transition4; + unsigned int seq_coreblk_transition5; + unsigned int seq_coreblk_transition6; + unsigned int seq_coreblk_transition7; + unsigned char res5[0x180]; + unsigned int swreset; + unsigned int rst_stat; + unsigned int automatic_wdt_reset_disable; + unsigned int mask_wdt_reset_request; + unsigned int mask_wreset_request; + unsigned char res6[0xec]; + unsigned int reset_sequencer_configuration; + unsigned int reset_sequencer_status; + unsigned int reset_sequencer_option; + unsigned char res7[0xf4]; + unsigned int wakeup_stat; + unsigned int eint_wakeup_mask; + unsigned int wakeup_mask; + unsigned int wakeup_interrupt; + unsigned char res8[0x10]; + unsigned int wakeup_stat_coreblk; + unsigned int eint_wakeup_mask_coreblk; + unsigned int wakeup_mask_coreblk; + unsigned int wakeup_interrupt_coreblk; + unsigned char res9[0xd0]; + unsigned int hdmi_phy_control; + unsigned int usbdev_phy_control; + unsigned int usbdev1_phy_control; + unsigned int usbhost_phy_control; + unsigned char res104[0x4]; + unsigned int mipi_phy0_control; + unsigned int mipi_phy1_control; + unsigned int mipi_phy2_control; + unsigned int adc_phy_control; + unsigned int mtcadc_phy_control; + unsigned int dptx_phy_control; + unsigned char res10[0xd4]; + unsigned int inform0; + unsigned int inform1; + unsigned int inform2; + unsigned int inform3; + unsigned int sysip_dat0; + unsigned int sysip_dat1; + unsigned int sysip_dat2; + unsigned int sysip_dat3; + unsigned char res11[0xe0]; + unsigned int pmu_spare0; + unsigned int pmu_spare1; + unsigned int pmu_spare2; + unsigned int pmu_spare3; + unsigned char res12[0x4]; + unsigned int cg_status0; + unsigned int cg_status1; + unsigned int cg_status2; + unsigned int cg_status3; + unsigned int cg_status4; + unsigned char res200[0x58]; + unsigned int irom_data_reg0; + unsigned int irom_data_reg1; + unsigned int irom_data_reg2; + unsigned int irom_data_reg3; + unsigned char res13[0x70]; + unsigned int pmu_debug; + unsigned char res14[0x5fc]; + unsigned int arm_core0_sys_pwr_reg; + unsigned char res500[0xc]; + unsigned int arm_core1_sys_pwr_reg; + unsigned char res501[0xc]; + unsigned int arm_core2_sys_pwr_reg; + unsigned char res502[0xc]; + unsigned int arm_core3_sys_pwr_reg; + unsigned char res503[0xc]; + unsigned int kfc_core0_sys_pwr_reg; + unsigned char res504[0xc]; + unsigned int kfc_core1_sys_pwr_reg; + unsigned char res505[0xc]; + unsigned int kfc_core2_sys_pwr_reg; + unsigned char res506[0xc]; + unsigned int kfc_core3_sys_pwr_reg; + unsigned char res507[0x1c]; + unsigned int isp_arm_sys_pwr_reg; + unsigned char res18[0xc]; + unsigned int arm_common_sys_pwr_reg; + unsigned char res508[0xc]; + unsigned int kfc_common_sys_pwr_reg; + unsigned char res19[0xc]; + unsigned int arm_l2_sys_pwr_reg; + unsigned char res509[0xc]; + unsigned int kfc_l2_sys_pwr_reg; + unsigned char res20[0xc]; + unsigned int cmu_cpu_aclkstop_sys_pwr_reg; + unsigned int cmu_cpu_sclkstop_sys_pwr_reg; + unsigned char res510[0x8]; + unsigned int cmu_kfc_aclkstop_sys_pwr_reg; + unsigned char res511[0xc]; + unsigned int cmu_aclkstop_sys_pwr_reg; + unsigned int cmu_sclkstop_sys_pwr_reg; + unsigned char res21[0x4]; + unsigned int cmu_reset_sys_pwr_reg; + unsigned char res22[0x10]; + unsigned int cmu_aclkstop_coreblk_sys_pwr_reg; + unsigned int cmu_sclkstop_coreblk_sys_pwr_reg; + unsigned char res23[0x4]; + unsigned int cmu_reset_coreblk_sys_pwr_reg; + unsigned int dram_freq_down_sys_pwr_reg; + unsigned int ddrphy_dlloff_sys_pwr_reg; + unsigned int ddrphy_dlllock_sys_pwr_reg; + unsigned char res25[0x4]; + unsigned int apll_sysclk_sys_pwr_reg; + unsigned int mpll_sysclk_sys_pwr_reg; + unsigned int vpll_sysclk_sys_pwr_reg; + unsigned int epll_sysclk_sys_pwr_reg; + unsigned int bpll_sysclk_sys_pwr_reg; + unsigned int cpll_sysclk_sys_pwr_reg; + unsigned int dpll_sysclk_sys_pwr_reg; + unsigned int ipll_sysclk_sys_pwr_reg; + unsigned int kpll_sysclk_sys_pwr_reg; + unsigned int mplluser_sysclk_sys_pwr_reg; + unsigned char res512[0x8]; + unsigned int bplluser_sysclk_sys_pwr_reg; + unsigned int rpll_sysclk_sys_pwr_reg; + unsigned int spll_sysclk_sys_pwr_reg; + unsigned char res26[0x4]; + unsigned int top_bus_sys_pwr_reg; + unsigned int top_retention_sys_pwr_reg; + unsigned int top_pwr_sys_pwr_reg; + unsigned char res29[0x4]; + unsigned int top_bus_coreblk_sys_pwr_reg; + unsigned int top_retention_coreblk_sys_pwr_reg; + unsigned int top_pwr_coreblk_sys_pwr_reg; + unsigned char res30[0x4]; + unsigned int logic_reset_sys_pwr_reg; + unsigned int oscclk_gate_sys_pwr_reg; + unsigned char res31[0x8]; + unsigned int logic_reset_coreblk_sys_pwr_reg; + unsigned int oscclk_gate_coreblk_sys_pwr_reg; + unsigned int intram_mem_sys_pwr_reg; + unsigned int introm_mem_sys_pwr_reg; + unsigned char res32[0x44]; + unsigned int pad_retention_mau_sys_pwr_reg; + unsigned int pad_retention_jtag_sys_pwr_reg; + unsigned char res36[0x4]; + unsigned int pad_retention_dram_sys_pwr_reg; + unsigned int pad_retention_uart_sys_pwr_reg; + unsigned int pad_retention_mmca_sys_pwr_reg; + unsigned int pad_retention_mmcb_sys_pwr_reg; + unsigned int pad_retention_mmcc_sys_pwr_reg; + unsigned int pad_retention_hsi_sys_pwr_reg; + unsigned int pad_retention_ebia_sys_pwr_reg; + unsigned int pad_retention_ebib_sys_pwr_reg; + unsigned int pad_retention_spi_sys_pwr_reg; + unsigned int pad_retention_dram_coreblk_sys_pwr_reg; + unsigned char res28[0x8]; + unsigned int pad_isolation_sys_pwr_reg; + unsigned char res37[0xc]; + unsigned int pad_isolation_coreblk_sys_pwr_reg; + unsigned char res38[0xc]; + unsigned int pad_alv_sel_sys_pwr_reg; + unsigned char res39[0x1c]; + unsigned int xusbxti_sys_pwr_reg; + unsigned int xxti_sys_pwr_reg; + unsigned char res40[0x38]; + unsigned int ext_regulator_sys_pwr_reg; + unsigned char res41[0x3c]; + unsigned int gpio_mode_sys_pwr_reg; + unsigned char res42[0x1c]; + unsigned int gpio_mode_coreblk_sys_pwr_reg; + unsigned char res43[0x1c]; + unsigned int gpio_mode_mau_sys_pwr_reg; + unsigned int top_asb_reset_sys_pwr_reg; + unsigned int top_asb_isolation_sys_pwr_reg; + unsigned char res44[0xb4]; + unsigned int gscl_sys_pwr_reg; + unsigned int isp_sys_pwr_reg; + unsigned int mfc_sys_pwr_reg; + unsigned int g3d_sys_pwr_reg; + unsigned int disp1_sys_pwr_reg; + unsigned int mau_sys_pwr_reg; + unsigned int g2d_sys_pwr_reg; + unsigned int msc_sys_pwr_reg; + unsigned int fsys_sys_pwr_reg; + unsigned int fsys2_sys_pwr_reg; + unsigned int psgen_sys_pwr_reg; + unsigned int peric_sys_pwr_reg; + unsigned int wcore_sys_pwr_reg; + unsigned char res46[0x4c]; + unsigned int cmu_clkstop_gscl_sys_pwr_reg; + unsigned int cmu_clkstop_isp_sys_pwr_reg; + unsigned int cmu_clkstop_mfc_sys_pwr_reg; + unsigned int cmu_clkstop_g3d_sys_pwr_reg; + unsigned int cmu_clkstop_disp1_sys_pwr_reg; + unsigned int cmu_clkstop_mau_sys_pwr_reg; + unsigned int cmu_clkstop_g2d_sys_pwr_reg; + unsigned int cmu_clkstop_msc_sys_pwr_reg; + unsigned int cmu_clkstop_fsys_sys_pwr_reg; + unsigned int cmu_clkstop_fsys2_sys_pwr_reg; + unsigned int cmu_clkstop_psgen_sys_pwr_reg; + unsigned int cmu_clkstop_peric_sys_pwr_reg; + unsigned int cmu_clkstop_wcore_sys_pwr_reg; + unsigned char res48[0x8]; + unsigned int cmu_sysclk_toppwr_sys_pwr_reg; + unsigned int cmu_sysclk_gscl_sys_pwr_reg; + unsigned int cmu_sysclk_isp_sys_pwr_reg; + unsigned int cmu_sysclk_mfc_sys_pwr_reg; + unsigned int cmu_sysclk_g3d_sys_pwr_reg; + unsigned int cmu_sysclk_disp1_sys_pwr_reg; + unsigned int cmu_sysclk_mau_sys_pwr_reg; + unsigned int cmu_sysclk_g2d_sys_pwr_reg; + unsigned int cmu_sysclk_msc_sys_pwr_reg; + unsigned int cmu_sysclk_fsys_sys_pwr_reg; + unsigned int cmu_sysclk_fsys2_sys_pwr_reg; + unsigned int cmu_sysclk_psgen_sys_pwr_reg; + unsigned int cmu_sysclk_peric_sys_pwr_reg; + unsigned int cmu_sysclk_wcore_sys_pwr_reg; + unsigned int cmu_sysclk_coreblk_toppwr_sys_pwr_reg; + unsigned char res50[0x78]; + unsigned int cmu_reset_fsys2_sys_pwr_reg; + unsigned int cmu_reset_psgen_sys_pwr_reg; + unsigned int cmu_reset_peric_sys_pwr_reg; + unsigned int cmu_reset_wcore_sys_pwr_reg; + unsigned int cmu_reset_gscl_sys_pwr_reg; + unsigned int cmu_reset_isp_sys_pwr_reg; + unsigned int cmu_reset_mfc_sys_pwr_reg; + unsigned int cmu_reset_g3d_sys_pwr_reg; + unsigned int cmu_reset_disp1_sys_pwr_reg; + unsigned int cmu_reset_mau_sys_pwr_reg; + unsigned int cmu_reset_g2d_sys_pwr_reg; + unsigned int cmu_reset_msc_sys_pwr_reg; + unsigned int cmu_reset_fsys_sys_pwr_reg; + unsigned char res52[0xa5c]; + unsigned int arm_core0_configuration; + unsigned int arm_core0_status; + unsigned int arm_core0_option; + unsigned char res53[0x14]; + unsigned int dis_irq_arm_core0_local_configuration; + unsigned int dis_irq_arm_core0_local_status; + unsigned int dis_irq_arm_core0_local_option; + unsigned char res54[0x14]; + unsigned int dis_irq_arm_core0_central_configuration; + unsigned int dis_irq_arm_core0_central_status; + unsigned int dis_irq_arm_core0_central_option; + unsigned char res55[0x34]; + unsigned int arm_core1_configuration; + unsigned int arm_core1_status; + unsigned int arm_core1_option; + unsigned char res56[0x14]; + unsigned int dis_irq_arm_core1_local_configuration; + unsigned int dis_irq_arm_core1_local_status; + unsigned int dis_irq_arm_core1_local_option; + unsigned char res57[0x14]; + unsigned int dis_irq_arm_core1_central_configuration; + unsigned int dis_irq_arm_core1_central_status; + unsigned int dis_irq_arm_core1_central_option; + unsigned char res600[0x34]; + unsigned int arm_core2_configuration; + unsigned int arm_core2_status; + unsigned int arm_core2_option; + unsigned char res601[0x14]; + unsigned int dis_irq_arm_core2_local_configuration; + unsigned int dis_irq_arm_core2_local_status; + unsigned int dis_irq_arm_core2_local_option; + unsigned char res602[0x14]; + unsigned int dis_irq_arm_core2_central_configuration; + unsigned int dis_irq_arm_core2_central_status; + unsigned int dis_irq_arm_core2_central_option; + unsigned char res603[0x34]; + unsigned int arm_core3_configuration; + unsigned int arm_core3_status; + unsigned int arm_core3_option; + unsigned char res900[0x14]; + unsigned int dis_irq_arm_core3_local_configuration; + unsigned int dis_irq_arm_core3_local_status; + unsigned int dis_irq_arm_core3_local_option; + unsigned char res901[0x14]; + unsigned int dis_irq_arm_core3_central_configuration; + unsigned int dis_irq_arm_core3_central_status; + unsigned int dis_irq_arm_core3_central_option; + unsigned char res604[0x34]; + unsigned int kfc_core0_configuration; + unsigned int kfc_core0_status; + unsigned int kfc_core0_option; + unsigned char res605[0x14]; + unsigned int dis_irq_kfc_core0_local_configuration; + unsigned int dis_irq_kfc_core0_local_status; + unsigned int dis_irq_kfc_core0_local_option; + unsigned char res606[0x14]; + unsigned int dis_irq_kfc_core0_central_configuration; + unsigned int dis_irq_kfc_core0_central_status; + unsigned int dis_irq_kfc_core0_central_option; + unsigned char res607[0x34]; + unsigned int kfc_core1_configuration; + unsigned int kfc_core1_status; + unsigned int kfc_core1_option; + unsigned char res608[0x14]; + unsigned int dis_irq_kfc_core1_local_configuration; + unsigned int dis_irq_kfc_core1_local_status; + unsigned int dis_irq_kfc_core1_local_option; + unsigned char res609[0x14]; + unsigned int dis_irq_kfc_core1_central_configuration; + unsigned int dis_irq_kfc_core1_central_status; + unsigned int dis_irq_kfc_core1_central_option; + unsigned char res610[0x34]; + unsigned int kfc_core2_configuration; + unsigned int kfc_core2_status; + unsigned int kfc_core2_option; + unsigned char res611[0x14]; + unsigned int dis_irq_kfc_core2_local_configuration; + unsigned int dis_irq_kfc_core2_local_status; + unsigned int dis_irq_kfc_core2_local_option; + unsigned char res612[0x14]; + unsigned int dis_irq_kfc_core2_central_configuration; + unsigned int dis_irq_kfc_core2_central_status; + unsigned int dis_irq_kfc_core2_central_option; + unsigned char res613[0x34]; + unsigned int kfc_core3_configuration; + unsigned int kfc_core3_status; + unsigned int kfc_core3_option; + unsigned char res614[0x14]; + unsigned int dis_irq_kfc_core3_local_configuration; + unsigned int dis_irq_kfc_core3_local_status; + unsigned int dis_irq_kfc_core3_local_option; + unsigned char res615[0x14]; + unsigned int dis_irq_kfc_core3_central_configuration; + unsigned int dis_irq_kfc_core3_central_status; + unsigned int dis_irq_kfc_core3_central_option; + unsigned char res61[0xb4]; + unsigned int isp_arm_configuration; + unsigned int isp_arm_status; + unsigned int isp_arm_option; + unsigned char res62[0x14]; + unsigned int dis_irq_isp_arm_local_configuration; + unsigned int dis_irq_isp_arm_local_status; + unsigned int dis_irq_isp_arm_local_option; + unsigned char res63[0x14]; + unsigned int dis_irq_isp_arm_central_configuration; + unsigned int dis_irq_isp_arm_central_status; + unsigned int dis_irq_isp_arm_central_option; + unsigned char res64[0x34]; + unsigned int arm_common_configuration; + unsigned int arm_common_status; + unsigned int arm_common_option; + unsigned char res616[0x74]; + unsigned int kfc_common_configuration; + unsigned int kfc_common_status; + unsigned int kfc_common_option; + unsigned char res65[0x74]; + unsigned int arm_l2_configuration; + unsigned int arm_l2_status; + unsigned int arm_l2_option; + unsigned char res617[0x74]; + unsigned int kfc_l2_configuration; + unsigned int kfc_l2_status; + unsigned int kfc_l2_option; + unsigned char res66[0x74]; + unsigned int cmu_cpu_aclkstop_configuration; + unsigned int cmu_cpu_aclkstop_status; + unsigned int cmu_cpu_aclkstop_option; + unsigned char res67[0x14]; + unsigned int cmu_cpu_sclkstop_configuration; + unsigned int cmu_cpu_sclkstop_status; + unsigned int cmu_cpu_sclkstop_option; + unsigned char res618[0x4]; + unsigned int cmu_kfc_aclkstop_configuration; + unsigned int cmu_kfc_aclkstop_status; + unsigned int cmu_kfc_aclkstop_option; + unsigned char res619[0xc4]; + unsigned int cmu_aclkstop_configuration; + unsigned int cmu_aclkstop_status; + unsigned int cmu_aclkstop_option; + unsigned char res620[0x14]; + unsigned int cmu_sclkstop_configuration; + unsigned int cmu_sclkstop_status; + unsigned int cmu_sclkstop_option; + unsigned char res68[0x34]; + unsigned int cmu_reset_configuration; + unsigned int cmu_reset_status; + unsigned int cmu_reset_option; + unsigned char res69[0x94]; + unsigned int cmu_aclkstop_coreblk_configuration; + unsigned int cmu_aclkstop_coreblk_status; + unsigned int cmu_aclkstop_coreblk_option; + unsigned char res70[0x14]; + unsigned int cmu_sclkstop_coreblk_configuration; + unsigned int cmu_sclkstop_coreblk_status; + unsigned int cmu_sclkstop_coreblk_option; + unsigned char res71[0x34]; + unsigned int cmu_reset_coreblk_configuration; + unsigned int cmu_reset_coreblk_status; + unsigned int cmu_reset_coreblk_option; + unsigned char res621[0x14]; + unsigned int dram_freq_down_configuration; + unsigned int dram_freq_down_status; + unsigned int dram_freq_down_option; + unsigned char res622[0x14]; + unsigned int ddrphy_dlloff_configuration; + unsigned int ddrphy_dlloff_status; + unsigned int ddrphy_dlloff_option; + unsigned char res72[0x14]; + unsigned int ddrphy_dlllock_configuration; + unsigned int ddrphy_dlllock_status; + unsigned int ddrphy_dlllock_option; + unsigned char res73[0x34]; + unsigned int apll_sysclk_configuration; + unsigned int apll_sysclk_status; + unsigned int apll_sysclk_option; + unsigned char res74[0x18]; + unsigned int mpll_sysclk_status; + unsigned int mpll_sysclk_option; + unsigned char res75[0x14]; + unsigned int vpll_sysclk_configuration; + unsigned int vpll_sysclk_status; + unsigned int vpll_sysclk_option; + unsigned char res76[0x14]; + unsigned int epll_sysclk_configuration; + unsigned int epll_sysclk_status; + unsigned int epll_sysclk_option; + unsigned char res77[0x14]; + unsigned int bpll_sysclk_configuration; + unsigned int bpll_sysclk_status; + unsigned int bpll_sysclk_option; + unsigned char res78[0x14]; + unsigned int cpll_sysclk_configuration; + unsigned int cpll_sysclk_status; + unsigned int cpll_sysclk_option; + unsigned char res79[0x14]; + unsigned int dpll_sysclk_configuration; + unsigned int dpll_sysclk_status; + unsigned int dpll_sysclk_option; + unsigned char res700[0x14]; + unsigned int ipll_sysclk_configuration; + unsigned int ipll_sysclk_status; + unsigned int ipll_sysclk_option; + unsigned char res903[0x14]; + unsigned int kpll_sysclk_configuration; + unsigned int kpll_sysclk_status; + unsigned int kpll_sysclk_option; + unsigned char res80[0x14]; + unsigned int mplluser_sysclk_configuration; + unsigned int mplluser_sysclk_status; + unsigned int mplluser_sysclk_option; + unsigned char res81[0x54]; + unsigned int bplluser_sysclk_configuration; + unsigned int bplluser_sysclk_status; + unsigned int bplluser_sysclk_option; + unsigned char res701[0x14]; + unsigned int rplluser_sysclk_configuration; + unsigned int rplluser_sysclk_status; + unsigned int rplluser_sysclk_option; + unsigned char res702[0x14]; + unsigned int splluser_sysclk_configuration; + unsigned int splluser_sysclk_status; + unsigned int splluser_sysclk_option; + unsigned char res82[0x34]; + unsigned int top_bus_configuration; + unsigned int top_bus_status; + unsigned int top_bus_option; + unsigned char res83[0x14]; + unsigned int top_retention_configuration; + unsigned int top_retention_status; + unsigned int top_retention_option; + unsigned char res84[0x14]; + unsigned int top_pwr_configuration; + unsigned int top_pwr_status; + unsigned int top_pwr_option; + unsigned char res85[0x34]; + unsigned int top_bus_coreblk_configuration; + unsigned int top_bus_coreblk_status; + unsigned int top_bus_coreblk_option; + unsigned char res86[0x14]; + unsigned int top_retention_coreblk_configuration; + unsigned int top_retention_coreblk_status; + unsigned int top_retention_coreblk_option; + unsigned char res87[0x14]; + unsigned int top_pwr_coreblk_configuration; + unsigned int top_pwr_coreblk_status; + unsigned int top_pwr_coreblk_option; + unsigned char res88[0x34]; + unsigned int logic_reset_configuration; + unsigned int logic_reset_status; + unsigned int logic_reset_option; + unsigned char res89[0x14]; + unsigned int oscclk_gate_configuration; + unsigned int oscclk_gate_status; + unsigned int oscclk_gate_option; + unsigned char res90[0x54]; + unsigned int logic_reset_coreblk_configuration; + unsigned int logic_reset_coreblk_status; + unsigned int logic_reset_coreblk_option; + unsigned char res91[0x14]; + unsigned int oscclk_gate_coreblk_configuration; + unsigned int oscclk_gate_coreblk_status; + unsigned int oscclk_gate_coreblk_option; + unsigned char res99[0x174]; + unsigned int intram_mem_configuration; + unsigned int intram_mem_status; + unsigned int intram_mem_option; + unsigned char res100[0x14]; + unsigned int introm_mem_configuration; + unsigned int introm_mem_status; + unsigned int introm_mem_option; + unsigned char res101[0xb4]; + unsigned int pad_retention_dram_configuration; + unsigned int pad_retention_dram_status; + unsigned int pad_retention_dram_option; + unsigned char res106[0x14]; + unsigned int pad_retention_mau_configuration; + unsigned int pad_retention_mau_status; + unsigned int pad_retention_mau_option; + unsigned char res107[0x14]; + unsigned int pad_retention_jtag_configuration; + unsigned int pad_retention_jtag_status; + unsigned int pad_retention_jtag_option; + unsigned char res92[0x74]; + unsigned int pad_retention_dram_configuration_2; + unsigned int pad_retention_dram_status_2; + unsigned int pad_retention_dram_option_2; + unsigned char res111[0x14]; + unsigned int pad_retention_uart_configuration; + unsigned int pad_retention_uart_status; + unsigned int pad_retention_uart_option; + unsigned char res112[0x14]; + unsigned int pad_retention_mmca_configuration; + unsigned int pad_retention_mmca_status; + unsigned int pad_retention_mmca_option; + unsigned char res113[0x14]; + unsigned int pad_retention_mmcb_configuration; + unsigned int pad_retention_mmcb_status; + unsigned int pad_retention_mmcb_option; + unsigned char res93[0x14]; + unsigned int pad_retention_mmcc_configuration; + unsigned int pad_retention_mmcc_status; + unsigned int pad_retention_mmcc_option; + unsigned char res94[0x14]; + unsigned int pad_retention_hsi_configuration; + unsigned int pad_retention_hsi_status; + unsigned int pad_retention_hsi_option; + unsigned char res114[0x14]; + unsigned int pad_retention_ebia_configuration; + unsigned int pad_retention_ebia_status; + unsigned int pad_retention_ebia_option; + unsigned char res115[0x14]; + unsigned int pad_retention_ebib_configuration; + unsigned int pad_retention_ebib_status; + unsigned int pad_retention_ebib_option; + unsigned char res116[0x14]; + unsigned int pad_retention_spi_configuration; + unsigned int pad_retention_spi_status; + unsigned int pad_retention_spi_option; + unsigned char res117[0x14]; + unsigned int pad_retention_dram_coreblk_configuration; + unsigned int pad_retention_dram_coreblk_status; + unsigned int pad_retention_dram_coreblk_option; + unsigned char res118[0x14]; + unsigned int pad_isolation_configuration; + unsigned int pad_isolation_status; + unsigned int pad_isolation_option; + unsigned char res119[0x74]; + unsigned int pad_isolation_coreblk_configuration; + unsigned int pad_isolation_coreblk_status; + unsigned int pad_isolation_coreblk_option; + unsigned char res120[0x74]; + unsigned int pad_alv_sel_configuration; + unsigned int pad_alv_sel_status; + unsigned int pad_alv_sel_option0; + unsigned int ps_hold_control; + unsigned char res130[0xf0]; + unsigned int xusbxti_configuration; + unsigned int xusbxti_status; + unsigned int xusbxti_option; + unsigned char res910[0x10]; + unsigned int xusbxti_duration3; + unsigned int xxti_configuration; + unsigned int xxti_status; + unsigned int xxti_option; + unsigned char res131[0x10]; + unsigned int xxti_duration3; + unsigned char res132[0x1c0]; + unsigned int ext_regulator_configuration; + unsigned int ext_regulator_status; + unsigned int ext_regulator_option; + unsigned char res133[0x10]; + unsigned int ext_regulator_duration3; + unsigned char res134[0x1e0]; + unsigned int gpio_mode_configuration; + unsigned int gpio_mode_status; + unsigned int gpio_mode_option; + unsigned char res135[0xf4]; + unsigned int gpio_mode_coreblk_configuration; + unsigned int gpio_mode_coreblk_status; + unsigned int gpio_mode_coreblk_option; + unsigned char res136[0xd4]; + unsigned int gpio_mode_mau_configuration; + unsigned int gpio_mode_mau_status; + unsigned int gpio_mode_mau_option; + unsigned char res137[0x14]; + unsigned int top_asb_reset_configuration; + unsigned int top_asb_reset_status; + unsigned int top_asb_reset_option; + unsigned char res138[0x14]; + unsigned int top_asb_isolation_configuration; + unsigned int top_asb_isolation_status; + unsigned int top_asb_isolation_option; + unsigned char res139[0x5d4]; + unsigned int gscl_configuration; + unsigned int gscl_status; + unsigned int gscl_option; + unsigned char res140[0x14]; + unsigned int isp_configuration; + unsigned int isp_status; + unsigned int isp_option; + unsigned char res141[0x34]; + unsigned int mfc_configuration; + unsigned int mfc_status; + unsigned int mfc_option; + unsigned char res142[0x14]; + unsigned int g3d_configuration; + unsigned int g3d_status; + unsigned int g3d_option; + unsigned char res143[0x34]; + unsigned int disp1_configuration; + unsigned int disp1_status; + unsigned int disp1_option; + unsigned char res144[0x14]; + unsigned int mau_configuration; + unsigned int mau_status; + unsigned int mau_option; + unsigned char res800[0x14]; + unsigned int g2d_configuration; + unsigned int g2d_status; + unsigned int g2d_option; + unsigned char res801[0x14]; + unsigned int msc_configuration; + unsigned int msc_status; + unsigned int msc_option; + unsigned char res802[0x14]; + unsigned int fsys_configuration; + unsigned int fsys_status; + unsigned int fsys_option; + unsigned char res803[0x14]; + unsigned int fsys2_configuration; + unsigned int fsys2_status; + unsigned int fsys2_option; + unsigned char res804[0x14]; + unsigned int psgen_configuration; + unsigned int psgen_status; + unsigned int psgen_option; + unsigned char res805[0x14]; + unsigned int peric_configuration; + unsigned int peric_status; + unsigned int peric_option; + unsigned char res806[0x14]; + unsigned int wcore_configuration; + unsigned int wcore_status; + unsigned int wcore_option; + unsigned char res145[0x234]; + unsigned int cmu_clkstop_gscl_configuration; + unsigned int cmu_clkstop_gscl_status; + unsigned int cmu_clkstop_gscl_option; + unsigned char res146[0x14]; + unsigned int cmu_clkstop_isp_configuration; + unsigned int cmu_clkstop_isp_status; + unsigned int cmu_clkstop_isp_option; + unsigned char res147[0x34]; + unsigned int cmu_clkstop_mfc_configuration; + unsigned int cmu_clkstop_mfc_status; + unsigned int cmu_clkstop_mfc_option; + unsigned char res148[0x14]; + unsigned int cmu_clkstop_g3d_configuration; + unsigned int cmu_clkstop_g3d_status; + unsigned int cmu_clkstop_g3d_option; + unsigned char res149[0x34]; + unsigned int cmu_clkstop_disp1_configuration; + unsigned int cmu_clkstop_disp1_status; + unsigned int cmu_clkstop_disp1_option; + unsigned char res150[0x14]; + unsigned int cmu_clkstop_mau_configuration; + unsigned int cmu_clkstop_mau_status; + unsigned int cmu_clkstop_mau_option; + unsigned char res807[0x14]; + unsigned int cmu_clkstop_g2d_configuration; + unsigned int cmu_clkstop_g2d_status; + unsigned int cmu_clkstop_g2d_option; + unsigned char res808[0x14]; + unsigned int cmu_clkstop_msc_configuration; + unsigned int cmu_clkstop_msc_status; + unsigned int cmu_clkstop_msc_option; + unsigned char res809[0x14]; + unsigned int cmu_clkstop_fsys_configuration; + unsigned int cmu_clkstop_fsys_status; + unsigned int cmu_clkstop_fsys_option; + unsigned char res810[0x14]; + unsigned int cmu_clkstop_fsys2_configuration; + unsigned int cmu_clkstop_fsys2_status; + unsigned int cmu_clkstop_fsys2_option; + unsigned char res811[0x14]; + unsigned int cmu_clkstop_psgen_configuration; + unsigned int cmu_clkstop_psgen_status; + unsigned int cmu_clkstop_psgen_option; + unsigned char res812[0x14]; + unsigned int cmu_clkstop_peric_configuration; + unsigned int cmu_clkstop_peric_status; + unsigned int cmu_clkstop_peric_option; + unsigned char res813[0x14]; + unsigned int cmu_clkstop_wcore_configuration; + unsigned int cmu_clkstop_wcore_status; + unsigned int cmu_clkstop_wcore_option; + unsigned char res151[0x14]; + unsigned int cmu_sysclk_toppwr_configuration; + unsigned int cmu_sysclk_toppwr_status; + unsigned int cmu_sysclk_toppwr_option; + unsigned char res920[0x18]; + unsigned int cmu_sysclk_gscl_status; + unsigned int cmu_sysclk_gscl_option; + unsigned char res152[0x18]; + unsigned int cmu_sysclk_isp_status; + unsigned int cmu_sysclk_isp_option; + unsigned char res153[0x38]; + unsigned int cmu_sysclk_mfc_status; + unsigned int cmu_sysclk_mfc_option; + unsigned char res154[0x18]; + unsigned int cmu_sysclk_g3d_status; + unsigned int cmu_sysclk_g3d_option; + unsigned char res155[0x38]; + unsigned int cmu_sysclk_disp1_status; + unsigned int cmu_sysclk_disp1_option; + unsigned char res156[0x18]; + unsigned int cmu_sysclk_mau_status; + unsigned int cmu_sysclk_mau_option; + unsigned char res814[0x18]; + unsigned int cmu_sysclk_g2d_status; + unsigned int cmu_sysclk_g2d_option; + unsigned char res815[0x18]; + unsigned int cmu_sysclk_msc_status; + unsigned int cmu_sysclk_msc_option; + unsigned char res922[0x18]; + unsigned int cmu_sysclk_fsys_status; + unsigned int cmu_sysclk_fsys_option; + unsigned char res816[0x18]; + unsigned int cmu_sysclk_fsys2_status; + unsigned int cmu_sysclk_fsys2_option; + unsigned char res817[0x18]; + unsigned int cmu_sysclk_psgen_status; + unsigned int cmu_sysclk_psgen_option; + unsigned char res950[0x18]; + unsigned int cmu_sysclk_peric_status; + unsigned int cmu_sysclk_peric_option; + unsigned char res818[0x18]; + unsigned int cmu_sysclk_wcore_status; + unsigned int cmu_sysclk_wcore_option; + unsigned char res819[0x18]; + unsigned int cmu_sysclk_coreblk_toppwr_status; + unsigned int cmu_sysclk_coreblk_toppwr_option; + unsigned char res157[0x414]; + unsigned int cmu_reset_gscl_configuration; + unsigned int cmu_reset_gscl_status; + unsigned int cmu_reset_gscl_option; + unsigned char res158[0x14]; + unsigned int cmu_reset_isp_configuration; + unsigned int cmu_reset_isp_status; + unsigned int cmu_reset_isp_option; + unsigned char res159[0x34]; + unsigned int cmu_reset_mfc_configuration; + unsigned int cmu_reset_mfc_status; + unsigned int cmu_reset_mfc_option; + unsigned char res160[0x14]; + unsigned int cmu_reset_g3d_configuration; + unsigned int cmu_reset_g3d_status; + unsigned int cmu_reset_g3d_option; + unsigned char res161[0x34]; + unsigned int cmu_reset_disp1_configuration; + unsigned int cmu_reset_disp1_status; + unsigned int cmu_reset_disp1_option; + unsigned char res162[0x14]; + unsigned int cmu_reset_mau_configuration; + unsigned int cmu_reset_mau_status; + unsigned int cmu_reset_mau_option; + unsigned char res163[0x14]; + unsigned int version_info; + unsigned int i2s_bypass; + unsigned int kfc_swreset_mask_from_eagle; + unsigned char res164[0xf4]; + unsigned int cmu_reset_g2d_configuration; + unsigned int cmu_reset_g2d_status; + unsigned int cmu_reset_g2d_option; + unsigned char res165[0x14]; + unsigned int cmu_reset_msc_configuration; + unsigned int cmu_reset_msc_status; + unsigned int cmu_reset_msc_option; + unsigned char res166[0x14]; + unsigned int cmu_reset_fsys_configuration; + unsigned int cmu_reset_fsys_status; + unsigned int cmu_reset_fsys_option; + unsigned char res167[0x14]; + unsigned int cmu_reset_fsys2_configuration; + unsigned int cmu_reset_fsys2_status; + unsigned int cmu_reset_fsys2_option; + unsigned char res168[0x14]; + unsigned int cmu_reset_psgen_configuration; + unsigned int cmu_reset_psgen_status; + unsigned int cmu_reset_psgen_option; + unsigned char res169[0x14]; + unsigned int cmu_reset_peric_configuration; + unsigned int cmu_reset_peric_status; + unsigned int cmu_reset_peric_option; + unsigned char res170[0x14]; + unsigned int cmu_reset_wcore_configuration; + unsigned int cmu_reset_wcore_status; + unsigned int cmu_reset_wcore_option; +}; #endif /* __ASSEMBLY__ */ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); -- cgit v0.10.2 From e89278c9331143f1c5f3bc97c90aee8bce76f8b4 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:20 +0530 Subject: EXYNOS5420: Add dmc and phy_control register structure Add dmc and phy_control register structure for 5420. Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index f65c676..32ad3ae 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -205,6 +205,127 @@ struct exynos5_dmc { unsigned int pmcnt3_ppc_a; }; +struct exynos5420_dmc { + unsigned int concontrol; + unsigned int memcontrol; + unsigned int cgcontrol; + unsigned char res500[0x4]; + unsigned int directcmd; + unsigned int prechconfig0; + unsigned int phycontrol0; + unsigned int prechconfig1; + unsigned char res1[0x8]; + unsigned int pwrdnconfig; + unsigned int timingpzq; + unsigned int timingref; + unsigned int timingrow0; + unsigned int timingdata0; + unsigned int timingpower0; + unsigned int phystatus; + unsigned int etctiming; + unsigned int chipstatus; + unsigned char res3[0x8]; + unsigned int mrstatus; + unsigned char res4[0x8]; + unsigned int qoscontrol0; + unsigned char resr5[0x4]; + unsigned int qoscontrol1; + unsigned char res6[0x4]; + unsigned int qoscontrol2; + unsigned char res7[0x4]; + unsigned int qoscontrol3; + unsigned char res8[0x4]; + unsigned int qoscontrol4; + unsigned char res9[0x4]; + unsigned int qoscontrol5; + unsigned char res10[0x4]; + unsigned int qoscontrol6; + unsigned char res11[0x4]; + unsigned int qoscontrol7; + unsigned char res12[0x4]; + unsigned int qoscontrol8; + unsigned char res13[0x4]; + unsigned int qoscontrol9; + unsigned char res14[0x4]; + unsigned int qoscontrol10; + unsigned char res15[0x4]; + unsigned int qoscontrol11; + unsigned char res16[0x4]; + unsigned int qoscontrol12; + unsigned char res17[0x4]; + unsigned int qoscontrol13; + unsigned char res18[0x4]; + unsigned int qoscontrol14; + unsigned char res19[0x4]; + unsigned int qoscontrol15; + unsigned char res20[0x4]; + unsigned int timing_set_sw; + unsigned int timingrow1; + unsigned int timingdata1; + unsigned int timingpower1; + unsigned char res300[0x4]; + unsigned int wrtra_config; + unsigned int rdlvl_config; + unsigned char res21[0x4]; + unsigned int brbrsvcontrol; + unsigned int brbrsvconfig; + unsigned int brbqosconfig; + unsigned char res301[0x14]; + unsigned int wrlvl_config0; + unsigned int wrlvl_config1; + unsigned int wrlvl_status; + unsigned char res23[0x4]; + unsigned int ppcclockon; + unsigned int perevconfig0; + unsigned int perevconfig1; + unsigned int perevconfig2; + unsigned int perevconfig3; + unsigned char res24[0xc]; + unsigned int control_io_rdata; + unsigned char res240[0xc]; + unsigned int cacal_config0; + unsigned int cacal_config1; + unsigned int cacal_status; + unsigned char res302[0xa4]; + unsigned int bp_control0; + unsigned int bp_config0_r; + unsigned int bp_config0_w; + unsigned char res303[0x4]; + unsigned int bp_control1; + unsigned int bp_config1_r; + unsigned int bp_config1_w; + unsigned char res304[0x4]; + unsigned int bp_control2; + unsigned int bp_config2_r; + unsigned int bp_config2_w; + unsigned char res305[0x4]; + unsigned int bp_control3; + unsigned int bp_config3_r; + unsigned int bp_config3_w; + unsigned char res306[0xddb4]; + unsigned int pmnc_ppc; + unsigned char res25[0xc]; + unsigned int cntens_ppc; + unsigned char res26[0xc]; + unsigned int cntenc_ppc; + unsigned char res27[0xc]; + unsigned int intens_ppc; + unsigned char res28[0xc]; + unsigned int intenc_ppc; + unsigned char res29[0xc]; + unsigned int flag_ppc; + unsigned char res30[0xac]; + unsigned int ccnt_ppc; + unsigned char res31[0xc]; + unsigned int pmcnt0_ppc; + unsigned char res32[0xc]; + unsigned int pmcnt1_ppc; + unsigned char res33[0xc]; + unsigned int pmcnt2_ppc; + unsigned char res34[0xc]; + unsigned int pmcnt3_ppc; +}; + struct exynos5_phy_control { unsigned int phy_con0; unsigned int phy_con1; @@ -252,6 +373,52 @@ struct exynos5_phy_control { unsigned int phy_con42; }; +struct exynos5420_phy_control { + unsigned int phy_con0; + unsigned int phy_con1; + unsigned int phy_con2; + unsigned int phy_con3; + unsigned int phy_con4; + unsigned int phy_con5; + unsigned int phy_con6; + unsigned char res2[0x4]; + unsigned int phy_con8; + unsigned char res5[0x4]; + unsigned int phy_con10; + unsigned int phy_con11; + unsigned int phy_con12; + unsigned int phy_con13; + unsigned int phy_con14; + unsigned int phy_con15; + unsigned int phy_con16; + unsigned char res4[0x4]; + unsigned int phy_con17; + unsigned int phy_con18; + unsigned int phy_con19; + unsigned int phy_con20; + unsigned int phy_con21; + unsigned int phy_con22; + unsigned int phy_con23; + unsigned int phy_con24; + unsigned int phy_con25; + unsigned int phy_con26; + unsigned int phy_con27; + unsigned int phy_con28; + unsigned int phy_con29; + unsigned int phy_con30; + unsigned int phy_con31; + unsigned int phy_con32; + unsigned int phy_con33; + unsigned int phy_con34; + unsigned char res6[0x8]; + unsigned int phy_con37; + unsigned char res7[0x4]; + unsigned int phy_con39; + unsigned int phy_con40; + unsigned int phy_con41; + unsigned int phy_con42; +}; + enum ddr_mode { DDR_MODE_DDR2, DDR_MODE_DDR3, -- cgit v0.10.2 From 060c227a2861b0702e34eabe08eea9cc5bb68b45 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:21 +0530 Subject: Exynos5420: Add clock initialization for 5420 This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 84a5047..5bde9d1 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) freq = CONFIG_SYS_CLK_FREQ; - if (pllreg == EPLL) { + if (pllreg == EPLL || pllreg == RPLL) { k = k & 0xffff; /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s))); @@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) div = PLL_DIV_1024; else if (proid_is_exynos4412()) div = PLL_DIV_65535; - else if (proid_is_exynos5250()) + else if (proid_is_exynos5250() || proid_is_exynos5420()) div = PLL_DIV_65536; else return 0; @@ -362,6 +362,43 @@ unsigned long clock_get_periph_rate(int peripheral) return 0; } +/* exynos5420: return pll clock frequency */ +static unsigned long exynos5420_get_pll_clk(int pllreg) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + case BPLL: + r = readl(&clk->bpll_con0); + break; + case RPLL: + r = readl(&clk->rpll_con0); + k = readl(&clk->rpll_con1); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + /* exynos4: return ARM clock frequency */ static unsigned long exynos4_get_arm_clk(void) { @@ -485,6 +522,27 @@ static unsigned long exynos4x12_get_pwm_clk(void) return pclk; } +/* exynos5420: return pwm clock frequency */ +static unsigned long exynos5420_get_pwm_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int ratio; + + /* + * CLK_DIV_PERIC0 + * PWM_RATIO [31:28] + */ + ratio = readl(&clk->div_peric0); + ratio = (ratio >> 28) & 0xf; + sclk = get_pll_clk(MPLL); + + pclk = sclk / (ratio + 1); + + return pclk; +} + /* exynos4: return uart clock frequency */ static unsigned long exynos4_get_uart_clk(int dev_index) { @@ -624,6 +682,53 @@ static unsigned long exynos5_get_uart_clk(int dev_index) return uclk; } +/* exynos5420: return uart clock frequency */ +static unsigned long exynos5420_get_uart_clk(int dev_index) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_PERIC0 + * UART0_SEL [6:4] + * UART1_SEL [10:8] + * UART2_SEL [14:12] + * UART3_SEL [18:16] + * generalised calculation as follows + * sel = (sel >> ((dev_index * 4) + 4)) & mask; + */ + sel = readl(&clk->src_peric0); + sel = (sel >> ((dev_index * 4) + 4)) & 0x7; + + if (sel == 0x3) + sclk = get_pll_clk(MPLL); + else if (sel == 0x6) + sclk = get_pll_clk(EPLL); + else if (sel == 0x7) + sclk = get_pll_clk(RPLL); + else + return 0; + + /* + * CLK_DIV_PERIC0 + * UART0_RATIO [11:8] + * UART1_RATIO [15:12] + * UART2_RATIO [19:16] + * UART3_RATIO [23:20] + * generalised calculation as follows + * ratio = (ratio >> ((dev_index * 4) + 8)) & mask; + */ + ratio = readl(&clk->div_peric0); + ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf; + + uclk = sclk / (ratio + 1); + + return uclk; +} + static unsigned long exynos4_get_mmc_clk(int dev_index) { struct exynos4_clock *clk = @@ -718,6 +823,47 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) return uclk; } +static unsigned long exynos5420_get_mmc_clk(int dev_index) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel, ratio; + + /* + * CLK_SRC_FSYS + * MMC0_SEL [10:8] + * MMC1_SEL [14:12] + * MMC2_SEL [18:16] + * generalised calculation as follows + * sel = (sel >> ((dev_index * 4) + 8)) & mask + */ + sel = readl(&clk->src_fsys); + sel = (sel >> ((dev_index * 4) + 8)) & 0x7; + + if (sel == 0x3) + sclk = get_pll_clk(MPLL); + else if (sel == 0x6) + sclk = get_pll_clk(EPLL); + else + return 0; + + /* + * CLK_DIV_FSYS1 + * MMC0_RATIO [9:0] + * MMC1_RATIO [19:10] + * MMC2_RATIO [29:20] + * generalised calculation as follows + * ratio = (ratio >> (dev_index * 10)) & mask + */ + ratio = readl(&clk->div_fsys1); + ratio = (ratio >> (dev_index * 10)) & 0x3ff; + + uclk = (sclk / (ratio + 1)); + + return uclk; +} + /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { @@ -804,6 +950,29 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +/* exynos5: set the mmc clock */ +static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int addr; + unsigned int val, shift; + + /* + * CLK_DIV_FSYS1 + * MMC0_RATIO [9:0] + * MMC1_RATIO [19:10] + * MMC2_RATIO [29:20] + */ + addr = (unsigned int)&clk->div_fsys1; + shift = dev_index * 10; + + val = readl(addr); + val &= ~(0x3ff << shift); + val |= (div & 0x3ff) << shift; + writel(val, addr); +} + /* get_lcd_clk: return lcd clock frequency */ static unsigned long exynos4_get_lcd_clk(void) { @@ -1324,6 +1493,71 @@ static int exynos5_set_spi_clk(enum periph_id periph_id, return 0; } +static int exynos5420_set_spi_clk(enum periph_id periph_id, + unsigned int rate) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + int main; + unsigned int fine; + unsigned shift, pre_shift; + unsigned div_mask = 0xf, pre_div_mask = 0xff; + u32 *reg; + u32 *pre_reg; + + main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); + if (main < 0) { + debug("%s: Cannot set clock rate for periph %d", + __func__, periph_id); + return -1; + } + main = main - 1; + fine = fine - 1; + + switch (periph_id) { + case PERIPH_ID_SPI0: + reg = &clk->div_peric1; + shift = 20; + pre_reg = &clk->div_peric4; + pre_shift = 8; + break; + case PERIPH_ID_SPI1: + reg = &clk->div_peric1; + shift = 24; + pre_reg = &clk->div_peric4; + pre_shift = 16; + break; + case PERIPH_ID_SPI2: + reg = &clk->div_peric1; + shift = 28; + pre_reg = &clk->div_peric4; + pre_shift = 24; + break; + case PERIPH_ID_SPI3: + reg = &clk->div_isp1; + shift = 16; + pre_reg = &clk->div_isp1; + pre_shift = 0; + break; + case PERIPH_ID_SPI4: + reg = &clk->div_isp1; + shift = 20; + pre_reg = &clk->div_isp1; + pre_shift = 8; + break; + default: + debug("%s: Unsupported peripheral ID %d\n", __func__, + periph_id); + return -1; + } + + clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift); + clrsetbits_le32(pre_reg, pre_div_mask << pre_shift, + (fine & pre_div_mask) << pre_shift); + + return 0; +} + static unsigned long exynos4_get_i2c_clk(void) { struct exynos4_clock *clk = @@ -1341,9 +1575,11 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); - else { + } else { if (proid_is_exynos4412()) return exynos4x12_get_pll_clk(pllreg); return exynos4_get_pll_clk(pllreg); @@ -1375,9 +1611,11 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_get_pwm_clk(); return clock_get_periph_rate(PERIPH_ID_PWM0); - else { + } else { if (proid_is_exynos4412()) return exynos4x12_get_pwm_clk(); return exynos4_get_pwm_clk(); @@ -1386,9 +1624,11 @@ unsigned long get_pwm_clk(void) unsigned long get_uart_clk(int dev_index) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_get_uart_clk(dev_index); return exynos5_get_uart_clk(dev_index); - else { + } else { if (proid_is_exynos4412()) return exynos4x12_get_uart_clk(dev_index); return exynos4_get_uart_clk(dev_index); @@ -1397,17 +1637,23 @@ unsigned long get_uart_clk(int dev_index) unsigned long get_mmc_clk(int dev_index) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_get_mmc_clk(dev_index); return exynos5_get_mmc_clk(dev_index); - else + } else { return exynos4_get_mmc_clk(dev_index); + } } void set_mmc_clk(int dev_index, unsigned int div) { - if (cpu_is_exynos5()) - exynos5_set_mmc_clk(dev_index, div); - else { + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + exynos5420_set_mmc_clk(dev_index, div); + else + exynos5_set_mmc_clk(dev_index, div); + } else { if (proid_is_exynos4412()) exynos4x12_set_mmc_clk(dev_index, div); else @@ -1439,10 +1685,13 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); - else + } else { return 0; + } } int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h index c28ff3a..a875d0b 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ b/arch/arm/cpu/armv7/exynos/clock_init.h @@ -10,7 +10,11 @@ #define __EXYNOS_CLOCK_INIT_H enum { +#ifdef CONFIG_EXYNOS5420 + MEM_TIMINGS_MSR_COUNT = 5, +#else MEM_TIMINGS_MSR_COUNT = 4, +#endif }; /* These are the ratio's for configuring ARM clock */ @@ -59,6 +63,18 @@ struct mem_timings { unsigned bpll_mdiv; unsigned bpll_pdiv; unsigned bpll_sdiv; + unsigned kpll_mdiv; + unsigned kpll_pdiv; + unsigned kpll_sdiv; + unsigned dpll_mdiv; + unsigned dpll_pdiv; + unsigned dpll_sdiv; + unsigned ipll_mdiv; + unsigned ipll_pdiv; + unsigned ipll_sdiv; + unsigned spll_mdiv; + unsigned spll_pdiv; + unsigned spll_sdiv; unsigned pclk_cdrex_ratio; unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; @@ -115,6 +131,7 @@ struct mem_timings { uint8_t send_zq_init; /* 1 to send this command */ unsigned impedance; /* drive strength impedeance */ uint8_t gate_leveling_enable; /* check gate leveling is enabled */ + uint8_t read_leveling_enable; /* check h/w read leveling is enabled */ }; /** diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index a24c2f3..1d6977f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -24,6 +24,24 @@ DECLARE_GLOBAL_DATA_PTR; struct arm_clk_ratios arm_clk_ratios[] = { +#ifdef CONFIG_EXYNOS5420 + { + .arm_freq_mhz = 900, + + .apll_mdiv = 0x96, + .apll_pdiv = 0x2, + .apll_sdiv = 0x1, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x6, + .atb_ratio = 0x6, + .periph_ratio = 0x7, + .acp_ratio = 0x0, + .cpud_ratio = 0x2, + .arm_ratio = 0x0, + } +#else { .arm_freq_mhz = 600, @@ -115,8 +133,133 @@ struct arm_clk_ratios arm_clk_ratios[] = { .cpud_ratio = 0x3, .arm_ratio = 0x0, } +#endif }; + struct mem_timings mem_timings[] = { +#ifdef CONFIG_EXYNOS5420 + { + .mem_manuf = MEM_MANUF_SAMSUNG, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + + /* MPLL @800MHz*/ + .mpll_mdiv = 0xc8, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x1, + /* CPLL @666MHz */ + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x1, + /* EPLL @600MHz */ + .epll_mdiv = 0x64, + .epll_pdiv = 0x2, + .epll_sdiv = 0x1, + /* VPLL @430MHz */ + .vpll_mdiv = 0xd7, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + /* BPLL @800MHz */ + .bpll_mdiv = 0xc8, + .bpll_pdiv = 0x3, + .bpll_sdiv = 0x1, + /* KPLL @600MHz */ + .kpll_mdiv = 0x190, + .kpll_pdiv = 0x4, + .kpll_sdiv = 0x2, + /* DPLL @600MHz */ + .dpll_mdiv = 0x190, + .dpll_pdiv = 0x4, + .dpll_sdiv = 0x2, + /* IPLL @370MHz */ + .ipll_mdiv = 0xb9, + .ipll_pdiv = 0x3, + .ipll_sdiv = 0x2, + /* SPLL @400MHz */ + .spll_mdiv = 0xc8, + .spll_pdiv = 0x3, + .spll_sdiv = 0x2, + + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010046, 0x00000d70, + 0x00000c70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x6836650f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a26, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x8, + .phy1_tFS = 0x8, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x7, + .zq_mode_term = 0x1, + .zq_mode_noterm = 1, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_DISABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT | + DMC_MEMCONFIGX_CHIP_COL_10 | + DMC_MEMCONFIGX_CHIP_ROW_15 | + DMC_MEMCONFIGX_CHIP_BANK_8, + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 1, + .chips_per_channel = 1, + .chips_to_configure = 1, + .send_zq_init = 1, + .gate_leveling_enable = 1, + .read_leveling_enable = 0, + } +#else { .mem_manuf = MEM_MANUF_ELPIDA, .mem_type = DDR_MODE_DDR3, @@ -324,6 +467,7 @@ struct mem_timings mem_timings[] = { .impedance = IMP_OUTPUT_DRV_40_OHM, .gate_leveling_enable = 1, } +#endif }; /** @@ -399,7 +543,7 @@ struct mem_timings *clock_get_mem_timings(void) return NULL; } -void system_clock_init() +static void exynos5250_system_clock_init(void) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); @@ -436,19 +580,13 @@ void system_clock_init() } while ((val | MUX_BPLL_SEL_MASK) != val); /* PLL locktime */ - writel(APLL_LOCK_VAL, &clk->apll_lock); - - writel(MPLL_LOCK_VAL, &clk->mpll_lock); - - writel(BPLL_LOCK_VAL, &clk->bpll_lock); - - writel(CPLL_LOCK_VAL, &clk->cpll_lock); - - writel(GPLL_LOCK_VAL, &clk->gpll_lock); - - writel(EPLL_LOCK_VAL, &clk->epll_lock); - - writel(VPLL_LOCK_VAL, &clk->vpll_lock); + writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock); + writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock); + writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock); + writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock); + writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock); + writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock); + writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock); writel(CLK_REG_DISABLE, &clk->pll_div2_sel); @@ -640,6 +778,192 @@ void system_clock_init() writel(val, &clk->div_fsys2); } +static void exynos5420_system_clock_init(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + struct mem_timings *mem; + struct arm_clk_ratios *arm_clk_ratio; + u32 val; + + mem = clock_get_mem_timings(); + arm_clk_ratio = get_arm_ratios(); + + /* PLL locktime */ + writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock); + writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock); + writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock); + writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock); + writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock); + writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock); + writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock); + writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock); + writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock); + writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock); + + setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK); + + writel(0, &clk->src_top6); + + writel(0, &clk->src_cdrex); + writel(SRC_KFC_HPM_SEL, &clk->src_kfc); + writel(HPM_RATIO, &clk->div_cpu1); + writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); + + /* switch A15 clock source to OSC clock before changing APLL */ + clrbits_le32(&clk->src_cpu, APLL_FOUT); + + /* Set APLL */ + writel(APLL_CON1_VAL, &clk->apll_con1); + val = set_pll(arm_clk_ratio->apll_mdiv, + arm_clk_ratio->apll_pdiv, + arm_clk_ratio->apll_sdiv); + writel(val, &clk->apll_con0); + while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0) + ; + + /* now it is safe to switch to APLL */ + setbits_le32(&clk->src_cpu, APLL_FOUT); + + writel(SRC_KFC_HPM_SEL, &clk->src_kfc); + writel(CLK_DIV_KFC_VAL, &clk->div_kfc0); + + /* switch A7 clock source to OSC clock before changing KPLL */ + clrbits_le32(&clk->src_kfc, KPLL_FOUT); + + /* Set KPLL*/ + writel(KPLL_CON1_VAL, &clk->kpll_con1); + val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv); + writel(val, &clk->kpll_con0); + while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0) + ; + + /* now it is safe to switch to KPLL */ + setbits_le32(&clk->src_kfc, KPLL_FOUT); + + /* Set MPLL */ + writel(MPLL_CON1_VAL, &clk->mpll_con1); + val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); + writel(val, &clk->mpll_con0); + while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set DPLL */ + writel(DPLL_CON1_VAL, &clk->dpll_con1); + val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv); + writel(val, &clk->dpll_con0); + while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set EPLL */ + writel(EPLL_CON2_VAL, &clk->epll_con2); + writel(EPLL_CON1_VAL, &clk->epll_con1); + val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); + writel(val, &clk->epll_con0); + while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0) + ; + + /* Set CPLL */ + writel(CPLL_CON1_VAL, &clk->cpll_con1); + val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); + writel(val, &clk->cpll_con0); + while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set IPLL */ + writel(IPLL_CON1_VAL, &clk->ipll_con1); + val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv); + writel(val, &clk->ipll_con0); + while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0) + ; + + /* Set VPLL */ + writel(VPLL_CON1_VAL, &clk->vpll_con1); + val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); + writel(val, &clk->vpll_con0); + while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set BPLL */ + writel(BPLL_CON1_VAL, &clk->bpll_con1); + val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); + writel(val, &clk->bpll_con0); + while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0) + ; + + /* Set SPLL */ + writel(SPLL_CON1_VAL, &clk->spll_con1); + val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv); + writel(val, &clk->spll_con0); + while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) + ; + + writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0); + writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1); + + writel(CLK_SRC_TOP0_VAL, &clk->src_top0); + writel(CLK_SRC_TOP1_VAL, &clk->src_top1); + writel(CLK_SRC_TOP2_VAL, &clk->src_top2); + writel(CLK_SRC_TOP7_VAL, &clk->src_top7); + + writel(CLK_DIV_TOP0_VAL, &clk->div_top0); + writel(CLK_DIV_TOP1_VAL, &clk->div_top1); + writel(CLK_DIV_TOP2_VAL, &clk->div_top2); + + writel(0, &clk->src_top10); + writel(0, &clk->src_top11); + writel(0, &clk->src_top12); + + writel(CLK_SRC_TOP3_VAL, &clk->src_top3); + writel(CLK_SRC_TOP4_VAL, &clk->src_top4); + writel(CLK_SRC_TOP5_VAL, &clk->src_top5); + + /* DISP1 BLK CLK SELECTION */ + writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10); + writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10); + + /* AUDIO BLK */ + writel(AUDIO0_SEL_EPLL, &clk->src_mau); + writel(DIV_MAU_VAL, &clk->div_mau); + + /* FSYS */ + writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); + writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); + writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); + writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); + + writel(CLK_SRC_ISP_VAL, &clk->src_isp); + writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); + writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); + + writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); + writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); + + writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); + writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); + writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); + writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3); + writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4); + + writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1); + + writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio); + writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio); + writel(CLK_DIV_G2D, &clk->div_g2d); + + writel(CLK_SRC_TOP6_VAL, &clk->src_top6); + writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex); + writel(CLK_SRC_KFC_VAL, &clk->src_kfc); +} + +void system_clock_init(void) +{ + if (proid_is_exynos5420()) + exynos5420_system_clock_init(); + else + exynos5250_system_clock_init(); +} + void clock_init_dp_clock(void) { struct exynos5_clock *clk = diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 696b386..c8d6515 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -12,42 +12,16 @@ #include #include -/* APLL_CON1 */ -#define APLL_CON1_VAL (0x00203800) - -/* MPLL_CON1 */ -#define MPLL_CON1_VAL (0x00203800) - -/* CPLL_CON1 */ -#define CPLL_CON1_VAL (0x00203800) - -/* GPLL_CON1 */ -#define GPLL_CON1_VAL (0x00203800) - -/* EPLL_CON1, CON2 */ -#define EPLL_CON1_VAL 0x00000000 -#define EPLL_CON2_VAL 0x00000080 - -/* VPLL_CON1, CON2 */ -#define VPLL_CON1_VAL 0x00000000 -#define VPLL_CON2_VAL 0x00000080 +#define NOT_AVAILABLE 0 +#define DATA_MASK 0xFFFFF -/* BPLL_CON1 */ -#define BPLL_CON1_VAL 0x00203800 +#define ENABLE_BIT 0x1 +#define DISABLE_BIT 0x0 +#define CA_SWAP_EN (1 << 0) /* Set PLL */ #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) -/* CLK_SRC_CPU */ -/* 0 = MOUTAPLL, 1 = SCLKMPLL */ -#define MUX_HPM_SEL 0 -#define MUX_CPU_SEL 0 -#define MUX_APLL_SEL 1 - -#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ - | (MUX_CPU_SEL << 16) \ - | (MUX_APLL_SEL)) - /* MEMCONTROL register bit fields */ #define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0) #define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1) @@ -78,6 +52,7 @@ /* MEMCONFIG0 register bit fields */ #define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12) +#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12) #define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8) #define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4) #define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4) @@ -90,6 +65,17 @@ DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \ ) +/* + * As we use channel interleaving, therefore value of the base address + * register must be set as half of the bus base address + * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so + * we need to set half 0x10 to the membaseconfigx registers + * see exynos5420 UM section 17.17.3.21 for more. + */ +#define DMC_CHIP_BASE_0 0x10 +#define DMC_CHIP_BASE_1 0x50 +#define DMC_CHIP_MASK 0x7C0 + #define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80) @@ -113,29 +99,24 @@ /* COJCONTROL register bit fields */ #define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3) +#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3) #define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5) +#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5) #define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8) #define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8) #define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12) #define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16) #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28) -/* CLK_DIV_CPU0_VAL */ -#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \ - | (APLL_RATIO << 24) \ - | (PCLK_DBG_RATIO << 20) \ - | (ATB_RATIO << 16) \ - | (PERIPH_RATIO << 12) \ - | (ACP_RATIO << 8) \ - | (CPUD_RATIO << 4) \ - | (ARM_RATIO)) +#define DMC_CONCONTROL_VAL 0x1FFF2101 +#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \ + | DMC_CONCONTROL_AREF_EN_ENABLE \ + | DMC_CONCONTROL_IO_PD_CON_ENABLE -/* CLK_FSYS */ -#define CLK_SRC_FSYS0_VAL 0x66666 -#define CLK_DIV_FSYS0_VAL 0x0BB00000 +#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6) -/* CLK_DIV_CPU1 */ +/* CLK_DIV_CPU1 */ #define HPM_RATIO 0x2 #define COPY_RATIO 0x0 @@ -164,10 +145,367 @@ /* CLK_DIV_SYSLFT */ #define CLK_DIV_SYSLFT_VAL 0x00000311 +#define MUX_APLL_SEL_MASK (1 << 0) +#define MUX_MPLL_SEL_MASK (1 << 8) +#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8) +#define MUX_CPLL_SEL_MASK (1 << 8) +#define MUX_EPLL_SEL_MASK (1 << 12) +#define MUX_VPLL_SEL_MASK (1 << 16) +#define MUX_GPLL_SEL_MASK (1 << 28) +#define MUX_BPLL_SEL_MASK (1 << 0) +#define MUX_HPM_SEL_MASK (1 << 20) +#define HPM_SEL_SCLK_MPLL (1 << 21) +#define PLL_LOCKED (1 << 29) +#define APLL_CON0_LOCKED (1 << 29) +#define MPLL_CON0_LOCKED (1 << 29) +#define BPLL_CON0_LOCKED (1 << 29) +#define CPLL_CON0_LOCKED (1 << 29) +#define EPLL_CON0_LOCKED (1 << 29) +#define GPLL_CON0_LOCKED (1 << 29) +#define VPLL_CON0_LOCKED (1 << 29) +#define CLK_REG_DISABLE 0x0 +#define TOP2_VAL 0x0110000 + +/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */ +#define SPI0_ISP_SEL 6 +#define SPI1_ISP_SEL 6 +#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \ + | (SPI0_ISP_SEL << 0) + +/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */ +#define SPI0_ISP_RATIO 0xf +#define SPI1_ISP_RATIO 0xf +#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \ + | (SPI0_ISP_RATIO << 0) + +/* CLK_DIV_FSYS2 */ +#define MMC2_RATIO_MASK 0xf +#define MMC2_RATIO_VAL 0x3 +#define MMC2_RATIO_OFFSET 0 + +#define MMC2_PRE_RATIO_MASK 0xff +#define MMC2_PRE_RATIO_VAL 0x9 +#define MMC2_PRE_RATIO_OFFSET 8 + +#define MMC3_RATIO_MASK 0xf +#define MMC3_RATIO_VAL 0x1 +#define MMC3_RATIO_OFFSET 16 + +#define MMC3_PRE_RATIO_MASK 0xff +#define MMC3_PRE_RATIO_VAL 0x0 +#define MMC3_PRE_RATIO_OFFSET 24 + +/* CLK_SRC_LEX */ +#define CLK_SRC_LEX_VAL 0x0 + +/* CLK_DIV_LEX */ +#define CLK_DIV_LEX_VAL 0x10 + +/* CLK_DIV_R0X */ +#define CLK_DIV_R0X_VAL 0x10 + +/* CLK_DIV_L0X */ +#define CLK_DIV_R1X_VAL 0x10 + +/* CLK_DIV_ISP2 */ +#define CLK_DIV_ISP2_VAL 0x1 + +/* CLK_SRC_KFC */ +#define SRC_KFC_HPM_SEL (1 << 15) + +/* CLK_SRC_KFC */ +#define CLK_SRC_KFC_VAL 0x00008001 + +/* CLK_DIV_KFC */ +#define CLK_DIV_KFC_VAL 0x03300110 + +/* CLK_DIV2_RATIO */ +#define CLK_DIV2_RATIO 0x10111150 + +/* CLK_DIV4_RATIO */ +#define CLK_DIV4_RATIO 0x00000003 + +/* CLK_DIV_G2D */ +#define CLK_DIV_G2D 0x00000010 + +/* + * DIV_DISP1_0 + * For DP, divisor should be 2 + */ +#define CLK_DIV_DISP1_0_FIMD1 (2 << 0) + +/* CLK_GATE_IP_DISP1 */ +#define CLK_GATE_DP1_ALLOW (1 << 4) + +/* AUDIO CLK SEL */ +#define AUDIO0_SEL_EPLL (0x6 << 28) +#define AUDIO0_RATIO 0x5 +#define PCM0_RATIO 0x3 +#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20) + +/* CLK_SRC_CDREX */ +#define MUX_MCLK_CDR_MSPLL (1 << 4) +#define MUX_BPLL_SEL_FOUTBPLL (1 << 0) +#define BPLL_SEL_MASK 0x7 +#define FOUTBPLL 2 + +#define DDR3PHY_CTRL_PHY_RESET (1 << 0) +#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) + +#define PHY_CON0_RESET_VAL 0x17020a40 +#define P0_CMD_EN (1 << 14) +#define BYTE_RDLVL_EN (1 << 13) +#define CTRL_SHGATE (1 << 8) + +#define PHY_CON1_RESET_VAL 0x09210100 +#define RDLVL_PASS_ADJ_VAL 0x6 +#define RDLVL_PASS_ADJ_OFFSET 16 +#define CTRL_GATEDURADJ_MASK (0xf << 20) +#define READ_LEVELLING_DDR3 0x0100 + +#define PHY_CON2_RESET_VAL 0x00010004 +#define INIT_DESKEW_EN (1 << 6) +#define DLL_DESKEW_EN (1 << 12) +#define RDLVL_GATE_EN (1 << 24) +#define RDLVL_EN (1 << 25) +#define RDLVL_INCR_ADJ (0x1 << 16) + +/* DREX_PAUSE */ +#define DREX_PAUSE_EN (1 << 0) + +#define BYPASS_EN (1 << 22) + +/* MEMMORY VAL */ +#define PHY_CON0_VAL 0x17021A00 + +#define PHY_CON12_RESET_VAL 0x10100070 +#define PHY_CON12_VAL 0x10107F50 +#define CTRL_START (1 << 6) +#define CTRL_DLL_ON (1 << 5) +#define CTRL_FORCE_MASK (0x7F << 8) +#define CTRL_LOCK_COARSE_MASK (0x7F << 10) + +#define CTRL_OFFSETD_RESET_VAL 0x8 +#define CTRL_OFFSETD_VAL 0x7F + +#define CTRL_OFFSETR0 0x7F +#define CTRL_OFFSETR1 0x7F +#define CTRL_OFFSETR2 0x7F +#define CTRL_OFFSETR3 0x7F +#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \ + CTRL_OFFSETR1 << 8 | \ + CTRL_OFFSETR2 << 16 | \ + CTRL_OFFSETR3 << 24) +#define PHY_CON4_RESET_VAL 0x08080808 + +#define CTRL_OFFSETW0 0x7F +#define CTRL_OFFSETW1 0x7F +#define CTRL_OFFSETW2 0x7F +#define CTRL_OFFSETW3 0x7F +#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \ + CTRL_OFFSETW1 << 8 | \ + CTRL_OFFSETW2 << 16 | \ + CTRL_OFFSETW3 << 24) +#define PHY_CON6_RESET_VAL 0x08080808 + +#define PHY_CON14_RESET_VAL 0x001F0000 +#define CTRL_PULLD_DQS 0xF +#define CTRL_PULLD_DQS_OFFSET 0 + +/* ZQ Configurations */ +#define PHY_CON16_RESET_VAL 0x08000304 + +#define ZQ_CLK_EN (1 << 27) +#define ZQ_CLK_DIV_EN (1 << 18) +#define ZQ_MANUAL_STR (1 << 1) +#define ZQ_DONE (1 << 0) +#define ZQ_MODE_DDS_OFFSET 24 + +#define CTRL_RDLVL_GATE_ENABLE 1 +#define CTRL_RDLVL_GATE_DISABLE 0 +#define CTRL_RDLVL_DATA_ENABLE 2 + +/* Direct Command */ +#define DIRECT_CMD_NOP 0x07000000 +#define DIRECT_CMD_PALL 0x01000000 +#define DIRECT_CMD_ZQINIT 0x0a000000 +#define DIRECT_CMD_CHANNEL_SHIFT 28 +#define DIRECT_CMD_CHIP_SHIFT 20 +#define DIRECT_CMD_BANK_SHIFT 16 +#define DIRECT_CMD_REFA (5 << 24) +#define DIRECT_CMD_MRS1 0x71C00 +#define DIRECT_CMD_MRS2 0x10BFC +#define DIRECT_CMD_MRS3 0x0050C +#define DIRECT_CMD_MRS4 0x00868 +#define DIRECT_CMD_MRS5 0x00C04 + +/* Drive Strength */ +#define IMPEDANCE_48_OHM 4 +#define IMPEDANCE_40_OHM 5 +#define IMPEDANCE_34_OHM 6 +#define IMPEDANCE_30_OHM 7 +#define PHY_CON39_VAL_48_OHM 0x09240924 +#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D +#define PHY_CON39_VAL_34_OHM 0x0DB60DB6 +#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF + +#define CTRL_BSTLEN_OFFSET 8 +#define CTRL_RDLAT_OFFSET 0 + +#define CMD_DEFAULT_LPDDR3 0xF +#define CMD_DEFUALT_OFFSET 0 +#define T_WRDATA_EN 0x7 +#define T_WRDATA_EN_DDR3 0x8 +#define T_WRDATA_EN_OFFSET 16 +#define T_WRDATA_EN_MASK 0x1f + +#define PHY_CON31_VAL 0x0C183060 +#define PHY_CON32_VAL 0x60C18306 +#define PHY_CON33_VAL 0x00000030 + +#define PHY_CON31_RESET_VAL 0x0 +#define PHY_CON32_RESET_VAL 0x0 +#define PHY_CON33_RESET_VAL 0x0 + +#define SL_DLL_DYN_CON_EN (1 << 1) +#define FP_RESYNC (1 << 3) +#define CTRL_START (1 << 6) + +#define DMC_AREF_EN (1 << 5) +#define DMC_CONCONTROL_EMPTY (1 << 8) +#define DFI_INIT_START (1 << 28) + +#define DMC_MEMCONTROL_VAL 0x00312700 +#define CLK_STOP_EN (1 << 0) +#define DPWRDN_EN (1 << 1) +#define DSREF_EN (1 << 5) + +#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0 +#define MEMBASECONFIG_CHIP_MASK_OFFSET 0 +#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20 +#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40 +#define CHIP_BASE_OFFSET 16 + +#define MEMCONFIG_VAL 0x1323 +#define PRECHCONFIG_DEFAULT_VAL 0xFF000000 +#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF + +#define TIMINGAREF_VAL 0x5d +#define TIMINGROW_VAL 0x345A8692 +#define TIMINGDATA_VAL 0x3630065C +#define TIMINGPOWER_VAL 0x50380336 +#define DFI_INIT_COMPLETE (1 << 3) + +#define BRBRSVCONTROL_VAL 0x00000033 +#define BRBRSVCONFIG_VAL 0x88778877 + +/* Clock Gating Control (CGCONTROL) register */ +#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */ +#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */ +#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */ +#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */ +#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \ + BUSIF_WR_CG_EN | BUSIF_RD_CG_EN) + +/* DMC PHY Control0 register */ +#define PHY_CONTROL0_RESET_VAL 0x0 +#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ +#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */ +#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */ +#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */ + +/* Driver strength for CK, CKE, CS & CA */ +#define IMP_OUTPUT_DRV_40_OHM 0x5 +#define IMP_OUTPUT_DRV_30_OHM 0x7 +#define DA_3_DS_OFFSET 25 +#define DA_2_DS_OFFSET 22 +#define DA_1_DS_OFFSET 19 +#define DA_0_DS_OFFSET 16 +#define CA_CK_DRVR_DS_OFFSET 9 +#define CA_CKE_DRVR_DS_OFFSET 6 +#define CA_CS_DRVR_DS_OFFSET 3 +#define CA_ADR_DRVR_DS_OFFSET 0 + +#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 +#define PHY_CON42_CTRL_RDLAT_SHIFT 0 + +/* + * Definitions that differ with SoC's. + * Below is the part defining macros for smdk5250. + * Else part introduces macros for smdk5420. + */ +#ifndef CONFIG_SMDK5420 + +/* APLL_CON1 */ +#define APLL_CON1_VAL (0x00203800) + +/* MPLL_CON1 */ +#define MPLL_CON1_VAL (0x00203800) + +/* CPLL_CON1 */ +#define CPLL_CON1_VAL (0x00203800) + +/* DPLL_CON1 */ +#define DPLL_CON1_VAL (NOT_AVAILABLE) + +/* GPLL_CON1 */ +#define GPLL_CON1_VAL (0x00203800) + +/* EPLL_CON1, CON2 */ +#define EPLL_CON1_VAL 0x00000000 +#define EPLL_CON2_VAL 0x00000080 + +/* VPLL_CON1, CON2 */ +#define VPLL_CON1_VAL 0x00000000 +#define VPLL_CON2_VAL 0x00000080 + +/* RPLL_CON1, CON2 */ +#define RPLL_CON1_VAL NOT_AVAILABLE +#define RPLL_CON2_VAL NOT_AVAILABLE + +/* BPLL_CON1 */ +#define BPLL_CON1_VAL 0x00203800 + +/* SPLL_CON1 */ +#define SPLL_CON1_VAL NOT_AVAILABLE + +/* IPLL_CON1 */ +#define IPLL_CON1_VAL NOT_AVAILABLE + +/* KPLL_CON1 */ +#define KPLL_CON1_VAL NOT_AVAILABLE + +/* CLK_SRC_ISP */ +#define CLK_SRC_ISP_VAL NOT_AVAILABLE +#define CLK_DIV_ISP0_VAL 0x31 +#define CLK_DIV_ISP1_VAL 0x0 + +/* CLK_FSYS */ +#define CLK_SRC_FSYS0_VAL 0x66666 +#define CLK_DIV_FSYS0_VAL 0x0BB00000 +#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE +#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE + +/* CLK_SRC_CPU */ +/* 0 = MOUTAPLL, 1 = SCLKMPLL */ +#define MUX_HPM_SEL 0 +#define MUX_CPU_SEL 0 +#define MUX_APLL_SEL 1 + +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ + | (MUX_CPU_SEL << 16) \ + | (MUX_APLL_SEL)) + /* CLK_SRC_CDREX */ #define CLK_SRC_CDREX_VAL 0x1 /* CLK_DIV_CDREX */ +#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE +#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE + +/* CLK_DIV_CPU0_VAL */ +#define CLK_DIV_CPU0_VAL NOT_AVAILABLE + #define MCLK_CDREX2_RATIO 0x0 #define ACLK_EFCON_RATIO 0x1 #define MCLK_DPHY_RATIO 0x1 @@ -247,6 +585,11 @@ | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ | (MUX_ACLK_200_DISP1_SUB_SEL << 4)) +#define CLK_SRC_TOP4_VAL NOT_AVAILABLE +#define CLK_SRC_TOP5_VAL NOT_AVAILABLE +#define CLK_SRC_TOP6_VAL NOT_AVAILABLE +#define CLK_SRC_TOP7_VAL NOT_AVAILABLE + /* CLK_DIV_TOP0 */ #define ACLK_300_DISP1_RATIO 0x2 #define ACLK_400_G3D_RATIO 0x0 @@ -279,40 +622,11 @@ | (ACLK_400_IOP_RATIO << 16) \ | (ACLK_300_GSCL_RATIO << 12)) -/* APLL_LOCK */ -#define APLL_LOCK_VAL (0x546) -/* MPLL_LOCK */ -#define MPLL_LOCK_VAL (0x546) -/* CPLL_LOCK */ -#define CPLL_LOCK_VAL (0x546) -/* GPLL_LOCK */ -#define GPLL_LOCK_VAL (0x546) -/* EPLL_LOCK */ -#define EPLL_LOCK_VAL (0x3A98) -/* VPLL_LOCK */ -#define VPLL_LOCK_VAL (0x3A98) -/* BPLL_LOCK */ -#define BPLL_LOCK_VAL (0x546) +#define CLK_DIV_TOP2_VAL NOT_AVAILABLE -#define MUX_APLL_SEL_MASK (1 << 0) -#define MUX_MPLL_SEL_MASK (1 << 8) -#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8) -#define MUX_CPLL_SEL_MASK (1 << 8) -#define MUX_EPLL_SEL_MASK (1 << 12) -#define MUX_VPLL_SEL_MASK (1 << 16) -#define MUX_GPLL_SEL_MASK (1 << 28) -#define MUX_BPLL_SEL_MASK (1 << 0) -#define MUX_HPM_SEL_MASK (1 << 20) -#define HPM_SEL_SCLK_MPLL (1 << 21) -#define APLL_CON0_LOCKED (1 << 29) -#define MPLL_CON0_LOCKED (1 << 29) -#define BPLL_CON0_LOCKED (1 << 29) -#define CPLL_CON0_LOCKED (1 << 29) -#define EPLL_CON0_LOCKED (1 << 29) -#define GPLL_CON0_LOCKED (1 << 29) -#define VPLL_CON0_LOCKED (1 << 29) -#define CLK_REG_DISABLE 0x0 -#define TOP2_VAL 0x0110000 +/* PLL Lock Value Factor */ +#define PLL_LOCK_FACTOR 250 +#define PLL_X_LOCK_FACTOR 3000 /* CLK_SRC_PERIC0 */ #define PWM_SEL 6 @@ -336,18 +650,6 @@ | (SPI1_SEL << 20) \ | (SPI0_SEL << 16)) -/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */ -#define SPI0_ISP_SEL 6 -#define SPI1_ISP_SEL 6 -#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \ - | (SPI0_ISP_SEL << 0) - -/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */ -#define SPI0_ISP_RATIO 0xf -#define SPI1_ISP_RATIO 0xf -#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \ - | (SPI0_ISP_RATIO << 0) - /* CLK_DIV_PERIL0 */ #define UART5_RATIO 7 #define UART4_RATIO 7 @@ -380,105 +682,200 @@ #define PWM_RATIO 8 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0) -/* CLK_DIV_FSYS2 */ -#define MMC2_RATIO_MASK 0xf -#define MMC2_RATIO_VAL 0x3 -#define MMC2_RATIO_OFFSET 0 -#define MMC2_PRE_RATIO_MASK 0xff -#define MMC2_PRE_RATIO_VAL 0x9 -#define MMC2_PRE_RATIO_OFFSET 8 +/* CLK_DIV_PERIC4 */ +#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE -#define MMC3_RATIO_MASK 0xf -#define MMC3_RATIO_VAL 0x1 -#define MMC3_RATIO_OFFSET 16 +/* CLK_SRC_DISP1_0 */ +#define CLK_SRC_DISP1_0_VAL 0x6 +#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE -#define MMC3_PRE_RATIO_MASK 0xff -#define MMC3_PRE_RATIO_VAL 0x0 -#define MMC3_PRE_RATIO_OFFSET 24 +#define APLL_FOUT (1 << 0) +#define KPLL_FOUT NOT_AVAILABLE -/* CLK_SRC_LEX */ -#define CLK_SRC_LEX_VAL 0x0 +#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE -/* CLK_DIV_LEX */ -#define CLK_DIV_LEX_VAL 0x10 +#else -/* CLK_DIV_R0X */ -#define CLK_DIV_R0X_VAL 0x10 +/* APLL_CON1 */ +#define APLL_CON1_VAL (0x0020F300) -/* CLK_DIV_L0X */ -#define CLK_DIV_R1X_VAL 0x10 +/* MPLL_CON1 */ +#define MPLL_CON1_VAL (0x0020F300) -/* CLK_DIV_ISP0 */ -#define CLK_DIV_ISP0_VAL 0x31 -/* CLK_DIV_ISP1 */ -#define CLK_DIV_ISP1_VAL 0x0 +/* CPLL_CON1 */ +#define CPLL_CON1_VAL 0x0020f300 -/* CLK_DIV_ISP2 */ -#define CLK_DIV_ISP2_VAL 0x1 +/* DPLL_CON1 */ +#define DPLL_CON1_VAL (0x0020F300) -/* CLK_SRC_DISP1_0 */ -#define CLK_SRC_DISP1_0_VAL 0x6 +/* GPLL_CON1 */ +#define GPLL_CON1_VAL (NOT_AVAILABLE) -/* - * DIV_DISP1_0 - * For DP, divisor should be 2 - */ -#define CLK_DIV_DISP1_0_FIMD1 (2 << 0) -/* CLK_GATE_IP_DISP1 */ -#define CLK_GATE_DP1_ALLOW (1 << 4) +/* EPLL_CON1, CON2 */ +#define EPLL_CON1_VAL 0x00000000 +#define EPLL_CON2_VAL 0x00000080 -#define DDR3PHY_CTRL_PHY_RESET (1 << 0) -#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) +/* VPLL_CON1, CON2 */ +#define VPLL_CON1_VAL 0x0020f300 +#define VPLL_CON2_VAL NOT_AVAILABLE -#define PHY_CON0_RESET_VAL 0x17020a40 -#define P0_CMD_EN (1 << 14) -#define BYTE_RDLVL_EN (1 << 13) -#define CTRL_SHGATE (1 << 8) +/* RPLL_CON1, CON2 */ +#define RPLL_CON1_VAL 0x00000000 +#define RPLL_CON2_VAL 0x00000080 -#define PHY_CON1_RESET_VAL 0x09210100 -#define CTRL_GATEDURADJ_MASK (0xf << 20) +/* BPLL_CON1 */ +#define BPLL_CON1_VAL 0x0020f300 -#define PHY_CON2_RESET_VAL 0x00010004 -#define INIT_DESKEW_EN (1 << 6) -#define RDLVL_GATE_EN (1 << 24) +/* SPLL_CON1 */ +#define SPLL_CON1_VAL 0x0020f300 -/*ZQ Configurations */ -#define PHY_CON16_RESET_VAL 0x08000304 +/* IPLL_CON1 */ +#define IPLL_CON1_VAL 0x00000080 -#define ZQ_CLK_DIV_EN (1 << 18) -#define ZQ_MANUAL_STR (1 << 1) -#define ZQ_DONE (1 << 0) +/* KPLL_CON1 */ +#define KPLL_CON1_VAL 0x200000 -#define CTRL_RDLVL_GATE_ENABLE 1 -#define CTRL_RDLVL_GATE_DISABLE 1 +/* CLK_SRC_ISP */ +#define CLK_SRC_ISP_VAL 0x33366000 +#define CLK_DIV_ISP0_VAL 0x13131300 +#define CLK_DIV_ISP1_VAL 0xbb110202 -/* Direct Command */ -#define DIRECT_CMD_NOP 0x07000000 -#define DIRECT_CMD_PALL 0x01000000 -#define DIRECT_CMD_ZQINIT 0x0a000000 -#define DIRECT_CMD_CHANNEL_SHIFT 28 -#define DIRECT_CMD_CHIP_SHIFT 20 -/* DMC PHY Control0 register */ -#define PHY_CONTROL0_RESET_VAL 0x0 -#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ -#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */ -#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */ -#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */ +/* CLK_FSYS */ +#define CLK_SRC_FSYS0_VAL 0x33033300 +#define CLK_DIV_FSYS0_VAL 0x0 +#define CLK_DIV_FSYS1_VAL 0x04f13c4f +#define CLK_DIV_FSYS2_VAL 0x041d0000 + +/* CLK_SRC_CPU */ +/* 0 = MOUTAPLL, 1 = SCLKMPLL */ +#define MUX_HPM_SEL 1 +#define MUX_CPU_SEL 0 +#define MUX_APLL_SEL 1 -/* Driver strength for CK, CKE, CS & CA */ -#define IMP_OUTPUT_DRV_40_OHM 0x5 -#define IMP_OUTPUT_DRV_30_OHM 0x7 -#define CA_CK_DRVR_DS_OFFSET 9 -#define CA_CKE_DRVR_DS_OFFSET 6 -#define CA_CS_DRVR_DS_OFFSET 3 -#define CA_ADR_DRVR_DS_OFFSET 0 +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ + | (MUX_CPU_SEL << 16) \ + | (MUX_APLL_SEL)) -#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 -#define PHY_CON42_CTRL_RDLAT_SHIFT 0 +/* CLK_SRC_CDREX */ +#define CLK_SRC_CDREX_VAL 0x00000011 + +/* CLK_DIV_CDREX */ +#define CLK_DIV_CDREX0_VAL 0x30010100 +#define CLK_DIV_CDREX1_VAL 0x300 + +#define CLK_DIV_CDREX_VAL 0x17010100 + +/* CLK_DIV_CPU0_VAL */ +#define CLK_DIV_CPU0_VAL 0x01440020 + +/* CLK_SRC_TOP */ +#define CLK_SRC_TOP0_VAL 0x12221222 +#define CLK_SRC_TOP1_VAL 0x00100200 +#define CLK_SRC_TOP2_VAL 0x11101000 +#define CLK_SRC_TOP3_VAL 0x11111111 +#define CLK_SRC_TOP4_VAL 0x11110111 +#define CLK_SRC_TOP5_VAL 0x11111100 +#define CLK_SRC_TOP6_VAL 0x11110111 +#define CLK_SRC_TOP7_VAL 0x00022200 + +/* CLK_DIV_TOP */ +#define CLK_DIV_TOP0_VAL 0x23712311 +#define CLK_DIV_TOP1_VAL 0x13100B00 +#define CLK_DIV_TOP2_VAL 0x11101100 + +/* PLL Lock Value Factor */ +#define PLL_LOCK_FACTOR 200 +#define PLL_X_LOCK_FACTOR 3000 + +/* CLK_SRC_PERIC0 */ +#define SPDIF_SEL 1 +#define PWM_SEL 3 +#define UART4_SEL 3 +#define UART3_SEL 3 +#define UART2_SEL 3 +#define UART1_SEL 3 +#define UART0_SEL 3 +/* SRC_CLOCK = SCLK_RPLL */ +#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \ + | (PWM_SEL << 24) \ + | (UART4_SEL << 20) \ + | (UART3_SEL << 16) \ + | (UART2_SEL << 12) \ + | (UART1_SEL << 8) \ + | (UART0_SEL << 4)) + +/* CLK_SRC_PERIC1 */ +/* SRC_CLOCK = SCLK_EPLL */ +#define SPI0_SEL 6 +#define SPI1_SEL 6 +#define SPI2_SEL 6 +#define AUDIO0_SEL 6 +#define AUDIO1_SEL 6 +#define AUDIO2_SEL 6 +#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \ + | (SPI1_SEL << 24) \ + | (SPI0_SEL << 20) \ + | (AUDIO2_SEL << 16) \ + | (AUDIO2_SEL << 12) \ + | (AUDIO2_SEL << 8)) + +/* CLK_DIV_PERIC0 */ +#define PWM_RATIO 8 +#define UART4_RATIO 9 +#define UART3_RATIO 9 +#define UART2_RATIO 9 +#define UART1_RATIO 9 +#define UART0_RATIO 9 + +#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \ + | (UART4_RATIO << 24) \ + | (UART3_RATIO << 20) \ + | (UART2_RATIO << 16) \ + | (UART1_RATIO << 12) \ + | (UART0_RATIO << 8)) +/* CLK_DIV_PERIC1 */ +#define SPI2_RATIO 0x1 +#define SPI1_RATIO 0x1 +#define SPI0_RATIO 0x1 +#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \ + | (SPI1_RATIO << 24) \ + | (SPI0_RATIO << 20)) + +/* CLK_DIV_PERIC2 */ +#define PCM2_RATIO 0x3 +#define PCM1_RATIO 0x3 +#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \ + | (PCM1_RATIO << 16)) + +/* CLK_DIV_PERIC3 */ +#define AUDIO2_RATIO 0x5 +#define AUDIO1_RATIO 0x5 +#define AUDIO0_RATIO 0x5 +#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \ + | (AUDIO1_RATIO << 24) \ + | (AUDIO0_RATIO << 20)) + +/* CLK_DIV_PERIC4 */ +#define SPI2_PRE_RATIO 0x2 +#define SPI1_PRE_RATIO 0x2 +#define SPI0_PRE_RATIO 0x2 +#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \ + | (SPI1_PRE_RATIO << 16) \ + | (SPI0_PRE_RATIO << 8)) + +/* CLK_SRC_DISP1_0 */ +#define CLK_SRC_DISP1_0_VAL 0x10666600 +#define CLK_DIV_DISP1_0_VAL 0x01050211 + +#define APLL_FOUT (1 << 0) +#define KPLL_FOUT (1 << 0) + +#define CLK_DIV_CPERI1_VAL 0x3f3f0000 +#endif struct mem_timings; @@ -490,7 +887,7 @@ enum { }; /* - * Memory variant specific initialization code + * Memory variant specific initialization code for DDR3 * * @param mem Memory timings for this memory type. * @param mem_iv_size Memory interleaving size is a configurable parameter @@ -503,6 +900,9 @@ enum { int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, int reset); +/* Memory variant specific initialization code for LPDDR3 */ +void lpddr3_mem_ctrl_init(void); + /* * Configure ZQ I/O interface * @@ -532,14 +932,6 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc); void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc); /* - * Configure the memconfig and membaseconfig registers - * - * @param mem Memory timings for this memory type. - * @param exynos5_dmc Pointer to struct of DMC registers - */ -void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc); - -/* * Reset the DLL. This function is common between DDR3 and LPDDR2. * However, the reset value is different. So we are passing a flag * ddr_mode to distinguish between LPDDR2 and DDR3. diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 1d6fa93..cdeef32 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -14,6 +14,7 @@ #define HPLL 3 #define VPLL 4 #define BPLL 5 +#define RPLL 6 enum pll_src_bit { EXYNOS_SRC_MPLL = 6, diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index cf26eef..8259b92 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -858,6 +858,500 @@ struct exynos5_clock { unsigned char res123[0xf5d8]; }; +struct exynos5420_clock { + unsigned int apll_lock; /* 0x10010000 */ + unsigned char res1[0xfc]; + unsigned int apll_con0; + unsigned int apll_con1; + unsigned char res2[0xf8]; + unsigned int src_cpu; + unsigned char res3[0x1fc]; + unsigned int mux_stat_cpu; + unsigned char res4[0xfc]; + unsigned int div_cpu0; /* 0x10010500 */ + unsigned int div_cpu1; + unsigned char res5[0xf8]; + unsigned int div_stat_cpu0; + unsigned int div_stat_cpu1; + unsigned char res6[0xf8]; + unsigned int gate_bus_cpu; + unsigned char res7[0xfc]; + unsigned int gate_sclk_cpu; + unsigned char res8[0x1fc]; + unsigned int clkout_cmu_cpu; /* 0x10010a00 */ + unsigned int clkout_cmu_cpu_div_stat; + unsigned char res9[0x5f8]; + unsigned int armclk_stopctrl; + unsigned char res10[0x4]; + unsigned int arm_ema_ctrl; + unsigned int arm_ema_status; + unsigned char res11[0x10]; + unsigned int pwr_ctrl; + unsigned int pwr_ctrl2; + unsigned char res12[0xd8]; + unsigned int apll_con0_l8; /* 0x1001100 */ + unsigned int apll_con0_l7; + unsigned int apll_con0_l6; + unsigned int apll_con0_l5; + unsigned int apll_con0_l4; + unsigned int apll_con0_l3; + unsigned int apll_con0_l2; + unsigned int apll_con0_l1; + unsigned int iem_control; + unsigned char res13[0xdc]; + unsigned int apll_con1_l8; /* 0x10011200 */ + unsigned int apll_con1_l7; + unsigned int apll_con1_l6; + unsigned int apll_con1_l5; + unsigned int apll_con1_l4; + unsigned int apll_con1_l3; + unsigned int apll_con1_l2; + unsigned int apll_con1_l1; + unsigned char res14[0xe0]; + unsigned int clkdiv_iem_l8; + unsigned int clkdiv_iem_l7; /* 0x10011304 */ + unsigned int clkdiv_iem_l6; + unsigned int clkdiv_iem_l5; + unsigned int clkdiv_iem_l4; + unsigned int clkdiv_iem_l3; + unsigned int clkdiv_iem_l2; + unsigned int clkdiv_iem_l1; + unsigned char res15[0xe0]; + unsigned int l2_status; + unsigned char res16[0x0c]; + unsigned int cpu_status; /* 0x10011410 */ + unsigned char res17[0x0c]; + unsigned int ptm_status; + unsigned char res18[0xbdc]; + unsigned int cmu_cpu_spare0; + unsigned int cmu_cpu_spare1; + unsigned int cmu_cpu_spare2; + unsigned int cmu_cpu_spare3; + unsigned int cmu_cpu_spare4; + unsigned char res19[0x1fdc]; + unsigned int cmu_cpu_version; + unsigned char res20[0x20c]; + unsigned int src_cperi0; /* 0x10014200 */ + unsigned int src_cperi1; + unsigned char res21[0xf8]; + unsigned int src_mask_cperi; + unsigned char res22[0x100]; + unsigned int mux_stat_cperi1; + unsigned char res23[0xfc]; + unsigned int div_cperi1; + unsigned char res24[0xfc]; + unsigned int div_stat_cperi1; + unsigned char res25[0xf8]; + unsigned int gate_bus_cperi0; /* 0x10014700 */ + unsigned int gate_bus_cperi1; + unsigned char res26[0xf8]; + unsigned int gate_sclk_cperi; + unsigned char res27[0xfc]; + unsigned int gate_ip_cperi; + unsigned char res28[0xfc]; + unsigned int clkout_cmu_cperi; + unsigned int clkout_cmu_cperi_div_stat; + unsigned char res29[0x5f8]; + unsigned int dcgidx_map0; /* 0x10015000 */ + unsigned int dcgidx_map1; + unsigned int dcgidx_map2; + unsigned char res30[0x14]; + unsigned int dcgperf_map0; + unsigned int dcgperf_map1; + unsigned char res31[0x18]; + unsigned int dvcidx_map; + unsigned char res32[0x1c]; + unsigned int freq_cpu; + unsigned int freq_dpm; + unsigned char res33[0x18]; + unsigned int dvsemclk_en; /* 0x10015080 */ + unsigned int maxperf; + unsigned char res34[0x2e78]; + unsigned int cmu_cperi_spare0; + unsigned int cmu_cperi_spare1; + unsigned int cmu_cperi_spare2; + unsigned int cmu_cperi_spare3; + unsigned int cmu_cperi_spare4; + unsigned int cmu_cperi_spare5; + unsigned int cmu_cperi_spare6; + unsigned int cmu_cperi_spare7; + unsigned int cmu_cperi_spare8; + unsigned char res35[0xcc]; + unsigned int cmu_cperi_version; /* 0x10017ff0 */ + unsigned char res36[0x50c]; + unsigned int div_g2d; + unsigned char res37[0xfc]; + unsigned int div_stat_g2d; + unsigned char res38[0xfc]; + unsigned int gate_bus_g2d; + unsigned char res39[0xfc]; + unsigned int gate_ip_g2d; + unsigned char res40[0x1fc]; + unsigned int clkout_cmu_g2d; + unsigned int clkout_cmu_g2d_div_stat; /* 0x10018a04 */ + unsigned char res41[0xf8]; + unsigned int cmu_g2d_spare0; + unsigned int cmu_g2d_spare1; + unsigned int cmu_g2d_spare2; + unsigned int cmu_g2d_spare3; + unsigned int cmu_g2d_spare4; + unsigned char res42[0x34dc]; + unsigned int cmu_g2d_version; + unsigned char res43[0x30c]; + unsigned int div_cmu_isp0; + unsigned int div_cmu_isp1; + unsigned int div_isp2; /* 0x1001c308 */ + unsigned char res44[0xf4]; + unsigned int div_stat_cmu_isp0; + unsigned int div_stat_cmu_isp1; + unsigned int div_stat_isp2; + unsigned char res45[0x2f4]; + unsigned int gate_bus_isp0; + unsigned int gate_bus_isp1; + unsigned int gate_bus_isp2; + unsigned int gate_bus_isp3; + unsigned char res46[0xf0]; + unsigned int gate_ip_isp0; + unsigned int gate_ip_isp1; + unsigned char res47[0xf8]; + unsigned int gate_sclk_isp; + unsigned char res48[0x0c]; + unsigned int mcuisp_pwr_ctrl; /* 0x1001c910 */ + unsigned char res49[0x0ec]; + unsigned int clkout_cmu_isp; + unsigned int clkout_cmu_isp_div_stat; + unsigned char res50[0xf8]; + unsigned int cmu_isp_spare0; + unsigned int cmu_isp_spare1; + unsigned int cmu_isp_spare2; + unsigned int cmu_isp_spare3; + unsigned char res51[0x34e0]; + unsigned int cmu_isp_version; + unsigned char res52[0x2c]; + unsigned int cpll_lock; /* 10020020 */ + unsigned char res53[0xc]; + unsigned int dpll_lock; + unsigned char res54[0xc]; + unsigned int epll_lock; + unsigned char res55[0xc]; + unsigned int rpll_lock; + unsigned char res56[0xc]; + unsigned int ipll_lock; + unsigned char res57[0xc]; + unsigned int spll_lock; + unsigned char res58[0xc]; + unsigned int vpll_lock; + unsigned char res59[0xc]; + unsigned int mpll_lock; + unsigned char res60[0x8c]; + unsigned int cpll_con0; /* 10020120 */ + unsigned int cpll_con1; + unsigned int dpll_con0; + unsigned int dpll_con1; + unsigned int epll_con0; + unsigned int epll_con1; + unsigned int epll_con2; + unsigned char res601[0x4]; + unsigned int rpll_con0; + unsigned int rpll_con1; + unsigned int rpll_con2; + unsigned char res602[0x4]; + unsigned int ipll_con0; + unsigned int ipll_con1; + unsigned char res61[0x8]; + unsigned int spll_con0; + unsigned int spll_con1; + unsigned char res62[0x8]; + unsigned int vpll_con0; + unsigned int vpll_con1; + unsigned char res63[0x8]; + unsigned int mpll_con0; + unsigned int mpll_con1; + unsigned char res64[0x78]; + unsigned int src_top0; /* 0x10020200 */ + unsigned int src_top1; + unsigned int src_top2; + unsigned int src_top3; + unsigned int src_top4; + unsigned int src_top5; + unsigned int src_top6; + unsigned int src_top7; + unsigned char res65[0xc]; + unsigned int src_disp10; /* 0x1002022c */ + unsigned char res66[0x10]; + unsigned int src_mau; + unsigned int src_fsys; + unsigned char res67[0x8]; + unsigned int src_peric0; + unsigned int src_peric1; + unsigned char res68[0x18]; + unsigned int src_isp; + unsigned char res69[0x0c]; + unsigned int src_top10; + unsigned int src_top11; + unsigned int src_top12; + unsigned char res70[0x74]; + unsigned int src_mask_top0; + unsigned int src_mask_top1; + unsigned int src_mask_top2; + unsigned char res71[0x10]; + unsigned int src_mask_top7; + unsigned char res72[0xc]; + unsigned int src_mask_disp10; /* 0x1002032c */ + unsigned char res73[0x4]; + unsigned int src_mask_mau; + unsigned char res74[0x8]; + unsigned int src_mask_fsys; + unsigned char res75[0xc]; + unsigned int src_mask_peric0; + unsigned int src_mask_peric1; + unsigned char res76[0x18]; + unsigned int src_mask_isp; + unsigned char res77[0x8c]; + unsigned int mux_stat_top0; /* 0x10020400 */ + unsigned int mux_stat_top1; + unsigned int mux_stat_top2; + unsigned int mux_stat_top3; + unsigned int mux_stat_top4; + unsigned int mux_stat_top5; + unsigned int mux_stat_top6; + unsigned int mux_stat_top7; + unsigned char res78[0x60]; + unsigned int mux_stat_top10; + unsigned int mux_stat_top11; + unsigned int mux_stat_top12; + unsigned char res79[0x74]; + unsigned int div_top0; /* 0x10020500 */ + unsigned int div_top1; + unsigned int div_top2; + unsigned char res80[0x20]; + unsigned int div_disp10; + unsigned char res81[0x14]; + unsigned int div_mau; + unsigned int div_fsys0; + unsigned int div_fsys1; + unsigned int div_fsys2; + unsigned char res82[0x4]; + unsigned int div_peric0; + unsigned int div_peric1; + unsigned int div_peric2; + unsigned int div_peric3; + unsigned int div_peric4; /* 0x10020568 */ + unsigned char res83[0x14]; + unsigned int div_isp0; + unsigned int div_isp1; + unsigned char res84[0x8]; + unsigned int clkdiv2_ratio; + unsigned char res850[0xc]; + unsigned int clkdiv4_ratio; + unsigned char res85[0x5c]; + unsigned int div_stat_top0; + unsigned int div_stat_top1; + unsigned int div_stat_top2; + unsigned char res86[0x20]; + unsigned int div_stat_disp10; + unsigned char res87[0x14]; + unsigned int div_stat_mau; /* 0x10020644 */ + unsigned int div_stat_fsys0; + unsigned int div_stat_fsys1; + unsigned int div_stat_fsys2; + unsigned char res88[0x4]; + unsigned int div_stat_peric0; + unsigned int div_stat_peric1; + unsigned int div_stat_peric2; + unsigned int div_stat_peric3; + unsigned int div_stat_peric4; + unsigned char res89[0x14]; + unsigned int div_stat_isp0; + unsigned int div_stat_isp1; + unsigned char res90[0x8]; + unsigned int clkdiv2_stat0; + unsigned char res91[0xc]; + unsigned int clkdiv4_stat; + unsigned char res92[0x5c]; + unsigned int gate_bus_top; /* 0x10020700 */ + unsigned char res93[0xc]; + unsigned int gate_bus_gscl0; + unsigned char res94[0xc]; + unsigned int gate_bus_gscl1; + unsigned char res95[0x4]; + unsigned int gate_bus_disp1; + unsigned char res96[0x4]; + unsigned int gate_bus_wcore; + unsigned int gate_bus_mfc; + unsigned int gate_bus_g3d; + unsigned int gate_bus_gen; + unsigned int gate_bus_fsys0; + unsigned int gate_bus_fsys1; + unsigned int gate_bus_fsys2; + unsigned int gate_bus_mscl; + unsigned int gate_bus_peric; + unsigned int gate_bus_peric1; + unsigned char res97[0x8]; + unsigned int gate_bus_peris0; + unsigned int gate_bus_peris1; /* 0x10020764 */ + unsigned char res98[0x8]; + unsigned int gate_bus_noc; + unsigned char res99[0xac]; + unsigned int gate_top_sclk_gscl; + unsigned char res1000[0x4]; + unsigned int gate_top_sclk_disp1; + unsigned char res100[0x10]; + unsigned int gate_top_sclk_mau; + unsigned int gate_top_sclk_fsys; + unsigned char res101[0xc]; + unsigned int gate_top_sclk_peric; + unsigned char res102[0xc]; + unsigned int gate_top_sclk_cperi; + unsigned char res103[0xc]; + unsigned int gate_top_sclk_isp; + unsigned char res104[0x9c]; + unsigned int gate_ip_gscl0; + unsigned char res105[0xc]; + unsigned int gate_ip_gscl1; + unsigned char res106[0x4]; + unsigned int gate_ip_disp1; + unsigned int gate_ip_mfc; + unsigned int gate_ip_g3d; + unsigned int gate_ip_gen; /* 0x10020934 */ + unsigned char res107[0xc]; + unsigned int gate_ip_fsys; + unsigned char res108[0x8]; + unsigned int gate_ip_peric; + unsigned char res109[0xc]; + unsigned int gate_ip_peris; + unsigned char res110[0xc]; + unsigned int gate_ip_mscl; + unsigned char res111[0xc]; + unsigned int gate_ip_block; + unsigned char res112[0xc]; + unsigned int bypass; + unsigned char res113[0x6c]; + unsigned int clkout_cmu_top; + unsigned int clkout_cmu_top_div_stat; + unsigned char res114[0xf8]; + unsigned int clkout_top_spare0; + unsigned int clkout_top_spare1; + unsigned int clkout_top_spare2; + unsigned int clkout_top_spare3; + unsigned char res115[0x34e0]; + unsigned int clkout_top_version; + unsigned char res116[0xc01c]; + unsigned int bpll_lock; /* 0x10030010 */ + unsigned char res117[0xfc]; + unsigned int bpll_con0; + unsigned int bpll_con1; + unsigned char res118[0xe8]; + unsigned int src_cdrex; + unsigned char res119[0x1fc]; + unsigned int mux_stat_cdrex; + unsigned char res120[0xfc]; + unsigned int div_cdrex0; + unsigned int div_cdrex1; + unsigned char res121[0xf8]; + unsigned int div_stat_cdrex; + unsigned char res1211[0xfc]; + unsigned int gate_bus_cdrex; + unsigned int gate_bus_cdrex1; + unsigned char res122[0x1f8]; + unsigned int gate_ip_cdrex; + unsigned char res123[0x10]; + unsigned int dmc_freq_ctrl; /* 0x10030914 */ + unsigned char res124[0x4]; + unsigned int pause; + unsigned int ddrphy_lock_ctrl; + unsigned char res125[0xdc]; + unsigned int clkout_cmu_cdrex; + unsigned int clkout_cmu_cdrex_div_stat; + unsigned char res126[0x8]; + unsigned int lpddr3phy_ctrl; + unsigned int lpddr3phy_con0; + unsigned int lpddr3phy_con1; + unsigned int lpddr3phy_con2; + unsigned int lpddr3phy_con3; + unsigned int lpddr3phy_con4; + unsigned int lpddr3phy_con5; /* 0x10030a28 */ + unsigned int pll_div2_sel; + unsigned char res127[0xd0]; + unsigned int cmu_cdrex_spare0; + unsigned int cmu_cdrex_spare1; + unsigned int cmu_cdrex_spare2; + unsigned int cmu_cdrex_spare3; + unsigned int cmu_cdrex_spare4; + unsigned char res128[0x34dc]; + unsigned int cmu_cdrex_version; /* 0x10033ff0 */ + unsigned char res129[0x400c]; + unsigned int kpll_lock; + unsigned char res130[0xfc]; + unsigned int kpll_con0; + unsigned int kpll_con1; + unsigned char res131[0xf8]; + unsigned int src_kfc; + unsigned char res132[0x1fc]; + unsigned int mux_stat_kfc; /* 0x10038400 */ + unsigned char res133[0xfc]; + unsigned int div_kfc0; + unsigned char res134[0xfc]; + unsigned int div_stat_kfc0; + unsigned char res135[0xfc]; + unsigned int gate_bus_cpu_kfc; + unsigned char res136[0xfc]; + unsigned int gate_sclk_cpu_kfc; + unsigned char res137[0x1fc]; + unsigned int clkout_cmu_kfc; + unsigned int clkout_cmu_kfc_div_stat; /* 0x10038a04 */ + unsigned char res138[0x5f8]; + unsigned int armclk_stopctrl_kfc; + unsigned char res139[0x4]; + unsigned int armclk_ema_ctrl_kfc; + unsigned int armclk_ema_status_kfc; + unsigned char res140[0x10]; + unsigned int pwr_ctrl_kfc; + unsigned int pwr_ctrl2_kfc; + unsigned char res141[0xd8]; + unsigned int kpll_con0_l8; + unsigned int kpll_con0_l7; + unsigned int kpll_con0_l6; + unsigned int kpll_con0_l5; + unsigned int kpll_con0_l4; + unsigned int kpll_con0_l3; + unsigned int kpll_con0_l2; + unsigned int kpll_con0_l1; + unsigned int iem_control_kfc; /* 0x10039120 */ + unsigned char res142[0xdc]; + unsigned int kpll_con1_l8; + unsigned int kpll_con1_l7; + unsigned int kpll_con1_l6; + unsigned int kpll_con1_l5; + unsigned int kpll_con1_l4; + unsigned int kpll_con1_l3; + unsigned int kpll_con1_l2; + unsigned int kpll_con1_l1; + unsigned char res143[0xe0]; + unsigned int clkdiv_iem_l8_kfc; /* 0x10039300 */ + unsigned int clkdiv_iem_l7_kfc; + unsigned int clkdiv_iem_l6_kfc; + unsigned int clkdiv_iem_l5_kfc; + unsigned int clkdiv_iem_l4_kfc; + unsigned int clkdiv_iem_l3_kfc; + unsigned int clkdiv_iem_l2_kfc; + unsigned int clkdiv_iem_l1_kfc; + unsigned char res144[0xe0]; + unsigned int l2_status_kfc; + unsigned char res145[0xc]; + unsigned int cpu_status_kfc; /* 0x10039410 */ + unsigned char res146[0xc]; + unsigned int ptm_status_kfc; + unsigned char res147[0xbdc]; + unsigned int cmu_kfc_spare0; + unsigned int cmu_kfc_spare1; + unsigned int cmu_kfc_spare2; + unsigned int cmu_kfc_spare3; + unsigned int cmu_kfc_spare4; + unsigned char res148[0x1fdc]; + unsigned int cmu_kfc_version; /* 0x1003bff0 */ +}; + /* structure for epll configuration used in audio clock configuration */ struct set_epll_con_val { unsigned int freq_out; /* frequency out */ -- cgit v0.10.2 From f3d7c2fe9da9b03230cecd634ddbbb2654f3d13d Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:22 +0530 Subject: Exynos5420: Add DDR3 initialization for 5420 This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c index 53cfe6e..cca925e 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_common.c +++ b/arch/arm/cpu/armv7/exynos/dmc_common.c @@ -1,5 +1,5 @@ /* - * Mem setup common file for different types of DDR present on SMDK5250 boards. + * Mem setup common file for different types of DDR present on Exynos boards. * * Copyright (C) 2012 Samsung Electronics * @@ -15,9 +15,9 @@ #define ZQ_INIT_TIMEOUT 10000 -int dmc_config_zq(struct mem_timings *mem, - struct exynos5_phy_control *phy0_ctrl, - struct exynos5_phy_control *phy1_ctrl) +int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16, + uint32_t *phy1_con16, uint32_t *phy0_con17, + uint32_t *phy1_con17) { unsigned long val = 0; int i; @@ -31,19 +31,19 @@ int dmc_config_zq(struct mem_timings *mem, val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; val |= ZQ_CLK_DIV_EN; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + writel(val, phy0_con16); + writel(val, phy1_con16); /* Disable termination */ if (mem->zq_mode_noterm) val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + writel(val, phy0_con16); + writel(val, phy1_con16); /* ZQ_MANUAL_START: Enable */ val |= ZQ_MANUAL_STR; - writel(val, &phy0_ctrl->phy_con16); - writel(val, &phy1_ctrl->phy_con16); + writel(val, phy0_con16); + writel(val, phy1_con16); /* ZQ_MANUAL_START: Disable */ val &= ~ZQ_MANUAL_STR; @@ -53,47 +53,47 @@ int dmc_config_zq(struct mem_timings *mem, * we are looping for the ZQ_init to complete. */ i = ZQ_INIT_TIMEOUT; - while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((readl(phy0_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { sdelay(100); i--; } if (!i) return -1; - writel(val, &phy0_ctrl->phy_con16); + writel(val, phy0_con16); i = ZQ_INIT_TIMEOUT; - while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { + while ((readl(phy1_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { sdelay(100); i--; } if (!i) return -1; - writel(val, &phy1_ctrl->phy_con16); + writel(val, phy1_con16); return 0; } -void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) +void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode) { unsigned long val; if (mode == DDR_MODE_DDR3) { val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE; - writel(val, &dmc->phycontrol0); + writel(val, phycontrol0); } /* Update DLL Information: Force DLL Resyncronization */ - val = readl(&dmc->phycontrol0); + val = readl(phycontrol0); val |= FP_RSYNC; - writel(val, &dmc->phycontrol0); + writel(val, phycontrol0); /* Reset Force DLL Resyncronization */ - val = readl(&dmc->phycontrol0); + val = readl(phycontrol0); val &= ~FP_RSYNC; - writel(val, &dmc->phycontrol0); + writel(val, phycontrol0); } -void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) +void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd) { int channel, chip; @@ -107,7 +107,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* Sending NOP command */ - writel(DIRECT_CMD_NOP | mask, &dmc->directcmd); + writel(DIRECT_CMD_NOP | mask, directcmd); /* * TODO(alim.akhtar@samsung.com): Do we need these @@ -119,14 +119,14 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { writel(mem->direct_cmd_msr[i] | mask, - &dmc->directcmd); + directcmd); sdelay(0x10000); } if (mem->send_zq_init) { /* Sending ZQINIT command */ writel(DIRECT_CMD_ZQINIT | mask, - &dmc->directcmd); + directcmd); sdelay(10000); } @@ -134,7 +134,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) } } -void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) +void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd) { int channel, chip; @@ -146,20 +146,12 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) mask |= chip << DIRECT_CMD_CHIP_SHIFT; /* PALL (all banks precharge) CMD */ - writel(DIRECT_CMD_PALL | mask, &dmc->directcmd); + writel(DIRECT_CMD_PALL | mask, directcmd); sdelay(0x10000); } } } -void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc) -{ - writel(mem->memconfig, &dmc->memconfig0); - writel(mem->memconfig, &dmc->memconfig1); - writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0); - writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1); -} - void mem_ctrl_init(int reset) { struct spl_machine_param *param = spl_get_machine_params(); diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 5f5914e..487e6f4 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -1,5 +1,5 @@ /* - * DDR3 mem setup file for SMDK5250 board based on EXYNOS5 + * DDR3 mem setup file for board based on EXYNOS5 * * Copyright (C) 2012 Samsung Electronics * @@ -11,12 +11,14 @@ #include #include #include +#include #include "common_setup.h" #include "exynos5_setup.h" #include "clock_init.h" -#define RDLVL_COMPLETE_TIMEOUT 10000 +#define TIMEOUT 10000 +#ifdef CONFIG_EXYNOS5250 static void reset_phy_ctrl(void) { struct exynos5_clock *clk = @@ -57,7 +59,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(val, &phy1_ctrl->phy_con42); /* ZQ Calibration */ - if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl)) + if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16, + &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17)) return SETUP_ERR_ZQ_CALIBRATION_FAILURE; /* DQ Signal */ @@ -68,7 +71,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT), &dmc->concontrol); - update_reset_dll(dmc, DDR_MODE_DDR3); + update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); /* DQS Signal */ writel(mem->phy0_dqs, &phy0_ctrl->phy_con4); @@ -93,7 +96,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), &phy1_ctrl->phy_con12); - update_reset_dll(dmc, DDR_MODE_DDR3); + update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), &dmc->concontrol); @@ -124,10 +127,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(mem->timing_power, &dmc->timingpower); /* Send PALL command */ - dmc_config_prech(mem, dmc); + dmc_config_prech(mem, &dmc->directcmd); /* Send NOP, MRS and ZQINIT commands */ - dmc_config_mrs(mem, dmc); + dmc_config_mrs(mem, &dmc->directcmd); if (mem->gate_leveling_enable) { val = PHY_CON0_RESET_VAL; @@ -174,7 +177,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(val, &phy1_ctrl->phy_con1); writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config); - i = RDLVL_COMPLETE_TIMEOUT; + i = TIMEOUT; while ((readl(&dmc->phystatus) & (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { @@ -202,11 +205,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(val, &phy0_ctrl->phy_con12); writel(val, &phy1_ctrl->phy_con12); - update_reset_dll(dmc, DDR_MODE_DDR3); + update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); } /* Send PALL command */ - dmc_config_prech(mem, dmc); + dmc_config_prech(mem, &dmc->directcmd); writel(mem->memcontrol, &dmc->memcontrol); @@ -215,3 +218,419 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol); return 0; } +#endif + +#ifdef CONFIG_EXYNOS5420 +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, + int reset) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + struct exynos5420_power *power = + (struct exynos5420_power *)samsung_get_base_power(); + struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl; + struct exynos5420_dmc *drex0, *drex1; + struct exynos5420_tzasc *tzasc0, *tzasc1; + uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; + int chip; + int i; + + phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy(); + phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy() + + DMC_OFFSET); + drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl(); + drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl() + + DMC_OFFSET); + tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc(); + tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc() + + DMC_OFFSET); + + /* Enable PAUSE for DREX */ + setbits_le32(&clk->pause, ENABLE_BIT); + + /* Enable BYPASS mode */ + setbits_le32(&clk->bpll_con1, BYPASS_EN); + + writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex); + do { + val = readl(&clk->mux_stat_cdrex); + val &= BPLL_SEL_MASK; + } while (val != FOUTBPLL); + + clrbits_le32(&clk->bpll_con1, BYPASS_EN); + + /* Specify the DDR memory type as DDR3 */ + val = readl(&phy0_ctrl->phy_con0); + val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); + val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); + writel(val, &phy0_ctrl->phy_con0); + + val = readl(&phy1_ctrl->phy_con0); + val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); + val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); + writel(val, &phy1_ctrl->phy_con0); + + /* Set Read Latency and Burst Length for PHY0 and PHY1 */ + val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | + (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); + writel(val, &phy0_ctrl->phy_con42); + writel(val, &phy1_ctrl->phy_con42); + + val = readl(&phy0_ctrl->phy_con26); + val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); + val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); + writel(val, &phy0_ctrl->phy_con26); + + val = readl(&phy1_ctrl->phy_con26); + val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); + val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); + writel(val, &phy1_ctrl->phy_con26); + + /* + * Set Driver strength for CK, CKE, CS & CA to 0x7 + * Set Driver strength for Data Slice 0~3 to 0x7 + */ + val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) | + (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET); + val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) | + (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET); + writel(val, &phy0_ctrl->phy_con39); + writel(val, &phy1_ctrl->phy_con39); + + /* ZQ Calibration */ + if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16, + &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17)) + return SETUP_ERR_ZQ_CALIBRATION_FAILURE; + + clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN); + clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN); + + /* DQ Signal */ + val = readl(&phy0_ctrl->phy_con14); + val |= mem->phy0_pulld_dqs; + writel(val, &phy0_ctrl->phy_con14); + val = readl(&phy1_ctrl->phy_con14); + val |= mem->phy1_pulld_dqs; + writel(val, &phy1_ctrl->phy_con14); + + val = MEM_TERM_EN | PHY_TERM_EN; + writel(val, &drex0->phycontrol0); + writel(val, &drex1->phycontrol0); + + writel(mem->concontrol | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + &drex0->concontrol); + writel(mem->concontrol | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + &drex1->concontrol); + + do { + val = readl(&drex0->phystatus); + } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); + do { + val = readl(&drex1->phystatus); + } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); + + clrbits_le32(&drex0->concontrol, DFI_INIT_START); + clrbits_le32(&drex1->concontrol, DFI_INIT_START); + + update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3); + update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3); + + /* + * Set Base Address: + * 0x2000_0000 ~ 0x5FFF_FFFF + * 0x6000_0000 ~ 0x9FFF_FFFF + */ + /* MEMBASECONFIG0 */ + val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) | + DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK); + writel(val, &tzasc0->membaseconfig0); + writel(val, &tzasc1->membaseconfig0); + + /* MEMBASECONFIG1 */ + val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) | + DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK); + writel(val, &tzasc0->membaseconfig1); + writel(val, &tzasc1->membaseconfig1); + + /* + * Memory Channel Inteleaving Size + * Ares Channel interleaving = 128 bytes + */ + /* MEMCONFIG0/1 */ + writel(mem->memconfig, &tzasc0->memconfig0); + writel(mem->memconfig, &tzasc1->memconfig0); + writel(mem->memconfig, &tzasc0->memconfig1); + writel(mem->memconfig, &tzasc1->memconfig1); + + /* Precharge Configuration */ + writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, + &drex0->prechconfig0); + writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, + &drex1->prechconfig0); + + /* + * TimingRow, TimingData, TimingPower and Timingaref + * values as per Memory AC parameters + */ + writel(mem->timing_ref, &drex0->timingref); + writel(mem->timing_ref, &drex1->timingref); + writel(mem->timing_row, &drex0->timingrow0); + writel(mem->timing_row, &drex1->timingrow0); + writel(mem->timing_data, &drex0->timingdata0); + writel(mem->timing_data, &drex1->timingdata0); + writel(mem->timing_power, &drex0->timingpower0); + writel(mem->timing_power, &drex1->timingpower0); + + if (reset) { + /* + * Send NOP, MRS and ZQINIT commands + * Sending MRS command will reset the DRAM. We should not be + * reseting the DRAM after resume, this will lead to memory + * corruption as DRAM content is lost after DRAM reset + */ + dmc_config_mrs(mem, &drex0->directcmd); + dmc_config_mrs(mem, &drex1->directcmd); + } else { + /* + * During Suspend-Resume & S/W-Reset, as soon as PMU releases + * pad retention, CKE goes high. This causes memory contents + * not to be retained during DRAM initialization. Therfore, + * there is a new control register(0x100431e8[28]) which lets us + * release pad retention and retain the memory content until the + * initialization is complete. + */ + writel(PAD_RETENTION_DRAM_COREBLK_VAL, + &power->pad_retention_dram_coreblk_option); + do { + val = readl(&power->pad_retention_dram_status); + } while (val != 0x1); + + /* + * CKE PAD retention disables DRAM self-refresh mode. + * Send auto refresh command for DRAM refresh. + */ + for (i = 0; i < 128; i++) { + for (chip = 0; chip < mem->chips_to_configure; chip++) { + writel(DIRECT_CMD_REFA | + (chip << DIRECT_CMD_CHIP_SHIFT), + &drex0->directcmd); + writel(DIRECT_CMD_REFA | + (chip << DIRECT_CMD_CHIP_SHIFT), + &drex1->directcmd); + } + } + } + + if (mem->gate_leveling_enable) { + writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0); + writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0); + + setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN); + setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN); + + val = PHY_CON2_RESET_VAL; + val |= INIT_DESKEW_EN; + writel(val, &phy0_ctrl->phy_con2); + writel(val, &phy1_ctrl->phy_con2); + + val = readl(&phy0_ctrl->phy_con1); + val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); + writel(val, &phy0_ctrl->phy_con1); + + val = readl(&phy1_ctrl->phy_con1); + val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); + writel(val, &phy1_ctrl->phy_con1); + + n_lock_r = readl(&phy0_ctrl->phy_con13); + n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_r = readl(&phy0_ctrl->phy_con12); + n_lock_r &= ~CTRL_DLL_ON; + n_lock_r |= n_lock_w_phy0; + writel(n_lock_r, &phy0_ctrl->phy_con12); + + n_lock_r = readl(&phy1_ctrl->phy_con13); + n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_r = readl(&phy1_ctrl->phy_con12); + n_lock_r &= ~CTRL_DLL_ON; + n_lock_r |= n_lock_w_phy1; + writel(n_lock_r, &phy1_ctrl->phy_con12); + + val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; + for (chip = 0; chip < mem->chips_to_configure; chip++) { + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex0->directcmd); + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex1->directcmd); + } + + setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN); + setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN); + + setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE); + setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE); + + val = readl(&phy0_ctrl->phy_con1); + val &= ~(CTRL_GATEDURADJ_MASK); + writel(val, &phy0_ctrl->phy_con1); + + val = readl(&phy1_ctrl->phy_con1); + val &= ~(CTRL_GATEDURADJ_MASK); + writel(val, &phy1_ctrl->phy_con1); + + writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config); + i = TIMEOUT; + while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) != + RDLVL_COMPLETE_CHO) && (i > 0)) { + /* + * TODO(waihong): Comment on how long this take to + * timeout + */ + sdelay(100); + i--; + } + if (!i) + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config); + + writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config); + i = TIMEOUT; + while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) != + RDLVL_COMPLETE_CHO) && (i > 0)) { + /* + * TODO(waihong): Comment on how long this take to + * timeout + */ + sdelay(100); + i--; + } + if (!i) + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config); + + writel(0, &phy0_ctrl->phy_con14); + writel(0, &phy1_ctrl->phy_con14); + + val = (0x3 << DIRECT_CMD_BANK_SHIFT); + for (chip = 0; chip < mem->chips_to_configure; chip++) { + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex0->directcmd); + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex1->directcmd); + } + + if (mem->read_leveling_enable) { + /* Set Read DQ Calibration */ + val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; + for (chip = 0; chip < mem->chips_to_configure; chip++) { + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex0->directcmd); + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex1->directcmd); + } + + val = readl(&phy0_ctrl->phy_con1); + val |= READ_LEVELLING_DDR3; + writel(val, &phy0_ctrl->phy_con1); + val = readl(&phy1_ctrl->phy_con1); + val |= READ_LEVELLING_DDR3; + writel(val, &phy1_ctrl->phy_con1); + + val = readl(&phy0_ctrl->phy_con2); + val |= (RDLVL_EN | RDLVL_INCR_ADJ); + writel(val, &phy0_ctrl->phy_con2); + val = readl(&phy1_ctrl->phy_con2); + val |= (RDLVL_EN | RDLVL_INCR_ADJ); + writel(val, &phy1_ctrl->phy_con2); + + setbits_le32(&drex0->rdlvl_config, + CTRL_RDLVL_DATA_ENABLE); + i = TIMEOUT; + while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) + != RDLVL_COMPLETE_CHO) && (i > 0)) { + /* + * TODO(waihong): Comment on how long this take + * to timeout + */ + sdelay(100); + i--; + } + if (!i) + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + + clrbits_le32(&drex0->rdlvl_config, + CTRL_RDLVL_DATA_ENABLE); + setbits_le32(&drex1->rdlvl_config, + CTRL_RDLVL_DATA_ENABLE); + i = TIMEOUT; + while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) + != RDLVL_COMPLETE_CHO) && (i > 0)) { + /* + * TODO(waihong): Comment on how long this take + * to timeout + */ + sdelay(100); + i--; + } + if (!i) + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + + clrbits_le32(&drex1->rdlvl_config, + CTRL_RDLVL_DATA_ENABLE); + + val = (0x3 << DIRECT_CMD_BANK_SHIFT); + for (chip = 0; chip < mem->chips_to_configure; chip++) { + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex0->directcmd); + writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), + &drex1->directcmd); + } + + update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3); + update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3); + } + + /* Common Settings for Leveling */ + val = PHY_CON12_RESET_VAL; + writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12); + writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12); + + setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN); + setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN); + } + + /* Send PALL command */ + dmc_config_prech(mem, &drex0->directcmd); + dmc_config_prech(mem, &drex1->directcmd); + + writel(mem->memcontrol, &drex0->memcontrol); + writel(mem->memcontrol, &drex1->memcontrol); + + /* + * Set DMC Concontrol: Enable auto-refresh counter, provide + * read data fetch cycles and enable DREX auto set powerdown + * for input buffer of I/O in none read memory state. + */ + writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| + DMC_CONCONTROL_IO_PD_CON(0x2), + &drex0->concontrol); + writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)| + DMC_CONCONTROL_IO_PD_CON(0x2), + &drex1->concontrol); + + /* + * Enable Clock Gating Control for DMC + * this saves around 25 mw dmc power as compared to the power + * consumption without these bits enabled + */ + setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG); + setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG); + + return 0; +} +#endif diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index c8d6515..53b0ace 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -696,6 +696,7 @@ #define CLK_DIV_CPERI1_VAL NOT_AVAILABLE #else +#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000 /* APLL_CON1 */ #define APLL_CON1_VAL (0x0020F300) @@ -907,37 +908,38 @@ void lpddr3_mem_ctrl_init(void); * Configure ZQ I/O interface * * @param mem Memory timings for this memory type. - * @param phy0_ctrl Pointer to struct containing PHY0 control reg - * @param phy1_ctrl Pointer to struct containing PHY1 control reg + * @param phy0_con16 Register address for dmc_phy0->phy_con16 + * @param phy1_con16 Register address for dmc_phy1->phy_con16 + * @param phy0_con17 Register address for dmc_phy0->phy_con17 + * @param phy1_con17 Register address for dmc_phy1->phy_con17 * @return 0 if ok, -1 on error */ -int dmc_config_zq(struct mem_timings *mem, - struct exynos5_phy_control *phy0_ctrl, - struct exynos5_phy_control *phy1_ctrl); - +int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16, + uint32_t *phy1_con16, uint32_t *phy0_con17, + uint32_t *phy1_con17); /* * Send NOP and MRS/EMRS Direct commands * * @param mem Memory timings for this memory type. - * @param dmc Pointer to struct of DMC registers + * @param directcmd Register address for dmc_phy->directcmd */ -void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc); +void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd); /* * Send PALL Direct commands * * @param mem Memory timings for this memory type. - * @param dmc Pointer to struct of DMC registers + * @param directcmd Register address for dmc_phy->directcmd */ -void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc); +void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd); /* * Reset the DLL. This function is common between DDR3 and LPDDR2. * However, the reset value is different. So we are passing a flag * ddr_mode to distinguish between LPDDR2 and DDR3. * - * @param exynos5_dmc Pointer to struct of DMC registers + * @param phycontrol0 Register address for dmc_phy->phycontrol0 * @param ddr_mode Type of DDR memory */ -void update_reset_dll(struct exynos5_dmc *, enum ddr_mode); +void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode); #endif diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 2b44210..573f755 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -53,6 +53,7 @@ #define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE /* EXYNOS4X12 */ #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 @@ -91,6 +92,7 @@ #define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE /* EXYNOS5 */ #define EXYNOS5_I2C_SPACING 0x10000 @@ -129,6 +131,7 @@ #define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE /* EXYNOS5420 */ #define EXYNOS5420_AUDIOSS_BASE 0x03810000 @@ -143,8 +146,7 @@ #define EXYNOS5420_ACE_SFR_BASE 0x10830000 #define EXYNOS5420_DMC_PHY_BASE 0x10C00000 #define EXYNOS5420_DMC_CTRL_BASE 0x10C20000 -#define EXYNOS5420_DMC_TZASC0_BASE 0x10D40000 -#define EXYNOS5420_DMC_TZASC1_BASE 0x10D50000 +#define EXYNOS5420_DMC_TZASC_BASE 0x10D40000 #define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000 #define EXYNOS5420_MMC_BASE 0x12200000 #define EXYNOS5420_SROMC_BASE 0x12250000 @@ -284,6 +286,7 @@ SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) SAMSUNG_BASE(tzpc, TZPC_BASE) SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE) SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE) +SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE) SAMSUNG_BASE(audio_ass, AUDIOSS_BASE) #endif diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index 32ad3ae..d78536d 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -419,6 +419,15 @@ struct exynos5420_phy_control { unsigned int phy_con42; }; +struct exynos5420_tzasc { + unsigned char res1[0xf00]; + unsigned int membaseconfig0; + unsigned int membaseconfig1; + unsigned char res2[0x8]; + unsigned int memconfig0; + unsigned int memconfig1; +}; + enum ddr_mode { DDR_MODE_DDR2, DDR_MODE_DDR3, @@ -453,6 +462,7 @@ enum mem_manuf { #define PHY_CON0_T_WRRDCMD_SHIFT 17 #define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) #define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 +#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3 /* PHY_CON1 register fields */ #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 -- cgit v0.10.2 From 5af4a4f74ac0607c71f5fca3fd0c6679b662b207 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:23 +0530 Subject: Exynos5420: Add support for 5420 in pinmux and gpio Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Saraswat Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 74cc700..904177a 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -46,6 +46,42 @@ static void exynos5_uart_config(int peripheral) } } +static void exynos5420_uart_config(int peripheral) +{ + struct exynos5420_gpio_part1 *gpio1 = + (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank; + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + bank = &gpio1->a0; + start = 0; + count = 4; + break; + case PERIPH_ID_UART1: + bank = &gpio1->a0; + start = 4; + count = 4; + break; + case PERIPH_ID_UART2: + bank = &gpio1->a1; + start = 0; + count = 4; + break; + case PERIPH_ID_UART3: + bank = &gpio1->a1; + start = 4; + count = 2; + break; + } + + for (i = start; i < start + count; i++) { + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } +} + static int exynos5_mmc_config(int peripheral, int flags) { struct exynos5_gpio_part1 *gpio1 = @@ -101,6 +137,75 @@ static int exynos5_mmc_config(int peripheral, int flags) return 0; } +static int exynos5420_mmc_config(int peripheral, int flags) +{ + struct exynos5420_gpio_part3 *gpio3 = + (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3(); + struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL; + int i, start; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + bank = &gpio3->c0; + bank_ext = &gpio3->c3; + start = 0; + break; + case PERIPH_ID_SDMMC1: + bank = &gpio3->c1; + bank_ext = &gpio3->d1; + start = 4; + break; + case PERIPH_ID_SDMMC2: + bank = &gpio3->c2; + bank_ext = NULL; + start = 0; + break; + default: + start = 0; + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + debug("SDMMC device %d does not support 8bit mode", + peripheral); + return -1; + } + + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start; i <= (start + 3); i++) { + s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + } + } + + for (i = 0; i < 3; i++) { + /* + * MMC0 is intended to be used for eMMC. The + * card detect pin is used as a VDDEN signal to + * power on the eMMC. The 5420 iROM makes + * this same assumption. + */ + if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) { + s5p_gpio_set_value(bank, i, 1); + s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT); + } else { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + + return 0; +} + static void exynos5_sromc_config(int flags) { struct exynos5_gpio_part1 *gpio1 = @@ -216,6 +321,59 @@ static void exynos5_i2c_config(int peripheral, int flags) } } +static void exynos5420_i2c_config(int peripheral) +{ + struct exynos5420_gpio_part1 *gpio1 = + (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C8: + s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C9: + s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C10: + s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2)); + break; + } +} + static void exynos5_i2s_config(int peripheral) { int i; @@ -279,6 +437,58 @@ void exynos5_spi_config(int peripheral) } } +void exynos5420_spi_config(int peripheral) +{ + int cfg, pin, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5420_gpio_part1 *gpio1 = + (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); + struct exynos5420_gpio_part4 *gpio4 = + (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio4->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + cfg = 0; + pin = 0; + break; + default: + cfg = 0; + pin = 0; + debug("%s: invalid peripheral %d", __func__, peripheral); + return; + } + + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } else { + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4)); + } + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -325,6 +535,48 @@ static int exynos5_pinmux_config(int peripheral, int flags) return 0; } +static int exynos5420_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos5420_uart_config(peripheral); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + return exynos5420_mmc_config(peripheral, flags); + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5420_spi_config(peripheral); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + case PERIPH_ID_I2C8: + case PERIPH_ID_I2C9: + case PERIPH_ID_I2C10: + exynos5420_i2c_config(peripheral); + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + static void exynos4_i2c_config(int peripheral, int flags) { struct exynos4_gpio_part1 *gpio1 = @@ -475,13 +727,17 @@ static int exynos4_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { - return exynos5_pinmux_config(peripheral, flags); + if (proid_is_exynos5420()) + return exynos5420_pinmux_config(peripheral, flags); + else if (proid_is_exynos5250()) + return exynos5_pinmux_config(peripheral, flags); } else if (cpu_is_exynos4()) { return exynos4_pinmux_config(peripheral, flags); } else { debug("pinmux functionality not supported\n"); - return -1; } + + return -1; } #ifdef CONFIG_OF_CONTROL diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index a1a7439..2a19852 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 { struct s5p_gpio_bank v4; }; +struct exynos5420_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank a2; + struct s5p_gpio_bank b0; + struct s5p_gpio_bank b1; + struct s5p_gpio_bank b2; + struct s5p_gpio_bank b3; + struct s5p_gpio_bank b4; + struct s5p_gpio_bank h0; +}; + +struct exynos5420_gpio_part2 { + struct s5p_gpio_bank y7; /* 0x1340_0000 */ + struct s5p_gpio_bank res[0x5f]; /* */ + struct s5p_gpio_bank x0; /* 0x1340_0C00 */ + struct s5p_gpio_bank x1; /* 0x1340_0C20 */ + struct s5p_gpio_bank x2; /* 0x1340_0C40 */ + struct s5p_gpio_bank x3; /* 0x1340_0C60 */ +}; + +struct exynos5420_gpio_part3 { + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank c2; + struct s5p_gpio_bank c3; + struct s5p_gpio_bank c4; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; +}; + +struct exynos5420_gpio_part4 { + struct s5p_gpio_bank e0; /* 0x1400_0000 */ + struct s5p_gpio_bank e1; /* 0x1400_0020 */ + struct s5p_gpio_bank f0; /* 0x1400_0040 */ + struct s5p_gpio_bank f1; /* 0x1400_0060 */ + struct s5p_gpio_bank g0; /* 0x1400_0080 */ + struct s5p_gpio_bank g1; /* 0x1400_00A0 */ + struct s5p_gpio_bank g2; /* 0x1400_00C0 */ + struct s5p_gpio_bank j4; /* 0x1400_00E0 */ +}; + +struct exynos5420_gpio_part5 { + struct s5p_gpio_bank z0; /* 0x0386_0000 */ +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1; @@ -259,16 +311,67 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) + +/* EXYNOS5420 */ +#define exynos5420_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\ + EXYNOS5420_GPIO_PART1_BASE)->bank)) \ + - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos5420_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\ + EXYNOS5420_GPIO_PART2_BASE)->bank)) \ + - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX) + +#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos5420_gpio_part3_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\ + EXYNOS5420_GPIO_PART3_BASE)->bank)) \ + - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX) + +#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos5420_gpio_part4_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\ + EXYNOS5420_GPIO_PART4_BASE)->bank)) \ + - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX) + +#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + static inline unsigned int s5p_gpio_base(int nr) { if (cpu_is_exynos5()) { - if (nr < EXYNOS5_GPIO_PART1_MAX) - return EXYNOS5_GPIO_PART1_BASE; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART2_BASE; - else - return EXYNOS5_GPIO_PART3_BASE; - + if (proid_is_exynos5420()) { + if (nr < EXYNOS5420_GPIO_PART1_MAX) + return EXYNOS5420_GPIO_PART1_BASE; + else if (nr < EXYNOS5420_GPIO_PART2_MAX) + return EXYNOS5420_GPIO_PART2_BASE; + else if (nr < EXYNOS5420_GPIO_PART3_MAX) + return EXYNOS5420_GPIO_PART3_BASE; + else + return EXYNOS5420_GPIO_PART4_BASE; + } else { + if (nr < EXYNOS5_GPIO_PART1_MAX) + return EXYNOS5_GPIO_PART1_BASE; + else if (nr < EXYNOS5_GPIO_PART2_MAX) + return EXYNOS5_GPIO_PART2_BASE; + else + return EXYNOS5_GPIO_PART3_BASE; + } } else if (cpu_is_exynos4()) { if (nr < EXYNOS4_GPIO_PART1_MAX) return EXYNOS4_GPIO_PART1_BASE; @@ -282,13 +385,25 @@ static inline unsigned int s5p_gpio_base(int nr) static inline unsigned int s5p_gpio_part_max(int nr) { if (cpu_is_exynos5()) { - if (nr < EXYNOS5_GPIO_PART1_MAX) - return 0; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART1_MAX; - else - return EXYNOS5_GPIO_PART2_MAX; - + if (proid_is_exynos5420()) { + if (nr < EXYNOS5420_GPIO_PART1_MAX) + return 0; + else if (nr < EXYNOS5420_GPIO_PART2_MAX) + return EXYNOS5420_GPIO_PART1_MAX; + else if (nr < EXYNOS5420_GPIO_PART3_MAX) + return EXYNOS5420_GPIO_PART2_MAX; + else if (nr < EXYNOS5420_GPIO_PART4_MAX) + return EXYNOS5420_GPIO_PART3_MAX; + else + return EXYNOS5420_GPIO_PART4_MAX; + } else { + if (nr < EXYNOS5_GPIO_PART1_MAX) + return 0; + else if (nr < EXYNOS5_GPIO_PART2_MAX) + return EXYNOS5_GPIO_PART1_MAX; + else + return EXYNOS5_GPIO_PART2_MAX; + } } else if (cpu_is_exynos4()) { if (proid_is_exynos4412()) { if (nr < EXYNOS4X12_GPIO_PART1_MAX) diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 64bd8b7..30c7f18 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -34,6 +34,9 @@ enum periph_id { PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3, + PERIPH_ID_I2C8 = 87, + PERIPH_ID_I2C9, + PERIPH_ID_I2C10 = 203, PERIPH_ID_I2S0 = 98, PERIPH_ID_I2S1 = 99, -- cgit v0.10.2 From e106bd9b9d0c3ec429b2e85184738789b75ca247 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:24 +0530 Subject: Exynos5420: Add base patch for SMDK5420 Adding the base patch for Exynos based SMDK5420. This shall enable compilation and basic boot support for SMDK5420. Signed-off-by: Rajeshwari S Shinde Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index dc68e3a..cd873bc 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -149,6 +149,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void) return local.cros_ec_dev; } +#ifdef CONFIG_CROS_EC static int board_init_cros_ec_devices(const void *blob) { local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); @@ -157,6 +158,7 @@ static int board_init_cros_ec_devices(const void *blob) return 0; } +#endif #if defined(CONFIG_POWER) #ifdef CONFIG_POWER_MAX77686 diff --git a/board/samsung/smdk5420/Makefile b/board/samsung/smdk5420/Makefile new file mode 100644 index 0000000..c2f8886 --- /dev/null +++ b/board/samsung/smdk5420/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2013 Samsung Electronics +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += smdk5420_spl.o + +ifndef CONFIG_SPL_BUILD +obj-y += smdk5420.o +endif diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c new file mode 100644 index 0000000..3ad2ad0 --- /dev/null +++ b/board/samsung/smdk5420/smdk5420.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USB_EHCI_EXYNOS +static int board_usb_vbus_init(void) +{ + struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) + samsung_get_base_gpio_part1(); + + /* Enable VBUS power switch */ + s5p_gpio_direction_output(&gpio1->x2, 6, 1); + + /* VBUS turn ON time */ + mdelay(3); + + return 0; +} +#endif + +int exynos_init(void) +{ +#ifdef CONFIG_USB_EHCI_EXYNOS + board_usb_vbus_init(); +#endif + return 0; +} + +#ifdef CONFIG_LCD +void cfg_lcd_gpio(void) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); + + /* For Backlight */ + s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); + s5p_gpio_set_value(&gpio1->b2, 0, 1); + + /* LCD power on */ + s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); + s5p_gpio_set_value(&gpio1->x1, 5, 1); + + /* Set Hotplug detect for DP */ + s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); +} + +vidinfo_t panel_info = { + .vl_freq = 60, + .vl_col = 2560, + .vl_row = 1600, + .vl_width = 2560, + .vl_height = 1600, + .vl_clkp = CONFIG_SYS_LOW, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_LOW, + .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */ + + /* wDP panel timing infomation */ + .vl_hspw = 32, + .vl_hbpd = 80, + .vl_hfpd = 48, + + .vl_vspw = 6, + .vl_vbpd = 37, + .vl_vfpd = 3, + .vl_cmd_allow_len = 0xf, + + .win_id = 3, + .cfg_gpio = cfg_lcd_gpio, + .backlight_on = NULL, + .lcd_power_on = NULL, + .reset_lcd = NULL, + .dual_lcd_enabled = 0, + + .init_delay = 0, + .power_on_delay = 0, + .reset_delay = 0, + .interface_mode = FIMD_RGB_INTERFACE, + .dp_enabled = 1, +}; + +static struct edp_device_info edp_info = { + .disp_info = { + .h_res = 2560, + .h_sync_width = 32, + .h_back_porch = 80, + .h_front_porch = 48, + .v_res = 1600, + .v_sync_width = 6, + .v_back_porch = 37, + .v_front_porch = 3, + .v_sync_rate = 60, + }, + .lt_info = { + .lt_status = DP_LT_NONE, + }, + .video_info = { + .master_mode = 0, + .bist_mode = DP_DISABLE, + .bist_pattern = NO_PATTERN, + .h_sync_polarity = 0, + .v_sync_polarity = 0, + .interlaced = 0, + .color_space = COLOR_RGB, + .dynamic_range = VESA, + .ycbcr_coeff = COLOR_YCBCR601, + .color_depth = COLOR_8, + }, +}; + +static struct exynos_dp_platform_data dp_platform_data = { + .phy_enable = set_dp_phy_ctrl, + .edp_dev_info = &edp_info, +}; + +void init_panel_info(vidinfo_t *vid) +{ + vid->rgb_mode = MODE_RGB_P; + + exynos_set_dp_platform_data(&dp_platform_data); +} +#endif + +int board_get_revision(void) +{ + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + const char *board_name; + + board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + if (board_name == NULL) + printf("\nUnknown Board\n"); + else + printf("\nBoard: %s\n", board_name); + + return 0; +} +#endif diff --git a/board/samsung/smdk5420/smdk5420_spl.c b/board/samsung/smdk5420/smdk5420_spl.c new file mode 100644 index 0000000..73359f7 --- /dev/null +++ b/board/samsung/smdk5420/smdk5420_spl.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2013 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param + __attribute__((section(".machine_param"))) = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirM", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 900, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, + .mem_manuf = MEM_MANUF_SAMSUNG, +}; + +struct spl_machine_param *spl_get_machine_params(void) +{ + if (machine_param.signature != SIGNATURE) { + /* Will hang if SIGNATURE dont match */ + while (1) + ; + } + + return &machine_param; +} diff --git a/boards.cfg b/boards.cfg index d85d4dd..bd018ff 100644 --- a/boards.cfg +++ b/boards.cfg @@ -276,6 +276,7 @@ Active arm armv7 exynos samsung arndale Active arm armv7 exynos samsung origen origen - Chander Kashyap Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde +Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap Active arm armv7 exynos samsung trats trats - Lukasz Majewski Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek diff --git a/include/configs/arndale.h b/include/configs/arndale.h index a3cb56b..b7fb29e 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -117,6 +117,7 @@ #define CONFIG_USB_STORAGE /* MMC SPL */ +#define CONFIG_EXYNOS_SPL #define CONFIG_SPL #define COPY_BL2_FNPTR_ADDR 0x02020030 diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 79e85db..3b989eb 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -155,6 +155,7 @@ #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 /* MMC SPL */ +#define CONFIG_EXYNOS_SPL #define CONFIG_SPL #define COPY_BL2_FNPTR_ADDR 0x02020030 diff --git a/tools/Makefile b/tools/Makefile index 14d94e3..d4bc84d 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -53,6 +53,7 @@ BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) BIN_FILES-y += mkenvimage$(SFX) BIN_FILES-y += mkimage$(SFX) BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX) +BIN_FILES-$(CONFIG_EXYNOS5420) += mk$(BOARD)spl$(SFX) BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX) BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX) BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) @@ -87,7 +88,7 @@ NOPED_OBJ_FILES-y += ublimage.o OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o -OBJ_FILES-$(CONFIG_EXYNOS5250) += mkexynosspl.o +OBJ_FILES-$(CONFIG_EXYNOS_SPL) += mkexynosspl.o OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o OBJ_FILES-$(CONFIG_MX23) += mxsboot.o -- cgit v0.10.2 From e2be3369c84f8b9a91ba904823ba70ed842019d3 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:25 +0530 Subject: DTS: Add dts support for SMDK5420 This patch adds dts support for SMDK5420. exynos5.dtsi created is a common file which has the nodes common to both 5420 and 5250. Signed-off-by: Akshay Saraswat Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi new file mode 100644 index 0000000..f8c8741 --- /dev/null +++ b/arch/arm/dts/exynos5.dtsi @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2013 The Chromium OS Authors + * SAMSUNG EXYNOS5 SoC device tree source + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "samsung,exynos5"; + + sromc@12250000 { + compatible = "samsung,exynos-sromc"; + reg = <0x12250000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@12c60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C60000 0x100>; + interrupts = <0 56 0>; + }; + + i2c@12c70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C70000 0x100>; + interrupts = <0 57 0>; + }; + + i2c@12c80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C80000 0x100>; + interrupts = <0 58 0>; + }; + + i2c@12c90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x12C90000 0x100>; + interrupts = <0 59 0>; + }; + + spi@12d20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x12d20000 0x30>; + interrupts = <0 68 0>; + }; + + spi@12d30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x12d30000 0x30>; + interrupts = <0 69 0>; + }; + + spi@12d40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x12d40000 0x30>; + clock-frequency = <50000000>; + interrupts = <0 70 0>; + }; + + spi@131a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x131a0000 0x30>; + interrupts = <0 129 0>; + }; + + spi@131b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-spi"; + reg = <0x131b0000 0x30>; + interrupts = <0 130 0>; + }; + + ehci@12110000 { + compatible = "samsung,exynos-ehci"; + reg = <0x12110000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos-usb-phy"; + reg = <0x12130000 0x100>; + }; + }; + + tmu@10060000 { + compatible = "samsung,exynos-tmu"; + reg = <0x10060000 0x10000>; + }; + + fimd@14400000 { + compatible = "samsung,exynos-fimd"; + reg = <0x14400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + dp@145b0000 { + compatible = "samsung,exynos5-dp"; + reg = <0x145b0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + xhci0: xhci@12000000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12000000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12100000 0x100>; + }; + }; + + mmc@12200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12200000 0x1000>; + interrupts = <0 75 0>; + }; + + mmc@12210000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12210000 0x1000>; + interrupts = <0 76 0>; + }; + + mmc@12220000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12220000 0x1000>; + interrupts = <0 77 0>; + }; + + mmc@12230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5250-dwmmc"; + reg = <0x12230000 0x1000>; + interrupts = <0 78 0>; + }; + + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 51 0>; + id = <0>; + }; + + serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 52 0>; + id = <1>; + }; + + serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 53 0>; + id = <2>; + }; + + serial@12C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C30000 0x100>; + interrupts = <0 54 0>; + id = <3>; + }; + + gpio: gpio { + }; +}; diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index 31880eb..0c644e7 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -1,66 +1,13 @@ /* + * (C) Copyright 2012 SAMSUNG Electronics * SAMSUNG EXYNOS5250 SoC device tree source * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. - * EXYNOS5250 based board files can include this file and provide - * values for board specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, - * additional nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + * SPDX-License-Identifier: GPL-2.0+ + */ -/include/ "skeleton.dtsi" +/include/ "exynos5.dtsi" / { - compatible = "samsung,exynos5250"; - - sromc@12250000 { - compatible = "samsung,exynos-sromc"; - reg = <0x12250000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@12c60000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; - }; - - i2c@12c70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; - }; - - i2c@12c80000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; - }; - - i2c@12c90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; - }; - i2c@12ca0000 { #address-cells = <1>; #size-cells = <0>; @@ -117,46 +64,6 @@ samsung,i2s-id = <1>; }; - spi@12d20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x12d20000 0x30>; - interrupts = <0 68 0>; - }; - - spi@12d30000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x12d30000 0x30>; - interrupts = <0 69 0>; - }; - - spi@12d40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x12d40000 0x30>; - clock-frequency = <50000000>; - interrupts = <0 70 0>; - }; - - spi@131a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x131a0000 0x30>; - interrupts = <0 129 0>; - }; - - spi@131b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos-spi"; - reg = <0x131b0000 0x30>; - interrupts = <0 130 0>; - }; xhci@12000000 { compatible = "samsung,exynos5250-xhci"; @@ -170,97 +77,4 @@ }; }; - ehci@12110000 { - compatible = "samsung,exynos-ehci"; - reg = <0x12110000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - phy { - compatible = "samsung,exynos-usb-phy"; - reg = <0x12130000 0x100>; - }; - }; - - tmu@10060000 { - compatible = "samsung,exynos-tmu"; - reg = <0x10060000 0x10000>; - }; - - fimd@14400000 { - compatible = "samsung,exynos-fimd"; - reg = <0x14400000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - dp@145b0000 { - compatible = "samsung,exynos5-dp"; - reg = <0x145b0000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - mmc@12200000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12200000 0x1000>; - interrupts = <0 75 0>; - }; - - mmc@12210000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12210000 0x1000>; - interrupts = <0 76 0>; - }; - - mmc@12220000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12220000 0x1000>; - interrupts = <0 77 0>; - }; - - mmc@12230000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5250-dwmmc"; - reg = <0x12230000 0x1000>; - interrupts = <0 78 0>; - }; - - serial@12C00000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; - interrupts = <0 51 0>; - id = <0>; - }; - - serial@12C10000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; - interrupts = <0 52 0>; - id = <1>; - }; - - serial@12C20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; - interrupts = <0 53 0>; - id = <2>; - }; - - serial@12C30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x12C30000 0x100>; - interrupts = <0 54 0>; - id = <3>; - }; - - gpio: gpio { - }; }; diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi new file mode 100644 index 0000000..02ead61 --- /dev/null +++ b/arch/arm/dts/exynos5420.dtsi @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2013 SAMSUNG Electronics + * SAMSUNG EXYNOS5420 SoC device tree source + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "exynos5.dtsi" + +/ { + config { + machine-arch-id = <4151>; + }; + + i2c@12ca0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CA0000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@12cb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CB0000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@12cc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CC0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@12cd0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CD0000 0x100>; + interrupts = <0 63 0>; + }; + + i2c@12e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E00000 0x100>; + interrupts = <0 87 0>; + }; + + i2c@12e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E10000 0x100>; + interrupts = <0 88 0>; + }; + + i2c@12e20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E20000 0x100>; + interrupts = <0 203 0>; + }; +}; diff --git a/board/samsung/dts/exynos5420-smdk5420.dts b/board/samsung/dts/exynos5420-smdk5420.dts new file mode 100644 index 0000000..d739763 --- /dev/null +++ b/board/samsung/dts/exynos5420-smdk5420.dts @@ -0,0 +1,169 @@ +/* + * SAMSUNG SMDK5420 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos5420.dtsi" + +/ { + model = "SAMSUNG SMDK5420 board based on EXYNOS5420"; + compatible = "samsung,smdk5420", "samsung,exynos5"; + + config { + hwid = "smdk5420 TEST A-A 9382"; + }; + + aliases { + i2c0 = "/i2c@12c60000"; + i2c1 = "/i2c@12c70000"; + i2c2 = "/i2c@12c80000"; + i2c3 = "/i2c@12c90000"; + i2c4 = "/i2c@12ca0000"; + i2c5 = "/i2c@12cb0000"; + i2c6 = "/i2c@12cc0000"; + i2c7 = "/i2c@12cd0000"; + i2c8 = "/i2c@12e00000"; + i2c9 = "/i2c@12e10000"; + i2c10 = "/i2c@12e20000"; + spi0 = "/spi@12d20000"; + spi1 = "/spi@12d30000"; + spi2 = "/spi@12d40000"; + spi3 = "/spi@131a0000"; + spi4 = "/spi@131b0000"; + mmc0 = "/mmc@12200000"; + mmc1 = "/mmc@12210000"; + mmc2 = "/mmc@12220000"; + xhci0 = "/xhci@12000000"; + xhci1 = "/xhci@12400000"; + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* s2mps11 is on i2c bus 4 */ + i2c@12ca0000 { + #address-cells = <1>; + #size-cells = <0>; + pmic@66 { + reg = <0x66>; + compatible = "samsung,s2mps11-pmic"; + }; + }; + + spi@12d20000 { /* spi0 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + reg = <0>; + }; + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <2560>; + samsung,vl-row = <1600>; + samsung,vl-width = <2560>; + samsung,vl-height = <1600>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <80>; + samsung,vl-hfpd = <48>; + samsung,vl-vspw = <6>; + samsung,vl-vbpd = <37>; + samsung,vl-vfpd = <3>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; + + sound@3830000 { + samsung,codec-type = "wm8994"; + }; + + i2c@12c70000 { + soundcodec@1a { + reg = <0x1a>; + compatible = "wolfson,wm8994-codec"; + }; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + samsung,pre-init; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + }; + + mmc@12230000 { + status = "disabled"; + }; + + fimd@14400000 { + /* sysmmu is not used in U-Boot */ + samsung,disable-sysmmu; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; + + dmc { + mem-type = "ddr3"; + }; + + xhci1: xhci@12400000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12500000 0x100>; + }; + }; +}; -- cgit v0.10.2 From 76dd9b6a63cb67343116aa6d99e7f922b214e729 Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:26 +0530 Subject: Config: Add initial config for SMDK5420 Adding initial config for SMDK5420 to build and boot U-Boot over Exynos based SMDK5420. Signed-off-by: Rajeshwari S Shinde Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h new file mode 100644 index 0000000..d684790 --- /dev/null +++ b/include/configs/exynos5-dt.h @@ -0,0 +1,290 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ + +#include /* get chip and board defs */ + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_EXYNOS_SPL + +/* Enable fdt support for Exynos5250 */ +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* Allow tracing to be enabled */ +#define CONFIG_TRACE +#define CONFIG_CMD_TRACE +#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) +#define CONFIG_TRACE_EARLY_SIZE (8 << 20) +#define CONFIG_TRACE_EARLY +#define CONFIG_TRACE_EARLY_ADDR 0x50000000 + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Enable ACE acceleration for SHA1 and SHA256 */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_SHA_HW_ACCEL + +/* input clock of PLL: SMDK5250 has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* Offset for inform registers */ +#define INFORM0_OFFSET 0x800 +#define INFORM1_OFFSET 0x804 +#define INFORM2_OFFSET 0x808 +#define INFORM3_OFFSET 0x80c + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 +#define CONFIG_SILENT_CONSOLE + +/* Enable keyboard */ +#define CONFIG_CROS_EC /* CROS_EC protocol */ +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ +#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ +#define CONFIG_CMD_CROS_EC +#define CONFIG_KEYBOARD + +/* Console configuration */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_S5P_SDHCI +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_SUPPORT_EMMC_BOOT + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* PWM */ +#define CONFIG_PWM + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NET +#define CONFIG_CMD_HASH + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* Thermal Management Unit */ +#define CONFIG_EXYNOS_TMU +#define CONFIG_CMD_DTT +#define CONFIG_TMU_CMD_DTT + +/* TPM */ +#define CONFIG_TPM +#define CONFIG_CMD_TPM +#define CONFIG_TPM_TIS_I2C +#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 +#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 + +/* MMC SPL */ +#define CONFIG_SPL +#define COPY_BL2_FNPTR_ADDR 0x02020030 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* specific .lds file */ +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) + + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_RD_LVL + +#define CONFIG_NR_DRAM_BANKS 8 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_SECURE_BL1_ONLY + +/* Secure FW size configuration */ +#ifdef CONFIG_SECURE_BL1_ONLY +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ +#else +#define CONFIG_SEC_FW_SIZE 0 +#endif + +/* Configuration of BL1, BL2, ENV Blocks on mmc */ +#define CONFIG_RES_BLOCK_SIZE (512) +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ + +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) +#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) + +/* U-boot copy size from boot Media to DRAM.*/ +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) + +#define CONFIG_SPI_BOOTING +#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 +#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +/* I2C */ +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 +#define CONFIG_I2C_EDID + +/* SPI */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 + +#ifdef CONFIG_SPI_FLASH +#define CONFIG_EXYNOS_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define EXYNOS5_SPI_NUM_CONTROLLERS 5 +#define CONFIG_OF_SPI +#endif + +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C + +/* Ethernet Controllor Driver */ +#ifdef CONFIG_CMD_NET +#define CONFIG_SMC911X +#define CONFIG_SMC911X_BASE 0x5000000 +#define CONFIG_SMC911X_16_BIT +#define CONFIG_ENV_SROM_BANK 1 +#endif /*CONFIG_CMD_NET*/ + +/* Enable PXE Support */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_PXE +#define CONFIG_MENU +#endif + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT + +/* SHA hashing */ +#define CONFIG_CMD_HASH +#define CONFIG_HASH_VERIFY +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +/* Enable Time Command */ +#define CONFIG_CMD_TIME + +#define CONFIG_CMD_BOOTZ + +#endif /* __CONFIG_H */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 3b989eb..615df64 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -1,3 +1,4 @@ + /* * Copyright (C) 2012 Samsung Electronics * @@ -6,134 +7,19 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_5250_H +#define __CONFIG_5250_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ +#include #define CONFIG_EXYNOS5250 -#include /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON -#define CONFIG_ARCH_EARLY_INIT_R - -/* Enable fdt support for Exynos5250 */ -#define CONFIG_OF_CONTROL -#define CONFIG_OF_SEPARATE - -/* Allow tracing to be enabled */ -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x50000000 - -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -/* Enable ACE acceleration for SHA1 and SHA256 */ -#define CONFIG_EXYNOS_ACE_SHA -#define CONFIG_SHA_HW_ACCEL - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_TEXT_BASE 0x43E00000 -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - /* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ #define MACH_TYPE_SMDK5250 3774 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* Offset for inform registers */ -#define INFORM0_OFFSET 0x800 -#define INFORM1_OFFSET 0x804 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - -/* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -#define CONFIG_SILENT_CONSOLE - -/* Enable keyboard */ -#define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ -#define CONFIG_CMD_CROS_EC -#define CONFIG_KEYBOARD - -/* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS - -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_SUPPORT_EMMC_BOOT - - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NET -#define CONFIG_CMD_HASH - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* Thermal Management Unit */ -#define CONFIG_EXYNOS_TMU -#define CONFIG_CMD_DTT -#define CONFIG_TMU_CMD_DTT - /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_XHCI @@ -147,169 +33,20 @@ #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 -/* TPM */ -#define CONFIG_TPM -#define CONFIG_CMD_TPM -#define CONFIG_TPM_TIS_I2C -#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 -#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 - -/* MMC SPL */ -#define CONFIG_EXYNOS_SPL -#define CONFIG_SPL -#define COPY_BL2_FNPTR_ADDR 0x02020030 - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - -/* specific .lds file */ -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x02023400 -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "SMDK5250 # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_RD_LVL - -#define CONFIG_NR_DRAM_BANKS 8 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for SMDK5250" -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_SECURE_BL1_ONLY - -/* Secure FW size configuration */ -#ifdef CONFIG_SECURE_BL1_ONLY -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ -#else -#define CONFIG_SEC_FW_SIZE 0 -#endif - -/* Configuration of BL1, BL2, ENV Blocks on mmc */ -#define CONFIG_RES_BLOCK_SIZE (512) -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ - -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) -#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) - -/* U-boot copy size from boot Media to DRAM.*/ -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) - -#define CONFIG_SPI_BOOTING -#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 -#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - - #define CONFIG_IRAM_STACK 0x02050000 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK -/* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_MAX_I2C_NUM 8 -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 -#define CONFIG_I2C_EDID - /* PMIC */ -#define CONFIG_PMIC -#define CONFIG_PMIC_I2C #define CONFIG_PMIC_MAX77686 -/* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 - -#ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 50000000 -#define EXYNOS5_SPI_NUM_CONTROLLERS 5 -#define CONFIG_OF_SPI -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_MAX77686 - -/* Ethernet Controllor Driver */ -#ifdef CONFIG_CMD_NET -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x5000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_ENV_SROM_BANK 1 -#endif /*CONFIG_CMD_NET*/ - -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - /* Sound */ #define CONFIG_CMD_SOUND #ifdef CONFIG_CMD_SOUND @@ -319,14 +56,8 @@ #define CONFIG_SOUND_WM8994 #endif -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - -/* SHA hashing */ -#define CONFIG_CMD_HASH -#define CONFIG_HASH_VERIFY -#define CONFIG_SHA1 -#define CONFIG_SHA256 +/* I2C */ +#define CONFIG_MAX_I2C_NUM 8 /* Display */ #define CONFIG_LCD @@ -337,8 +68,4 @@ #define LCD_YRES 1600 #define LCD_BPP LCD_COLOR16 #endif - -/* Enable Time Command */ -#define CONFIG_CMD_TIME - -#endif /* __CONFIG_H */ +#endif /* __CONFIG_5250_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h new file mode 100644 index 0000000..9eab7d6 --- /dev/null +++ b/include/configs/smdk5420.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5420 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_5420_H +#define __CONFIG_5420_H + +#include + +#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */ +#define CONFIG_SMDK5420 /* which is in a SMDK5420 */ + +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos5420-smdk5420 + +#define CONFIG_ARCH_DEVICE_TREE exynos5420 + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 + +#define CONFIG_BOARD_REV_GPIO_COUNT 2 + +/* MACH_TYPE_SMDK5420 macro will be removed once added to mach-types */ +#define MACH_TYPE_SMDK5420 8002 /* Temporary number */ +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 + +/* select serial console configuration */ +#define CONFIG_SERIAL3 /* use SERIAL 3 */ + +#define CONFIG_SPL_TEXT_BASE 0x02024400 + +#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" + +#define CONFIG_SYS_PROMPT "SMDK5420 # " +#define CONFIG_IDENT_STRING " for SMDK5420" + +#define CONFIG_IRAM_TOP 0x02074000 +/* + * Put the initial stack pointer 1KB below this to allow room for the + * SPL marker. This value is arbitrary, but gd_t is placed starting here. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +#define CONFIG_MAX_I2C_NUM 11 + +#endif /* __CONFIG_5420_H */ -- cgit v0.10.2 From 0fcac1abde69a81ab1f773e41df612525c7d322a Mon Sep 17 00:00:00 2001 From: Rajeshwari Birje Date: Thu, 26 Dec 2013 09:44:27 +0530 Subject: SPL: EXYNOS: Prepare for variable size SPL support When variable size SPL is used, the BL1 expects the SPL to be encapsulated differently: instead of putting the checksum at a fixed offset in the SPL blob, prepend the blob with a header including the size and the checksum. The enhancements include - adding a command line option, '--vs' to indicate the need for the variable size encapsulation - padding the fixed size encapsulated blob with 0xff instead of random memory contents - do not silently truncate the input file, report error instead - no need to explicitly closing files/freeing memory, this all happens on exit; removing cleanups it makes code clearer - profuse commenting - modify Makefile to allow enabling the new feature per board Signed-off-by: Vadim Bendebury Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 9eab7d6..447f8e5 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -19,6 +19,8 @@ #define CONFIG_ARCH_DEVICE_TREE exynos5420 +#define CONFIG_VAR_SIZE_SPL + #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_TEXT_BASE 0x23E00000 @@ -31,7 +33,11 @@ /* select serial console configuration */ #define CONFIG_SERIAL3 /* use SERIAL 3 */ +#ifdef CONFIG_VAR_SIZE_SPL +#define CONFIG_SPL_TEXT_BASE 0x02024410 +#else #define CONFIG_SPL_TEXT_BASE 0x02024400 +#endif #define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" diff --git a/spl/Makefile b/spl/Makefile index 2a787af..0caa982 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -166,8 +166,13 @@ endif all: $(ALL-y) ifdef CONFIG_SAMSUNG +ifdef CONFIG_VAR_SIZE_SPL +VAR_SIZE_PARAM = --vs +else +VAR_SIZE_PARAM = +endif $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin - $(OBJTREE)/tools/mk$(BOARD)spl $< $@ + $(OBJTREE)/tools/mk$(BOARD)spl $(VAR_SIZE_PARAM) $< $@ endif $(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN) diff --git a/tools/mkexynosspl.c b/tools/mkexynosspl.c index ef685b7..32b786c 100644 --- a/tools/mkexynosspl.c +++ b/tools/mkexynosspl.c @@ -14,93 +14,174 @@ #include #define CHECKSUM_OFFSET (14*1024-4) -#define BUFSIZE (14*1024) #define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \ | S_IWGRP | S_IROTH | S_IWOTH) /* -* Requirement: -* IROM code reads first 14K bytes from boot device. -* It then calculates the checksum of 14K-4 bytes and compare with data at -* 14K-4 offset. -* -* This function takes two filenames: -* IN "u-boot-spl.bin" and -* OUT "$(BOARD)-spl.bin as filenames. -* It reads the "u-boot-spl.bin" in 16K buffer. -* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer. -* It writes the buffer to "$(BOARD)-spl.bin" file. -*/ + * Requirement for the fixed size SPL header: + * IROM code reads first (CHECKSUM_OFFSET + 4) bytes from boot device. It then + * calculates the checksum of CHECKSUM_OFFSET bytes and compares with data at + * CHECKSUM_OFFSET location. + * + * Requirement for the variable size SPL header: + + * IROM code reads the below header to find out the size of the blob (total + * size, header size included) and its checksum. Then it reads the rest of the + * blob [i.e size - sizeof(struct var_size_header) bytes], calculates the + * checksum and compares it with value read from the header. + */ +struct var_size_header { + uint32_t spl_size; + uint32_t spl_checksum; + uint32_t reserved[2]; +}; + +static const char *prog_name; + +static void write_to_file(int ofd, void *buffer, int size) +{ + if (write(ofd, buffer, size) == size) + return; + + fprintf(stderr, "%s: Failed to write to output file: %s\n", + prog_name, strerror(errno)); + exit(EXIT_FAILURE); +} +/* + * The argv is expected to include one optional parameter and two filenames: + * [--vs] IN OUT + * + * --vs - turns on the variable size SPL mode + * IN - the u-boot SPL binary, usually u-boot-spl.bin + * OUT - the prepared SPL blob, usually ${BOARD}-spl.bin + * + * This utility first reads the "u-boot-spl.bin" into a buffer. In case of + * fixed size SPL the buffer size is exactly CHECKSUM_OFFSET (such that + * smaller u-boot-spl.bin gets padded with 0xff bytes, the larger than limit + * u-boot-spl.bin causes an error). For variable size SPL the buffer size is + * eqaul to size of the IN file. + * + * Then it calculates checksum of the buffer by just summing up all bytes. + * Then + * + * - for fixed size SPL the buffer is written into the output file and the + * checksum is appended to the file in little endian format, which results + * in checksum added exactly at CHECKSUM_OFFSET. + * + * - for variable size SPL the checksum and file size are stored in the + * var_size_header structure (again, in little endian format) and the + * structure is written into the output file. Then the buffer is written + * into the output file. + */ int main(int argc, char **argv) { - unsigned char buffer[BUFSIZE]; + unsigned char *buffer; int i, ifd, ofd; uint32_t checksum = 0; off_t len; - ssize_t count; + int var_size_flag, read_size, count; struct stat stat; - - if (argc != 3) { - fprintf(stderr, "Usage: %s \n", argv[0]); + const int if_index = argc - 2; /* Input file name index in argv. */ + const int of_index = argc - 1; /* Output file name index in argv. */ + + /* Strip path off the program name. */ + prog_name = strrchr(argv[0], '/'); + if (prog_name) + prog_name++; + else + prog_name = argv[0]; + + if ((argc < 3) || + (argc > 4) || + ((argc == 4) && strcmp(argv[1], "--vs"))) { + fprintf(stderr, "Usage: %s [--vs] \n", + prog_name); exit(EXIT_FAILURE); } - ifd = open(argv[1], O_RDONLY); + /* four args mean variable size SPL wrapper is required */ + var_size_flag = (argc == 4); + + ifd = open(argv[if_index], O_RDONLY); if (ifd < 0) { fprintf(stderr, "%s: Can't open %s: %s\n", - argv[0], argv[1], strerror(errno)); + prog_name, argv[if_index], strerror(errno)); exit(EXIT_FAILURE); } - ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); + ofd = open(argv[of_index], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); if (ifd < 0) { fprintf(stderr, "%s: Can't open %s: %s\n", - argv[0], argv[2], strerror(errno)); - close(ifd); + prog_name, argv[of_index], strerror(errno)); exit(EXIT_FAILURE); } if (fstat(ifd, &stat)) { fprintf(stderr, "%s: Unable to get size of %s: %s\n", - argv[0], argv[1], strerror(errno)); - close(ifd); - close(ofd); + prog_name, argv[if_index], strerror(errno)); exit(EXIT_FAILURE); } len = stat.st_size; - count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET; - - if (read(ifd, buffer, count) != count) { - fprintf(stderr, "%s: Can't read %s: %s\n", - argv[0], argv[1], strerror(errno)); + if (var_size_flag) { + read_size = len; + count = len; + } else { + if (len > CHECKSUM_OFFSET) { + fprintf(stderr, + "%s: %s is too big (exceeds %d bytes)\n", + prog_name, argv[if_index], CHECKSUM_OFFSET); + exit(EXIT_FAILURE); + } + count = CHECKSUM_OFFSET; + read_size = len; + } - close(ifd); - close(ofd); + buffer = malloc(count); + if (!buffer) { + fprintf(stderr, + "%s: Failed to allocate %d bytes to store %s\n", + prog_name, count, argv[if_index]); + exit(EXIT_FAILURE); + } + if (read(ifd, buffer, read_size) != read_size) { + fprintf(stderr, "%s: Can't read %s: %s\n", + prog_name, argv[if_index], strerror(errno)); exit(EXIT_FAILURE); } - for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++) - checksum += buffer[i]; + /* Pad if needed with 0xff to make flashing faster. */ + if (read_size < count) + memset((char *)buffer + read_size, 0xff, count - read_size); + for (i = 0, checksum = 0; i < count; i++) + checksum += buffer[i]; checksum = cpu_to_le32(checksum); - memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum)); - - if (write(ofd, buffer, BUFSIZE) != BUFSIZE) { - fprintf(stderr, "%s: Can't write %s: %s\n", - argv[0], argv[2], strerror(errno)); + if (var_size_flag) { + /* Prepare and write out the variable size SPL header. */ + struct var_size_header vsh; + uint32_t spl_size; - close(ifd); - close(ofd); + memset(&vsh, 0, sizeof(vsh)); + memcpy(&vsh.spl_checksum, &checksum, sizeof(checksum)); - exit(EXIT_FAILURE); + spl_size = cpu_to_le32(count + sizeof(struct var_size_header)); + memcpy(&vsh.spl_size, &spl_size, sizeof(spl_size)); + write_to_file(ofd, &vsh, sizeof(vsh)); } + write_to_file(ofd, buffer, count); + + /* For fixed size SPL checksum is appended in the end. */ + if (!var_size_flag) + write_to_file(ofd, &checksum, sizeof(checksum)); + close(ifd); close(ofd); + free(buffer); return EXIT_SUCCESS; } -- cgit v0.10.2 From ef23b99607de0c0055e6f627c2d2be142a9ab4a6 Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Wed, 18 Dec 2013 15:43:37 +0100 Subject: board:trats1:trats2: fix adapter number This fix is necessary after increased by one the number of adapters in s3c24x0 driver. Tested on Trats and Trats2. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Cc: Minkyu Kang Cc: Lukasz Majewski Signed-off-by: Minkyu Kang diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 8aba51c..640a193 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -295,7 +295,7 @@ int power_init_board(void) */ ret = pmic_init(I2C_5); ret |= pmic_init_max8997(); - ret |= power_fg_init(I2C_8); + ret |= power_fg_init(I2C_9); ret |= power_muic_init(I2C_5); ret |= power_bat_init(0); if (ret) diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index 147de17..be15357 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -195,9 +195,9 @@ int power_init_board(void) #endif pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */ pmic_init_max77686(); - pmic_init_max77693(I2C_9); /* I2C adapter 9 - bus name soft1 */ - power_muic_init(I2C_9); /* I2C adapter 9 - bus name soft1 */ - power_fg_init(I2C_8); /* I2C adapter 8 - bus name soft0 */ + pmic_init_max77693(I2C_10); /* I2C adapter 10 - bus name soft1 */ + power_muic_init(I2C_10); /* I2C adapter 10 - bus name soft1 */ + power_fg_init(I2C_9); /* I2C adapter 9 - bus name soft0 */ power_bat_init(0); p_chrg = pmic_get("MAX77693_PMIC"); -- cgit v0.10.2 From a5e15bbb42512ee5be53967019e9649816790d7e Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Mon, 30 Dec 2013 09:40:40 +0100 Subject: board:trats2: fix default partitions and mmc env This patch add uuid disk to defualt partions necessary to restore gpt partitions and fixes mmcdev environmental variable. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 5d86a3d..c9ce828 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -160,6 +160,7 @@ #define PARTS_UMS "ums" #define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ "name="PARTS_BOOT",size=64MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ "name="PARTS_MODEM",size=100MiB,uuid=${uuid_gpt_"PARTS_MODEM"};" \ @@ -201,7 +202,7 @@ "${kernelname}\0" \ "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ "${fdtfile}\0" \ - "mmcdev=CONFIG_MMC_DEFAULT_DEV\0" \ + "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ "mmcbootpart=2\0" \ "mmcrootpart=5\0" \ "opts=always_resume=1\0" \ -- cgit v0.10.2 From 6f3bef9e30b9193dfd9962a00bcd5d6dd2a291da Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Dec 2013 13:07:17 -0200 Subject: doc: README.fuse: Add an example on how to use the fuse API on mx6q MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When using the fuse API in U-boot user must calculate the 'bank' and 'word' values. Provide a real example on how to calculate such values for the mx6q. Signed-off-by: Fabio Estevam Reviewed-by: Benoît Thébaudeau diff --git a/doc/README.imx6 b/doc/README.imx6 index 513a06e..437af2f 100644 --- a/doc/README.imx6 +++ b/doc/README.imx6 @@ -8,3 +8,79 @@ SoC. 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the 16 msbs in word 3. + +Example: + +For reading the MAC address fuses on a MX6Q: + +- The MAC address is stored in two fuse addresses (the fuse addresses are +described in the Fusemap Descriptions table from the mx6q Reference Manual): + +0x620[31:0] - MAC_ADDR[31:0] +0x630[15:0] - MAC_ADDR[47:32] + +In order to use the fuse API, we need to pass the bank and word values, which +are calculated as below: + +Fuse address for the lower MAC address: 0x620 +Base address for the fuses: 0x400 + +(0x620 - 0x400)/0x10 = 0x22 = 34 decimal + +As the fuses are arranged in banks of 8 words: + +34 / 8 = 4 and the remainder is 2, so in this case: + +bank = 4 +word = 2 + +And the U-boot command would be: + +=> fuse read 4 2 +Reading bank 4: + +Word 0x00000002: 9f027772 + +Doing the same for the upper MAC address: + +Fuse address for the upper MAC address: 0x630 +Base address for the fuses: 0x400 + +(0x630 - 0x400)/0x10 = 0x23 = 35 decimal + +As the fuses are arranged in banks of 8 words: + +35 / 8 = 4 and the remainder is 3, so in this case: + +bank = 4 +word = 3 + +And the U-boot command would be: + +=> fuse read 4 3 +Reading bank 4: + +Word 0x00000003: 00000004 + +,which matches the ethaddr value: +=> echo ${ethaddr} +00:04:9f:02:77:72 + +Some other useful hints: + +- The 'bank' and 'word' numbers can be easily obtained from the mx6 Reference +Manual. For the mx6quad case, please check the "46.5 OCOTP Memory Map/Register +Definition" from the "i.MX 6Dual/6Quad Applications Processor Reference Manual, +Rev. 1, 04/2013" document. For example, for the MAC fuses we have: + +Address: +21B_C620 Value of OTP Bank4 Word2 (MAC Address)(OCOTP_MAC0) + +21B_C630 Value of OTP Bank4 Word3 (MAC Address)(OCOTP_MAC1) + +- The command '=> fuse read 4 2 2' reads the whole MAC addresses at once: + +=> fuse read 4 2 2 +Reading bank 4: + +Word 0x00000002: 9f027772 00000004 -- cgit v0.10.2 From 5dc64ab730de14d9992c3f6ddce141d799a00106 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Dec 2013 13:07:18 -0200 Subject: mx6sabre_common.h: Add CONFIG_CMD_FUSE support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add CONFIG_CMD_FUSE option, so that the fuse API can be used. Signed-off-by: Fabio Estevam Reviewed-by: Benoît Thébaudeau diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index d52c9a8..63405aa 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -34,6 +34,11 @@ #define CONFIG_MXC_UART +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -- cgit v0.10.2 From fc740648bddbf1fdb26e6cba1a8b436a814ef8bc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 26 Dec 2013 14:51:30 -0200 Subject: mx6: soc: Staticize set_vddsoc() set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 335706a..2eee6e9 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -101,7 +101,7 @@ void init_aips(void) * Possible values are from 0.725V to 1.450V in steps of * 0.025V (25mV). */ -void set_vddsoc(u32 mv) +static void set_vddsoc(u32 mv) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 val, reg = readl(&anatop->reg_core); diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 8c21364..17125a6 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -29,8 +29,6 @@ u32 get_cpu_rev(void); const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); -void set_vddsoc(u32 mv); - /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() -- cgit v0.10.2 From e113fd1972aa921258e3219e6666bc41c9459503 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 26 Dec 2013 14:51:31 -0200 Subject: mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages Since ROM may modify the LDO ramp up time according to fuse setting, it is safer to reset the ramp up field to its default value of 00: 00: 64 cycles of 24MHz clock; 01: 128 cycles of 24MHz clock; 02: 256 cycles of 24MHz clock; 03: 512 cycles of 24MHz clock; Signed-off-by: Anson Huang Signed-off-by: Jason Liu Signed-off-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 2eee6e9..486b870 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -93,6 +93,20 @@ void init_aips(void) writel(0x00000000, &aips2->opacr4); } +static void clear_ldo_ramp(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg; + + /* ROM may modify LDO ramp up time according to fuse setting, so in + * order to be in the safe side we neeed to reset these settings to + * match the reset value: 0'b00 + */ + reg = readl(&anatop->ana_misc2); + reg &= ~(0x3f << 24); + writel(reg, &anatop->ana_misc2); +} + /* * Set the VDDSOC * @@ -113,6 +127,8 @@ static void set_vddsoc(u32 mv) else val = (mv - 700) / 25; + clear_ldo_ramp(); + /* * Mask out the REG_CORE[22:18] bits (REG2_TRIG) * and set them to the calculated value (0.7V + val * 0.25V) -- cgit v0.10.2 From 7e5e8c94a9dd6654285aff96e0ff45a353ed79fa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 26 Dec 2013 14:51:32 -0200 Subject: mx6: soc: Set the VDDSOC at 1.175 V mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V. Add a 25 mV margin and set it to 1.175V. This also matches the VDDSOC voltages for 792MHz operation that the kernel configures: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 486b870..3e095aa 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -151,7 +151,7 @@ int arch_cpu_init(void) { init_aips(); - set_vddsoc(1200); /* Set VDDSOC to 1.2V */ + set_vddsoc(1175); /* Set VDDSOC to 1.175V */ imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ -- cgit v0.10.2 From 3d622b78bdd6832f6fa8599aaf31de541bf04ea8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 26 Dec 2013 14:51:33 -0200 Subject: mx6: soc: Introduce set_ldo_voltage() Introduce set_ldo_voltage() so that all three LDO regulators can be configured. Signed-off-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 3e095aa..d8ccf3a 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -19,6 +19,12 @@ #include #include +enum ldo_reg { + LDO_ARM, + LDO_SOC, + LDO_PU, +}; + struct scu_regs { u32 ctrl; u32 config; @@ -115,10 +121,11 @@ static void clear_ldo_ramp(void) * Possible values are from 0.725V to 1.450V in steps of * 0.025V (25mV). */ -static void set_vddsoc(u32 mv) +static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 val, reg = readl(&anatop->reg_core); + u8 shift; if (mv < 725) val = 0x00; /* Power gated off */ @@ -129,12 +136,24 @@ static void set_vddsoc(u32 mv) clear_ldo_ramp(); - /* - * Mask out the REG_CORE[22:18] bits (REG2_TRIG) - * and set them to the calculated value (0.7V + val * 0.25V) - */ - reg = (reg & ~(0x1F << 18)) | (val << 18); + switch (ldo) { + case LDO_SOC: + shift = 18; + break; + case LDO_PU: + shift = 9; + break; + case LDO_ARM: + shift = 0; + break; + default: + return -EINVAL; + } + + reg = (reg & ~(0x1F << shift)) | (val << shift); writel(reg, &anatop->reg_core); + + return 0; } static void imx_set_wdog_powerdown(bool enable) @@ -151,7 +170,7 @@ int arch_cpu_init(void) { init_aips(); - set_vddsoc(1175); /* Set VDDSOC to 1.175V */ + set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ -- cgit v0.10.2 From 39f0ac9347ed825089181c4b57ea9326332e66c3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 26 Dec 2013 14:51:34 -0200 Subject: mx6: soc: Add the required LDO ramp up delay When changing LDO voltages we need to wait for the required amount of time for the voltage to settle. Also, as the timer is still not available when arch_cpu_init() is called, we need to call it later at board_postclk_init() phase. Signed-off-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index d8ccf3a..0208cba 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -124,7 +124,7 @@ static void clear_ldo_ramp(void) static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - u32 val, reg = readl(&anatop->reg_core); + u32 val, step, old, reg = readl(&anatop->reg_core); u8 shift; if (mv < 725) @@ -150,9 +150,20 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) return -EINVAL; } + old = (reg & (0x1F << shift)) >> shift; + step = abs(val - old); + if (step == 0) + return 0; + reg = (reg & ~(0x1F << shift)) | (val << shift); writel(reg, &anatop->reg_core); + /* + * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per + * step + */ + udelay(3 * step); + return 0; } @@ -170,8 +181,6 @@ int arch_cpu_init(void) { init_aips(); - set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ - imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ #ifdef CONFIG_APBH_DMA @@ -182,6 +191,13 @@ int arch_cpu_init(void) return 0; } +int board_postclk_init(void) +{ + set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ + + return 0; +} + #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 674bcd3..514d634 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -20,5 +20,6 @@ #define CONFIG_ARM_ERRATA_742230 #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 +#define CONFIG_BOARD_POSTCLK_INIT #endif -- cgit v0.10.2 From 02229827804980e3cce48bf4fce43699046bcf7e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 26 Dec 2013 14:51:35 -0200 Subject: mx6: soc: Disable VDDPU regulator As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang Signed-off-by: Jason Liu Signed-off-by: Fabio Estevam diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 0208cba..009a644 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -19,6 +19,8 @@ #include #include +#define VDDPU_MASK (0x1f << 9) + enum ldo_reg { LDO_ARM, LDO_SOC, @@ -177,11 +179,50 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } +static void imx_set_vddpu_power_down(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR; + + u32 reg; + + /* + * Disable the brown out detection since we are going to be + * disabling the LDO. + */ + reg = readl(&anatop->ana_misc2); + reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN; + writel(reg, &anatop->ana_misc2); + + /* need to power down xPU in GPC before turning off PU LDO */ + reg = readl(&gpc->gpu_ctrl); + writel(reg | 0x1, &gpc->gpu_ctrl); + + reg = readl(&gpc->ctrl); + writel(reg | 0x1, &gpc->ctrl); + while (readl(&gpc->ctrl) & 0x1) + ; + + /* Mask the ANATOP brown out interrupt in the GPC. */ + reg = readl(&gpc->imr4); + reg |= 0x80000000; + writel(reg, &gpc->imr4); + + /* disable VDDPU */ + writel(VDDPU_MASK, &anatop->reg_core_clr); + + /* Clear the BO interrupt in the ANATOP. */ + reg = readl(&anatop->ana_misc1); + reg |= 0x80000000; + writel(reg, &anatop->ana_misc1); +} + int arch_cpu_init(void) { init_aips(); imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ + imx_set_vddpu_power_down(); #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 7202073..aede126 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -890,4 +890,5 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) +#define ANADIG_ANA_MISC2_REG1_BO_EN (1 << 13) #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 7ef7152..fb0c4c7 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -659,5 +659,28 @@ struct wdog_regs { u16 wmcr; /* Miscellaneous Control */ }; +struct gpc_regs { + u32 ctrl; /* 0x000 */ + u32 pgr; /* 0x004 */ + u32 imr1; /* 0x008 */ + u32 imr2; /* 0x00c */ + u32 imr3; /* 0x010 */ + u32 imr4; /* 0x014 */ + u32 isr1; /* 0x018 */ + u32 isr2; /* 0x01c */ + u32 isr3; /* 0x020 */ + u32 isr4; /* 0x024 */ + u32 reserved1[0x86]; + u32 gpu_ctrl; /* 0x260 */ + u32 gpu_pupscr; /* 0x264 */ + u32 gpu_pdnscr; /* 0x268 */ + u32 gpu_sr; /* 0x26c */ + u32 reserved2[0xc]; + u32 cpu_ctrl; /* 0x2a0 */ + u32 cpu_pupscr; /* 0x2a4 */ + u32 cpu_pdnscr; /* 0x2a8 */ + u32 cpu_sr; /* 0x2ac */ +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ -- cgit v0.10.2 From 7773fd196918826ebaab769e63a4775607f5256c Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 16 Dec 2013 20:44:00 -0200 Subject: imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau , Fabio Estevam and Eric Bénard for helping to properly trace this down. Signed-off-by: Otavio Salvador Acked-by: Stefano Babic diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dc2b3ef..dec11a1 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -63,6 +63,8 @@ typedef u64 iomux_v3_cfg_t; #define MUX_SEL_INPUT_SHIFT 59 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) +#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ + MUX_MODE_SHIFT) #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ -- cgit v0.10.2 From 4d64050b065cd45f0c62dba657bf886f93ace0c1 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 16 Dec 2013 20:44:01 -0200 Subject: mx28evk: Use 512k for fdt partition to align it Using 512k for fdt partition allow it to be aligned with the other small partitions and 512k erase block size. Signed-off-by: Otavio Salvador Acked-by: Stefano Babic diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 22fdb3a..3de0599 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -96,7 +96,7 @@ "512k(environment)," \ "512k(redundant-environment)," \ "4m(kernel)," \ - "128k(fdt)," \ + "512k(fdt)," \ "8m(ramdisk)," \ "-(filesystem)" #endif -- cgit v0.10.2 From 09308e8e4953886951a3b5921d6944584e997dc0 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 16 Dec 2013 20:44:02 -0200 Subject: mx28evk: Add 'nandboot' environment command This reads the kernel, ftd and boot into ubifs filesystem. While on that, the SD firmware filename definition has been moved next to the other SD related commands. Signed-off-by: Otavio Salvador Reviewed-by: Fabio Estevam diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 3de0599..6c9fa00 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -162,7 +162,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ - "update_sd_firmware_filename=u-boot.sd\0" \ "update_nand_firmware_maxsz=0x100000\0" \ "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ @@ -190,6 +189,23 @@ "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ "fi\0" \ + "nandargs=setenv bootargs console=${console_mainline},${baudrate} " \ + "rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \ + "nandboot=" /* Boot from NAND */ \ + "mtdparts default; " \ + "run nandargs; " \ + "nand read ${loadaddr} kernel 0x00400000; " \ + "if test ${boot_fdt} = yes; then " \ + "nand read ${fdt_addr} fdt 0x00080000; " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = no; then " \ + "bootm; " \ + "else " \ + "echo \"ERROR: Set boot_fdt to yes or no.\"; " \ + "fi; " \ + "fi\0" \ + "update_sd_firmware_filename=u-boot.sd\0" \ "update_sd_firmware=" /* Update the SD firmware partition */ \ "if mmc rescan ; then " \ "if tftp ${update_sd_firmware_filename} ; then " \ -- cgit v0.10.2 From 8ae269d41e2551439284d2c837c476ae4a357032 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 16 Dec 2013 20:44:03 -0200 Subject: mx28evk: Extend environment to easy write of NAND system This adds following new targets: - update_nand_kernel - update_nand_fdt - update_nand_filesystem and to avoid confusion, the 'update_nand_full' has been renamed to 'update_nand_firmware_full'. Signed-off-by: Otavio Salvador diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 6c9fa00..4fd67eb 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -160,6 +160,7 @@ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ + "ubifs_file=filesystem.ubifs\0" \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ "update_nand_firmware_maxsz=0x100000\0" \ @@ -170,7 +171,7 @@ "nand info ; " \ "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ - "update_nand_full=" /* Update FCB, DBBT and FW */ \ + "update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \ "if tftp ${update_nand_full_filename} ; then " \ "run update_nand_get_fcb_size ; " \ "nand scrub -y 0x0 ${filesize} ; " \ @@ -189,6 +190,38 @@ "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ "fi\0" \ + "update_nand_kernel=" /* Update kernel */ \ + "mtdparts default; " \ + "nand erase.part kernel; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "nand write ${loadaddr} kernel ${filesize}\0" \ + "update_nand_fdt=" /* Update fdt */ \ + "mtdparts default; " \ + "nand erase.part fdt; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${fdt_file}; " \ + "nand write ${loadaddr} fdt ${filesize}\0" \ + "update_nand_filesystem=" /* Update filesystem */ \ + "mtdparts default; " \ + "nand erase.part filesystem; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${ubifs_file}; " \ + "ubi part filesystem; " \ + "ubi create filesystem; " \ + "ubi write ${loadaddr} filesystem ${filesize}\0" \ "nandargs=setenv bootargs console=${console_mainline},${baudrate} " \ "rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \ "nandboot=" /* Boot from NAND */ \ -- cgit v0.10.2 From 6584a1b52624d60249c3d5115b176315dbac3939 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 16 Dec 2013 20:44:04 -0200 Subject: ARM: mx6: Change the FDT loading address to avoid overlaping This patch fixes allow for the DeviceTree and initrd relocation fixing the boot of FSL 3.10.9-1.0.0-alpha kernel. This changes following boards: - mx6sabreauto - mx6sabresd - wandboard - udoo - nitrogen6x - cgtqmx6eval The reasoning, as explained by Hui Liu, is: ,---- | The FDT blob will be placed at DDR physical addr: 0x11000000. When Linux kernel | Boot up, it will decompress the compressed kernel image and place the decompressed | kernel image at the low end of the DDR memory and start running from it. If the | decompressed kernel image is bigger for example than 16M, it may over written the | fdt blob which u-boot loaded to the DDR memory @0x11000000 with fdt_addr=0x11000000 | | To expand the fdt_addr from 0x11000000 to 0x18000000, which can avoid the override | Since we will not likely have one kernel image larger than 128MB. `---- Signed-off-by: Otavio Salvador Acked-by: Stefano Babic diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index d5db8f5..29a023c 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -81,7 +81,7 @@ "console=ttymxc1\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x11000000\0" \ + "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "mmcdev=1\0" \ "mmcpart=1\0" \ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 63405aa..21c848f 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -99,7 +99,7 @@ "script=boot.scr\0" \ "uimage=uImage\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x11000000\0" \ + "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "console=" CONFIG_CONSOLE_DEV "\0" \ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 9c9f8f7..f4ff5cd 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -180,7 +180,7 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=imx6q-sabrelite.dtb\0" \ - "fdt_addr=0x11000000\0" \ + "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev=0\0" \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 4d96f18..614e1fe 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -106,7 +106,7 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x11000000\0" \ + "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev=0\0" \ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 8ce2d6e..ae8480d 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -114,7 +114,7 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x11000000\0" \ + "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ -- cgit v0.10.2 From c655b816e55464bf615e875475b8ffa506a4455e Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 16 Dec 2013 20:44:05 -0200 Subject: ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6 The enable_fec_anatop_clock method should be available for all MX6 variant as it is not MX6 SoloLite specific. This moves the code out of the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC instead. Signed-off-by: Otavio Salvador Acked-by: Stefano Babic diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 20c7e70..fcc4f35 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -310,7 +310,18 @@ static u32 get_mmdc_ch0_clk(void) return freq / (podf + 1); } +#else +static u32 get_mmdc_ch0_clk(void) +{ + u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); + u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >> + MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET; + + return get_periph_clk() / (mmdc_ch0_podf + 1); +} +#endif +#ifdef CONFIG_FEC_MXC int enable_fec_anatop_clock(void) { u32 reg = 0; @@ -339,16 +350,6 @@ int enable_fec_anatop_clock(void) return 0; } - -#else -static u32 get_mmdc_ch0_clk(void) -{ - u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); - u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >> - MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET; - - return get_periph_clk() / (mmdc_ch0_podf + 1); -} #endif static u32 get_usdhc_clk(u32 port) -- cgit v0.10.2 From 4611d5bab26f93471b84f6f33967cef69b3f723a Mon Sep 17 00:00:00 2001 From: Sergey Alyoshin Date: Tue, 17 Dec 2013 23:24:54 +0400 Subject: arm: mx5: Add fuse supply enable in fsl_iim MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin Reviewed-by: Benoît Thébaudeau diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index fb3b128..bf52f0d 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable) MXC_CCM_CCGR5_EMI_ENFC(cg)); } +#ifdef CONFIG_FSL_IIM +void enable_efuse_prog_supply(bool enable) +{ + if (enable) + setbits_le32(&mxc_ccm->cgpr, + MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE); + else + clrbits_le32(&mxc_ccm->cgpr, + MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE); +} +#endif + /* Config main_bus_clock for periphs */ static int config_periph_clk(u32 ref, u32 freq) { diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 9ee79ae..3db4112 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable); void mxc_set_sata_internal_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_nfc_clk(unsigned char enable); +void enable_efuse_prog_supply(bool enable); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index 392881c..efe57e0 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -305,6 +305,9 @@ struct mxc_ccm_reg { /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) +/* Define the bits in register CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) + /* Define the bits in register CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 #define MXC_CCM_CCGR_CG_OFF 0x0 diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c index 44ae7b1..36433a7 100644 --- a/drivers/misc/fsl_iim.c +++ b/drivers/misc/fsl_iim.c @@ -16,6 +16,9 @@ #ifndef CONFIG_MPC512X #include #endif +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) +#include +#endif /* FSL IIM-specific constants */ #define STAT_BUSY 0x80 @@ -93,6 +96,10 @@ struct fsl_iim { } bank[8]; }; +#if !defined(CONFIG_MX51) && !defined(CONFIG_MX53) +#define enable_efuse_prog_supply(enable) +#endif + static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert, const char *caller) { @@ -237,12 +244,16 @@ int fuse_prog(u32 bank, u32 word, u32 val) if (ret) return ret; + enable_efuse_prog_supply(1); for (bit = 0; val; bit++, val >>= 1) if (val & 0x01) { ret = prog_bit(regs, bank, word, bit); - if (ret) + if (ret) { + enable_efuse_prog_supply(0); return ret; + } } + enable_efuse_prog_supply(0); return 0; } -- cgit v0.10.2 From 57226221f4becb629026ad78b3be55fa3247fbeb Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Thu, 31 Oct 2013 04:05:05 +0100 Subject: kirkwood: ib62x0: use device tree and update config Signed-off-by: Luka Perkov CC: Prafulla Wadaskar Acked-By: Prafulla Wadaskar diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index 7fa0c53..186fd35 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -28,6 +28,11 @@ #define CONFIG_MACH_TYPE MACH_TYPE_NAS6210 /* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* * Compression configuration */ #define CONFIG_BZIP2 @@ -41,6 +46,7 @@ #define CONFIG_SYS_MVFS #include #define CONFIG_CMD_ENV +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_IDE #define CONFIG_CMD_MII #define CONFIG_CMD_NAND @@ -66,7 +72,7 @@ #define CONFIG_ENV_IS_NOWHERE #endif #define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_OFFSET 0xe0000 /* * Default environment variables @@ -74,24 +80,26 @@ #define CONFIG_BOOTCOMMAND \ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ "ubi part root; " \ - "ubifsmount ubi:root; " \ + "ubifsmount ubi:rootfs; " \ "ubifsload 0x800000 ${kernel}; " \ - "ubifsload 0x1100000 ${initrd}; " \ - "bootm 0x800000 0x1100000" - -#define CONFIG_MTDPARTS \ - "mtdparts=orion_nand:" \ - "0x80000@0x0(uboot)," \ - "0x20000@0x80000(uboot_env)," \ - "-@0xa0000(root)\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ + "ubifsload 0x700000 ${fdt}; " \ + "ubifsumount; " \ + "fdt addr 0x700000; fdt resize; fdt chosen; " \ + "bootz 0x800000 - 0x700000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0xe0000@0x0(uboot)," \ + "0x20000@0xe0000(uboot_env)," \ + "-@0x100000(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "mtdids=nand0=orion_nand\0" \ "mtdparts="CONFIG_MTDPARTS \ - "kernel=/boot/uImage\0" \ - "initrd=/boot/uInitrd\0" \ - "bootargs_root=ubi.mtd=2 root=ubi0:root rootfstype=ubifs\0" + "kernel=/boot/zImage\0" \ + "fdt=/boot/ib62x0.dtb\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" /* * Ethernet driver configuration -- cgit v0.10.2 From 5e4eeab92bb900ebb79e42deec601511071f17f1 Mon Sep 17 00:00:00 2001 From: Karlheinz Jerg Date: Wed, 18 Sep 2013 09:32:48 +0200 Subject: arm/km: add support for km_kirkwood_128m16 board The board is similar to the standard km_kirkwood board. From a u-boot point of view, the only difference is an increased 256 MiB DRAM (128M16). A board based on this design is for example the SUP12. Signed-off-by: Karlheinz Jerg Signed-off-by: Holger Brunck diff --git a/boards.cfg b/boards.cfg index 9949bb5..01ff5b5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -171,6 +171,7 @@ Active arm arm926ejs kirkwood iomega - Active arm arm926ejs kirkwood karo tk71 tk71 - - Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp +Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_128m16 km_kirkwood:KM_KIRKWOOD_128M16 Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 0e6073c..b8b64c4 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -35,6 +35,16 @@ #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ #define CONFIG_KM_FPGA_CONFIG +/* KM_KIRKWOOD_128M16 */ +#elif defined(CONFIG_KM_KIRKWOOD_128M16) +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood 128M16" +#define CONFIG_HOSTNAME km_kirkwood_128m16 +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_KM_DISABLE_PCIE +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ + /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ -- cgit v0.10.2 From e28d4a272f4e59185581f9c7252016872b4681e6 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Mon, 7 Oct 2013 15:10:03 +0200 Subject: arm/km: fix i2c mux define for km_kirkwood_128m16 target Due to the i2c mux rework in u-boot we now have only to specify the busnumber and not the whole mux configuration. Signed-off-by: Holger Brunck Acked-by: Heiko Schocher diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index b8b64c4..74c7232 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -43,7 +43,7 @@ #define CONFIG_SYS_KWD_CONFIG \ $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_DISABLE_PCIE -#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) -- cgit v0.10.2 From d8794da53b918929b6345e3d64dd74861aab086d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 18 Dec 2013 14:43:08 -0500 Subject: cam_enc_4xx: Set CONFIG_SYS_NAND_MAX_OOBFREE / CONFIG_SYS_NAND_MAX_ECCPOS With the changes to make OOBFREE/ECCPOS configurable but default to larger, we need to set these config options for the space savings they provide. Cc: Scott Wood Cc: Heiko Schocher Signed-off-by: Tom Rini diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index c1042ae..8182a75 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -236,6 +236,8 @@ #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_NAND_ECCSIZE 0x200 #define CONFIG_SYS_NAND_ECCBYTES 10 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_5_ADDR_CYCLE -- cgit v0.10.2 From 456ccfdf0d5eefc153b143bd13731a59e2d71585 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 20 Dec 2013 11:19:33 -0500 Subject: TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini diff --git a/board/logicpd/zoom2/Makefile b/board/logicpd/zoom2/Makefile deleted file mode 100644 index 8ec5f25..0000000 --- a/board/logicpd/zoom2/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := zoom2.o -obj-y += debug_board.o -obj-y += zoom2_serial.o -obj-$(CONFIG_STATUS_LED) += led.o diff --git a/board/logicpd/zoom2/config.mk b/board/logicpd/zoom2/config.mk deleted file mode 100644 index 1c382f7..0000000 --- a/board/logicpd/zoom2/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2009 -# Texas Instruments, -# -# Zoom II uses OMAP3 (ARM-CortexA8) CPU -# see http://www.ti.com/ for more information on Texas Instruments -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Physical Address: -# 0x80000000 (bank0) -# 0xA0000000 (bank1) -# Linux-Kernel is expected to be at 0x80008000, entry 0x80008000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/logicpd/zoom2/debug_board.c b/board/logicpd/zoom2/debug_board.c deleted file mode 100644 index 071f410..0000000 --- a/board/logicpd/zoom2/debug_board.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include - -#define DEBUG_BOARD_CONNECTED 1 -#define DEBUG_BOARD_NOT_CONNECTED 0 - -static int debug_board_connected = DEBUG_BOARD_CONNECTED; - -static void zoom2_debug_board_detect (void) -{ - int val = 0; - - if (!gpio_request(158, "")) { - /* - * GPIO to query for debug board - * 158 db board query - */ - gpio_direction_input(158); - val = gpio_get_value(158); - } - - if (!val) - debug_board_connected = DEBUG_BOARD_NOT_CONNECTED; -} - -int zoom2_debug_board_connected (void) -{ - static int first_time = 1; - - if (first_time) { - zoom2_debug_board_detect (); - first_time = 0; - } - return debug_board_connected; -} diff --git a/board/logicpd/zoom2/led.c b/board/logicpd/zoom2/led.c deleted file mode 100644 index 5d37ac1..0000000 --- a/board/logicpd/zoom2/led.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include - -static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; - -/* - * GPIO LEDs - * 173 red - * 154 blue - * 61 blue2 - */ -#define ZOOM2_LED_RED 173 -#define ZOOM2_LED_BLUE 154 -#define ZOOM2_LED_BLUE2 61 - -void red_led_off(void) -{ - /* red */ - if (!gpio_request(ZOOM2_LED_RED, "")) { - gpio_direction_output(ZOOM2_LED_RED, 0); - gpio_set_value(ZOOM2_LED_RED, 0); - } - saved_state[STATUS_LED_RED] = STATUS_LED_OFF; -} - -void blue_led_off(void) -{ - /* blue */ - if (!gpio_request(ZOOM2_LED_BLUE, "")) { - gpio_direction_output(ZOOM2_LED_BLUE, 0); - gpio_set_value(ZOOM2_LED_BLUE, 0); - } - - /* blue 2 */ - if (!gpio_request(ZOOM2_LED_BLUE2, "")) { - gpio_direction_output(ZOOM2_LED_BLUE2, 0); - gpio_set_value(ZOOM2_LED_BLUE2, 0); - } - saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF; -} - -void red_led_on(void) -{ - blue_led_off(); - - /* red */ - if (!gpio_request(ZOOM2_LED_RED, "")) { - gpio_direction_output(ZOOM2_LED_RED, 0); - gpio_set_value(ZOOM2_LED_RED, 1); - } - saved_state[STATUS_LED_RED] = STATUS_LED_ON; -} - -void blue_led_on(void) -{ - red_led_off(); - - /* blue */ - if (!gpio_request(ZOOM2_LED_BLUE, "")) { - gpio_direction_output(ZOOM2_LED_BLUE, 0); - gpio_set_value(ZOOM2_LED_BLUE, 1); - } - - /* blue 2 */ - if (!gpio_request(ZOOM2_LED_BLUE2, "")) { - gpio_direction_output(ZOOM2_LED_BLUE2, 0); - gpio_set_value(ZOOM2_LED_BLUE2, 1); - } - - saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; -} - -void __led_init (led_id_t mask, int state) -{ - __led_set (mask, state); -} - -void __led_toggle (led_id_t mask) -{ - if (STATUS_LED_BLUE == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE]) - blue_led_off(); - else - blue_led_on(); - } else if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) - red_led_off(); - else - red_led_on(); - } -} - -void __led_set (led_id_t mask, int state) -{ - if (STATUS_LED_BLUE == mask) { - if (STATUS_LED_ON == state) - blue_led_on(); - else - blue_led_off(); - } else if (STATUS_LED_RED == mask) { - if (STATUS_LED_ON == state) - red_led_on(); - else - red_led_off(); - } -} diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c deleted file mode 100644 index e14de04..0000000 --- a/board/logicpd/zoom2/zoom2.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * Derived from Zoom1 code by - * Nishanth Menon - * Sunil Kumar - * Shashi Ranjan - * Richard Woodruff - * Syed Mohammed Khasim - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include "zoom2.h" -#include "zoom2_serial.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * This the the zoom2, board specific, gpmc configuration for the - * quad uart on the debug board. The more general gpmc configurations - * are setup at the cpu level in arch/arm/cpu/armv7/omap3/mem.c - * - * The details of the setting of the serial gpmc setup are not available. - * The values were provided by another party. - */ -static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { - 0x00011000, - 0x001F1F01, - 0x00080803, - 0x1D091D09, - 0x041D1F1F, - 0x1D0904C4, 0 -}; - -/* Used to track the revision of the board */ -static zoom2_revision revision = ZOOM2_REVISION_UNKNOWN; - -/* - * Routine: zoom2_get_revision - * Description: Return the revision of the Zoom2 this code is running on. - */ -zoom2_revision zoom2_get_revision(void) -{ - return revision; -} - -/* - * Routine: zoom2_identify - * Description: Detect which version of Zoom2 we are running on. - */ -void zoom2_identify(void) -{ - /* - * To check for production board vs beta board, - * check if gpio 94 is clear. - * - * No way yet to check for alpha board identity. - * Alpha boards were produced in very limited quantities - * and they are not commonly used. They are mentioned here - * only for completeness. - */ - if (!gpio_request(94, "")) { - unsigned int val; - - gpio_direction_input(94); - val = gpio_get_value(94); - - if (val) - revision = ZOOM2_REVISION_BETA; - else - revision = ZOOM2_REVISION_PRODUCTION; - } - - printf("Board revision "); - switch (revision) { - case ZOOM2_REVISION_PRODUCTION: - printf("Production\n"); - break; - case ZOOM2_REVISION_BETA: - printf("Beta\n"); - break; - default: - printf("Unknown\n"); - break; - } -} - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init (void) -{ - u32 *gpmc_config; - - gpmc_init (); /* in SRAM or SDRAM, finish GPMC */ - - /* Configure console support on zoom2 */ - gpmc_config = gpmc_serial_TL16CP754C; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3], - SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M); - - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - -#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) - status_led_set (STATUS_LED_BOOT, STATUS_LED_ON); -#endif - return 0; -} - -/* - * Routine: misc_init_r - * Description: Configure zoom board specific configurations - */ -int misc_init_r(void) -{ - zoom2_identify(); - twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - dieid_num_r(); - - /* - * Board Reset - * The board is reset by holding the the large button - * on the top right side of the main board for - * eight seconds. - * - * There are reported problems of some beta boards - * continously resetting. For those boards, disable resetting. - */ - if (ZOOM2_REVISION_PRODUCTION <= zoom2_get_revision()) - twl4030_power_reset_init(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs (void) -{ - /* platform specific muxes */ - MUX_ZOOM2 (); -} - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/logicpd/zoom2/zoom2.h b/board/logicpd/zoom2/zoom2.h deleted file mode 100644 index 850c790..0000000 --- a/board/logicpd/zoom2/zoom2.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * Derived from: board/omap3/zoom1/zoom1.h - * Nishanth Menon - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _BOARD_ZOOM2_H_ -#define _BOARD_ZOOM2_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 Zoom2 ", - "NAND", -}; - -typedef enum { - ZOOM2_REVISION_UNKNOWN = 0, - ZOOM2_REVISION_ALPHA, - ZOOM2_REVISION_BETA, - ZOOM2_REVISION_PRODUCTION -} zoom2_revision; - -zoom2_revision zoom2_get_revision(void); - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_ZOOM2() \ - /* SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ -/* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /* GPMC_nCS1 */\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /* GPMC_nCS2 */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /* GPMC_nCS3 */\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /* GPMC_nCS4 */\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /* GPMC_nCS6 */\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /* GPMC_nCS7 */\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ - MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /* GPMC_nWP */\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /* GPMC_WAIT0 */\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /* GPMC_WAIT1 */\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /* GPMC_WAIT2 */\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /* GPMC_WAIT3 */\ -/* IDCC modem Power On */\ - MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /* GPIO_110 */\ - MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /* GPIO_103 */\ -/* GPMC CS7 has LAN9211 device */\ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /* LAN9221 */\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M0)) /* MCSPI1_CS2 */\ -/* GPMC CS3 has Serial TL16CP754C device */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPMC_nCS3 */\ -/* Toggle Reset pin of TL16CP754C device */\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTU | EN | M4)) /* GPIO_152 */\ - udelay(10);\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M4)) /* GPIO_152 */\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */\ -/* LEDS */\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M4)) /* GPIO_173 red */\ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | EN | M4)) /* GPIO_154 blue */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | EN | M4)) /* GPIO_61 blue2 */ - -#endif /* _BOARD_ZOOM2_H_ */ diff --git a/board/logicpd/zoom2/zoom2_serial.c b/board/logicpd/zoom2/zoom2_serial.c deleted file mode 100644 index 2959276..0000000 --- a/board/logicpd/zoom2/zoom2_serial.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - * - * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c - */ - -#include -#include -#include -#include -#include "zoom2_serial.h" - -int quad_init_dev (unsigned long base) -{ - /* - * The Quad UART is on the debug board. - * Check if the debug board is attached before using the UART - */ - if (zoom2_debug_board_connected ()) { - NS16550_t com_port = (NS16550_t) base; - int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 / - CONFIG_BAUDRATE; - - /* - * Zoom2 has a board specific initialization of its UART. - * This generic initialization has been copied from - * drivers/serial/ns16550.c. The macros have been expanded. - * - * Do the following instead of - * - * NS16550_init (com_port, clock_divisor); - */ - com_port->ier = 0x00; - - /* - * On Zoom2 board Set pre-scalar to 1 - * CLKSEL is GND => MCR[7] is 1 => preslr is 4 - * So change the prescl to 1 - */ - com_port->lcr = 0xBF; - com_port->fcr |= 0x10; - com_port->mcr &= 0x7F; - - /* This is generic ns16550.c setup */ - com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; - com_port->dll = 0; - com_port->dlm = 0; - com_port->lcr = UART_LCR_8N1; - com_port->mcr = UART_MCR_DTR | UART_MCR_RTS; - com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | - UART_FCR_TXSR; - com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = UART_LCR_8N1; - } - /* - * We have to lie here, otherwise the board init code will hang - * on the check - */ - return 0; -} - -void quad_putc_dev (unsigned long base, const char c) -{ - if (zoom2_debug_board_connected ()) { - - if (c == '\n') - quad_putc_dev (base, '\r'); - - NS16550_putc ((NS16550_t) base, c); - } else { - usbtty_putc(c); - } -} - -void quad_puts_dev (unsigned long base, const char *s) -{ - if (zoom2_debug_board_connected ()) { - while ((s != NULL) && (*s != '\0')) - quad_putc_dev (base, *s++); - } else { - usbtty_puts(s); - } -} - -int quad_getc_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) - return NS16550_getc ((NS16550_t) base); - - return usbtty_getc(); -} - -int quad_tstc_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) - return NS16550_tstc ((NS16550_t) base); - - return usbtty_tstc(); -} - -void quad_setbrg_dev (unsigned long base) -{ - if (zoom2_debug_board_connected ()) { - - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / - CONFIG_BAUDRATE; - - NS16550_reinit ((NS16550_t) base, clock_divisor); - } -} - -QUAD_INIT (0) -QUAD_INIT (1) -QUAD_INIT (2) -QUAD_INIT (3) - -struct serial_device *default_serial_console(void) -{ - switch (ZOOM2_DEFAULT_SERIAL_DEVICE) { - case 0: return &zoom2_serial_device0; - case 1: return &zoom2_serial_device1; - case 2: return &zoom2_serial_device2; - case 3: return &zoom2_serial_device3; - } -} diff --git a/board/logicpd/zoom2/zoom2_serial.h b/board/logicpd/zoom2/zoom2_serial.h deleted file mode 100644 index 8224452..0000000 --- a/board/logicpd/zoom2/zoom2_serial.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef ZOOM2_SERIAL_H -#define ZOOM2_SERIAL_H - -#include - -extern int zoom2_debug_board_connected (void); - -#define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom2 Serial chip address */ - -#define QUAD_BASE_0 SERIAL_TL16CP754C_BASE -#define QUAD_BASE_1 (SERIAL_TL16CP754C_BASE + 0x100) -#define QUAD_BASE_2 (SERIAL_TL16CP754C_BASE + 0x200) -#define QUAD_BASE_3 (SERIAL_TL16CP754C_BASE + 0x300) - -#define QUAD_INIT(n) \ -int quad_init_##n(void) \ -{ \ - return quad_init_dev(QUAD_BASE_##n); \ -} \ -void quad_setbrg_##n(void) \ -{ \ - quad_setbrg_dev(QUAD_BASE_##n); \ -} \ -void quad_putc_##n(const char c) \ -{ \ - quad_putc_dev(QUAD_BASE_##n, c); \ -} \ -void quad_puts_##n(const char *s) \ -{ \ - quad_puts_dev(QUAD_BASE_##n, s); \ -} \ -int quad_getc_##n(void) \ -{ \ - return quad_getc_dev(QUAD_BASE_##n); \ -} \ -int quad_tstc_##n(void) \ -{ \ - return quad_tstc_dev(QUAD_BASE_##n); \ -} \ -struct serial_device zoom2_serial_device##n = \ -{ \ - .name = __stringify(n), \ - .start = quad_init_##n, \ - .stop = NULL, \ - .setbrg = quad_setbrg_##n, \ - .getc = quad_getc_##n, \ - .tstc = quad_tstc_##n, \ - .putc = quad_putc_##n, \ - .puts = quad_puts_##n, \ -}; - -#endif /* ZOOM2_SERIAL_H */ diff --git a/boards.cfg b/boards.cfg index 9949bb5..a49fa66 100644 --- a/boards.cfg +++ b/boards.cfg @@ -326,7 +326,6 @@ Active arm armv7 omap3 isee igep00x0 Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon -Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár Active arm armv7 omap3 technexion tao3530 omap3_ha tao3530:SYS_BOARD_OMAP3_HA Stefan Roese diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 181c818..fbc37b2 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -56,9 +56,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) ; serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); -#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ - defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX) || \ - defined(CONFIG_AM43XX) +#if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \ + defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h deleted file mode 100644 index f749740..0000000 --- a/include/configs/omap3_zoom2.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * Nishanth Menon - * Tom Rix - * - * Configuration settings for the TI OMAP3430 Zoom II board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON - -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include /* get chip and board defs */ -#include - -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - * Zoom2 uses the TL16CP754C on the debug board - */ -/* - * 0 - 1 : first USB with respect to the left edge of the debug board - * 2 - 3 : second USB with respect to the left edge of the debug board - */ -#define ZOOM2_DEFAULT_SERIAL_DEVICE 0 - -#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_REG_SIZE (-2) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200} - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - -/* Status LED */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED 1 -#define STATUS_LED_BLUE 0 -#define STATUS_LED_RED 1 -/* Blue */ -#define STATUS_LED_BIT STATUS_LED_BLUE -#define STATUS_LED_STATE STATUS_LED_ON -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -/* Red */ -#define STATUS_LED_BIT1 STATUS_LED_RED -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) -/* Optional value */ -#define STATUS_LED_BOOT STATUS_LED_BIT - -/* GPIO banks */ -#ifdef CONFIG_STATUS_LED -#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */ -#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */ -#endif -#define CONFIG_OMAP3_GPIO_3 /* board revision */ -#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */ - -/* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "Zoom2" - -/* commands to include */ -#include - -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ -#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ - -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMI /* iminfo */ -#undef CONFIG_CMD_IMLS /* List all found images */ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#undef CONFIG_CMD_NFS /* NFS support */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 -#define CONFIG_TWL4030_LED 1 - -/* - * Board NAND Info. - */ -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Environment information */ -#define CONFIG_BOOTDELAY 10 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "usbtty=cdc_acm\0" \ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # " -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -/* Memtest from start of memory to 31MB */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) -/* The default load address is the start of memory */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) -/* everything, incl board info, in Hz */ -#undef CONFIG_SYS_CLKS_IN_HZ -/* - * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_IS_IN_NAND 1 -#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET -#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#endif /* __CONFIG_H */ -- cgit v0.10.2 From 8ad59c9a7bef49a18078888ad8eba8e87737c3b2 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Sat, 21 Dec 2013 18:03:09 +0100 Subject: ARM: tam3517-common: fix nand spl boot commit f9095aac793aa8917ab9b915c5d449e6dc8d3d30, "mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme" removed CONFIG_SPL_NAND_SOFTECC from the tam3517 common config, causing the spl nand boot to fail. Add it back, so derived boards boot again. Cc: Pekon Gupta Cc: Scott Wood Cc: Raphael Assenat Cc: Stefano Babic Cc: Tapani Utriainen Signed-off-by: Jeroen Hofstee Acked-by: Stefano Babic diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 439fc47..d44b5c0 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -224,6 +224,7 @@ #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_CONSOLE #define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ #define CONFIG_SPL_LIBCOMMON_SUPPORT -- cgit v0.10.2 From 4b9b2c300a23ca4a85811918dc92e822a9571a87 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Sat, 21 Dec 2013 18:06:33 +0100 Subject: ARM: twister: add missing gpio clock init Commit f33b9bd3984fb11e1d8566a866adc5957b1e1c9d breaks boards which do not explicitly enable the gpio clocks. This causes the twister spl to hang, since it uses the no longer enabled gpio 55. Add CONFIG_OMAP3_GPIO_2 to unbrick the board. Cc: Stefano Babic Cc: Tapani Utriainen Signed-off-by: Jeroen Hofstee Acked-by: Stefano Babic diff --git a/include/configs/twister.h b/include/configs/twister.h index b6ca59c..f24dc13 100644 --- a/include/configs/twister.h +++ b/include/configs/twister.h @@ -50,4 +50,7 @@ #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_SPL_BOARD_INIT +/* gpio 55 is used as SPL_OS_BOOT_KEY */ +#define CONFIG_OMAP3_GPIO_2 + #endif /* __CONFIG_H */ -- cgit v0.10.2 From 6f72892a4412013c4257f8475ed9d940132a202f Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Tue, 31 Dec 2013 12:55:15 +0200 Subject: arm: omap: cm_t35: enable gpio bank 5 clocks explicitly Following commit "arm: omap3: Enable clocks for peripherals only if they are used" (f33b9bd3984fb11e1d8566a866adc5957b1e1c9d) it is now necessary to enable clocks for GPIO banks explicitly. On cm_t35, GPIO bank 5 is necessary for scf0403 lcd support. Enable GPIO bank 5 clocks. Signed-off-by: Nikita Kiryanov Cc: Igor Grinberg Cc: Tom Rini Acked-by: Igor Grinberg diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 4640c43..7729a02 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -316,6 +316,7 @@ /* Display Configuration */ #define CONFIG_OMAP3_GPIO_2 +#define CONFIG_OMAP3_GPIO_5 #define CONFIG_VIDEO_OMAP3 #define LCD_BPP LCD_COLOR16 -- cgit v0.10.2 From e0a1d598ef0155f31589c42db17ff4784e84ca67 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Tue, 7 Jan 2014 19:57:38 +0530 Subject: ARM: dra7_evm: read mac address properly from e-fuse Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is not working on some boards, modifying the offset to read properly. Signed-off-by: Mugunthan V N diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9ae88c5..1b60b8f 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -202,12 +202,12 @@ int board_eth_init(bd_t *bis) /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); - mac_addr[0] = mac_hi & 0xFF; + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = mac_lo & 0xFF; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; - mac_addr[5] = (mac_lo & 0xFF0000) >> 16; + mac_addr[5] = mac_lo & 0xFF; if (!getenv("ethaddr")) { printf(" not set. Validating first E-fuse MAC\n"); -- cgit v0.10.2 From f77a606a0602be5d1fe23e8dcdfa5defde51dfd7 Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 14 Dec 2013 11:47:29 +0800 Subject: fdt_support: 64bit initrd start address support Signed-off-by: David Feng diff --git a/common/fdt_support.c b/common/fdt_support.c index 1f0d8f5..a3f7442 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -21,6 +21,34 @@ */ DECLARE_GLOBAL_DATA_PTR; +/* + * Get cells len in bytes + * if #NNNN-cells property is 2 then len is 8 + * otherwise len is 4 + */ +static int get_cells_len(void *blob, char *nr_cells_name) +{ + const fdt32_t *cell; + + cell = fdt_getprop(blob, 0, nr_cells_name, NULL); + if (cell && fdt32_to_cpu(*cell) == 2) + return 8; + + return 4; +} + +/* + * Write a 4 or 8 byte big endian cell + */ +static void write_cell(u8 *addr, u64 val, int size) +{ + int shift = (size - 1) * 8; + while (size-- > 0) { + *addr++ = (val >> shift) & 0xff; + shift -= 8; + } +} + /** * fdt_getprop_u32_default - Find a node and return it's property or a default * @@ -131,9 +159,9 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff) int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force) { - int nodeoffset; + int nodeoffset, addr_cell_len; int err, j, total; - fdt32_t tmp; + fdt64_t tmp; const char *path; uint64_t addr, size; @@ -170,9 +198,11 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force) return err; } + addr_cell_len = get_cells_len(fdt, "#address-cells"); + path = fdt_getprop(fdt, nodeoffset, "linux,initrd-start", NULL); if ((path == NULL) || force) { - tmp = cpu_to_fdt32(initrd_start); + write_cell((u8 *)&tmp, initrd_start, addr_cell_len); err = fdt_setprop(fdt, nodeoffset, "linux,initrd-start", &tmp, sizeof(tmp)); if (err < 0) { @@ -181,7 +211,7 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force) fdt_strerror(err)); return err; } - tmp = cpu_to_fdt32(initrd_end); + write_cell((u8 *)&tmp, initrd_end, addr_cell_len); err = fdt_setprop(fdt, nodeoffset, "linux,initrd-end", &tmp, sizeof(tmp)); if (err < 0) { @@ -343,34 +373,6 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat, do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create); } -/* - * Get cells len in bytes - * if #NNNN-cells property is 2 then len is 8 - * otherwise len is 4 - */ -static int get_cells_len(void *blob, char *nr_cells_name) -{ - const fdt32_t *cell; - - cell = fdt_getprop(blob, 0, nr_cells_name, NULL); - if (cell && fdt32_to_cpu(*cell) == 2) - return 8; - - return 4; -} - -/* - * Write a 4 or 8 byte big endian cell - */ -static void write_cell(u8 *addr, u64 val, int size) -{ - int shift = (size - 1) * 8; - while (size-- > 0) { - *addr++ = (val >> shift) & 0xff; - shift -= 8; - } -} - #ifdef CONFIG_NR_DRAM_BANKS #define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS #else -- cgit v0.10.2 From 5cea95cb53c7192c3ab9cb61634fa1a1f33649f4 Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 14 Dec 2013 11:47:30 +0800 Subject: cmd_pxe: remove compiling warnings Signed-off-by: David Feng diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index db6b156..c27ec35 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -59,7 +59,7 @@ static int format_mac_pxe(char *outbuf, size_t outbuf_len) uchar ethaddr[6]; if (outbuf_len < 21) { - printf("outbuf is too small (%d < 21)\n", outbuf_len); + printf("outbuf is too small (%zd < 21)\n", outbuf_len); return -EINVAL; } @@ -103,7 +103,7 @@ static int get_bootfile_path(const char *file_path, char *bootfile_path, path_len = (last_slash - bootfile) + 1; if (bootfile_path_size < path_len) { - printf("bootfile_path too small. (%d < %d)\n", + printf("bootfile_path too small. (%zd < %zd)\n", bootfile_path_size, path_len); return -1; -- cgit v0.10.2 From ec4fa56743a3534c4bace2c9c72ea36b9d41000c Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 14 Dec 2013 11:47:31 +0800 Subject: add weak entry definition Signed-off-by: David Feng diff --git a/include/linux/linkage.h b/include/linux/linkage.h index 39c712e..7435fcd 100644 --- a/include/linux/linkage.h +++ b/include/linux/linkage.h @@ -48,6 +48,10 @@ .globl SYMBOL_NAME(name); \ LENTRY(name) +#define WEAK(name) \ + .weak SYMBOL_NAME(name); \ + LENTRY(name) + #ifndef END #define END(name) \ .size name, .-name -- cgit v0.10.2 From 8137af19e75a761d4d9e3ada6820ea7824078a54 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Sat, 14 Dec 2013 11:47:32 +0800 Subject: arm64: Add tool to statically apply RELA relocations ARM64 uses the newer RELA-style relocations rather than the older REL. RELA relocations have an addend in the relocation struct, rather than expecting the loader to read a value from the location to be updated. While this is beneficial for ordinary program loading, it's problematic for U-Boot because the location to be updated starts out with zero, rather than a pre-relocation value. Since we need to be able to run C code before relocation, we need a tool to apply the relocations at build time. In theory this tool is applicable to other newer architectures (mainly 64-bit), but currently the only relocations it supports are for arm64, and it assumes a 64-bit little-endian target. If the latter limitation is ever to be changed, we'll need a way to tell the tool what format the image is in. Eventually this may be replaced by a tool that uses libelf or similar and operates directly on the ELF file. I've written some code for such an approach but libelf does not make it easy to poke addresses by memory address (rather than by section), and I was hesitant to write code to manually parse the program headers and do the update outside of libelf (or to iterate over sections) -- especially since it wouldn't get test coverage on things like binaries with multiple PT_LOAD segments. This should be good enough for now to let the manual relocation stuff be removed from the arm64 patches. Signed-off-by: Scott Wood Signed-off-by: David Feng diff --git a/Makefile b/Makefile index 0d86b55..85a9330 100644 --- a/Makefile +++ b/Makefile @@ -334,6 +334,17 @@ else BOARD_SIZE_CHECK = endif +# Statically apply RELA-style relocations (currently arm64 only) +ifneq ($(CONFIG_STATIC_RELA),) +# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base +DO_STATIC_RELA = \ + start=$$($(NM) $(1) | grep __rel_dyn_start | cut -f 1 -d ' '); \ + end=$$($(NM) $(1) | grep __rel_dyn_end | cut -f 1 -d ' '); \ + $(obj)tools/relocate-rela $(2) $(3) $$start $$end +else +DO_STATIC_RELA = +endif + # Always append ALL so that arch config.mk's can add custom ones ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map @@ -378,6 +389,7 @@ $(obj)u-boot.srec: $(obj)u-boot $(obj)u-boot.bin: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE)) $(BOARD_SIZE_CHECK) $(obj)u-boot.ldr: $(obj)u-boot diff --git a/tools/Makefile b/tools/Makefile index d4bc84d..4a7e7e5 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -60,6 +60,7 @@ BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX) BIN_FILES-y += proftool(SFX) +BIN_FILES-$(CONFIG_STATIC_RELA) += relocate-rela$(SFX) # Source files which exist outside the tools directory EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o @@ -85,6 +86,7 @@ NOPED_OBJ_FILES-y += os_support.o NOPED_OBJ_FILES-y += pblimage.o NOPED_OBJ_FILES-y += proftool.o NOPED_OBJ_FILES-y += ublimage.o +NOPED_OBJ_FILES-y += relocate-rela.o OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o @@ -251,6 +253,10 @@ $(obj)kwboot$(SFX): $(obj)kwboot.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ +$(obj)relocate-rela$(SFX): $(obj)relocate-rela.o + $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ + $(HOSTSTRIP) $@ + # Some of the tool objects need to be accessed from outside the tools directory $(obj)%.o: $(SRCTREE)/common/%.c $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c new file mode 100644 index 0000000..93b4c39 --- /dev/null +++ b/tools/relocate-rela.c @@ -0,0 +1,189 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ BSD-2-Clause + * + * 64-bit and little-endian target only until we need to support a different + * arch that needs this. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef R_AARCH64_RELATIVE +#define R_AARCH64_RELATIVE 1027 +#endif + +static const bool debug_en; + +static void debug(const char *fmt, ...) +{ + va_list args; + + va_start(args, fmt); + if (debug_en) + vprintf(fmt, args); +} + +static bool supported_rela(Elf64_Rela *rela) +{ + uint64_t mask = 0xffffffffULL; /* would be different on 32-bit */ + uint32_t type = rela->r_info & mask; + + switch (type) { +#ifdef R_AARCH64_RELATIVE + case R_AARCH64_RELATIVE: + return true; +#endif + default: + fprintf(stderr, "warning: unsupported relocation type %" + PRIu32 " at %" PRIx64 "\n", + type, rela->r_offset); + + return false; + } +} + +static inline uint64_t swap64(uint64_t val) +{ + return ((val >> 56) & 0x00000000000000ffULL) | + ((val >> 40) & 0x000000000000ff00ULL) | + ((val >> 24) & 0x0000000000ff0000ULL) | + ((val >> 8) & 0x00000000ff000000ULL) | + ((val << 8) & 0x000000ff00000000ULL) | + ((val << 24) & 0x0000ff0000000000ULL) | + ((val << 40) & 0x00ff000000000000ULL) | + ((val << 56) & 0xff00000000000000ULL); +} + +#if __BYTE_ORDER == __LITTLE_ENDIAN +static inline uint64_t be64(uint64_t val) +{ + return swap64(val); +} + +static inline uint64_t le64(uint64_t val) +{ + return val; +} +#else +static inline uint64_t le64(uint64_t val) +{ + return swap64(val); +} + +static inline uint64_t be64(uint64_t val) +{ + return val; +} +#endif + +static bool read_num(const char *str, uint64_t *num) +{ + char *endptr; + *num = strtoull(str, &endptr, 16); + return str[0] && !endptr[0]; +} + +int main(int argc, char **argv) +{ + FILE *f; + int i, num; + uint64_t rela_start, rela_end, text_base; + + if (argc != 5) { + fprintf(stderr, "Statically apply ELF rela relocations\n"); + fprintf(stderr, "Usage: %s " \ + " \n", argv[0]); + fprintf(stderr, "All numbers in hex.\n"); + return 1; + } + + f = fopen(argv[1], "r+b"); + if (!f) { + fprintf(stderr, "%s: Cannot open %s: %s\n", + argv[0], argv[1], strerror(errno)); + return 2; + } + + if (!read_num(argv[2], &text_base) || + !read_num(argv[3], &rela_start) || + !read_num(argv[4], &rela_end)) { + fprintf(stderr, "%s: bad number\n", argv[0]); + return 3; + } + + if (rela_start > rela_end || rela_start < text_base || + (rela_end - rela_start) % 24) { + fprintf(stderr, "%s: bad rela bounds\n", argv[0]); + return 3; + } + + rela_start -= text_base; + rela_end -= text_base; + + num = (rela_end - rela_start) / sizeof(Elf64_Rela); + + for (i = 0; i < num; i++) { + Elf64_Rela rela, swrela; + uint64_t pos = rela_start + sizeof(Elf64_Rela) * i; + uint64_t addr; + + if (fseek(f, pos, SEEK_SET) < 0) { + fprintf(stderr, "%s: %s: seek to %" PRIx64 + " failed: %s\n", + argv[0], argv[1], pos, strerror(errno)); + } + + if (fread(&rela, sizeof(rela), 1, f) != 1) { + fprintf(stderr, "%s: %s: read rela failed at %" + PRIx64 "\n", + argv[0], argv[1], pos); + return 4; + } + + swrela.r_offset = le64(rela.r_offset); + swrela.r_info = le64(rela.r_info); + swrela.r_addend = le64(rela.r_addend); + + if (!supported_rela(&swrela)) + continue; + + debug("Rela %" PRIx64 " %" PRIu64 " %" PRIx64 "\n", + swrela.r_offset, swrela.r_info, swrela.r_addend); + + if (swrela.r_offset < text_base) { + fprintf(stderr, "%s: %s: bad rela at %" PRIx64 "\n", + argv[0], argv[1], pos); + return 4; + } + + addr = swrela.r_offset - text_base; + + if (fseek(f, addr, SEEK_SET) < 0) { + fprintf(stderr, "%s: %s: seek to %" + PRIx64 " failed: %s\n", + argv[0], argv[1], addr, strerror(errno)); + } + + if (fwrite(&rela.r_addend, sizeof(rela.r_addend), 1, f) != 1) { + fprintf(stderr, "%s: %s: write failed at %" PRIx64 "\n", + argv[0], argv[1], addr); + return 4; + } + } + + if (fclose(f) < 0) { + fprintf(stderr, "%s: %s: close failed: %s\n", + argv[0], argv[1], strerror(errno)); + return 4; + } + + return 0; +} -- cgit v0.10.2 From f4dc714aaa2d86b84724ec01fb848da63aa63666 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Sat, 14 Dec 2013 11:47:33 +0800 Subject: arm64: Turn u-boot.bin back into an ELF file after relocate-rela While performing relocations on u-boot.bin should be good enough for booting on real hardware, some simulators insist on booting an ELF file (and yet don't perform ELF relocations), so convert the relocated binary back into an ELF file. This can go away in the future if we change relocate-rela to operate directly on the ELF file, or if and when we stop caring about a simulator with this restriction. Signed-off-by: Scott Wood Signed-off-by: David Feng diff --git a/Makefile b/Makefile index 85a9330..a4c2928 100644 --- a/Makefile +++ b/Makefile @@ -358,6 +358,7 @@ ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin ifneq ($(CONFIG_SPL_TARGET),) ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET)) endif +ALL-$(CONFIG_REMAKE_ELF) += $(obj)u-boot.elf # enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) @@ -528,6 +529,18 @@ $(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img conv=notrunc 2>/dev/null cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@ +# Create a new ELF from a raw binary file. This is useful for arm64 +# where static relocation needs to be performed on the raw binary, +# but certain simulators only accept an ELF file (but don't do the +# relocation). +# FIXME refactor dts/Makefile to share target/arch detection +$(obj)u-boot.elf: $(obj)u-boot.bin + @$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \ + $< $(obj)u-boot-elf.o + @$(LD) $(obj)u-boot-elf.o -o $@ \ + --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \ + -Ttext=$(CONFIG_SYS_TEXT_BASE) + ifeq ($(CONFIG_SANDBOX),y) GEN_UBOOT = \ cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \ -- cgit v0.10.2 From 54799e4596bf8af33fd4a8dee153be7011c06d8d Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Sat, 14 Dec 2013 11:47:34 +0800 Subject: arm64: Make checkarmreloc accept arm64 relocations Signed-off-by: Scott Wood Signed-off-by: David Feng diff --git a/Makefile b/Makefile index a4c2928..dc5ba04 100644 --- a/Makefile +++ b/Makefile @@ -744,12 +744,16 @@ tools: $(VERSION_FILE) $(TIMESTAMP_FILE) $(MAKE) -C $@ all endif # config.mk -# ARM relocations should all be R_ARM_RELATIVE. +# ARM relocations should all be R_ARM_RELATIVE (32-bit) or +# R_AARCH64_RELATIVE (64-bit). checkarmreloc: $(obj)u-boot - @if test "R_ARM_RELATIVE" != \ - "`$(CROSS_COMPILE)readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \ - then echo "$< contains relocations other than \ - R_ARM_RELATIVE"; false; fi + @RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \ + grep R_A | sort -u`"; \ + if test "$$RELOC" != "R_ARM_RELATIVE" -a \ + "$$RELOC" != "R_AARCH64_RELATIVE"; then \ + echo "$< contains unexpected relocations: $$RELOC"; \ + false; \ + fi $(VERSION_FILE): @mkdir -p $(dir $(VERSION_FILE)) -- cgit v0.10.2 From 0ae7653128c80a4f2920cbe9b124792c2fd9d9e0 Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 14 Dec 2013 11:47:35 +0800 Subject: arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood Signed-off-by: David Feng diff --git a/arch/arm/config.mk b/arch/arm/config.mk index fd3e5fb..329c7a7 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -17,7 +17,8 @@ endif LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \ - -fno-common -ffixed-r9 -msoft-float + -fno-common -ffixed-r9 +PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) # Support generic board on ARM __HAVE_ARCH_GENERIC_BOARD := y @@ -105,4 +106,8 @@ PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations) endif # limit ourselves to the sections we want in the .bin. +ifdef CONFIG_ARM64 +OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn +else OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn +endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile new file mode 100644 index 0000000..b6eb6de --- /dev/null +++ b/arch/arm/cpu/armv8/Makefile @@ -0,0 +1,17 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y := start.o + +obj-y += cpu.o +obj-y += generic_timer.o +obj-y += cache_v8.o +obj-y += exceptions.o +obj-y += cache.o +obj-y += tlb.o +obj-y += gic.o +obj-y += transition.o diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S new file mode 100644 index 0000000..546a83e --- /dev/null +++ b/arch/arm/cpu/armv8/cache.S @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * This file is based on sample code from ARMv8 ARM. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * void __asm_flush_dcache_level(level) + * + * clean and invalidate one level cache. + * + * x0: cache level + * x1~x9: clobbered + */ +ENTRY(__asm_flush_dcache_level) + lsl x1, x0, #1 + msr csselr_el1, x1 /* select cache level */ + isb /* sync change of cssidr_el1 */ + mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ + and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ + add x2, x2, #4 /* x2 <- log2(cache line size) */ + mov x3, #0x3ff + and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ + add w4, w3, w3 + sub w4, w4, 1 /* round up log2(#ways + 1) */ + clz w5, w4 /* bit position of #ways */ + mov x4, #0x7fff + and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ + /* x1 <- cache level << 1 */ + /* x2 <- line length offset */ + /* x3 <- number of cache ways - 1 */ + /* x4 <- number of cache sets - 1 */ + /* x5 <- bit position of #ways */ + +loop_set: + mov x6, x3 /* x6 <- working copy of #ways */ +loop_way: + lsl x7, x6, x5 + orr x9, x1, x7 /* map way and level to cisw value */ + lsl x7, x4, x2 + orr x9, x9, x7 /* map set number to cisw value */ + dc cisw, x9 /* clean & invalidate by set/way */ + subs x6, x6, #1 /* decrement the way */ + b.ge loop_way + subs x4, x4, #1 /* decrement the set */ + b.ge loop_set + + ret +ENDPROC(__asm_flush_dcache_level) + +/* + * void __asm_flush_dcache_all(void) + * + * clean and invalidate all data cache by SET/WAY. + */ +ENTRY(__asm_flush_dcache_all) + dsb sy + mrs x10, clidr_el1 /* read clidr_el1 */ + lsr x11, x10, #24 + and x11, x11, #0x7 /* x11 <- loc */ + cbz x11, finished /* if loc is 0, exit */ + mov x15, lr + mov x0, #0 /* start flush at cache level 0 */ + /* x0 <- cache level */ + /* x10 <- clidr_el1 */ + /* x11 <- loc */ + /* x15 <- return address */ + +loop_level: + lsl x1, x0, #1 + add x1, x1, x0 /* x0 <- tripled cache level */ + lsr x1, x10, x1 + and x1, x1, #7 /* x1 <- cache type */ + cmp x1, #2 + b.lt skip /* skip if no cache or icache */ + bl __asm_flush_dcache_level +skip: + add x0, x0, #1 /* increment cache level */ + cmp x11, x0 + b.gt loop_level + + mov x0, #0 + msr csselr_el1, x0 /* resotre csselr_el1 */ + dsb sy + isb + mov lr, x15 + +finished: + ret +ENDPROC(__asm_flush_dcache_all) + +/* + * void __asm_flush_dcache_range(start, end) + * + * clean & invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +ENTRY(__asm_flush_dcache_range) + mrs x3, ctr_el0 + lsr x3, x3, #16 + and x3, x3, #0xf + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc civac, x0 /* clean & invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret +ENDPROC(__asm_flush_dcache_range) + +/* + * void __asm_invalidate_icache_all(void) + * + * invalidate all tlb entries. + */ +ENTRY(__asm_invalidate_icache_all) + ic ialluis + isb sy + ret +ENDPROC(__asm_invalidate_icache_all) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c new file mode 100644 index 0000000..131fdab --- /dev/null +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -0,0 +1,219 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DCACHE_OFF + +static void set_pgtable_section(u64 section, u64 memory_type) +{ + u64 *page_table = (u64 *)gd->arch.tlb_addr; + u64 value; + + value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF; + value |= PMD_ATTRINDX(memory_type); + page_table[section] = value; +} + +/* to activate the MMU we need to set up virtual memory */ +static void mmu_setup(void) +{ + int i, j, el; + bd_t *bd = gd->bd; + + /* Setup an identity-mapping for all spaces */ + for (i = 0; i < (PGTABLE_SIZE >> 3); i++) + set_pgtable_section(i, MT_DEVICE_NGNRNE); + + /* Setup an identity-mapping for all RAM space */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + ulong start = bd->bi_dram[i].start; + ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size; + for (j = start >> SECTION_SHIFT; + j < end >> SECTION_SHIFT; j++) { + set_pgtable_section(j, MT_NORMAL); + } + } + + /* load TTBR0 */ + el = current_el(); + if (el == 1) + asm volatile("msr ttbr0_el1, %0" + : : "r" (gd->arch.tlb_addr) : "memory"); + else if (el == 2) + asm volatile("msr ttbr0_el2, %0" + : : "r" (gd->arch.tlb_addr) : "memory"); + else + asm volatile("msr ttbr0_el3, %0" + : : "r" (gd->arch.tlb_addr) : "memory"); + + /* enable the mmu */ + set_sctlr(get_sctlr() | CR_M); +} + +/* + * Performs a invalidation of the entire data cache at all levels + */ +void invalidate_dcache_all(void) +{ + __asm_flush_dcache_all(); +} + +/* + * Performs a clean & invalidation of the entire data cache at all levels + */ +void flush_dcache_all(void) +{ + __asm_flush_dcache_all(); +} + +/* + * Invalidates range in all levels of D-cache/unified cache + */ +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + __asm_flush_dcache_range(start, stop); +} + +/* + * Flush range(clean & invalidate) from all levels of D-cache/unified cache + */ +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + __asm_flush_dcache_range(start, stop); +} + +void dcache_enable(void) +{ + /* The data cache is not active unless the mmu is enabled */ + if (!(get_sctlr() & CR_M)) { + invalidate_dcache_all(); + __asm_invalidate_tlb_all(); + mmu_setup(); + } + + set_sctlr(get_sctlr() | CR_C); +} + +void dcache_disable(void) +{ + uint32_t sctlr; + + sctlr = get_sctlr(); + + /* if cache isn't enabled no need to disable */ + if (!(sctlr & CR_C)) + return; + + set_sctlr(sctlr & ~(CR_C|CR_M)); + + flush_dcache_all(); + __asm_invalidate_tlb_all(); +} + +int dcache_status(void) +{ + return (get_sctlr() & CR_C) != 0; +} + +#else /* CONFIG_SYS_DCACHE_OFF */ + +void invalidate_dcache_all(void) +{ +} + +void flush_dcache_all(void) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void dcache_enable(void) +{ +} + +void dcache_disable(void) +{ +} + +int dcache_status(void) +{ + return 0; +} + +#endif /* CONFIG_SYS_DCACHE_OFF */ + +#ifndef CONFIG_SYS_ICACHE_OFF + +void icache_enable(void) +{ + set_sctlr(get_sctlr() | CR_I); +} + +void icache_disable(void) +{ + set_sctlr(get_sctlr() & ~CR_I); +} + +int icache_status(void) +{ + return (get_sctlr() & CR_I) != 0; +} + +void invalidate_icache_all(void) +{ + __asm_invalidate_icache_all(); +} + +#else /* CONFIG_SYS_ICACHE_OFF */ + +void icache_enable(void) +{ +} + +void icache_disable(void) +{ +} + +int icache_status(void) +{ + return 0; +} + +void invalidate_icache_all(void) +{ +} + +#endif /* CONFIG_SYS_ICACHE_OFF */ + +/* + * Enable dCache & iCache, whether cache is actually enabled + * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF + */ +void enable_caches(void) +{ + icache_enable(); + dcache_enable(); +} + +/* + * Flush range from all levels of d-cache/unified-cache + */ +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk new file mode 100644 index 0000000..027a68c --- /dev/null +++ b/arch/arm/cpu/armv8/config.mk @@ -0,0 +1,15 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# SPDX-License-Identifier: GPL-2.0+ +# +PLATFORM_RELFLAGS += -fno-common -ffixed-x18 + +# SEE README.arm-unaligned-accesses +PF_NO_UNALIGNED := $(call cc-option, -mstrict-align) +PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED) + +PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a) +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8) +PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED) diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c new file mode 100644 index 0000000..e06c3cc --- /dev/null +++ b/arch/arm/cpu/armv8/cpu.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +int cleanup_before_linux(void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * disable interrupt and turn off caches etc ... + */ + disable_interrupts(); + + /* + * Turn off I-cache and invalidate it + */ + icache_disable(); + invalidate_icache_all(); + + /* + * turn off D-cache + * dcache_disable() in turn flushes the d-cache and disables MMU + */ + dcache_disable(); + invalidate_dcache_all(); + + return 0; +} diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S new file mode 100644 index 0000000..b91a1b6 --- /dev/null +++ b/arch/arm/cpu/armv8/exceptions.S @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* + * Enter Exception. + * This will save the processor state that is ELR/X0~X30 + * to the stack frame. + */ +.macro exception_entry + stp x29, x30, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + stp x17, x18, [sp, #-16]! + stp x15, x16, [sp, #-16]! + stp x13, x14, [sp, #-16]! + stp x11, x12, [sp, #-16]! + stp x9, x10, [sp, #-16]! + stp x7, x8, [sp, #-16]! + stp x5, x6, [sp, #-16]! + stp x3, x4, [sp, #-16]! + stp x1, x2, [sp, #-16]! + + /* Could be running at EL3/EL2/EL1 */ + switch_el x11, 3f, 2f, 1f +3: mrs x1, esr_el3 + mrs x2, elr_el3 + b 0f +2: mrs x1, esr_el2 + mrs x2, elr_el2 + b 0f +1: mrs x1, esr_el1 + mrs x2, elr_el1 +0: + stp x2, x0, [sp, #-16]! + mov x0, sp +.endm + +/* + * Exception vectors. + */ + .align 11 + .globl vectors +vectors: + .align 7 + b _do_bad_sync /* Current EL Synchronous Thread */ + + .align 7 + b _do_bad_irq /* Current EL IRQ Thread */ + + .align 7 + b _do_bad_fiq /* Current EL FIQ Thread */ + + .align 7 + b _do_bad_error /* Current EL Error Thread */ + + .align 7 + b _do_sync /* Current EL Synchronous Handler */ + + .align 7 + b _do_irq /* Current EL IRQ Handler */ + + .align 7 + b _do_fiq /* Current EL FIQ Handler */ + + .align 7 + b _do_error /* Current EL Error Handler */ + + +_do_bad_sync: + exception_entry + bl do_bad_sync + +_do_bad_irq: + exception_entry + bl do_bad_irq + +_do_bad_fiq: + exception_entry + bl do_bad_fiq + +_do_bad_error: + exception_entry + bl do_bad_error + +_do_sync: + exception_entry + bl do_sync + +_do_irq: + exception_entry + bl do_irq + +_do_fiq: + exception_entry + bl do_fiq + +_do_error: + exception_entry + bl do_error diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c new file mode 100644 index 0000000..223b95e --- /dev/null +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * Generic timer implementation of get_tbclk() + */ +unsigned long get_tbclk(void) +{ + unsigned long cntfrq; + asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq)); + return cntfrq; +} + +/* + * Generic timer implementation of timer_read_counter() + */ +unsigned long timer_read_counter(void) +{ + unsigned long cntpct; + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); + return cntpct; +} diff --git a/arch/arm/cpu/armv8/gic.S b/arch/arm/cpu/armv8/gic.S new file mode 100644 index 0000000..599aa8f --- /dev/null +++ b/arch/arm/cpu/armv8/gic.S @@ -0,0 +1,106 @@ +/* + * GIC Initialization Routines. + * + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + + +/************************************************************************* + * + * void gic_init(void) __attribute__((weak)); + * + * Currently, this routine only initialize secure copy of GIC + * with Security Extensions at EL3. + * + *************************************************************************/ +WEAK(gic_init) + branch_if_slave x0, 2f + + /* Initialize Distributor and SPIs */ + ldr x1, =GICD_BASE + mov w0, #0x3 /* EnableGrp0 | EnableGrp1 */ + str w0, [x1, GICD_CTLR] /* Secure GICD_CTLR */ + ldr w0, [x1, GICD_TYPER] + and w2, w0, #0x1f /* ITLinesNumber */ + cbz w2, 2f /* No SPIs */ + add x1, x1, (GICD_IGROUPRn + 4) + mov w0, #~0 /* Config SPIs as Grp1 */ +1: str w0, [x1], #0x4 + sub w2, w2, #0x1 + cbnz w2, 1b + + /* Initialize SGIs and PPIs */ +2: ldr x1, =GICD_BASE + mov w0, #~0 /* Config SGIs and PPIs as Grp1 */ + str w0, [x1, GICD_IGROUPRn] /* GICD_IGROUPR0 */ + mov w0, #0x1 /* Enable SGI 0 */ + str w0, [x1, GICD_ISENABLERn] + + /* Initialize Cpu Interface */ + ldr x1, =GICC_BASE + mov w0, #0x1e7 /* Disable IRQ/FIQ Bypass & */ + /* Enable Ack Group1 Interrupt & */ + /* EnableGrp0 & EnableGrp1 */ + str w0, [x1, GICC_CTLR] /* Secure GICC_CTLR */ + + mov w0, #0x1 << 7 /* Non-Secure access to GICC_PMR */ + str w0, [x1, GICC_PMR] + + ret +ENDPROC(gic_init) + + +/************************************************************************* + * + * void gic_send_sgi(u64 sgi) __attribute__((weak)); + * + *************************************************************************/ +WEAK(gic_send_sgi) + ldr x1, =GICD_BASE + mov w2, #0x8000 + movk w2, #0x100, lsl #16 + orr w2, w2, w0 + str w2, [x1, GICD_SGIR] + ret +ENDPROC(gic_send_sgi) + + +/************************************************************************* + * + * void wait_for_wakeup(void) __attribute__((weak)); + * + * Wait for SGI 0 from master. + * + *************************************************************************/ +WEAK(wait_for_wakeup) + ldr x1, =GICC_BASE +0: wfi + ldr w0, [x1, GICC_AIAR] + str w0, [x1, GICC_AEOIR] + cbnz w0, 0b + ret +ENDPROC(wait_for_wakeup) + + +/************************************************************************* + * + * void smp_kick_all_cpus(void) __attribute__((weak)); + * + *************************************************************************/ +WEAK(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ + mov x0, xzr /* SGI 0 */ + mov x29, lr /* Save LR */ + bl gic_send_sgi + mov lr, x29 /* Restore LR */ + ret +ENDPROC(smp_kick_all_cpus) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S new file mode 100644 index 0000000..bcc2603 --- /dev/null +++ b/arch/arm/cpu/armv8/start.S @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/************************************************************************* + * + * Startup Code (reset vector) + * + *************************************************************************/ + +.globl _start +_start: + b reset + + .align 3 + +.globl _TEXT_BASE +_TEXT_BASE: + .quad CONFIG_SYS_TEXT_BASE + +/* + * These are defined in the linker script. + */ +.globl _end_ofs +_end_ofs: + .quad _end - _start + +.globl _bss_start_ofs +_bss_start_ofs: + .quad __bss_start - _start + +.globl _bss_end_ofs +_bss_end_ofs: + .quad __bss_end - _start + +reset: + /* + * Could be EL3/EL2/EL1, Initial State: + * Little Endian, MMU Disabled, i/dCache Disabled + */ + adr x0, vectors + switch_el x1, 3f, 2f, 1f +3: msr vbar_el3, x0 + msr cptr_el3, xzr /* Enable FP/SIMD */ + ldr x0, =COUNTER_FREQUENCY + msr cntfrq_el0, x0 /* Initialize CNTFRQ */ + b 0f +2: msr vbar_el2, x0 + mov x0, #0x33ff + msr cptr_el2, x0 /* Enable FP/SIMD */ + b 0f +1: msr vbar_el1, x0 + mov x0, #3 << 20 + msr cpacr_el1, x0 /* Enable FP/SIMD */ +0: + + /* Cache/BPB/TLB Invalidate */ + bl __asm_flush_dcache_all /* dCache clean&invalidate */ + bl __asm_invalidate_icache_all /* iCache invalidate */ + bl __asm_invalidate_tlb_all /* invalidate TLBs */ + + /* Processor specific initialization */ + bl lowlevel_init + + branch_if_master x0, x1, master_cpu + + /* + * Slave CPUs + */ +slave_cpu: + wfe + ldr x1, =CPU_RELEASE_ADDR + ldr x0, [x1] + cbz x0, slave_cpu + br x0 /* branch to the given address */ + + /* + * Master CPU + */ +master_cpu: + bl _main + +/*-----------------------------------------------------------------------*/ + +WEAK(lowlevel_init) + /* Initialize GIC Secure Bank Status */ + mov x29, lr /* Save LR */ + bl gic_init + + branch_if_master x0, x1, 1f + + /* + * Slave should wait for master clearing spin table. + * This sync prevent salves observing incorrect + * value of spin table and jumping to wrong place. + */ + bl wait_for_wakeup + + /* + * All processors will enter EL2 and optionally EL1. + */ + bl armv8_switch_to_el2 +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + bl armv8_switch_to_el1 +#endif + +1: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) + +/*-----------------------------------------------------------------------*/ + +ENTRY(c_runtime_cpu_setup) + /* If I-cache is enabled invalidate it */ +#ifndef CONFIG_SYS_ICACHE_OFF + ic iallu /* I+BTB cache invalidate */ + isb sy +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF + /* + * Setup MAIR and TCR. + */ + ldr x0, =MEMORY_ATTRIBUTES + ldr x1, =TCR_FLAGS + + switch_el x2, 3f, 2f, 1f +3: orr x1, x1, TCR_EL3_IPS_BITS + msr mair_el3, x0 + msr tcr_el3, x1 + b 0f +2: orr x1, x1, TCR_EL2_IPS_BITS + msr mair_el2, x0 + msr tcr_el2, x1 + b 0f +1: orr x1, x1, TCR_EL1_IPS_BITS + msr mair_el1, x0 + msr tcr_el1, x1 +0: +#endif + + /* Relocate vBAR */ + adr x0, vectors + switch_el x1, 3f, 2f, 1f +3: msr vbar_el3, x0 + b 0f +2: msr vbar_el2, x0 + b 0f +1: msr vbar_el1, x0 +0: + + ret +ENDPROC(c_runtime_cpu_setup) diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S new file mode 100644 index 0000000..f840b04 --- /dev/null +++ b/arch/arm/cpu/armv8/tlb.S @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * void __asm_invalidate_tlb_all(void) + * + * invalidate all tlb entries. + */ +ENTRY(__asm_invalidate_tlb_all) + switch_el x9, 3f, 2f, 1f +3: tlbi alle3 + dsb sy + isb + b 0f +2: tlbi alle2 + dsb sy + isb + b 0f +1: tlbi vmalle1 + dsb sy + isb +0: + ret +ENDPROC(__asm_invalidate_tlb_all) diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S new file mode 100644 index 0000000..e0a5946 --- /dev/null +++ b/arch/arm/cpu/armv8/transition.S @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +ENTRY(armv8_switch_to_el2) + switch_el x0, 1f, 0f, 0f +0: ret +1: + mov x0, #0x5b1 /* Non-secure EL0/EL1 | HVC | 64bit EL2 */ + msr scr_el3, x0 + msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */ + mov x0, #0x33ff + msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */ + + /* Initialize SCTLR_EL2 */ + msr sctlr_el2, xzr + + /* Return to the EL2_SP2 mode from EL3 */ + mov x0, sp + msr sp_el2, x0 /* Migrate SP */ + mrs x0, vbar_el3 + msr vbar_el2, x0 /* Migrate VBAR */ + mov x0, #0x3c9 + msr spsr_el3, x0 /* EL2_SP2 | D | A | I | F */ + msr elr_el3, lr + eret +ENDPROC(armv8_switch_to_el2) + +ENTRY(armv8_switch_to_el1) + switch_el x0, 0f, 1f, 0f +0: ret +1: + /* Initialize Generic Timers */ + mrs x0, cnthctl_el2 + orr x0, x0, #0x3 /* Enable EL1 access to timers */ + msr cnthctl_el2, x0 + msr cntvoff_el2, x0 + mrs x0, cntkctl_el1 + orr x0, x0, #0x3 /* Enable EL0 access to timers */ + msr cntkctl_el1, x0 + + /* Initilize MPID/MPIDR registers */ + mrs x0, midr_el1 + mrs x1, mpidr_el1 + msr vpidr_el2, x0 + msr vmpidr_el2, x1 + + /* Disable coprocessor traps */ + mov x0, #0x33ff + msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */ + msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */ + mov x0, #3 << 20 + msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */ + + /* Initialize HCR_EL2 */ + mov x0, #(1 << 31) /* 64bit EL1 */ + orr x0, x0, #(1 << 29) /* Disable HVC */ + msr hcr_el2, x0 + + /* SCTLR_EL1 initialization */ + mov x0, #0x0800 + movk x0, #0x30d0, lsl #16 + msr sctlr_el1, x0 + + /* Return to the EL1_SP1 mode from EL2 */ + mov x0, sp + msr sp_el1, x0 /* Migrate SP */ + mrs x0, vbar_el2 + msr vbar_el1, x0 /* Migrate VBAR */ + mov x0, #0x3c5 + msr spsr_el2, x0 /* EL1_SP1 | D | A | I | F */ + msr elr_el2, lr + eret +ENDPROC(armv8_switch_to_el1) diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds new file mode 100644 index 0000000..4c12222 --- /dev/null +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(8); + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(8); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(8); + .data : { + *(.data*) + } + + . = ALIGN(8); + + . = .; + + . = ALIGN(8); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(8); + + .image_copy_end : + { + *(.__image_copy_end) + } + + . = ALIGN(8); + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rela.dyn : { + *(.rela*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + + . = ALIGN(8); + + .bss_start : { + KEEP(*(.__bss_start)); + } + + .bss : { + *(.bss*) + . = ALIGN(8); + } + + .bss_end : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h new file mode 100644 index 0000000..1193e76 --- /dev/null +++ b/arch/arm/include/asm/armv8/mmu.h @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_MMU_H_ +#define _ASM_ARMV8_MMU_H_ + +#ifdef __ASSEMBLY__ +#define _AC(X, Y) X +#else +#define _AC(X, Y) (X##Y) +#endif + +#define UL(x) _AC(x, UL) + +/***************************************************************/ +/* + * The following definitions are related each other, shoud be + * calculated specifically. + */ +#define VA_BITS (42) /* 42 bits virtual address */ + +/* PAGE_SHIFT determines the page size */ +#undef PAGE_SIZE +#define PAGE_SHIFT 16 +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +/* + * section address mask and size definitions. + */ +#define SECTION_SHIFT 29 +#define SECTION_SIZE (UL(1) << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) +/***************************************************************/ + +/* + * Memory types + */ +#define MT_DEVICE_NGNRNE 0 +#define MT_DEVICE_NGNRE 1 +#define MT_DEVICE_GRE 2 +#define MT_NORMAL_NC 3 +#define MT_NORMAL 4 + +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \ + (0x04 << (MT_DEVICE_NGNRE*8)) | \ + (0x0c << (MT_DEVICE_GRE*8)) | \ + (0x44 << (MT_NORMAL_NC*8)) | \ + (UL(0xff) << (MT_NORMAL*8))) + +/* + * Hardware page table definitions. + * + * Level 2 descriptor (PMD). + */ +#define PMD_TYPE_MASK (3 << 0) +#define PMD_TYPE_FAULT (0 << 0) +#define PMD_TYPE_TABLE (3 << 0) +#define PMD_TYPE_SECT (1 << 0) + +/* + * Section + */ +#define PMD_SECT_S (3 << 8) +#define PMD_SECT_AF (1 << 10) +#define PMD_SECT_NG (1 << 11) +#define PMD_SECT_PXN (UL(1) << 53) +#define PMD_SECT_UXN (UL(1) << 54) + +/* + * AttrIndx[2:0] + */ +#define PMD_ATTRINDX(t) ((t) << 2) +#define PMD_ATTRINDX_MASK (7 << 2) + +/* + * TCR flags. + */ +#define TCR_T0SZ(x) ((64 - (x)) << 0) +#define TCR_IRGN_NC (0 << 8) +#define TCR_IRGN_WBWA (1 << 8) +#define TCR_IRGN_WT (2 << 8) +#define TCR_IRGN_WBNWA (3 << 8) +#define TCR_IRGN_MASK (3 << 8) +#define TCR_ORGN_NC (0 << 10) +#define TCR_ORGN_WBWA (1 << 10) +#define TCR_ORGN_WT (2 << 10) +#define TCR_ORGN_WBNWA (3 << 10) +#define TCR_ORGN_MASK (3 << 10) +#define TCR_SHARED_NON (0 << 12) +#define TCR_SHARED_OUTER (1 << 12) +#define TCR_SHARED_INNER (2 << 12) +#define TCR_TG0_4K (0 << 14) +#define TCR_TG0_64K (1 << 14) +#define TCR_TG0_16K (2 << 14) +#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ +#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ +#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ + +/* PTWs cacheable, inner/outer WBWA and non-shareable */ +#define TCR_FLAGS (TCR_TG0_64K | \ + TCR_SHARED_NON | \ + TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | \ + TCR_T0SZ(VA_BITS)) + +#endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h index c3489f1..71a9966 100644 --- a/arch/arm/include/asm/byteorder.h +++ b/arch/arm/include/asm/byteorder.h @@ -23,10 +23,22 @@ # define __SWAB_64_THRU_32__ #endif +#ifdef CONFIG_ARM64 + +#ifdef __AARCH64EB__ +#include +#else +#include +#endif + +#else /* CONFIG_ARM64 */ + #ifdef __ARMEB__ #include #else #include #endif +#endif /* CONFIG_ARM64 */ + #endif diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 6d60a4a..ddebbc8 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -11,6 +11,8 @@ #include +#ifndef CONFIG_ARM64 + /* * Invalidate L2 Cache using co-proc instruction */ @@ -28,6 +30,9 @@ void l2_cache_disable(void); void set_section_dcache(int section, enum dcache_option option); void dram_bank_mmu_setup(int bank); + +#endif + /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 99b703e..abf79e5 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -9,4 +9,10 @@ #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH + +#ifdef CONFIG_ARM64 +#define CONFIG_PHYS_64BIT +#define CONFIG_STATIC_RELA +#endif + #endif diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h index a0891cc..ac2b2bf 100644 --- a/arch/arm/include/asm/gic.h +++ b/arch/arm/include/asm/gic.h @@ -1,19 +1,54 @@ -#ifndef __GIC_V2_H__ -#define __GIC_V2_H__ +#ifndef __GIC_H__ +#define __GIC_H__ -/* register offsets for the ARM generic interrupt controller (GIC) */ +/* Register offsets for the ARM generic interrupt controller (GIC) */ #define GIC_DIST_OFFSET 0x1000 +#define GIC_CPU_OFFSET_A9 0x0100 +#define GIC_CPU_OFFSET_A15 0x2000 + +/* Distributor Registers */ #define GICD_CTLR 0x0000 #define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_STATUSR 0x0010 +#define GICD_SETSPI_NSR 0x0040 +#define GICD_CLRSPI_NSR 0x0048 +#define GICD_SETSPI_SR 0x0050 +#define GICD_CLRSPI_SR 0x0058 +#define GICD_SEIR 0x0068 #define GICD_IGROUPRn 0x0080 -#define GICD_SGIR 0x0F00 +#define GICD_ISENABLERn 0x0100 +#define GICD_ICENABLERn 0x0180 +#define GICD_ISPENDRn 0x0200 +#define GICD_ICPENDRn 0x0280 +#define GICD_ISACTIVERn 0x0300 +#define GICD_ICACTIVERn 0x0380 +#define GICD_IPRIORITYRn 0x0400 +#define GICD_ITARGETSRn 0x0800 +#define GICD_ICFGR 0x0c00 +#define GICD_IGROUPMODRn 0x0d00 +#define GICD_NSACRn 0x0e00 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGIRn 0x0f10 +#define GICD_SPENDSGIRn 0x0f20 +#define GICD_IROUTERn 0x6000 -#define GIC_CPU_OFFSET_A9 0x0100 -#define GIC_CPU_OFFSET_A15 0x2000 +/* Cpu Interface Memory Mapped Registers */ #define GICC_CTLR 0x0000 #define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 #define GICC_IAR 0x000C #define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APRn 0x00d0 +#define GICC_NSAPRn 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 -#endif +#endif /* __GIC_H__ */ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index e126436..60e8726 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -47,6 +47,10 @@ struct arch_global_data { #include -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") +#ifdef CONFIG_ARM64 +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") +#else +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") +#endif #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 1fbc531..6a1f05a 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -75,42 +75,45 @@ static inline phys_addr_t virt_to_phys(void * vaddr) #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) -extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen) +extern inline void __raw_writesb(unsigned long addr, const void *data, + int bytelen) { uint8_t *buf = (uint8_t *)data; while(bytelen--) __arch_putb(*buf++, addr); } -extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen) +extern inline void __raw_writesw(unsigned long addr, const void *data, + int wordlen) { uint16_t *buf = (uint16_t *)data; while(wordlen--) __arch_putw(*buf++, addr); } -extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen) +extern inline void __raw_writesl(unsigned long addr, const void *data, + int longlen) { uint32_t *buf = (uint32_t *)data; while(longlen--) __arch_putl(*buf++, addr); } -extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen) +extern inline void __raw_readsb(unsigned long addr, void *data, int bytelen) { uint8_t *buf = (uint8_t *)data; while(bytelen--) *buf++ = __arch_getb(addr); } -extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen) +extern inline void __raw_readsw(unsigned long addr, void *data, int wordlen) { uint16_t *buf = (uint16_t *)data; while(wordlen--) *buf++ = __arch_getw(addr); } -extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) +extern inline void __raw_readsl(unsigned long addr, void *data, int longlen) { uint32_t *buf = (uint32_t *)data; while(longlen--) diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index ff13f36..f77e4b8 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -54,5 +54,58 @@ bcs 1b .endm +#ifdef CONFIG_ARM64 +/* + * Register aliases. + */ +lr .req x30 + +/* + * Branch according to exception level + */ +.macro switch_el, xreg, el3_label, el2_label, el1_label + mrs \xreg, CurrentEL + cmp \xreg, 0xc + b.eq \el3_label + cmp \xreg, 0x8 + b.eq \el2_label + cmp \xreg, 0x4 + b.eq \el1_label +.endm + +/* + * Branch if current processor is a slave, + * choose processor with all zero affinity value as the master. + */ +.macro branch_if_slave, xreg, slave_label + mrs \xreg, mpidr_el1 + tst \xreg, #0xff /* Test Affinity 0 */ + b.ne \slave_label + lsr \xreg, \xreg, #8 + tst \xreg, #0xff /* Test Affinity 1 */ + b.ne \slave_label + lsr \xreg, \xreg, #8 + tst \xreg, #0xff /* Test Affinity 2 */ + b.ne \slave_label + lsr \xreg, \xreg, #16 + tst \xreg, #0xff /* Test Affinity 3 */ + b.ne \slave_label +.endm + +/* + * Branch if current processor is a master, + * choose processor with all zero affinity value as the master. + */ +.macro branch_if_master, xreg1, xreg2, master_label + mrs \xreg1, mpidr_el1 + lsr \xreg2, \xreg1, #32 + lsl \xreg1, \xreg1, #40 + lsr \xreg1, \xreg1, #40 + orr \xreg1, \xreg1, \xreg2 + cbz \xreg1, \master_label +.endm + +#endif /* CONFIG_ARM64 */ + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_MACRO_H__ */ diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h index c412486..9ba9add 100644 --- a/arch/arm/include/asm/posix_types.h +++ b/arch/arm/include/asm/posix_types.h @@ -13,6 +13,8 @@ #ifndef __ARCH_ARM_POSIX_TYPES_H #define __ARCH_ARM_POSIX_TYPES_H +#include + /* * This file is generally used by user-level software, so you need to * be a little careful about namespace pollution etc. Also, we cannot @@ -28,9 +30,17 @@ typedef int __kernel_pid_t; typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; + +#ifdef CONFIG_ARM64 +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#else /* CONFIG_ARM64 */ typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; typedef int __kernel_ptrdiff_t; +#endif /* CONFIG_ARM64 */ + typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index a060ee6..21aef58 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -10,6 +10,25 @@ #ifndef __ASM_PROC_PTRACE_H #define __ASM_PROC_PTRACE_H +#ifdef CONFIG_ARM64 + +#define PCMASK 0 + +#ifndef __ASSEMBLY__ + +/* + * This struct defines the way the registers are stored + * on the stack during an exception. + */ +struct pt_regs { + unsigned long elr; + unsigned long regs[31]; +}; + +#endif /* __ASSEMBLY__ */ + +#else /* CONFIG_ARM64 */ + #define USR26_MODE 0x00 #define FIQ26_MODE 0x01 #define IRQ26_MODE 0x02 @@ -104,4 +123,6 @@ static inline int valid_user_regs(struct pt_regs *regs) #endif /* __ASSEMBLY__ */ +#endif /* CONFIG_ARM64 */ + #endif diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h index cda8976..693d1f4 100644 --- a/arch/arm/include/asm/proc-armv/system.h +++ b/arch/arm/include/asm/proc-armv/system.h @@ -13,6 +13,60 @@ /* * Save the current interrupt enable state & disable IRQs */ +#ifdef CONFIG_ARM64 + +/* + * Save the current interrupt enable state + * and disable IRQs/FIQs + */ +#define local_irq_save(flags) \ + ({ \ + asm volatile( \ + "mrs %0, daif" \ + "msr daifset, #3" \ + : "=r" (flags) \ + : \ + : "memory"); \ + }) + +/* + * restore saved IRQ & FIQ state + */ +#define local_irq_restore(flags) \ + ({ \ + asm volatile( \ + "msr daif, %0" \ + : \ + : "r" (flags) \ + : "memory"); \ + }) + +/* + * Enable IRQs/FIQs + */ +#define local_irq_enable() \ + ({ \ + asm volatile( \ + "msr daifclr, #3" \ + : \ + : \ + : "memory"); \ + }) + +/* + * Disable IRQs/FIQs + */ +#define local_irq_disable() \ + ({ \ + asm volatile( \ + "msr daifset, #3" \ + : \ + : \ + : "memory"); \ + }) + +#else /* CONFIG_ARM64 */ + #define local_irq_save(x) \ ({ \ unsigned long temp; \ @@ -107,7 +161,10 @@ : "r" (x) \ : "memory") -#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) +#endif /* CONFIG_ARM64 */ + +#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \ + defined(CONFIG_ARM64) /* * On the StrongARM, "swp" is terminally broken since it bypasses the * cache totally. This means that the cache becomes inconsistent, and, diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 760345f..4178f8c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -1,6 +1,86 @@ #ifndef __ASM_ARM_SYSTEM_H #define __ASM_ARM_SYSTEM_H +#ifdef CONFIG_ARM64 + +/* + * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_WXN (1 << 19) /* Write Permision Imply XN */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ + +#define PGTABLE_SIZE (0x10000) + +#ifndef __ASSEMBLY__ + +#define isb() \ + ({asm volatile( \ + "isb" : : : "memory"); \ + }) + +#define wfi() \ + ({asm volatile( \ + "wfi" : : : "memory"); \ + }) + +static inline unsigned int current_el(void) +{ + unsigned int el; + asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); + return el >> 2; +} + +static inline unsigned int get_sctlr(void) +{ + unsigned int el, val; + + el = current_el(); + if (el == 1) + asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); + else if (el == 2) + asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); + else + asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); + + return val; +} + +static inline void set_sctlr(unsigned int val) +{ + unsigned int el; + + el = current_el(); + if (el == 1) + asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); + else if (el == 2) + asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); + else + asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); + + asm volatile("isb"); +} + +void __asm_flush_dcache_all(void); +void __asm_flush_dcache_range(u64 start, u64 end); +void __asm_invalidate_tlb_all(void); +void __asm_invalidate_icache_all(void); + +void armv8_switch_to_el2(void); +void armv8_switch_to_el1(void); +void gic_init(void); +void gic_send_sgi(unsigned long sgino); +void wait_for_wakeup(void); +void smp_kick_all_cpus(void); + +#endif /* __ASSEMBLY__ */ + +#else /* CONFIG_ARM64 */ + #ifdef __KERNEL__ #define CPU_ARCH_UNKNOWN 0 @@ -45,6 +125,8 @@ #define CR_AFE (1 << 29) /* Access flag enable */ #define CR_TE (1 << 30) /* Thumb exception enable */ +#define PGTABLE_SIZE (4096 * 4) + /* * This is used to ensure the compiler did actually allocate the register we * asked it for some inline assembly sequences. Apparently we can't trust @@ -132,4 +214,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop); #endif /* __KERNEL__ */ +#endif /* CONFIG_ARM64 */ + #endif diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index 71dc049..2326420 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -39,7 +39,11 @@ typedef unsigned int u32; typedef signed long long s64; typedef unsigned long long u64; +#ifdef CONFIG_ARM64 +#define BITS_PER_LONG 64 +#else /* CONFIG_ARM64 */ #define BITS_PER_LONG 32 +#endif /* CONFIG_ARM64 */ /* Dma addresses are 32-bits wide. */ diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index 2b5fce8..cb81232 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -44,6 +44,10 @@ typedef struct bd_info { #endif /* !CONFIG_SYS_GENERIC_BOARD */ /* For image.h:image_check_target_arch() */ +#ifndef CONFIG_ARM64 #define IH_ARCH_DEFAULT IH_ARCH_ARM +#else +#define IH_ARCH_DEFAULT IH_ARCH_ARM64 +#endif #endif /* _U_BOOT_H_ */ diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h index 44593a8..0a228fb 100644 --- a/arch/arm/include/asm/unaligned.h +++ b/arch/arm/include/asm/unaligned.h @@ -8,7 +8,7 @@ /* * Select endianness */ -#ifndef __ARMEB__ +#if __BYTE_ORDER == __LITTLE_ENDIAN #define get_unaligned __get_unaligned_le #define put_unaligned __put_unaligned_le #else diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 679f19a..321997c 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -17,14 +17,22 @@ lib-y += _umodsi3.o lib-y += div0.o endif -obj-y += crt0.o +ifdef CONFIG_ARM64 +obj-y += crt0_64.o +else +obj-y += crt0.o +endif ifndef CONFIG_SPL_BUILD -obj-y += relocate.o +ifdef CONFIG_ARM64 +obj-y += relocate_64.o +else +obj-y += relocate.o +endif ifndef CONFIG_SYS_GENERIC_BOARD obj-y += board.o endif -obj-y += sections.o +obj-y += sections.o obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTM) += bootm.o @@ -35,11 +43,17 @@ else obj-$(CONFIG_SPL_FRAMEWORK) += spl.o endif +ifdef CONFIG_ARM64 +obj-y += interrupts_64.o +else obj-y += interrupts.o +endif obj-y += reset.o obj-y += cache.o +ifndef CONFIG_ARM64 obj-y += cache-cp15.o +endif # For EABI conformant tool chains, provide eabi_compat() ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 9c72a53..b770e25 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -344,7 +344,7 @@ void board_init_f(ulong bootflag) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* reserve TLB table */ - gd->arch.tlb_size = 4096 * 4; + gd->arch.tlb_size = PGTABLE_SIZE; addr -= gd->arch.tlb_size; /* round down to next 64 kB limit */ @@ -419,6 +419,7 @@ void board_init_f(ulong bootflag) } #endif +#ifndef CONFIG_ARM64 /* setup stackpointer for exeptions */ gd->irq_sp = addr_sp; #ifdef CONFIG_USE_IRQ @@ -431,6 +432,10 @@ void board_init_f(ulong bootflag) /* 8-byte alignment for ABI compliance */ addr_sp &= ~0x07; +#else /* CONFIG_ARM64 */ + /* 16-byte alignment for ABI compliance */ + addr_sp &= ~0x0f; +#endif /* CONFIG_ARM64 */ #else addr_sp += 128; /* leave 32 words for abort-stack */ gd->irq_sp = addr_sp; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index f476a89..77f1a5c 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -196,6 +196,14 @@ static void do_nonsec_virt_switch(void) debug("entered non-secure state\n"); #endif #endif + +#ifdef CONFIG_ARM64 + smp_kick_all_cpus(); + armv8_switch_to_el2(); +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + armv8_switch_to_el1(); +#endif +#endif } /* Subcommand: PREP */ @@ -240,6 +248,21 @@ static void boot_prep_linux(bootm_headers_t *images) /* Subcommand: GO */ static void boot_jump_linux(bootm_headers_t *images, int flag) { +#ifdef CONFIG_ARM64 + void (*kernel_entry)(void *fdt_addr); + int fake = (flag & BOOTM_STATE_OS_FAKE_GO); + + kernel_entry = (void (*)(void *fdt_addr))images->ep; + + debug("## Transferring control to Linux (at address %lx)...\n", + (ulong) kernel_entry); + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + announce_and_cleanup(fake); + + if (!fake) + kernel_entry(images->ft_addr); +#else unsigned long machid = gd->bd->bi_arch_number; char *s; void (*kernel_entry)(int zero, int arch, uint params); @@ -266,6 +289,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) if (!fake) kernel_entry(0, machid, r2); +#endif } /* Main Entry point for arm bootm implementation diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S new file mode 100644 index 0000000..7756396 --- /dev/null +++ b/arch/arm/lib/crt0_64.S @@ -0,0 +1,113 @@ +/* + * crt0 - C-runtime startup Code for AArch64 U-Boot + * + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2012 + * Albert ARIBAUD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* + * This file handles the target-independent stages of the U-Boot + * start-up where a C runtime environment is needed. Its entry point + * is _main and is branched into from the target's start.S file. + * + * _main execution sequence is: + * + * 1. Set up initial environment for calling board_init_f(). + * This environment only provides a stack and a place to store + * the GD ('global data') structure, both located in some readily + * available RAM (SRAM, locked cache...). In this context, VARIABLE + * global data, initialized or not (BSS), are UNAVAILABLE; only + * CONSTANT initialized data are available. + * + * 2. Call board_init_f(). This function prepares the hardware for + * execution from system RAM (DRAM, DDR...) As system RAM may not + * be available yet, , board_init_f() must use the current GD to + * store any data which must be passed on to later stages. These + * data include the relocation destination, the future stack, and + * the future GD location. + * + * (the following applies only to non-SPL builds) + * + * 3. Set up intermediate environment where the stack and GD are the + * ones allocated by board_init_f() in system RAM, but BSS and + * initialized non-const data are still not available. + * + * 4. Call relocate_code(). This function relocates U-Boot from its + * current location into the relocation destination computed by + * board_init_f(). + * + * 5. Set up final environment for calling board_init_r(). This + * environment has BSS (initialized to 0), initialized non-const + * data (initialized to their intended value), and stack in system + * RAM. GD has retained values set by board_init_f(). Some CPUs + * have some work left to do at this point regarding memory, so + * call c_runtime_cpu_setup. + * + * 6. Branch to board_init_r(). + */ + +ENTRY(_main) + +/* + * Set up initial C runtime environment and call board_init_f(0). + */ + ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) + sub x0, x0, #GD_SIZE /* allocate one GD above SP */ + bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ + mov x18, sp /* GD is above SP */ + mov x0, #0 + bl board_init_f + +/* + * Set up intermediate environment (new sp and gd) and call + * relocate_code(addr_moni). Trick here is that we'll return + * 'here' but relocated. + */ + ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */ + bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ + ldr x18, [x18, #GD_BD] /* x18 <- gd->bd */ + sub x18, x18, #GD_SIZE /* new GD is below bd */ + + adr lr, relocation_return + ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */ + add lr, lr, x9 /* new return address after relocation */ + ldr x0, [x18, #GD_RELOCADDR] /* x0 <- gd->relocaddr */ + b relocate_code + +relocation_return: + +/* + * Set up final (full) environment + */ + bl c_runtime_cpu_setup /* still call old routine */ + +/* + * Clear BSS section + */ + ldr x0, =__bss_start /* this is auto-relocated! */ + ldr x1, =__bss_end /* this is auto-relocated! */ + mov x2, #0 +clear_loop: + str x2, [x0] + add x0, x0, #8 + cmp x0, x1 + b.lo clear_loop + + /* call board_init_r(gd_t *id, ulong dest_addr) */ + mov x0, x18 /* gd_t */ + ldr x1, [x18, #GD_RELOCADDR] /* dest_addr */ + b board_init_r /* PC relative jump */ + + /* NOTREACHED - board_init_r() does not return */ + +ENDPROC(_main) diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c new file mode 100644 index 0000000..b476722 --- /dev/null +++ b/arch/arm/lib/interrupts_64.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + + +int interrupt_init(void) +{ + return 0; +} + +void enable_interrupts(void) +{ + return; +} + +int disable_interrupts(void) +{ + return 0; +} + +void show_regs(struct pt_regs *regs) +{ + int i; + + printf("ELR: %lx\n", regs->elr); + printf("LR: %lx\n", regs->regs[30]); + for (i = 0; i < 29; i += 2) + printf("x%-2d: %016lx x%-2d: %016lx\n", + i, regs->regs[i], i+1, regs->regs[i+1]); + printf("\n"); +} + +/* + * do_bad_sync handles the impossible case in the Synchronous Abort vector. + */ +void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_bad_irq handles the impossible case in the Irq vector. + */ +void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_bad_fiq handles the impossible case in the Fiq vector. + */ +void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_bad_error handles the impossible case in the Error vector. + */ +void do_bad_error(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_sync handles the Synchronous Abort exception. + */ +void do_sync(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_irq handles the Irq exception. + */ +void do_irq(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("\"Irq\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_fiq handles the Fiq exception. + */ +void do_fiq(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("\"Fiq\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} + +/* + * do_error handles the Error exception. + * Errors are more likely to be processor specific, + * it is defined with weak attribute and can be redefined + * in processor specific code. + */ +void __weak do_error(struct pt_regs *pt_regs, unsigned int esr) +{ + printf("\"Error\" handler, esr 0x%08x\n", esr); + show_regs(pt_regs); + panic("Resetting CPU ...\n"); +} diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S new file mode 100644 index 0000000..7fba9e2 --- /dev/null +++ b/arch/arm/lib/relocate_64.S @@ -0,0 +1,58 @@ +/* + * relocate - common relocation function for AArch64 U-Boot + * + * (C) Copyright 2013 + * Albert ARIBAUD + * David Feng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * void relocate_code (addr_moni) + * + * This function relocates the monitor code. + * x0 holds the destination address. + */ +ENTRY(relocate_code) + /* + * Copy u-boot from flash to RAM + */ + ldr x1, =__image_copy_start /* x1 <- SRC &__image_copy_start */ + subs x9, x0, x1 /* x9 <- relocation offset */ + b.eq relocate_done /* skip relocation */ + ldr x2, =__image_copy_end /* x2 <- SRC &__image_copy_end */ + +copy_loop: + ldp x10, x11, [x1], #16 /* copy from source address [x1] */ + stp x10, x11, [x0], #16 /* copy to target address [x0] */ + cmp x1, x2 /* until source end address [x2] */ + b.lo copy_loop + + /* + * Fix .rela.dyn relocations + */ + ldr x2, =__rel_dyn_start /* x2 <- SRC &__rel_dyn_start */ + ldr x3, =__rel_dyn_end /* x3 <- SRC &__rel_dyn_end */ +fixloop: + ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */ + ldr x4, [x2], #8 /* x4 <- addend */ + and x1, x1, #0xffffffff + cmp x1, #1027 /* relative fixup? */ + bne fixnext + + /* relative fix: store addend plus offset at dest location */ + add x0, x0, x9 + add x4, x4, x9 + str x4, [x0] +fixnext: + cmp x2, x3 + b.lo fixloop + +relocate_done: + ret +ENDPROC(relocate_code) diff --git a/common/image.c b/common/image.c index b0ae58f..4145354 100644 --- a/common/image.c +++ b/common/image.c @@ -81,6 +81,7 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_NDS32, "nds32", "NDS32", }, { IH_ARCH_OPENRISC, "or1k", "OpenRISC 1000",}, { IH_ARCH_SANDBOX, "sandbox", "Sandbox", }, + { IH_ARCH_ARM64, "arm64", "AArch64", }, { -1, "", "", }, }; diff --git a/doc/README.arm64 b/doc/README.arm64 new file mode 100644 index 0000000..75586db --- /dev/null +++ b/doc/README.arm64 @@ -0,0 +1,46 @@ +U-boot for arm64 + +Summary +======= +No hardware platform of arm64 is available now. The u-boot is +simulated on Foundation Model and Fast Model for ARMv8. + +Notes +===== + +1. Currenly, u-boot run at the highest exception level processor + supported and jump to EL2 or optionally EL1 before enter OS. + +2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc + use rela relocation format, a tool(tools/relocate-rela) by Scott Wood + is used to encode the initial addend of rela to u-boot.bin. After running, + the u-boot will be relocated to destination again. + +3. Fdt should be placed at a 2-megabyte boundary and within the first 512 + megabytes from the start of the kernel image. So, fdt_high should be + defined specially. + Please reference linux/Documentation/arm64/booting.txt for detail. + +4. Spin-table is used to wake up secondary processors. One location + (or per processor location) is defined to hold the kernel entry point + for secondary processors. It must be ensured that the location is + accessible and zero immediately after secondary processor + enter slave_cpu branch execution in start.S. The location address + is encoded in cpu node of DTS. Linux kernel store the entry point + of secondary processors to it and send event to wakeup secondary + processors. + Please reference linux/Documentation/arm64/booting.txt for detail. + +5. Generic board is supported. + +6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and + aarch32 specific codes. + +Contributor +=========== + Tom Rini + Scott Wood + York Sun + Simon Glass + Sharma Bhupesh + Rob Herring diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 5d2ab56..32a19ce 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -39,6 +39,20 @@ gd_t *global_data; " bctr\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r11"); #elif defined(CONFIG_ARM) +#ifdef CONFIG_ARM64 +/* + * x18 holds the pointer to the global_data, x9 is a call-clobbered + * register + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" ldr x9, [x18, %0]\n" \ +" ldr x9, [x9, %1]\n" \ +" br x9\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "x9"); +#else /* * r9 holds the pointer to the global_data, ip is a call-clobbered * register @@ -50,6 +64,7 @@ gd_t *global_data; " ldr ip, [r9, %0]\n" \ " ldr pc, [ip, %1]\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "ip"); +#endif #elif defined(CONFIG_MIPS) /* * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call- diff --git a/include/image.h b/include/image.h index ee6eb8d..7de2bb2 100644 --- a/include/image.h +++ b/include/image.h @@ -156,6 +156,7 @@ struct lmb; #define IH_ARCH_SANDBOX 19 /* Sandbox architecture (test only) */ #define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */ #define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */ +#define IH_ARCH_ARM64 22 /* ARM64 */ /* * Image Types -- cgit v0.10.2 From cce6be7f081edc19ecc3f0ff0f811e5300be2de6 Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 14 Dec 2013 11:47:36 +0800 Subject: arm64: generic board support Signed-off-by: David Feng diff --git a/common/board_f.c b/common/board_f.c index f0664bc..d918e4b 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -462,7 +462,7 @@ static int reserve_round_4k(void) static int reserve_mmu(void) { /* reserve TLB table */ - gd->arch.tlb_size = 4096 * 4; + gd->arch.tlb_size = PGTABLE_SIZE; gd->relocaddr -= gd->arch.tlb_size; /* round down to next 64 kB limit */ @@ -614,7 +614,7 @@ static int reserve_stacks(void) * TODO(sjg@chromium.org): Perhaps create arch_reserve_stack() * to handle this and put in arch/xxx/lib/stack.c */ -# ifdef CONFIG_ARM +# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64) # ifdef CONFIG_USE_IRQ gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", @@ -811,11 +811,6 @@ static int mark_bootstage(void) } static init_fnc_t init_sequence_f[] = { -#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ - !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ - !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86) - zero_global_data, -#endif #ifdef CONFIG_SANDBOX setup_ram_buf, #endif @@ -1009,6 +1004,17 @@ void board_init_f(ulong boot_flags) gd = &data; #endif + /* + * Clear global data before it is accessed at debug print + * in initcall_run_list. Otherwise the debug print probably + * get the wrong vaule of gd->have_console. + */ +#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ + !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ + !defined(CONFIG_MPC86xx) && !defined(CONFIG_X86) + zero_global_data(); +#endif + gd->flags = boot_flags; if (initcall_run_list(init_sequence_f)) -- cgit v0.10.2 From 129168290a9a21afb4cbb899cdc25580cbe5921c Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 14 Dec 2013 11:47:37 +0800 Subject: arm64: board support of vexpress_aemv8a Signed-off-by: David Feng Signed-off-by: Bhupesh Sharma diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile new file mode 100644 index 0000000..e009141 --- /dev/null +++ b/board/armltd/vexpress64/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := vexpress64.o diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c new file mode 100644 index 0000000..2ec3bc9 --- /dev/null +++ b/board/armltd/vexpress64/vexpress64.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2013 + * David Feng + * Sharma Bhupesh + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + /* + * Clear spin table so that secondary processors + * observe the correct value after waken up from wfe. + */ + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +int timer_init(void) +{ + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +/* + * Board specific ethernet initialization routine. + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} diff --git a/boards.cfg b/boards.cfg index ba88c1d..e168590 100644 --- a/boards.cfg +++ b/boards.cfg @@ -397,6 +397,7 @@ Active arm pxa - - vpac270 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich Active arm pxa - toradex - colibri_pxa270 - Marek Vasut Active arm sa1100 - - - jornada - Kristoffer Ericson +Active arm armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h new file mode 100644 index 0000000..ce5f384 --- /dev/null +++ b/include/configs/vexpress_aemv8a.h @@ -0,0 +1,189 @@ +/* + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __VEXPRESS_AEMV8A_H +#define __VEXPRESS_AEMV8A_H + +#define DEBUG + +#define CONFIG_REMAKE_ELF + +/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ + +/*#define CONFIG_SYS_GENERIC_BOARD*/ + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SUPPORT_RAW_INITRD + +/* Cache Definitions */ +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF + +#define CONFIG_IDENT_STRING " vexpress_aemv8a" +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" + +/* Link Definitions */ +#define CONFIG_SYS_TEXT_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +#define CONFIG_DEFAULT_DEVICE_TREE vexpress64 + +/* SMP Spin Table Definitions */ +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* CS register bases for the original memory map. */ +#define V2M_PA_CS0 0x00000000 +#define V2M_PA_CS1 0x14000000 +#define V2M_PA_CS2 0x18000000 +#define V2M_PA_CS3 0x1c000000 +#define V2M_PA_CS4 0x0c000000 +#define V2M_PA_CS5 0x10000000 + +#define V2M_PERIPH_OFFSET(x) (x << 16) +#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) +#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) +#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) + +#define V2M_BASE 0x80000000 + +/* + * Physical addresses, offset from V2M_PA_CS0-3 + */ +#define V2M_NOR0 (V2M_PA_CS0) +#define V2M_NOR1 (V2M_PA_CS4) +#define V2M_SRAM (V2M_PA_CS1) + +/* Common peripherals relative to CS7. */ +#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) +#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) +#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) +#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) + +#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) +#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) +#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) +#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) + +#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) + +#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) +#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) + +#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) +#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) + +#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) + +#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) + +/* System register offsets. */ +#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) +#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) +#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0x2C001000) +#define GICC_BASE (0x2C002000) + +#define CONFIG_SYS_MEMTEST_START V2M_BASE +#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/* SMSC9115 Ethernet from SMSC9118 family */ +#define CONFIG_SMC9111 1 +#define CONFIG_SMC9111_BASE (0x1a000000) + +/* PL011 Serial Configuration */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_CONS_INDEX 0 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_SERIAL0 V2M_UART0 +#define CONFIG_SYS_SERIAL1 V2M_UART1 + +/* Command line configuration */ +#define CONFIG_MENU +/*#define CONFIG_MENU_SHOW*/ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PXE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2048 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=0x200000\0" \ + "initrd_addr=0xa00000\0" \ + "initrd_size=0x2000000\0" \ + "fdt_addr=0x100000\0" \ + "fdt_high=0xa0000000\0" + +#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0" +#define CONFIG_BOOTCOMMAND "bootm $kernel_addr " \ + "$initrd_addr:$initrd_size $fdt_addr" +#define CONFIG_BOOTDELAY -1 + +/* Do not preserve environment */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "VExpress64# " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#endif /* __VEXPRESS_AEMV8A_H */ -- cgit v0.10.2 From 2475e634758577baad4a54f4585c7fa9a638ae73 Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 14 Dec 2013 11:47:38 +0800 Subject: arm64: MAKEALL, filter armv8 boards from LIST_arm Signed-off-by: David Feng diff --git a/MAKEALL b/MAKEALL index a74f0fc..562071a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -381,6 +381,12 @@ LIST_ARM11="$(targets_by_cpu arm1136) \ LIST_ARMV7="$(targets_by_cpu armv7)" ######################################################################### +## ARMV8 Systems +######################################################################### + +LIST_ARMV8="$(targets_by_cpu armv8)" + +######################################################################### ## AT91 Systems ######################################################################### @@ -404,7 +410,11 @@ LIST_spear="$(targets_by_soc spear)" ## ARM groups ######################################################################### -LIST_arm="$(targets_by_arch arm)" +LIST_arm="$(targets_by_arch arm | \ + for ARMV8_TARGET in $LIST_ARMV8; \ + do sed "/$ARMV8_TARGET/d"; \ + done) \ +" ######################################################################### ## MIPS Systems (default = big endian) -- cgit v0.10.2 From 795611e6ffb7d95c2a4529f365953bead0ccd13f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 9 Jan 2014 15:11:27 -0500 Subject: armv8: Use __aarch64__ rather than CONFIG_ARM64 in some cases The toolchain sets __aarch64__ for both LE and BE. In the case of posix_types.h we cannot reliably use config.h as that will lead to problems. In the case of byteorder.h it's clearer to check the EB flag being set in either case instead. Cc: David Feng Signed-off-by: Tom Rini Amended by Albert ARIBAUD to actually remove the config.h include from the posix_types.h files, with permission from Tom Rini. diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h index 71a9966..20cce76 100644 --- a/arch/arm/include/asm/byteorder.h +++ b/arch/arm/include/asm/byteorder.h @@ -23,22 +23,10 @@ # define __SWAB_64_THRU_32__ #endif -#ifdef CONFIG_ARM64 - -#ifdef __AARCH64EB__ -#include -#else -#include -#endif - -#else /* CONFIG_ARM64 */ - -#ifdef __ARMEB__ +#if defined(__ARMEB__) || defined(__AARCH64EB__) #include #else #include #endif -#endif /* CONFIG_ARM64 */ - #endif diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h index 9ba9add..d254b95 100644 --- a/arch/arm/include/asm/posix_types.h +++ b/arch/arm/include/asm/posix_types.h @@ -13,8 +13,6 @@ #ifndef __ARCH_ARM_POSIX_TYPES_H #define __ARCH_ARM_POSIX_TYPES_H -#include - /* * This file is generally used by user-level software, so you need to * be a little careful about namespace pollution etc. Also, we cannot @@ -31,15 +29,15 @@ typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; -#ifdef CONFIG_ARM64 +#ifdef __aarch64__ typedef unsigned long __kernel_size_t; typedef long __kernel_ssize_t; typedef long __kernel_ptrdiff_t; -#else /* CONFIG_ARM64 */ +#else typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; typedef int __kernel_ptrdiff_t; -#endif /* CONFIG_ARM64 */ +#endif typedef long __kernel_time_t; typedef long __kernel_suseconds_t; -- cgit v0.10.2 From 400a9488d0f9eaaf513b8ac438a7adf216acd91a Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 10 Jan 2014 10:19:45 +0100 Subject: arm: make 'MAKEALL -a' distinguish between arm and aarch64 The vexpress_aemv8a is the first aarch64 board in U-Boot. As it was introduced, it gets built when "MAKEALL -a arm" is invoked, and fails as this command is run with a 32-bit, not 64-bit, toolchain as the cross-compiler. Introduce 'aarch64' as a valid 'MAKEALL -a' argument, treated as 'arm' for all other intents, and change the architecture of the vexpress_aemv8a entry in boards.cfg from 'arm' to 'aarch64'. diff --git a/boards.cfg b/boards.cfg index e168590..029553d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -397,7 +397,7 @@ Active arm pxa - - vpac270 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich Active arm pxa - toradex - colibri_pxa270 - Marek Vasut Active arm sa1100 - - - jornada - Kristoffer Ericson -Active arm armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng +Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen @@ -1242,4 +1242,3 @@ Orphan powerpc mpc8xx - - genietv Orphan powerpc mpc8xx - - mbx8xx MBX - - Orphan powerpc mpc8xx - - mbx8xx MBX860T - - Orphan powerpc mpc8xx - - nx823 NX823 - - - diff --git a/mkconfig b/mkconfig index 40db991..b96c81f 100755 --- a/mkconfig +++ b/mkconfig @@ -85,6 +85,13 @@ if [ "${ARCH}" -a "${ARCH}" != "${arch}" ]; then exit 1 fi +# +# Test above needed aarch64, now we need arm +# +if [ "${arch}" = "aarch64" ]; then + arch="arm" +fi + if [ "$options" ] ; then echo "Configuring for ${BOARD_NAME} - Board: ${CONFIG_NAME}, Options: ${options}" else -- cgit v0.10.2 From 773590ebaf602e7df20715f41b1d58d3c489d48c Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:02 +0530 Subject: zynq: Enable CONFIG_FIT_VERBOSE Enabled fit_format_{error,warning}() Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 82ec826..6019c4a 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -127,6 +127,7 @@ /* OF */ #define CONFIG_FIT +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_OF_LIBFDT /* Commands */ -- cgit v0.10.2 From 09ed635bcc794110840c4e8661a6e272ffe779bb Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:03 +0530 Subject: zynq: Enable Boot FreeBSD/vxWorks This enabled Boot FreeBSD/vxWorks from an ELF image support Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 6019c4a..0492818 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -130,6 +130,13 @@ #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_OF_LIBFDT +/* Boot FreeBSD/vxWorks from an ELF image */ +#if defined(CONFIG_ZYNQ_BOOT_FREEBSD) +# define CONFIG_API +# define CONFIG_CMD_ELF +# define CONFIG_SYS_MMC_MAX_DEVICE 1 +#endif + /* Commands */ #include -- cgit v0.10.2 From 36e0e197349259d18d366f4bf3820f8212dd0cc2 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:04 +0530 Subject: zynq: Cleanup on miscellaneous configs Cleanup on miscellaneous configurable options: - Rename SYS_PROMPT as "zynq-uboot" - Add comment - Re-order configs Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 0492818..e34024d 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -111,19 +111,20 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "zynq-uboot> " +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LOAD_ADDR 0 -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* OF */ #define CONFIG_FIT -- cgit v0.10.2 From 7cd04192fc4e616b150240b396e1f5ae959cfe1c Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:05 +0530 Subject: zynq: Cleanup on memory configs Cleanup on memory configuration options: - Add comment - Re-order configs Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq.h b/include/configs/zynq.h index e34024d..8be52df 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -13,14 +13,6 @@ /* CPU clock */ #define CONFIG_CPU_FREQ_HZ 800000000 -/* Ram */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_TEXT_BASE 0 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) - /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} @@ -105,11 +97,6 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_MALLOC_LEN 0x400000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "zynq-uboot> " @@ -125,7 +112,21 @@ #define CONFIG_SYS_LOAD_ADDR 0 +/* Physical Memory map */ +#define CONFIG_SYS_TEXT_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) + +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) /* OF */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ -- cgit v0.10.2 From 53e49f746ce16c8f51063522542270a31c136e66 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:06 +0530 Subject: zynq: Minor config cleanup Cleanups mostly on: - Add comments - Re-order configs - Remove #define CONFIG_ZYNQ_SDHCI Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 8be52df..c8ab06f 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -7,33 +7,51 @@ #ifndef __CONFIG_ZYNQ_H #define __CONFIG_ZYNQ_H -#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ +/* High Level configuration Options */ +#define CONFIG_ARMV7 #define CONFIG_ZYNQ /* CPU clock */ -#define CONFIG_CPU_FREQ_HZ 800000000 +#ifndef CONFIG_CPU_FREQ_HZ +# define CONFIG_CPU_FREQ_HZ 800000000 +#endif +/* Serial drivers */ +#define CONFIG_BAUDRATE 115200 /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -#define CONFIG_BAUDRATE 115200 - -/* XPSS Serial driver */ +/* Zynq Serial driver */ #define CONFIG_ZYNQ_SERIAL #define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 #define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE #define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +/* DCC driver */ +#if defined(CONFIG_ZYNQ_DCC) +# define CONFIG_ARM_DCC +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#endif + /* Ethernet driver */ #define CONFIG_NET_MULTI #define CONFIG_ZYNQ_GEM #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 -#define CONFIG_ZYNQ_SDHCI -#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_SPI +/* SPI */ +#ifdef CONFIG_ZYNQ_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_SST +# define CONFIG_CMD_SF +#endif + +/* NOR */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ZYNQ_SDHCI0 /* MMC */ #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) # define CONFIG_MMC @@ -48,7 +66,6 @@ #endif #define CONFIG_ZYNQ_I2C0 - /* I2C */ #if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) # define CONFIG_CMD_I2C @@ -58,26 +75,6 @@ # define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 #endif -#if defined(CONFIG_ZYNQ_DCC) -# define CONFIG_ARM_DCC -# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ -#endif - -#define CONFIG_ZYNQ_SPI - -/* SPI */ -#ifdef CONFIG_ZYNQ_SPI -# define CONFIG_SPI_FLASH -# define CONFIG_SPI_FLASH_SST -# define CONFIG_CMD_SF -#endif - -/* Enable the PL to be downloaded */ -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_ZYNQPL -#define CONFIG_CMD_FPGA - #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY @@ -91,12 +88,9 @@ #define CONFIG_PHY_MARVELL /* Environment */ +#define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_SYS_MALLOC_LEN 0x400000 +#define CONFIG_SYS_LOAD_ADDR 0 /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "zynq-uboot> " @@ -110,8 +104,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LOAD_ADDR 0 - /* Physical Memory map */ #define CONFIG_SYS_TEXT_BASE 0 @@ -122,15 +114,25 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) +#define CONFIG_SYS_MALLOC_LEN 0x400000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -/* OF */ + +/* Enable the PL to be downloaded */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_ZYNQPL +#define CONFIG_CMD_FPGA + +/* Open Firmware flat tree */ +#define CONFIG_OF_LIBFDT + +/* FIT support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ -#define CONFIG_OF_LIBFDT /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) -- cgit v0.10.2 From 8cfac504427306f3050ce81f9f7bea09fbe9d76a Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:07 +0530 Subject: zynq: Enable cache options - Enable cache command - Turn-off L2 cache - Turn-on D-cache Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq.h b/include/configs/zynq.h index c8ab06f..6e545e5 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -16,6 +16,16 @@ # define CONFIG_CPU_FREQ_HZ 800000000 #endif +/* Cache options */ +#define CONFIG_CMD_CACHE +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +# define CONFIG_SYS_L2_PL310 +# define CONFIG_SYS_PL310_BASE 0xf8f02000 +#endif + /* Serial drivers */ #define CONFIG_BAUDRATE 115200 /* The following table includes the supported baudrates */ -- cgit v0.10.2 From 625d7637513a41045e47b7ccd36185f0e4c1df26 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:08 +0530 Subject: zynq: Add UART0, UART1 configs support Zynq uart controller support two serial ports like CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1 enabled both so-that the respective board will define these macros based on their usage. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 6e545e5..f104558 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -33,10 +33,22 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /* Zynq Serial driver */ -#define CONFIG_ZYNQ_SERIAL -#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 -#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE -#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +#define CONFIG_ZYNQ_SERIAL_UART1 +#ifdef CONFIG_ZYNQ_SERIAL_UART0 +# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000 +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE +# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +#endif + +#ifdef CONFIG_ZYNQ_SERIAL_UART1 +# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000 +# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE +# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 +#endif + +#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) +# define CONFIG_ZYNQ_SERIAL +#endif /* DCC driver */ #if defined(CONFIG_ZYNQ_DCC) -- cgit v0.10.2 From 88fcfb1ce72d063a867fcc391f18b3d551a5ccac Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:09 +0530 Subject: zynq: Add GEM0, GEM1 configs support Zynq ethernet controller support two GEM's like CONFIG_ZYNQ_GEM0 and CONFIG_ZYNQ_GEM1 enabled both so-that the respective board will define these macros based on their usage. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq.h b/include/configs/zynq.h index f104558..ea25159 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -57,10 +57,16 @@ #endif /* Ethernet driver */ -#define CONFIG_NET_MULTI -#define CONFIG_ZYNQ_GEM #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 +#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) +# define CONFIG_NET_MULTI +# define CONFIG_ZYNQ_GEM +# define CONFIG_MII +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_PHYLIB +# define CONFIG_PHY_MARVELL +#endif #define CONFIG_ZYNQ_SPI /* SPI */ @@ -103,12 +109,6 @@ #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_MAY_FAIL -/* MII and Phylib */ -#define CONFIG_MII -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_PHYLIB -#define CONFIG_PHY_MARVELL - /* Environment */ #define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ #define CONFIG_ENV_IS_NOWHERE -- cgit v0.10.2 From 06fe8daeb5a8c255555b09e1660682560c23df8d Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:10 +0530 Subject: zynq-common: Rename zynq with zynq-common zynq.h -> zynq-common.h, zynq-common is Common configuration options for all Zynq boards. zynq.h is no longer exists hense removed from boards.cfg Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/boards.cfg b/boards.cfg index 029553d..9e85fe0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -357,8 +357,6 @@ Active arm armv7 socfpga altera socfpga Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang -Active arm armv7 zynq xilinx zynq zynq - Michal Simek -Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h new file mode 100644 index 0000000..9fe06e8 --- /dev/null +++ b/include/configs/zynq-common.h @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2012 Michal Simek + * (C) Copyright 2013 Xilinx, Inc. + * + * Common configuration options for all Zynq boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_COMMON_H +#define __CONFIG_ZYNQ_COMMON_H + +/* High Level configuration Options */ +#define CONFIG_ARMV7 +#define CONFIG_ZYNQ + +/* CPU clock */ +#ifndef CONFIG_CPU_FREQ_HZ +# define CONFIG_CPU_FREQ_HZ 800000000 +#endif + +/* Cache options */ +#define CONFIG_CMD_CACHE +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +# define CONFIG_SYS_L2_PL310 +# define CONFIG_SYS_PL310_BASE 0xf8f02000 +#endif + +/* Serial drivers */ +#define CONFIG_BAUDRATE 115200 +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* Zynq Serial driver */ +#define CONFIG_ZYNQ_SERIAL_UART1 +#ifdef CONFIG_ZYNQ_SERIAL_UART0 +# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000 +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE +# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +#endif + +#ifdef CONFIG_ZYNQ_SERIAL_UART1 +# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000 +# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE +# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 +#endif + +#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) +# define CONFIG_ZYNQ_SERIAL +#endif + +/* DCC driver */ +#if defined(CONFIG_ZYNQ_DCC) +# define CONFIG_ARM_DCC +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#endif + +/* Ethernet driver */ +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 +#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) +# define CONFIG_NET_MULTI +# define CONFIG_ZYNQ_GEM +# define CONFIG_MII +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_PHYLIB +# define CONFIG_PHY_MARVELL +#endif + +#define CONFIG_ZYNQ_SPI +/* SPI */ +#ifdef CONFIG_ZYNQ_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_SST +# define CONFIG_CMD_SF +#endif + +/* NOR */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI0 +/* MMC */ +#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +# define CONFIG_MMC +# define CONFIG_GENERIC_MMC +# define CONFIG_SDHCI +# define CONFIG_ZYNQ_SDHCI +# define CONFIG_CMD_MMC +# define CONFIG_CMD_FAT +# define CONFIG_SUPPORT_VFAT +# define CONFIG_CMD_EXT2 +# define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_ZYNQ_I2C0 +/* I2C */ +#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) +# define CONFIG_CMD_I2C +# define CONFIG_SYS_I2C +# define CONFIG_SYS_I2C_ZYNQ +# define CONFIG_SYS_I2C_ZYNQ_SPEED 100000 +# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 +#endif + +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_MAY_FAIL + +/* Environment */ +#define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_LOAD_ADDR 0 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "zynq-uboot> " +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Physical Memory map */ +#define CONFIG_SYS_TEXT_BASE 0 + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) + +#define CONFIG_SYS_MALLOC_LEN 0x400000 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Enable the PL to be downloaded */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_ZYNQPL +#define CONFIG_CMD_FPGA + +/* Open Firmware flat tree */ +#define CONFIG_OF_LIBFDT + +/* FIT support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ + +/* Boot FreeBSD/vxWorks from an ELF image */ +#if defined(CONFIG_ZYNQ_BOOT_FREEBSD) +# define CONFIG_API +# define CONFIG_CMD_ELF +# define CONFIG_SYS_MMC_MAX_DEVICE 1 +#endif + +/* Commands */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII + +#endif /* __CONFIG_ZYNQ_COMMON_H */ diff --git a/include/configs/zynq.h b/include/configs/zynq.h deleted file mode 100644 index ea25159..0000000 --- a/include/configs/zynq.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * (C) Copyright 2012 Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQ_H -#define __CONFIG_ZYNQ_H - -/* High Level configuration Options */ -#define CONFIG_ARMV7 -#define CONFIG_ZYNQ - -/* CPU clock */ -#ifndef CONFIG_CPU_FREQ_HZ -# define CONFIG_CPU_FREQ_HZ 800000000 -#endif - -/* Cache options */ -#define CONFIG_CMD_CACHE -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define CONFIG_SYS_L2CACHE_OFF -#ifndef CONFIG_SYS_L2CACHE_OFF -# define CONFIG_SYS_L2_PL310 -# define CONFIG_SYS_PL310_BASE 0xf8f02000 -#endif - -/* Serial drivers */ -#define CONFIG_BAUDRATE 115200 -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* Zynq Serial driver */ -#define CONFIG_ZYNQ_SERIAL_UART1 -#ifdef CONFIG_ZYNQ_SERIAL_UART0 -# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000 -# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE -# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 -#endif - -#ifdef CONFIG_ZYNQ_SERIAL_UART1 -# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000 -# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE -# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 -#endif - -#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) -# define CONFIG_ZYNQ_SERIAL -#endif - -/* DCC driver */ -#if defined(CONFIG_ZYNQ_DCC) -# define CONFIG_ARM_DCC -# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ -#endif - -/* Ethernet driver */ -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 -#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) -# define CONFIG_NET_MULTI -# define CONFIG_ZYNQ_GEM -# define CONFIG_MII -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_PHYLIB -# define CONFIG_PHY_MARVELL -#endif - -#define CONFIG_ZYNQ_SPI -/* SPI */ -#ifdef CONFIG_ZYNQ_SPI -# define CONFIG_SPI_FLASH -# define CONFIG_SPI_FLASH_SST -# define CONFIG_CMD_SF -#endif - -/* NOR */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_SDHCI0 -/* MMC */ -#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) -# define CONFIG_MMC -# define CONFIG_GENERIC_MMC -# define CONFIG_SDHCI -# define CONFIG_ZYNQ_SDHCI -# define CONFIG_CMD_MMC -# define CONFIG_CMD_FAT -# define CONFIG_SUPPORT_VFAT -# define CONFIG_CMD_EXT2 -# define CONFIG_DOS_PARTITION -#endif - -#define CONFIG_ZYNQ_I2C0 -/* I2C */ -#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) -# define CONFIG_CMD_I2C -# define CONFIG_SYS_I2C -# define CONFIG_SYS_I2C_ZYNQ -# define CONFIG_SYS_I2C_ZYNQ_SPEED 100000 -# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 -#endif - -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_MAY_FAIL - -/* Environment */ -#define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_LOAD_ADDR 0 - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "zynq-uboot> " -#define CONFIG_SYS_HUSH_PARSER - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Physical Memory map */ -#define CONFIG_SYS_TEXT_BASE 0 - -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) - -#define CONFIG_SYS_MALLOC_LEN 0x400000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Enable the PL to be downloaded */ -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_ZYNQPL -#define CONFIG_CMD_FPGA - -/* Open Firmware flat tree */ -#define CONFIG_OF_LIBFDT - -/* FIT support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ - -/* Boot FreeBSD/vxWorks from an ELF image */ -#if defined(CONFIG_ZYNQ_BOOT_FREEBSD) -# define CONFIG_API -# define CONFIG_CMD_ELF -# define CONFIG_SYS_MMC_MAX_DEVICE 1 -#endif - -/* Commands */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII - -#endif /* __CONFIG_ZYNQ_H */ -- cgit v0.10.2 From ba45a072bf9a186d99aae35af56699eeb7704b1c Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:11 +0530 Subject: doc: zynq: Add information on zynq u-boot Information on zynq u-boot about - zynq boards - mainline status - TODO Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/doc/README.zynq b/doc/README.zynq new file mode 100644 index 0000000..56a74b4 --- /dev/null +++ b/doc/README.zynq @@ -0,0 +1,60 @@ +# +# Xilinx ZYNQ U-Boot +# +# (C) Copyright 2013 Xilinx, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +1. About this + +This document describes the information about Xilinx Zynq U-Boot - +like supported boards, ML status and TODO list. + +2. Zynq boards + +Xilinx Zynq-7000 All Programmable SoCs enable extensive system level +differentiation, integration, and flexibility through hardware, software, +and I/O programmability. + +* zc70x + - zc702 (single qspi, gem0, mmc) [1] + - zc706 (dual parallel qspi, gem0, mmc) [2] +* zed (single qspi, gem0, mmc) [3] +* microzed (single qspi, gem0, mmc) [4] +* zc770 + - zc770-xm010 (single qspi, gem0, mmc) + - zc770-xm011 (8 or 16 bit nand) + - zc770-xm012 (nor) + - zc770-xm013 (dual parallel qspi, gem1) + +3. Mainline status + +- Added basic board configurations support. +- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq +- Added zynq boards named - zynq, zynq_dcc +- Added zynq drivers: + serial - drivers/serial/serial_zynq.c + net - drivers/net/zynq_gem.c + mmc - drivers/mmc/zynq_sdhci.c + mmc - drivers/mmc/zynq_sdhci.c + spi- drivers/spi/zynq_spi.c + i2c - drivers/i2c/zynq_i2c.c + +4. TODO + +- Add zynq boards support - zc70x, zed, microzed, zc770 +- Add zynq qspi controller driver +- Add zynq nand controller driver +- d-cache support for zynq_gem.c +- FDT support for zynq boards +- Need proper cleanups on board configurations + +[1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm +[2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm +[3] http://zedboard.org/product/zedboard +[4] http://zedboard.org/product/microzed + +-- +Jagannadha Sutradharudu Teki +Sun Dec 15 14:52:41 IST 2013 -- cgit v0.10.2 From 022b02064a04d5edf2dc8e7cdf666421eed9d888 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:12 +0530 Subject: zynq: Add zynq zc70x board support The Zynq-7000 APSOC zc702 and zc706 enabled complte embedded processing includes ASIC and FPGA design. ZC702-: APSOC: - XC7Z020-CLG484-1 Memory: - DDR3 Component Memory 1GB - 16MB Quad SPI Flash - IIC - 1 KB EEPROM Connectivity: - Gigabit Ethernet GMII, RGMII and SGMII. - USB OTG - Host USB - IIC Bus Headers/HUB - 1 CAN with Wake on CAN - USB-UART Video/Display: - HDMI Video OUT - 8X LEDs Control & I/O: - 3 User Push Buttons - 2 User Switches - 8 User LEDs For more info on zc702 board: - http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm ZC706-: APSOC: - XC7Z045 FFG900 -2 AP SoC Memory: - DDR3 Component Memory 1GB (PS) - DDR3 SODIM Memory 1GB (PL) - 2X16MB Quad SPI Flash (dual parallel) - IIC - 1 KB EEPROM Connectivity: - PCIe Gen2x4 - SFP+ and SMA Pairs - GigE RGMII Ethernet (PS) - USB OTG 1 (PS) - Host USB - IIC Bus Headers/HUB (PS) - 1 CAN with Wake on CAN (PS) - USB-UART Video/Display: - HDMI 8 color RGB 4.4.4 1080P-60 OUT - HDMI IN 8 color RGB 4.4.4 Control & I/O: - 2 User Push Buttons/Dip Switch, 2 User LEDs - IIC access to GPIO - SDIO (SD Card slot) - 3 User Push Buttons, 2 User Switches, 8 User LEDs For more info on zc706 board: - http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/boards.cfg b/boards.cfg index 9e85fe0..51090ae 100644 --- a/boards.cfg +++ b/boards.cfg @@ -357,6 +357,7 @@ Active arm armv7 socfpga altera socfpga Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang +Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 9fe06e8..bce1094 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -36,7 +36,6 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /* Zynq Serial driver */ -#define CONFIG_ZYNQ_SERIAL_UART1 #ifdef CONFIG_ZYNQ_SERIAL_UART0 # define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000 # define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE @@ -60,8 +59,6 @@ #endif /* Ethernet driver */ -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 #if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) # define CONFIG_NET_MULTI # define CONFIG_ZYNQ_GEM @@ -71,7 +68,6 @@ # define CONFIG_PHY_MARVELL #endif -#define CONFIG_ZYNQ_SPI /* SPI */ #ifdef CONFIG_ZYNQ_SPI # define CONFIG_SPI_FLASH @@ -79,10 +75,6 @@ # define CONFIG_CMD_SF #endif -/* NOR */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_SDHCI0 /* MMC */ #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) # define CONFIG_MMC @@ -96,7 +88,6 @@ # define CONFIG_DOS_PARTITION #endif -#define CONFIG_ZYNQ_I2C0 /* I2C */ #if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) # define CONFIG_CMD_I2C diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h new file mode 100644 index 0000000..9910804 --- /dev/null +++ b/include/configs/zynq_zc70x.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards + * See zynq_common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZC70X_H +#define __CONFIG_ZYNQ_ZC70X_H + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_BOOT_FREEBSD + +#include + +#endif /* __CONFIG_ZYNQ_ZC70X_H */ -- cgit v0.10.2 From 796d49969e2674f1f2ab8564ccc7b6cb62892e38 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:13 +0530 Subject: zynq: Add zynq zed board support Zed is a complete development board based on the Xilinx Zynq-7000 All Programmable SoC. APSOC: - XC7Z020-CLG484-1 Memory: - 512 MB DDR3 - 256 Mb Quad-SPI Flash( - Full size SD/MMC card cage Connectivity: - 10/100/1000 Ethernet - USB OTG (Device/Host/OTG) - USB-UART Expansion: - FMC (Low Pin Count) - Pmod. headers (2x6) Video/Display: - HDMI output (1080p60 + audio) - VGA connector - 128 x 32 OLED - User LEDs (9) User inputs: - Slide switches (8) - Push button switches (7) Audio: - 24-bit stereo audio CODEC - Stereo line in/out - Headphone - Microphone input Analog: - Xilinx XADC header - Supports 4 analog inputs - 2 Differential / 4 Single-ended Debug: - On-board USB JTAG programming port - ARM Debug Access Port (DAP) For more info - http://zedboard.org/product/zedboard Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/boards.cfg b/boards.cfg index 51090ae..d8e27cc 100644 --- a/boards.cfg +++ b/boards.cfg @@ -358,6 +358,7 @@ Active arm armv7 u8500 st-ericsson snowball Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h new file mode 100644 index 0000000..278db1e --- /dev/null +++ b/include/configs/zynq_zed.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Configuration for Zynq Evaluation and Development Board - ZedBoard + * See zynq_common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZED_H +#define __CONFIG_ZYNQ_ZED_H + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_BOOT_FREEBSD + +#include + +#endif /* __CONFIG_ZYNQ_ZED_H */ -- cgit v0.10.2 From 86737bcf07e595e78620d29b429ad9e994a32659 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:14 +0530 Subject: zynq: Move CONFIG_SYS_SDRAM_SIZE to pre-board configs CONFIG_SYS_SDRAM_SIZE is specific to a board hence moved to specific pre-config board files. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bce1094..bb9e337 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -125,7 +125,6 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 9910804..6950d41 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -10,6 +10,8 @@ #ifndef __CONFIG_ZYNQ_ZC70X_H #define __CONFIG_ZYNQ_ZC70X_H +#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) + #define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 278db1e..31926df 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -10,6 +10,8 @@ #ifndef __CONFIG_ZYNQ_ZED_H #define __CONFIG_ZYNQ_ZED_H +#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) + #define CONFIG_ZYNQ_SERIAL_UART1 #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 -- cgit v0.10.2 From 0f5c215650625f4533c0456f60638aeab1801b3e Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:15 +0530 Subject: zynq-common: Define exact TEXT_BASE Defined TEXT_BASE for u-boot starts from 0x4000000 w.r.t zynq memory-map. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bb9e337..e5b1e1d 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -121,7 +121,7 @@ sizeof(CONFIG_SYS_PROMPT) + 16) /* Physical Memory map */ -#define CONFIG_SYS_TEXT_BASE 0 +#define CONFIG_SYS_TEXT_BASE 0x4000000 #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0 -- cgit v0.10.2 From 65da1efde2d76535265bf521f9f5a643e6755c9b Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:16 +0530 Subject: zynq: zc70x: Add Catalyst 24WC08 EEPROM config support Adds configurations for Catalyst 24WC08 EEPROM, which is present on the zynq boards. Enable EEPROM support for zc70x boards. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index e5b1e1d..cf96333 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -97,6 +97,16 @@ # define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 #endif +/* EEPROM */ +#ifdef CONFIG_ZYNQ_EEPROM +# define CONFIG_CMD_EEPROM +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +# define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ +#endif + #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 6950d41..0a7fa97 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -20,6 +20,7 @@ #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_EEPROM #define CONFIG_ZYNQ_BOOT_FREEBSD #include -- cgit v0.10.2 From e3b01de78c58a83f596deb4ab7fdcdffa3cb806c Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:17 +0530 Subject: zynq: Add zynq microzed board support MicroZed is a low-cost development board based on the Xilinx Zynq-7000 All Programmable SoC. APSOC: - XC7Z010-1CLG400C Memory: - 1 GB of DDR3 SDRAM - 128Mb of QSPI flash(S25FL128SAGBHI200) - Micro SD card interface Communication: - 10/100/1000 Ethernet - USB 2.0 - USB-UART User I/O: - 100 User I/O (50 per connector) - Configurable as up to 48 LVDS pairs or 100 single-ended I/O Misc: - Xilinx PC4 JTAG configuration port - PS JTAG pins accessible via Pmod - 33.33 MHz oscillator - User LED and push switch For more info - http://zedboard.org/product/microzed Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/boards.cfg b/boards.cfg index d8e27cc..682af42 100644 --- a/boards.cfg +++ b/boards.cfg @@ -359,6 +359,7 @@ Active arm armv7 u8500 st-ericsson u8500 Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h new file mode 100644 index 0000000..549a664 --- /dev/null +++ b/include/configs/zynq_microzed.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_MICROZED_H +#define __CONFIG_ZYNQ_MICROZED_H + +#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI0 + +#include + +#endif /* __CONFIG_ZYNQ_MICROZED_H */ -- cgit v0.10.2 From e1d3425b0b4a6119f4eeeaee2802d3081418b7ff Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:18 +0530 Subject: zynq: Add zynq_zc770 xm010 board support ZC770 is a complete development board based on the Xilinx Zynq-7000 All Programmable SoC, similar to ZC70x board but which has four different daughter cards, like XM010, XM011, XM012 and XM013 ZC770 XM010: - 1Gb DDR3 - 1Mb SST SPI flash - 128 Mb Quad-SPI Flash - 8 Mb SST SI flash - Full size SD/MMC card cage - 10/100/1000 Ethernet - USB-UART Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/boards.cfg b/boards.cfg index 682af42..02e144f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -360,6 +360,7 @@ Active arm armv7 vf610 freescale vf610twr Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h new file mode 100644 index 0000000..8589d9d --- /dev/null +++ b/include/configs/zynq_zc770.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Configuration settings for the Xilinx Zynq ZC770 board. + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZC770_H +#define __CONFIG_ZYNQ_ZC770_H + +#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_SYS_NO_FLASH + +#if defined(CONFIG_ZC770_XM010) +# define CONFIG_ZYNQ_SERIAL_UART1 +# define CONFIG_ZYNQ_GEM0 +# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 +# define CONFIG_ZYNQ_SDHCI0 +# define CONFIG_ZYNQ_SPI + +#else +# define CONFIG_ZYNQ_SERIAL_UART0 +#endif + +#include + +#endif /* __CONFIG_ZYNQ_ZC770_H */ -- cgit v0.10.2 From 309a9165f8564dc4608ed9dacfe4577413225cd7 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:19 +0530 Subject: zynq: Add zynq_zc770 xm013 board support ZC770 is a complete development board based on the Xilinx Zynq-7000 All Programmable SoC, similar to ZC70x board but which has four different daughter cards, like XM010, XM011, XM012 and XM013 ZC770 XM013: - 1GB DDR3 - 128 Mb Quad-SPI Flash(dual parallel) - USB-UART Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/boards.cfg b/boards.cfg index 02e144f..19905d0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -361,6 +361,7 @@ Active arm armv7 zynq xilinx zynq zynq_zc70x - Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h index 8589d9d..181f9fb 100644 --- a/include/configs/zynq_zc770.h +++ b/include/configs/zynq_zc770.h @@ -21,6 +21,11 @@ # define CONFIG_ZYNQ_SDHCI0 # define CONFIG_ZYNQ_SPI +#elif defined(CONFIG_ZC770_XM013) +# define CONFIG_ZYNQ_SERIAL_UART0 +# define CONFIG_ZYNQ_GEM1 +# define CONFIG_ZYNQ_GEM_PHY_ADDR1 7 + #else # define CONFIG_ZYNQ_SERIAL_UART0 #endif -- cgit v0.10.2 From fe5eddbf9818ba857d0d7f5e849b5682c9717b74 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:20 +0530 Subject: zynq: Add zynq_zc770 xm012 board support ZC770 is a complete development board based on the Xilinx Zynq-7000 All Programmable SoC, similar to ZC70x board but which has four different daughter cards, like XM010, XM011, XM012 and XM013 ZC770 XM012: - 1GB DDR3 - 64MiB Numonyx NOR flash - USB-UART Signed-off-by: Jagannadha Sutradharudu Teki Cc: Stefan Roese diff --git a/boards.cfg b/boards.cfg index 19905d0..a1a727f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -361,6 +361,7 @@ Active arm armv7 zynq xilinx zynq zynq_zc70x - Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek :Jagannadha Sutradharudu Teki +Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek :Jagannadha Sutradharudu Teki Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index cf96333..db47c42 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -75,6 +75,22 @@ # define CONFIG_CMD_SF #endif +/* NOR */ +#ifndef CONFIG_SYS_NO_FLASH +# define CONFIG_SYS_FLASH_BASE 0xE2000000 +# define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024) +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +# define CONFIG_SYS_MAX_FLASH_SECT 512 +# define CONFIG_SYS_FLASH_ERASE_TOUT 1000 +# define CONFIG_SYS_FLASH_WRITE_TOUT 5000 +# define CONFIG_FLASH_SHOW_PROGRESS 10 +# define CONFIG_SYS_FLASH_CFI +# undef CONFIG_SYS_FLASH_EMPTY_INFO +# define CONFIG_FLASH_CFI_DRIVER +# undef CONFIG_SYS_FLASH_PROTECTION +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + /* MMC */ #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) # define CONFIG_MMC diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h index 181f9fb..16b9047 100644 --- a/include/configs/zynq_zc770.h +++ b/include/configs/zynq_zc770.h @@ -21,6 +21,10 @@ # define CONFIG_ZYNQ_SDHCI0 # define CONFIG_ZYNQ_SPI +#elif defined(CONFIG_ZC770_XM012) +# define CONFIG_ZYNQ_SERIAL_UART1 +# undef CONFIG_SYS_NO_FLASH + #elif defined(CONFIG_ZC770_XM013) # define CONFIG_ZYNQ_SERIAL_UART0 # define CONFIG_ZYNQ_GEM1 -- cgit v0.10.2 From b3de92495f23db58a2643fb9328edacbf9a17f1c Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:21 +0530 Subject: zynq: Add support to find bootmode Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 717ec65..b4c11c3 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -101,6 +101,12 @@ void zynq_slcr_devcfg_enable(void) zynq_slcr_lock(); } +u32 zynq_slcr_get_boot_mode(void) +{ + /* Get the bootmode register value */ + return readl(&slcr_base->boot_mode); +} + u32 zynq_slcr_get_idcode(void) { return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 110de90..8f925af 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -13,6 +13,7 @@ extern void zynq_slcr_cpu_reset(void); extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk); extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); +extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); extern void zynq_ddrc_init(void); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 5119c09..a5b9bde 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -12,6 +12,12 @@ DECLARE_GLOBAL_DATA_PTR; +/* Bootmode setting values */ +#define ZYNQ_BM_MASK 0x0F +#define ZYNQ_BM_NOR 0x02 +#define ZYNQ_BM_SD 0x05 +#define ZYNQ_BM_JTAG 0x0 + #ifdef CONFIG_FPGA Xilinx_desc fpga; @@ -59,6 +65,25 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { + case ZYNQ_BM_NOR: + setenv("modeboot", "norboot"); + break; + case ZYNQ_BM_SD: + setenv("modeboot", "sdboot"); + break; + case ZYNQ_BM_JTAG: + setenv("modeboot", "jtagboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +} #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) diff --git a/doc/README.zynq b/doc/README.zynq index 56a74b4..ea1c8c1 100644 --- a/doc/README.zynq +++ b/doc/README.zynq @@ -28,7 +28,27 @@ and I/O programmability. - zc770-xm012 (nor) - zc770-xm013 (dual parallel qspi, gem1) -3. Mainline status +3. Bootmode + +Zynq has a facility to read the bootmode from the slcr bootmode register +once user is setting through jumpers on the board - see page no:1546 on [5] + +All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins +on [5]. + +board_late_init() will read the bootmode values using slcr bootmode register +at runtime and assign the modeboot variable to specific bootmode string which +is intern used in autoboot. + +SLCR bootmode register Bit[3:0] values +#define ZYNQ_BM_NOR 0x02 +#define ZYNQ_BM_SD 0x05 +#define ZYNQ_BM_JTAG 0x0 + +"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot" +bootmode strings at runtime. + +4. Mainline status - Added basic board configurations support. - Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq @@ -41,7 +61,7 @@ and I/O programmability. spi- drivers/spi/zynq_spi.c i2c - drivers/i2c/zynq_i2c.c -4. TODO +5. TODO - Add zynq boards support - zc70x, zed, microzed, zc770 - Add zynq qspi controller driver @@ -54,6 +74,7 @@ and I/O programmability. [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm [3] http://zedboard.org/product/zedboard [4] http://zedboard.org/product/microzed +[5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf -- Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index db47c42..b1fa0cb 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -140,6 +140,7 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE +#define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MAXARGS 15 /* max number of command args */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -- cgit v0.10.2 From e83f61a6b3c1123b5fede849cd2a426df1d3b9d1 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:22 +0530 Subject: zynq-common: Define default environment Defined default env. for autoboot FIT image from respective boot devices. Default settings: fit_image=fit.itb load_addr=0x2000000 fit_size=0x800000 flash_off=0x100000 nor_flash_off=0xE2100000 Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index b1fa0cb..1eaf17d 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -132,7 +132,28 @@ /* Environment */ #define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_LOAD_ADDR 0 + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fit_image=fit.itb\0" \ + "load_addr=0x2000000\0" \ + "fit_size=0x800000\0" \ + "flash_off=0x100000\0" \ + "nor_flash_off=0xE2100000\0" \ + "fdt_high=0x20000000\0" \ + "initrd_high=0x20000000\0" \ + "norboot=echo Copying FIT from NOR flash to RAM... && " \ + "cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \ + "bootm ${load_addr}\0" \ + "sdboot=echo Copying FIT from SD to RAM... && " \ + "fatload mmc 0 ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + "jtagboot=echo TFTPing FIT to RAM... && " \ + "tftp ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" +#define CONFIG_BOOTCOMMAND "run $modeboot" +#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ +#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "zynq-uboot> " -- cgit v0.10.2 From 18eee22f4cd9f864a3986f54c5af14040e093cbe Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:23 +0530 Subject: zynq-common: Change Env. Sector size to 128Kb Changed Env. Sector size from 0x10000 to 128Kb Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 1eaf17d..402009e 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -129,8 +129,10 @@ #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_MAY_FAIL +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE (128 << 10) + /* Environment */ -#define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ #define CONFIG_ENV_IS_NOWHERE /* Default environment */ -- cgit v0.10.2 From ed53e4d6900e863ef971bb79b96c0cb6676f35d8 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:24 +0530 Subject: zynq-common: Define flash env. partition Last 128Kb sector of 1Mb flash is defined as u-boot environment partition. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 402009e..568c49f 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -133,7 +133,17 @@ #define CONFIG_ENV_SIZE (128 << 10) /* Environment */ -#define CONFIG_ENV_IS_NOWHERE +#ifndef CONFIG_ENV_IS_NOWHERE +# ifndef CONFIG_SYS_NO_FLASH +# define CONFIG_ENV_IS_IN_FLASH +# elif defined(CONFIG_SYS_NO_FLASH) +# define CONFIG_ENV_IS_NOWHERE +# endif + +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +# define CONFIG_ENV_OFFSET 0xE0000 +# define CONFIG_CMD_SAVEENV +#endif /* Default environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v0.10.2 From b660ca13a8b2dab6d9d4127274060359abea4210 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:25 +0530 Subject: zynq-common: Define CONFIG_ENV_OVERWRITE Defined CONFIG_ENV_OVERWRITE, which allow to overwrite serial baudrate and ethaddr. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 568c49f..184d4ba 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -132,6 +132,9 @@ /* Total Size of Environment Sector */ #define CONFIG_ENV_SIZE (128 << 10) +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + /* Environment */ #ifndef CONFIG_ENV_IS_NOWHERE # ifndef CONFIG_SYS_NO_FLASH -- cgit v0.10.2 From f8f36c5dda67c53c471d1fe65215b9124ef62d71 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:26 +0530 Subject: dts: zynq: Add basic fdt support This patch provides a basic fdt support for zynq u-boot. zynq-7000.dtsi-> initial arch dts file zynq-zed.dts -> initial zed board dts file more devices should be added in subsequent patches. u-boot build: once configuring of a board done for building dtb with zynq-zed.dts as an input zynq-uboot> make DEVICE_TREE=zynq-zed Enabled CONFIG_OF_SEPARATE for building dtb separately. There is a new binary called u-boot-dtb.bin which is a u-boot with devicetree supported. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi new file mode 100644 index 0000000..f20b8bd --- /dev/null +++ b/arch/arm/dts/zynq-7000.dtsi @@ -0,0 +1,13 @@ +/* + * Xilinx Zynq 7000 DTSI + * Describes the hardware common to all Zynq 7000-based boards. + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/include/ "skeleton.dtsi" + +/ { + compatible = "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zed.dts b/board/xilinx/dts/zynq-zed.dts new file mode 100644 index 0000000..91a5deb --- /dev/null +++ b/board/xilinx/dts/zynq-zed.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZED board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZED Board"; + compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; +}; diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 184d4ba..8707bc0 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -212,6 +212,11 @@ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ +/* FDT support */ +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE +#define CONFIG_DISPLAY_BOARDINFO_LATE + /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) # define CONFIG_API -- cgit v0.10.2 From 84515165da1dd21171b7d6042f07b2af210849b5 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:27 +0530 Subject: gpio: zynq: Add dummy gpio routines GPIO dummy routines are required for fdt build, may be removed these dependencies once the u-boot fdt is fully optimized. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h new file mode 100644 index 0000000..2dbba75 --- /dev/null +++ b/arch/arm/include/asm/arch-zynq/gpio.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ZYNQ_GPIO_H +#define _ZYNQ_GPIO_H + +inline int gpio_get_value(unsigned gpio) +{ + return 0; +} + +inline int gpio_set_value(unsigned gpio, int val) +{ + return 0; +} + +inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +#endif /* _ZYNQ_GPIO_H */ -- cgit v0.10.2 From a8826eb4b34f47747ef760191c2aeaaa53d4d482 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:28 +0530 Subject: zynq-common: Enable verified boot(RSA) CONFIG_FIT_SIGNATURE - signature node support in FIT image CONFIG_RSA - RSA lib support Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 8707bc0..e7a8e9f 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -217,6 +217,10 @@ #define CONFIG_OF_SEPARATE #define CONFIG_DISPLAY_BOARDINFO_LATE +/* RSA support */ +#define CONFIG_FIT_SIGNATURE +#define CONFIG_RSA + /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) # define CONFIG_API -- cgit v0.10.2 From 9e0802bf821074a90d3bb5c9d4d9d3424d8c51aa Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:29 +0530 Subject: dts: zynq: Add more zynq dts files This patch adds initial dts support for supported zynq boards. Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/board/xilinx/dts/zynq-microzed.dts b/board/xilinx/dts/zynq-microzed.dts new file mode 100644 index 0000000..6da71c1 --- /dev/null +++ b/board/xilinx/dts/zynq-microzed.dts @@ -0,0 +1,14 @@ +/* + * Xilinx MicroZED board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq MicroZED Board"; + compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc702.dts b/board/xilinx/dts/zynq-zc702.dts new file mode 100644 index 0000000..667dc28 --- /dev/null +++ b/board/xilinx/dts/zynq-zc702.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC702 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC702 Board"; + compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc706.dts b/board/xilinx/dts/zynq-zc706.dts new file mode 100644 index 0000000..526fc88 --- /dev/null +++ b/board/xilinx/dts/zynq-zc706.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC706 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC706 Board"; + compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc770-xm010.dts b/board/xilinx/dts/zynq-zc770-xm010.dts new file mode 100644 index 0000000..8b542a1 --- /dev/null +++ b/board/xilinx/dts/zynq-zc770-xm010.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC770 XM010 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM010 Board"; + compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc770-xm012.dts b/board/xilinx/dts/zynq-zc770-xm012.dts new file mode 100644 index 0000000..0379a07 --- /dev/null +++ b/board/xilinx/dts/zynq-zc770-xm012.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC770 XM012 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM012 Board"; + compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; +}; diff --git a/board/xilinx/dts/zynq-zc770-xm013.dts b/board/xilinx/dts/zynq-zc770-xm013.dts new file mode 100644 index 0000000..a4f9e05 --- /dev/null +++ b/board/xilinx/dts/zynq-zc770-xm013.dts @@ -0,0 +1,14 @@ +/* + * Xilinx ZC770 XM013 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZC770 XM013 Board"; + compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; +}; -- cgit v0.10.2 From c91d0c74cfe4c6c6e155392a6b057fa868719297 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:30 +0530 Subject: zynq: Enable CONFIG_DEFAULT_DEVICE_TREE Enabled default dts files on respective pre-board config files this is way MAKEALL will works. and it's upto user to build specific dts by specifying at build time. $ make zynq_zc70x_config $ make --> with default dts zynq-zc702.dts or $ make DEVICE_TREE=zynq-zc702 --> Same configuration with zynq-zc706.dts Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h index 549a664..b0328a2 100644 --- a/include/configs/zynq_microzed.h +++ b/include/configs/zynq_microzed.h @@ -19,6 +19,7 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_DEFAULT_DEVICE_TREE zynq-microzed #include diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 0a7fa97..673660e 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -22,6 +22,7 @@ #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_EEPROM #define CONFIG_ZYNQ_BOOT_FREEBSD +#define CONFIG_DEFAULT_DEVICE_TREE zynq-zc702 #include diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h index 16b9047..8aa96e7 100644 --- a/include/configs/zynq_zc770.h +++ b/include/configs/zynq_zc770.h @@ -20,15 +20,18 @@ # define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 # define CONFIG_ZYNQ_SDHCI0 # define CONFIG_ZYNQ_SPI +# define CONFIG_DEFAULT_DEVICE_TREE zynq-zc770-xm010 #elif defined(CONFIG_ZC770_XM012) # define CONFIG_ZYNQ_SERIAL_UART1 # undef CONFIG_SYS_NO_FLASH +# define CONFIG_DEFAULT_DEVICE_TREE zynq-zc770-xm012 #elif defined(CONFIG_ZC770_XM013) # define CONFIG_ZYNQ_SERIAL_UART0 # define CONFIG_ZYNQ_GEM1 # define CONFIG_ZYNQ_GEM_PHY_ADDR1 7 +# define CONFIG_DEFAULT_DEVICE_TREE zynq-zc770-xm013 #else # define CONFIG_ZYNQ_SERIAL_UART0 diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 31926df..412dede 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -20,6 +20,7 @@ #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_BOOT_FREEBSD +#define CONFIG_DEFAULT_DEVICE_TREE zynq-zed #include -- cgit v0.10.2 From 10a147bc665367111920be657409a5d56d3c0590 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 9 Jan 2014 01:48:31 +0530 Subject: doc: Update the zynq u-boot status Updated doc/README.zynq to current status Signed-off-by: Jagannadha Sutradharudu Teki diff --git a/doc/README.zynq b/doc/README.zynq index ea1c8c1..043c970 100644 --- a/doc/README.zynq +++ b/doc/README.zynq @@ -28,7 +28,19 @@ and I/O programmability. - zc770-xm012 (nor) - zc770-xm013 (dual parallel qspi, gem1) -3. Bootmode +3. Building + + # Configure for zc70x board + $ make zynq_zc70x_config + Configuring for zynq_zc70x board... + + # Building default dts for zc702 board + $ make + + # Building specified dts for zc706 board + $ make DEVICE_TREE=zynq-zc706 + +4. Bootmode Zynq has a facility to read the bootmode from the slcr bootmode register once user is setting through jumpers on the board - see page no:1546 on [5] @@ -48,11 +60,11 @@ SLCR bootmode register Bit[3:0] values "modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot" bootmode strings at runtime. -4. Mainline status +5. Mainline status - Added basic board configurations support. - Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq -- Added zynq boards named - zynq, zynq_dcc +- Added zynq boards named - zc70x, zed, microzed, zc770_xm010, zc770_xm012, zc770_xm013 - Added zynq drivers: serial - drivers/serial/serial_zynq.c net - drivers/net/zynq_gem.c @@ -60,15 +72,16 @@ bootmode strings at runtime. mmc - drivers/mmc/zynq_sdhci.c spi- drivers/spi/zynq_spi.c i2c - drivers/i2c/zynq_i2c.c +- Done proper cleanups on board configurations +- Added basic FDT support for zynq boards +- d-cache support for zynq_gem.c -5. TODO +6. TODO -- Add zynq boards support - zc70x, zed, microzed, zc770 +- Add zynq boards support - zc770_xm011 - Add zynq qspi controller driver - Add zynq nand controller driver -- d-cache support for zynq_gem.c -- FDT support for zynq boards -- Need proper cleanups on board configurations +- Add FDT support on individual drivers [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm -- cgit v0.10.2