From 83d40dfd79fe868796275802f60116d84b9e4395 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 01:13:58 -0600 Subject: 85xx: Move LAW init code into C Move the initialization of the LAWs into C code and provide an API to allow modification of LAWs after init. Board code is responsible to provide a law_table and num_law_entries. We should be able to use the same code on 86xx as well. Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index fdb9ecb..9a65142 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -31,6 +31,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -140,6 +141,9 @@ void cpu_init_f (void) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); +#ifdef CONFIG_FSL_LAW + init_laws(); +#endif #ifdef CONFIG_CPM2 config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); @@ -222,11 +226,15 @@ void cpu_init_f (void) int cpu_init_r(void) { #ifdef CONFIG_CLEAR_LAW0 +#ifdef CONFIG_FSL_LAW + disable_law(0); +#else volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); /* clear alternate boot location LAW (used for sdram, or ddr bank) */ ecm->lawar0 = 0; #endif +#endif #if defined(CONFIG_L2_CACHE) volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index adc9c4d..bb5dc1f 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -27,6 +27,7 @@ #include #include #include +#include #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) @@ -1022,7 +1023,9 @@ spd_sdram(void) static unsigned int setup_laws_and_tlbs(unsigned int memsize) { +#ifndef CONFIG_FSL_LAW volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); +#endif unsigned int tlb_size; unsigned int law_size; unsigned int ram_tlb_index; @@ -1098,12 +1101,17 @@ setup_laws_and_tlbs(unsigned int memsize) /* * Set up LAWBAR for all of DDR. */ + +#ifdef CONFIG_FSL_LAW + set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR); +#else ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1); debug("DDR: LARAR1=0x%08x\n", ecm->lawar1); +#endif /* * Confirm that the requested amount of memory was mapped. diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index b489d2f..346369c 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -201,6 +201,7 @@ _start_e500: lis r7,CFG_CCSRBAR@h ori r7,r7,CFG_CCSRBAR@l +#ifndef CONFIG_FSL_LAW bl law_entry mr r6,r0 lwzu r5,0(r6) /* how many windows we actually use */ @@ -216,6 +217,7 @@ _start_e500: addi r2,r2,0x0020 addi r1,r1,0x0020 bdnz 0b +#endif /* Clear and set up some registers. */ li r0,0 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 78cec21..67521720 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libmisc.a COBJS-y += ali512x.o COBJS-y += ns87308.o COBJS-y += status_led.o +COBJS-$(CONFIG_FSL_LAW) += fsl_law.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c new file mode 100644 index 0000000..8bdf5a7 --- /dev/null +++ b/drivers/misc/fsl_law.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define LAWAR_EN 0x80000000 + +void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) +{ + volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08); + volatile u32 *lawbar = base + 8 * idx; + volatile u32 *lawar = base + 8 * idx + 2; + + out_be32(lawbar, addr >> 12); + out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz); + + return ; +} + +void disable_law(u8 idx) +{ + volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08); + volatile u32 *lawbar = base + 8 * idx; + volatile u32 *lawar = base + 8 * idx + 2; + + out_be32(lawar, 0); + out_be32(lawbar, 0); + + return; +} + +void init_laws(void) +{ + int i; + u8 law_idx = 0; + + for (i = 0; i < num_law_entries; i++) { + if (law_table[i].index != -1) + law_idx = law_table[i].index; + + set_law(law_idx++, law_table[i].addr, + law_table[i].size, law_table[i].trgt_id); + } + + return ; +} diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h new file mode 100644 index 0000000..7cb8840 --- /dev/null +++ b/include/asm-ppc/fsl_law.h @@ -0,0 +1,80 @@ +#ifndef _FSL_LAW_H_ +#define _FSL_LAW_H_ + +#include + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define SET_LAW_ENTRY(idx, a, sz, trgt) \ + { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } + +enum law_size { + LAW_SIZE_4K = 0xb, + LAW_SIZE_8K, + LAW_SIZE_16K, + LAW_SIZE_32K, + LAW_SIZE_64K, + LAW_SIZE_128K, + LAW_SIZE_256K, + LAW_SIZE_512K, + LAW_SIZE_1M, + LAW_SIZE_2M, + LAW_SIZE_4M, + LAW_SIZE_8M, + LAW_SIZE_16M, + LAW_SIZE_32M, + LAW_SIZE_64M, + LAW_SIZE_128M, + LAW_SIZE_256M, + LAW_SIZE_512M, + LAW_SIZE_1G, + LAW_SIZE_2G, + LAW_SIZE_4G, + LAW_SIZE_8G, + LAW_SIZE_16G, + LAW_SIZE_32G, +}; + +enum law_trgt_if { + LAW_TRGT_IF_PCI = 0x00, + LAW_TRGT_IF_PCI_2 = 0x01, +#ifndef CONFIG_MPC8641 + LAW_TRGT_IF_PCIE_1 = 0x02, +#endif +#ifndef CONFIG_MPC8572 + LAW_TRGT_IF_PCIE_3 = 0x03, +#endif + LAW_TRGT_IF_LBC = 0x04, + LAW_TRGT_IF_CCSR = 0x08, + LAW_TRGT_IF_DDR_INTRLV = 0x0b, + LAW_TRGT_IF_RIO = 0x0c, + LAW_TRGT_IF_DDR = 0x0f, + LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ +}; +#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR +#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI +#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI +#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 + +#ifdef CONFIG_MPC8641 +#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI +#endif + +#ifdef CONFIG_MPC8572 +#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI +#endif + +struct law_entry { + int index; + phys_addr_t addr; + enum law_size size; + enum law_trgt_if trgt_id; +}; + +extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); +extern void disable_law(u8 idx); +extern void init_laws(void); + +/* define in board code */ +extern struct law_entry law_table[]; +extern int num_law_entries; +#endif -- cgit v0.10.2 From 4bcae9c92aee0d72a2f19b81cab27ef38107ce75 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 01:16:16 -0600 Subject: 85xx: convert MPC8544 DS over to use new LAW init code Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index c6f159a..665251d 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o SOBJS := init.o diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index 544dc07..3918176 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -172,51 +172,3 @@ tlb1_entry: .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) 2: entry_end - -/* - * LAW(Local Access Window) configuration: - * - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * LAW 0 is reserved for boot mapping - */ - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - - .long (4f-3f)/8 -3: - .long 0 - .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN - - .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) - - .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K) - - .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) - - .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M) - - .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K) - - .long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M) - - .long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K) - - /* contains both PCIE3 MEM & IO space */ - .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M) -4: - entry_end diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c new file mode 100644 index 0000000..433e509 --- /dev/null +++ b/board/freescale/mpc8544ds/law.c @@ -0,0 +1,42 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(4, CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(5, CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW_ENTRY(6, CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW_ENTRY(7, CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW_ENTRY(8, CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + /* contains both PCIE3 MEM & IO space */ + SET_LAW_ENTRY(9, CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 5a96db5..a894209 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -42,6 +42,8 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -- cgit v0.10.2 From 7232a2724ccc9dcbc3ec4ef84ada02f13ccd1238 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 01:32:06 -0600 Subject: 85xx: convert MPC8540/MPC8560 ADS over to use new LAW init code Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile index 2913650..0c8f470 100644 --- a/board/freescale/mpc8540ads/Makefile +++ b/board/freescale/mpc8540ads/Makefile @@ -25,9 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o SOBJS := init.o -#SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S index 74d71c6..c495f1e 100644 --- a/board/freescale/mpc8540ads/init.S +++ b/board/freescale/mpc8540ads/init.S @@ -210,56 +210,3 @@ tlb1_entry: #endif entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c new file mode 100644 index 0000000..ab6a6f2 --- /dev/null +++ b/board/freescale/mpc8540ads/law.c @@ -0,0 +1,58 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { +#ifndef CONFIG_SPD_EEPROM + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), +#endif + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + /* This is not so much the SDRAM map as it is the whole localbus map. */ + SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile index 2913650..0c8f470 100644 --- a/board/freescale/mpc8560ads/Makefile +++ b/board/freescale/mpc8560ads/Makefile @@ -25,9 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o SOBJS := init.o -#SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S index 37fd0c6..151b4f6 100644 --- a/board/freescale/mpc8560ads/init.S +++ b/board/freescale/mpc8560ads/init.S @@ -211,56 +211,3 @@ tlb1_entry: #endif entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c new file mode 100644 index 0000000..ab6a6f2 --- /dev/null +++ b/board/freescale/mpc8560ads/law.c @@ -0,0 +1,58 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { +#ifndef CONFIG_SPD_EEPROM + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), +#endif + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + /* This is not so much the SDRAM map as it is the whole localbus map. */ + SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index afce7fb..5ea7b25 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -55,6 +55,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 5f10555..08884b3 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -52,6 +52,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx -- cgit v0.10.2 From 2cfaa1aa1aac39a81006b7b27e0e431bf21f6dfa Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 01:45:10 -0600 Subject: 85xx: convert MPC8541/MPC8555/MPC8548 CDS over to use new LAW init code Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile index 7f53098..5497708 100644 --- a/board/freescale/mpc8541cds/Makefile +++ b/board/freescale/mpc8541cds/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o \ +COBJS := $(BOARD).o law.o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ diff --git a/board/freescale/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S index 8c8c087..563ea2d 100644 --- a/board/freescale/mpc8541cds/init.S +++ b/board/freescale/mpc8541cds/init.S @@ -190,54 +190,3 @@ tlb1_entry: .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe20f_ffff PCI1 IO 1M - * 0xe210_0000 0xe21f_ffff PCI2 IO 1M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. - */ - -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) - -#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) - -/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ -#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - - .section .bootpg, "ax" - .globl law_entry - -law_entry: - entry_start - .long 6 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 - entry_end diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c new file mode 100644 index 0000000..a8aa4db --- /dev/null +++ b/board/freescale/mpc8541cds/law.c @@ -0,0 +1,58 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile index 7f53098..5497708 100644 --- a/board/freescale/mpc8548cds/Makefile +++ b/board/freescale/mpc8548cds/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o \ +COBJS := $(BOARD).o law.o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ diff --git a/board/freescale/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S index ed0fc44..51e1cc4 100644 --- a/board/freescale/mpc8548cds/init.S +++ b/board/freescale/mpc8548cds/init.S @@ -182,71 +182,3 @@ tlb1_entry: 2: entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCIe MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe10f_ffff PCI1 IO 1M - * 0xe280_0000 0xe20f_ffff PCI2 IO 1M - * 0xe300_0000 0xe30f_ffff PCIe IO 1M - * 0xf000_0000 0xf3ff_ffff SDRAM 64M - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * LAW 0 is reserved for boot mapping - */ - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - - .long (4f-3f)/8 -3: - .long 0 - .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN - -#ifdef CFG_PCI1_MEM_PHYS - .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) - - .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) -#endif - -#ifdef CFG_PCI2_MEM_PHYS - .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) - - .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) -#endif - -#ifdef CFG_PCIE1_MEM_PHYS - .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M) - - .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M) -#endif - - /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) - -#ifdef CFG_RIO_MEM_PHYS - .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M) -#endif -4: - entry_end diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c new file mode 100644 index 0000000..6920863 --- /dev/null +++ b/board/freescale/mpc8548cds/law.c @@ -0,0 +1,73 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe10f_ffff PCI1 IO 1M + * 0xe280_0000 0xe20f_ffff PCI2 IO 1M + * 0xe300_0000 0xe30f_ffff PCIe IO 1M + * 0xf000_0000 0xf3ff_ffff SDRAM 64M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * LAW 0 is reserved for boot mapping + */ + +struct law_entry law_table[] = { +#ifdef CFG_PCI1_MEM_PHYS + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), +#endif +#ifdef CFG_PCI2_MEM_PHYS + SET_LAW_ENTRY(4, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), +#endif +#ifdef CFG_PCIE1_MEM_PHYS + SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), +#endif + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + SET_LAW_ENTRY(8, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#ifdef CFG_RIO_MEM_PHYS + SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile index 7f53098..5497708 100644 --- a/board/freescale/mpc8555cds/Makefile +++ b/board/freescale/mpc8555cds/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o \ +COBJS := $(BOARD).o law.o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ diff --git a/board/freescale/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S index 8c8c087..563ea2d 100644 --- a/board/freescale/mpc8555cds/init.S +++ b/board/freescale/mpc8555cds/init.S @@ -190,54 +190,3 @@ tlb1_entry: .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe20f_ffff PCI1 IO 1M - * 0xe210_0000 0xe21f_ffff PCI2 IO 1M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. - */ - -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) - -#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) - -/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ -#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - - .section .bootpg, "ax" - .globl law_entry - -law_entry: - entry_start - .long 6 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 - entry_end diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c new file mode 100644 index 0000000..a8aa4db --- /dev/null +++ b/board/freescale/mpc8555cds/law.c @@ -0,0 +1,58 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index c83382f..7334088 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -47,6 +47,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 90beb25..a3db9f4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -55,6 +55,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 76d673c..93877ae 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -47,6 +47,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, -- cgit v0.10.2 From e2b159d0070ee06e4ac7e2f9381d3e8e542e614a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 09:05:27 -0600 Subject: 85xx: convert SBC8540/SBC8560/SBC8548 over to use new LAW init code Signed-off-by: Kumar Gala diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index 1596525..c346fdf 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -28,9 +28,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o SOBJS := init.o -#SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/sbc8548/init.S b/board/sbc8548/init.S index cafa214..6696dd9 100644 --- a/board/sbc8548/init.S +++ b/board/sbc8548/init.S @@ -191,51 +191,3 @@ tlb1_entry: .long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x0fff_ffff DDR 256M - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf8b0_0000 0xf80f_ffff EEPROM 1M - * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. - */ - - -#if !defined(CONFIG_SPD_EEPROM) - #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) - #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#else - #define LAWBAR0 0 - #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ -#define LAWBAR3 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - - .section .bootpg, "ax" - .globl law_entry - -law_entry: - entry_start - .long 4 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - entry_end diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c new file mode 100644 index 0000000..6bf4199 --- /dev/null +++ b/board/sbc8548/law.c @@ -0,0 +1,57 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x0fff_ffff DDR 256M + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf8b0_0000 0xf80f_ffff EEPROM 1M + * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { +#ifndef CONFIG_SPD_EEPROM + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), +#endif + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + SET_LAW_ENTRY(4, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile index 1596525..c346fdf 100644 --- a/board/sbc8560/Makefile +++ b/board/sbc8560/Makefile @@ -28,9 +28,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o SOBJS := init.o -#SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S index 95cb85a..e149fbd 100644 --- a/board/sbc8560/init.S +++ b/board/sbc8560/init.S @@ -40,51 +40,6 @@ mtlr r1 ; \ blr ; - -/* LAW(Local Access Window) configuration: - * 0000_0000-0800_0000: DDR(512M) -or- larger - * c000_0000-cfff_ffff: PCI(256M) - * d000_0000-dfff_ffff: RapidIO(256M) - * e000_0000-ffff_ffff: localbus(512M) - * e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6 - * e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1 - * e800_0000-efff_ffff: LBC 128M, nothing here - * f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3 - * f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4 - * f800_0000-fdff_ffff: LBC 64M, nothing here - * fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5 - * fd00_0000-fdff_ffff: LBC 16M, nothing here - * fe00_0000-feff_ffff: LBC 16M, nothing here - * ff00_0000-ff6f_ffff: LBC 7M, nothing here - * ff70_0000-ff7f_ffff: CCSRBAR 1M - * ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0 - * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access - * Window. - * Note: If flash is 8M at default position(last 8M),no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) - #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) - #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#else - #define LAWBAR0 0 - #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR2 ((0xe0000000>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x03 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 - entry_end - /* TLB1 entries configuration: */ .section .bootpg, "ax" diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c new file mode 100644 index 0000000..d1c6dc2 --- /dev/null +++ b/board/sbc8560/law.c @@ -0,0 +1,60 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* LAW(Local Access Window) configuration: + * 0000_0000-0800_0000: DDR(512M) -or- larger + * c000_0000-cfff_ffff: PCI(256M) + * d000_0000-dfff_ffff: RapidIO(256M) + * e000_0000-ffff_ffff: localbus(512M) + * e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6 + * e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1 + * e800_0000-efff_ffff: LBC 128M, nothing here + * f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3 + * f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4 + * f800_0000-fdff_ffff: LBC 64M, nothing here + * fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5 + * fd00_0000-fdff_ffff: LBC 16M, nothing here + * fe00_0000-feff_ffff: LBC 16M, nothing here + * ff00_0000-ff6f_ffff: LBC 7M, nothing here + * ff70_0000-ff7f_ffff: CCSRBAR 1M + * ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0 + * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access + * Window. + * Note: If flash is 8M at default position(last 8M),no LAW needed. + */ + +struct law_entry law_table[] = { +#ifndef CONFIG_SPD_EEPROM + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), +#endif + SET_LAW_ENTRY(2, CFG_PCI_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 3ca85b8..2bbfe9a 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -56,6 +56,7 @@ #undef CONFIG_PCI /* pci ethernet support */ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index c050a06..0a7a904 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -56,6 +56,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index b71ba78..f9ede5f 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -50,6 +50,7 @@ #undef CONFIG_PCI /* pci ethernet support */ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE -- cgit v0.10.2 From 45f2166ac0233a9263058378f39612bd11f61196 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 09:06:48 -0600 Subject: 85xx: convert PM854/PM856 over to use new LAW init code Signed-off-by: Kumar Gala diff --git a/board/pm854/Makefile b/board/pm854/Makefile index 2913650..0c8f470 100644 --- a/board/pm854/Makefile +++ b/board/pm854/Makefile @@ -25,9 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o SOBJS := init.o -#SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/pm854/init.S b/board/pm854/init.S index 0a403ab..f6ea8b3 100644 --- a/board/pm854/init.S +++ b/board/pm854/init.S @@ -196,56 +196,3 @@ tlb1_entry: #endif entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/pm854/law.c b/board/pm854/law.c new file mode 100644 index 0000000..65a4b59 --- /dev/null +++ b/board/pm854/law.c @@ -0,0 +1,58 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { +#ifndef CONFIG_SPD_EEPROM + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), +#endif + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + /* This is not so much the SDRAM map as it is the whole localbus map. */ + SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/pm856/Makefile b/board/pm856/Makefile index 2913650..0c8f470 100644 --- a/board/pm856/Makefile +++ b/board/pm856/Makefile @@ -25,9 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o SOBJS := init.o -#SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/pm856/init.S b/board/pm856/init.S index 0a403ab..f6ea8b3 100644 --- a/board/pm856/init.S +++ b/board/pm856/init.S @@ -196,56 +196,3 @@ tlb1_entry: #endif entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/pm856/law.c b/board/pm856/law.c new file mode 100644 index 0000000..65a4b59 --- /dev/null +++ b/board/pm856/law.c @@ -0,0 +1,58 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { +#ifndef CONFIG_SPD_EEPROM + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), +#endif + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + /* This is not so much the SDRAM map as it is the whole localbus map. */ + SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/PM854.h b/include/configs/PM854.h index f0d0399..819bee7 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -51,6 +51,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/PM856.h b/include/configs/PM856.h index ae2645c..8902f42 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -51,6 +51,7 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx -- cgit v0.10.2 From 572b13afc42710f2957c382a710360429c0e099b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 09:11:53 -0600 Subject: 85xx: convert STXGP3/STXSSA over to use new LAW init code Signed-off-by: Kumar Gala diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile index 7d52f8c..c892247 100644 --- a/board/stxgp3/Makefile +++ b/board/stxgp3/Makefile @@ -25,9 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o +COBJS := $(BOARD).o flash.o law.o SOBJS := init.o -#SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S index f491a57..9bc8dd6 100644 --- a/board/stxgp3/init.S +++ b/board/stxgp3/init.S @@ -217,56 +217,3 @@ tlb1_entry: #endif entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xfc00_0000 0xfc00_ffff Config Latch 64K - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/stxgp3/law.c b/board/stxgp3/law.c new file mode 100644 index 0000000..6f215e1 --- /dev/null +++ b/board/stxgp3/law.c @@ -0,0 +1,58 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xfc00_0000 0xfc00_ffff Config Latch 64K + * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { +#ifndef CONFIG_SPD_EEPROM + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), +#endif + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + /* This is not so much the SDRAM map as it is the whole localbus map. */ + SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stxssa/Makefile b/board/stxssa/Makefile index 344ecdf..c43dd4e 100644 --- a/board/stxssa/Makefile +++ b/board/stxssa/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o SOBJS := init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/stxssa/init.S b/board/stxssa/init.S index 82dafb8..0c4fb30 100644 --- a/board/stxssa/init.S +++ b/board/stxssa/init.S @@ -189,56 +189,3 @@ tlb1_entry: .long FSL_BOOKE_MAS2(CFG_LBC_OPTION_BASE, (MAS2_I|MAS2_G)) .long FSL_BOOKE_MAS3(CFG_LBC_OPTION_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xfaff_ffff Local bus 128M - * 0xfb00_0000 0xfb00_ffff Config Latch 64K - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* Map the whole localbus, including flash and reset latch. -*/ -#define LAWBAR5 ((CFG_LBC_OPTION_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 6 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 - entry_end diff --git a/board/stxssa/law.c b/board/stxssa/law.c new file mode 100644 index 0000000..2969060 --- /dev/null +++ b/board/stxssa/law.c @@ -0,0 +1,60 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf000_0000 0xfaff_ffff Local bus 128M + * 0xfb00_0000 0xfb00_ffff Config Latch 64K + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { +#ifndef CONFIG_SPD_EEPROM + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), +#endif + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + /* Map the whole localbus, including flash and reset latch. */ + SET_LAW_ENTRY(6, CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 3baa32c..047e1cf 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -51,6 +51,7 @@ #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* sysclk for MPC85xx */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 9457bce..e09dd71 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -51,6 +51,7 @@ #undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* sysclk for MPC85xx */ -- cgit v0.10.2 From 4d3521cc79cabc61edf12c48c0ce318d4efb712f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 09:15:29 -0600 Subject: 85xx: convert remaining 85xx boards over to use new LAW init code Converted ATUM8548, MPC8568 MDS, MPC8540 EVAL, and TQM85xx boards over to use new LAW init code. Signed-off-by: Kumar Gala diff --git a/board/atum8548/Makefile b/board/atum8548/Makefile index e198062..bf0830c 100644 --- a/board/atum8548/Makefile +++ b/board/atum8548/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o SOBJS := init.o diff --git a/board/atum8548/init.S b/board/atum8548/init.S index 654a569..7e161c1 100644 --- a/board/atum8548/init.S +++ b/board/atum8548/init.S @@ -30,11 +30,6 @@ #include #include -#define LAWAR_TRGT_PCI1 0x00000000 -#define LAWAR_TRGT_PCI2 0x00100000 -#define LAWAR_TRGT_PCIE 0x00200000 -#define LAWAR_TRGT_DDR 0x00f00000 - /* * TLB0 and TLB1 Entries * @@ -178,58 +173,3 @@ tlb1_entry: 2: entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCIe MEM 512M - * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe10f_ffff PCI1 IO 1M - * 0xe280_0000 0xe20f_ffff PCI2 IO 1M - * 0xe300_0000 0xe30f_ffff PCIe IO 1M - * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * LAW 0 is reserved for boot mapping - */ - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - - .long (4f-3f)/8 -3: - .long 0 - .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)) & ~LAWAR_EN - - .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) - - .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) - - .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) - - .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) - - .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M) - - .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) - - /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) - -4: - entry_end diff --git a/board/atum8548/law.c b/board/atum8548/law.c new file mode 100644 index 0000000..3606cbb --- /dev/null +++ b/board/atum8548/law.c @@ -0,0 +1,61 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M + * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe10f_ffff PCI1 IO 1M + * 0xe280_0000 0xe20f_ffff PCI2 IO 1M + * 0xe300_0000 0xe30f_ffff PCIe IO 1M + * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * LAW 0 is reserved for boot mapping + */ + +struct law_entry law_table[] = { + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + SET_LAW_ENTRY(8, CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile index 643fbc0..ef78942 100644 --- a/board/freescale/mpc8568mds/Makefile +++ b/board/freescale/mpc8568mds/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o bcsr.o +COBJS := $(BOARD).o bcsr.o law.o SOBJS := init.o diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S index 2748c51..39819ab 100644 --- a/board/freescale/mpc8568mds/init.S +++ b/board/freescale/mpc8568mds/init.S @@ -176,61 +176,3 @@ tlb1_entry: 2: entry_end - -/* - * LAW(Local Access Window) configuration: - * - *0) 0x0000_0000 0x7fff_ffff DDR 2G - *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB - *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB - *-) 0xe000_0000 0xe00f_ffff CCSR 1M - *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M - *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M - *5) 0xc000_0000 0xdfff_ffff SRIO 512MB - *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB - *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB - *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB - *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB - *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB - * - *Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. - */ - -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) - -#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) - -#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ -#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - - .section .bootpg, "ax" - .globl law_entry - -law_entry: - entry_start - .long (4f-3f)/8 -3: - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6 -4: - entry_end diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c new file mode 100644 index 0000000..b35bbcd --- /dev/null +++ b/board/freescale/mpc8568mds/law.c @@ -0,0 +1,62 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + *0) 0x0000_0000 0x7fff_ffff DDR 2G + *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB + *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB + *-) 0xe000_0000 0xe00f_ffff CCSR 1M + *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M + *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M + *5) 0xc000_0000 0xdfff_ffff SRIO 512MB + *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB + *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB + *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB + *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB + *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB + * + *Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + */ + +struct law_entry law_table[] = { + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), + SET_LAW_ENTRY(6, CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ + SET_LAW_ENTRY(7, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile index d649c60..c892247 100644 --- a/board/mpc8540eval/Makefile +++ b/board/mpc8540eval/Makefile @@ -25,10 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o -#COBJS := $(BOARD).o flash.o $(BOARD)_slave.o +COBJS := $(BOARD).o flash.o law.o SOBJS := init.o -#SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S index a8ac3fb..adc5115 100644 --- a/board/mpc8540eval/init.S +++ b/board/mpc8540eval/init.S @@ -135,44 +135,3 @@ tlb1_entry: .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) #endif entry_end - -/* LAW(Local Access Window) configuration: - * 0000_0000-0800_0000: DDR(128M) -or- larger - * f000_0000-f3ff_ffff: PCI(256M) - * f400_0000-f7ff_ffff: RapidIO(128M) - * f800_0000-ffff_ffff: localbus(128M) - * f800_0000-fbff_ffff: LBC SDRAM(64M) - * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M) - * fdf0_0000-fdff_ffff: CCSRBAR(1M) - * fe00_0000-ffff_ffff: Flash(32M) - * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access - * Window. - * Note: If flash is 8M at default position(last 8M),no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#if !defined(CONFIG_RAM_AS_FLASH) -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR2 0 -#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x03 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 - entry_end diff --git a/board/mpc8540eval/law.c b/board/mpc8540eval/law.c new file mode 100644 index 0000000..4d603f0 --- /dev/null +++ b/board/mpc8540eval/law.c @@ -0,0 +1,54 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* LAW(Local Access Window) configuration: + * 0000_0000-0800_0000: DDR(128M) -or- larger + * f000_0000-f3ff_ffff: PCI(256M) + * f400_0000-f7ff_ffff: RapidIO(128M) + * f800_0000-ffff_ffff: localbus(128M) + * f800_0000-fbff_ffff: LBC SDRAM(64M) + * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M) + * fdf0_0000-fdff_ffff: CCSRBAR(1M) + * fe00_0000-ffff_ffff: Flash(32M) + * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access + * Window. + * Note: If flash is 8M at default position(last 8M),no LAW needed. + */ + +struct law_entry law_table[] = { +#ifndef CONFIG_SPD_EEPROM + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), +#endif + SET_LAW_ENTRY(2, CFG_PCI_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCI), +#ifndef CONFIG_RAM_AS_FLASH + SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/tqm85xx/Makefile b/board/tqm85xx/Makefile index cad7e1e..66f2830 100644 --- a/board/tqm85xx/Makefile +++ b/board/tqm85xx/Makefile @@ -25,9 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o sdram.o +COBJS := $(BOARD).o sdram.o law.o SOBJS := init.o -#SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S index dcb9386..1b25deb 100644 --- a/board/tqm85xx/init.S +++ b/board/tqm85xx/init.S @@ -176,47 +176,3 @@ tlb1_entry: .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/tqm85xx/law.c b/board/tqm85xx/law.c new file mode 100644 index 0000000..1573e58 --- /dev/null +++ b/board/tqm85xx/law.c @@ -0,0 +1,54 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index f7020b4..c14376e 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -63,6 +63,8 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ #define CONFIG_SYS_CLK_FREQ 33000000 diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 2868dcb..bf64f27 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -43,6 +43,8 @@ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + /* Using Localbus SDRAM to emulate flash before we can program the flash, * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. * Not availabe for EVAL board diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 2b089d9..a12d193 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -49,6 +49,7 @@ /*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index f3b1a53..dd0654b 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -50,6 +50,8 @@ #define CONFIG_CPM2 1 /* has CPM2 */ #endif +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + /* * sysclk for MPC85xx * -- cgit v0.10.2 From 54a5070115eff38e9b324b78abdfa0b4520580b9 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 09:22:29 -0600 Subject: 85xx: Remove old style of LAW init All boards are now using the new fsl_law code so we can drop the old version. Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index bb5dc1f..90c3d44 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1023,9 +1023,6 @@ spd_sdram(void) static unsigned int setup_laws_and_tlbs(unsigned int memsize) { -#ifndef CONFIG_FSL_LAW - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); -#endif unsigned int tlb_size; unsigned int law_size; unsigned int ram_tlb_index; @@ -1104,13 +1101,6 @@ setup_laws_and_tlbs(unsigned int memsize) #ifdef CONFIG_FSL_LAW set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR); -#else - ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - ecm->lawar1 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR - | (LAWAR_SIZE & law_size)); - debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1); - debug("DDR: LARAR1=0x%08x\n", ecm->lawar1); #endif /* diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 346369c..2044722 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -201,24 +201,6 @@ _start_e500: lis r7,CFG_CCSRBAR@h ori r7,r7,CFG_CCSRBAR@l -#ifndef CONFIG_FSL_LAW - bl law_entry - mr r6,r0 - lwzu r5,0(r6) /* how many windows we actually use */ - mtctr r5 - - li r2,0x0c28 /* the first pair is reserved for */ - li r1,0x0c30 /* boot-over-rio-or-pci */ - -0: lwzu r4,4(r6) - lwzu r3,4(r6) - stwx r4,r7,r2 - stwx r3,r7,r1 - addi r2,r2,0x0020 - addi r1,r1,0x0020 - bdnz 0b -#endif - /* Clear and set up some registers. */ li r0,0 mtmsr r0 -- cgit v0.10.2 From c8c41d4a80b1a8ad5984a287d81ea780496259f8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 10:04:42 -0600 Subject: 85xx: Use proper defines for PCI addresses We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE. While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only be used for configuring the PCI ATMU. Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S index c495f1e..4c8dd0e 100644 --- a/board/freescale/mpc8540ads/init.S +++ b/board/freescale/mpc8540ads/init.S @@ -130,8 +130,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -139,8 +139,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c index ab6a6f2..785576a 100644 --- a/board/freescale/mpc8540ads/law.c +++ b/board/freescale/mpc8540ads/law.c @@ -48,7 +48,7 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), diff --git a/board/freescale/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S index 563ea2d..6e93fb0 100644 --- a/board/freescale/mpc8541cds/init.S +++ b/board/freescale/mpc8541cds/init.S @@ -130,8 +130,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -139,8 +139,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded @@ -148,8 +148,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 3, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 4: 256M Non-cacheable, guarded @@ -157,8 +157,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 4, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 5: 64M Non-cacheable, guarded diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c index a8aa4db..0ac223c 100644 --- a/board/freescale/mpc8541cds/law.c +++ b/board/freescale/mpc8541cds/law.c @@ -47,8 +47,8 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index 6920863..0ee53e2 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -52,11 +52,11 @@ struct law_entry law_table[] = { #ifdef CFG_PCI1_MEM_PHYS - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), #endif #ifdef CFG_PCI2_MEM_PHYS - SET_LAW_ENTRY(4, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), #endif #ifdef CFG_PCIE1_MEM_PHYS diff --git a/board/freescale/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S index 563ea2d..6e93fb0 100644 --- a/board/freescale/mpc8555cds/init.S +++ b/board/freescale/mpc8555cds/init.S @@ -130,8 +130,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -139,8 +139,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded @@ -148,8 +148,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 3, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 4: 256M Non-cacheable, guarded @@ -157,8 +157,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 4, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 5: 64M Non-cacheable, guarded diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c index a8aa4db..0ac223c 100644 --- a/board/freescale/mpc8555cds/law.c +++ b/board/freescale/mpc8555cds/law.c @@ -47,8 +47,8 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ diff --git a/board/freescale/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S index 151b4f6..8ade9ca 100644 --- a/board/freescale/mpc8560ads/init.S +++ b/board/freescale/mpc8560ads/init.S @@ -131,8 +131,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -140,8 +140,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c index ab6a6f2..785576a 100644 --- a/board/freescale/mpc8560ads/law.c +++ b/board/freescale/mpc8560ads/law.c @@ -48,7 +48,7 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S index 39819ab..c777eb1 100644 --- a/board/freescale/mpc8568mds/init.S +++ b/board/freescale/mpc8568mds/init.S @@ -140,8 +140,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLBe 3: 64M Non-cacheable, guarded diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index b35bbcd..5e96ea7 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -50,8 +50,8 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(3, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), SET_LAW_ENTRY(6, CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S index adc5115..93654a5 100644 --- a/board/mpc8540eval/init.S +++ b/board/mpc8540eval/init.S @@ -115,8 +115,8 @@ tlb1_entry: .long FSL_BOOKE_MAS0(1,8,0) .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR)) .long FSL_BOOKE_MAS0(1,9,0) .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) diff --git a/board/mpc8540eval/law.c b/board/mpc8540eval/law.c index 4d603f0..273ec5c 100644 --- a/board/mpc8540eval/law.c +++ b/board/mpc8540eval/law.c @@ -45,7 +45,7 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), #ifndef CONFIG_RAM_AS_FLASH SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), #endif diff --git a/board/pm854/init.S b/board/pm854/init.S index f6ea8b3..770daa0 100644 --- a/board/pm854/init.S +++ b/board/pm854/init.S @@ -131,8 +131,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -140,8 +140,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded diff --git a/board/pm854/law.c b/board/pm854/law.c index 65a4b59..cb6b37f 100644 --- a/board/pm854/law.c +++ b/board/pm854/law.c @@ -48,7 +48,7 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), diff --git a/board/pm856/init.S b/board/pm856/init.S index f6ea8b3..770daa0 100644 --- a/board/pm856/init.S +++ b/board/pm856/init.S @@ -131,8 +131,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -140,8 +140,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded diff --git a/board/pm856/law.c b/board/pm856/law.c index 65a4b59..cb6b37f 100644 --- a/board/pm856/law.c +++ b/board/pm856/law.c @@ -48,7 +48,7 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), diff --git a/board/sbc8548/init.S b/board/sbc8548/init.S index 6696dd9..162c326 100644 --- a/board/sbc8548/init.S +++ b/board/sbc8548/init.S @@ -135,8 +135,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -144,8 +144,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index 6bf4199..d903cdc 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -48,7 +48,7 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW_ENTRY(4, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S index e149fbd..3baa506 100644 --- a/board/sbc8560/init.S +++ b/board/sbc8560/init.S @@ -103,8 +103,8 @@ tlb1_entry: .long FSL_BOOKE_MAS0(1,7,0) .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR)) #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) .long FSL_BOOKE_MAS0(1,15,0) diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c index d1c6dc2..e370853 100644 --- a/board/sbc8560/law.c +++ b/board/sbc8560/law.c @@ -53,7 +53,7 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), }; diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S index 9bc8dd6..8e1f16e 100644 --- a/board/stxgp3/init.S +++ b/board/stxgp3/init.S @@ -137,8 +137,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -146,8 +146,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded diff --git a/board/stxgp3/law.c b/board/stxgp3/law.c index 6f215e1..312b3c5 100644 --- a/board/stxgp3/law.c +++ b/board/stxgp3/law.c @@ -48,7 +48,7 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), diff --git a/board/stxssa/init.S b/board/stxssa/init.S index 0c4fb30..d747946 100644 --- a/board/stxssa/init.S +++ b/board/stxssa/init.S @@ -137,8 +137,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -146,8 +146,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded @@ -155,8 +155,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 3, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 4: 256M Non-cacheable, guarded @@ -164,8 +164,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 4, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 5: 64M Non-cacheable, guarded diff --git a/board/stxssa/law.c b/board/stxssa/law.c index 2969060..2b25292 100644 --- a/board/stxssa/law.c +++ b/board/stxssa/law.c @@ -49,8 +49,8 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), /* Map the whole localbus, including flash and reset latch. */ diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S index 1b25deb..f8b9fa2 100644 --- a/board/tqm85xx/init.S +++ b/board/tqm85xx/init.S @@ -119,8 +119,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded @@ -128,8 +128,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 3, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 4: 256M Non-cacheable, guarded diff --git a/board/tqm85xx/law.c b/board/tqm85xx/law.c index 1573e58..224af6c 100644 --- a/board/tqm85xx/law.c +++ b/board/tqm85xx/law.c @@ -45,7 +45,7 @@ struct law_entry law_table[] = { SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), -- cgit v0.10.2 From 44a23cfd6360a68eaa41f945190618a55519eac3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 22:33:22 -0600 Subject: 85xx: Introduce new tlb API Add a set of functions to manipulate TLB entries: * set_tlb() - write a tlb entry * invalidate_tlb() - invalidate a tlb array * disable_tlb() - disable a variable size tlb entry * init_tlbs() - setup initial tlbs based on static table Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index d179d70..2205dca 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a START = start.o resetvec.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \ $(COBJS-y) diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 90c3d44..abc63c4 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1071,19 +1071,9 @@ setup_laws_and_tlbs(unsigned int memsize) ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize * 1024 * 1024) && ram_tlb_index < 16) { - mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); - mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); - mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0)); - mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))); - asm volatile("isync;msync;tlbwe;isync"); - - debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); - debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); - debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0)); - debug("DDR: MAS3=0x%08x\n", - FSL_BOOKE_MAS3(ram_tlb_address, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))); + set_tlb(1, ram_tlb_address, ram_tlb_address, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, ram_tlb_index, tlb_size, 1); ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); ram_tlb_index++; diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c new file mode 100644 index 0000000..b319ad4 --- /dev/null +++ b/cpu/mpc85xx/tlb.c @@ -0,0 +1,95 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +void set_tlb(u8 tlb, u32 epn, u64 rpn, + u8 perms, u8 wimge, + u8 ts, u8 esel, u8 tsize, u8 iprot) +{ + u32 _mas0, _mas1, _mas2, _mas3, _mas7; + + _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); + _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); + _mas2 = FSL_BOOKE_MAS2(epn, wimge); + _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); + _mas7 = rpn >> 32; + + mtspr(MAS0, _mas0); + mtspr(MAS1, _mas1); + mtspr(MAS2, _mas2); + mtspr(MAS3, _mas3); +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr(MAS7, _mas7); +#endif + asm volatile("isync;msync;tlbwe;isync"); +} + +void disable_tlb(u8 esel) +{ + u32 _mas0, _mas1, _mas2, _mas3, _mas7; + + _mas0 = FSL_BOOKE_MAS0(1, esel, 0); + _mas1 = 0; + _mas2 = 0; + _mas3 = 0; + _mas7 = 0; + + mtspr(MAS0, _mas0); + mtspr(MAS1, _mas1); + mtspr(MAS2, _mas2); + mtspr(MAS3, _mas3); +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr(MAS7, _mas7); +#endif + asm volatile("isync;msync;tlbwe;isync"); +} + +void invalidate_tlb(u8 tlb) +{ + if (tlb == 0) + mtspr(MMUCSR0, 0x4); + if (tlb == 1) + mtspr(MMUCSR0, 0x2); +} + +void init_tlbs(void) +{ +#ifdef CONFIG_FSL_INIT_TLBS + int i; + + for (i = 0; i < num_tlb_entries; i++) { + set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn, + tlb_table[i].perms, tlb_table[i].wimge, + tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize, + tlb_table[i].iprot); + } +#endif + + return ; +} + diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 45a4764..ec1ca53 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -418,6 +418,37 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_256GB 14 #define BOOKE_PAGESZ_1TB 15 +#ifdef CONFIG_E500 +#ifndef __ASSEMBLY__ +extern void set_tlb(u8 tlb, u32 epn, u64 rpn, + u8 perms, u8 wimge, + u8 ts, u8 esel, u8 tsize, u8 iprot); +extern void disable_tlb(u8 esel); +extern void invalidate_tlb(u8 tlb); +extern void init_tlbs(void); + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ + { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \ + .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot } + +struct fsl_e_tlb_entry { + u8 tlb; + u32 epn; + u64 rpn; + u8 perms; + u8 wimge; + u8 ts; + u8 esel; + u8 tsize; + u8 iprot; +}; + +extern struct fsl_e_tlb_entry tlb_table[]; +extern int num_tlb_entries; +#endif +#endif + #if defined(CONFIG_MPC86xx) #define LAWBAR_BASE_ADDR 0x00FFFFFF #define LAWAR_TRGT_IF 0x01F00000 -- cgit v0.10.2 From 8716318057a5f60ab1ba081ece2dbe82ae00e1ee Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 22:38:34 -0600 Subject: 85xx: Reworked initial processor init Reworked the initial processor initialzation sequence: * introduced cpu_early_init_f that is run in address space 1 (AS=1) * Moved TLB/LAW and CCSR init into cpu_early_init_f() * Reworked initial asm code to do most of the core init before TLBs The main reasons for these changes are to allow handling of 36-bit phys addresses in the future and some of the issues that will exist when we do that. There are a few caveats on what can be initialized via the LAW and TLB static tables: * TLB entry 14/15 can't be initialized via the TLB table * any LAW that covers the implicit boot window (4G-8M to 4G) must map to the code that is currently executing. Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 9a65142..4e2bfe7 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -31,6 +31,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -123,6 +124,54 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) } #endif +/* We run cpu_init_early_f in AS = 1 */ +void cpu_init_early_f(void) +{ + set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 1, 0, BOOKE_PAGESZ_4K, 0); + + /* set up CCSR if we want it moved */ +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + { + u32 temp; + + set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 1, 1, BOOKE_PAGESZ_4K, 0); + + temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); + out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12); + + temp = in_be32((volatile u32 *)CFG_CCSRBAR); + } +#endif + + init_laws(); + invalidate_tlb(0); +#ifdef CONFIG_FSL_INIT_TLBS + init_tlbs(); +#else + { + extern u32 tlb1_entry; + u32 *tmp = &tlb1_entry; + int i; + int num = tmp[2]; + + /* skip to actual table */ + tmp += 3; + + for (i = 0; i < num; i++, tmp += 4) { + mtspr(MAS0, tmp[0]); + mtspr(MAS1, tmp[1]); + mtspr(MAS2, tmp[2]); + mtspr(MAS3, tmp[3]); + asm volatile("isync;msync;tlbwe;isync"); + } + } +#endif +} + /* * Breathe some life into the CPU... * @@ -135,16 +184,15 @@ void cpu_init_f (void) volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); + disable_tlb(14); + disable_tlb(15); + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); -#ifdef CONFIG_FSL_LAW - init_laws(); -#endif - #ifdef CONFIG_CPM2 config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); #endif diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 2044722..e8e5eb2 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -143,68 +143,8 @@ _start_e500: li r1,0x0f00 mtspr IVOR15,r1 /* 15: Debug */ - - /* - * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. - * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB - * region before we can access any CCSR registers such as L2 - * registers, Local Access Registers,etc. We will also re-allocate - * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup. - * - * Please refer to board-specif directory for TLB1 entry configuration. - * (e.g. board//init.S) - * - */ - bl tlb1_entry - mr r5,r0 - lwzu r4,0(r5) /* how many TLB1 entries we actually use */ - mtctr r4 - -0: lwzu r6,4(r5) - lwzu r7,4(r5) - lwzu r8,4(r5) - lwzu r9,4(r5) - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - isync - msync - tlbwe - isync - bdnz 0b - -1: -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* Special sequence needed to update CCSRBAR itself */ - lis r4,CFG_CCSRBAR_DEFAULT@h - ori r4,r4,CFG_CCSRBAR_DEFAULT@l - - lis r5,CFG_CCSRBAR@h - ori r5,r5,CFG_CCSRBAR@l - srwi r6,r5,12 - stw r6,0(r4) - isync - - lis r5,0xffff - ori r5,r5,0xf000 - lwz r5,0(r5) - isync - - lis r3,CFG_CCSRBAR@h - lwz r5,CFG_CCSRBAR@l(r3) - isync -#endif - - - /* set up local access windows, defined at board//init.S */ - lis r7,CFG_CCSRBAR@h - ori r7,r7,CFG_CCSRBAR@l - /* Clear and set up some registers. */ - li r0,0 - mtmsr r0 - li r0,0x0000 + li r0,0x0000 lis r1,0xffff mtspr DEC,r0 /* prevent dec exceptions */ mttbl r0 /* prevent fit & wdt exceptions */ @@ -214,18 +154,13 @@ _start_e500: mtspr ESR,r0 /* clear exception syndrome register */ mtspr MCSR,r0 /* machine check syndrome register */ mtxer r0 /* clear integer exception register */ - lis r1,0x0002 /* set CE bit (Critical Exceptions) */ - ori r1,r1,0x1200 /* set ME/DE bit */ - mtmsr r1 /* change MSR */ - isync /* Enable Time Base and Select Time Base Clock */ lis r0,HID0_EMCP@h /* Enable machine check */ #if defined(CONFIG_ENABLE_36BIT_PHYS) - ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */ -#else - ori r0,r0,HID0_TBEN@l /* enable Timebase */ + ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ #endif + ori r0,r0,HID0_TBEN@l /* Enable Timebase */ mtspr HID0,r0 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ @@ -246,6 +181,58 @@ _start_e500: mtspr DBCR0,r0 #endif + /* create a temp mapping in AS=1 to the boot window */ + lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l + + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l + + lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe + + /* create a temp mapping in AS=1 to the stack */ + lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l + + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l + + lis r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@h + ori r8,r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@l + + lis r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe + + lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h + ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l + lis r7,switch_as@h + ori r7,r7,switch_as@l + + mtspr SPRN_SRR0,r7 + mtspr SPRN_SRR1,r6 + rfi + +switch_as: /* L1 DCache is used for initial RAM */ /* Allocate Initial RAM in data cache. @@ -305,6 +292,14 @@ _start_cont: stw r0,+12(r1) /* Save return addr (underflow vect) */ GET_GOT + bl cpu_init_early_f + + /* switch back to AS = 0 */ + lis r3,(MSR_CE|MSR_ME|MSR_DE)@h + ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l + mtmsr r3 + isync + bl cpu_init_f bl board_init_f isync -- cgit v0.10.2 From 0f7a3dc95cbff3c21bd6dbc639313796412bbbab Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Jan 2008 23:11:57 -0600 Subject: 85xx: Convert MPC8544 DS to new TLB setup Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 665251d..53368b2 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -26,9 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o - -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S deleted file mode 100644 index 3918176..0000000 --- a/board/freescale/mpc8544ds/init.S +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long (2f-1f)/16 -1: - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB0 16K Cacheable, guarded - * Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 1G Non-cacheable, guarded - * 0x80000000 1G PCIE 8,9,a,b - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long FSL_BOOKE_MAS2(CFG_PCIE_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCIE_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe100_0000 255M PCI IO range - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#ifdef CFG_LBC_CACHE_BASE - /* - * TLB 5: 64M Cacheable, non-guarded - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -2: - entry_end diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c new file mode 100644 index 0000000..34cfb38 --- /dev/null +++ b/board/freescale/mpc8544ds/tlb.c @@ -0,0 +1,99 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + /* + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 1G PCIE 8,9,a,b + */ + SET_TLB_ENTRY(1, CFG_PCIE_PHYS, CFG_PCIE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1G, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_PCI_PHYS + 0x10000000, CFG_PCI_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe100_0000 255M PCI IO range + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_64M, 1), + +#ifdef CFG_LBC_CACHE_BASE + /* + * TLB 5: 64M Cacheable, non-guarded + */ + SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_64M, 1), +#endif + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF + */ + SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds index 66bd4b6..17db8c0 100644 --- a/board/freescale/mpc8544ds/u-boot.lds +++ b/board/freescale/mpc8544ds/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8544ds/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8544ds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index a894209..1269c8a 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -43,6 +43,7 @@ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -- cgit v0.10.2 From 80d0b6a1498761c4355b2db9c8001b04c295e7b8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 00:32:17 -0600 Subject: 85xx: Convert ATUM8548 to new TLB setup Signed-off-by: Kumar Gala diff --git a/board/atum8548/Makefile b/board/atum8548/Makefile index bf0830c..ac4e5838 100644 --- a/board/atum8548/Makefile +++ b/board/atum8548/Makefile @@ -29,9 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o - -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/atum8548/init.S b/board/atum8548/init.S deleted file mode 100644 index 7e161c1..0000000 --- a/board/atum8548/init.S +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright 2007 - * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com - * Copyright 2004, 2007 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long (2f-1f)/16 - -1: -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, guarded - * Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, MAS2_G) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, MAS2_G) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, MAS2_G) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, MAS2_G) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* TLB 1 Initializations */ - /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x4000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x4000000, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 1G Non-cacheable, guarded - * 0x80000000 1G PCI1/PCIE 8,9,a,b - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3, 4: 512M Non-cacheable, guarded - * 0xc0000000 1G PCI2 - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 1M PCI1 IO - * 0xe210_0000 1M PCI2 IO - * 0xe300_0000 1M PCIe IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -2: - entry_end diff --git a/board/atum8548/tlb.c b/board/atum8548/tlb.c new file mode 100644 index 0000000..bb6ce76 --- /dev/null +++ b/board/atum8548/tlb.c @@ -0,0 +1,90 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 Initializations */ + /* + * TLB 0, 1: 128M Non-cacheable, guarded + * 0xf8000000 128M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 2: 1G Non-cacheable, guarded + * 0x80000000 1G PCI1/PCIE 8,9,a,b + */ + SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1G, 1), + + /* + * TLB 3, 4: 512M Non-cacheable, guarded + * 0xc0000000 1G PCI2 + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 1M PCI1 IO + * 0xe210_0000 1M PCI2 IO + * 0xe300_0000 1M PCIe IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/atum8548/u-boot.lds b/board/atum8548/u-boot.lds index 0d1c217..3f04cae 100644 --- a/board/atum8548/u-boot.lds +++ b/board/atum8548/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/atum8548/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/atum8548/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index c14376e..c2dde41 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -64,6 +64,7 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ -- cgit v0.10.2 From 219a81b98d834f9071b6f7c3bdc6b7ec39cc46cc Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 00:52:29 -0600 Subject: 85xx: Convert MPC8540/MPC8560 ADS to new TLB setup Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile index 0c8f470..be24388 100644 --- a/board/freescale/mpc8540ads/Makefile +++ b/board/freescale/mpc8540ads/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S deleted file mode 100644 index 4c8dd0e..0000000 --- a/board/freescale/mpc8540ads/init.S +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4*1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8*1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12*1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) - .long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - .long FSL_BOOKE_MAS0(1, 8, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1, 9, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - entry_end diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c new file mode 100644 index 0000000..3eaff01 --- /dev/null +++ b/board/freescale/mpc8540ads/tlb.c @@ -0,0 +1,130 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xf8000000 16K BCSR registers + */ + SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_16K, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_64M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds index bc0db55..86f8f13 100644 --- a/board/freescale/mpc8540ads/u-boot.lds +++ b/board/freescale/mpc8540ads/u-boot.lds @@ -35,7 +35,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8540ads/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -65,7 +64,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8540ads/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile index 0c8f470..be24388 100644 --- a/board/freescale/mpc8560ads/Makefile +++ b/board/freescale/mpc8560ads/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S deleted file mode 100644 index 8ade9ca..0000000 --- a/board/freescale/mpc8560ads/init.S +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) - .long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - .long FSL_BOOKE_MAS0(1, 8, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1, 9, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - entry_end diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c new file mode 100644 index 0000000..3eaff01 --- /dev/null +++ b/board/freescale/mpc8560ads/tlb.c @@ -0,0 +1,130 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xf8000000 16K BCSR registers + */ + SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_16K, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_64M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds index 96af2b1..e2474e5 100644 --- a/board/freescale/mpc8560ads/u-boot.lds +++ b/board/freescale/mpc8560ads/u-boot.lds @@ -35,7 +35,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8560ads/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -65,7 +64,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8560ads/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5ea7b25..74076fb 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -56,6 +56,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 08884b3..84c517f 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -53,6 +53,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * sysclk for MPC85xx -- cgit v0.10.2 From 0db37dc2eed30884db2daa24dbd9a113b5d00610 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 01:01:09 -0600 Subject: 85xx: Convert MPC8541/MPC8555/MPC8548 CDS to new TLB setup Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile index 5497708..d1a585a 100644 --- a/board/freescale/mpc8541cds/Makefile +++ b/board/freescale/mpc8541cds/Makefile @@ -29,14 +29,12 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o \ +COBJS := $(BOARD).o law.o tlb.o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ ../common/via.o -SOBJS := init.o - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S deleted file mode 100644 index 6e93fb0..0000000 --- a/board/freescale/mpc8541cds/init.S +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - entry_end diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c new file mode 100644 index 0000000..92f759b --- /dev/null +++ b/board/freescale/mpc8541cds/tlb.c @@ -0,0 +1,112 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8541cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds index 1e490d0..1cbadf2 100644 --- a/board/freescale/mpc8541cds/u-boot.lds +++ b/board/freescale/mpc8541cds/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8541cds/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8541cds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile index 5497708..d1a585a 100644 --- a/board/freescale/mpc8548cds/Makefile +++ b/board/freescale/mpc8548cds/Makefile @@ -29,14 +29,12 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o \ +COBJS := $(BOARD).o law.o tlb.o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ ../common/via.o -SOBJS := init.o - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S deleted file mode 100644 index 51e1cc4..0000000 --- a/board/freescale/mpc8548cds/init.S +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright 2004, 2007 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long (2f-1f)/16 - -1: -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, guarded - * Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 1G Non-cacheable, guarded - * 0x80000000 1G PCI1/PCIE 8,9,a,b - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#ifdef CFG_RIO_MEM_PHYS - /* - * TLB 2: 256M Non-cacheable, guarded - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 1M PCI1 IO - * 0xe210_0000 1M PCI2 IO - * 0xe300_0000 1M PCIe IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 64M Non-cacheable, guarded - * 0xf8000000 64M CADMUS registers, relocated L2SRAM - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -2: - entry_end diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c new file mode 100644 index 0000000..b21f71b --- /dev/null +++ b/board/freescale/mpc8548cds/tlb.c @@ -0,0 +1,104 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 1G PCI1/PCIE 8,9,a,b + */ + SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1G, 1), + +#ifdef CFG_RIO_MEM_PHYS + /* + * TLB 2: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), +#endif + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 1M PCI1 IO + * 0xe210_0000 1M PCI2 IO + * 0xe300_0000 1M PCIe IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 64M Non-cacheable, guarded + * 0xf8000000 64M CADMUS registers, relocated L2SRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_64M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds index acf25e3..d701096 100644 --- a/board/freescale/mpc8548cds/u-boot.lds +++ b/board/freescale/mpc8548cds/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8548cds/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8548cds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile index 5497708..d1a585a 100644 --- a/board/freescale/mpc8555cds/Makefile +++ b/board/freescale/mpc8555cds/Makefile @@ -29,14 +29,12 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o \ +COBJS := $(BOARD).o law.o tlb.o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ ../common/via.o -SOBJS := init.o - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S deleted file mode 100644 index 6e93fb0..0000000 --- a/board/freescale/mpc8555cds/init.S +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - entry_end diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c new file mode 100644 index 0000000..92f759b --- /dev/null +++ b/board/freescale/mpc8555cds/tlb.c @@ -0,0 +1,112 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8555cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds index e9fa51e..1cbadf2 100644 --- a/board/freescale/mpc8555cds/u-boot.lds +++ b/board/freescale/mpc8555cds/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8555cds/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8555cds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 7334088..92195ed 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -48,6 +48,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a3db9f4..77bcc29 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -56,6 +56,7 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 93877ae..e7b9694 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -48,6 +48,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, -- cgit v0.10.2 From 73aa9ac2b46f1cfd039106ebd6b9865016005234 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 01:12:22 -0600 Subject: 85xx: Convert MPC8568 MDS to new TLB setup Signed-off-by: Kumar Gala diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile index ef78942..d9f20f9 100644 --- a/board/freescale/mpc8568mds/Makefile +++ b/board/freescale/mpc8568mds/Makefile @@ -29,9 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o bcsr.o law.o - -SOBJS := init.o +COBJS := $(BOARD).o bcsr.o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S deleted file mode 100644 index c777eb1..0000000 --- a/board/freescale/mpc8568mds/init.S +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long (2f-1f)/16 - -1: -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* TLB 1 Initializations */ - /* - * TLBe 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH (upper half) - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x1000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x1000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLBe 1: 16M Non-cacheable, guarded - * 0xfe000000 16M FLASH (lower half) - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLBe 2: 1G Non-cacheable, guarded - * 0x80000000 512M PCI1 MEM - * 0xa0000000 512M PCIe MEM - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLBe 3: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 8M PCI1 IO - * 0xe280_0000 8M PCIe IO - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLBe 4: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLBe 5: 256K Non-cacheable, guarded - * 0xf8000000 32K BCSR - * 0xf8008000 32K PIB (CS4) - * 0xf8010000 32K PIB (CS5) - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K) - .long FSL_BOOKE_MAS2(CFG_BCSR_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BCSR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -2: - entry_end diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c new file mode 100644 index 0000000..225fc94 --- /dev/null +++ b/board/freescale/mpc8568mds/tlb.c @@ -0,0 +1,100 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 Initializations */ + /* + * TLBe 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH (upper half) + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x1000000, CFG_FLASH_BASE + 0x1000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLBe 1: 16M Non-cacheable, guarded + * 0xfe000000 16M FLASH (lower half) + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* + * TLBe 2: 1G Non-cacheable, guarded + * 0x80000000 512M PCI1 MEM + * 0xa0000000 512M PCIe MEM + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1G, 1), + + /* + * TLBe 3: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 8M PCI1 IO + * 0xe280_0000 8M PCIe IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_64M, 1), + + /* + * TLBe 4: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 4, BOOKE_PAGESZ_64M, 1), + + /* + * TLBe 5: 256K Non-cacheable, guarded + * 0xf8000000 32K BCSR + * 0xf8008000 32K PIB (CS4) + * 0xf8010000 32K PIB (CS5) + */ + SET_TLB_ENTRY(1, CFG_BCSR_BASE, CFG_BCSR_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds index 7917409..6b30f15 100644 --- a/board/freescale/mpc8568mds/u-boot.lds +++ b/board/freescale/mpc8568mds/u-boot.lds @@ -37,7 +37,6 @@ SECTIONS .bootpg 0xFFFFF000: { cpu/mpc85xx/start.o (.bootpg) - board/freescale/mpc8568mds/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -67,7 +66,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/freescale/mpc8568mds/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a12d193..04f442f 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -50,6 +50,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, -- cgit v0.10.2 From ff4681c9285b2b4d24552a19cacc1769fe2fc7e0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 01:25:33 -0600 Subject: 85xx: Convert MPC8540EVAL to new TLB setup Signed-off-by: Kumar Gala diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile index c892247..28d6cb9 100644 --- a/board/mpc8540eval/Makefile +++ b/board/mpc8540eval/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o law.o -SOBJS := init.o +COBJS := $(BOARD).o flash.o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S deleted file mode 100644 index 93654a5..0000000 --- a/board/mpc8540eval/init.S +++ /dev/null @@ -1,137 +0,0 @@ -/* -* Copyright (C) 2002,2003, Motorola Inc. -* Xianghua Xiao -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include -#include - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -/* TLB1 entries configuration: */ - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - .long 0x0a /* the following data table uses a few of 16 TLB entries */ - - .long FSL_BOOKE_MAS0(1,1,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - #if defined(CFG_FLASH_PORT_WIDTH_16) - .long FSL_BOOKE_MAS0(1,2,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,3,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x400000,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x400000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #else - .long FSL_BOOKE_MAS0(1,2,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,3,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #endif - - #if !defined(CONFIG_SPD_EEPROM) - .long FSL_BOOKE_MAS0(1,4,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,5,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x4000000,0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x4000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #else - .long FSL_BOOKE_MAS0(1,4,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,5,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #endif - - .long FSL_BOOKE_MAS0(1,6,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - #if defined(CONFIG_RAM_AS_FLASH) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,(MAS2_I|MAS2_G)) - #else - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,0) - #endif - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,7,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) - #ifdef CONFIG_L2_INIT_RAM - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0) - #else - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0) - #endif - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,8,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,9,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) - .long FSL_BOOKE_MAS2(CFG_BCSR,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_BCSR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - .long FSL_BOOKE_MAS0(1,15,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #else - .long FSL_BOOKE_MAS0(1,15,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - #endif - entry_end diff --git a/board/mpc8540eval/tlb.c b/board/mpc8540eval/tlb.c new file mode 100644 index 0000000..f041236 --- /dev/null +++ b/board/mpc8540eval/tlb.c @@ -0,0 +1,78 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + #if defined(CFG_FLASH_PORT_WIDTH_16) + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_4M, 1), + SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x400000, CFG_FLASH_BASE + 0x400000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_4M, 1), + #else + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_16M, 1), + #endif + + #if !defined(CONFIG_SPD_EEPROM) + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 4, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_64M, 1), + #endif + + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + #if defined(CONFIG_RAM_AS_FLASH) + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + #else + MAS3_SX|MAS3_SW|MAS3_SR, 0, + #endif + 0, 6, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16K, 1), + + SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_16K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/mpc8540eval/u-boot.lds b/board/mpc8540eval/u-boot.lds index 4b342c7..9bbba30 100644 --- a/board/mpc8540eval/u-boot.lds +++ b/board/mpc8540eval/u-boot.lds @@ -56,7 +56,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/mpc8540eval/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) @@ -143,7 +142,6 @@ SECTIONS .bootpg : { cpu/mpc85xx/start.o (.bootpg) - board/mpc8540eval/init.o (.bootpg) } = 0xffff . = (. & 0xFFF80000) + 0x0007FFFC; diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index bf64f27..416cee4 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -44,6 +44,7 @@ #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* Using Localbus SDRAM to emulate flash before we can program the flash, * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. -- cgit v0.10.2 From 818218bac6a11591e2542c344d2330e0f4e1968b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 01:31:34 -0600 Subject: 85xx: Convert PM854/PM856 to new TLB setup Signed-off-by: Kumar Gala diff --git a/board/pm854/Makefile b/board/pm854/Makefile index 0c8f470..be24388 100644 --- a/board/pm854/Makefile +++ b/board/pm854/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/pm854/init.S b/board/pm854/init.S deleted file mode 100644 index 770daa0..0000000 --- a/board/pm854/init.S +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M FLASH (8,16,32 or 64 MB) - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - entry_end diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c new file mode 100644 index 0000000..5d87537 --- /dev/null +++ b/board/pm854/tlb.c @@ -0,0 +1,117 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH (8,16,32 or 64 MB) + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 7: 256M DDR + * 0x00000000 256M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_256M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pm854/u-boot.lds b/board/pm854/u-boot.lds index 9feaf55..86f8f13 100644 --- a/board/pm854/u-boot.lds +++ b/board/pm854/u-boot.lds @@ -35,7 +35,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/pm854/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -65,7 +64,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/pm854/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/pm856/Makefile b/board/pm856/Makefile index 0c8f470..be24388 100644 --- a/board/pm856/Makefile +++ b/board/pm856/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/pm856/init.S b/board/pm856/init.S deleted file mode 100644 index 770daa0..0000000 --- a/board/pm856/init.S +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M FLASH (8,16,32 or 64 MB) - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - entry_end diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c new file mode 100644 index 0000000..5d87537 --- /dev/null +++ b/board/pm856/tlb.c @@ -0,0 +1,117 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH (8,16,32 or 64 MB) + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 7: 256M DDR + * 0x00000000 256M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_256M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pm856/u-boot.lds b/board/pm856/u-boot.lds index c68f05a..6cfddea 100644 --- a/board/pm856/u-boot.lds +++ b/board/pm856/u-boot.lds @@ -36,7 +36,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/pm856/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -66,7 +65,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/pm856/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 819bee7..d881057 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -52,6 +52,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 8902f42..48bbef6 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -52,6 +52,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * sysclk for MPC85xx -- cgit v0.10.2 From 143b518d9125b54f96f1d7f1afc640b8aae81ff0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 01:44:34 -0600 Subject: 85xx: Convert SBC8540/SBC8560/SBC8548 to new TLB setup Signed-off-by: Kumar Gala diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index c346fdf..4b2a9f6 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -28,8 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/sbc8548/init.S b/board/sbc8548/init.S deleted file mode 100644 index 162c326..0000000 --- a/board/sbc8548/init.S +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright 2007 Wind River Systemes, Inc. - * Copyright 2007 Embedded Specialties, Inc. - * - * Copyright 2004 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - .section .bootpg, "ax" - .globl tlb1_entry - -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xe4010000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff800000 16M TLB for 8MB FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, - (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Cacheable, non-guarded - * 0x0 256M DDR SDRAM - */ - #if !defined(CONFIG_SPD_EEPROM) - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - #endif - - /* - * TLB 4: 64M Non-cacheable, guarded - * 0xe0000000 1M CCSRBAR - * 0xe2000000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Cacheable, non-guarded - * 0xf0000000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 16M Cacheable, non-guarded - * 0xf8000000 1M 7-segment LED display - * 0xf8100000 1M User switches - * 0xf8300000 1M Board revision - * 0xf8b00000 1M EEPROM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_EPLD_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - entry_end diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c new file mode 100644 index 0000000..8d6625e --- /dev/null +++ b/board/sbc8548/tlb.c @@ -0,0 +1,108 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff800000 16M TLB for 8MB FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Cacheable, non-guarded + * 0x0 256M DDR SDRAM + */ + #if !defined(CONFIG_SPD_EEPROM) + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 3, BOOKE_PAGESZ_256M, 1), + #endif + + /* + * TLB 4: 64M Non-cacheable, guarded + * 0xe0000000 1M CCSRBAR + * 0xe2000000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 5: 64M Cacheable, non-guarded + * 0xf0000000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 16M Cacheable, non-guarded + * 0xf8000000 1M 7-segment LED display + * 0xf8100000 1M User switches + * 0xf8300000 1M Board revision + * 0xf8b00000 1M EEPROM + */ + SET_TLB_ENTRY(1, CFG_EPLD_BASE, CFG_EPLD_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/sbc8548/u-boot.lds b/board/sbc8548/u-boot.lds index 8e301d4..d701096 100644 --- a/board/sbc8548/u-boot.lds +++ b/board/sbc8548/u-boot.lds @@ -34,7 +34,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/sbc8548/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -64,7 +63,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/sbc8548/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile index c346fdf..4b2a9f6 100644 --- a/board/sbc8560/Makefile +++ b/board/sbc8560/Makefile @@ -28,8 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S deleted file mode 100644 index 3baa506..0000000 --- a/board/sbc8560/init.S +++ /dev/null @@ -1,120 +0,0 @@ -/* -* Copyright (C) 2002,2003, Motorola Inc. -* Xianghua Xiao -* -* (C) Copyright 2004 Wind River Systems Inc . -* Added support for Wind River SBC8560 board -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include -#include - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -/* TLB1 entries configuration: */ - - .section .bootpg, "ax" - .globl tlb1_entry - -tlb1_entry: - entry_start - - .long 0x08 /* the following data table uses a few of 16 TLB entries */ - -/* TLB for CCSRBAR (IMMR) */ - - .long FSL_BOOKE_MAS0(1,1,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - -/* TLB for Local Bus stuff, just map the whole 512M */ -/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ - - .long FSL_BOOKE_MAS0(1,2,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(0xe0000000,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(0xe0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,3,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(0xf0000000,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(0xf0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - .long FSL_BOOKE_MAS0(1,4,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,5,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000,0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) -#else - .long FSL_BOOKE_MAS0(1,4,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,5,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - .long FSL_BOOKE_MAS0(1,6,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) -#ifdef CONFIG_L2_INIT_RAM - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0) -#else - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0) -#endif - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1,7,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR)) - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - .long FSL_BOOKE_MAS0(1,15,0) - .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR)) -#else - .long FSL_BOOKE_MAS0(1,15,0) - .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long FSL_BOOKE_MAS2(0,0) - .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - entry_end diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c new file mode 100644 index 0000000..155ff64 --- /dev/null +++ b/board/sbc8560/tlb.c @@ -0,0 +1,65 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { +/* TLB for CCSRBAR (IMMR) */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +/* TLB for Local Bus stuff, just map the whole 512M */ +/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ + + SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + +#if !defined(CONFIG_SPD_EEPROM) + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif + + SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_16K, 1), + + SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds index 449fed8..f3dbf26 100644 --- a/board/sbc8560/u-boot.lds +++ b/board/sbc8560/u-boot.lds @@ -38,7 +38,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/sbc8560/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -68,7 +67,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/sbc8560/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 2bbfe9a..322b5fa 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -57,6 +57,7 @@ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 0a7a904..9c80a79 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -57,6 +57,7 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index f9ede5f..7761f51 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -51,6 +51,7 @@ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE -- cgit v0.10.2 From 74121b470c14f7eaf284ee838bffca6f9521069e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 01:56:32 -0600 Subject: 85xx: Convert STXGP3 & STXSSA to new TLB setup Signed-off-by: Kumar Gala diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile index c892247..28d6cb9 100644 --- a/board/stxgp3/Makefile +++ b/board/stxgp3/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o law.o -SOBJS := init.o +COBJS := $(BOARD).o flash.o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S deleted file mode 100644 index 8e1f16e..0000000 --- a/board/stxgp3/init.S +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (C) 2004 Embedded Edge, LLC - * Dan Malek - * Copied from ADS85xx. - * Updates for Silicon Tx GP3 8560. We only support 32-bit flash - * and DDR with SPD EEPROM configuration. - * - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xfc000000 16K Configuration Latch register - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K) - .long FSL_BOOKE_MAS2(CFG_LBC_LCLDEVS_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_LBC_LCLDEVS_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - .long FSL_BOOKE_MAS0(1, 8, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(1, 9, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#endif - - entry_end diff --git a/board/stxgp3/tlb.c b/board/stxgp3/tlb.c new file mode 100644 index 0000000..529f230 --- /dev/null +++ b/board/stxgp3/tlb.c @@ -0,0 +1,130 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xfc000000 16K Configuration Latch register + */ + SET_TLB_ENTRY(1, CFG_LBC_LCLDEVS_BASE, CFG_LBC_LCLDEVS_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_16K, 1), + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_64M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds index 3f9bc55..4a9a103 100644 --- a/board/stxgp3/u-boot.lds +++ b/board/stxgp3/u-boot.lds @@ -40,7 +40,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/stxgp3/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -70,7 +69,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/stxgp3/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) diff --git a/board/stxssa/Makefile b/board/stxssa/Makefile index c43dd4e..f1f5d0b 100644 --- a/board/stxssa/Makefile +++ b/board/stxssa/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o -SOBJS := init.o +COBJS := $(BOARD).o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/stxssa/init.S b/board/stxssa/init.S deleted file mode 100644 index d747946..0000000 --- a/board/stxssa/init.S +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2005 Embedded Alley Solutions, Inc. - * Dan Malek - * Copied from STx GP3. - * Updates for Silicon Tx GP3 SSA. We only support 32-bit flash - * and DDR with SPD EEPROM configuration. - * - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 12 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 6M4 FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 256M Non-cacheable, guarded - * 0xf0000000 Local bus expansion option. - * 0xfb000000 Configuration Latch register (one word) - * 0xfc000000 Up to 64M flash - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_LBC_OPTION_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_LBC_OPTION_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - entry_end diff --git a/board/stxssa/tlb.c b/board/stxssa/tlb.c new file mode 100644 index 0000000..46b1440 --- /dev/null +++ b/board/stxssa/tlb.c @@ -0,0 +1,106 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 6M4 FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 6: 256M Non-cacheable, guarded + * 0xf0000000 Local bus expansion option. + * 0xfb000000 Configuration Latch register (one word) + * 0xfc000000 Up to 64M flash + */ + SET_TLB_ENTRY(1, CFG_LBC_OPTION_BASE, CFG_LBC_OPTION_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds index a0ba125..99a8a8b 100644 --- a/board/stxssa/u-boot.lds +++ b/board/stxssa/u-boot.lds @@ -40,7 +40,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/stxssa/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -70,7 +69,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/stxssa/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 047e1cf..d6d4c46 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -52,6 +52,7 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* sysclk for MPC85xx */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index e09dd71..21fb6f6 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -52,6 +52,7 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* sysclk for MPC85xx */ -- cgit v0.10.2 From 3b558e26a5ef31635787d6d6e97d70939d4f892d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 02:02:10 -0600 Subject: 85xx: Convert TQM85xx to new TLB setup Signed-off-by: Kumar Gala diff --git a/board/tqm85xx/Makefile b/board/tqm85xx/Makefile index 66f2830..52f5ef9 100644 --- a/board/tqm85xx/Makefile +++ b/board/tqm85xx/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o sdram.o law.o -SOBJS := init.o +COBJS := $(BOARD).o sdram.o law.o tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S deleted file mode 100644 index f8b9fa2..0000000 --- a/board/tqm85xx/init.S +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - .long FSL_BOOKE_MAS0(0, 0, 0) - .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) - .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) - .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - - /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH - * Out of reset this entry is only 4K. - */ - .long FSL_BOOKE_MAS0(1, 1, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - .long FSL_BOOKE_MAS0(1, 0, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x4000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long FSL_BOOKE_MAS0(1, 2, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 3, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long FSL_BOOKE_MAS0(1, 4, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long FSL_BOOKE_MAS0(1, 5, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long FSL_BOOKE_MAS0(1, 6, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - /* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - .long FSL_BOOKE_MAS0(1, 7, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - .long FSL_BOOKE_MAS0(1, 8, 0) - .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) - - entry_end diff --git a/board/tqm85xx/tlb.c b/board/tqm85xx/tlb.c new file mode 100644 index 0000000..a178cfe --- /dev/null +++ b/board/tqm85xx/tlb.c @@ -0,0 +1,114 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + + /* + * TLB 0, 1: 128M Non-cacheable, guarded + * 0xf8000000 128M FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7+8: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/tqm85xx/u-boot.lds b/board/tqm85xx/u-boot.lds index a8ca3c8..6c1f904 100644 --- a/board/tqm85xx/u-boot.lds +++ b/board/tqm85xx/u-boot.lds @@ -35,7 +35,6 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) - board/tqm85xx/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -65,7 +64,6 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) - board/tqm85xx/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index dd0654b..e2e9964 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -51,6 +51,7 @@ #endif #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * sysclk for MPC85xx -- cgit v0.10.2 From 7dc358bb0de9e2fa341f3b4c914466b1f34b2d89 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Jan 2008 02:19:18 -0600 Subject: 85xx: Get ride of old TLB setup code Now that all boards have been converted, remove old config code and the config option for the new style. Signed-off-by: Kumar Gala diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 4e2bfe7..c0ff1d5 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -149,27 +149,7 @@ void cpu_init_early_f(void) init_laws(); invalidate_tlb(0); -#ifdef CONFIG_FSL_INIT_TLBS init_tlbs(); -#else - { - extern u32 tlb1_entry; - u32 *tmp = &tlb1_entry; - int i; - int num = tmp[2]; - - /* skip to actual table */ - tmp += 3; - - for (i = 0; i < num; i++, tmp += 4) { - mtspr(MAS0, tmp[0]); - mtspr(MAS1, tmp[1]); - mtspr(MAS2, tmp[2]); - mtspr(MAS3, tmp[3]); - asm volatile("isync;msync;tlbwe;isync"); - } - } -#endif } /* diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index b319ad4..b2c799a 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -79,7 +79,6 @@ void invalidate_tlb(u8 tlb) void init_tlbs(void) { -#ifdef CONFIG_FSL_INIT_TLBS int i; for (i = 0; i < num_tlb_entries; i++) { @@ -88,7 +87,6 @@ void init_tlbs(void) tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize, tlb_table[i].iprot); } -#endif return ; } diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index c2dde41..c14376e 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -64,7 +64,6 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 74076fb..5ea7b25 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -56,7 +56,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 416cee4..bf64f27 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -44,7 +44,6 @@ #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* Using Localbus SDRAM to emulate flash before we can program the flash, * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 92195ed..7334088 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -48,7 +48,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 1269c8a..a894209 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -43,7 +43,6 @@ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 77bcc29..a3db9f4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -56,7 +56,6 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index e7b9694..93877ae 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -48,7 +48,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 84c517f..08884b3 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -53,7 +53,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 04f442f..a12d193 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -50,7 +50,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * When initializing flash, if we cannot find the manufacturer ID, diff --git a/include/configs/PM854.h b/include/configs/PM854.h index d881057..819bee7 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -52,7 +52,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 48bbef6..8902f42 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -52,7 +52,6 @@ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 322b5fa..2bbfe9a 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -57,7 +57,6 @@ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index e2e9964..dd0654b 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -51,7 +51,6 @@ #endif #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* * sysclk for MPC85xx diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 9c80a79..0a7a904 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -57,7 +57,6 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 7761f51..f9ede5f 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -51,7 +51,6 @@ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index d6d4c46..047e1cf 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -52,7 +52,6 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* sysclk for MPC85xx */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 21fb6f6..e09dd71 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -52,7 +52,6 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */ /* sysclk for MPC85xx */ -- cgit v0.10.2