From c53711bb6289a5ac2d909dfe626e6a3cb9b23bfe Mon Sep 17 00:00:00 2001 From: Wang Dongsheng Date: Wed, 19 Mar 2014 10:47:55 +0800 Subject: fsl/diu: ch7301 encoder split off from t1040qds/diu.c The ch7301 encoder not only used in t1040qds platform, so we split it for t1042rdb and LSx platform. Signed-off-by: Wang Dongsheng Reviewed-by: York Sun diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 22b57cc..50d7731 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -34,6 +34,8 @@ ifndef CONFIG_RAMBOOT_PBL obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o endif +obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o + obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c new file mode 100644 index 0000000..82ce870 --- /dev/null +++ b/board/freescale/common/diu_ch7301.c @@ -0,0 +1,136 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Authors: Priyanka Jain + * Wang Dongsheng + * + * This file is copied and modified from the original t1040qds/diu.c. + * Encoder can be used in T104x and LSx Platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F +#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 +#define I2C_DVI_PLL_DIVIDER_REG 0x34 +#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 +#define I2C_DVI_PLL_FILTER_REG 0x36 +#define I2C_DVI_TEST_PATTERN_REG 0x48 +#define I2C_DVI_POWER_MGMT_REG 0x49 +#define I2C_DVI_LOCK_STATE_REG 0x4D +#define I2C_DVI_SYNC_POLARITY_REG 0x56 + +/* + * Set VSYNC/HSYNC to active high. This is polarity of sync signals + * from DIU->DVI. The DIU default is active igh, so DVI is set to + * active high. + */ +#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 + +#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 +#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 +#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 +#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 +#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 +#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 + +/* Clear test pattern */ +#define I2C_DVI_TEST_PATTERN_VAL 0x18 +/* Exit Power-down mode */ +#define I2C_DVI_POWER_MGMT_VAL 0xC0 + +/* Monitor polarity is handled via DVI Sync Polarity Register */ +#define I2C_DVI_SYNC_POLARITY_VAL 0x00 + +/* Programming of HDMI Chrontel CH7301 connector */ +int diu_set_dvi_encoder(unsigned int pixclock) +{ + int ret; + u8 temp; + + temp = I2C_DVI_TEST_PATTERN_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select proper dvi test pattern\n"); + return ret; + } + temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, + 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi input data format\n"); + return ret; + } + + /* Set Sync polarity register */ + temp = I2C_DVI_SYNC_POLARITY_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi syc polarity\n"); + return ret; + } + + /* Set PLL registers based on pixel clock rate*/ + if (pixclock > 65000000) { + temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } else { + temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } + + temp = I2C_DVI_POWER_MGMT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi power mgmt\n"); + return ret; + } + + udelay(500); + + return 0; +} diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h new file mode 100644 index 0000000..8b6ead0 --- /dev/null +++ b/board/freescale/common/diu_ch7301.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DIU_HDMI_CH7301__ +#define __DIU_HDMI_CH7301__ + +/* Programming of HDMI Chrontel CH7301 connector */ +int diu_set_dvi_encoder(unsigned int pixclock); + +#endif diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c index ffd074b..0214224 100644 --- a/board/freescale/t1040qds/diu.c +++ b/board/freescale/t1040qds/diu.c @@ -13,42 +13,9 @@ #include #include #include "../common/qixis.h" +#include "../common/diu_ch7301.h" #include "t1040qds.h" #include "t1040qds_qixis.h" -#include - - -#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F -#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 -#define I2C_DVI_PLL_DIVIDER_REG 0x34 -#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 -#define I2C_DVI_PLL_FILTER_REG 0x36 -#define I2C_DVI_TEST_PATTERN_REG 0x48 -#define I2C_DVI_POWER_MGMT_REG 0x49 -#define I2C_DVI_LOCK_STATE_REG 0x4D -#define I2C_DVI_SYNC_POLARITY_REG 0x56 - -/* - * Set VSYNC/HSYNC to active high. This is polarity of sync signals - * from DIU->DVI. The DIU default is active igh, so DVI is set to - * active high. - */ -#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 - -#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 -#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 -#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 -#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 -#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 -#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 - -/* Clear test pattern */ -#define I2C_DVI_TEST_PATTERN_VAL 0x18 -/* Exit Power-down mode */ -#define I2C_DVI_POWER_MGMT_VAL 0xC0 - -/* Monitor polarity is handled via DVI Sync Polarity Register */ -#define I2C_DVI_SYNC_POLARITY_VAL 0x00 /* * DIU Area Descriptor @@ -69,98 +36,6 @@ #define AD_COMP_1_SHIFT 4 #define AD_COMP_0_SHIFT 0 -/* Programming of HDMI Chrontel CH7301 connector */ -int diu_set_dvi_encoder(unsigned int pixclock) -{ - int ret; - u8 temp; - select_i2c_ch_pca9547(I2C_MUX_CH_DIU); - - temp = I2C_DVI_TEST_PATTERN_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select proper dvi test pattern\n"); - return ret; - } - temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, - 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi input data format\n"); - return ret; - } - - /* Set Sync polarity register */ - temp = I2C_DVI_SYNC_POLARITY_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select dvi syc polarity\n"); - return ret; - } - - /* Set PLL registers based on pixel clock rate*/ - if (pixclock > 65000000) { - temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll charge_cntl\n"); - return ret; - } - temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll divider\n"); - return ret; - } - temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll filter\n"); - return ret; - } - } else { - temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll charge_cntl\n"); - return ret; - } - temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll divider\n"); - return ret; - } - temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, - I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); - if (ret) { - puts("I2C: failed to select dvi pll filter\n"); - return ret; - } - } - - temp = I2C_DVI_POWER_MGMT_VAL; - ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, - &temp, 1); - if (ret) { - puts("I2C: failed to select dvi power mgmt\n"); - return ret; - } - - udelay(500); - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - return 0; -} - void diu_set_pixel_clock(unsigned int pixclock) { unsigned long speed_ccb, temp; @@ -172,12 +47,19 @@ void diu_set_pixel_clock(unsigned int pixclock) pixval = speed_ccb / temp; /* Program HDMI encoder */ + /* Switch channel to DIU */ + select_i2c_ch_pca9547(I2C_MUX_CH_DIU); + + /* Set dispaly encoder */ ret = diu_set_dvi_encoder(temp); if (ret) { puts("Failed to set DVI encoder\n"); return; } + /* Switch channel to default */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + /* Program pixel clock */ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, ((pixval << PXCK_BITS_START) & PXCK_MASK)); diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index ebee89a..a781ba3 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -416,6 +416,7 @@ unsigned long get_board_ddr_clk(void); /* Video */ #define CONFIG_FSL_DIU_FB #ifdef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_CH7301 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) #define CONFIG_VIDEO #define CONFIG_CMD_BMP -- cgit v0.10.2 From cf8ddacffce84376380260c9b0bbe03a39b8884d Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Wed, 19 Mar 2014 10:47:56 +0800 Subject: powerpc/t1042RDB: Add Video - HDMI support T1042 has internal display interface unit (DIU) for driving video. T1042RDB supports video mode via -LCD using TI enconder -HDMI type interface via HDMI encoder Chrontel, CH7301C encoder which is I2C programmable is used as HDMI connector on T1042RDB. This patch add support to -enable Video interface for T1042RDB -route qixis multiplexing to enable DIU-HDMI interface on board -program DIU pixel clock gerenartor for T1042 -program HDMI encoder via I2C on board This patch refer to the upstream diu patch (337b0c52b3296f371d04aef71a833e09110e0e6b) for T1040qds. Signed-off-by: Jason Jin Signed-off-by: Wang Dongsheng [York Sun: resolve conflict and move changes to T104xRDB.h] Reviewed-by: York Sun diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index 6cd304c..b9ef17f 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -11,6 +11,7 @@ obj-y += t104xrdb.o obj-y += cpld.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_FSL_DIU_FB)+= diu.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c new file mode 100644 index 0000000..3285bef --- /dev/null +++ b/board/freescale/t104xrdb/diu.c @@ -0,0 +1,84 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Author: Priyanka Jain + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/diu_ch7301.h" + +#include "cpld.h" +#include "t104xrdb.h" + +/* + * DIU Area Descriptor + * + * Note that we need to byte-swap the value before it's written to the AD + * register. So even though the registers don't look like they're in the same + * bit positions as they are on the MPC8610, the same value is written to the + * AD register on the MPC8610 and on the P1022. + */ +#define AD_BYTE_F 0x10000000 +#define AD_ALPHA_C_SHIFT 25 +#define AD_BLUE_C_SHIFT 23 +#define AD_GREEN_C_SHIFT 21 +#define AD_RED_C_SHIFT 19 +#define AD_PIXEL_S_SHIFT 16 +#define AD_COMP_3_SHIFT 12 +#define AD_COMP_2_SHIFT 8 +#define AD_COMP_1_SHIFT 4 +#define AD_COMP_0_SHIFT 0 + +void diu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long speed_ccb, temp; + u32 pixval; + int ret; + + speed_ccb = get_bus_freq(0); + temp = 1000000000 / pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + + /* Program HDMI encoder */ + ret = diu_set_dvi_encoder(temp); + if (ret) { + puts("Failed to set DVI encoder\n"); + return; + } + + /* Program pixel clock */ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, + ((pixval << PXCK_BITS_START) & PXCK_MASK)); + + /* enable clock*/ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | + ((pixval << PXCK_BITS_START) & PXCK_MASK)); +} + +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) +{ + u32 pixel_format; + u8 sw; + + /*Configure Display ouput port as HDMI*/ + sw = CPLD_READ(sfp_ctl_status); + CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP)); + + pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | + (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | + (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | + (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | + (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); + + printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres); + + return fsl_diu_init(xres, yres, pixel_format, 0); +} diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index c4bf0d6..89e20b1 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -268,6 +268,9 @@ #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 +#ifdef CONFIG_T1042RDB_PI +#define CPLD_DIU_SEL_DFP 0x80 +#endif #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) @@ -429,6 +432,24 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#ifdef CONFIG_T1042RDB_PI +/* Video */ +#define CONFIG_FSL_DIU_FB + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_CFB_CONSOLE_ANSI +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#endif +#endif + /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP @@ -461,6 +482,10 @@ #endif #ifdef CONFIG_T1042RDB_PI +/* LDI/DVI Encoder for display */ +#define CONFIG_SYS_I2C_LDI_ADDR 0x38 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 + /* * RTC configuration */ @@ -772,11 +797,18 @@ #define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot" #endif +#ifdef CONFIG_FSL_DIU_FB +#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" +#else +#define DIU_ENVIRONMENT +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ + "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ -- cgit v0.10.2 From 3067547502873281b19e01c7bc25da63c9b42b1e Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Wed, 23 Jul 2014 17:27:52 +0800 Subject: powerpc/mpc85xx: Make boot flag effective bootflag as a parameter is passed to board_init_f(). But it is not actually used in this function. Make it effective by assigned it to gd->flags. Signed-off-by: Tang Yuantian Reviewed-by: York Sun diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 0296205..6eaab88 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -366,6 +366,8 @@ void board_init_f(ulong bootflag) memset((void *) gd, 0, sizeof(gd_t)); #endif + gd->flags = bootflag; + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) if ((*init_fnc_ptr) () != 0) hang(); -- cgit v0.10.2 From ce249d956c820af4b9790406461b1748741d0478 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Wed, 23 Jul 2014 17:27:53 +0800 Subject: powerpc/t104xrdb: support deep sleep in SPI/SD boot Add deep sleep support in SPI/SD boot. The destination address second stage uboot image is loaded to is changed because currently this address will be used by kernel which means we can't reserve it for resume. Entry point to kernel is still placed in second stage uboot. Signed-off-by: Tang Yuantian Reviewed-by: York Sun diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 3665ec6..3222e26 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -134,6 +134,21 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) printf("Failed to reserve memory for spin table: %s\n", fdt_strerror(off)); } +#ifdef CONFIG_DEEP_SLEEP +#ifdef CONFIG_SPL_MMC_BOOT + off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, + CONFIG_SYS_MMC_U_BOOT_SIZE); + if (off < 0) + printf("Failed to reserve memory for SD deep sleep: %s\n", + fdt_strerror(off)); +#elif defined(CONFIG_SPL_SPI_BOOT) + off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START, + CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE); + if (off < 0) + printf("Failed to reserve memory for SPI deep sleep: %s\n", + fdt_strerror(off)); +#endif +#endif } #endif diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index c628c95..3822a37 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -55,6 +56,11 @@ void board_init_f(ulong bootflag) /* Update GD pointer */ gd = (gd_t *)(CONFIG_SPL_GD_ADDR); +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +#endif /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("" : : : "memory"); @@ -120,3 +126,16 @@ void board_init_r(gd_t *gd, ulong dest_addr) nand_boot(); #endif } + +#ifdef CONFIG_DEEP_SLEEP +void board_mem_sleep_setup(void) +{ + void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(cpld_base + 0x17, 0x40); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 89e20b1..0ee0ff2 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -32,7 +32,7 @@ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_FSL_LAW /* Use common FSL init code */ -#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SYS_TEXT_BASE 0x30001000 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -48,21 +48,21 @@ #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #define CONFIG_SPL_NAND_BOOT #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD @@ -72,12 +72,12 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD -- cgit v0.10.2 From 390619ddb390b08d77a23dd6531d2ec4866fb1bd Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Wed, 2 Jul 2014 11:44:15 +0530 Subject: powerpc/mpc85xx: Enabling CPC conditionally based on hwconfig options If hwconfig does not contains "en_cpc" then by default all cpcs are enabled If this config is defined then only those individual cpcs which are defined in the subargument of "en_cpc" will be enabled e.g en_cpc:cpc1,cpc2; (this will enable cpc1 and cpc2) or en_cpc:cpc2; (this enables just cpc2) Signed-off-by: Shaveta Leekha Signed-off-by: Sandeep Singh Reviewed-by: York Sun diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b237505..5bfab70 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -254,12 +254,36 @@ static void enable_tdm_law(void) void enable_cpc(void) { int i; + int ret; u32 size = 0; - + u32 cpccfg0; + char buffer[HWCONFIG_BUFFER_SIZE]; + char cpc_subarg[16]; + bool have_hwconfig = false; + int cpc_args = 0; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + /* Extract hwconfig from environment */ + ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (ret > 0) { + /* + * If "en_cpc" is not defined in hwconfig then by default all + * cpcs are enable. If this config is defined then individual + * cpcs which have to be enabled should also be defined. + * e.g en_cpc:cpc1,cpc2; + */ + if (hwconfig_f("en_cpc", buffer)) + have_hwconfig = true; + } + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { - u32 cpccfg0 = in_be32(&cpc->cpccfg0); + if (have_hwconfig) { + sprintf(cpc_subarg, "cpc%u", i + 1); + cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); + if (cpc_args == 0) + continue; + } + cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 -- cgit v0.10.2 From 12eeb1359aa365061f65d978bf728e42813d53dd Mon Sep 17 00:00:00 2001 From: Vijay Rai Date: Wed, 23 Jul 2014 18:33:16 +0530 Subject: driver/qe: update status of QE microcode This Patch updates error print for QE which should be easily understood Signed-off-by: Vijay Rai Reviewed-by: York Sun diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index be09a17..4358a91 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -333,7 +333,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware) /* Check the magic */ if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || (hdr->magic[2] != 'F')) { - printf("Not a microcode\n"); + printf("QE microcode not found\n"); #ifdef CONFIG_DEEP_SLEEP setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); #endif -- cgit v0.10.2 From 24753676700020b635bd0f27712df26cb71f3646 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Wed, 13 Aug 2014 10:24:04 +0200 Subject: km-powerpc: define CONFIG_PRAM to protect PHRAM and PNVRAM When u-boot initializes the RAM (early in boot) it looks for the "pram" env variable to know which is area it cannot use. If the "pram" env variable is not found, the default CONFIG_PRAM value is used. This value used to be 0 (no protection at all). This patch sets it to a value that covers PHRAM and PNVRAM that must be protected in our case. Signed-off-by: Valentin Longchamp Signed-off-by: Holger Brunck Reviewed-by: York Sun diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 763c5ba..eb85a74 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -59,8 +59,9 @@ #define CONFIG_KM_PHRAM 0x100000 /* resereved pram area at the end of memroy [hex] */ #define CONFIG_KM_RESERVED_PRAM 0x0 -/* enable protected RAM */ -#define CONFIG_PRAM 0 +/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable + * is not valid yet, which is the case for when u-boot copies itself to RAM */ +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) #define CONFIG_KM_CRAMFS_ADDR 0x800000 #define CONFIG_KM_KERNEL_ADDR 0x400000 /* 3968Kbytes */ -- cgit v0.10.2 From 9bf499ace8dd0d4b9c092081425696c150ffc563 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Wed, 13 Aug 2014 18:19:15 +0800 Subject: powerpc/T4240QDS/eth: some fix for XFI XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs of serdes2 are routed to a SFP+ cages, which to house fiber cable or direct attach cable(copper), the copper cable is used to emulate the 10GBASE-KR scenario. So, for XFI usage, there are two scenarios, one will use fiber cable, another will use copper cable. For fiber cable, there is NO PHY, while for copper cable, we need to use internal PHY which exist in Serdes to do auto-negotiation and link training, which implemented in kernel. We use hwconfig to define cable type for XFI, and fixup dtb based on the cable type. For copper cable, set below env in hwconfig: fsl_10gkr_copper:<10g_mac_name> the <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The four <10g_mac_name>s do not have to be coexist in hwconfig. For XFI ports, if a given 10G port will use the copper cable for 10GBASE-KR, set the <10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be assumed to be used for the port. For ex. if four XFI ports will both use copper cable, the hwconfig should contain: fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2 For fiber cable: 1. give PHY address to a XFI port, otherwise, the XFI ports will not be available in U-boot, there is no PHY physically for XFI when using fiber cable, this is just to make U-boot happy and we can use the XFI ports in U-boot. 2. fixup dtb to use fixed-link in case of fiber cable which has no PHY. Kernel requests that a MAC must have a PHY or fixed-link. When using XFI protocol, the MAC 9/10 on FM1 should init as 10G interface. Change serdes 2 protocol 56 to 55 which has same feature as 56 since 56 is not valid any longer. Signed-off-by: Shaohui Xie Reviewed-by: York Sun diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index 6210e46..9b416b1 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "../common/fman.h" @@ -173,6 +174,10 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) { int interface = fm_info_get_enet_if(port); + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + + prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; if (interface == PHY_INTERFACE_MODE_SGMII || interface == PHY_INTERFACE_MODE_QSGMII) { @@ -262,6 +267,76 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, default: break; } + } else if (interface == PHY_INTERFACE_MODE_XGMII && + ((prtcl2 == 55) || (prtcl2 == 57))) { + /* + * if the 10G is XFI, check hwconfig to see what is the + * media type, there are two types, fiber or copper, + * fix the dtb accordingly. + */ + int media_type = 0; + struct fixed_link f_link; + char lane_mode[20] = {"10GBASE-KR"}; + char buf[32] = "serdes-2,"; + int off; + + switch (port) { + case FM1_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi1"); + sprintf(buf, "%s%s%s", buf, "lane-a,", + (char *)lane_mode); + } + break; + case FM1_10GEC2: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi2"); + sprintf(buf, "%s%s%s", buf, "lane-b,", + (char *)lane_mode); + } + break; + case FM2_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi3"); + sprintf(buf, "%s%s%s", buf, "lane-d,", + (char *)lane_mode); + } + break; + case FM2_10GEC2: + if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) { + media_type = 1; + fdt_set_phy_handle(blob, prop, pa, + "phy_xfi4"); + sprintf(buf, "%s%s%s", buf, "lane-c,", + (char *)lane_mode); + } + break; + default: + return; + } + + if (!media_type) { + /* fixed-link is used for XFI fiber cable */ + fdt_delprop(blob, offset, "phy-handle"); + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + fdt_setprop(blob, offset, "fixed-link", &f_link, + sizeof(f_link)); + } else { + /* set property for copper cable */ + off = fdt_node_offset_by_compat_reg(blob, + "fsl,fman-memac-mdio", pa + 0x1000); + fdt_setprop_string(blob, off, "lane-instance", buf); + } } } @@ -295,8 +370,23 @@ void fdt_fixup_board_enet(void *fdt) break; case PHY_INTERFACE_MODE_XGMII: /* check if it's XFI interface for 10g */ - if ((prtcl2 == 56) || (prtcl2 == 57)) { - fdt_status_okay_by_alias(fdt, "emi2_xfislot3"); + if ((prtcl2 == 55) || (prtcl2 == 57)) { + if (i == FM1_10GEC1 && hwconfig_sub( + "fsl_10gkr_copper", "fm1_10g1")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio1"); + if (i == FM1_10GEC2 && hwconfig_sub( + "fsl_10gkr_copper", "fm1_10g2")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio2"); + if (i == FM2_10GEC1 && hwconfig_sub( + "fsl_10gkr_copper", "fm2_10g1")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio3"); + if (i == FM2_10GEC2 && hwconfig_sub( + "fsl_10gkr_copper", "fm2_10g2")) + fdt_status_okay_by_alias( + fdt, "xfi_pcs_mdio4"); break; } switch (i) { @@ -460,7 +550,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, slot_qsgmii_phyaddr[1][3]); fm_info_set_phy_address(FM1_DTSEC10, @@ -475,7 +565,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, slot_qsgmii_phyaddr[1][2]); fm_info_set_phy_address(FM1_DTSEC10, @@ -490,7 +580,7 @@ int board_eth_init(bd_t *bis) case 48: fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC10, slot_qsgmii_phyaddr[1][2]); fm_info_set_phy_address(FM1_DTSEC9, @@ -567,13 +657,18 @@ int board_eth_init(bd_t *bis) idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, + if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) { + /* A fake PHY address to make U-boot happy */ + fm_info_set_phy_address(i, i); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, XAUI_FM1_MAC9 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm1[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); + if (lane < 0) + break; + slot = lane_to_slot_fsm1[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + } mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; @@ -666,7 +761,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; - case 56: + case 55: case 57: /* XFI in Slot3, SGMII in Slot4 */ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); @@ -743,13 +838,18 @@ int board_eth_init(bd_t *bis) idx = i - FM2_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(FSL_SRDS_2, + if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) { + /* A fake PHY address to make U-boot happy */ + fm_info_set_phy_address(i, i); + } else { + lane = serdes_get_first_lane(FSL_SRDS_2, XAUI_FM2_MAC9 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm2[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); + if (lane < 0) + break; + slot = lane_to_slot_fsm2[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + } mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; diff --git a/doc/README.t4240qds b/doc/README.t4240qds index ef8c75f..3962fee 100644 --- a/doc/README.t4240qds +++ b/doc/README.t4240qds @@ -79,6 +79,25 @@ Board Features - High-speed serial flash Two Serial port Four I2C ports + XFI + XFI is supported on T4QDS-XFI board which removed slot3 and routed + four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or + direct attach cable(copper), the copper cable is used to emulate + 10GBASE-KR scenario. + So, for XFI usage, there are two scenarios, one will use fiber cable, + another will use copper cable. An hwconfig env "fsl_10gkr_copper" is + introduced to indicate a XFI port will use copper cable, and U-boot + will fixup the dtb accordingly. + It's used as: fsl_10gkr_copper:<10g_mac_name> + The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they + do not have to be coexist in hwconfig. If a MAC is listed in the env + "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable + will be used by default. + for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in + hwconfig, then both four XFI ports will use copper cable. + set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two + XFI ports will use copper cable, the other two XFI ports will use fiber + cable. Memory map ---------- diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c index 1eacb22..ae5aca4 100644 --- a/drivers/net/fm/t4240.c +++ b/drivers/net/fm/t4240.c @@ -71,6 +71,11 @@ phy_interface_t fman_port_enet_if(enum fm_port port) (is_serdes_configured(XFI_FM1_MAC10)))) return PHY_INTERFACE_MODE_XGMII; + if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) && + ((is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + if ((port == FM2_10GEC1 || port == FM2_10GEC2) && ((is_serdes_configured(XAUI_FM2_MAC9)) || (is_serdes_configured(XAUI_FM2_MAC10)) || -- cgit v0.10.2 From 8af353bb0efa3152396ecca99ba9e91633bdb8a0 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 13 Aug 2014 10:54:44 -0700 Subject: powerpc/t4qds: Move doc/README.t4240qds under board/freescale/t4qds Board specific README file should be moved to board folder. Signed-off-by: York Sun diff --git a/board/freescale/t4qds/README b/board/freescale/t4qds/README new file mode 100644 index 0000000..3962fee --- /dev/null +++ b/board/freescale/t4qds/README @@ -0,0 +1,194 @@ +Overview +-------- +The T4240QDS is a high-performance computing evaluation, development and test +platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is +optimized to support the high-bandwidth DDR3 memory ports, as well as the +highly-configurable SerDes ports. The system is lead-free and RoHS-compliant. + +Board Features + SERDES Connections + 32 lanes grouped into four 8-lane banks + Two “front side” banks dedicated to Ethernet + - High-speed crosspoint switch fabric on selected lanes + - Two PCI Express slots with side-band connector supporting + - SGMII + - XAUI + - HiGig + - I-pass connectors allow board-to-board and loopback support + Two “back side” banks dedicated to other protocols + - High-speed crosspoint switch fabric on all lanes + - Four PCI Express slots with side-band connector supporting + - PCI Express 3.0 + - SATA 2.0 + - SRIO 2.0 + - Supports 4X Aurora debug with two connectors + DDR Controllers + Three independant 64-bit DDR3 controllers + Supports rates of 1866 up to 2133 MHz data-rate + Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller + DDR power supplies 1.5V to all devices with automatic tracking of VTT. + Power software-switchable to 1.35V if software detects all DDR3LP devices. + MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and + 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time + increases by 1 clock. + + IFC/Local Bus + NAND flash: 8-bit, async or sync, up to 2GB. + NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB + NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB + - NOR devices support 16 virtual banks + GASIC: Minimal target within Qixis FPGA + PromJET rapid memory download support + Address demultiplexing handled within FPGA. + - Flexible demux allows 8 or 16 bit evaluation. + IFC Debug/Development card + - Support for 32-bit devices + Ethernet + Support two on-board RGMII 10/100/1G ethernet ports. + SGMII and XAUI support via SERDES block (see above). + 1588 support via Symmetricom board. + QIXIS System Logic FPGA + Manages system power and reset sequencing + Manages DUT, board, clock, etc. configuration for dynamic shmoo + Collects V-I-T data in background for code/power profiling. + Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion) + General fault monitoring and logging + Runs from ATX “hot” power rails allowing operation while system is off. + Clocks + System and DDR clock (SYSCLK, “DDRCLK”) + - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz. + - Software selectable in 1MHz increments from 1-200MHz. + SERDES clocks + - Provides clocks to all SerDes blocks and slots + - 100, 125 and 156.25 MHz + Power Supplies + Dedicated regulators for VDD + - Adjustable from (0.7V to 1.3V at 80A + - Regulators can be controlled by VID and/or software + Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A + - VTT/MVREF automatically track operating voltage + Dedicated regulators/filters for AVDD supplies + Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc. + USB + Supports two USB 2.0 ports with integrated PHYs + - One type A, one type micro-AB with 1.0A power per port. + Other IO + eSDHC/MMC + - SDHC card slot + eSPI port + - High-speed serial flash + Two Serial port + Four I2C ports + XFI + XFI is supported on T4QDS-XFI board which removed slot3 and routed + four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or + direct attach cable(copper), the copper cable is used to emulate + 10GBASE-KR scenario. + So, for XFI usage, there are two scenarios, one will use fiber cable, + another will use copper cable. An hwconfig env "fsl_10gkr_copper" is + introduced to indicate a XFI port will use copper cable, and U-boot + will fixup the dtb accordingly. + It's used as: fsl_10gkr_copper:<10g_mac_name> + The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they + do not have to be coexist in hwconfig. If a MAC is listed in the env + "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable + will be used by default. + for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in + hwconfig, then both four XFI ports will use copper cable. + set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two + XFI ports will use copper cable, the other two XFI ports will use fiber + cable. + +Memory map +---------- +The addresses in brackets are physical addresses. + +0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB) +0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory +0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers) +0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan +0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan +0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO +0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash +0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR +0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS +0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores + +The physical address of the last (boot page translation) varies with the actual DDR size. + +Voltage ID and VDD override +-------------------- +T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage +accordingly. The voltage can also be override by command vdd_override. The +syntax is + +vdd_override , eg. 1050 is for 1.050v. + +Upon success, the actual voltage will be read back. The value is checked +for safety and any invalid value will not adjust the voltage. + +Another way to override VDD is to use environmental variable, in case of using +command is too late for some debugging. The syntax is + +setenv t4240qds_vdd_mv +saveenv +reset + +The override voltage takes effect when booting. + +Note: voltage adjustment needs to be done step by step. Changing voltage too +rapidly may cause current surge. The voltage stepping is done by software. +Users can set the final voltage directly. + +2-stage NAND/SD boot loader +------------------------------- +PBL initializes the internal SRAM and copy SPL(160K) in SRAM. +SPL further initialise DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T4QDS +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x140000 0x15FFFF u-boot env 128KB +0x160000 0x17FFFF FMAN Ucode 128KB + +Micro SD Card memory Map on T4QDS +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0128 FMAN ucode 64KB + +Switch Settings: (ON is 1, OFF is 0) +=============== +NAND boot SW setting: +SW1[1:8] = 10000010 +SW2[1.1] = 0 +SW6[1:4] = 1001 + +SD boot SW setting: +SW1[1:8] = 00100000 +SW2[1.1] = 0 diff --git a/doc/README.t4240qds b/doc/README.t4240qds deleted file mode 100644 index 3962fee..0000000 --- a/doc/README.t4240qds +++ /dev/null @@ -1,194 +0,0 @@ -Overview --------- -The T4240QDS is a high-performance computing evaluation, development and test -platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is -optimized to support the high-bandwidth DDR3 memory ports, as well as the -highly-configurable SerDes ports. The system is lead-free and RoHS-compliant. - -Board Features - SERDES Connections - 32 lanes grouped into four 8-lane banks - Two “front side” banks dedicated to Ethernet - - High-speed crosspoint switch fabric on selected lanes - - Two PCI Express slots with side-band connector supporting - - SGMII - - XAUI - - HiGig - - I-pass connectors allow board-to-board and loopback support - Two “back side” banks dedicated to other protocols - - High-speed crosspoint switch fabric on all lanes - - Four PCI Express slots with side-band connector supporting - - PCI Express 3.0 - - SATA 2.0 - - SRIO 2.0 - - Supports 4X Aurora debug with two connectors - DDR Controllers - Three independant 64-bit DDR3 controllers - Supports rates of 1866 up to 2133 MHz data-rate - Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller - DDR power supplies 1.5V to all devices with automatic tracking of VTT. - Power software-switchable to 1.35V if software detects all DDR3LP devices. - MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and - 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time - increases by 1 clock. - - IFC/Local Bus - NAND flash: 8-bit, async or sync, up to 2GB. - NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - - NOR devices support 16 virtual banks - GASIC: Minimal target within Qixis FPGA - PromJET rapid memory download support - Address demultiplexing handled within FPGA. - - Flexible demux allows 8 or 16 bit evaluation. - IFC Debug/Development card - - Support for 32-bit devices - Ethernet - Support two on-board RGMII 10/100/1G ethernet ports. - SGMII and XAUI support via SERDES block (see above). - 1588 support via Symmetricom board. - QIXIS System Logic FPGA - Manages system power and reset sequencing - Manages DUT, board, clock, etc. configuration for dynamic shmoo - Collects V-I-T data in background for code/power profiling. - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion) - General fault monitoring and logging - Runs from ATX “hot” power rails allowing operation while system is off. - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz. - - Software selectable in 1MHz increments from 1-200MHz. - SERDES clocks - - Provides clocks to all SerDes blocks and slots - - 100, 125 and 156.25 MHz - Power Supplies - Dedicated regulators for VDD - - Adjustable from (0.7V to 1.3V at 80A - - Regulators can be controlled by VID and/or software - Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A - - VTT/MVREF automatically track operating voltage - Dedicated regulators/filters for AVDD supplies - Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc. - USB - Supports two USB 2.0 ports with integrated PHYs - - One type A, one type micro-AB with 1.0A power per port. - Other IO - eSDHC/MMC - - SDHC card slot - eSPI port - - High-speed serial flash - Two Serial port - Four I2C ports - XFI - XFI is supported on T4QDS-XFI board which removed slot3 and routed - four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or - direct attach cable(copper), the copper cable is used to emulate - 10GBASE-KR scenario. - So, for XFI usage, there are two scenarios, one will use fiber cable, - another will use copper cable. An hwconfig env "fsl_10gkr_copper" is - introduced to indicate a XFI port will use copper cable, and U-boot - will fixup the dtb accordingly. - It's used as: fsl_10gkr_copper:<10g_mac_name> - The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they - do not have to be coexist in hwconfig. If a MAC is listed in the env - "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable - will be used by default. - for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in - hwconfig, then both four XFI ports will use copper cable. - set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two - XFI ports will use copper cable, the other two XFI ports will use fiber - cable. - -Memory map ----------- -The addresses in brackets are physical addresses. - -0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB) -0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory -0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers) -0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan -0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan -0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO -0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash -0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR -0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS -0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores - -The physical address of the last (boot page translation) varies with the actual DDR size. - -Voltage ID and VDD override --------------------- -T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage -accordingly. The voltage can also be override by command vdd_override. The -syntax is - -vdd_override , eg. 1050 is for 1.050v. - -Upon success, the actual voltage will be read back. The value is checked -for safety and any invalid value will not adjust the voltage. - -Another way to override VDD is to use environmental variable, in case of using -command is too late for some debugging. The syntax is - -setenv t4240qds_vdd_mv -saveenv -reset - -The override voltage takes effect when booting. - -Note: voltage adjustment needs to be done step by step. Changing voltage too -rapidly may cause current surge. The voltage stepping is done by software. -Users can set the final voltage directly. - -2-stage NAND/SD boot loader -------------------------------- -PBL initializes the internal SRAM and copy SPL(160K) in SRAM. -SPL further initialise DDR using SPD and environment variables -and copy u-boot(768 KB) from NAND/SD device to DDR. -Finally SPL transers control to u-boot for futher booting. - -SPL has following features: - - Executes within 256K - - No relocation required - -Run time view of SPL framework -------------------------------------------------- -|Area | Address | -------------------------------------------------- -|SecureBoot header | 0xFFFC0000 (32KB) | -------------------------------------------------- -|GD, BD | 0xFFFC8000 (4KB) | -------------------------------------------------- -|ENV | 0xFFFC9000 (8KB) | -------------------------------------------------- -|HEAP | 0xFFFCB000 (50KB) | -------------------------------------------------- -|STACK | 0xFFFD8000 (22KB) | -------------------------------------------------- -|U-boot SPL | 0xFFFD8000 (160KB) | -------------------------------------------------- - -NAND Flash memory Map on T4QDS --------------------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF u-boot img 1MB -0x140000 0x15FFFF u-boot env 128KB -0x160000 0x17FFFF FMAN Ucode 128KB - -Micro SD Card memory Map on T4QDS ----------------------------------------------------- -Block #blocks Definition Size -0x008 2048 u-boot img 1MB -0x800 0016 u-boot env 8KB -0x820 0128 FMAN ucode 64KB - -Switch Settings: (ON is 1, OFF is 0) -=============== -NAND boot SW setting: -SW1[1:8] = 10000010 -SW2[1.1] = 0 -SW6[1:4] = 1001 - -SD boot SW setting: -SW1[1:8] = 00100000 -SW2[1.1] = 0 -- cgit v0.10.2 From f38391793f1a5c62d1c72a647f15a88e7c22ef11 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 19 Aug 2014 15:40:04 +0200 Subject: kmp204x: reset the Zarlink clocking chips at power up only There is the requirement on the chassis's backplane that when the clocks have been enabled, they then should not disappear. Resetting the Zarlink clocking chips at unit reset violates this requirement because the backplane clocks are not supplied during the reset time. To avoid this side effect, both the Zarlink clocking chips are reset only at power up. Signed-off-by: Valentin Longchamp diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index cd08379..4a73613 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -108,8 +108,8 @@ int board_early_init_f(void) /* and enable WD on it */ qrio_wdmask(BFTIC4_RST, true); - /* set the ZL30138's prstcfg to reset at power-up and unit reset only */ - qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST); + /* set the ZL30138's prstcfg to reset at power-up only */ + qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST); /* and take it out of reset as soon as possible (needed for Hooper) */ qrio_prst(ZL30158_RST, false, false); @@ -158,8 +158,8 @@ int misc_init_f(void) qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST); qrio_prst(ETH_FRONT_PHY_RST, false, false); - /* set the ZL30343 prstcfg to reset at power-up and unit reset only */ - qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST); + /* set the ZL30343 prstcfg to reset at power-up only */ + qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST); /* and enable the WD on it */ qrio_wdmask(ZL30343_RST, true); -- cgit v0.10.2