From 97205eeab4d1a785340052657673c56f2d440db7 Mon Sep 17 00:00:00 2001 From: "jerry.huang@nxp.com" Date: Tue, 15 Nov 2016 10:47:52 +0800 Subject: fsl/usb: enable usb feature for ls1046ardb Enable usb feature for ls1046ardb Signed-off-by: Changming Huang Reviewed-by: York Sun diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 2fe8fc1..f0719ad 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -211,6 +211,18 @@ #define CONFIG_SPI_FLASH_BAR #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_HCD +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 15cac40..1fa3161 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -62,7 +62,7 @@ struct fsl_xhci { #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_LS1043A) +#elif defined(CONFIG_LS1043A) || defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR -- cgit v0.10.2 From d037261f7f36a8c1e56acb1a52480d945cbb6f63 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Wed, 9 Nov 2016 12:27:54 +0530 Subject: armv8: fsl-layerscape, ccn504: Set forced-order mode in RNI-6, RNI-20 It is recommended to set forced-order mode in RNI-6, RNI-20 for performance optimization in LS2088A. Both LS2080A, LS2088A families has CONFIG_LS2080A define. As above update is required only for LS2088A, skip this for LS2080A SoC family. Signed-off-by: Priyanka Jain Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 72f2c11..3404459 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -29,6 +29,26 @@ ENTRY(lowlevel_init) ldr x0, =CCI_AUX_CONTROL_BASE(20) ldr x1, =0x00000010 bl ccn504_set_aux + + /* + * Set forced-order mode in RNI-6, RNI-20 + * This is required for performance optimization on LS2088A + * LS2080A family does not support setting forced-order mode, + * so skip this operation for LS2080A family + */ + bl get_svr + lsr w0, w0, #16 + ldr w1, =SVR_DEV_LS2080A + cmp w0, w1 + b.eq 1f + + ldr x0, =CCI_AUX_CONTROL_BASE(6) + ldr x1, =0x00000020 + bl ccn504_set_aux + ldr x0, =CCI_AUX_CONTROL_BASE(20) + ldr x1, =0x00000020 + bl ccn504_set_aux +1: #endif /* Add fully-coherent masters to DVM domain */ -- cgit v0.10.2 From 388f3865832fd4118974854813d119b82220446c Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 15 Nov 2016 17:35:24 +0800 Subject: armv8/layerscape: remove unnecessary function declares For the function alloc_stream_ids() append_mmu_masters() and fdt_fixup_smmu_pcie() there are no related definitions and they are never called. So the patch removes the unnecessary declares. Signed-off-by: Minghuan Lian Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h index 099563e..537486d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h @@ -7,9 +7,5 @@ #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ #define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ -void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); -void append_mmu_masters(void *blob, const char *smmu_path, - const char *master_name, u32 *stream_ids, int count); -void fdt_fixup_smmu_pcie(void *blob); void fdt_fixup_board_enet(void *fdt); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */ -- cgit v0.10.2 From 1e960e15a58d029fbf7ad2a58afc565275d3485e Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 13 Dec 2016 14:54:08 +0800 Subject: configs: ls1021a: enable DT and DM support Enable DT to support Driver Model. Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass Reviewed-by: York Sun diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 1eaa640..8bb518a 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y @@ -12,6 +13,7 @@ CONFIG_VIDEO=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_NAND_BOOT=y @@ -38,6 +40,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_PCI=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 820d6fc..8719a35 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -1,11 +1,13 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SECURE_BOOT=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_VIDEO=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 746a66a..348958b 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -1,12 +1,14 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SECURE_BOOT=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_VIDEO=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_OF_CONTROL=y CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 6f22f1a..2d32e96 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SECURE_BOOT=y @@ -13,6 +14,7 @@ CONFIG_VIDEO=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_BOOTDELAY=0 diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 22be22c..1c79d58 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y @@ -11,6 +12,7 @@ CONFIG_VIDEO=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_SD_BOOT=y @@ -35,6 +37,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_PCI=y -- cgit v0.10.2 From d7482ca4265fbe4065b28ace998636f78406ed95 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:09 +0800 Subject: dm: pci: return the real controller in pci_bus_to_hose() for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: York Sun diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c index ddaf358..25bc095 100644 --- a/drivers/pci/pci_compat.c +++ b/drivers/pci/pci_compat.c @@ -49,5 +49,5 @@ struct pci_controller *pci_bus_to_hose(int busnum) return NULL; } - return dev_get_uclass_priv(bus); + return dev_get_uclass_priv(pci_get_controller(bus)); } -- cgit v0.10.2 From fcf45692b7ea63f7947e60fa6425f1c8aceae4ae Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:10 +0800 Subject: dm: pci: remove pci_bus_to_hose(0) calling There may be multiple PCIe controllers in a SoC. It is not correct that always calling pci_bus_to_hose(0) to get the first PCIe controller for the PCIe device connected other controllers. We just remove this calling because hose always point the correct PCIe controller. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: York Sun diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index 1755914..6526de8 100644 --- a/drivers/pci/pci_common.c +++ b/drivers/pci/pci_common.c @@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose, return phys_addr; } -#ifdef CONFIG_DM_PCI - /* The root controller has the region information */ - hose = pci_bus_to_hose(0); -#endif - /* * if PCI_REGION_MEM is set we do a two pass search with preference * on matches that don't have PCI_REGION_SYS_MEMORY set @@ -236,6 +231,13 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose, return 1; } +/* + * pci_hose_phys_to_bus(): Convert physical address to bus address + * @hose: PCI hose of the root PCI controller + * @phys_addr: physical address to convert + * @flags: flags of pci regions + * @return bus address if OK, 0 on error + */ pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose, phys_addr_t phys_addr, unsigned long flags) @@ -248,11 +250,6 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose, return bus_addr; } -#ifdef CONFIG_DM_PCI - /* The root controller has the region information */ - hose = pci_bus_to_hose(0); -#endif - /* * if PCI_REGION_MEM is set we do a two pass search with preference * on matches that don't have PCI_REGION_SYS_MEMORY set -- cgit v0.10.2 From add73a1dad49236fd1f5b2ebaca87bed36db247d Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:11 +0800 Subject: arm: ls1021a: add PCIe dts node Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 37be169..c40d87c 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -374,5 +374,36 @@ interrupts = ; dr_mode = "host"; }; + + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x03400000 0x20000 /* dbi registers */ + 0x01570000 0x10000 /* pf controls registers */ + 0x24000000 0x20000>; /* configuration space */ + reg-names = "dbi", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x03500000 0x10000 /* dbi registers */ + 0x01570000 0x10000 /* pf controls registers */ + 0x34000000 0x20000>; /* configuration space */ + reg-names = "dbi", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */ + }; }; }; -- cgit v0.10.2 From 048a04530700704af622dc80a192b59de2e65fa2 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:12 +0800 Subject: arm: ls1012a: add PCIe dts node Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 024527e..c4ca9c1 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -103,5 +103,20 @@ status = "disabled"; }; + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ + 0x00 0x03480000 0x0 0x40000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x40 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; }; -- cgit v0.10.2 From ed9bddefb904c3d46bb0dd2e06bcfb082c666579 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:13 +0800 Subject: armv8: ls1043a: add PCIe dts node Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index f038f96..fe6698f 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -236,5 +236,51 @@ interrupts = <0 63 0x4>; dr_mode = "host"; }; + + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */ + 0x00 0x03410000 0x0 0x10000 /* lut registers */ + 0x40 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */ + 0x00 0x03510000 0x0 0x10000 /* lut registers */ + 0x48 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3600000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */ + 0x00 0x03610000 0x0 0x10000 /* lut registers */ + 0x50 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; }; -- cgit v0.10.2 From b948a16f3439b7bc4fed0adfc465a5634103e970 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:14 +0800 Subject: armv8: ls1046a: add PCIe dts node Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 359a9d1..aaf0ae9 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -216,5 +216,54 @@ big-endian; status = "disabled"; }; + + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ + 0x00 0x03480000 0x0 0x40000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x40 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ + 0x00 0x03580000 0x0 0x40000 /* lut registers */ + 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ + 0x48 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3600000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ + 0x00 0x03680000 0x0 0x40000 /* lut registers */ + 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */ + 0x50 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; }; -- cgit v0.10.2 From 33f61e07b3d020f708899304e43f6fd7301198b8 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:15 +0800 Subject: armv8: ls2080a: add PCIe dts node Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index f76e981..79047d5 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -89,4 +89,64 @@ interrupts = <0 81 0x4>; /* Level high type */ dr_mode = "host"; }; + + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ + 0x00 0x03480000 0x0 0x80000 /* lut registers */ + 0x10 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ + 0x00 0x03580000 0x0 0x80000 /* lut registers */ + 0x12 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3600000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ + 0x00 0x03680000 0x0 0x80000 /* lut registers */ + 0x14 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3700000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */ + 0x00 0x03780000 0x0 0x80000 /* lut registers */ + 0x16 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; -- cgit v0.10.2 From a7294aba086fb05ef2bbb50098a84d6c81e38a4b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 13 Dec 2016 14:54:16 +0800 Subject: pci: layerscape: move kernel DT fixup to a separate file To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c. Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass Reviewed-by: York Sun diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 86717a4..42174f9 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -32,4 +32,5 @@ obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o obj-$(CONFIG_WINBOND_83C553) += w83c553f.o obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o +obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 2e6b986..0e3b494 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -14,129 +14,12 @@ #ifndef CONFIG_LS102XA #include #include +#else +#include #endif - -#ifndef CONFIG_SYS_PCI_MEMORY_BUS -#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE -#endif - -#ifndef CONFIG_SYS_PCI_MEMORY_PHYS -#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE -#endif - -#ifndef CONFIG_SYS_PCI_MEMORY_SIZE -#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */ -#endif - -#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE -#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR -#endif - -/* iATU registers */ -#define PCIE_ATU_VIEWPORT 0x900 -#define PCIE_ATU_REGION_INBOUND (0x1 << 31) -#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) -#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) -#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) -#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) -#define PCIE_ATU_REGION_INDEX3 (0x3 << 0) -#define PCIE_ATU_CR1 0x904 -#define PCIE_ATU_TYPE_MEM (0x0 << 0) -#define PCIE_ATU_TYPE_IO (0x2 << 0) -#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) -#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) -#define PCIE_ATU_CR2 0x908 -#define PCIE_ATU_ENABLE (0x1 << 31) -#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) -#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8) -#define PCIE_ATU_LOWER_BASE 0x90C -#define PCIE_ATU_UPPER_BASE 0x910 -#define PCIE_ATU_LIMIT 0x914 -#define PCIE_ATU_LOWER_TARGET 0x918 -#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) -#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) -#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) -#define PCIE_ATU_UPPER_TARGET 0x91C - -#define PCIE_DBI_RO_WR_EN 0x8bc - -#define PCIE_LINK_CAP 0x7c -#define PCIE_LINK_SPEED_MASK 0xf -#define PCIE_LINK_STA 0x82 - -#define LTSSM_STATE_MASK 0x3f -#define LTSSM_PCIE_L0 0x11 /* L0 state */ - -#define PCIE_DBI_SIZE 0x100000 /* 1M */ - -#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31) -#define PCIE_LCTRL0_VF(vf) ((vf) << 22) -#define PCIE_LCTRL0_PF(pf) ((pf) << 16) -#define PCIE_LCTRL0_VF_ACTIVE (1 << 21) -#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \ - PCIE_LCTRL0_VF(vf) | \ - ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \ - PCIE_LCTRL0_CFG2_ENABLE) - -#define PCIE_NO_SRIOV_BAR_BASE 0x1000 - -#define PCIE_PF_NUM 2 -#define PCIE_VF_NUM 64 - -#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */ -#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */ -#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ -#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ - -struct ls_pcie { - int idx; - void __iomem *dbi; - void __iomem *va_cfg0; - void __iomem *va_cfg1; - int next_lut_index; - struct pci_controller hose; -}; - -struct ls_pcie_info { - unsigned long regs; - int pci_num; - u64 phys_base; - u64 cfg0_phys; - u64 cfg0_size; - u64 cfg1_phys; - u64 cfg1_size; - u64 mem_bus; - u64 mem_phys; - u64 mem_size; - u64 io_bus; - u64 io_phys; - u64 io_size; -}; - -#define SET_LS_PCIE_INFO(x, num) \ -{ \ - x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ - x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ - x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \ - CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ - x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \ - x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \ - CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ - x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \ - x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \ - CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ - x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \ - CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ - x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \ - x.pci_num = num; \ -} +#include "pcie_layerscape.h" #ifdef CONFIG_LS102XA -#include - /* PEX1/2 Misc Ports Status Register */ #define LTSSM_STATE_SHIFT 20 @@ -483,150 +366,6 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info) } } -#ifdef CONFIG_FSL_LSCH3 -/* - * Return next available LUT index. - */ -static int ls_pcie_next_lut_index(struct ls_pcie *pcie) -{ - if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) - return pcie->next_lut_index++; - else - return -1; /* LUT is full */ -} - -/* - * Program a single LUT entry - */ -static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, - u32 streamid) -{ - void __iomem *lut; - - lut = pcie->dbi + PCIE_LUT_BASE; - - /* leave mask as all zeroes, want to match all bits */ - writel((devid << 16), lut + PCIE_LUT_UDR(index)); - writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index)); -} - -/* returns the next available streamid */ -static u32 ls_pcie_next_streamid(void) -{ - static int next_stream_id = FSL_PEX_STREAM_ID_START; - - if (next_stream_id > FSL_PEX_STREAM_ID_END) - return 0xffffffff; - - return next_stream_id++; -} - -/* - * An msi-map is a property to be added to the pci controller - * node. It is a table, where each entry consists of 4 fields - * e.g.: - * - * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count] - * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>; - */ -static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, - u32 devid, u32 streamid) -{ - char pcie_path[19]; - u32 *prop; - u32 phandle; - int nodeoffset; - - /* find pci controller node */ - snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx", - (u64)pcie->dbi); - nodeoffset = fdt_path_offset(blob, pcie_path); - if (nodeoffset < 0) { - printf("\n%s: ERROR: unable to update PCIe node: %s\n", - __func__, pcie_path); - return; - } - - /* get phandle to MSI controller */ - prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0); - if (prop == NULL) { - printf("\n%s: ERROR: missing msi-parent: %s\n", __func__, - pcie_path); - return; - } - phandle = be32_to_cpu(*prop); - - /* set one msi-map row */ - fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid); - fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle); - fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid); - fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); -} - -static void fdt_fixup_pcie(void *blob) -{ - unsigned int found_multi = 0; - unsigned char header_type; - int index; - u32 streamid; - pci_dev_t dev, bdf; - int bus; - unsigned short id; - struct pci_controller *hose; - struct ls_pcie *pcie; - int i; - - for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) { - pcie = hose->priv_data; - for (bus = hose->first_busno; bus <= hose->last_busno; bus++) { - - for (dev = PCI_BDF(bus, 0, 0); - dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, - PCI_MAX_PCI_FUNCTIONS - 1); - dev += PCI_BDF(0, 0, 1)) { - - if (PCI_FUNC(dev) && !found_multi) - continue; - - pci_read_config_word(dev, PCI_VENDOR_ID, &id); - - pci_read_config_byte(dev, PCI_HEADER_TYPE, - &header_type); - - if ((id == 0xFFFF) || (id == 0x0000)) - continue; - - if (!PCI_FUNC(dev)) - found_multi = header_type & 0x80; - - streamid = ls_pcie_next_streamid(); - if (streamid == 0xffffffff) { - printf("ERROR: no stream ids free\n"); - continue; - } - - index = ls_pcie_next_lut_index(pcie); - if (index < 0) { - printf("ERROR: no LUT indexes free\n"); - continue; - } - - /* the DT fixup must be relative to the hose first_busno */ - bdf = dev - PCI_BDF(hose->first_busno, 0, 0); - - /* map PCI b.d.f to streamID in LUT */ - ls_pcie_lut_set_mapping(pcie, index, bdf >> 8, - streamid); - - /* update msi-map in device tree */ - fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, - streamid); - } - } - } -} -#endif - int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) { struct ls_pcie *pcie; @@ -767,50 +506,3 @@ void pci_init_board(void) { ls_pcie_init_board(0); } - -#ifdef CONFIG_OF_BOARD_SETUP -#include -#include - -static void ft_pcie_ls_setup(void *blob, const char *pci_compat, - unsigned long ctrl_addr, enum srds_prtcl dev) -{ - int off; - - off = fdt_node_offset_by_compat_reg(blob, pci_compat, - (phys_addr_t)ctrl_addr); - if (off < 0) - return; - - if (!is_serdes_configured(dev)) - fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); -} - -void ft_pci_setup(void *blob, bd_t *bd) -{ - #ifdef CONFIG_PCIE1 - ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); - #endif - - #ifdef CONFIG_PCIE2 - ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); - #endif - - #ifdef CONFIG_PCIE3 - ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3); - #endif - - #ifdef CONFIG_PCIE4 - ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4); - #endif - - #ifdef CONFIG_FSL_LSCH3 - fdt_fixup_pcie(blob); - #endif -} - -#else -void ft_pci_setup(void *blob, bd_t *bd) -{ -} -#endif diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h new file mode 100644 index 0000000..159e5ce --- /dev/null +++ b/drivers/pci/pcie_layerscape.h @@ -0,0 +1,135 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * Layerscape PCIe driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PCIE_LAYERSCAPE_H_ +#define _PCIE_LAYERSCAPE_H_ +#include + +#ifndef CONFIG_SYS_PCI_MEMORY_BUS +#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#endif + +#ifndef CONFIG_SYS_PCI_MEMORY_PHYS +#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE +#endif + +#ifndef CONFIG_SYS_PCI_MEMORY_SIZE +#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */ +#endif + +#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE +#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR +#endif + +/* iATU registers */ +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) +#define PCIE_ATU_REGION_INDEX3 (0x3 << 0) +#define PCIE_ATU_REGION_NUM 6 +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C + +/* DBI registers */ +#define PCIE_SRIOV 0x178 +#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ +#define PCIE_DBI_RO_WR_EN 0x8bc + +#define PCIE_LINK_CAP 0x7c +#define PCIE_LINK_SPEED_MASK 0xf +#define PCIE_LINK_WIDTH_MASK 0x3f0 +#define PCIE_LINK_STA 0x82 + +#define LTSSM_STATE_MASK 0x3f +#define LTSSM_PCIE_L0 0x11 /* L0 state */ + +#define PCIE_DBI_SIZE 0x100000 /* 1M */ + +#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31) +#define PCIE_LCTRL0_VF(vf) ((vf) << 22) +#define PCIE_LCTRL0_PF(pf) ((pf) << 16) +#define PCIE_LCTRL0_VF_ACTIVE (1 << 21) +#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \ + PCIE_LCTRL0_VF(vf) | \ + ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \ + PCIE_LCTRL0_CFG2_ENABLE) + +#define PCIE_NO_SRIOV_BAR_BASE 0x1000 + +#define PCIE_PF_NUM 2 +#define PCIE_VF_NUM 64 + +#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */ +#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */ +#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ +#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ + +struct ls_pcie { + int idx; + void __iomem *dbi; + void __iomem *va_cfg0; + void __iomem *va_cfg1; + int next_lut_index; + struct pci_controller hose; +}; + +struct ls_pcie_info { + unsigned long regs; + int pci_num; + u64 phys_base; + u64 cfg0_phys; + u64 cfg0_size; + u64 cfg1_phys; + u64 cfg1_size; + u64 mem_bus; + u64 mem_phys; + u64 mem_size; + u64 io_bus; + u64 io_phys; + u64 io_size; +}; + +#define SET_LS_PCIE_INFO(x, num) \ +{ \ + x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ + x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ + x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \ + CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ + x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \ + x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \ + CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ + x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \ + x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \ + x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \ + CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ + x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \ + x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \ + x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \ + CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ + x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \ + x.pci_num = num; \ +} + +#endif /* _PCIE_LAYERSCAPE_H_ */ diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c new file mode 100644 index 0000000..6de9355 --- /dev/null +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -0,0 +1,204 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * Layerscape PCIe driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_OF_BOARD_SETUP +#include +#include +#include "pcie_layerscape.h" + +#ifdef CONFIG_FSL_LSCH3 +/* + * Return next available LUT index. + */ +static int ls_pcie_next_lut_index(struct ls_pcie *pcie) +{ + if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) + return pcie->next_lut_index++; + else + return -ENOSPC; /* LUT is full */ +} + +/* returns the next available streamid for pcie, -errno if failed */ +static int ls_pcie_next_streamid(void) +{ + static int next_stream_id = FSL_PEX_STREAM_ID_START; + + if (next_stream_id > FSL_PEX_STREAM_ID_END) + return -EINVAL; + + return next_stream_id++; +} + +/* + * Program a single LUT entry + */ +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, + u32 streamid) +{ + void __iomem *lut; + + lut = pcie->dbi + PCIE_LUT_BASE; + + /* leave mask as all zeroes, want to match all bits */ + writel((devid << 16), lut + PCIE_LUT_UDR(index)); + writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index)); +} + +/* + * An msi-map is a property to be added to the pci controller + * node. It is a table, where each entry consists of 4 fields + * e.g.: + * + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count] + * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>; + */ +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, + u32 devid, u32 streamid) +{ + char pcie_path[19]; + u32 *prop; + u32 phandle; + int nodeoffset; + + /* find pci controller node */ + snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx", + (u64)pcie->dbi); + nodeoffset = fdt_path_offset(blob, pcie_path); + if (nodeoffset < 0) { + printf("\n%s: ERROR: unable to update PCIe node: %s\n", + __func__, pcie_path); + return; + } + + /* get phandle to MSI controller */ + prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0); + if (prop == NULL) { + printf("\n%s: ERROR: missing msi-parent: %s\n", __func__, + pcie_path); + return; + } + phandle = fdt32_to_cpu(*prop); + + /* set one msi-map row */ + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid); + fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle); + fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid); + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); +} + +static void fdt_fixup_pcie(void *blob) +{ + unsigned int found_multi = 0; + unsigned char header_type; + int index; + u32 streamid; + pci_dev_t dev, bdf; + int bus; + unsigned short id; + struct pci_controller *hose; + struct ls_pcie *pcie; + int i; + + for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) { + pcie = hose->priv_data; + for (bus = hose->first_busno; bus <= hose->last_busno; bus++) { + + for (dev = PCI_BDF(bus, 0, 0); + dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, + PCI_MAX_PCI_FUNCTIONS - 1); + dev += PCI_BDF(0, 0, 1)) { + + if (PCI_FUNC(dev) && !found_multi) + continue; + + pci_read_config_word(dev, PCI_VENDOR_ID, &id); + + pci_read_config_byte(dev, PCI_HEADER_TYPE, + &header_type); + + if ((id == 0xFFFF) || (id == 0x0000)) + continue; + + if (!PCI_FUNC(dev)) + found_multi = header_type & 0x80; + + streamid = ls_pcie_next_streamid(); + if (streamid < 0) { + debug("ERROR: no stream ids free\n"); + continue; + } + + index = ls_pcie_next_lut_index(pcie); + if (index < 0) { + debug("ERROR: no LUT indexes free\n"); + continue; + } + + /* the DT fixup must be relative to the hose first_busno */ + bdf = dev - PCI_BDF(hose->first_busno, 0, 0); + + /* map PCI b.d.f to streamID in LUT */ + ls_pcie_lut_set_mapping(pcie, index, bdf >> 8, + streamid); + + /* update msi-map in device tree */ + fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, + streamid); + } + } + } +} +#endif + +static void ft_pcie_ls_setup(void *blob, const char *pci_compat, + unsigned long ctrl_addr, enum srds_prtcl dev) +{ + int off; + + off = fdt_node_offset_by_compat_reg(blob, pci_compat, + (phys_addr_t)ctrl_addr); + if (off < 0) + return; + + if (!is_serdes_configured(dev)) + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +} + +/* Fixup Kernel DT for PCIe */ +void ft_pci_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCIE1 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); +#endif + +#ifdef CONFIG_PCIE2 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); +#endif + +#ifdef CONFIG_PCIE3 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3); +#endif + +#ifdef CONFIG_PCIE4 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4); +#endif + +#ifdef CONFIG_FSL_LSCH3 + fdt_fixup_pcie(blob); +#endif +} + +#else /* !CONFIG_OF_BOARD_SETUP */ +void ft_pci_setup(void *blob, bd_t *bd) +{ +} +#endif -- cgit v0.10.2 From 80afc63fc34286d363074d7779322c8720f346b5 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:17 +0800 Subject: pci: layerscape: add pci driver based on DM There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass Reviewed-by: York Sun diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 275b29b..692a398 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -71,4 +71,12 @@ config PCI_XILINX Enable support for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. +config PCIE_LAYERSCAPE + bool "Layerscape PCIe support" + depends on DM_PCI + help + Support Layerscape PCIe. The Layerscape SoC may have one or several + PCIe controllers. The PCIe may works in RC or EP mode according to + RCW[HOST_AGT_PEX] setting. + endif diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 0e3b494..62a0316 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -11,6 +11,7 @@ #include #include #include +#include #ifndef CONFIG_LS102XA #include #include @@ -19,6 +20,9 @@ #endif #include "pcie_layerscape.h" +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_PCI #ifdef CONFIG_LS102XA /* PEX1/2 Misc Ports Status Register */ #define LTSSM_STATE_SHIFT 20 @@ -506,3 +510,539 @@ void pci_init_board(void) { ls_pcie_init_board(0); } + +#else +LIST_HEAD(ls_pcie_list); + +static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) +{ + return in_le32(pcie->dbi + offset); +} + +static void dbi_writel(struct ls_pcie *pcie, unsigned int value, + unsigned int offset) +{ + out_le32(pcie->dbi + offset, value); +} + +static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset) +{ + if (pcie->big_endian) + return in_be32(pcie->ctrl + offset); + else + return in_le32(pcie->ctrl + offset); +} + +static void ctrl_writel(struct ls_pcie *pcie, unsigned int value, + unsigned int offset) +{ + if (pcie->big_endian) + out_be32(pcie->ctrl + offset, value); + else + out_le32(pcie->ctrl + offset, value); +} + +static int ls_pcie_ltssm(struct ls_pcie *pcie) +{ + u32 state; + uint svr; + + svr = get_svr(); + if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) { + state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx)); + state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; + } else { + state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK; + } + + return state; +} + +static int ls_pcie_link_up(struct ls_pcie *pcie) +{ + int ltssm; + + ltssm = ls_pcie_ltssm(pcie); + if (ltssm < LTSSM_PCIE_L0) + return 0; + + return 1; +} + +static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev) +{ + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, + PCIE_ATU_VIEWPORT); + dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET); +} + +static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev) +{ + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, + PCIE_ATU_VIEWPORT); + dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET); +} + +static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type, + u64 phys, u64 bus_addr, pci_size_t size) +{ + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT); + dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE); + dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE); + dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT); + dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET); + dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET); + dbi_writel(pcie, type, PCIE_ATU_CR1); + dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2); +} + +/* Use bar match mode and MEM type as default */ +static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, + int bar, u64 phys) +{ + dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT); + dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET); + dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET); + dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); + dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | + PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2); +} + +static void ls_pcie_dump_atu(struct ls_pcie *pcie) +{ + int i; + + for (i = 0; i < PCIE_ATU_REGION_NUM; i++) { + dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i, + PCIE_ATU_VIEWPORT); + debug("iATU%d:\n", i); + debug("\tLOWER PHYS 0x%08x\n", + dbi_readl(pcie, PCIE_ATU_LOWER_BASE)); + debug("\tUPPER PHYS 0x%08x\n", + dbi_readl(pcie, PCIE_ATU_UPPER_BASE)); + debug("\tLOWER BUS 0x%08x\n", + dbi_readl(pcie, PCIE_ATU_LOWER_TARGET)); + debug("\tUPPER BUS 0x%08x\n", + dbi_readl(pcie, PCIE_ATU_UPPER_TARGET)); + debug("\tLIMIT 0x%08x\n", + readl(pcie->dbi + PCIE_ATU_LIMIT)); + debug("\tCR1 0x%08x\n", + dbi_readl(pcie, PCIE_ATU_CR1)); + debug("\tCR2 0x%08x\n", + dbi_readl(pcie, PCIE_ATU_CR2)); + } +} + +static void ls_pcie_setup_atu(struct ls_pcie *pcie) +{ + struct pci_region *io, *mem, *pref; + unsigned long long offset = 0; + int idx = 0; + uint svr; + + svr = get_svr(); + if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) { + offset = LS1021_PCIE_SPACE_OFFSET + + LS1021_PCIE_SPACE_SIZE * pcie->idx; + } + + /* ATU 0 : OUTBOUND : CFG0 */ + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_CFG0, + pcie->cfg_res.start + offset, + 0, + fdt_resource_size(&pcie->cfg_res) / 2); + /* ATU 1 : OUTBOUND : CFG1 */ + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_CFG1, + pcie->cfg_res.start + offset + + fdt_resource_size(&pcie->cfg_res) / 2, + 0, + fdt_resource_size(&pcie->cfg_res) / 2); + + pci_get_regions(pcie->bus, &io, &mem, &pref); + idx = PCIE_ATU_REGION_INDEX1 + 1; + + if (io) + /* ATU : OUTBOUND : IO */ + ls_pcie_atu_outbound_set(pcie, idx++, + PCIE_ATU_TYPE_IO, + io->phys_start + offset, + io->bus_start, + io->size); + + if (mem) + /* ATU : OUTBOUND : MEM */ + ls_pcie_atu_outbound_set(pcie, idx++, + PCIE_ATU_TYPE_MEM, + mem->phys_start + offset, + mem->bus_start, + mem->size); + + if (pref) + /* ATU : OUTBOUND : pref */ + ls_pcie_atu_outbound_set(pcie, idx++, + PCIE_ATU_TYPE_MEM, + pref->phys_start + offset, + pref->bus_start, + pref->size); + + ls_pcie_dump_atu(pcie); +} + +/* Return 0 if the address is valid, -errno if not valid */ +static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf) +{ + struct udevice *bus = pcie->bus; + + if (!pcie->enabled) + return -ENXIO; + + if (PCI_BUS(bdf) < bus->seq) + return -EINVAL; + + if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie))) + return -EINVAL; + + if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0)) + return -EINVAL; + + return 0; +} + +void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf, + int offset) +{ + struct udevice *bus = pcie->bus; + u32 busdev; + + if (PCI_BUS(bdf) == bus->seq) + return pcie->dbi + offset; + + busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) | + PCIE_ATU_DEV(PCI_DEV(bdf)) | + PCIE_ATU_FUNC(PCI_FUNC(bdf)); + + if (PCI_BUS(bdf) == bus->seq + 1) { + ls_pcie_cfg0_set_busdev(pcie, busdev); + return pcie->cfg0 + offset; + } else { + ls_pcie_cfg1_set_busdev(pcie, busdev); + return pcie->cfg1 + offset; + } +} + +static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + struct ls_pcie *pcie = dev_get_priv(bus); + void *address; + + if (ls_pcie_addr_valid(pcie, bdf)) { + *valuep = pci_get_ff(size); + return 0; + } + + address = ls_pcie_conf_address(pcie, bdf, offset); + + switch (size) { + case PCI_SIZE_8: + *valuep = readb(address); + return 0; + case PCI_SIZE_16: + *valuep = readw(address); + return 0; + case PCI_SIZE_32: + *valuep = readl(address); + return 0; + default: + return -EINVAL; + } +} + +static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + struct ls_pcie *pcie = dev_get_priv(bus); + void *address; + + if (ls_pcie_addr_valid(pcie, bdf)) + return 0; + + address = ls_pcie_conf_address(pcie, bdf, offset); + + switch (size) { + case PCI_SIZE_8: + writeb(value, address); + return 0; + case PCI_SIZE_16: + writew(value, address); + return 0; + case PCI_SIZE_32: + writel(value, address); + return 0; + default: + return -EINVAL; + } +} + +/* Clear multi-function bit */ +static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) +{ + writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE); +} + +/* Fix class value */ +static void ls_pcie_fix_class(struct ls_pcie *pcie) +{ + writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); +} + +/* Drop MSG TLP except for Vendor MSG */ +static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) +{ + u32 val; + + val = dbi_readl(pcie, PCIE_STRFMR1); + val &= 0xDFFFFFFF; + dbi_writel(pcie, val, PCIE_STRFMR1); +} + +/* Disable all bars in RC mode */ +static void ls_pcie_disable_bars(struct ls_pcie *pcie) +{ + u32 sriov; + + sriov = in_le32(pcie->dbi + PCIE_SRIOV); + + /* + * TODO: For PCIe controller with SRIOV, the method to disable bars + * is different and more complex, so will add later. + */ + if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) + return; + + dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0); + dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1); + dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1); +} + +static void ls_pcie_setup_ctrl(struct ls_pcie *pcie) +{ + ls_pcie_setup_atu(pcie); + + dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN); + ls_pcie_fix_class(pcie); + ls_pcie_clear_multifunction(pcie); + ls_pcie_drop_msg_tlp(pcie); + dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN); + + ls_pcie_disable_bars(pcie); +} + +static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie) +{ + u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE; + + /* ATU 0 : INBOUND : map BAR0 */ + ls_pcie_atu_inbound_set(pcie, 0, 0, phys); + /* ATU 1 : INBOUND : map BAR1 */ + phys += PCIE_BAR1_SIZE; + ls_pcie_atu_inbound_set(pcie, 1, 1, phys); + /* ATU 2 : INBOUND : map BAR2 */ + phys += PCIE_BAR2_SIZE; + ls_pcie_atu_inbound_set(pcie, 2, 2, phys); + /* ATU 3 : INBOUND : map BAR4 */ + phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE; + ls_pcie_atu_inbound_set(pcie, 3, 4, phys); + + /* ATU 0 : OUTBOUND : map MEM */ + ls_pcie_atu_outbound_set(pcie, 0, + PCIE_ATU_TYPE_MEM, + pcie->cfg_res.start, + 0, + CONFIG_SYS_PCI_MEMORY_SIZE); +} + +/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ +static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) +{ + /* The least inbound window is 4KiB */ + if (size < 4 * 1024) + return; + + switch (bar) { + case 0: + writel(size - 1, bar_base + PCI_BASE_ADDRESS_0); + break; + case 1: + writel(size - 1, bar_base + PCI_BASE_ADDRESS_1); + break; + case 2: + writel(size - 1, bar_base + PCI_BASE_ADDRESS_2); + writel(0, bar_base + PCI_BASE_ADDRESS_3); + break; + case 4: + writel(size - 1, bar_base + PCI_BASE_ADDRESS_4); + writel(0, bar_base + PCI_BASE_ADDRESS_5); + break; + default: + break; + } +} + +static void ls_pcie_ep_setup_bars(void *bar_base) +{ + /* BAR0 - 32bit - 4K configuration */ + ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); + /* BAR1 - 32bit - 8K MSIX*/ + ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); + /* BAR2 - 64bit - 4K MEM desciptor */ + ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); + /* BAR4 - 64bit - 1M MEM*/ + ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); +} + +static void ls_pcie_setup_ep(struct ls_pcie *pcie) +{ + u32 sriov; + + sriov = readl(pcie->dbi + PCIE_SRIOV); + if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) { + int pf, vf; + + for (pf = 0; pf < PCIE_PF_NUM; pf++) { + for (vf = 0; vf <= PCIE_VF_NUM; vf++) { + ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf), + PCIE_PF_VF_CTRL); + + ls_pcie_ep_setup_bars(pcie->dbi); + ls_pcie_ep_setup_atu(pcie); + } + } + /* Disable CFG2 */ + ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); + } else { + ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); + ls_pcie_ep_setup_atu(pcie); + } +} + +static int ls_pcie_probe(struct udevice *dev) +{ + struct ls_pcie *pcie = dev_get_priv(dev); + const void *fdt = gd->fdt_blob; + int node = dev->of_offset; + u8 header_type; + u16 link_sta; + bool ep_mode; + int ret; + + pcie->bus = dev; + + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", + "dbi", &pcie->dbi_res); + if (ret) { + printf("ls-pcie: resource \"dbi\" not found\n"); + return ret; + } + + pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE; + + list_add(&pcie->list, &ls_pcie_list); + + pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); + if (!pcie->enabled) { + printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); + return 0; + } + + pcie->dbi = map_physmem(pcie->dbi_res.start, + fdt_resource_size(&pcie->dbi_res), + MAP_NOCACHE); + + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", + "lut", &pcie->lut_res); + if (!ret) + pcie->lut = map_physmem(pcie->lut_res.start, + fdt_resource_size(&pcie->lut_res), + MAP_NOCACHE); + + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", + "ctrl", &pcie->ctrl_res); + if (!ret) + pcie->ctrl = map_physmem(pcie->ctrl_res.start, + fdt_resource_size(&pcie->ctrl_res), + MAP_NOCACHE); + if (!pcie->ctrl) + pcie->ctrl = pcie->lut; + + if (!pcie->ctrl) { + printf("%s: NOT find CTRL\n", dev->name); + return -1; + } + + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", + "config", &pcie->cfg_res); + if (ret) { + printf("%s: resource \"config\" not found\n", dev->name); + return ret; + } + + pcie->cfg0 = map_physmem(pcie->cfg_res.start, + fdt_resource_size(&pcie->cfg_res), + MAP_NOCACHE); + pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2; + + pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian"); + + debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n", + dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut, + (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0, + pcie->big_endian); + + header_type = readb(pcie->dbi + PCI_HEADER_TYPE); + ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; + printf("PCIe%u: %s %s", pcie->idx, dev->name, + ep_mode ? "Endpoint" : "Root Complex"); + + if (ep_mode) + ls_pcie_setup_ep(pcie); + else + ls_pcie_setup_ctrl(pcie); + + if (!ls_pcie_link_up(pcie)) { + /* Let the user know there's no PCIe link */ + printf(": no link\n"); + return 0; + } + + /* Print the negotiated PCIe link width */ + link_sta = readw(pcie->dbi + PCIE_LINK_STA); + printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4, + link_sta & PCIE_LINK_SPEED_MASK); + + return 0; +} + +static const struct dm_pci_ops ls_pcie_ops = { + .read_config = ls_pcie_read_config, + .write_config = ls_pcie_write_config, +}; + +static const struct udevice_id ls_pcie_ids[] = { + { .compatible = "fsl,ls-pcie" }, + { } +}; + +U_BOOT_DRIVER(pci_layerscape) = { + .name = "pci_layerscape", + .id = UCLASS_PCI, + .of_match = ls_pcie_ids, + .ops = &ls_pcie_ops, + .probe = ls_pcie_probe, + .priv_auto_alloc_size = sizeof(struct ls_pcie), +}; +#endif /* CONFIG_DM_PCI */ diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 159e5ce..5e893d4 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -86,6 +86,7 @@ #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ +#ifndef CONFIG_DM_PCI struct ls_pcie { int idx; void __iomem *dbi; @@ -132,4 +133,59 @@ struct ls_pcie_info { x.pci_num = num; \ } +#else /* CONFIG_DM_PCI */ + +#include + +/* LUT registers */ +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) +#define PCIE_LUT_ENABLE (1 << 31) +#define PCIE_LUT_ENTRY_COUNT 32 + +/* PF Controll registers */ +#define PCIE_PF_VF_CTRL 0x7F8 +#define PCIE_PF_DBG 0x7FC + +#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx)) +#define PCIE_SYS_BASE_ADDR 0x3400000 +#define PCIE_CCSR_SIZE 0x0100000 + +/* CS2 */ +#define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */ + +#define SVR_LS102XA 0 +#define SVR_VAR_PER_SHIFT 8 +#define SVR_LS102XA_MASK 0x700 + +/* LS1021a PCIE space */ +#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL +#define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL + +/* LS1021a PEX1/2 Misc Ports Status Register */ +#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) +#define LS1021_LTSSM_STATE_SHIFT 20 + +struct ls_pcie { + int idx; + struct list_head list; + struct udevice *bus; + struct fdt_resource dbi_res; + struct fdt_resource lut_res; + struct fdt_resource ctrl_res; + struct fdt_resource cfg_res; + void __iomem *dbi; + void __iomem *lut; + void __iomem *ctrl; + void __iomem *cfg0; + void __iomem *cfg1; + bool big_endian; + bool enabled; + int next_lut_index; + struct pci_controller hose; +}; + +extern struct list_head ls_pcie_list; + +#endif /* CONFIG_DM_PCI */ #endif /* _PCIE_LAYERSCAPE_H_ */ diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 6de9355..c30a330 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -37,7 +37,11 @@ static int ls_pcie_next_streamid(void) return next_stream_id++; } +#endif + +#ifndef CONFIG_DM_PCI +#ifdef CONFIG_FSL_LSCH3 /* * Program a single LUT entry */ @@ -197,6 +201,152 @@ void ft_pci_setup(void *blob, bd_t *bd) #endif } +#else /* CONFIG_DM_PCI */ + +#ifdef CONFIG_FSL_LSCH3 +static void lut_writel(struct ls_pcie *pcie, unsigned int value, + unsigned int offset) +{ + if (pcie->big_endian) + out_be32(pcie->lut + offset, value); + else + out_le32(pcie->lut + offset, value); +} + +/* + * Program a single LUT entry + */ +static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, + u32 streamid) +{ + /* leave mask as all zeroes, want to match all bits */ + lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index)); + lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index)); +} + +/* + * An msi-map is a property to be added to the pci controller + * node. It is a table, where each entry consists of 4 fields + * e.g.: + * + * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count] + * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>; + */ +static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, + u32 devid, u32 streamid) +{ + u32 *prop; + u32 phandle; + int nodeoffset; + + /* find pci controller node */ + nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", + pcie->dbi_res.start); + if (nodeoffset < 0) { +#ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */ + nodeoffset = fdt_node_offset_by_compat_reg(blob, + FSL_PCIE_COMPAT, pcie->dbi_res.start); + if (nodeoffset < 0) + return; +#else + return; +#endif + } + + /* get phandle to MSI controller */ + prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0); + if (prop == NULL) { + debug("\n%s: ERROR: missing msi-parent: PCIe%d\n", + __func__, pcie->idx); + return; + } + phandle = fdt32_to_cpu(*prop); + + /* set one msi-map row */ + fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid); + fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle); + fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid); + fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); +} + +static void fdt_fixup_pcie(void *blob) +{ + struct udevice *dev, *bus; + struct ls_pcie *pcie; + int streamid; + int index; + pci_dev_t bdf; + + /* Scan all known buses */ + for (pci_find_first_device(&dev); + dev; + pci_find_next_device(&dev)) { + for (bus = dev; device_is_on_pci_bus(bus);) + bus = bus->parent; + pcie = dev_get_priv(bus); + + streamid = ls_pcie_next_streamid(); + if (streamid < 0) { + debug("ERROR: no stream ids free\n"); + continue; + } + + index = ls_pcie_next_lut_index(pcie); + if (index < 0) { + debug("ERROR: no LUT indexes free\n"); + continue; + } + + /* the DT fixup must be relative to the hose first_busno */ + bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0); + /* map PCI b.d.f to streamID in LUT */ + ls_pcie_lut_set_mapping(pcie, index, bdf >> 8, + streamid); + /* update msi-map in device tree */ + fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, + streamid); + } +} +#endif + +static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) +{ + int off; + + off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", + pcie->dbi_res.start); + if (off < 0) { +#ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */ + off = fdt_node_offset_by_compat_reg(blob, + FSL_PCIE_COMPAT, + pcie->dbi_res.start); + if (off < 0) + return; +#else + return; +#endif + } + + if (pcie->enabled) + fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0); + else + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +} + +/* Fixup Kernel DT for PCIe */ +void ft_pci_setup(void *blob, bd_t *bd) +{ + struct ls_pcie *pcie; + + list_for_each_entry(pcie, &ls_pcie_list, list) + ft_pcie_ls_setup(blob, pcie); + +#ifdef CONFIG_FSL_LSCH3 + fdt_fixup_pcie(blob); +#endif +} +#endif /* CONFIG_DM_PCI */ + #else /* !CONFIG_OF_BOARD_SETUP */ void ft_pci_setup(void *blob, bd_t *bd) { -- cgit v0.10.2 From 8808aeb7a93dc36973f3a421e00d8e32318b0352 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:18 +0800 Subject: arm: ls1021a: Enable PCIe in defconfigs The patch enables PCIe in ls1021a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 21464cb..be39889 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -13,3 +13,7 @@ CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 1369fe6..f72bd4e 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -16,3 +16,7 @@ CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 7b1bcc3..431000d 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -28,7 +28,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_USB=y @@ -37,3 +36,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index fd5b3b2..e91bd2a 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -29,7 +29,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_USB=y @@ -38,3 +37,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 8bb518a..8fb0f36 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -43,7 +43,6 @@ CONFIG_SYS_FSL_DDR3=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -51,3 +50,7 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 8719a35..8544810 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -31,7 +31,6 @@ CONFIG_DM=y CONFIG_SYS_FSL_DDR3=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -41,3 +40,7 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_OF_LIBFDT=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 1972fd0..5d2e038 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -29,7 +29,6 @@ CONFIG_DM=y CONFIG_SYS_FSL_DDR3=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_USB=y @@ -38,3 +37,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index dd44140..c7f5a8b 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -30,7 +30,6 @@ CONFIG_DM=y CONFIG_SYS_FSL_DDR3=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_USB=y @@ -39,3 +38,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 24443e2..f72236c 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -35,7 +35,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y @@ -45,3 +44,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 6f14a03..29b0a12 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -41,10 +41,13 @@ CONFIG_DM=y CONFIG_SYS_FSL_DDR3=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 49bcba0..34de544 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -45,7 +45,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y @@ -55,3 +54,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 348958b..2bd9298 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -30,7 +30,6 @@ CONFIG_CMD_FAT=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -40,3 +39,7 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_OF_LIBFDT=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 2b351aa..98d7a5d 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -28,7 +28,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_USB=y @@ -36,3 +35,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index daede61..9443598 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -29,7 +29,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_USB=y @@ -37,3 +36,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 05793e9..ec35138 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -35,7 +35,6 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y @@ -45,3 +44,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 2d32e96..3e05a25 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -44,7 +44,6 @@ CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -54,3 +53,7 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_OF_LIBFDT=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 1c79d58..5297361 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -40,7 +40,6 @@ CONFIG_CMD_FAT=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -48,3 +47,7 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 80329fc..d465363 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -45,7 +45,6 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y @@ -55,3 +54,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index ae8ee24..e270f42 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -232,31 +232,12 @@ #endif /* PCIe */ -#define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ -/* Use common FSL Layerscape PCIe code */ -#define CONFIG_PCIE_LAYERSCAPE #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ - #ifdef CONFIG_PCI -#define CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6f857a7..f1d1975 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -500,24 +500,8 @@ unsigned long get_board_ddr_clk(void); /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ - #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b48cd00..6aff6b5 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -370,24 +370,8 @@ /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ - #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI -- cgit v0.10.2 From 41873d1571613230faab17286fe40e1b192e6c2d Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:19 +0800 Subject: arm: ls1012a: Enable PCIe and E1000 in defconfigs The patch enables PCIe and E1000 in ls1012a defconfigs and removes unused PCIe related macro defines Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 9b2ca4f..b00226f 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -30,9 +30,14 @@ CONFIG_DM=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y +CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index e74141f..c2d8b64 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -31,7 +31,6 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y @@ -39,3 +38,7 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index d5ed70f..f569ddc 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -31,7 +31,6 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y @@ -39,3 +38,7 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index b5b4d7e..4d9a814 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -154,24 +154,8 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ - #define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index f35fd31..23214e7 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -67,24 +67,8 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ - #define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI -- cgit v0.10.2 From be6430dc7a4be7818a924050c10fe5336231667e Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:20 +0800 Subject: armv8: ls1043a: Enable PCIe and E1000 in defconfigs The patch enables PCIe and E1000 in ls1043a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 5507982..a36bdeb 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y @@ -32,3 +31,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index ec911e0..a564a2f 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_SPI=y @@ -34,3 +33,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index bb3466f..45b2c66 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y @@ -46,3 +45,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 5aa058b..8f74cc8 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -25,7 +25,6 @@ CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SYS_FSL_DDR3=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y @@ -33,3 +32,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 4e07ff3..b1a5230 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y @@ -35,3 +34,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 5c20633..eb23c66 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y @@ -46,3 +45,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 707dcb5..62ebcb1 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -39,7 +39,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y @@ -47,3 +46,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index d429017..5b48977 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -20,7 +20,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y @@ -30,3 +29,9 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 9fa8921..51cabc7 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -20,7 +20,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y @@ -28,3 +27,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 73e6603..b4aaaa1 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y @@ -42,3 +41,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 171ec37..5587860 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y @@ -42,3 +41,9 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 3e70464..ff521ab 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -118,27 +118,10 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ - #ifdef CONFIG_PCI #define CONFIG_NET_MULTI -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI #endif -- cgit v0.10.2 From 831b4e0cb6a752e7a0a7d2cfe3588e2862ab5e00 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:21 +0800 Subject: armv8: ls1046a: Enable PCIe and E1000 in defconfigs The patch enables PCIe and E1000 in ls1046a related defconfigs. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 5636885..5af91b6 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -25,3 +25,9 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index ebb1b5e..27b733c 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -30,3 +30,9 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index bdb8433..809fb3b 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -28,3 +28,9 @@ CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 9995047..2f90e4f 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -30,3 +30,9 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 4fccce4..175b2bf 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -32,3 +32,9 @@ CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 38117f2..0b29796 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -27,3 +27,9 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 765868a..2a72132 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -24,3 +24,9 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index c74e007..d11792e 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -27,3 +27,9 @@ CONFIG_SPI_FLASH=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y -- cgit v0.10.2 From 2acfda1292ecc1942cdcc4cae0e719ebdbd5d7d7 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:22 +0800 Subject: armv8: ls2080a: Enable PCIe in defconfigs The patch enables PCIe in ls2080a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index e18dcbd..f613efa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -107,14 +107,6 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL -/* LUT registers */ -#define PCIE_LUT_BASE 0x80000 -#define PCIE_LUT_LCTRL0 0x7F8 -#define PCIE_LUT_DBG 0x7FC -#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) -#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) -#define PCIE_LUT_ENABLE (1 << 31) -#define PCIE_LUT_ENTRY_COUNT 32 /* Device Configuration */ #define DCFG_BASE 0x01e00000 diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index b443be3..047c2c1 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -21,7 +21,6 @@ CONFIG_DM=y CONFIG_DM_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y @@ -33,3 +32,7 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index d26f1b6..97a2527 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -21,7 +21,6 @@ CONFIG_DM=y CONFIG_DM_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y @@ -31,3 +30,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 91b3b57..db1642f 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -30,7 +30,6 @@ CONFIG_DM=y CONFIG_DM_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y @@ -40,3 +39,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 803d3bb..8ba3922 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -22,7 +22,6 @@ CONFIG_DM=y CONFIG_DM_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y @@ -32,3 +31,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 0e6f4dc..f917035 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -21,7 +21,6 @@ CONFIG_DM=y CONFIG_DM_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y @@ -33,3 +32,7 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index f22c625..8a7acc9 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -21,7 +21,6 @@ CONFIG_DM=y CONFIG_DM_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y @@ -31,3 +30,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index f42f00a..658b4b4 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -27,7 +27,6 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y -CONFIG_PCI=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y @@ -35,3 +34,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 2cae966..805457d 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -171,29 +171,7 @@ unsigned long long get_qixis_addr(void); #endif /* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ -#ifdef CONFIG_LS2080A #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" -#endif - -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ /* Command line configuration */ #define CONFIG_CMD_ENV diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 37d5704..171b77f 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -347,7 +347,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_FSL_MEMAC -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 713e86b..feeb962 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -291,7 +291,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_FSL_MEMAC -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW -- cgit v0.10.2 From 9fa2a4fc8b60949bd2b66a57c119acbf8df3aaae Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 13 Dec 2016 14:54:23 +0800 Subject: pci: layerscape: remove unnecessary legacy code All Layerscape SoCs have supported new PCIe driver based on DM. The lagecy PCIe driver code is unused and can be removed. Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass Reviewed-by: York Sun diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 62a0316..90b9fe2 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -12,506 +12,10 @@ #include #include #include -#ifndef CONFIG_LS102XA -#include -#include -#else -#include -#endif #include "pcie_layerscape.h" DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_DM_PCI -#ifdef CONFIG_LS102XA -/* PEX1/2 Misc Ports Status Register */ -#define LTSSM_STATE_SHIFT 20 - -static int ls_pcie_link_state(struct ls_pcie *pcie) -{ - u32 state; - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - - state = in_be32(&scfg->pexmscportsr[pcie->idx]); - state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; - if (state < LTSSM_PCIE_L0) { - debug("....PCIe link error. LTSSM=0x%02x.\n", state); - return 0; - } - - return 1; -} -#else -static int ls_pcie_link_state(struct ls_pcie *pcie) -{ - u32 state; - - state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) & - LTSSM_STATE_MASK; - if (state < LTSSM_PCIE_L0) { - debug("....PCIe link error. LTSSM=0x%02x.\n", state); - return 0; - } - - return 1; -} -#endif - -static int ls_pcie_link_up(struct ls_pcie *pcie) -{ - int state; - u32 cap; - - state = ls_pcie_link_state(pcie); - if (state) - return state; - - /* Try to download speed to gen1 */ - cap = readl(pcie->dbi + PCIE_LINK_CAP); - writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP); - /* - * Notice: the following delay has critical impact on link training - * if too short (<30ms) the link doesn't get up. - */ - mdelay(100); - state = ls_pcie_link_state(pcie); - if (state) - return state; - - writel(cap, pcie->dbi + PCIE_LINK_CAP); - - return 0; -} - -static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev) -{ - writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, - pcie->dbi + PCIE_ATU_VIEWPORT); - writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET); -} - -static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev) -{ - writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, - pcie->dbi + PCIE_ATU_VIEWPORT); - writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET); -} - -static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type, - u64 phys, u64 bus_addr, pci_size_t size) -{ - writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT); - writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE); - writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE); - writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT); - writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET); - writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET); - writel(type, pcie->dbi + PCIE_ATU_CR1); - writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2); -} - -/* Use bar match mode and MEM type as default */ -static void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx, - int bar, u64 phys) -{ - writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT); - writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET); - writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET); - writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1); - writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | - PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2); -} - -static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info) -{ -#ifdef DEBUG - int i; -#endif - - /* ATU 0 : OUTBOUND : CFG0 */ - ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_CFG0, - info->cfg0_phys, - 0, - info->cfg0_size); - /* ATU 1 : OUTBOUND : CFG1 */ - ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, - PCIE_ATU_TYPE_CFG1, - info->cfg1_phys, - 0, - info->cfg1_size); - /* ATU 2 : OUTBOUND : MEM */ - ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2, - PCIE_ATU_TYPE_MEM, - info->mem_phys, - info->mem_bus, - info->mem_size); - /* ATU 3 : OUTBOUND : IO */ - ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3, - PCIE_ATU_TYPE_IO, - info->io_phys, - info->io_bus, - info->io_size); - -#ifdef DEBUG - for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) { - writel(PCIE_ATU_REGION_OUTBOUND | i, - pcie->dbi + PCIE_ATU_VIEWPORT); - debug("iATU%d:\n", i); - debug("\tLOWER PHYS 0x%08x\n", - readl(pcie->dbi + PCIE_ATU_LOWER_BASE)); - debug("\tUPPER PHYS 0x%08x\n", - readl(pcie->dbi + PCIE_ATU_UPPER_BASE)); - debug("\tLOWER BUS 0x%08x\n", - readl(pcie->dbi + PCIE_ATU_LOWER_TARGET)); - debug("\tUPPER BUS 0x%08x\n", - readl(pcie->dbi + PCIE_ATU_UPPER_TARGET)); - debug("\tLIMIT 0x%08x\n", - readl(pcie->dbi + PCIE_ATU_LIMIT)); - debug("\tCR1 0x%08x\n", - readl(pcie->dbi + PCIE_ATU_CR1)); - debug("\tCR2 0x%08x\n", - readl(pcie->dbi + PCIE_ATU_CR2)); - } -#endif -} - -int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) -{ - /* Do not skip controller */ - return 0; -} - -static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d) -{ - if (PCI_DEV(d) > 0) - return -EINVAL; - - /* Controller does not support multi-function in RC mode */ - if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0)) - return -EINVAL; - - return 0; -} - -static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d, - int where, u32 *val) -{ - struct ls_pcie *pcie = hose->priv_data; - u32 busdev, *addr; - - if (ls_pcie_addr_valid(hose, d)) { - *val = 0xffffffff; - return 0; - } - - if (PCI_BUS(d) == hose->first_busno) { - addr = pcie->dbi + (where & ~0x3); - } else { - busdev = PCIE_ATU_BUS(PCI_BUS(d)) | - PCIE_ATU_DEV(PCI_DEV(d)) | - PCIE_ATU_FUNC(PCI_FUNC(d)); - - if (PCI_BUS(d) == hose->first_busno + 1) { - ls_pcie_cfg0_set_busdev(pcie, busdev); - addr = pcie->va_cfg0 + (where & ~0x3); - } else { - ls_pcie_cfg1_set_busdev(pcie, busdev); - addr = pcie->va_cfg1 + (where & ~0x3); - } - } - - *val = readl(addr); - - return 0; -} - -static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d, - int where, u32 val) -{ - struct ls_pcie *pcie = hose->priv_data; - u32 busdev, *addr; - - if (ls_pcie_addr_valid(hose, d)) - return -EINVAL; - - if (PCI_BUS(d) == hose->first_busno) { - addr = pcie->dbi + (where & ~0x3); - } else { - busdev = PCIE_ATU_BUS(PCI_BUS(d)) | - PCIE_ATU_DEV(PCI_DEV(d)) | - PCIE_ATU_FUNC(PCI_FUNC(d)); - - if (PCI_BUS(d) == hose->first_busno + 1) { - ls_pcie_cfg0_set_busdev(pcie, busdev); - addr = pcie->va_cfg0 + (where & ~0x3); - } else { - ls_pcie_cfg1_set_busdev(pcie, busdev); - addr = pcie->va_cfg1 + (where & ~0x3); - } - } - - writel(val, addr); - - return 0; -} - -static void ls_pcie_setup_ctrl(struct ls_pcie *pcie, - struct ls_pcie_info *info) -{ - struct pci_controller *hose = &pcie->hose; - pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); - - ls_pcie_setup_atu(pcie, info); - - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0); - - /* program correct class for RC */ - writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN); - pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE, - PCI_CLASS_BRIDGE_PCI); -#ifndef CONFIG_LS102XA - writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN); -#endif -} - -static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie, - struct ls_pcie_info *info) -{ - u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE; - - /* ATU 0 : INBOUND : map BAR0 */ - ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX0, 0, phys); - /* ATU 1 : INBOUND : map BAR1 */ - phys += PCIE_BAR1_SIZE; - ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX1, 1, phys); - /* ATU 2 : INBOUND : map BAR2 */ - phys += PCIE_BAR2_SIZE; - ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX2, 2, phys); - /* ATU 3 : INBOUND : map BAR4 */ - phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE; - ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX3, 4, phys); - - /* ATU 0 : OUTBOUND : map 4G MEM */ - ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_MEM, - info->phys_base, - 0, - 4 * 1024 * 1024 * 1024ULL); -} - -/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ -static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) -{ - if (size < 4 * 1024) - return; - - switch (bar) { - case 0: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_0); - break; - case 1: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_1); - break; - case 2: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_2); - writel(0, bar_base + PCI_BASE_ADDRESS_3); - break; - case 4: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_4); - writel(0, bar_base + PCI_BASE_ADDRESS_5); - break; - default: - break; - } -} - -static void ls_pcie_ep_setup_bars(void *bar_base) -{ - /* BAR0 - 32bit - 4K configuration */ - ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); - /* BAR1 - 32bit - 8K MSIX*/ - ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); - /* BAR2 - 64bit - 4K MEM desciptor */ - ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); - /* BAR4 - 64bit - 1M MEM*/ - ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); -} - -static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info) -{ - struct pci_controller *hose = &pcie->hose; - pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); - int sriov; - - sriov = pci_hose_find_ext_capability(hose, dev, PCI_EXT_CAP_ID_SRIOV); - if (sriov) { - int pf, vf; - - for (pf = 0; pf < PCIE_PF_NUM; pf++) { - for (vf = 0; vf <= PCIE_VF_NUM; vf++) { -#ifndef CONFIG_LS102XA - writel(PCIE_LCTRL0_VAL(pf, vf), - pcie->dbi + PCIE_LUT_BASE + - PCIE_LUT_LCTRL0); -#endif - ls_pcie_ep_setup_bars(pcie->dbi); - ls_pcie_ep_setup_atu(pcie, info); - } - } - - /* Disable CFG2 */ -#ifndef CONFIG_LS102XA - writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0); -#endif - } else { - ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); - ls_pcie_ep_setup_atu(pcie, info); - } -} - -int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info) -{ - struct ls_pcie *pcie; - struct pci_controller *hose; - int num = dev - PCIE1; - pci_dev_t pdev = PCI_BDF(busno, 0, 0); - int i, linkup, ep_mode; - u8 header_type; - u16 temp16; - - if (!is_serdes_configured(dev)) { - printf("PCIe%d: disabled\n", num + 1); - return busno; - } - - pcie = malloc(sizeof(*pcie)); - if (!pcie) - return busno; - memset(pcie, 0, sizeof(*pcie)); - - hose = &pcie->hose; - hose->priv_data = pcie; - hose->first_busno = busno; - pcie->idx = num; - pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE); - pcie->va_cfg0 = map_physmem(info->cfg0_phys, - info->cfg0_size, - MAP_NOCACHE); - pcie->va_cfg1 = map_physmem(info->cfg1_phys, - info->cfg1_size, - MAP_NOCACHE); - pcie->next_lut_index = 0; - - /* outbound memory */ - pci_set_region(&hose->regions[0], - (pci_size_t)info->mem_bus, - (phys_size_t)info->mem_phys, - (pci_size_t)info->mem_size, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(&hose->regions[1], - (pci_size_t)info->io_bus, - (phys_size_t)info->io_phys, - (pci_size_t)info->io_size, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(&hose->regions[2], - CONFIG_SYS_PCI_MEMORY_BUS, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_SYS_MEMORY); - - hose->region_count = 3; - - for (i = 0; i < hose->region_count; i++) - debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", - i, - (u64)hose->regions[i].phys_start, - (u64)hose->regions[i].bus_start, - (u64)hose->regions[i].size, - hose->regions[i].flags); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - ls_pcie_read_config, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - ls_pcie_write_config); - - pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type); - ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; - printf("PCIe%u: %s ", info->pci_num, - ep_mode ? "Endpoint" : "Root Complex"); - - if (ep_mode) - ls_pcie_setup_ep(pcie, info); - else - ls_pcie_setup_ctrl(pcie, info); - - linkup = ls_pcie_link_up(pcie); - - if (!linkup) { - /* Let the user know there's no PCIe link */ - printf("no link, regs @ 0x%lx\n", info->regs); - hose->last_busno = hose->first_busno; - return busno; - } - - /* Print the negotiated PCIe link width */ - pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16); - printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4, - (temp16 & 0xf), info->regs); - - if (ep_mode) - return busno; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - printf("PCIe%x: Bus %02x - %02x\n", - info->pci_num, hose->first_busno, hose->last_busno); - - return hose->last_busno + 1; -} - -int ls_pcie_init_board(int busno) -{ - struct ls_pcie_info info; - -#ifdef CONFIG_PCIE1 - SET_LS_PCIE_INFO(info, 1); - busno = ls_pcie_init_ctrl(busno, PCIE1, &info); -#endif - -#ifdef CONFIG_PCIE2 - SET_LS_PCIE_INFO(info, 2); - busno = ls_pcie_init_ctrl(busno, PCIE2, &info); -#endif - -#ifdef CONFIG_PCIE3 - SET_LS_PCIE_INFO(info, 3); - busno = ls_pcie_init_ctrl(busno, PCIE3, &info); -#endif - -#ifdef CONFIG_PCIE4 - SET_LS_PCIE_INFO(info, 4); - busno = ls_pcie_init_ctrl(busno, PCIE4, &info); -#endif - - return busno; -} - -void pci_init_board(void) -{ - ls_pcie_init_board(0); -} - -#else LIST_HEAD(ls_pcie_list); static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) @@ -1045,4 +549,3 @@ U_BOOT_DRIVER(pci_layerscape) = { .probe = ls_pcie_probe, .priv_auto_alloc_size = sizeof(struct ls_pcie), }; -#endif /* CONFIG_DM_PCI */ diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 5e893d4..1e635ef 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -8,6 +8,7 @@ #ifndef _PCIE_LAYERSCAPE_H_ #define _PCIE_LAYERSCAPE_H_ #include +#include #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE @@ -86,57 +87,6 @@ #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ -#ifndef CONFIG_DM_PCI -struct ls_pcie { - int idx; - void __iomem *dbi; - void __iomem *va_cfg0; - void __iomem *va_cfg1; - int next_lut_index; - struct pci_controller hose; -}; - -struct ls_pcie_info { - unsigned long regs; - int pci_num; - u64 phys_base; - u64 cfg0_phys; - u64 cfg0_size; - u64 cfg1_phys; - u64 cfg1_size; - u64 mem_bus; - u64 mem_phys; - u64 mem_size; - u64 io_bus; - u64 io_phys; - u64 io_size; -}; - -#define SET_LS_PCIE_INFO(x, num) \ -{ \ - x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ - x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ - x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \ - CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ - x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \ - x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \ - CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ - x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \ - x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \ - CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ - x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \ - CONFIG_SYS_PCIE##num##_PHYS_ADDR; \ - x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \ - x.pci_num = num; \ -} - -#else /* CONFIG_DM_PCI */ - -#include - /* LUT registers */ #define PCIE_LUT_UDR(n) (0x800 + (n) * 8) #define PCIE_LUT_LDR(n) (0x804 + (n) * 8) @@ -187,5 +137,4 @@ struct ls_pcie { extern struct list_head ls_pcie_list; -#endif /* CONFIG_DM_PCI */ #endif /* _PCIE_LAYERSCAPE_H_ */ diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index c30a330..47e621f 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -37,173 +37,7 @@ static int ls_pcie_next_streamid(void) return next_stream_id++; } -#endif - -#ifndef CONFIG_DM_PCI - -#ifdef CONFIG_FSL_LSCH3 -/* - * Program a single LUT entry - */ -static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, - u32 streamid) -{ - void __iomem *lut; - - lut = pcie->dbi + PCIE_LUT_BASE; - - /* leave mask as all zeroes, want to match all bits */ - writel((devid << 16), lut + PCIE_LUT_UDR(index)); - writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index)); -} - -/* - * An msi-map is a property to be added to the pci controller - * node. It is a table, where each entry consists of 4 fields - * e.g.: - * - * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count] - * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>; - */ -static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, - u32 devid, u32 streamid) -{ - char pcie_path[19]; - u32 *prop; - u32 phandle; - int nodeoffset; - - /* find pci controller node */ - snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx", - (u64)pcie->dbi); - nodeoffset = fdt_path_offset(blob, pcie_path); - if (nodeoffset < 0) { - printf("\n%s: ERROR: unable to update PCIe node: %s\n", - __func__, pcie_path); - return; - } - - /* get phandle to MSI controller */ - prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0); - if (prop == NULL) { - printf("\n%s: ERROR: missing msi-parent: %s\n", __func__, - pcie_path); - return; - } - phandle = fdt32_to_cpu(*prop); - - /* set one msi-map row */ - fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid); - fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle); - fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid); - fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); -} -static void fdt_fixup_pcie(void *blob) -{ - unsigned int found_multi = 0; - unsigned char header_type; - int index; - u32 streamid; - pci_dev_t dev, bdf; - int bus; - unsigned short id; - struct pci_controller *hose; - struct ls_pcie *pcie; - int i; - - for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) { - pcie = hose->priv_data; - for (bus = hose->first_busno; bus <= hose->last_busno; bus++) { - - for (dev = PCI_BDF(bus, 0, 0); - dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, - PCI_MAX_PCI_FUNCTIONS - 1); - dev += PCI_BDF(0, 0, 1)) { - - if (PCI_FUNC(dev) && !found_multi) - continue; - - pci_read_config_word(dev, PCI_VENDOR_ID, &id); - - pci_read_config_byte(dev, PCI_HEADER_TYPE, - &header_type); - - if ((id == 0xFFFF) || (id == 0x0000)) - continue; - - if (!PCI_FUNC(dev)) - found_multi = header_type & 0x80; - - streamid = ls_pcie_next_streamid(); - if (streamid < 0) { - debug("ERROR: no stream ids free\n"); - continue; - } - - index = ls_pcie_next_lut_index(pcie); - if (index < 0) { - debug("ERROR: no LUT indexes free\n"); - continue; - } - - /* the DT fixup must be relative to the hose first_busno */ - bdf = dev - PCI_BDF(hose->first_busno, 0, 0); - - /* map PCI b.d.f to streamID in LUT */ - ls_pcie_lut_set_mapping(pcie, index, bdf >> 8, - streamid); - - /* update msi-map in device tree */ - fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, - streamid); - } - } - } -} -#endif - -static void ft_pcie_ls_setup(void *blob, const char *pci_compat, - unsigned long ctrl_addr, enum srds_prtcl dev) -{ - int off; - - off = fdt_node_offset_by_compat_reg(blob, pci_compat, - (phys_addr_t)ctrl_addr); - if (off < 0) - return; - - if (!is_serdes_configured(dev)) - fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); -} - -/* Fixup Kernel DT for PCIe */ -void ft_pci_setup(void *blob, bd_t *bd) -{ -#ifdef CONFIG_PCIE1 - ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); -#endif - -#ifdef CONFIG_PCIE2 - ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); -#endif - -#ifdef CONFIG_PCIE3 - ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3); -#endif - -#ifdef CONFIG_PCIE4 - ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4); -#endif - -#ifdef CONFIG_FSL_LSCH3 - fdt_fixup_pcie(blob); -#endif -} - -#else /* CONFIG_DM_PCI */ - -#ifdef CONFIG_FSL_LSCH3 static void lut_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset) { @@ -345,7 +179,6 @@ void ft_pci_setup(void *blob, bd_t *bd) fdt_fixup_pcie(blob); #endif } -#endif /* CONFIG_DM_PCI */ #else /* !CONFIG_OF_BOARD_SETUP */ void ft_pci_setup(void *blob, bd_t *bd) -- cgit v0.10.2 From 19538f306b230fabb4f7244bf802eda7dee28bc7 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 13 Dec 2016 14:54:24 +0800 Subject: kconfig: move FSL_PCIE_COMPAT to platform Kconfig Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 9ffb90e..b61f3cd 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -18,6 +18,14 @@ config ARCH_LS1021A menu "LS102xA architecture" depends on ARCH_LS1021A +config FSL_PCIE_COMPAT + string "PCIe compatible of Kernel DT" + depends on PCIE_LAYERSCAPE + default "fsl,ls1021a-pcie" if ARCH_LS1021A + help + This compatible is used to find pci controller node in Kernel DT + to complete fixup. + config LS1_DEEP_SLEEP bool "Deep sleep" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index de0b580..9d37b2f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -75,6 +75,17 @@ config FSL_LSCH3 menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3 +config FSL_PCIE_COMPAT + string "PCIe compatible of Kernel DT" + depends on PCIE_LAYERSCAPE + default "fsl,ls1012a-pcie" if ARCH_LS1012A + default "fsl,ls1043a-pcie" if ARCH_LS1043A + default "fsl,ls1046a-pcie" if ARCH_LS1046A + default "fsl,ls2080a-pcie" if ARCH_LS2080A + help + This compatible is used to find pci controller node in Kernel DT + to complete fixup. + menu "Layerscape PPA" config FSL_LS_PPA bool "FSL Layerscape PPA firmware support" diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 47e621f..19ede2f 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -77,9 +77,9 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", pcie->dbi_res.start); if (nodeoffset < 0) { -#ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */ +#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ nodeoffset = fdt_node_offset_by_compat_reg(blob, - FSL_PCIE_COMPAT, pcie->dbi_res.start); + CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start); if (nodeoffset < 0) return; #else @@ -150,9 +150,9 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", pcie->dbi_res.start); if (off < 0) { -#ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */ +#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ off = fdt_node_offset_by_compat_reg(blob, - FSL_PCIE_COMPAT, + CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start); if (off < 0) return; diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 4d9a814..45da2af 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -154,7 +154,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_PCIE1 /* PCIE controller 1 */ -#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" #define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 23214e7..7e4e480 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -67,7 +67,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_PCIE1 /* PCIE controller 1 */ -#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" #define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index f1d1975..1b4b447 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -500,7 +500,6 @@ unsigned long get_board_ddr_clk(void); /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 6aff6b5..b54c4d3 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -370,7 +370,6 @@ /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index ff521ab..740d2d6 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -118,7 +118,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" #ifdef CONFIG_PCI #define CONFIG_NET_MULTI diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 805457d..eb628fd 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -170,9 +170,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif -/* PCIe */ -#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" - /* Command line configuration */ #define CONFIG_CMD_ENV -- cgit v0.10.2 From 6930be345aab208ac22ace91eea6790a13b46262 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 16 Dec 2016 17:15:45 +0800 Subject: ARMv8/fsl-layerscape: Correct the OCRAM size The real size of OCRAM is 128KiB, so correct the size of OCRAM. And OCRAM reserved 2MiB space, then add a new macro to describe it, which is used for MMU setup. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6073d44..b381872 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -28,8 +28,9 @@ #define CONFIG_FSL_TZASC_400 #endif -#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ /* DDR */ #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) @@ -122,7 +123,8 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ #define CONFIG_SYS_FSL_CCSR_SCFG_BE #define CONFIG_SYS_FSL_ESDHC_BE diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index a97be5c..4ea4aea 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -93,7 +93,7 @@ static struct mm_region early_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, + SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, @@ -140,7 +140,7 @@ static struct mm_region early_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, + SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, @@ -178,7 +178,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, + SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, @@ -280,7 +280,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, + SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, -- cgit v0.10.2 From 3b6bf8115ff2d85caa5b0af366b7053d5c7822fd Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 16 Dec 2016 17:15:46 +0800 Subject: armv8/fsl_lsch2: Add the OCRAM initialization Clear the content to zero and the ECC error bit of OCRAM1/2. The OCRAM must be initialized to ZERO by the unit of 8-Byte before accessing it, or else it will generate ECC error. And the IBR has accessed the OCRAM before this initialization, so the ECC error status bit should to be cleared. Signed-off-by: Hou Zhiqiang Signed-off-by: Pratiyush Srivastava Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 3404459..04a2598 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -229,10 +229,47 @@ ENTRY(lowlevel_init) isb #endif +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) + bl fsl_ocram_init +#endif + mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +ENTRY(fsl_ocram_init) + mov x28, lr /* Save LR */ + bl fsl_clear_ocram + bl fsl_ocram_clear_ecc_err + mov lr, x28 /* Restore LR */ + ret +ENDPROC(fsl_ocram_init) + +ENTRY(fsl_clear_ocram) +/* Clear OCRAM */ + ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE + ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE) + mov x2, #0 +clear_loop: + str x2, [x0] + add x0, x0, #8 + cmp x0, x1 + b.lo clear_loop + ret +ENDPROC(fsl_clear_ocram) + +ENTRY(fsl_ocram_clear_ecc_err) + /* OCRAM1/2 ECC status bit */ + mov w1, #0x60 + ldr x0, =DCSR_DCFG_SBEESR2 + str w1, [x0] + ldr x0, =DCSR_DCFG_MBEESR2 + str w1, [x0] + ret +ENDPROC(fsl_ocram_init) +#endif + #ifdef CONFIG_FSL_LSCH3 .globl get_svr get_svr: diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b381872..045825e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -126,6 +126,9 @@ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ +#define DCSR_DCFG_SBEESR2 0x20140534 +#define DCSR_DCFG_MBEESR2 0x20140544 + #define CONFIG_SYS_FSL_CCSR_SCFG_BE #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE -- cgit v0.10.2 From a73058740df230daddce7e1956d1051b5171783d Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Tue, 27 Dec 2016 10:24:44 +0800 Subject: armv8: ls1012: added usb nodes in dts The LS1012A processor has two integrated USB controllers. One is USB2.0 controller, the other is USB3.0 controller that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. Signed-off-by: Tang Yuantian Reviewed-by: York Sun diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index c4ca9c1..f8665b6 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -118,5 +118,20 @@ ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + usb0: usb2@8600000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + reg = <0x0 0x8600000 0x0 0x1000>; + interrupts = <0 139 0x4>; + dr_mode = "host"; + fsl,usb-erratum-a005697; + }; + + usb1: usb3@2f00000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 61 0x4>; + dr_mode = "host"; + }; }; }; -- cgit v0.10.2 From 57dfe200a61b93a329608a68f6acdd01a0e2da0c Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Tue, 27 Dec 2016 10:24:45 +0800 Subject: armv8: ls1012: Enable CONFIG_DM_USB in defconfigs Enables driver model flag CONFIG_DM_USB for LS1012A platform in defconfigs. Signed-off-by: Tang Yuantian Reviewed-by: York Sun diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index b00226f..8932650 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -34,6 +34,7 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index c2d8b64..e104816 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -35,6 +35,7 @@ CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index f569ddc..1650758 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -35,6 +35,7 @@ CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -- cgit v0.10.2 From 9e0bb4c1d9560cf8af0657939d01d7da8ef0f342 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 26 Dec 2016 12:15:08 +0530 Subject: arm: layerscape: Enable UUID & GPT partition for NXP's ARM SoC Enable UUID and GPT partition support for NXP's ARM based SoCs i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A. Also enable DOS partition for LS1012AFRDM boards. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index f6f88e8..94f7460 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -42,6 +42,11 @@ #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif +#define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 45da2af..fa1ed73 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -153,6 +153,10 @@ #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_NET_MULTI diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 7e4e480..d2dc5ea 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -66,6 +66,10 @@ #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_NET_MULTI diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index e270f42..9c3b163 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -179,6 +179,9 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 1b4b447..031dce7 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -397,6 +397,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b54c4d3..1f179f4 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -298,6 +298,9 @@ #define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 561a05a..431c8f8 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -100,6 +100,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION #define CONFIG_BOARD_LATE_INIT +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 71c26bd..36df331 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -310,6 +310,10 @@ #define SCSI_DEV_ID 0x9170 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #include #endif /* __LS1043ARDB_H__ */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 29e0aa5..3618a06 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -143,6 +143,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION #define CONFIG_BOARD_LATE_INIT +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index f0719ad..8a8f942 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -237,6 +237,10 @@ #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT + #define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \ "$kernel_start $kernel_size;" \ "bootm $kernel_load" diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 171b77f..5a54c1f 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -63,6 +63,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index feeb962..7f78fd8 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -71,6 +71,9 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_PARTITION_UUIDS +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_GPT /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ -- cgit v0.10.2 From 3aec452e4dbd16be7bdbabfa80d1fcc840cf342c Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 6 Jan 2017 17:41:10 +0800 Subject: armv8: Enable CPUECTLR.SMPEN for coherency For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations. Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Signed-off-by: Mateusz Kulikowski Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 22dce88..472b2ba 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -3,6 +3,24 @@ if ARM64 config ARMV8_MULTIENTRY bool "Enable multiple CPUs to enter into U-Boot" +config ARMV8_SET_SMPEN + bool "Enable data coherency with other cores in cluster" + help + Say Y here if there is not any trust firmware to set + CPUECTLR_EL1.SMPEN bit before U-Boot. + + For A53, it enables data coherency with other cores in the + cluster, and for A57/A72, it enables receiving of instruction + cache and TLB maintenance operations. + Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even + for single core systems. Unfortunately write access to this + register may be controlled by EL3/EL2 firmware. To be more + precise, by default (if there is EL2/EL3 firmware running) + this register is RO for NS EL1. + This switch can be used to avoid writing to CPUECTLR_EL1, + it can be safely enabled when EL2/EL3 initialized SMPEN bit + or when CPU implementation doesn't include that register. + config ARMV8_SPIN_TABLE bool "Support spin-table enable method" depends on ARMV8_MULTIENTRY && OF_LIBFDT diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 4f5f6d8..5308702 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -86,6 +86,17 @@ save_boot_params_ret: msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: + /* + * Enalbe SMPEN bit for coherency. + * This register is not architectural but at the moment + * this bit should be set for A53/A57/A72. + */ +#ifdef CONFIG_ARMV8_SET_SMPEN + mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ + orr x0, x0, #0x40 + msr S3_1_c15_c2_1, x0 +#endif + /* Apply ARM core specific erratas */ bl apply_core_errata -- cgit v0.10.2 From ee2a51022135a01fa2258b7788702313d0f54dac Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 6 Jan 2017 17:41:11 +0800 Subject: ARMv8/fsl-layerscape: Enable data coherency between cores in cluster Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9d37b2f..7572f19 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,5 +1,6 @@ config ARCH_LS1012A bool + select ARMV8_SET_SMPEN select FSL_LSCH2 select SYS_FSL_DDR_BE select SYS_FSL_MMDC @@ -7,6 +8,7 @@ config ARCH_LS1012A config ARCH_LS1043A bool + select ARMV8_SET_SMPEN select FSL_LSCH2 select SYS_FSL_DDR select SYS_FSL_DDR_BE @@ -23,6 +25,7 @@ config ARCH_LS1043A config ARCH_LS1046A bool + select ARMV8_SET_SMPEN select FSL_LSCH2 select SYS_FSL_DDR select SYS_FSL_DDR_BE @@ -38,6 +41,7 @@ config ARCH_LS1046A config ARCH_LS2080A bool + select ARMV8_SET_SMPEN select FSL_LSCH3 select SYS_FSL_DDR select SYS_FSL_DDR_LE -- cgit v0.10.2 From 904110c7ac801b99029b2bca4765c792c9eac582 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 10 Jan 2017 16:44:15 +0800 Subject: armv8/fsl-lsch2: refactor the clock system initialization Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 7572f19..92e8fa6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -163,6 +163,83 @@ config SYS_HAS_SERDES endmenu +menu "Layerscape clock tree configuration" + depends on FSL_LSCH2 || FSL_LSCH3 + +config SYS_FSL_CLK + bool "Enable clock tree initialization" + default y + +config CLUSTER_CLK_FREQ + int "Reference clock of core cluster" + depends on ARCH_LS1012A + default 100000000 + help + This number is the reference clock frequency of core PLL. + For most platforms, the core PLL and Platform PLL have the same + reference clock, but for some platforms, LS1012A for instance, + they are provided sepatately. + +config SYS_FSL_PCLK_DIV + int "Platform clock divider" + default 1 if ARCH_LS1043A + default 1 if ARCH_LS1046A + default 2 + help + This is the divider that is used to derive Platform clock from + Platform PLL, in another word: + Platform_clk = Platform_PLL_freq / this_divider + +config SYS_FSL_DSPI_CLK_DIV + int "DSPI clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive DSPI clock from Platform + PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. + +config SYS_FSL_DUART_CLK_DIV + int "DUART clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive DUART clock from Platform + clock, in another word DUART_clk = Platform_clk / this_divider. + +config SYS_FSL_I2C_CLK_DIV + int "I2C clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive I2C clock from Platform + clock, in another word I2C_clk = Platform_clk / this_divider. + +config SYS_FSL_IFC_CLK_DIV + int "IFC clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive IFC clock from Platform + clock, in another word IFC_clk = Platform_clk / this_divider. + +config SYS_FSL_LPUART_CLK_DIV + int "LPUART clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive LPUART clock from Platform + clock, in another word LPUART_clk = Platform_clk / this_divider. + +config SYS_FSL_SDHC_CLK_DIV + int "SDHC clock divider" + default 1 if ARCH_LS1043A + default 1 if ARCH_LS1012A + default 2 + help + This is the divider that is used to derive SDHC clock from Platform + clock, in another word SDHC_clk = Platform_clk / this_divider. +endmenu + config SYS_FSL_ERRATUM_A008336 bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 467d9af..3bdeb0e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -345,8 +345,9 @@ int print_cpuinfo(void) (type == TY_ITYP_VER_A72 ? "A72" : " "))), strmhz(buf, sysinfo.freq_processor[core])); } + /* Display platform clock as Bus frequency. */ printf("\n Bus: %-4s MHz ", - strmhz(buf, sysinfo.freq_systembus)); + strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV)); printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); #ifdef CONFIG_SYS_DPAA_FMAN printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 55005f0..3da7037 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info) uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + unsigned long cluster_clk; sys_info->freq_systembus = sysclk; +#ifndef CONFIG_CLUSTER_CLK_FREQ +#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ +#endif + cluster_clk = CONFIG_CLUSTER_CLK_FREQ; + #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; #else sys_info->freq_ddrbus = sysclk; #endif -#ifdef CONFIG_ARCH_LS1012A - sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; -#else + /* The freq_systembus is used to record frequency of platform PLL */ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; + +#ifdef CONFIG_ARCH_LS1012A + sys_info->freq_ddrbus = 2 * sys_info->freq_systembus; +#else sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; @@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info) for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; if (ratio[i] > 4) - freq_c_pll[i] = sysclk * ratio[i]; + freq_c_pll[i] = cluster_clk * ratio[i]; else freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } @@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#ifdef CONFIG_ARCH_LS1012A - sys_info->freq_systembus = sys_info->freq_ddrbus / 2; - sys_info->freq_ddrbus *= 2; -#endif - #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 #ifdef CONFIG_SYS_DPAA_FMAN @@ -148,7 +149,9 @@ void get_sys_info(struct sys_info *sys_info) break; } #else - sys_info->freq_sdhc = sys_info->freq_systembus; + sys_info->freq_sdhc = (sys_info->freq_systembus / + CONFIG_SYS_FSL_PCLK_DIV) / + CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif #endif @@ -166,7 +169,7 @@ int get_clocks(void) get_sys_info(&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; - gd->bus_clk = sys_info.freq_systembus; + gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV; gd->mem_clk = sys_info.freq_ddrbus; #ifdef CONFIG_FSL_ESDHC @@ -179,41 +182,73 @@ int get_clocks(void) return 1; } +/******************************************** + * get_bus_freq + * return platform clock in Hz + *********************************************/ ulong get_bus_freq(ulong dummy) { + if (!gd->bus_clk) + get_clocks(); + return gd->bus_clk; } ulong get_ddr_freq(ulong dummy) { + if (!gd->mem_clk) + get_clocks(); + return gd->mem_clk; } #ifdef CONFIG_FSL_ESDHC int get_sdhc_freq(ulong dummy) { + if (!gd->arch.sdhc_clk) + get_clocks(); + return gd->arch.sdhc_clk; } #endif int get_serial_clock(void) { - return gd->bus_clk; + return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; +} + +int get_i2c_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV; +} + +int get_dspi_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; } +#ifdef CONFIG_FSL_LPUART +int get_uart_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV; +} +#endif + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { case MXC_I2C_CLK: - return get_bus_freq(0); + return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: - return get_bus_freq(0); + return get_dspi_freq(0); +#ifdef CONFIG_FSL_LPUART case MXC_UART_CLK: - return get_bus_freq(0); + return get_uart_freq(0); +#endif default: printf("Unsupported clock\n"); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index b3cfd89..6ace3da 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -137,6 +137,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; + /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus; diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 20f0c61..910835e 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40100000 -#define CONFIG_SYS_FSL_CLK -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 125000000 +#define CONFIG_SYS_CLK_FREQ 125000000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 @@ -82,7 +80,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 740d2d6..47b6ef7 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -11,7 +11,6 @@ #define CONFIG_FSL_LAYERSCAPE #define CONFIG_LS1043A #define CONFIG_MP -#define CONFIG_SYS_FSL_CLK #define CONFIG_GICV2 #include @@ -42,7 +41,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 40e6af8..4a910d1 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -10,7 +10,6 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE #define CONFIG_MP -#define CONFIG_SYS_FSL_CLK #define CONFIG_GICV2 #include @@ -41,7 +40,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 5a54c1f..c39e9cf 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -14,8 +14,6 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif -#define CONFIG_SYS_FSL_CLK - #ifdef CONFIG_FSL_QSPI #define CONFIG_SYS_NO_FLASH #undef CONFIG_CMD_IMLS diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 7f78fd8..5626d88 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -32,7 +32,6 @@ unsigned long get_board_sys_clk(void); #endif -#define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ 133333333 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) -- cgit v0.10.2 From 3564208e013d34eb0dab58d2f1561feee3f5735d Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 10 Jan 2017 16:44:16 +0800 Subject: armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index a9b12a4..f8fefc7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info) #endif #endif + /* The freq_systembus is used to record frequency of platform PLL */ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; - /* Platform clock is half of platform PLL */ - sys_info->freq_systembus /= 2; sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; @@ -142,13 +141,13 @@ int get_clocks(void) struct sys_info sys_info; get_sys_info(&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; - gd->bus_clk = sys_info.freq_systembus; + gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV; gd->mem_clk = sys_info.freq_ddrbus; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR gd->arch.mem2_clk = sys_info.freq_ddrbus2; #endif #if defined(CONFIG_FSL_ESDHC) - gd->arch.sdhc_clk = gd->bus_clk / 2; + gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif /* defined(CONFIG_FSL_ESDHC) */ if (gd->cpu_clk != 0) @@ -159,7 +158,7 @@ int get_clocks(void) /******************************************** * get_bus_freq - * return system bus freq in Hz + * return platform clock in Hz *********************************************/ ulong get_bus_freq(ulong dummy) { @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num) return gd->mem_clk; } +int get_i2c_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV; +} + +int get_dspi_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; +} + +int get_serial_clock(void) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { case MXC_I2C_CLK: - return get_bus_freq(0) / 2; + return get_i2c_freq(0); case MXC_DSPI_CLK: - return get_bus_freq(0) / 2; + return get_dspi_freq(0); default: printf("Unsupported clock\n"); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index f613efa..43ae686 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -151,6 +151,7 @@ #ifndef __ASSEMBLY__ struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; + /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index eb628fd..32d56ae 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -97,7 +97,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -- cgit v0.10.2 From fc8048a88e7b5467a77512bf31e5225c0e5a2a0b Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 7 Dec 2016 11:54:30 +0800 Subject: mmc: fsl_esdhc: make GPIO support optional There would be compiling error as below when enable driver model for esdhc. undefined reference to `dm_gpio_get_value' undefined reference to `gpio_request_by_name_nodev' This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because all boards of QorIQ platform don't need it and they just check register for CD/WP status, only some boards of i.MX platform require this. Signed-off-by: Yangbo Lu Acked-by: Jaehoon Chung Reviewed-by: York Sun diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 9796d39..da3a151 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -104,8 +104,10 @@ struct fsl_esdhc_priv { struct udevice *dev; int non_removable; int wp_enable; +#ifdef CONFIG_DM_GPIO struct gpio_desc cd_gpio; struct gpio_desc wp_gpio; +#endif }; /* Return the XFERTYP flags for a given command and data packet */ @@ -687,10 +689,11 @@ static int esdhc_getcd(struct mmc *mmc) #ifdef CONFIG_DM_MMC if (priv->non_removable) return 1; - +#ifdef CONFIG_DM_GPIO if (dm_gpio_is_valid(&priv->cd_gpio)) return dm_gpio_get_value(&priv->cd_gpio); #endif +#endif while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000); @@ -967,17 +970,20 @@ static int fsl_esdhc_probe(struct udevice *dev) priv->non_removable = 1; } else { priv->non_removable = 0; +#ifdef CONFIG_DM_GPIO gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); +#endif } priv->wp_enable = 1; +#ifdef CONFIG_DM_GPIO ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); if (ret) priv->wp_enable = 0; - +#endif /* * TODO: * Because lack of clk driver, if SDHC clk is not enabled, -- cgit v0.10.2 From a6473f8e3fb53c65d3a6f9fc7e37cff59284faa6 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 7 Dec 2016 11:54:31 +0800 Subject: mmc: fsl_esdhc: add 'fsl, esdhc' into of_match table This patch is to add 'fsl,esdhc' into of_match table to support driver model for QorIQ eSDHC. Signed-off-by: Yangbo Lu Reviewed-by: York Sun diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index da3a151..0ae1cfd 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1027,6 +1027,7 @@ static const struct udevice_id fsl_esdhc_ids[] = { { .compatible = "fsl,imx6sl-usdhc", }, { .compatible = "fsl,imx6q-usdhc", }, { .compatible = "fsl,imx7d-usdhc", }, + { .compatible = "fsl,esdhc", }, { /* sentinel */ } }; -- cgit v0.10.2 From e1f39751d533a9d2bc439f8ec72683e6405b5e8e Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 7 Dec 2016 11:54:32 +0800 Subject: armv8: ls1012a: add eSDHC nodes This patch is to add eSDHC nodes for ls1012a. Signed-off-by: Yangbo Lu Reviewed-by: York Sun diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index f8665b6..ed5ea54 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -54,6 +54,22 @@ status = "disabled"; }; + esdhc0: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <0 62 0x4>; + big-endian; + bus-width = <4>; + }; + + esdhc1: esdhc@1580000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1580000 0x0 0x10000>; + interrupts = <0 65 0x4>; + big-endian; + non-removable; + bus-width = <4>; + }; i2c0: i2c@2180000 { compatible = "fsl,vf610-i2c"; -- cgit v0.10.2 From cda000f3c3815f1fa5cfd64cec2ca8adfff5d437 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 7 Dec 2016 11:54:33 +0800 Subject: configs: ls1012a: enable driver model for eSDHC Enable driver model for eSDHC on ls1012a rdb and qds boards. Signed-off-by: Yangbo Lu Reviewed-by: York Sun diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index e104816..0bb40d0 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -34,6 +34,9 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_DM_MMC=y +CONFIG_DM_MMC_OPS=n +CONFIG_BLK=n CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 1650758..6fed6c7 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -34,6 +34,9 @@ CONFIG_E1000=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_DM_MMC=y +CONFIG_DM_MMC_OPS=n +CONFIG_BLK=n CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y -- cgit v0.10.2 From 39199356e9ff3db2cd7851a0e29840f1972fb959 Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Fri, 6 Jan 2017 15:58:56 +0530 Subject: SECURE_BOOT: Update bootscript and its hdr addresses Update bootscript and its hdr addresses for Layerscape Chasis 3 based platforms instead of individual SoCs. Signed-off-by: Sumit Garg Signed-off-by: Udit Agarwal Reviewed-by: York Sun diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 4525287..f920215 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -80,18 +80,18 @@ /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ defined(CONFIG_SD_BOOT) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif /* The address needs to be modified according to NOR, NAND, SD and * DDR memory map */ -#ifdef CONFIG_LS2080A -#define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000 -#define CONFIG_BS_ADDR_DEVICE 0x583900000 -#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 -#define CONFIG_BS_ADDR_RAM 0xa3900000 +#ifdef CONFIG_FSL_LSCH3 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000 +#define CONFIG_BS_ADDR_DEVICE 0x580e00000 +#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000 +#define CONFIG_BS_ADDR_RAM 0xa0e00000 #define CONFIG_BS_HDR_SIZE 0x00002000 #define CONFIG_BS_SIZE 0x00001000 #else -- cgit v0.10.2 From 9ed44787f60a93d440824130dee0ae53500e1b83 Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Fri, 6 Jan 2017 15:58:57 +0530 Subject: LS2080A: Add validation of MC & DPC images. Add secure boot validation of MC, DPC images using esbc_validate command. Signed-off-by: Sumit Garg Signed-off-by: Udit Agarwal Reviewed-by: York Sun diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index c39e9cf..e8f2e49 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -364,6 +364,7 @@ unsigned long get_board_ddr_clk(void); /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CONFIG_SECURE_BOOT #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ @@ -375,8 +376,26 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ + "mcinitcmd=esbc_validate 0x580c80000;" \ + "esbc_validate 0x580cc0000;" \ + "fsl_mc start mc 0x580300000" \ " 0x580800000 \0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581100000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" +#endif /* CONFIG_SECURE_BOOT */ + #ifdef CONFIG_FSL_MC_ENET #define CONFIG_FSL_MEMAC diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 5626d88..bbcbd66 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -329,6 +329,7 @@ unsigned long get_board_sys_clk(void); /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CONFIG_SECURE_BOOT #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "scriptaddr=0x80800000\0" \ @@ -346,9 +347,34 @@ unsigned long get_board_sys_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" \ + "mcinitcmd=esbc_validate 0x580c80000;" \ + "esbc_validate 0x580cc0000;" \ + "fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" \ BOOTENV +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581100000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "fdtfile=fsl-ls2080a-rdb.dtb\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" \ + BOOTENV +#endif + #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ -- cgit v0.10.2 From 9cfab06e7938453438008c2f561df7d35f83e8f4 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 4 Jan 2017 10:32:08 -0800 Subject: armv8: fsl-layerscape: Fix SECURE_BOOT config Without a prompt in Kconfig, SECURE_BOOT cannot be selected by defconfig. The option was dropped unintentionally when defconfig files were cleaned up. Three targets were impacted ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT, ls2080aqds_SECURE_BOOT. Signed-off-by: York Sun Reviewed-by: Simon Glass diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 92e8fa6..79e2dd6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -131,7 +131,7 @@ config MAX_CPUS in spin table to properly handle all cores. config SECURE_BOOT - bool + bool "Secure Boot" help Enable Freescale Secure Boot feature diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 5b48977..d8eee00 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043ARDB=y +CONFIG_SECURE_BOOT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 047c2c1..c741bf9 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y +CONFIG_SECURE_BOOT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index f917035..543c940 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y +CONFIG_SECURE_BOOT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y -- cgit v0.10.2 From 762161b04ade62be5c708ff167f5fdde2e61fa9c Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 9 Dec 2016 16:08:57 +0800 Subject: pmic: pmic_mc34vr500: Add a driver for the mc34vr500 pmic This patch adds a simple pmic driver for the mc34vr500 pmic which is used in conjunction with the fsl T1 and LS1 series SoC. Signed-off-by: Hou Zhiqiang Reviewed-by: Jaehoon Chung Reviewed-by: York Sun diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 5e244c8..e7cc405 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -164,3 +164,10 @@ config PMIC_LP873X ---help--- The LP873X is a PMIC containing couple of LDOs and couple of SMPS. This driver binds the pmic children. + +config POWER_MC34VR500 + bool "Enable driver for Freescale MC34VR500 PMIC" + ---help--- + The MC34VR500 is used in conjunction with the FSL T1 and LS1 series + SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed + via an I2C interface. diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index b4ac7d2..8615939 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -33,3 +33,4 @@ obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o +obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o diff --git a/drivers/power/pmic/pmic_mc34vr500.c b/drivers/power/pmic/pmic_mc34vr500.c new file mode 100644 index 0000000..db9e210 --- /dev/null +++ b/drivers/power/pmic/pmic_mc34vr500.c @@ -0,0 +1,32 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Hou Zhiqiang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int power_mc34vr500_init(unsigned char bus) +{ + static const char name[] = "MC34VR500"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = MC34VR500_NUM_OF_REGS; + p->hw.i2c.addr = MC34VR500_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/include/power/mc34vr500_pmic.h b/include/power/mc34vr500_pmic.h new file mode 100644 index 0000000..df4985a --- /dev/null +++ b/include/power/mc34vr500_pmic.h @@ -0,0 +1,166 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Hou Zhiqiang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MC34VR500_H_ +#define __MC34VR500_H_ + +#include + +#define MC34VR500_I2C_ADDR 0x08 + +/* Drivers name */ +#define MC34VR500_REGULATOR_DRIVER "mc34vr500_regulator" + +/* Register map */ +enum { + MC34VR500_DEVICEID = 0x00, + + MC34VR500_SILICONREVID = 0x03, + MC34VR500_FABID, + MC34VR500_INTSTAT0, + MC34VR500_INTMASK0, + MC34VR500_INTSENSE0, + MC34VR500_INTSTAT1, + MC34VR500_INTMASK1, + MC34VR500_INTSENSE1, + + MC34VR500_INTSTAT4 = 0x11, + MC34VR500_INTMASK4, + MC34VR500_INTSENSE4, + + MC34VR500_PWRCTL = 0x1B, + + MC34VR500_SW1VOLT = 0x2E, + MC34VR500_SW1STBY, + MC34VR500_SW1OFF, + MC34VR500_SW1MODE, + MC34VR500_SW1CONF, + MC34VR500_SW2VOLT, + MC34VR500_SW2STBY, + MC34VR500_SW2OFF, + MC34VR500_SW2MODE, + MC34VR500_SW2CONF, + + MC34VR500_SW3VOLT = 0x3C, + MC34VR500_SW3STBY, + MC34VR500_SW3OFF, + MC34VR500_SW3MODE, + MC34VR500_SW3CONF, + + MC34VR500_SW4VOLT = 0x4A, + MC34VR500_SW4STBY, + MC34VR500_SW4OFF, + MC34VR500_SW4MODE, + MC34VR500_SW4CONF, + + MC34VR500_REFOUTCRTRL = 0x6A, + + MC34VR500_LDO1CTL = 0x6D, + MC34VR500_LDO2CTL, + MC34VR500_LDO3CTL, + MC34VR500_LDO4CTL, + MC34VR500_LDO5CTL, + + MC34VR500_PAGE_REGISTER = 0x7F, + + /* Internal RAM */ + MC34VR500_SW1_VOLT = 0xA8, + MC34VR500_SW1_SEQ, + MC34VR500_SW1_CONFIG, + + MC34VR500_SW2_VOLT = 0xAC, + MC34VR500_SW2_SEQ, + MC34VR500_SW2_CONFIG, + + MC34VR500_SW3_VOLT = 0xB0, + MC34VR500_SW3_SEQ, + MC34VR500_SW3_CONFIG, + + MC34VR500_SW4_VOLT = 0xB8, + MC34VR500_SW4_SEQ, + MC34VR500_SW4_CONFIG, + + MC34VR500_REFOUT_SEQ = 0xC4, + + MC34VR500_LDO1_VOLT = 0xCC, + MC34VR500_LDO1_SEQ, + + MC34VR500_LDO2_VOLT = 0xD0, + MC34VR500_LDO2_SEQ, + + MC34VR500_LDO3_VOLT = 0xD4, + MC34VR500_LDO3_SEQ, + + MC34VR500_LDO4_VOLT = 0xD8, + MC34VR500_LDO4_SEQ, + + MC34VR500_LDO5_VOLT = 0xDC, + MC34VR500_LDO5_SEQ, + + MC34VR500_PU_CONFIG1 = 0xE0, + + MC34VR500_TBB_POR = 0xE4, + + MC34VR500_PWRGD_EN = 0xE8, + + MC34VR500_NUM_OF_REGS, +}; + +/* Registor offset based on SWxVOLT register */ +#define MC34VR500_VOLT_OFFSET 0 +#define MC34VR500_STBY_OFFSET 1 +#define MC34VR500_OFF_OFFSET 2 +#define MC34VR500_MODE_OFFSET 3 +#define MC34VR500_CONF_OFFSET 4 + +#define SW_MODE_MASK 0xf +#define SW_MODE_SHIFT 0 + +#define LDO_VOL_MASK 0xf +#define LDO_EN (1 << 4) +#define LDO_MODE_SHIFT 4 +#define LDO_MODE_MASK (1 << 4) +#define LDO_MODE_OFF 0 +#define LDO_MODE_ON 1 + +#define REFOUTEN (1 << 4) + +/* + * Regulator Mode Control + * + * OFF: The regulator is switched off and the output voltage is discharged. + * PFM: In this mode, the regulator is always in PFM mode, which is useful + * at light loads for optimized efficiency. + * PWM: In this mode, the regulator is always in PWM mode operation + * regardless of load conditions. + * APS: In this mode, the regulator moves automatically between pulse + * skipping mode and PWM mode depending on load conditions. + * + * SWxMODE[3:0] + * Normal Mode | Standby Mode | value + * OFF OFF 0x0 + * PWM OFF 0x1 + * PFM OFF 0x3 + * APS OFF 0x4 + * PWM PWM 0x5 + * PWM APS 0x6 + * APS APS 0x8 + * APS PFM 0xc + * PWM PFM 0xd + */ +#define OFF_OFF 0x0 +#define PWM_OFF 0x1 +#define PFM_OFF 0x3 +#define APS_OFF 0x4 +#define PWM_PWM 0x5 +#define PWM_APS 0x6 +#define APS_APS 0x8 +#define APS_PFM 0xc +#define PWM_PFM 0xd + +int power_mc34vr500_init(unsigned char bus); +#endif /* __MC34VR500_PMIC_H_ */ -- cgit v0.10.2 From 4394ad1227e5752b13fefa99846cb7073f4dd42b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 9 Dec 2016 16:08:58 +0800 Subject: pmic: pmic_mc34vr500: Add APIs to set/get SWx volt Signed-off-by: Hou Zhiqiang Reviewed-by: Jaehoon Chung Reviewed-by: York Sun diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index e941949..1c53fb6 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o obj-$(CONFIG_ZM7300) += zm7300.o obj-$(CONFIG_POWER_PFUZE100) += pfuze.o +obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o diff --git a/board/freescale/common/mc34vr500.c b/board/freescale/common/mc34vr500.c new file mode 100644 index 0000000..9c57569 --- /dev/null +++ b/board/freescale/common/mc34vr500.c @@ -0,0 +1,95 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Hou Zhiqiang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static uint8_t swxvolt_addr[4] = { MC34VR500_SW1VOLT, + MC34VR500_SW2VOLT, + MC34VR500_SW3VOLT, + MC34VR500_SW4VOLT }; + +static uint8_t swx_set_point_base[4] = { 13, 9, 9, 9 }; + +int mc34vr500_get_sw_volt(uint8_t sw) +{ + struct pmic *p; + u32 swxvolt; + uint8_t spb; + int sw_volt; + int ret; + + debug("%s: Get SW%u volt from swxvolt_addr = 0x%x\n", + __func__, sw + 1, swxvolt_addr[sw]); + if (sw > SW4) { + printf("%s: Unsupported SW(sw%d)\n", __func__, sw + 1); + return -EINVAL; + } + + p = pmic_get("MC34VR500"); + if (!p) { + printf("%s: Did NOT find PMIC MC34VR500\n", __func__); + return -ENODEV; + } + + ret = pmic_probe(p); + if (ret) + return ret; + + ret = pmic_reg_read(p, swxvolt_addr[sw], &swxvolt); + if (ret) { + printf("%s: Failed to get SW%u volt\n", __func__, sw + 1); + return ret; + } + + debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt); + spb = swx_set_point_base[sw]; + /* The base of SW volt is 625mV and increase by step 25mV */ + sw_volt = 625 + (swxvolt - spb) * 25; + + debug("%s: SW%u volt = %dmV\n", __func__, sw + 1, sw_volt); + return sw_volt; +} + +int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt) +{ + struct pmic *p; + u32 swxvolt; + uint8_t spb; + int ret; + + debug("%s: Set SW%u volt to %dmV\n", __func__, sw + 1, sw_volt); + /* The least SW volt is 625mV, and only 4 SW outputs */ + if (sw > SW4 || sw_volt < 625) + return -EINVAL; + + p = pmic_get("MC34VR500"); + if (!p) { + printf("%s: Did NOT find PMIC MC34VR500\n", __func__); + return -ENODEV; + } + + ret = pmic_probe(p); + if (ret) + return ret; + + spb = swx_set_point_base[sw]; + /* The base of SW volt is 625mV and increase by step 25mV */ + swxvolt = (sw_volt - 625) / 25 + spb; + debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt); + if (swxvolt > 63) + return -EINVAL; + + ret = pmic_reg_write(p, swxvolt_addr[sw], swxvolt); + if (ret) + return ret; + + return 0; +} diff --git a/include/power/mc34vr500_pmic.h b/include/power/mc34vr500_pmic.h index df4985a..b0b143a 100644 --- a/include/power/mc34vr500_pmic.h +++ b/include/power/mc34vr500_pmic.h @@ -162,5 +162,14 @@ enum { #define APS_PFM 0xc #define PWM_PFM 0xd +enum swx { + SW1 = 0, + SW2, + SW3, + SW4, +}; + +int mc34vr500_get_sw_volt(uint8_t sw); +int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt); int power_mc34vr500_init(unsigned char bus); #endif /* __MC34VR500_PMIC_H_ */ -- cgit v0.10.2 From 6424577b1bf1c7872baea42de174bc461de74b6b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 9 Dec 2016 16:08:59 +0800 Subject: ls1046ardb: cpld: add API for selecting core volt Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c index 81a646e..c0500f4 100644 --- a/board/freescale/ls1046ardb/cpld.c +++ b/board/freescale/ls1046ardb/cpld.c @@ -82,6 +82,15 @@ void cpld_set_sd(void) CPLD_WRITE(system_rst, 1); } + +void cpld_select_core_volt(bool en_0v9) +{ + u8 reg17 = en_0v9; + + CPLD_WRITE(vdd_en, 1); + CPLD_WRITE(vdd_sel, reg17); +} + #ifdef DEBUG static void cpld_dump_regs(void) { diff --git a/board/freescale/ls1046ardb/cpld.h b/board/freescale/ls1046ardb/cpld.h index 458da7e..f6a1a61 100644 --- a/board/freescale/ls1046ardb/cpld.h +++ b/board/freescale/ls1046ardb/cpld.h @@ -35,6 +35,7 @@ struct cpld_data { u8 cpld_read(unsigned int reg); void cpld_write(unsigned int reg, u8 value); void cpld_rev_bit(unsigned char *value); +void cpld_select_core_volt(bool en_0v9); #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) #define CPLD_WRITE(reg, value) \ -- cgit v0.10.2 From 031acdbae89515371f794d01df819b490ff7ca9c Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 9 Dec 2016 16:09:00 +0800 Subject: armv8/fsl_lsch2: Add chip power supply voltage setup Set up chip power supply voltage according to voltage ID. The fuse status register provides the values from on-chip voltage ID fuses programmed at the factory. These values define the voltage requirements for the chip. Main operations: 1. Set up the core voltage 2. Set up the SERDES voltage and reset SERDES lanes 3. Enable/disable DDR controller support 0.9V if needed Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index e06b063..c0b4d0a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -129,6 +129,278 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, serdes_prtcl_map[NONE] = 1; } +__weak int get_serdes_volt(void) +{ + return -1; +} + +__weak int set_serdes_volt(int svdd) +{ + return -1; +} + +int setup_serdes_volt(u32 svdd) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_serdes *serdes1_base; +#ifdef CONFIG_SYS_FSL_SRDS_2 + struct ccsr_serdes *serdes2_base; +#endif + u32 cfg_rcw4 = gur_in32(&gur->rcwsr[4]); + u32 cfg_rcw5 = gur_in32(&gur->rcwsr[5]); + u32 cfg_tmp, reg = 0; + int svdd_cur, svdd_tar; + int ret; + int i; + + /* Only support switch SVDD to 900mV/1000mV */ + if (svdd != 900 && svdd != 1000) + return -EINVAL; + + svdd_tar = svdd; + svdd_cur = get_serdes_volt(); + if (svdd_cur < 0) + return -EINVAL; + + debug("%s: current SVDD: %dmV; target SVDD: %dmV\n", + __func__, svdd_cur, svdd_tar); + if (svdd_cur == svdd_tar) + return 0; + + serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR; +#ifdef CONFIG_SYS_FSL_SRDS_2 + serdes2_base = (void *)serdes1_base + 0x10000; +#endif + + /* Put the all enabled lanes in reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { + reg = in_be32(&serdes1_base->lane[i].gcr0); + reg &= 0xFF9FFFFF; + out_be32(&serdes1_base->lane[i].gcr0, reg); + } +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; + cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; + + for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { + reg = in_be32(&serdes2_base->lane[i].gcr0); + reg &= 0xFF9FFFFF; + out_be32(&serdes2_base->lane[i].gcr0, reg); + } +#endif + + /* Put the all enabled PLL in reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = (cfg_rcw5 >> 22) & 0x3; + for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { + reg = in_be32(&serdes1_base->bank[i].rstctl); + reg &= 0xFFFFFFBF; + reg |= 0x10000000; + out_be32(&serdes1_base->bank[i].rstctl, reg); + udelay(1); + + reg = in_be32(&serdes1_base->bank[i].rstctl); + reg &= 0xFFFFFF1F; + out_be32(&serdes1_base->bank[i].rstctl, reg); + } + udelay(1); +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = (cfg_rcw5 >> 20) & 0x3; + for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { + reg = in_be32(&serdes2_base->bank[i].rstctl); + reg &= 0xFFFFFFBF; + reg |= 0x10000000; + out_be32(&serdes2_base->bank[i].rstctl, reg); + udelay(1); + + reg = in_be32(&serdes2_base->bank[i].rstctl); + reg &= 0xFFFFFF1F; + out_be32(&serdes2_base->bank[i].rstctl, reg); + } + udelay(1); +#endif + + /* Put the Rx/Tx calibration into reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + reg = in_be32(&serdes1_base->srdstcalcr); + reg &= 0xF7FFFFFF; + out_be32(&serdes1_base->srdstcalcr, reg); + reg = in_be32(&serdes1_base->srdsrcalcr); + reg &= 0xF7FFFFFF; + out_be32(&serdes1_base->srdsrcalcr, reg); + +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + reg = in_be32(&serdes2_base->srdstcalcr); + reg &= 0xF7FFFFFF; + out_be32(&serdes2_base->srdstcalcr, reg); + reg = in_be32(&serdes2_base->srdsrcalcr); + reg &= 0xF7FFFFFF; + out_be32(&serdes2_base->srdsrcalcr, reg); +#endif + + /* + * If SVDD set failed, will not return directly, so that the + * serdes lanes can complete reseting. + */ + ret = set_serdes_volt(svdd_tar); + if (ret) + printf("%s: Failed to set SVDD\n", __func__); + + /* Wait for SVDD to stabilize */ + udelay(100); + + /* For each PLL that’s not disabled via RCW */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = (cfg_rcw5 >> 22) & 0x3; + for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { + reg = in_be32(&serdes1_base->bank[i].rstctl); + reg |= 0x00000020; + out_be32(&serdes1_base->bank[i].rstctl, reg); + udelay(1); + + reg = in_be32(&serdes1_base->bank[i].rstctl); + reg |= 0x00000080; + out_be32(&serdes1_base->bank[i].rstctl, reg); + + /* Take the Rx/Tx calibration out of reset */ + if (!(cfg_tmp == 0x3 && i == 1)) { + udelay(1); + reg = in_be32(&serdes1_base->srdstcalcr); + reg |= 0x08000000; + out_be32(&serdes1_base->srdstcalcr, reg); + reg = in_be32(&serdes1_base->srdsrcalcr); + reg |= 0x08000000; + out_be32(&serdes1_base->srdsrcalcr, reg); + } + } + udelay(1); +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = (cfg_rcw5 >> 20) & 0x3; + for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { + reg = in_be32(&serdes2_base->bank[i].rstctl); + reg |= 0x00000020; + out_be32(&serdes2_base->bank[i].rstctl, reg); + udelay(1); + + reg = in_be32(&serdes2_base->bank[i].rstctl); + reg |= 0x00000080; + out_be32(&serdes2_base->bank[i].rstctl, reg); + + /* Take the Rx/Tx calibration out of reset */ + if (!(cfg_tmp == 0x3 && i == 1)) { + udelay(1); + reg = in_be32(&serdes2_base->srdstcalcr); + reg |= 0x08000000; + out_be32(&serdes2_base->srdstcalcr, reg); + reg = in_be32(&serdes2_base->srdsrcalcr); + reg |= 0x08000000; + out_be32(&serdes2_base->srdsrcalcr, reg); + } + } + udelay(1); + +#endif + + /* Wait for at lesat 625us to ensure the PLLs being reset are locked */ + udelay(800); + +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = (cfg_rcw5 >> 22) & 0x3; + for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { + /* if the PLL is not locked, set RST_ERR */ + reg = in_be32(&serdes1_base->bank[i].pllcr0); + if (!((reg >> 23) & 0x1)) { + reg = in_be32(&serdes1_base->bank[i].rstctl); + reg |= 0x20000000; + out_be32(&serdes1_base->bank[i].rstctl, reg); + } else { + udelay(1); + reg = in_be32(&serdes1_base->bank[i].rstctl); + reg &= 0xFFFFFFEF; + reg |= 0x00000040; + out_be32(&serdes1_base->bank[i].rstctl, reg); + udelay(1); + } + } +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = (cfg_rcw5 >> 20) & 0x3; + for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { + reg = in_be32(&serdes2_base->bank[i].pllcr0); + if (!((reg >> 23) & 0x1)) { + reg = in_be32(&serdes2_base->bank[i].rstctl); + reg |= 0x20000000; + out_be32(&serdes2_base->bank[i].rstctl, reg); + } else { + udelay(1); + reg = in_be32(&serdes2_base->bank[i].rstctl); + reg &= 0xFFFFFFEF; + reg |= 0x00000040; + out_be32(&serdes2_base->bank[i].rstctl, reg); + udelay(1); + } + } +#endif + + /* Take the all enabled lanes out of reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { + reg = in_be32(&serdes1_base->lane[i].gcr0); + reg |= 0x00600000; + out_be32(&serdes1_base->lane[i].gcr0, reg); + } +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; + cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; + + for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { + reg = in_be32(&serdes2_base->lane[i].gcr0); + reg |= 0x00600000; + out_be32(&serdes2_base->lane[i].gcr0, reg); + } +#endif + /* For each PLL being reset, and achieved PLL lock set RST_DONE */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = (cfg_rcw5 >> 22) & 0x3; + for (i = 0; i < 2; i++) { + reg = in_be32(&serdes1_base->bank[i].pllcr0); + if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) { + reg = in_be32(&serdes1_base->bank[i].rstctl); + reg |= 0x40000000; + out_be32(&serdes1_base->bank[i].rstctl, reg); + } + } +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = (cfg_rcw5 >> 20) & 0x3; + for (i = 0; i < 2; i++) { + reg = in_be32(&serdes2_base->bank[i].pllcr0); + if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) { + reg = in_be32(&serdes2_base->bank[i].rstctl); + reg |= 0x40000000; + out_be32(&serdes2_base->bank[i].rstctl, reg); + } + } +#endif + + return ret; +} + void fsl_serdes_init(void) { #ifdef CONFIG_SYS_FSL_SRDS_1 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 2f54625..c0fd1a6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -336,6 +336,95 @@ static void erratum_a010539(void) #endif } +/* Get VDD in the unit mV from voltage ID */ +int get_core_volt_from_fuse(void) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + int vdd; + u32 fusesr; + u8 vid; + + fusesr = in_be32(&gur->dcfg_fusesr); + debug("%s: fusesr = 0x%x\n", __func__, fusesr); + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; + } + debug("%s: VID = 0x%x\n", __func__, vid); + switch (vid) { + case 0x00: /* VID isn't supported */ + vdd = -EINVAL; + debug("%s: The VID feature is not supported\n", __func__); + break; + case 0x08: /* 0.9V silicon */ + vdd = 900; + break; + case 0x10: /* 1.0V silicon */ + vdd = 1000; + break; + default: /* Other core voltage */ + vdd = -EINVAL; + printf("%s: The VID(%x) isn't supported\n", __func__, vid); + break; + } + debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); + + return vdd; +} + +__weak int board_switch_core_volt(u32 vdd) +{ + return 0; +} + +static int setup_core_volt(u32 vdd) +{ + return board_setup_core_volt(vdd); +} + +#ifdef CONFIG_SYS_FSL_DDR +static void ddr_enable_0v9_volt(bool en) +{ + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + u32 tmp; + + tmp = ddr_in32(&ddr->ddr_cdr1); + + if (en) + tmp |= DDR_CDR1_V0PT9_EN; + else + tmp &= ~DDR_CDR1_V0PT9_EN; + + ddr_out32(&ddr->ddr_cdr1, tmp); +} +#endif + +int setup_chip_volt(void) +{ + int vdd; + + vdd = get_core_volt_from_fuse(); + /* Nothing to do for silicons doesn't support VID */ + if (vdd < 0) + return vdd; + + if (setup_core_volt(vdd)) + printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd); +#ifdef CONFIG_SYS_HAS_SERDES + if (setup_serdes_volt(vdd)) + printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd); +#endif + +#ifdef CONFIG_SYS_FSL_DDR + if (vdd == 900) + ddr_enable_0v9_volt(true); +#endif + + return 0; +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 9f94b45..d9d948e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -162,6 +162,14 @@ int is_serdes_prtcl_valid(int serdes, u32 prtcl); #ifdef CONFIG_FSL_LSCH2 const char *serdes_clock_to_string(u32 clock); int get_serdes_protocol(void); +#ifdef CONFIG_SYS_HAS_SERDES +/* Get the volt of SVDD in unit mV */ +int get_serdes_volt(void); +/* Set the volt of SVDD in unit mV */ +int set_serdes_volt(int svdd); +/* The target volt of SVDD in unit mV */ +int setup_serdes_volt(u32 svdd); +#endif #endif #endif /* __FSL_SERDES_H__ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 78363b6..9bafa6d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -99,6 +99,9 @@ struct ccsr_ahci { void fsl_lsch3_early_init_f(void); #elif defined(CONFIG_FSL_LSCH2) void fsl_lsch2_early_init_f(void); +int setup_chip_volt(void); +/* Setup core vdd in unit mV */ +int board_setup_core_volt(u32 vdd); #endif void cpu_name(char *name); diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 1404c57..b8de46b 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -173,6 +173,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; /* DDR_CDR1 */ #define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_V0PT9_EN 0x40000000 #define DDR_CDR1_ODT_SHIFT 17 #define DDR_CDR1_ODT_MASK 0x6 #define DDR_CDR2_ODT_MASK 0x1 -- cgit v0.10.2 From dccef2ec01cdf5403d78223fd60a4ccd761ae6b0 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 9 Dec 2016 16:09:01 +0800 Subject: ls1046ardb: Add support power initialization Add the chip power supply voltage initialization on LS1046ARDB. Add function power_init_board(), and it will initialize the PMIC and call the chip power initialization function. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0ed36cd..80038ec 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -844,6 +844,7 @@ config TARGET_LS1046ARDB select ARMV8_MULTIENTRY select SUPPORT_SPL select DM_SPI_FLASH if DM_SPI + select POWER_MC34VR500 help Support for Freescale LS1046ARDB platform. The LS1046A Reference Design Board (RDB) is a high-performance diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 585c807..33a58cf 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "cpld.h" DECLARE_GLOBAL_DATA_PTR; @@ -87,6 +88,39 @@ int board_init(void) return 0; } +int board_setup_core_volt(u32 vdd) +{ + bool en_0v9; + + en_0v9 = (vdd == 900) ? true : false; + cpld_select_core_volt(en_0v9); + + return 0; +} + +int get_serdes_volt(void) +{ + return mc34vr500_get_sw_volt(SW4); +} + +int set_serdes_volt(int svdd) +{ + return mc34vr500_set_sw_volt(SW4, svdd); +} + +int power_init_board(void) +{ + int ret; + + ret = power_mc34vr500_init(0); + if (ret) + return ret; + + setup_chip_volt(); + + return 0; +} + void config_board_mux(void) { #ifdef CONFIG_HAS_FSL_XHCI_USB diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 8a8f942..2bfd83c 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -164,6 +164,12 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define I2C_RETIMER_ADDR 0x18 +/* PMIC */ +#define CONFIG_POWER +#ifdef CONFIG_POWER +#define CONFIG_POWER_I2C +#endif + /* * Environment */ -- cgit v0.10.2 From 435cca167149d19a9740806f63a3f58388280507 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Thu, 1 Dec 2016 17:06:58 +0800 Subject: armv8: fsl-lsch3: enable snoopable sata read and write By default the SATA IP on the ls208Xa SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. Signed-off-by: Tang Yuantian Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index c0fd1a6..9489f85 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -213,10 +213,12 @@ int sata_init(void) ccsr_ahci = (void *)CONFIG_SYS_SATA2; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); ccsr_ahci = (void *)CONFIG_SYS_SATA1; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); ahci_init((void __iomem *)CONFIG_SYS_SATA1); scsi_scan(0); -- cgit v0.10.2 From fa18ed76589a684fc9ba14b68d7b917b1bea16cf Mon Sep 17 00:00:00 2001 From: Wenbin Song Date: Tue, 17 Jan 2017 18:31:15 +0800 Subject: armv8/ls1043a: fixup GIC offset for ls1043a rev1 The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song Signed-off-by: Mingkai Hu Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 79e2dd6..dce1689 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -90,6 +90,11 @@ config FSL_PCIE_COMPAT This compatible is used to find pci controller node in Kernel DT to complete fixup. +config HAS_FEATURE_GIC64K_ALIGN + bool + default y if ARCH_LS1043A + + menu "Layerscape PPA" config FSL_LS_PPA bool "FSL Layerscape PPA firmware support" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index c10ccf9..f289172 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -133,6 +133,67 @@ void fsl_fdt_disable_usb(void *blob) } } +#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN +static void fdt_fixup_gic(void *blob) +{ + int offset, err; + u64 reg[8]; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int val; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + int align_64k = 0; + + val = gur_in32(&gur->svr); + + if (SVR_SOC_VER(val) != SVR_LS1043A) { + align_64k = 1; + } else if (SVR_REV(val) != REV1_0) { + val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT); + if (!val) + align_64k = 1; + } + + offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000"); + if (offset < 0) { + printf("WARNING: fdt_subnode_offset can't find node %s: %s\n", + "interrupt-controller@1400000", fdt_strerror(offset)); + return; + } + + /* Fixup gic node align with 64K */ + if (align_64k) { + reg[0] = cpu_to_fdt64(GICD_BASE_64K); + reg[1] = cpu_to_fdt64(GICD_SIZE_64K); + reg[2] = cpu_to_fdt64(GICC_BASE_64K); + reg[3] = cpu_to_fdt64(GICC_SIZE_64K); + reg[4] = cpu_to_fdt64(GICH_BASE_64K); + reg[5] = cpu_to_fdt64(GICH_SIZE_64K); + reg[6] = cpu_to_fdt64(GICV_BASE_64K); + reg[7] = cpu_to_fdt64(GICV_SIZE_64K); + } else { + /* Fixup gic node align with default */ + reg[0] = cpu_to_fdt64(GICD_BASE); + reg[1] = cpu_to_fdt64(GICD_SIZE); + reg[2] = cpu_to_fdt64(GICC_BASE); + reg[3] = cpu_to_fdt64(GICC_SIZE); + reg[4] = cpu_to_fdt64(GICH_BASE); + reg[5] = cpu_to_fdt64(GICH_SIZE); + reg[6] = cpu_to_fdt64(GICV_BASE); + reg[7] = cpu_to_fdt64(GICV_SIZE); + } + + err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg)); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s\n", + "reg", "interrupt-controller@1400000", + fdt_strerror(err)); + return; + } + + return; +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FSL_LSCH2 @@ -177,4 +238,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif fsl_fdt_disable_usb(blob); +#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN + fdt_fixup_gic(blob); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 04a2598..62efa90 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -10,15 +10,66 @@ #include #include #include +#include #ifdef CONFIG_MP #include #endif #ifdef CONFIG_FSL_LSCH3 #include -#include #endif #include +/* Get GIC offset +* For LS1043a rev1.0, GIC base address align with 4k. +* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT] +* is set, GIC base address align with 4K, or else align +* with 64k. +* output: +* x0: the base address of GICD +* x1: the base address of GICC +*/ +ENTRY(get_gic_offset) + ldr x0, =GICD_BASE +#ifdef CONFIG_GICV2 + ldr x1, =GICC_BASE +#endif +#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN + ldr x2, =DCFG_CCSR_SVR + ldr w2, [x2] + rev w2, w2 + mov w3, w2 + ands w3, w3, #SVR_WO_E << 8 + mov w4, #SVR_LS1043A << 8 + cmp w3, w4 + b.ne 1f + ands w2, w2, #0xff + cmp w2, #REV1_0 + b.eq 1f + ldr x2, =SCFG_GIC400_ALIGN + ldr w2, [x2] + rev w2, w2 + tbnz w2, #GIC_ADDR_BIT, 1f + ldr x0, =GICD_BASE_64K +#ifdef CONFIG_GICV2 + ldr x1, =GICC_BASE_64K +#endif +1: +#endif + ret +ENDPROC(get_gic_offset) + +ENTRY(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + mov x29, lr /* Save LR */ + bl get_gic_offset + bl gic_kick_secondary_cpus + mov lr, x29 /* Restore LR */ +#endif + ret +ENDPROC(smp_kick_all_cpus) + + ENTRY(lowlevel_init) mov x29, lr /* Save LR */ @@ -130,15 +181,14 @@ ENTRY(lowlevel_init) /* Initialize GIC Secure Bank Status */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f - ldr x0, =GICD_BASE + bl get_gic_offset bl gic_init_secure 1: #ifdef CONFIG_GICV3 ldr x0, =GICR_BASE bl gic_init_secure_percpu #elif defined(CONFIG_GICV2) - ldr x0, =GICD_BASE - ldr x1, =GICC_BASE + bl get_gic_offset bl gic_init_secure_percpu #endif #endif @@ -413,7 +463,8 @@ ENTRY(secondary_boot_func) #if defined(CONFIG_GICV3) gic_wait_for_interrupt_m x0 #elif defined(CONFIG_GICV2) - ldr x0, =GICC_BASE + bl get_gic_offset + mov x0, x1 gic_wait_for_interrupt_m x0, w1 #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 045825e..8c426af 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -163,6 +163,28 @@ /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define GICH_BASE 0x01404000 +#define GICV_BASE 0x01406000 +#define GICD_SIZE 0x1000 +#define GICC_SIZE 0x2000 +#define GICH_SIZE 0x2000 +#define GICV_SIZE 0x2000 +#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN +#define GICD_BASE_64K 0x01410000 +#define GICC_BASE_64K 0x01420000 +#define GICH_BASE_64K 0x01440000 +#define GICV_BASE_64K 0x01460000 +#define GICD_SIZE_64K 0x10000 +#define GICC_SIZE_64K 0x20000 +#define GICH_SIZE_64K 0x20000 +#define GICV_SIZE_64K 0x20000 +#endif + +#define DCFG_CCSR_SVR 0x1ee00a4 +#define REV1_0 0x10 +#define REV1_1 0x11 +#define GIC_ADDR_BIT 31 +#define SCFG_GIC400_ALIGN 0x1570188 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 6ace3da..8ad199f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -361,7 +361,8 @@ struct ccsr_scfg { u32 qspi_cfg; u8 res_160[0x180-0x160]; u32 dmamcr; - u8 res_184[0x18c-0x184]; + u8 res_184[0x188-0x184]; + u32 gic_align; u32 debug_icid; u8 res_190[0x1a4-0x190]; u32 snpcnfgcr; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 9bafa6d..426fe8e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -59,6 +59,7 @@ struct cpu_type { #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) +#define SVR_REV(svr) (((svr) >> 0) & 0xff) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) #define IS_SVR_REV(svr, maj, min) \ -- cgit v0.10.2 From 2ca84bf7b2d7930b424b19f5027d3c06ec7cb696 Mon Sep 17 00:00:00 2001 From: Wenbin Song Date: Tue, 17 Jan 2017 18:31:16 +0800 Subject: armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if rev1.1 silicon used, need to fixup the MSI node to match it. Signed-off-by: Wenbin Song Signed-off-by: Mingkai Hu Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index dce1689..66588e9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -94,6 +94,9 @@ config HAS_FEATURE_GIC64K_ALIGN bool default y if ARCH_LS1043A +config HAS_FEATURE_ENHANCED_MSI + bool + default y if ARCH_LS1043A menu "Layerscape PPA" config FSL_LS_PPA diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index f289172..dae9605 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -194,6 +194,157 @@ static void fdt_fixup_gic(void *blob) } #endif +#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI +static int _fdt_fixup_msi_node(void *blob, const char *name, + int irq_0, int irq_1, int rev) +{ + int err, offset, len; + u32 tmp[4][3]; + void *p; + + offset = fdt_path_offset(blob, name); + if (offset < 0) { + printf("WARNING: fdt_path_offset can't find path %s: %s\n", + name, fdt_strerror(offset)); + return 0; + } + + /*fixup the property of interrupts*/ + + tmp[0][0] = cpu_to_fdt32(0x0); + tmp[0][1] = cpu_to_fdt32(irq_0); + tmp[0][2] = cpu_to_fdt32(0x4); + + if (rev > REV1_0) { + tmp[1][0] = cpu_to_fdt32(0x0); + tmp[1][1] = cpu_to_fdt32(irq_1); + tmp[1][2] = cpu_to_fdt32(0x4); + tmp[2][0] = cpu_to_fdt32(0x0); + tmp[2][1] = cpu_to_fdt32(irq_1 + 1); + tmp[2][2] = cpu_to_fdt32(0x4); + tmp[3][0] = cpu_to_fdt32(0x0); + tmp[3][1] = cpu_to_fdt32(irq_1 + 2); + tmp[3][2] = cpu_to_fdt32(0x4); + len = sizeof(tmp); + } else { + len = sizeof(tmp[0]); + } + + err = fdt_setprop(blob, offset, "interrupts", tmp, len); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s\n", + "interrupts", name, fdt_strerror(err)); + return 0; + } + + /*fixup the property of reg*/ + p = (char *)fdt_getprop(blob, offset, "reg", &len); + if (!p) { + printf("WARNING: fdt_getprop can't get %s from node %s\n", + "reg", name); + return 0; + } + + memcpy((char *)tmp, p, len); + + if (rev > REV1_0) + *((u32 *)tmp + 3) = cpu_to_fdt32(0x1000); + else + *((u32 *)tmp + 3) = cpu_to_fdt32(0x8); + + err = fdt_setprop(blob, offset, "reg", tmp, len); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s\n", + "reg", name, fdt_strerror(err)); + return 0; + } + + /*fixup the property of compatible*/ + if (rev > REV1_0) + err = fdt_setprop_string(blob, offset, "compatible", + "fsl,ls1043a-v1.1-msi"); + else + err = fdt_setprop_string(blob, offset, "compatible", + "fsl,ls1043a-msi"); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s\n", + "compatible", name, fdt_strerror(err)); + return 0; + } + + return 1; +} + +static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev) +{ + int offset, len, err; + void *p; + int val; + u32 tmp[4][8]; + + offset = fdt_path_offset(blob, name); + if (offset < 0) { + printf("WARNING: fdt_path_offset can't find path %s: %s\n", + name, fdt_strerror(offset)); + return 0; + } + + p = (char *)fdt_getprop(blob, offset, "interrupt-map", &len); + if (!p || len != sizeof(tmp)) { + printf("WARNING: fdt_getprop can't get %s from node %s\n", + "interrupt-map", name); + return 0; + } + + memcpy((char *)tmp, p, len); + + val = fdt32_to_cpu(tmp[0][6]); + if (rev > REV1_0) { + tmp[1][6] = cpu_to_fdt32(val + 1); + tmp[2][6] = cpu_to_fdt32(val + 2); + tmp[3][6] = cpu_to_fdt32(val + 3); + } else { + tmp[1][6] = cpu_to_fdt32(val); + tmp[2][6] = cpu_to_fdt32(val); + tmp[3][6] = cpu_to_fdt32(val); + } + + err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp)); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n", + "interrupt-map", name, fdt_strerror(err)); + return 0; + } + return 1; +} + +/* Fixup msi node for ls1043a rev1.1*/ + +static void fdt_fixup_msi(void *blob) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int rev; + + rev = gur_in32(&gur->svr); + + if (SVR_SOC_VER(rev) != SVR_LS1043A) + return; + + rev = SVR_REV(rev); + + _fdt_fixup_msi_node(blob, "/soc/msi-controller1@1571000", + 116, 111, rev); + _fdt_fixup_msi_node(blob, "/soc/msi-controller2@1572000", + 126, 121, rev); + _fdt_fixup_msi_node(blob, "/soc/msi-controller3@1573000", + 160, 155, rev); + + _fdt_fixup_pci_msi(blob, "/soc/pcie@3400000", rev); + _fdt_fixup_pci_msi(blob, "/soc/pcie@3500000", rev); + _fdt_fixup_pci_msi(blob, "/soc/pcie@3600000", rev); +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FSL_LSCH2 @@ -241,4 +392,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN fdt_fixup_gic(blob); #endif +#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI + fdt_fixup_msi(blob); +#endif } -- cgit v0.10.2 From 7c5e1feb1d780cc857632c246e78ac7a8e6cf2d7 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 17 Jan 2017 09:39:17 +0800 Subject: armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang Reviewed-by: Alexander Graf Tested-by: Ryan Harkin Tested-by: Michal Simek Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 62efa90..a2185f2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -486,29 +486,29 @@ cpu_is_le: b.eq 1f #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x3, secondary_switch_to_el1 - ldr x4, =ES_TO_AARCH64 + adr x4, secondary_switch_to_el1 + ldr x5, =ES_TO_AARCH64 #else - ldr x3, [x11] - ldr x4, =ES_TO_AARCH32 + ldr x4, [x11] + ldr x5, =ES_TO_AARCH32 #endif bl secondary_switch_to_el2 1: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x3, secondary_switch_to_el1 + adr x4, secondary_switch_to_el1 #else - ldr x3, [x11] + ldr x4, [x11] #endif - ldr x4, =ES_TO_AARCH64 + ldr x5, =ES_TO_AARCH64 bl secondary_switch_to_el2 ENDPROC(secondary_boot_func) ENTRY(secondary_switch_to_el2) - switch_el x5, 1f, 0f, 0f + switch_el x6, 1f, 0f, 0f 0: ret -1: armv8_switch_to_el2_m x3, x4, x5 +1: armv8_switch_to_el2_m x4, x5, x6 ENDPROC(secondary_switch_to_el2) ENTRY(secondary_switch_to_el1) @@ -522,22 +522,22 @@ ENTRY(secondary_switch_to_el1) /* physical address of this cpus spin table element */ add x11, x1, x0 - ldr x3, [x11] + ldr x4, [x11] ldr x5, [x11, #24] ldr x6, =IH_ARCH_DEFAULT cmp x6, x5 b.eq 2f - ldr x4, =ES_TO_AARCH32 + ldr x5, =ES_TO_AARCH32 bl switch_to_el1 -2: ldr x4, =ES_TO_AARCH64 +2: ldr x5, =ES_TO_AARCH64 switch_to_el1: - switch_el x5, 0f, 1f, 0f + switch_el x6, 0f, 1f, 0f 0: ret -1: armv8_switch_to_el1_m x3, x4, x5 +1: armv8_switch_to_el1_m x4, x5, x6 ENDPROC(secondary_switch_to_el1) /* Ensure that the literals used by the secondary boot code are diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 903195d..5ed3677 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -57,7 +57,8 @@ ENDPROC(_sec_firmware_support_psci_version) * x0: argument, zero * x1: machine nr * x2: fdt address - * x3: kernel entry point + * x3: input argument + * x4: kernel entry point * @param outputs for secure firmware: * x0: function id * x1: kernel entry point @@ -65,10 +66,9 @@ ENDPROC(_sec_firmware_support_psci_version) * x3: fdt address */ ENTRY(armv8_el2_to_aarch32) - mov x0, x3 mov x3, x2 mov x2, x1 - mov x1, x0 + mov x1, x4 ldr x0, =0xc000ff04 smc #0 ret diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 5308702..368e3dc 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -262,14 +262,14 @@ WEAK(lowlevel_init) /* * All slaves will enter EL2 and optionally EL1. */ - adr x3, lowlevel_in_el2 - ldr x4, =ES_TO_AARCH64 + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el2 lowlevel_in_el2: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x3, lowlevel_in_el1 - ldr x4, =ES_TO_AARCH64 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el1 lowlevel_in_el1: diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index adb9f35..ca07465 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -11,9 +11,9 @@ #include ENTRY(armv8_switch_to_el2) - switch_el x5, 1f, 0f, 0f + switch_el x6, 1f, 0f, 0f 0: - cmp x4, #ES_TO_AARCH64 + cmp x5, #ES_TO_AARCH64 b.eq 2f /* * When loading 32-bit kernel, it will jump @@ -22,23 +22,23 @@ ENTRY(armv8_switch_to_el2) bl armv8_el2_to_aarch32 2: /* - * x3 is kernel entry point or switch_to_el1 + * x4 is kernel entry point or switch_to_el1 * if CONFIG_ARMV8_SWITCH_TO_EL1 is defined. * When running in EL2 now, jump to the - * address saved in x3. + * address saved in x4. */ - br x3 -1: armv8_switch_to_el2_m x3, x4, x5 + br x4 +1: armv8_switch_to_el2_m x4, x5, x6 ENDPROC(armv8_switch_to_el2) ENTRY(armv8_switch_to_el1) - switch_el x5, 0f, 1f, 0f + switch_el x6, 0f, 1f, 0f 0: - /* x3 is kernel entry point. When running in EL1 - * now, jump to the address saved in x3. + /* x4 is kernel entry point. When running in EL1 + * now, jump to the address saved in x4. */ - br x3 -1: armv8_switch_to_el1_m x3, x4, x5 + br x4 +1: armv8_switch_to_el1_m x4, x5, x6 ENDPROC(armv8_switch_to_el1) WEAK(armv8_el2_to_aarch32) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index dc4c991..766e929 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -196,11 +196,12 @@ void __asm_switch_ttbr(u64 new_ttbr); * For loading 32-bit OS, machine nr * @fdt_addr: For loading 64-bit OS, zero. * For loading 32-bit OS, fdt address. + * @arg4: Input argument. * @entry_point: kernel entry point * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 */ void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, - u64 entry_point, u64 es_flag); + u64 arg4, u64 entry_point, u64 es_flag); /* * Switch from EL2 to EL1 for ARMv8 * @@ -210,13 +211,14 @@ void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, * For loading 32-bit OS, machine nr * @fdt_addr: For loading 64-bit OS, zero. * For loading 32-bit OS, fdt address. + * @arg4: Input argument. * @entry_point: kernel entry point * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 */ void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr, - u64 entry_point, u64 es_flag); + u64 arg4, u64 entry_point, u64 es_flag); void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr, - u64 entry_point); + u64 arg4, u64 entry_point); void gic_init(void); void gic_send_sgi(unsigned long sgino); void wait_for_wakeup(void); diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 43cc83e..8125cf0 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -287,11 +287,11 @@ static void switch_to_el1(void) if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) && (images.os.arch == IH_ARCH_ARM)) armv8_switch_to_el1(0, (u64)gd->bd->bi_arch_number, - (u64)images.ft_addr, + (u64)images.ft_addr, 0, (u64)images.ep, ES_TO_AARCH32); else - armv8_switch_to_el1((u64)images.ft_addr, 0, 0, + armv8_switch_to_el1((u64)images.ft_addr, 0, 0, 0, images.ep, ES_TO_AARCH64); } @@ -324,17 +324,17 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) update_os_arch_secondary_cores(images->os.arch); #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - armv8_switch_to_el2((u64)images->ft_addr, 0, 0, + armv8_switch_to_el2((u64)images->ft_addr, 0, 0, 0, (u64)switch_to_el1, ES_TO_AARCH64); #else if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) && (images->os.arch == IH_ARCH_ARM)) armv8_switch_to_el2(0, (u64)gd->bd->bi_arch_number, - (u64)images->ft_addr, + (u64)images->ft_addr, 0, (u64)images->ep, ES_TO_AARCH32); else - armv8_switch_to_el2((u64)images->ft_addr, 0, 0, + armv8_switch_to_el2((u64)images->ft_addr, 0, 0, 0, images->ep, ES_TO_AARCH64); #endif diff --git a/arch/arm/mach-rmobile/lowlevel_init_gen3.S b/arch/arm/mach-rmobile/lowlevel_init_gen3.S index 11acce0..ce3d4f5 100644 --- a/arch/arm/mach-rmobile/lowlevel_init_gen3.S +++ b/arch/arm/mach-rmobile/lowlevel_init_gen3.S @@ -61,14 +61,14 @@ ENTRY(lowlevel_init) /* * All slaves will enter EL2 and optionally EL1. */ - adr x3, lowlevel_in_el2 - ldr x4, =ES_TO_AARCH64 + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el2 lowlevel_in_el2: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x3, lowlevel_in_el1 - ldr x4, =ES_TO_AARCH64 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el1 lowlevel_in_el1: diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 97a0fc9..06943a9 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -246,7 +246,7 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt) /* Move into EL2 and keep running there */ armv8_switch_to_el2((ulong)entry, (ulong)&loaded_image_info, - (ulong)&systab, (ulong)efi_run_in_el2, + (ulong)&systab, 0, (ulong)efi_run_in_el2, ES_TO_AARCH64); /* Should never reach here, efi exits with longjmp */ -- cgit v0.10.2 From 0897eb2ced0579ee58b7d50076faa93605e33ed1 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 16 Jan 2017 17:31:47 +0800 Subject: kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig Signed-off-by: Hou Zhiqiang [York S: clean up scripts/config_whitelist.txt] Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 472b2ba..7ef9c2f 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -39,6 +39,39 @@ config ARMV8_SPIN_TABLE - Reserve the code for the spin-table and the release address via a /memreserve/ region in the Device Tree. +menu "ARMv8 secure monitor firmware" +config ARMV8_SEC_FIRMWARE_SUPPORT + bool "Enable ARMv8 secure monitor firmware framework support" + select OF_LIBFDT + select FIT + help + This framework is aimed at making secure monitor firmware load + process brief. + Note: Only FIT format image is supported. + You should prepare and provide the below information: + - Address of secure firmware. + - Address to hold the return address from secure firmware. + - Secure firmware FIT image related information. + Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME + - The target exception level that secure monitor firmware will + return to. + +config SPL_ARMV8_SEC_FIRMWARE_SUPPORT + bool "Enable ARMv8 secure monitor firmware framework support for SPL" + select SPL_OF_LIBFDT + select SPL_FIT + help + Say Y here to support this framework in SPL phase. + +config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT + bool "ARMv8 secure monitor firmware ERET address byteorder swap" + depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT + help + Say Y here when the endianness of the register or memory holding the + Secure firmware exception return address is different with core's. + +endmenu + config PSCI_RESET bool "Use PSCI for reset and shutdown" default y diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 28ba786..1f1de4a 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -19,7 +19,7 @@ obj-y += cpu-dt.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o endif -obj-$(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o +obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ obj-$(CONFIG_S32V234) += s32v234/ diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 5ed3677..3275e95 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -23,12 +23,12 @@ WEAK(_sec_firmware_entry) /* Set exception return address hold pointer */ adr x4, 1f mov x3, x4 -#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT rev w3, w3 #endif str w3, [x1] lsr x3, x4, #32 -#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT rev w3, w3 #endif str w3, [x2] diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 36df331..3657f21 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -10,9 +10,6 @@ #include "ls1043a_common.h" #if defined(CONFIG_FSL_LS_PPA) -#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT -#define SEC_FIRMWARE_ERET_ADDR_REVERT - #define CONFIG_SYS_LS_PPA_FW_IN_XIP #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP #define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 2bfd83c..08c5441 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -10,10 +10,6 @@ #include "ls1046a_common.h" #if defined(CONFIG_FSL_LS_PPA) -#define CONFIG_ARMV8_PSCI -#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT -#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024) - #define CONFIG_SYS_LS_PPA_FW_IN_XIP #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP #define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 00ee3f1..da19e8e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -181,7 +181,6 @@ CONFIG_ARMV7_PSCI_1_0 CONFIG_ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_MAX_SIZE CONFIG_ARMV7_SECURE_RESERVE_SIZE -CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT CONFIG_ARMV8_SWITCH_TO_EL1 CONFIG_ARM_ARCH_CP15_ERRATA CONFIG_ARM_ASM_UNIFIED -- cgit v0.10.2 From daa926448c95ae758400737d87fad288ec7077e2 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 16 Jan 2017 17:31:48 +0800 Subject: ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCI Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 7ef9c2f..0b3d98e 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -63,6 +63,14 @@ config SPL_ARMV8_SEC_FIRMWARE_SUPPORT help Say Y here to support this framework in SPL phase. +config SEC_FIRMWARE_ARMV8_PSCI + bool "PSCI implementation in secure monitor firmware" + depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT + help + This config enables the ARMv8 PSCI implementation in secure monitor + firmware. This is a private PSCI implementation and different from + those implemented under the common ARMv8 PSCI framework. + config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT bool "ARMv8 secure monitor firmware ERET address byteorder swap" depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 3a5afe8..5156a15 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -14,7 +14,7 @@ int psci_update_dt(void *fdt) { #ifdef CONFIG_MP -#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_FSL_PPA_ARMV8_PSCI) +#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT /* diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 66588e9..0b8d300 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -103,20 +103,12 @@ config FSL_LS_PPA bool "FSL Layerscape PPA firmware support" depends on !ARMV8_PSCI depends on ARCH_LS1043A || ARCH_LS1046A - select FSL_PPA_ARMV8_PSCI + select SEC_FIRMWARE_ARMV8_PSCI help The FSL Primary Protected Application (PPA) is a software component which is loaded during boot stage, and then remains resident in RAM and runs in the TrustZone after boot. Say y to enable it. - -config FSL_PPA_ARMV8_PSCI - bool "PSCI implementation in PPA firmware" - depends on FSL_LS_PPA - help - This config enables the ARMv8 PSCI implementation in PPA firmware. - This is a private PSCI implementation and different from those - implemented under the common ARMv8 PSCI framework. endmenu config SYS_FSL_ERRATUM_A010315 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 3bdeb0e..335f225 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -412,7 +412,7 @@ int arch_early_init_r(void) #endif #ifdef CONFIG_MP #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ - defined(CONFIG_FSL_PPA_ARMV8_PSCI) + defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) /* Check the psci version to determine if the psci is supported */ psci_ver = sec_firmware_support_psci_version(); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index dae9605..26d4a30 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -43,7 +43,7 @@ void ft_fixup_cpu(void *blob) u64 val, core_id; size_t *boot_code_size = &(__secondary_boot_code_size); #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ - defined(CONFIG_FSL_PPA_ARMV8_PSCI) + defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) int node; u32 psci_ver; diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 0b973f0..ec9cf40 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -209,7 +209,7 @@ __weak bool sec_firmware_is_valid(const void *sec_firmware_img) return true; } -#ifdef CONFIG_FSL_PPA_ARMV8_PSCI +#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI /* * The PSCI_VERSION function is added from PSCI v0.2. When the PSCI * v0.1 received this function, the NOT_SUPPORTED (0xffff_ffff) error diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 3275e95..30563eb 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -41,7 +41,7 @@ WEAK(_sec_firmware_entry) ret ENDPROC(_sec_firmware_entry) -#ifdef CONFIG_FSL_PPA_ARMV8_PSCI +#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI ENTRY(_sec_firmware_support_psci_version) mov x0, 0x84000000 mov x1, 0x0 diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h index a4e144b..5ae00fa 100644 --- a/arch/arm/include/asm/armv8/sec_firmware.h +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -14,7 +14,7 @@ int sec_firmware_init(const void *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *); bool sec_firmware_is_valid(const void *); -#ifdef CONFIG_FSL_PPA_ARMV8_PSCI +#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI unsigned int sec_firmware_support_psci_version(void); unsigned int _sec_firmware_support_psci_version(void); #endif diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index e261d4f..d84789c 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -53,7 +53,7 @@ int arch_fixup_fdt(void *blob) #endif #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) || \ - defined(CONFIG_FSL_PPA_ARMV8_PSCI) + defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) ret = psci_update_dt(blob); if (ret) return ret; diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index 45af037..05e0ad6 100644 --- a/arch/arm/lib/psci-dt.c +++ b/arch/arm/lib/psci-dt.c @@ -17,7 +17,7 @@ int fdt_psci(void *fdt) { #if defined(CONFIG_ARMV7_PSCI) || defined(CONFIG_ARMV8_PSCI) || \ - defined(CONFIG_FSL_PPA_ARMV8_PSCI) + defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) int nodeoff; unsigned int psci_ver = 0; int tmp; -- cgit v0.10.2 From 0541527bde7d2df155fc9691115d234fa7a3f603 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 16 Jan 2017 17:31:49 +0800 Subject: kconfig: fsl PPA: move CONFIG_* to Kconfig Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 0b8d300..ba411e2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -102,13 +102,37 @@ menu "Layerscape PPA" config FSL_LS_PPA bool "FSL Layerscape PPA firmware support" depends on !ARMV8_PSCI - depends on ARCH_LS1043A || ARCH_LS1046A + select ARMV8_SEC_FIRMWARE_SUPPORT select SEC_FIRMWARE_ARMV8_PSCI + select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 help The FSL Primary Protected Application (PPA) is a software component which is loaded during boot stage, and then remains resident in RAM and runs in the TrustZone after boot. Say y to enable it. +choice + prompt "FSL Layerscape PPA firmware loading-media select" + depends on FSL_LS_PPA + default SYS_LS_PPA_FW_IN_XIP + +config SYS_LS_PPA_FW_IN_XIP + bool "XIP" + help + Say Y here if the PPA firmware locate at XIP flash, such + as NOR or QSPI flash. + +endchoice + +config SYS_LS_PPA_FW_ADDR + hex "Address of PPA firmware loading from" + depends on FSL_LS_PPA + default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT + default 0x60500000 if SYS_LS_PPA_FW_IN_XIP + help + If the PPA firmware locate at XIP flash, such as NOR or + QSPI flash, this address is a directly memory-mapped. + If it is in a serial accessed flash, such as NAND and SD + card, it is a byte offset. endmenu config SYS_FSL_ERRATUM_A010315 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 423b4b3..c9ab93e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -10,7 +10,7 @@ obj-y += soc.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SPL) += spl.o -obj-$(CONFIG_FSL_LS_PPA) += ppa.o +obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o ifneq ($(CONFIG_FSL_LSCH3),) obj-y += fsl_lsch3_speed.o diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 3657f21..0054d16 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -9,13 +9,6 @@ #include "ls1043a_common.h" -#if defined(CONFIG_FSL_LS_PPA) -#define CONFIG_SYS_LS_PPA_FW_IN_XIP -#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP -#define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 -#endif -#endif - #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) #define CONFIG_SYS_TEXT_BASE 0x82000000 #else diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 08c5441..24843dc 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -9,13 +9,6 @@ #include "ls1046a_common.h" -#if defined(CONFIG_FSL_LS_PPA) -#define CONFIG_SYS_LS_PPA_FW_IN_XIP -#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP -#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000 -#endif -#endif - #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_TEXT_BASE 0x82000000 #else -- cgit v0.10.2 From b595662ab991e833bc4ef5160b0fa5b377f67d08 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 16 Jan 2017 17:31:50 +0800 Subject: fsl PPA: enable PPA for ls1043ardb and ls1046ardb Enable PPA for ls1043ardb NOR boot and ls1046ardb QSPI boot. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 51cabc7..a86ad88 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 2a72132..cc7dfa1 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_QSPI_AHB_INIT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 -- cgit v0.10.2 From fce1e16c55ff9c93c21adad0155e435bcfe2fa6b Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 17 Jan 2017 10:43:54 +0800 Subject: mmc: fsl_esdhc: move 'status' property fixup into a weak function Move fdt fixup of 'status' property into a weak function. This allows board to define 'status' fdt fixup by themselves. Signed-off-by: Yangbo Lu Reviewed-by: York Sun diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0ae1cfd..7b7863f 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -911,17 +911,26 @@ void mmc_adapter_card_type_ident(void) #endif #ifdef CONFIG_OF_LIBFDT -void fdt_fixup_esdhc(void *blob, bd_t *bd) +__weak int esdhc_status_fixup(void *blob, const char *compat) { - const char *compat = "fsl,esdhc"; - #ifdef CONFIG_FSL_ESDHC_PIN_MUX if (!hwconfig("esdhc")) { do_fixup_by_compat(blob, compat, "status", "disabled", - 8 + 1, 1); - return; + sizeof("disabled"), 1); + return 1; } #endif + do_fixup_by_compat(blob, compat, "status", "okay", + sizeof("okay"), 1); + return 0; +} + +void fdt_fixup_esdhc(void *blob, bd_t *bd) +{ + const char *compat = "fsl,esdhc"; + + if (esdhc_status_fixup(blob, compat)) + return; #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", @@ -934,8 +943,6 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, compat, "adapter-type", (u32)(gd->arch.sdhc_adapter), 1); #endif - do_fixup_by_compat(blob, compat, "status", "okay", - 4 + 1, 1); } #endif -- cgit v0.10.2 From 208e1ae8d1668278fe46f13d8d7c0e40f7cdc6ec Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 17 Jan 2017 10:43:55 +0800 Subject: armv8: ls1012a: define esdhc_status_fixup for QDS board The LS1012AQDS board has a hardware issue. When there is no eMMC adapter card inserted in SDHC2 adapter slot, the command inhibit bits of eSDHC2_PRSSTAT register will never release. This would cause below continious error messages in linux since it uses polling mode to detect card. "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." This patch is to define esdhc_status_fixup function for QDS to disable SDHC2 status if no eMMC adapter card is detected. Signed-off-by: Yangbo Lu Reviewed-by: York Sun diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 94440b3..88fb4ce 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -121,6 +121,34 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } +int esdhc_status_fixup(void *blob, const char *compat) +{ + char esdhc0_path[] = "/soc/esdhc@1560000"; + char esdhc1_path[] = "/soc/esdhc@1580000"; + u8 card_id; + + do_fixup_by_path(blob, esdhc0_path, "status", "okay", + sizeof("okay"), 1); + + /* + * The Presence Detect 2 register detects the installation + * of cards in various PCI Express or SGMII slots. + * + * STAT_PRS2[7:5]: Specifies the type of card installed in the + * SDHC2 Adapter slot. 0b111 indicates no adapter is installed. + */ + card_id = (QIXIS_READ(present2) & 0xe0) >> 5; + + /* If no adapter is installed in SDHC2, disable SDHC2 */ + if (card_id == 0x7) + do_fixup_by_path(blob, esdhc1_path, "status", "disabled", + sizeof("disabled"), 1); + else + do_fixup_by_path(blob, esdhc1_path, "status", "okay", + sizeof("okay"), 1); + return 0; +} + #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { -- cgit v0.10.2 From 5e4a6db8f428cb1f8ced74bc77241144ac0c5b1a Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Tue, 17 Jan 2017 10:43:56 +0800 Subject: armv8: ls1012a: define esdhc_status_fixup for RDB board On LS1012ARDB board, three dual 1:4 mux/demux devices drive the SDHC2 signals to eMMC, SDIO wifi, SPI and Ardiuno shield. Only when we select eMMC and SDIO wifi, the SDHC2 could be used. Otherwise, the command inhibit bits of eSDHC2_PRSSTAT register will never release. This would cause below continious error messages in linux since it uses polling mode to detect card. "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." "mmc1: Controller never released inhibit bit(s)." This patch is to define esdhc_status_fixup function for RDB to disable SDHC2 status if no SDIO wifi or eMMC is selected. Signed-off-by: Yangbo Lu Reviewed-by: York Sun diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 778434d..65fa94c 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -113,6 +113,44 @@ int board_init(void) return 0; } +int esdhc_status_fixup(void *blob, const char *compat) +{ + char esdhc0_path[] = "/soc/esdhc@1560000"; + char esdhc1_path[] = "/soc/esdhc@1580000"; + u8 io = 0; + u8 mux_sdhc2; + + do_fixup_by_path(blob, esdhc0_path, "status", "okay", + sizeof("okay"), 1); + + i2c_set_bus_num(0); + + /* + * The I2C IO-expander for mux select is used to control the muxing + * of various onboard interfaces. + * + * IO1[3:2] indicates SDHC2 interface demultiplexer select lines. + * 00 - SDIO wifi + * 01 - GPIO (to Arduino) + * 10 - eMMC Memory + * 11 - SPI + */ + if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + + mux_sdhc2 = (io & 0x0c) >> 2; + /* Enable SDHC2 only when use SDIO wifi and eMMC */ + if (mux_sdhc2 == 2 || mux_sdhc2 == 0) + do_fixup_by_path(blob, esdhc1_path, "status", "okay", + sizeof("okay"), 1); + else + do_fixup_by_path(blob, esdhc1_path, "status", "disabled", + sizeof("disabled"), 1); + return 0; +} + int ft_board_setup(void *blob, bd_t *bd) { arch_fixup_fdt(blob); -- cgit v0.10.2