From bd99e6d0e4769922252a7a0e44f319ab9354739d Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Thu, 11 Sep 2014 14:02:03 +0900 Subject: Revert "odroid: set MPLL clock to 880MHz" This reverts commit b09200639d4c052e2bdf0df6fe843b7a8bcf01cc. diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index fd5d2d2..ac19527 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -195,8 +195,8 @@ static void board_clock_init(void) while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) continue; - /* Set MPLL to 880MHz */ - set = SDIV(0) | PDIV(3) | MDIV(110) | FSEL(0) | PLL_ENABLE(1); + /* Set MPLL to 800MHz */ + set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); @@ -220,15 +220,15 @@ static void board_clock_init(void) DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7); /* * For: - * MOUTdmc = 880 MHz - * MOUTdphy = 880 MHz + * MOUTdmc = 800 MHz + * MOUTdphy = 800 MHz * - * aclk_acp = MOUTdmc / (ratio + 1) = 220 (3) - * pclk_acp = aclk_acp / (ratio + 1) = 110 (1) - * sclk_dphy = MOUTdphy / (ratio + 1) = 440 (1) - * sclk_dmc = MOUTdmc / (ratio + 1) = 440 (1) - * aclk_dmcd = sclk_dmc / (ratio + 1) = 220 (1) - * aclk_dmcp = aclk_dmcd / (ratio + 1) = 110 (1) + * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) + * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) + * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) + * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) + * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) + * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) */ set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); @@ -244,13 +244,13 @@ static void board_clock_init(void) C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127); /* * For: - * MOUTg2d = 880 MHz - * MOUTc2c = 880 Mhz + * MOUTg2d = 800 MHz + * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 440 (1) - * sclk_c2c = MOUTc2c / (ratio + 1) = 440 (1) - * aclk_c2c = sclk_c2c / (ratio + 1) = 220 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) + * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | @@ -282,9 +282,9 @@ static void board_clock_init(void) clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | UART3_RATIO(15) | UART4_RATIO(15); /* - * For MOUTuart0-4: 880MHz + * For MOUTuart0-4: 800MHz * - * SCLK_UARTx = MOUTuartX / (ratio + 1) = 110 (7) + * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) */ set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | UART3_RATIO(7) | UART4_RATIO(7); @@ -298,12 +298,12 @@ static void board_clock_init(void) clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | MMC1_PRE_RATIO(255); /* - * For MOUTmmc0-3 = 880 MHz (MPLL) + * For MOUTmmc0-3 = 800 MHz (MPLL) * - * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 110 (7) - * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 60 (1) - * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 110 (7) - * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 60 (1) + * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) + * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) + * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) + * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) */ set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | MMC1_PRE_RATIO(1); @@ -318,12 +318,12 @@ static void board_clock_init(void) clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | MMC3_PRE_RATIO(255); /* - * For MOUTmmc0-3 = 880 MHz (MPLL) + * For MOUTmmc0-3 = 800 MHz (MPLL) * - * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 110 (7) - * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 60 (1) - * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 110 (7) - * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 60 (1) + * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) + * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) + * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) + * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) */ set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | MMC3_PRE_RATIO(1); @@ -337,10 +337,10 @@ static void board_clock_init(void) /* CLK_DIV_FSYS3 */ clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); /* - * For MOUTmmc4 = 880 MHz (MPLL) + * For MOUTmmc4 = 800 MHz (MPLL) * - * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 110 (7) - * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 110 (0) + * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) + * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) */ set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0); -- cgit v0.10.2 From e4d761000a50447a2afca2447088dbf282edda64 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:38 -0600 Subject: Exynos: Use 900MHz ARM frequency in SPL for peach_pit The device seems to hang in SPL if the full speed is used when booting from USB, perhaps because the PMIC has not been set to the maximum ARM core voltage yet. Slow it down to a reliable speed. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 3ed70a8..207782e 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -32,7 +32,7 @@ mem-manuf = "samsung"; mem-type = "ddr3"; clock-frequency = <800000000>; - arm-frequency = <1700000000>; + arm-frequency = <900000000>; }; tmu@10060000 { -- cgit v0.10.2 From 83d937803ad344234da8abdf616d4c1563a12e04 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:39 -0600 Subject: exynos5: Enable data cache Things run faster when the data cache is enabled, so turn it on along with the 'dcache' command. Signed-off-by: Simon Glass Tested-by: Ajay Kumar Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index 1dc3002..68f3a41 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -33,8 +33,8 @@ #define CONFIG_TRACE_EARLY_ADDR 0x50000000 /* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_CMD_CACHE /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA -- cgit v0.10.2 From 2c94611d5f6dc5b49c02806dfdaacf6b27a5da83 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:40 -0600 Subject: cros_ec: power: Add a tunnelled version of the tps65090 driver Unfortunately on Pit the AP has no direct access to the tps65090 but must talk through the EC (over SPI) to the EC's I2C bus. When driver model supports PMICs this will be relatively easy. In the meantime the best approach is to duplicate the driver. It will be refactored once driver model support is expanded. Signed-off-by: Simon Glass Tested-by: Ajay Kumar Signed-off-by: Minkyu Kang diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index a472f61..0b76611 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65090_ec.c b/drivers/power/pmic/pmic_tps65090_ec.c new file mode 100644 index 0000000..ac0d44f --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090_ec.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2013 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TPS65090_ADDR 0x48 + +static struct tps65090 { + struct cros_ec_dev *dev; /* The CROS_EC device */ +} config; + +/* TPS65090 register addresses */ +enum { + REG_IRQ1 = 0, + REG_CG_CTRL0 = 4, + REG_CG_STATUS1 = 0xa, + REG_FET1_CTRL = 0x0f, + REG_FET2_CTRL, + REG_FET3_CTRL, + REG_FET4_CTRL, + REG_FET5_CTRL, + REG_FET6_CTRL, + REG_FET7_CTRL, + TPS65090_NUM_REGS, +}; + +enum { + IRQ1_VBATG = 1 << 3, + CG_CTRL0_ENC_MASK = 0x01, + + MAX_FET_NUM = 7, + MAX_CTRL_READ_TRIES = 5, + + /* TPS65090 FET_CTRL register values */ + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ + FET_CTRL_ENFET = 1 << 0, /* Enable FET */ +}; + +/** + * tps65090_read - read a byte from tps6090 + * + * @param reg The register address to read from. + * @param val We'll return value value read here. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_read(u32 reg, u8 *val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + val, 1, true); +} + +/** + * tps65090_write - write a byte to tps6090 + * + * @param reg The register address to write to. + * @param val The value to write. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_write(u32 reg, u8 val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + &val, 1, false); +} + +/** + * Checks for a valid FET number + * + * @param fet_id FET number to check + * @return 0 if ok, -EINVAL if FET value is out of range + */ +static int tps65090_check_fet(unsigned int fet_id) +{ + if (fet_id == 0 || fet_id > MAX_FET_NUM) { + debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", + fet_id, MAX_FET_NUM); + return -EINVAL; + } + + return 0; +} + +/** + * Set the power state for a FET + * + * @param fet_id Fet number to set (1..MAX_FET_NUM) + * @param set 1 to power on FET, 0 to power off + * @return -EIO if we got a comms error, -EAGAIN if the FET failed to + * change state. If all is ok, returns 0. + */ +static int tps65090_fet_set(int fet_id, bool set) +{ + int retry; + u8 reg, value; + + value = FET_CTRL_ADENFET | FET_CTRL_WAIT; + if (set) + value |= FET_CTRL_ENFET; + + if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value)) + return -EIO; + + /* Try reading until we get a result */ + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { + if (tps65090_read(REG_FET1_CTRL + fet_id - 1, ®)) + return -EIO; + + /* Check that the fet went into the expected state */ + if (!!(reg & FET_CTRL_PGFET) == set) + return 0; + + /* If we got a timeout, there is no point in waiting longer */ + if (reg & FET_CTRL_TOFET) + break; + + mdelay(1); + } + + debug("FET %d: Power good should have set to %d but reg=%#02x\n", + fet_id, set, reg); + return -EAGAIN; +} + +int tps65090_fet_enable(unsigned int fet_id) +{ + ulong start; + int loops; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + start = get_timer(0); + for (loops = 0;; loops++) { + ret = tps65090_fet_set(fet_id, true); + if (!ret) + break; + + if (get_timer(start) > 100) + break; + + /* Turn it off and try again until we time out */ + tps65090_fet_set(fet_id, false); + } + + if (ret) { + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } else if (loops) { + debug("%s: FET%d powered on after %lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } + /* + * Unfortunately, there are some conditions where the power + * good bit will be 0, but the fet still comes up. One such + * case occurs with the lcd backlight. We'll just return 0 here + * and assume that the fet will eventually come up. + */ + if (ret == -EAGAIN) + ret = 0; + + return ret; +} + +int tps65090_fet_disable(unsigned int fet_id) +{ + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + ret = tps65090_fet_set(fet_id, false); + + return ret; +} + +int tps65090_fet_is_enabled(unsigned int fet_id) +{ + u8 reg = 0; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, ®); + if (ret) { + debug("fail to read FET%u_CTRL register over I2C", fet_id); + return -EIO; + } + + return reg & FET_CTRL_ENFET; +} + +int tps65090_init(void) +{ + puts("TPS65090 PMIC EC init\n"); + + config.dev = board_get_cros_ec_dev(); + if (!config.dev) { + debug("%s: no cros_ec device: cannot init tps65090\n", + __func__); + return -ENODEV; + } + + return 0; +} -- cgit v0.10.2 From 5b9c8cb6cbb822594b9e5171a7ee2839f497352e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:41 -0600 Subject: cros_ec: exynos: Use the correct tps65090 driver in each case Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards cannot due to a hardware design decision. Select the correct driver to use in each case. Signed-off-by: Simon Glass Tested-by: Ajay Kumar Signed-off-by: Minkyu Kang diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 0b76611..e7b07eb 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o -obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index c24984b..5504515 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -42,6 +42,7 @@ /* PMIC */ #define CONFIG_POWER_MAX77686 +#define CONFIG_POWER_TPS65090_I2C /* Sound */ #define CONFIG_CMD_SOUND diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 987cef5..34734ad 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -30,4 +30,6 @@ #define LCD_BPP LCD_COLOR16 #endif +#define CONFIG_POWER_TPS65090_EC + #endif /* __CONFIG_PEACH_PIT_H */ -- cgit v0.10.2 From 98149d72f36f5543854568cb2d48277b0e7a88ba Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:42 -0600 Subject: dm: exynos: Split out the cros_ec drivers With the driver model conversion we are going to be using driver model for SPI and not for I2C. This works OK so long as a board doesn't need both dm and non-dm versions of the cros_ec driver. Since pit uses SPI and snow uses I2C we need to split the configs so that only one driver is compiled for each platform. We can fix this later when driver model supports I2C. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index 68f3a41..0c400b1 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -69,8 +69,6 @@ /* Enable keyboard */ #define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ #define CONFIG_CMD_CROS_EC #define CONFIG_KEYBOARD diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 5504515..05d33a7 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -22,6 +22,8 @@ #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ + /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_XHCI diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 34734ad..8db889c 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -31,5 +31,6 @@ #endif #define CONFIG_POWER_TPS65090_EC +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ #endif /* __CONFIG_PEACH_PIT_H */ -- cgit v0.10.2 From f0d80fbcd70e3ab56dc460bc5f5325176161f5a8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:43 -0600 Subject: exynos: dts: Add device tree node for cros_ec keyboard Add a keyboard definition so that the keyboard can be used on pit. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 207782e..995e62b 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -28,6 +28,61 @@ pmic = "/i2c@12ca0000"; }; + cros-ec-keyb { + compatible = "google,cros-ec-keyb"; + google,key-rows = <8>; + google,key-columns = <13>; + google,repeat-delay-ms = <240>; + google,repeat-rate-ms = <30>; + google,ghost-filter; + /* + * Keymap entries take the form of 0xRRCCKKKK where + * RR=Row CC=Column KKKK=Key Code + * The values below are for a US keyboard layout and + * are taken from the Linux driver. Note that the + * 102ND key is not used for US keyboards. + */ + linux,keymap = < + /* CAPSLCK F1 B F10 */ + 0x0001003a 0x0002003b 0x00030030 0x00040044 + /* N = R_ALT ESC */ + 0x00060031 0x0008000d 0x000a0064 0x01010001 + /* F4 G F7 H */ + 0x0102003e 0x01030022 0x01040041 0x01060023 + /* ' F9 BKSPACE L_CTRL */ + 0x01080028 0x01090043 0x010b000e 0x0200001d + /* TAB F3 T F6 */ + 0x0201000f 0x0202003d 0x02030014 0x02040040 + /* ] Y 102ND [ */ + 0x0205001b 0x02060015 0x02070056 0x0208001a + /* F8 GRAVE F2 5 */ + 0x02090042 0x03010029 0x0302003c 0x03030006 + /* F5 6 - \ */ + 0x0304003f 0x03060007 0x0308000c 0x030b002b + /* R_CTRL A D F */ + 0x04000061 0x0401001e 0x04020020 0x04030021 + /* S K J ; */ + 0x0404001f 0x04050025 0x04060024 0x04080027 + /* L ENTER Z C */ + 0x04090026 0x040b001c 0x0501002c 0x0502002e + /* V X , M */ + 0x0503002f 0x0504002d 0x05050033 0x05060032 + /* L_SHIFT / . SPACE */ + 0x0507002a 0x05080035 0x05090034 0x050B0039 + /* 1 3 4 2 */ + 0x06010002 0x06020004 0x06030005 0x06040003 + /* 8 7 0 9 */ + 0x06050009 0x06060008 0x0608000b 0x0609000a + /* L_ALT DOWN RIGHT Q */ + 0x060a0038 0x060b006c 0x060c006a 0x07010010 + /* E R W I */ + 0x07020012 0x07030013 0x07040011 0x07050017 + /* U R_SHIFT P O */ + 0x07060016 0x07070036 0x07080019 0x07090018 + /* UP LEFT */ + 0x070b0067 0x070c0069>; + }; + dmc { mem-manuf = "samsung"; mem-type = "ddr3"; -- cgit v0.10.2 From 4c7bb1d2e0526d26972969d4c01fd6c760d4d865 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:44 -0600 Subject: exynos: Rename -dt config files to -common We want exynos5250-dt.h to be a board which can support any exynos5250 device. This matches the naming used by Linux. As a first step, rename the existing -dt files to -common to make it clear they are common files, and not specific boards. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h new file mode 100644 index 0000000..38b8961 --- /dev/null +++ b/include/configs/exynos4-common.h @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS4_COMMON_H +#define __CONFIG_EXYNOS4_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */ + +#include /* get chip and board defs */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +#include + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_S5P_SDHCI +#define CONFIG_SDHCI +#define CONFIG_MMC_SDMA +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_MMC_DEFAULT_DEV 0 + +/* PWM */ +#define CONFIG_PWM + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_CACHE +#undef CONFIG_CMD_ONENAND +#undef CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MMC +#define CONFIG_CMD_DFU +#define CONFIG_CMD_GPT +#define CONFIG_CMD_PMIC +#define CONFIG_CMD_SETEXPR + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* FAT */ +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE + +/* EXT4 */ +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET + +/* TIZEN THOR downloader support */ +#define CONFIG_CMD_THOR_DOWNLOAD +#define CONFIG_THOR_FUNCTION + +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB Samsung's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 +#define CONFIG_G_DNL_MANUFACTURER "Samsung" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT + +#endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h deleted file mode 100644 index 99472ac..0000000 --- a/include/configs/exynos4-dt.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2014 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */ - -#include /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON -#define CONFIG_SYS_GENERIC_BOARD - -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -#include - -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_S5P_SDHCI -#define CONFIG_SDHCI -#define CONFIG_MMC_SDMA -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_MMC_DEFAULT_DEV 0 - -/* PWM */ -#define CONFIG_PWM - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG -#undef CONFIG_CMD_CACHE -#undef CONFIG_CMD_ONENAND -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC -#define CONFIG_CMD_DFU -#define CONFIG_CMD_GPT -#define CONFIG_CMD_PMIC -#define CONFIG_CMD_SETEXPR - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* FAT */ -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* EXT4 */ -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USBDOWNLOAD_GADGET - -/* TIZEN THOR downloader support */ -#define CONFIG_CMD_THOR_DOWNLOAD -#define CONFIG_THOR_FUNCTION - -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 -#define CONFIG_G_DNL_MANUFACTURER "Samsung" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_GADGET_MASS_STORAGE - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - -#endif /* __CONFIG_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h new file mode 100644 index 0000000..fede0e8 --- /dev/null +++ b/include/configs/exynos5-common.h @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5_COMMON_H +#define __CONFIG_EXYNOS5_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ + +#include /* get chip and board defs */ + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_EXYNOS_SPL + +/* Allow tracing to be enabled */ +#define CONFIG_TRACE +#define CONFIG_CMD_TRACE +#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) +#define CONFIG_TRACE_EARLY_SIZE (8 << 20) +#define CONFIG_TRACE_EARLY +#define CONFIG_TRACE_EARLY_ADDR 0x50000000 + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_CMD_CACHE + +/* Enable ACE acceleration for SHA1 and SHA256 */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_SHA_HW_ACCEL + +/* input clock of PLL: SMDK5250 has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* Offset for inform registers */ +#define INFORM0_OFFSET 0x800 +#define INFORM1_OFFSET 0x804 +#define INFORM2_OFFSET 0x808 +#define INFORM3_OFFSET 0x80c + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 +#define CONFIG_SILENT_CONSOLE + +/* Enable keyboard */ +#define CONFIG_CROS_EC /* CROS_EC protocol */ +#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ +#define CONFIG_CMD_CROS_EC +#define CONFIG_KEYBOARD + +/* Console configuration */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_S5P_SDHCI +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* PWM */ +#define CONFIG_PWM + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NET +#define CONFIG_CMD_HASH + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* Thermal Management Unit */ +#define CONFIG_EXYNOS_TMU +#define CONFIG_CMD_DTT +#define CONFIG_TMU_CMD_DTT + +/* TPM */ +#define CONFIG_TPM +#define CONFIG_CMD_TPM +#define CONFIG_TPM_TIS_I2C +#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 +#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 + +/* MMC SPL */ +#define COPY_BL2_FNPTR_ADDR 0x02020030 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* specific .lds file */ +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_RD_LVL + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_SECURE_BL1_ONLY + +/* Secure FW size configuration */ +#ifdef CONFIG_SECURE_BL1_ONLY +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ +#else +#define CONFIG_SEC_FW_SIZE 0 +#endif + +/* Configuration of BL1, BL2, ENV Blocks on mmc */ +#define CONFIG_RES_BLOCK_SIZE (512) +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ + +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) + +/* Store environment at the end of a 4 MB SPI flash */ +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) + +/* U-boot copy size from boot Media to DRAM.*/ +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) + +#define CONFIG_SPI_BOOTING +#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 +#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +/* I2C */ +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 +#define CONFIG_I2C_EDID + +/* SPI */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 + +#ifdef CONFIG_SPI_FLASH +#define CONFIG_EXYNOS_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define EXYNOS5_SPI_NUM_CONTROLLERS 5 +#define CONFIG_OF_SPI +#endif + +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65090 + +/* Ethernet Controllor Driver */ +#ifdef CONFIG_CMD_NET +#define CONFIG_SMC911X +#define CONFIG_SMC911X_BASE 0x5000000 +#define CONFIG_SMC911X_16_BIT +#define CONFIG_ENV_SROM_BANK 1 +#endif /*CONFIG_CMD_NET*/ + +/* Enable PXE Support */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_PXE +#define CONFIG_MENU +#endif + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT + +/* SHA hashing */ +#define CONFIG_CMD_HASH +#define CONFIG_HASH_VERIFY +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +/* Enable Time Command */ +#define CONFIG_CMD_TIME + +#define CONFIG_CMD_BOOTZ + +#define CONFIG_CMD_GPIO + +/* USB boot mode */ +#define CONFIG_USB_BOOTING +#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 +#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 +#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 + +#endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h deleted file mode 100644 index 0c400b1..0000000 --- a/include/configs/exynos5-dt.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ - -#include /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON -#define CONFIG_ARCH_EARLY_INIT_R -#define CONFIG_EXYNOS_SPL - -/* Allow tracing to be enabled */ -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x50000000 - -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMD_CACHE - -/* Enable ACE acceleration for SHA1 and SHA256 */ -#define CONFIG_EXYNOS_ACE_SHA -#define CONFIG_SHA_HW_ACCEL - -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* Offset for inform registers */ -#define INFORM0_OFFSET 0x800 -#define INFORM1_OFFSET 0x804 -#define INFORM2_OFFSET 0x808 -#define INFORM3_OFFSET 0x80c - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - -/* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -#define CONFIG_SILENT_CONSOLE - -/* Enable keyboard */ -#define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ -#define CONFIG_CMD_CROS_EC -#define CONFIG_KEYBOARD - -/* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS - -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOUNCE_BUFFER - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NET -#define CONFIG_CMD_HASH - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* Thermal Management Unit */ -#define CONFIG_EXYNOS_TMU -#define CONFIG_CMD_DTT -#define CONFIG_TMU_CMD_DTT - -/* TPM */ -#define CONFIG_TPM -#define CONFIG_CMD_TPM -#define CONFIG_TPM_TIS_I2C -#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 -#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 - -/* MMC SPL */ -#define COPY_BL2_FNPTR_ADDR 0x02020030 - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - -/* specific .lds file */ -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_RD_LVL - -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_SECURE_BL1_ONLY - -/* Secure FW size configuration */ -#ifdef CONFIG_SECURE_BL1_ONLY -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ -#else -#define CONFIG_SEC_FW_SIZE 0 -#endif - -/* Configuration of BL1, BL2, ENV Blocks on mmc */ -#define CONFIG_RES_BLOCK_SIZE (512) -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ - -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) - -/* Store environment at the end of a 4 MB SPI flash */ -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) - -/* U-boot copy size from boot Media to DRAM.*/ -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) - -#define CONFIG_SPI_BOOTING -#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 -#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - -/* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 -#define CONFIG_I2C_EDID - -/* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 - -#ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 50000000 -#define EXYNOS5_SPI_NUM_CONTROLLERS 5 -#define CONFIG_OF_SPI -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_TPS65090 - -/* Ethernet Controllor Driver */ -#ifdef CONFIG_CMD_NET -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x5000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_ENV_SROM_BANK 1 -#endif /*CONFIG_CMD_NET*/ - -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - -/* SHA hashing */ -#define CONFIG_CMD_HASH -#define CONFIG_HASH_VERIFY -#define CONFIG_SHA1 -#define CONFIG_SHA256 - -/* Enable Time Command */ -#define CONFIG_CMD_TIME - -#define CONFIG_CMD_BOOTZ - -#define CONFIG_CMD_GPIO - -/* USB boot mode */ -#define CONFIG_USB_BOOTING -#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 -#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 -#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 - -#endif /* __CONFIG_H */ diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h new file mode 100644 index 0000000..b4c1ccf --- /dev/null +++ b/include/configs/exynos5250-common.h @@ -0,0 +1,74 @@ + +/* + * Copyright (C) 2012 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5250 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_5250_H +#define __CONFIG_5250_H + +#include +#define CONFIG_EXYNOS5250 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ +#define MACH_TYPE_SMDK5250 3774 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 + +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) + +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE + +#define CONFIG_SPL_TEXT_BASE 0x02023400 + +#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" + +#define CONFIG_SYS_PROMPT "SMDK5250 # " +#define CONFIG_IDENT_STRING " for SMDK5250" + +#define CONFIG_IRAM_STACK 0x02050000 + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK + +/* PMIC */ +#define CONFIG_POWER_MAX77686 +#define CONFIG_POWER_TPS65090_I2C + +/* Sound */ +#define CONFIG_CMD_SOUND +#ifdef CONFIG_CMD_SOUND +#define CONFIG_SOUND +#define CONFIG_I2S_SAMSUNG +#define CONFIG_I2S +#define CONFIG_SOUND_MAX98095 +#define CONFIG_SOUND_WM8994 +#endif + +/* I2C */ +#define CONFIG_MAX_I2C_NUM 8 + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 8 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#endif /* __CONFIG_5250_H */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h deleted file mode 100644 index 05d33a7..0000000 --- a/include/configs/exynos5250-dt.h +++ /dev/null @@ -1,74 +0,0 @@ - -/* - * Copyright (C) 2012 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5250 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_5250_H -#define __CONFIG_5250_H - -#include -#define CONFIG_EXYNOS5250 - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x43E00000 - -/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ -#define MACH_TYPE_SMDK5250 3774 -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 - -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ - -/* USB */ -#define CONFIG_CMD_USB -#define CONFIG_USB_XHCI -#define CONFIG_USB_XHCI_EXYNOS -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE - -#define CONFIG_SPL_TEXT_BASE 0x02023400 - -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" - -#define CONFIG_SYS_PROMPT "SMDK5250 # " -#define CONFIG_IDENT_STRING " for SMDK5250" - -#define CONFIG_IRAM_STACK 0x02050000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK - -/* PMIC */ -#define CONFIG_POWER_MAX77686 -#define CONFIG_POWER_TPS65090_I2C - -/* Sound */ -#define CONFIG_CMD_SOUND -#ifdef CONFIG_CMD_SOUND -#define CONFIG_SOUND -#define CONFIG_I2S_SAMSUNG -#define CONFIG_I2S -#define CONFIG_SOUND_MAX98095 -#define CONFIG_SOUND_WM8994 -#endif - -/* I2C */ -#define CONFIG_MAX_I2C_NUM 8 - -/* Display */ -#define CONFIG_LCD -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif - -/* DRAM Memory Banks */ -#define CONFIG_NR_DRAM_BANKS 8 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ - -#endif /* __CONFIG_5250_H */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index b616ac2..07a2ff6 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -12,7 +12,7 @@ #ifndef __CONFIG_ODROID_U3_H #define __CONFIG_ODROID_U3_H -#include +#include #define CONFIG_SYS_PROMPT "Odroid # " /* Monitor Command Prompt */ diff --git a/include/configs/origen.h b/include/configs/origen.h index fb1536c..fc8a202 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_ORIGEN_H #define __CONFIG_ORIGEN_H -#include +#include #define CONFIG_SYS_PROMPT "ORIGEN # " diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 8db889c..5e428cc 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H -#include +#include #include diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 082d51c..e26522d 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_UNIVERSAL_H #define __CONFIG_UNIVERSAL_H -#include +#include #define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 6117094..56d41e6 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_SMDK_H #define __CONFIG_SMDK_H -#include +#include /* Enable FIT support and comparison */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 36a156f..abda141 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_SMDK5420_H #define __CONFIG_SMDK5420_H -#include +#include #include diff --git a/include/configs/snow.h b/include/configs/snow.h index fbaaa59..2942fdf 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_SNOW_H #define __CONFIG_SNOW_H -#include +#include /* Enable FIT support and comparison */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 43751e7..c7edd07 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_TRATS_H #define __CONFIG_TRATS_H -#include +#include #define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index e9a04f7..de72651 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -11,7 +11,7 @@ #ifndef __CONFIG_TRATS2_H #define __CONFIG_TRATS2_H -#include +#include #define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ -- cgit v0.10.2 From 5ea01ab10dcdab41d1bfb1972b4b2298d5a26fcf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:45 -0600 Subject: exynos: Move common exynos settings into a common file Since exynos4 and exyno5 share many settings, we should move these into a common file to avoid duplication. In effect the changes are that all exynos boards now have EXT4 and FAT write support. This affects exynos5250 and exynos5420 which previously did not. This also disables the ext2 commands which are equivalent to ext4 anyway. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h new file mode 100644 index 0000000..7b9eda4 --- /dev/null +++ b/include/configs/exynos-common.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Common configuration settings for the SAMSUNG EXYNOS boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EXYNOS_COMMON_H +#define __EXYNOS_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ + +#include /* get chip and board defs */ +#include + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* Enable fdt support */ +#define CONFIG_OF_LIBFDT + +/* Keep L2 Cache Disabled */ +#define CONFIG_CMD_CACHE + +/* input clock of PLL: 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_ENV_OVERWRITE + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_S5P_SDHCI +#define CONFIG_SDHCI +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* PWM */ +#define CONFIG_PWM + +/* Command definition*/ +#include + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 38b8961..972add4 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -9,81 +9,29 @@ #ifndef __CONFIG_EXYNOS4_COMMON_H #define __CONFIG_EXYNOS4_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */ +#define CONFIG_EXYNOS4 /* Exynos4 Family */ -#include /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON -#define CONFIG_SYS_GENERIC_BOARD +#include "exynos-common.h" #define CONFIG_SYS_CACHELINE_SIZE 32 - -/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG #define CONFIG_REVISION_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -#include /* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_S5P_SDHCI -#define CONFIG_SDHCI #define CONFIG_MMC_SDMA -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_BOUNCE_BUFFER #define CONFIG_MMC_DEFAULT_DEV 0 -/* PWM */ -#define CONFIG_PWM - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_MISC #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS #undef CONFIG_CMD_XIMG -#undef CONFIG_CMD_CACHE #undef CONFIG_CMD_ONENAND #undef CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC #define CONFIG_CMD_DFU #define CONFIG_CMD_GPT #define CONFIG_CMD_PMIC #define CONFIG_CMD_SETEXPR -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* FAT */ -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* EXT4 */ -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE - /* USB Composite download gadget - g_dnl */ #define CONFIG_USBDOWNLOAD_GADGET @@ -105,26 +53,8 @@ #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 #define CONFIG_G_DNL_MANUFACTURER "Samsung" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG #define CONFIG_USB_GADGET_DUALSPEED @@ -133,7 +63,4 @@ #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - #endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index fede0e8..380a46f 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -9,18 +9,11 @@ #ifndef __CONFIG_EXYNOS5_COMMON_H #define __CONFIG_EXYNOS5_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ - -#include /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON +#define CONFIG_EXYNOS5 /* Exynos5 Family */ + +#include "exynos-common.h" + +#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_EXYNOS_SPL @@ -32,22 +25,11 @@ #define CONFIG_TRACE_EARLY #define CONFIG_TRACE_EARLY_ADDR 0x50000000 -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMD_CACHE /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA #define CONFIG_SHA_HW_ACCEL -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 @@ -59,13 +41,12 @@ #define INFORM2_OFFSET 0x808 #define INFORM3_OFFSET 0x80c -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - /* select serial console configuration */ #define CONFIG_BAUDRATE 115200 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 #define CONFIG_SILENT_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CONSOLE_MUX /* Enable keyboard */ #define CONFIG_CROS_EC /* CROS_EC protocol */ @@ -74,8 +55,6 @@ #define CONFIG_KEYBOARD /* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define EXYNOS_DEVICE_SETTINGS \ "stdin=serial,cros-ec-keyb\0" \ "stdout=serial,lcd\0" \ @@ -84,39 +63,11 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOUNCE_BUFFER - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - #define CONFIG_CMD_PING #define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_CMD_NET #define CONFIG_CMD_HASH -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - /* Thermal Management Unit */ #define CONFIG_EXYNOS_TMU #define CONFIG_CMD_DTT @@ -131,6 +82,7 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 +#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT @@ -139,14 +91,8 @@ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) @@ -173,10 +119,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SECURE_BL1_ONLY @@ -209,11 +151,6 @@ #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - /* I2C */ #define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_SYS_I2C @@ -267,9 +204,6 @@ #define CONFIG_MENU #endif -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - /* SHA hashing */ #define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY @@ -289,4 +223,8 @@ #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + #endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/origen.h b/include/configs/origen.h index fc8a202..da9d6a1 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -35,9 +35,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index e26522d..27f3d0a 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -27,9 +27,6 @@ #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 56d41e6..7673bae 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -12,8 +12,4 @@ #include -/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH - #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h index 2942fdf..0834cc9 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -12,8 +12,4 @@ #include -/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH - #endif /* __CONFIG_SNOW_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index c7edd07..b21ea2d 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -39,10 +39,6 @@ #define CONFIG_SYS_TEXT_BASE 0x63300000 -#include -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/trats2.h b/include/configs/trats2.h index de72651..42481ab 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -36,10 +36,6 @@ #define CONFIG_SYS_TEXT_BASE 0x43e00000 -#include -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 -- cgit v0.10.2 From 87033d4d97e0cc569c59efef7ce4ce940c48e71b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:46 -0600 Subject: exynos: Move common smdk5420 things to common file A few things are common but are not in the common file. Fix this and rename the file to fit with the other exynos*-common files. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h new file mode 100644 index 0000000..27e7edc --- /dev/null +++ b/include/configs/exynos5420-common.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5420 SoC + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5420_H +#define __CONFIG_EXYNOS5420_H + +#define CONFIG_EXYNOS5420 + +#include + +#define MACH_TYPE_SMDK5420 8002 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 + +#define CONFIG_VAR_SIZE_SPL + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 +#ifdef CONFIG_VAR_SIZE_SPL +#define CONFIG_SPL_TEXT_BASE 0x02024410 +#else +#define CONFIG_SPL_TEXT_BASE 0x02024400 +#endif +#define CONFIG_IRAM_TOP 0x02074000 + +#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) + +#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" + +#define CONFIG_MAX_I2C_NUM 11 + +#define CONFIG_BOARD_REV_GPIO_COUNT 2 + +#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" + +/* + * Put the initial stack pointer 1KB below this to allow room for the + * SPL marker. This value is arbitrary, but gd_t is placed starting here. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + +#endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h deleted file mode 100644 index d2a9556..0000000 --- a/include/configs/exynos5420.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5420 SoC - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_EXYNOS5420_H -#define __CONFIG_EXYNOS5420_H - -#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */ - -#define MACH_TYPE_SMDK5420 8002 -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 - -#define CONFIG_VAR_SIZE_SPL - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_TEXT_BASE 0x23E00000 -#ifdef CONFIG_VAR_SIZE_SPL -#define CONFIG_SPL_TEXT_BASE 0x02024410 -#else -#define CONFIG_SPL_TEXT_BASE 0x02024400 -#endif -#define CONFIG_IRAM_TOP 0x02074000 - -#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) - -#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" - -#define CONFIG_MAX_I2C_NUM 11 - -/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH - -#define CONFIG_BOARD_REV_GPIO_COUNT 2 - -#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" - -/* - * Put the initial stack pointer 1KB below this to allow room for the - * SPL marker. This value is arbitrary, but gd_t is placed starting here. - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -/* DRAM Memory Banks */ -#define CONFIG_NR_DRAM_BANKS 7 -#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ - -#endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 5e428cc..e9736fc 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,9 +9,7 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H -#include - -#include +#include /* select serial console configuration */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index abda141..894ed11 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -9,9 +9,7 @@ #ifndef __CONFIG_SMDK5420_H #define __CONFIG_SMDK5420_H -#include - -#include +#include #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ -- cgit v0.10.2 From 7d159536192323d65765211e7e7f56efcf3509ac Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:47 -0600 Subject: exynos: config: Move cros_ec and tps65090 out of smdk boards These boards do not in fact have a Chrome OS EC, nor a TPS565090 PMIC, so move the settings into a separate common file to be used by those that need it. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 380a46f..3581a38 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -48,17 +48,10 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_CONSOLE_MUX -/* Enable keyboard */ -#define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ -#define CONFIG_CMD_CROS_EC -#define CONFIG_KEYBOARD - -/* Console configuration */ #define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" #define CONFIG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS @@ -185,11 +178,6 @@ #define CONFIG_ENV_SPI_MAX_HZ 50000000 #endif -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_TPS65090 - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h new file mode 100644 index 0000000..66547fa --- /dev/null +++ b/include/configs/exynos5-dt-common.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * Configuration settings for generic Exynos 5 board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5_DT_COMMON_H +#define __CONFIG_EXYNOS5_DT_COMMON_H + +#include "exynos5-common.h" + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65090 + +/* Enable keyboard */ +#define CONFIG_CROS_EC /* CROS_EC protocol */ +#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ +#define CONFIG_CMD_CROS_EC +#define CONFIG_KEYBOARD + +/* Console configuration */ +#undef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS + +#endif diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index b4c1ccf..987eb15 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -22,8 +22,6 @@ #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ - /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_XHCI @@ -44,7 +42,6 @@ /* PMIC */ #define CONFIG_POWER_MAX77686 -#define CONFIG_POWER_TPS65090_I2C /* Sound */ #define CONFIG_CMD_SOUND diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index e9736fc..046813d 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -10,6 +10,7 @@ #define __CONFIG_PEACH_PIT_H #include +#include /* select serial console configuration */ diff --git a/include/configs/snow.h b/include/configs/snow.h index 0834cc9..dc09c66 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -10,6 +10,10 @@ #define __CONFIG_SNOW_H #include +#include +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ +#define CONFIG_POWER_TPS65090_I2C + #endif /* __CONFIG_SNOW_H */ -- cgit v0.10.2 From f94de733df8a3a6e28a9acbfc00871319f567775 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:48 -0600 Subject: config: Move arndale to use common exynos5250 file Most of the arndale features are common with other exynos5250 boards. To permit easier addition of driver model support, use the common file. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 43077cf..f9ee40f 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -9,109 +9,19 @@ #ifndef __CONFIG_ARNDALE_H #define __CONFIG_ARNDALE_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ -#define CONFIG_EXYNOS5250 - -#include /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - - -/* Allow tracing to be enabled */ -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x50000000 - -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x43E00000 - -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* Offset for inform registers */ -#define INFORM0_OFFSET 0x800 -#define INFORM1_OFFSET 0x804 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - -/* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -#define CONFIG_SILENT_CONSOLE - -/* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS +#include "exynos5250-common.h" /* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC #define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOUNCE_BUFFER - - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -/* Command definition*/ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC #define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NET -#define CONFIG_CMD_HASH - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* USB */ -#define CONFIG_CMD_USB #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS -#define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER @@ -119,106 +29,23 @@ /* MMC SPL */ #define CONFIG_EXYNOS_SPL -#define COPY_BL2_FNPTR_ADDR 0x02020030 - -#define CONFIG_SPL_LIBCOMMON_SUPPORT - -/* specific .lds file */ -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" -#define CONFIG_SPL_TEXT_BASE 0x02023400 -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "ARNDALE # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_RD_LVL #define CONFIG_NR_DRAM_BANKS 8 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for ARNDALE" -#define CONFIG_SYS_MMC_ENV_DEV 0 - #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SECURE_BL1_ONLY - -/* Secure FW size configuration */ -#ifdef CONFIG_SECURE_BL1_ONLY -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ -#else -#define CONFIG_SEC_FW_SIZE 0 -#endif - -/* Configuration of BL1, BL2, ENV Blocks on mmc */ -#define CONFIG_RES_BLOCK_SIZE (512) -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ - -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) -/* U-boot copy size from boot Media to DRAM.*/ -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - - #define CONFIG_IRAM_STACK 0x02050000 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK -/* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_MAX_I2C_NUM 8 -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 -#define CONFIG_I2C_EDID - /* PMIC */ #define CONFIG_PMIC #define CONFIG_POWER_I2C @@ -227,26 +54,6 @@ #define CONFIG_PREBOOT -/* Ethernet Controllor Driver */ -#ifdef CONFIG_CMD_NET -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x5000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_ENV_SROM_BANK 1 -#endif /*CONFIG_CMD_NET*/ - -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - -/* Enable Time Command */ -#define CONFIG_CMD_TIME - #define CONFIG_S5P_PA_SYSRAM 0x02020000 #define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 7b9eda4..54b61d7 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -20,7 +20,6 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 972add4..89ba14e 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -13,6 +13,8 @@ #include "exynos-common.h" +#define CONFIG_BOARD_COMMON + #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_REVISION_TAG diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 3581a38..ba591e7 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -14,7 +14,6 @@ #include "exynos-common.h" #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_EXYNOS_SPL /* Allow tracing to be enabled */ @@ -83,8 +82,6 @@ /* specific .lds file */ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" -/* Miscellaneous configurable options */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" /* Boot Argument Buffer Size */ /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE @@ -132,15 +129,10 @@ #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) -/* Store environment at the end of a 4 MB SPI flash */ -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) - /* U-boot copy size from boot Media to DRAM.*/ #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) -#define CONFIG_SPI_BOOTING #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) @@ -155,10 +147,6 @@ #define CONFIG_I2C_EDID /* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 - #ifdef CONFIG_SPI_FLASH #define CONFIG_EXYNOS_SPI #define CONFIG_CMD_SF diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 987eb15..713614f 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -24,8 +24,6 @@ /* USB */ #define CONFIG_CMD_USB -#define CONFIG_USB_XHCI -#define CONFIG_USB_XHCI_EXYNOS #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE @@ -33,9 +31,6 @@ #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" -#define CONFIG_SYS_PROMPT "SMDK5250 # " -#define CONFIG_IDENT_STRING " for SMDK5250" - #define CONFIG_IRAM_STACK 0x02050000 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 27e7edc..b0f940c 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -11,8 +11,17 @@ #define CONFIG_EXYNOS5420 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + #include +#define CONFIG_ARCH_EARLY_INIT_R + #define MACH_TYPE_SMDK5420 8002 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 @@ -37,6 +46,8 @@ #define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + /* * Put the initial stack pointer 1KB below this to allow room for the * SPL marker. This value is arbitrary, but gd_t is placed starting here. @@ -47,4 +58,7 @@ #define CONFIG_NR_DRAM_BANKS 7 #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ +/* Miscellaneous configurable options */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 046813d..ab8ac60 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,9 +9,16 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) + #include #include +#define CONFIG_BOARD_COMMON /* select serial console configuration */ #define CONFIG_SERIAL3 /* use SERIAL 3 */ @@ -32,4 +39,7 @@ #define CONFIG_POWER_TPS65090_EC #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + #endif /* __CONFIG_PEACH_PIT_H */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 7673bae..8395372 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -9,7 +9,26 @@ #ifndef __CONFIG_SMDK_H #define __CONFIG_SMDK_H +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + #include +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#define CONFIG_SYS_PROMPT "SMDK5250 # " +#define CONFIG_IDENT_STRING " for SMDK5250" + +/* Miscellaneous configurable options */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 894ed11..fd2d482 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -11,6 +11,8 @@ #include +#define CONFIG_BOARD_COMMON + #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ @@ -19,5 +21,6 @@ #define CONFIG_SYS_PROMPT "SMDK5420 # " #define CONFIG_IDENT_STRING " for SMDK5420" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #endif /* __CONFIG_SMDK5420_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h index dc09c66..7eaa586 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -9,6 +9,13 @@ #ifndef __CONFIG_SNOW_H #define __CONFIG_SNOW_H +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + #include #include @@ -16,4 +23,14 @@ #define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_POWER_TPS65090_I2C +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#define CONFIG_SYS_PROMPT "snow # " +#define CONFIG_IDENT_STRING " for snow" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + #endif /* __CONFIG_SNOW_H */ -- cgit v0.10.2 From 1d5511000367e94d5edce7d9c3720bd9097912a7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:49 -0600 Subject: config: Move smdkv310 to use common exynos4 file Most of the smdkv310 features are common with other exynos4 boards. To permit easier addition of driver model support, use the common file and add a device tree file. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index e7c93d8..7a0d182 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -5,6 +5,7 @@ choice config TARGET_SMDKV310 bool "Exynos4210 SMDKV310 board" + select OF_CONTROL if !SPL_BUILD config TARGET_TRATS bool "Exynos4210 Trats board" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5f2b946..43a70e4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ exynos4210-universal_c210.dtb \ exynos4210-trats.dtb \ exynos4412-trats2.dtb \ diff --git a/arch/arm/dts/exynos4210-smdkv310.dts b/arch/arm/dts/exynos4210-smdkv310.dts new file mode 100644 index 0000000..c390c8f --- /dev/null +++ b/arch/arm/dts/exynos4210-smdkv310.dts @@ -0,0 +1,21 @@ +/* + * Samsung's Exynos4210-based SMDKV310 board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Samsung SMDKV310 on Exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210"; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + }; + +}; diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index 44da273..0d1a24f 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -2,3 +2,4 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_ARCH_EXYNOS=y +S:CONFIG_TARGET_SMDKV310=y +CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310" diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 048c178..a2469eb 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -9,71 +9,42 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "exynos4-common.h" + +#undef CONFIG_BOARD_COMMON +#undef CONFIG_USB_GADGET +#undef CONFIG_USB_GADGET_S3C_UDC_OTG +#undef CONFIG_CMD_USB_MASS_STORAGE +#undef CONFIG_REVISION_TAG +#undef CONFIG_CMD_THOR_DOWNLOAD +#undef CONFIG_CMD_DFU + /* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* S5P Family */ -#define CONFIG_EXYNOS4 /* EXYNOS4 Family */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_SMDKV310 1 /* working with SMDKV310*/ -#include /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F - /* Mach Type */ #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_TEXT_BASE 0x43E00000 -/* input clock of PLL: SMDKV310 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - /* Handling Sleep Mode*/ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 #define S5P_CHECK_LPA 0xABAD0000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) - /* select serial console configuration */ #define CONFIG_SERIAL1 1 /* use SERIAL 1 */ -#define CONFIG_BAUDRATE 115200 #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI - -/* PWM */ -#define CONFIG_PWM 1 - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -/* Command definition*/ -#include - #define CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP -#define CONFIG_CMD_MMC #define CONFIG_CMD_NET -#define CONFIG_CMD_FAT - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* MMC SPL */ #define CONFIG_SKIP_LOWLEVEL_INIT @@ -84,15 +55,8 @@ #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "SMDKV310 # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) @@ -111,8 +75,6 @@ #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE /* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH 1 -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for SMDKC210/V310" #define CONFIG_CLK_1000_400_200 @@ -126,7 +88,6 @@ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) -#define CONFIG_DOS_PARTITION 1 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) @@ -146,6 +107,4 @@ #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT #endif /* __CONFIG_H */ -- cgit v0.10.2 From 311757be275c1d592ff357e9faedca4c967a3064 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:50 -0600 Subject: samsung: Enable device tree for s5p_goni Change this board to add a device tree. This also adds a pinmux header file although it is not used as yet. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 43ba33a..22ceb9d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -336,6 +336,9 @@ config TARGET_BCM958622HR config ARCH_EXYNOS bool "Samsung EXYNOS" +config ARCH_S5PC1XX + bool "Samsung S5PC1XX" + config ARCH_HIGHBANK bool "Calxeda Highbank" @@ -429,9 +432,6 @@ config RMOBILE config TARGET_CM_FX6 bool "Support cm_fx6" -config TARGET_S5P_GONI - bool "Support s5p_goni" - config TARGET_SMDKC100 bool "Support smdkc100" @@ -550,6 +550,8 @@ source "arch/arm/cpu/arm926ejs/orion5x/Kconfig" source "arch/arm/cpu/armv7/rmobile/Kconfig" +source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" + source "arch/arm/cpu/armv7/tegra-common/Kconfig" source "arch/arm/cpu/armv7/uniphier/Kconfig" @@ -657,7 +659,6 @@ source "board/raspberrypi/rpi_b/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" source "board/ronetix/pm9g45/Kconfig" -source "board/samsung/goni/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/samsung/smdkc100/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig new file mode 100644 index 0000000..1a8941d --- /dev/null +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -0,0 +1,20 @@ +if ARCH_S5PC1XX + +choice + prompt "S5PC1XX board select" + +config TARGET_S5P_GONI + bool "S5P Goni board" + select OF_CONTROL if !SPL_BUILD + +endchoice + +config SYS_CPU + default "armv7" + +config SYS_SOC + default "s5pc1xx" + +source "board/samsung/goni/Kconfig" + +endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 43a70e4..076e0f7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-universal_c210.dtb \ diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts new file mode 100644 index 0000000..2e671bb --- /dev/null +++ b/arch/arm/dts/s5pc1xx-goni.dts @@ -0,0 +1,28 @@ +/* + * Samsung's S5PC110-based Goni board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Samsung Goni based on S5PC110"; + compatible = "samsung,goni", "samsung,s5pc110"; + + aliases { + serial2 = "/serial@e2900800"; + console = "/serial@e2900800"; + }; + + serial@e2900800 { + compatible = "samsung,exynos4210-uart"; + reg = <0xe2900800 0x400>; + id = <2>; + }; + +}; diff --git a/arch/arm/include/asm/arch-s5pc1xx/periph.h b/arch/arm/include/asm/arch-s5pc1xx/periph.h new file mode 100644 index 0000000..5c1c3d4 --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc1xx/periph.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + PERIPH_ID_UART0 = 51, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_I2C0 = 56, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_SPI0 = 68, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SDMMC0 = 75, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_I2C8 = 87, + PERIPH_ID_I2C9, + PERIPH_ID_I2S0 = 98, + PERIPH_ID_I2S1 = 99, + + /* Since following peripherals do + * not have shared peripheral interrupts (SPIs) + * they are numbered arbitiraly after the maximum + * SPIs Exynos has (128) + */ + PERIPH_ID_SROMC = 128, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, + PERIPH_ID_SDMMC4, + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + PERIPH_ID_I2C10 = 203, + + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h new file mode 100644 index 0000000..0b91ef6 --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Abhilash Kesavan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + +/* + * Flags for setting specific configarations of peripherals. + * List will grow with support for more devices getting added. + */ +enum { + PINMUX_FLAG_NONE = 0x00000000, + + /* Flags for eMMC */ + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ + + /* Flags for SROM controller */ + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ +}; + +/** + * Configures the pinmux for a particular peripheral. + * + * Each gpio can be configured in many different ways (4 bits on exynos) + * such as "input", "output", "special function", "external interrupt" + * etc. This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @param flags configure flags + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int exynos_pinmux_config(int peripheral, int flags); + +/** + * Decode the peripheral id using the interrpt numbers. + * + * @param blob Device tree blob + * @param node FDT I2C node to find + * @return peripheral id if ok, PERIPH_ID_NONE on error + */ +int pinmux_decode_periph_id(const void *blob, int node); +#endif diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index c0c3509..618e590 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -1,2 +1,4 @@ CONFIG_ARM=y +CONFIG_ARCH_S5PC1XX=y CONFIG_TARGET_S5P_GONI=y +CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni" diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 2ff0ec2..637dd97 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -14,9 +14,7 @@ #include #include #include -#ifdef CONFIG_OF_CONTROL #include -#endif static char *S5P_NAME = "SAMSUNG SDHCI"; static void s5p_sdhci_set_control_reg(struct sdhci_host *host) diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index a51215d..feb4d76 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -53,6 +53,7 @@ #define CONFIG_MMC #define CONFIG_SDHCI #define CONFIG_S5P_SDHCI +#define SDHCI_MAX_HOSTS 4 /* PWM */ #define CONFIG_PWM 1 @@ -106,7 +107,6 @@ ",12m(modem)"\ ",60m(qboot)\0" -#define CONFIG_BOOTDELAY 1 #define CONFIG_ZERO_BOOTDELAY_CHECK /* partitions definitions */ @@ -283,4 +283,6 @@ #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_OF_LIBFDT + #endif /* __CONFIG_H */ -- cgit v0.10.2 From 93327f69769d9fe09ef25efd6ca9182f1095a417 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:51 -0600 Subject: samsung: Enable device tree for smdkc100 Change this board to add a device tree. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 22ceb9d..6c5ecd2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -432,9 +432,6 @@ config RMOBILE config TARGET_CM_FX6 bool "Support cm_fx6" -config TARGET_SMDKC100 - bool "Support smdkc100" - config TARGET_SOCFPGA_CYCLONE5 bool "Support socfpga_cyclone5" @@ -660,7 +657,6 @@ source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" source "board/ronetix/pm9g45/Kconfig" source "board/samsung/smdk2410/Kconfig" -source "board/samsung/smdkc100/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/scb9328/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig index 1a8941d..2fbbc18 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -7,6 +7,10 @@ config TARGET_S5P_GONI bool "S5P Goni board" select OF_CONTROL if !SPL_BUILD +config TARGET_SMDKC100 + bool "Support smdkc100 board" + select OF_CONTROL if !SPL_BUILD + endchoice config SYS_CPU @@ -16,5 +20,6 @@ config SYS_SOC default "s5pc1xx" source "board/samsung/goni/Kconfig" +source "board/samsung/smdkc100/Kconfig" endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 076e0f7..c37580e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ diff --git a/arch/arm/dts/s5pc1xx-smdkc100.dts b/arch/arm/dts/s5pc1xx-smdkc100.dts new file mode 100644 index 0000000..42754ce --- /dev/null +++ b/arch/arm/dts/s5pc1xx-smdkc100.dts @@ -0,0 +1,29 @@ +/* + * Samsung's Exynos4210-based SMDKV310 board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Samsung SMDKC100 based on S5PC100"; + compatible = "samsung,smdkc100", "samsung,s5pc100"; + + aliases { + serial0 = "/serial@ec000000"; + console = "/serial@ec000000"; + }; + + serial@ec000000 { + compatible = "samsung,exynos4210-uart"; + reg = <0xec000000 0x100>; + interrupts = <0 51 0>; + id = <0>; + }; + +}; diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index 7455235..041030f 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -1,2 +1,4 @@ CONFIG_ARM=y CONFIG_TARGET_SMDKC100=y +CONFIG_ARCH_S5PC1XX=y +CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100" diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index c9a2e15..566028d 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -217,4 +217,6 @@ #define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ #endif /* CONFIG_CMD_NET */ +#define CONFIG_OF_LIBFDT + #endif /* __CONFIG_H */ -- cgit v0.10.2 From 2ecd779742e3eda5b8d1355b56ddc1ea836c8407 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:52 -0600 Subject: exynos: Enable pre-relocation malloc() Enable this feature to support driver model before relocation. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 54b61d7..371f32d 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -38,8 +38,9 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_ENV_OVERWRITE -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) /* select serial console configuration */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 07a2ff6..b928af8 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -37,8 +37,6 @@ #define CONFIG_SYS_TEXT_BASE 0x43e00000 #include -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) /* select serial console configuration */ #define CONFIG_SERIAL1 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index feb4d76..0c6e9c7 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -39,8 +39,9 @@ #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING -/* Size of malloc() pool.*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 80 * SZ_1M) +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) /* * select serial console configuration diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 566028d..22835ff 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -47,6 +47,10 @@ * 1MB = 0x100000, 0x100000 = 1024 * 1024 */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* Small malloc pool before relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + /* * select serial console configuration */ -- cgit v0.10.2 From dab067c32307d7f78ab00ef19690fecbc3ad607a Mon Sep 17 00:00:00 2001 From: Robert Baldyga Date: Fri, 19 Sep 2014 12:17:55 +0200 Subject: armv7: s5pc1xx: improve cache handling Move cache handling code to C file, and add enable_caches() and disable_caches() functions. Signed-off-by: Robert Baldyga Signed-off-by: Minkyu Kang diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S deleted file mode 100644 index 3089592..0000000 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Minkyu Kang - * - * based on arch/arm/cpu/armv7/omap3/cache.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.align 5 - -#include - -#ifndef CONFIG_SYS_L2CACHE_OFF -ENTRY(v7_outer_cache_enable) - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - orr r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} -ENDPROC(v7_outer_cache_enable) - -ENTRY(v7_outer_cache_disable) - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - bic r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} -ENDPROC(v7_outer_cache_disable) -#endif diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/cpu/armv7/s5pc1xx/cache.c new file mode 100644 index 0000000..51af299 --- /dev/null +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Minkyu Kang + * Robert Baldyga + * + * based on arch/arm/cpu/armv7/omap3/cache.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + dcache_enable(); +} + +void disable_caches(void) +{ + dcache_disable(); +} +#endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +void v7_outer_cache_enable(void) +{ + __asm( + "push {r0, r1, r2, lr}\n\t" + "mrc 15, 0, r3, cr1, cr0, 1\n\t" + "orr r3, r3, #2\n\t" + "mcr 15, 0, r3, cr1, cr0, 1\n\t" + "pop {r1, r2, r3, pc}" + ); +} + +void v7_outer_cache_disable(void) +{ + __asm( + "push {r0, r1, r2, lr}\n\t" + "mrc 15, 0, r3, cr1, cr0, 1\n\t" + "bic r3, r3, #2\n\t" + "mcr 15, 0, r3, cr1, cr0, 1\n\t" + "pop {r1, r2, r3, pc}" + ); +} +#endif -- cgit v0.10.2 From de8f7705aa8f39f2f959299d8d6b290674ab27b3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 26 Sep 2014 18:54:43 +0900 Subject: exynos: update maintainer of Snow and SMDK5420 board The email address of Rajeshwari Shinde is not working. This commit gives Akshay the maintainership of Snow and SMDK5420 boards. Signed-off-by: Masahiro Yamada Cc: Akshay Saraswat Cc: Minkyu Kang Signed-off-by: Minkyu Kang diff --git a/board/samsung/smdk5250/MAINTAINERS b/board/samsung/smdk5250/MAINTAINERS index 8a2a4aa..070593e 100644 --- a/board/samsung/smdk5250/MAINTAINERS +++ b/board/samsung/smdk5250/MAINTAINERS @@ -6,7 +6,7 @@ F: include/configs/smdk5250.h F: configs/smdk5250_defconfig SNOW BOARD -M: Rajeshwari Shinde +M: Akshay Saraswat S: Maintained F: include/configs/snow.h F: configs/snow_defconfig diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index c8241a8..e0f5c7a 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -4,9 +4,5 @@ S: Maintained F: board/samsung/smdk5420/ F: include/configs/peach-pit.h F: configs/peach-pit_defconfig - -SMDK5420 BOARD -M: Rajeshwari Shinde -S: Maintained F: include/configs/smdk5420.h F: configs/smdk5420_defconfig -- cgit v0.10.2 From b219773957d2ee8fedb56f0fcb19288eb72d4867 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 23 Sep 2014 12:46:43 +0200 Subject: odroid: clock: set aclk_cores to 200MHz This change fixes suspend/resume issue in the kernel caused by the wrong 'aclk_cores' clock value expected by the kernel. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Signed-off-by: Minkyu Kang diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index ac19527..5edb250 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -158,10 +158,10 @@ static void board_clock_init(void) * For MOUThpm = 1000 MHz (MOUTapll) * doutcopy = MOUThpm / (ratio + 1) = 200 (4) * sclkhpm = doutcopy / (ratio + 1) = 200 (4) - * cores_out = armclk / (ratio + 1) = 1000 (0) + * cores_out = armclk / (ratio + 1) = 200 (4) */ clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); - set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0); + set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4); clrsetbits_le32(&clk->div_cpu1, clr, set); -- cgit v0.10.2