From 22854bda8092babd5a8ac2e64a5bbdc90d7b827f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 17:41:58 +0100 Subject: net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF Add code to process the KSZ9021/KSZ9031 OF props if they are present and configure skew registers based on the information from the OF. This code is only enabled if the DM support for ethernet is also enabled. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Chin Liang See Cc: Dinh Nguyen V2: - Implement struct ksz90x1_reg_field to describe the skew register fields more accurately. - Fix RXDV/TXEN skew register default value and offset. diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 5e49666..19b6bc7 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -9,9 +9,14 @@ */ #include #include +#include +#include +#include #include #include +DECLARE_GLOBAL_DATA_PTR; + static struct phy_driver KSZ804_driver = { .name = "Micrel KSZ804", .uid = 0x221510, @@ -174,6 +179,73 @@ static int ksz90xx_startup(struct phy_device *phydev) return 0; } +/* Common OF config bits for KSZ9021 and KSZ9031 */ +#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031) +#ifdef CONFIG_DM_ETH +struct ksz90x1_reg_field { + const char *name; + const u8 size; /* Size of the bitfield, in bits */ + const u8 off; /* Offset from bit 0 */ + const u8 dflt; /* Default value */ +}; + +struct ksz90x1_ofcfg { + const u16 reg; + const u16 devad; + const struct ksz90x1_reg_field *grp; + const u16 grpsz; +}; + +static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = { + { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 }, + { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 } +}; + +static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = { + { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 }, + { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 }, +}; + +static int ksz90x1_of_config_group(struct phy_device *phydev, + struct ksz90x1_ofcfg *ofcfg) +{ + struct udevice *dev = phydev->dev; + struct phy_driver *drv = phydev->drv; + const int ps_to_regval = 200; + int val[4]; + int i, changed = 0, offset, max; + u16 regval = 0; + + if (!drv || !drv->writeext) + return -EOPNOTSUPP; + + for (i = 0; i < ofcfg->grpsz; i++) { + val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + ofcfg->grp[i].name, -1); + offset = ofcfg->grp[i].off; + if (val[i] == -1) { + /* Default register value for KSZ9021 */ + regval |= ofcfg->grp[i].dflt << offset; + } else { + changed = 1; /* Value was changed in OF */ + /* Calculate the register value and fix corner cases */ + if (val[i] > ps_to_regval * 0xf) { + max = (1 << ofcfg->grp[i].size) - 1; + regval |= max << offset; + } else { + regval |= (val[i] / ps_to_regval) << offset; + } + } + } + + if (!changed) + return 0; + + return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval); +} +#endif +#endif + #ifdef CONFIG_PHY_MICREL_KSZ9021 /* * KSZ9021 @@ -188,6 +260,35 @@ static int ksz90xx_startup(struct phy_device *phydev) #define CTRL1000_CONFIG_MASTER (1 << 11) #define CTRL1000_MANUAL_CONFIG (1 << 12) +#ifdef CONFIG_DM_ETH +static const struct ksz90x1_reg_field ksz9021_clk_grp[] = { + { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 }, + { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 }, +}; + +static int ksz9021_of_config(struct phy_device *phydev) +{ + struct ksz90x1_ofcfg ofcfg[] = { + { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 }, + { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 }, + { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 }, + }; + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(ofcfg); i++) + ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); + if (ret) + return ret; + + return 0; +} +#else +static int ksz9021_of_config(struct phy_device *phydev) +{ + return 0; +} +#endif + int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val) { /* extended registers */ @@ -224,6 +325,11 @@ static int ksz9021_config(struct phy_device *phydev) const unsigned master = CTRL1000_PREFER_MASTER | CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG; unsigned features = phydev->drv->features; + int ret; + + ret = ksz9021_of_config(phydev); + if (ret) + return ret; if (getenv("disable_giga")) features &= ~(SUPPORTED_1000baseT_Half | @@ -260,6 +366,36 @@ static struct phy_driver ksz9021_driver = { #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d #define MII_KSZ9031_MMD_REG_DATA 0x0e +#ifdef CONFIG_DM_ETH +static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = + { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } }; +static const struct ksz90x1_reg_field ksz9031_clk_grp[] = + { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } }; + +static int ksz9031_of_config(struct phy_device *phydev) +{ + struct ksz90x1_ofcfg ofcfg[] = { + { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 }, + { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 }, + { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 }, + { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 }, + }; + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(ofcfg); i++) + ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); + if (ret) + return ret; + + return 0; +} +#else +static int ksz9031_of_config(struct phy_device *phydev) +{ + return 0; +} +#endif + /* Accessors to extended registers*/ int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr, int regnum, u16 mode, u16 val) @@ -304,13 +440,21 @@ static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr, MII_KSZ9031_MOD_DATA_POST_INC_RW, val); }; +static int ksz9031_config(struct phy_device *phydev) +{ + int ret; + ret = ksz9031_of_config(phydev); + if (ret) + return ret; + return genphy_config(phydev); +} static struct phy_driver ksz9031_driver = { .name = "Micrel ksz9031", .uid = 0x221620, .mask = 0xfffff0, .features = PHY_GBIT_FEATURES, - .config = &genphy_config, + .config = &ksz9031_config, .startup = &ksz90xx_startup, .shutdown = &genphy_shutdown, .writeext = &ksz9031_phy_extwrite, -- cgit v0.10.2 From 5d8546efa7b134ff16f70c614571bd9d1676a4f8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 17:53:40 +0100 Subject: arm: socfpga: socrates: Add missing PHY skew config Add missing KSZ9021 PHY skew configuration for the EBV socrates board. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 05b935d..a18d168 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -28,6 +28,15 @@ &gmac1 { status = "okay"; phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; }; &i2c0 { -- cgit v0.10.2 From 6b9cdb716f64d284046221e05bd10673c287bd05 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 17:54:35 +0100 Subject: arm: socfpga: arria5-socdk: Remove Micrel PHY configuration The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/board/altera/arria5-socdk/socfpga.c b/board/altera/arria5-socdk/socfpga.c index 0fbbc34..ccb1b4b 100644 --- a/board/altera/arria5-socdk/socfpga.c +++ b/board/altera/arria5-socdk/socfpga.c @@ -12,10 +12,6 @@ #include #include -#include -#include -#include - DECLARE_GLOBAL_DATA_PTR; void s_init(void) {} @@ -31,42 +27,6 @@ int board_init(void) return 0; } -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9021 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif - #ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { .regs_otg = CONFIG_USB_DWC2_REG_ADDR, diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index ebb6ed5..465df54 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -47,15 +47,8 @@ /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - #endif #define CONFIG_ENV_IS_IN_MMC -- cgit v0.10.2 From b5aaa03634a171d04824336b42790f3e77203bf2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 17:55:19 +0100 Subject: arm: socfpga: cyclone5-socdk: Remove Micrel PHY configuration The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c index 0fbbc34..ccb1b4b 100644 --- a/board/altera/cyclone5-socdk/socfpga.c +++ b/board/altera/cyclone5-socdk/socfpga.c @@ -12,10 +12,6 @@ #include #include -#include -#include -#include - DECLARE_GLOBAL_DATA_PTR; void s_init(void) {} @@ -31,42 +27,6 @@ int board_init(void) return 0; } -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9021 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif - #ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { .regs_otg = CONFIG_USB_DWC2_REG_ADDR, diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 67bb35f..5e4a709 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -47,15 +47,8 @@ /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - #endif #define CONFIG_ENV_IS_IN_MMC -- cgit v0.10.2 From 5df93c556445940a5e96e511d11497db382a409a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 19:00:00 +0100 Subject: arm: socfpga: de0_nano: Remove Micrel PHY configuration The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/board/terasic/de0-nano-soc/socfpga.c b/board/terasic/de0-nano-soc/socfpga.c index 85700b0..3ccc2a7 100644 --- a/board/terasic/de0-nano-soc/socfpga.c +++ b/board/terasic/de0-nano-soc/socfpga.c @@ -6,10 +6,6 @@ #include -#include -#include -#include - DECLARE_GLOBAL_DATA_PTR; void s_init(void) {} @@ -24,49 +20,3 @@ int board_init(void) return 0; } - -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9031 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x70); - if (ret) - return ret; - - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x7777); - if (ret) - return ret; - - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0); - if (ret) - return ret; - - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x03FC); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 16e146c..870192d 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -47,11 +47,8 @@ /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9031 - #endif #define CONFIG_ENV_IS_IN_MMC -- cgit v0.10.2 From 1f5f18717254d6d0c0758580980ff096a8587b9d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 17:55:54 +0100 Subject: arm: socfpga: sockit: Remove Micrel PHY configuration The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/board/terasic/sockit/socfpga.c b/board/terasic/sockit/socfpga.c index 0fbbc34..ccb1b4b 100644 --- a/board/terasic/sockit/socfpga.c +++ b/board/terasic/sockit/socfpga.c @@ -12,10 +12,6 @@ #include #include -#include -#include -#include - DECLARE_GLOBAL_DATA_PTR; void s_init(void) {} @@ -31,42 +27,6 @@ int board_init(void) return 0; } -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9021 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif - #ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { .regs_otg = CONFIG_USB_DWC2_REG_ADDR, diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 5bcee05..c1178ac 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -47,15 +47,8 @@ /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - #endif #define CONFIG_ENV_IS_IN_MMC -- cgit v0.10.2 From faed7ac8fa0f94c23cfef20684a268891a1a9fd2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 17:55:36 +0100 Subject: arm: socfpga: socrates: Remove Micrel PHY configuration The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c index 0fbbc34..ccb1b4b 100644 --- a/board/ebv/socrates/socfpga.c +++ b/board/ebv/socrates/socfpga.c @@ -12,10 +12,6 @@ #include #include -#include -#include -#include - DECLARE_GLOBAL_DATA_PTR; void s_init(void) {} @@ -31,42 +27,6 @@ int board_init(void) return 0; } -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9021 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif - #ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { .regs_otg = CONFIG_USB_DWC2_REG_ADDR, diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index 16a2a86..de8ced6 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -43,15 +43,8 @@ /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) - -/* PHY */ #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9021 -#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" -#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 -#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" -#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 - #endif #define CONFIG_ENV_IS_IN_MMC -- cgit v0.10.2 From ef4b01b2f7f176bb9107654257f7f3ed7fc2cf19 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 19:28:44 +0100 Subject: arm: socfpga: Allow DWC2 UDC probing from OF The USB gadget framework does not support DM yet, so add this bit to let DWC2 UDC probe from OF on platforms which support it. Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Chin Liang See Cc: Dinh Nguyen Cc: Lukasz Majewski Cc: Lukasz Majewski diff --git a/include/fdtdec.h b/include/fdtdec.h index 7fe657d..d82dc35 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -167,6 +167,7 @@ enum fdt_compat_id { COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ + COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 82d0090..ae0b708 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -71,6 +71,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"), COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"), COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), + COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), }; -- cgit v0.10.2 From 70311e69fa7f0b7c289eb6552ccc3f9fb7320c69 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 19:24:22 +0100 Subject: arm: socfpga: arria5-socdk: Probe DWC2 UDC from OF instead of hard-coded data This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Lukasz Majewski Cc: Lukasz Majewski diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 7d1836e..5933a40 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -25,6 +25,7 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + udc0 = &usb1; }; regulator_3_3v: 3-3-v-regulator { diff --git a/board/altera/arria5-socdk/socfpga.c b/board/altera/arria5-socdk/socfpga.c index ccb1b4b..449f3b5 100644 --- a/board/altera/arria5-socdk/socfpga.c +++ b/board/altera/arria5-socdk/socfpga.c @@ -5,12 +5,12 @@ */ #include +#include #include #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -29,12 +29,29 @@ int board_init(void) #ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, .usb_gusbcfg = 0x1417, }; int board_usb_init(int index, enum usb_init_type init) { + int node[2], count; + fdt_addr_t addr; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", + COMPAT_ALTERA_SOCFPGA_DWC2USB, + node, 2); + if (count <= 0) /* No controller found. */ + return 0; + + addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); + if (addr == FDT_ADDR_T_NONE) { + printf("UDC Controller has no 'reg' property!\n"); + return -EINVAL; + } + + /* Patch the address from OF into the controller pdata. */ + socfpga_otg_data.regs_otg = addr; + return dwc2_udc_probe(&socfpga_otg_data); } diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index f59bc00..10eb91d 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -21,3 +21,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 465df54..d2411e6 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -56,9 +56,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif #define CONFIG_G_DNL_MANUFACTURER "Altera" /* Extra Environment */ -- cgit v0.10.2 From c90ada94fba5486d4b4d3773013804982ccadb56 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 19:24:22 +0100 Subject: arm: socfpga: cyclone5-socdk: Probe DWC2 UDC from OF instead of hard-coded data This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Lukasz Majewski Cc: Lukasz Majewski diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 9eb5a22..224928f 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -25,6 +25,7 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + udc0 = &usb1; }; regulator_3_3v: 3-3-v-regulator { @@ -77,10 +78,6 @@ vqmmc-supply = <®ulator_3_3v>; }; -&usb1 { - status = "okay"; -}; - &qspi { status = "okay"; @@ -100,3 +97,7 @@ tslch-ns = <4>; }; }; + +&usb1 { + status = "okay"; +}; diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c index ccb1b4b..449f3b5 100644 --- a/board/altera/cyclone5-socdk/socfpga.c +++ b/board/altera/cyclone5-socdk/socfpga.c @@ -5,12 +5,12 @@ */ #include +#include #include #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -29,12 +29,29 @@ int board_init(void) #ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, .usb_gusbcfg = 0x1417, }; int board_usb_init(int index, enum usb_init_type init) { + int node[2], count; + fdt_addr_t addr; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", + COMPAT_ALTERA_SOCFPGA_DWC2USB, + node, 2); + if (count <= 0) /* No controller found. */ + return 0; + + addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); + if (addr == FDT_ADDR_T_NONE) { + printf("UDC Controller has no 'reg' property!\n"); + return -EINVAL; + } + + /* Patch the address from OF into the controller pdata. */ + socfpga_otg_data.regs_otg = addr; + return dwc2_udc_probe(&socfpga_otg_data); } diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index c0d6913..864358c 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -21,3 +21,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 5e4a709..76d29a3 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -56,9 +56,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif #define CONFIG_G_DNL_MANUFACTURER "Altera" /* Extra Environment */ -- cgit v0.10.2 From 5b5226a8e68eae394aed7ca2d7691ebd7ef8ba4e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 19:24:22 +0100 Subject: arm: socfpga: de0_nano: Probe DWC2 UDC from OF instead of hard-coded data This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Lukasz Majewski Cc: Lukasz Majewski diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts index b649c9a..dc09bed 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -16,6 +16,7 @@ aliases { ethernet0 = &gmac1; + udc0 = &usb1; }; memory { @@ -59,3 +60,7 @@ status = "okay"; u-boot,dm-pre-reloc; }; + +&usb1 { + status = "okay"; +}; diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index a4f75e6..65c1197 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -19,3 +19,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 870192d..d27aa9b 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -56,9 +56,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif #define CONFIG_G_DNL_MANUFACTURER "Terasic" /* Extra Environment */ -- cgit v0.10.2 From 9368aa6a680f150755a233be9f97956bba5a915e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 19:24:22 +0100 Subject: arm: socfpga: mcvevk: Probe DWC2 UDC from OF instead of hard-coded data This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Lukasz Majewski Cc: Lukasz Majewski diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts index e1e3d73..7d3f989 100644 --- a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts @@ -16,6 +16,7 @@ aliases { ethernet0 = &gmac0; + udc0 = &usb1; }; memory { @@ -51,3 +52,7 @@ bus-width = <8>; u-boot,dm-pre-reloc; }; + +&usb1 { + status = "okay"; +}; diff --git a/board/denx/mcvevk/socfpga.c b/board/denx/mcvevk/socfpga.c index 0f93722..d77d7ad 100644 --- a/board/denx/mcvevk/socfpga.c +++ b/board/denx/mcvevk/socfpga.c @@ -5,12 +5,12 @@ */ #include +#include #include #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -29,12 +29,29 @@ int board_init(void) #ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, .usb_gusbcfg = 0x1417, }; int board_usb_init(int index, enum usb_init_type init) { + int node[2], count; + fdt_addr_t addr; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", + COMPAT_ALTERA_SOCFPGA_DWC2USB, + node, 2); + if (count <= 0) /* No controller found. */ + return 0; + + addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); + if (addr == FDT_ADDR_T_NONE) { + printf("UDC Controller has no 'reg' property!\n"); + return -EINVAL; + } + + /* Patch the address from OF into the controller pdata. */ + socfpga_otg_data.regs_otg = addr; + return dwc2_udc_probe(&socfpga_otg_data); } diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 382db65..c98d4a1 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -19,3 +19,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index d051eec..b2c1f75 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -49,9 +49,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif #define CONFIG_G_DNL_MANUFACTURER "DENX" /* Extra Environment */ -- cgit v0.10.2 From 225217da2804d1c61725e2974262bd2f27882cd7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 19:24:22 +0100 Subject: arm: socfpga: sockit: Probe DWC2 UDC from OF instead of hard-coded data This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Lukasz Majewski Cc: Lukasz Majewski diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts index d7c41c8..e45c2ab 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts @@ -14,9 +14,10 @@ bootargs = "console=ttyS0,115200"; }; - aliases { + aliases { ethernet0 = &gmac1; - }; + udc0 = &usb1; + }; memory { name = "memory"; @@ -90,3 +91,7 @@ tslch-ns = <4>; }; }; + +&usb1 { + status = "okay"; +}; diff --git a/board/terasic/sockit/socfpga.c b/board/terasic/sockit/socfpga.c index ccb1b4b..1fe8c1c 100644 --- a/board/terasic/sockit/socfpga.c +++ b/board/terasic/sockit/socfpga.c @@ -5,12 +5,12 @@ */ #include +#include #include #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -29,12 +29,29 @@ int board_init(void) #ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, .usb_gusbcfg = 0x1417, }; int board_usb_init(int index, enum usb_init_type init) { + int node[2], count; + fdt_addr_t addr; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", + COMPAT_ALTERA_SOCFPGA_DWC2USB, + node, 2); + if (count <= 0) /* No controller found. */ + return -EINVAL; + + addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); + if (addr == FDT_ADDR_T_NONE) { + printf("UDC Controller has no 'reg' property!\n"); + return -EINVAL; + } + + /* Patch the address from OF into the controller pdata. */ + socfpga_otg_data.regs_otg = addr; + return dwc2_udc_probe(&socfpga_otg_data); } diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 03f8eff..b4f41a9 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -23,3 +23,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index c1178ac..eefe01c 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -56,9 +56,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif #define CONFIG_G_DNL_MANUFACTURER "Terasic" /* Extra Environment */ -- cgit v0.10.2 From b5a5d2bd967781818ab1eadcd3ce779d01676e2e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 19:24:22 +0100 Subject: arm: socfpga: socrates: Probe DWC2 UDC from OF instead of hard-coded data This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Lukasz Majewski Cc: Lukasz Majewski diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index a18d168..591d96c 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -14,6 +14,10 @@ bootargs = "console=ttyS0,115200"; }; + aliases { + udc0 = &usb1; + }; + memory { name = "memory"; device_type = "memory"; @@ -72,3 +76,7 @@ tslch-ns = <4>; }; }; + +&usb1 { + status = "okay"; +}; diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c index ccb1b4b..449f3b5 100644 --- a/board/ebv/socrates/socfpga.c +++ b/board/ebv/socrates/socfpga.c @@ -5,12 +5,12 @@ */ #include +#include #include #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -29,12 +29,29 @@ int board_init(void) #ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, .usb_gusbcfg = 0x1417, }; int board_usb_init(int index, enum usb_init_type init) { + int node[2], count; + fdt_addr_t addr; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", + COMPAT_ALTERA_SOCFPGA_DWC2USB, + node, 2); + if (count <= 0) /* No controller found. */ + return 0; + + addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); + if (addr == FDT_ADDR_T_NONE) { + printf("UDC Controller has no 'reg' property!\n"); + return -EINVAL; + } + + /* Patch the address from OF into the controller pdata. */ + socfpga_otg_data.regs_otg = addr; + return dwc2_udc_probe(&socfpga_otg_data); } diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 932f0e8..fe940f9 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -22,3 +22,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index de8ced6..1b0888f 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -52,9 +52,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -#endif #define CONFIG_G_DNL_MANUFACTURER "EBV" /* Extra Environment */ -- cgit v0.10.2 From ac5516dd30bd3ec125ba98e32e2eb656793a9532 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 20:00:52 +0100 Subject: arm: socfpga: de0_nano: Zap VIRTUAL_TARGET There is no VT for this board, so remove this incorrect macro. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index d27aa9b..6007895 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -37,11 +37,7 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v0.10.2 From 92232747bb99e1f72860dd4ed293402f21667358 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 20:01:40 +0100 Subject: arm: socfpga: sockit: Zap VIRTUAL_TARGET There is no VT for this board, so remove this incorrect macro. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index eefe01c..924de3f 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -37,11 +37,7 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v0.10.2 From a5cad67735a1f098c22ec30941f1bd0422459069 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 20:05:46 +0100 Subject: arm: socfpga: Switch CONFIG_G_DNL_MANUFACTURER to CONFIG_SYS_VENDOR We already have the CONFIG_SYS_VENDOR variable, which defines the manufacturer of the board. The value in CONFIG_G_DNL_MANUFACTURER is just a duplicity, so switch it to reuse CONFIG_SYS_VENDOR . Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index d2411e6..a036856 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -55,9 +55,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ -/* USB */ -#define CONFIG_G_DNL_MANUFACTURER "Altera" - /* Extra Environment */ #define CONFIG_HOSTNAME socfpga_arria5 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index b0bc689..4b2d246 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -262,7 +262,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM #ifndef CONFIG_G_DNL_MANUFACTURER -#define CONFIG_G_DNL_MANUFACTURER "Altera" +#define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR #endif #endif diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 76d29a3..4e38d5e 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -55,9 +55,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ -/* USB */ -#define CONFIG_G_DNL_MANUFACTURER "Altera" - /* Extra Environment */ #define CONFIG_HOSTNAME socfpga_cyclone5 diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 6007895..e06ca7b 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -51,9 +51,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ -/* USB */ -#define CONFIG_G_DNL_MANUFACTURER "Terasic" - /* Extra Environment */ #define CONFIG_HOSTNAME socfpga_de0_nano_soc diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index b2c1f75..5fc4edb 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -48,9 +48,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ -/* USB */ -#define CONFIG_G_DNL_MANUFACTURER "DENX" - /* Extra Environment */ #define CONFIG_HOSTNAME mcvevk diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 924de3f..d5e69fd 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -51,9 +51,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ -/* USB */ -#define CONFIG_G_DNL_MANUFACTURER "Terasic" - /* Extra Environment */ #define CONFIG_HOSTNAME socfpga_sockit diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index 1b0888f..f11c89c 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -51,9 +51,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ -/* USB */ -#define CONFIG_G_DNL_MANUFACTURER "EBV" - /* Extra Environment */ #define CONFIG_HOSTNAME socfpga_socrates -- cgit v0.10.2 From ea0823465157decd81bc06c3b6dfe8f604ee4471 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 20:08:21 +0100 Subject: arm: socfpga: Switch CONFIG_HOSTNAME to CONFIG_SYS_BOARD We already have the CONFIG_SYS_BOARD variable, which defines the name of the board. The value in CONFIG_HOSTNAME is exactly the same and is thus just a duplicity, so switch it to reuse CONFIG_SYS_BOARD . Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index a036856..3d5665d 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -56,8 +56,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_arria5 - #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4b2d246..f74c758 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -69,6 +69,10 @@ #define CONFIG_CMDLINE_EDITING /* Command history etc */ #define CONFIG_SYS_HUSH_PARSER +#ifndef CONFIG_SYS_HOSTNAME +#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD +#endif + /* * Cache */ diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 4e38d5e..d2efdda 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -56,8 +56,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_cyclone5 - #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index e06ca7b..959e3af 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -52,8 +52,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_de0_nano_soc - #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index 5fc4edb..cd63faf 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -49,8 +49,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ -#define CONFIG_HOSTNAME mcvevk - #define CONFIG_EXTRA_ENV_SETTINGS \ "consdev=ttyS0\0" \ "baudrate=115200\0" \ diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index d5e69fd..6cbe367 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -52,8 +52,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_sockit - #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index f11c89c..1d88f4f 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -52,8 +52,6 @@ #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ -#define CONFIG_HOSTNAME socfpga_socrates - #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index bccb235..5bd2956 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -53,9 +53,6 @@ #define CONFIG_PHY_MARVELL #define PHY_ANEG_TIMEOUT 8000 -/* Extra Environment */ -#define CONFIG_HOSTNAME sr1500 - #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ -- cgit v0.10.2 From 8e535af2e441030f5e4b940a3756a0d92646b5fe Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 21:07:23 +0100 Subject: arm: socfpga: Introduce common board code The SoCFPGA has reached a point where every single board code become the same, since each and every single board is probed equally from OF. Move the common board code into arch/arm/mach-socfpga/ . Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 316b326..5cf9e23 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,7 +8,7 @@ # obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ - fpga_manager.o scan_manager.o + fpga_manager.o scan_manager.o board.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o # QTS-generated config file wrappers diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c new file mode 100644 index 0000000..a41d089 --- /dev/null +++ b/arch/arm/mach-socfpga/board.c @@ -0,0 +1,64 @@ +/* + * Altera SoCFPGA common board code + * + * Copyright (C) 2015 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) {} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +#ifdef CONFIG_USB_GADGET +struct dwc2_plat_otg_data socfpga_otg_data = { + .usb_gusbcfg = 0x1417, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node[2], count; + fdt_addr_t addr; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", + COMPAT_ALTERA_SOCFPGA_DWC2USB, + node, 2); + if (count <= 0) /* No controller found. */ + return 0; + + addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); + if (addr == FDT_ADDR_T_NONE) { + printf("UDC Controller has no 'reg' property!\n"); + return -EINVAL; + } + + /* Patch the address from OF into the controller pdata. */ + socfpga_otg_data.regs_otg = addr; + + return dwc2_udc_probe(&socfpga_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + return 1; +} +#endif -- cgit v0.10.2 From dbd6fcfbe2331b953784ba972f66cb3df3e50ab2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 5 Dec 2015 21:10:44 +0100 Subject: arm: socfpga: Drop the board boilerplate Drop all the common board code, since it is not completely useless. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen diff --git a/board/altera/arria5-socdk/socfpga.c b/board/altera/arria5-socdk/socfpga.c index 449f3b5..97fb902 100644 --- a/board/altera/arria5-socdk/socfpga.c +++ b/board/altera/arria5-socdk/socfpga.c @@ -3,60 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include -#include -#include -#include - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_USB_GADGET -struct dwc2_plat_otg_data socfpga_otg_data = { - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node[2], count; - fdt_addr_t addr; - - count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", - COMPAT_ALTERA_SOCFPGA_DWC2USB, - node, 2); - if (count <= 0) /* No controller found. */ - return 0; - - addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); - if (addr == FDT_ADDR_T_NONE) { - printf("UDC Controller has no 'reg' property!\n"); - return -EINVAL; - } - - /* Patch the address from OF into the controller pdata. */ - socfpga_otg_data.regs_otg = addr; - - return dwc2_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c index 449f3b5..97fb902 100644 --- a/board/altera/cyclone5-socdk/socfpga.c +++ b/board/altera/cyclone5-socdk/socfpga.c @@ -3,60 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include -#include -#include -#include - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_USB_GADGET -struct dwc2_plat_otg_data socfpga_otg_data = { - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node[2], count; - fdt_addr_t addr; - - count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", - COMPAT_ALTERA_SOCFPGA_DWC2USB, - node, 2); - if (count <= 0) /* No controller found. */ - return 0; - - addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); - if (addr == FDT_ADDR_T_NONE) { - printf("UDC Controller has no 'reg' property!\n"); - return -EINVAL; - } - - /* Patch the address from OF into the controller pdata. */ - socfpga_otg_data.regs_otg = addr; - - return dwc2_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/denx/mcvevk/socfpga.c b/board/denx/mcvevk/socfpga.c index d77d7ad..6be58f0 100644 --- a/board/denx/mcvevk/socfpga.c +++ b/board/denx/mcvevk/socfpga.c @@ -3,60 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include -#include -#include -#include - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_USB_GADGET -struct dwc2_plat_otg_data socfpga_otg_data = { - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node[2], count; - fdt_addr_t addr; - - count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", - COMPAT_ALTERA_SOCFPGA_DWC2USB, - node, 2); - if (count <= 0) /* No controller found. */ - return 0; - - addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); - if (addr == FDT_ADDR_T_NONE) { - printf("UDC Controller has no 'reg' property!\n"); - return -EINVAL; - } - - /* Patch the address from OF into the controller pdata. */ - socfpga_otg_data.regs_otg = addr; - - return dwc2_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c index 449f3b5..97fb902 100644 --- a/board/ebv/socrates/socfpga.c +++ b/board/ebv/socrates/socfpga.c @@ -3,60 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include -#include -#include -#include - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_USB_GADGET -struct dwc2_plat_otg_data socfpga_otg_data = { - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node[2], count; - fdt_addr_t addr; - - count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", - COMPAT_ALTERA_SOCFPGA_DWC2USB, - node, 2); - if (count <= 0) /* No controller found. */ - return 0; - - addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); - if (addr == FDT_ADDR_T_NONE) { - printf("UDC Controller has no 'reg' property!\n"); - return -EINVAL; - } - - /* Patch the address from OF into the controller pdata. */ - socfpga_otg_data.regs_otg = addr; - - return dwc2_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c index 9f89584..617dffa 100644 --- a/board/sr1500/socfpga.c +++ b/board/sr1500/socfpga.c @@ -5,27 +5,10 @@ */ #include -#include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - int board_early_init_f(void) { int ret; diff --git a/board/terasic/de0-nano-soc/socfpga.c b/board/terasic/de0-nano-soc/socfpga.c index 3ccc2a7..97fb902 100644 --- a/board/terasic/de0-nano-soc/socfpga.c +++ b/board/terasic/de0-nano-soc/socfpga.c @@ -3,20 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} diff --git a/board/terasic/sockit/socfpga.c b/board/terasic/sockit/socfpga.c index 1fe8c1c..97fb902 100644 --- a/board/terasic/sockit/socfpga.c +++ b/board/terasic/sockit/socfpga.c @@ -3,60 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include -#include -#include -#include - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_USB_GADGET -struct dwc2_plat_otg_data socfpga_otg_data = { - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node[2], count; - fdt_addr_t addr; - - count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc", - COMPAT_ALTERA_SOCFPGA_DWC2USB, - node, 2); - if (count <= 0) /* No controller found. */ - return -EINVAL; - - addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg"); - if (addr == FDT_ADDR_T_NONE) { - printf("UDC Controller has no 'reg' property!\n"); - return -EINVAL; - } - - /* Patch the address from OF into the controller pdata. */ - socfpga_otg_data.regs_otg = addr; - - return dwc2_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif -- cgit v0.10.2 From ccf5648e0e3c4a61fe57109b39bf64c1cc1418c9 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 7 Dec 2015 16:48:04 -0600 Subject: arm: socfpga: remove note to add CONFIG_USB_DWC2_REG_ADDR Now that the USB DWC2 probing is done from OF, remove this note to add CONFIG_USB_DWC2_REG_ADDR. Signed-off-by: Dinh Nguyen diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f74c758..b57fd4c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -233,13 +233,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2 #define CONFIG_USB_STORAGE -/* - * NOTE: User must define either of the following to select which - * of the two USB controllers available on SoCFPGA to use. - * The DWC2 driver doesn't support multiple USB controllers. - * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS - * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS - */ #endif /* -- cgit v0.10.2 From ed77aeb575934ff8ec202a7fe6e0cdc07f8cee3e Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 2 Dec 2015 13:31:25 -0600 Subject: arm: socfpga: introduce TARGET_SOCFPGA_GEN5 config property In order to re-use as much Cyclone5 and Arria5 code as possible to support the Arria10 platform, we need to wrap some of the code with #ifdef's. By adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check for both AV || AV. Signed-off-by: Dinh Nguyen diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 0cb9f9e..dea4ce5 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -2,9 +2,14 @@ if ARCH_SOCFPGA config TARGET_SOCFPGA_ARRIA5 bool + select TARGET_SOCFPGA_GEN5 config TARGET_SOCFPGA_CYCLONE5 bool + select TARGET_SOCFPGA_GEN5 + +config TARGET_SOCFPGA_GEN5 + bool choice prompt "Altera SOCFPGA board select" -- cgit v0.10.2 From e5ad7d9889f6c2af625449dcb4487a3936709e50 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 2 Dec 2015 13:31:32 -0600 Subject: arm: socfpga: remove building scan manager The scan manager is not needed for the Arria10. Edit the makefile to build the scan manager for arria5 and cyclone5 only. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 5cf9e23..809cd47 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,11 +8,12 @@ # obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ - fpga_manager.o scan_manager.o board.o + fpga_manager.o board.o + obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o # QTS-generated config file wrappers -obj-y += wrap_pll_config.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) -- cgit v0.10.2 From a1684b61054714daae7250e570fe3298f86605b7 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 2 Dec 2015 13:31:33 -0600 Subject: arm: socfpga: fix up a questionable macro for SDMMC Move the macro into the socfpga_dwmci_clksel(). Signed-off-by: Dinh Nguyen Signed-off-by: Marek Vasut [fix parenthesis in the sdmmc_mask] diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 8712f8e..c45edea 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -129,9 +129,13 @@ struct socfpga_system_manager { #define SYSMGR_FPGAINTF_NAND (1 << 4) #define SYSMGR_FPGAINTF_SDMMC (1 << 5) -/* FIXME: This is questionable macro. */ -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 +#else +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#endif + +#define SYSMGR_SDMMC_DRVSEL_SHIFT 0 /* EMAC Group Bit definitions */ #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 5b0c3a8..43a7e7e 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -33,6 +33,8 @@ struct dwmci_socfpga_priv_data { static void socfpga_dwmci_clksel(struct dwmci_host *host) { struct dwmci_socfpga_priv_data *priv = host->priv; + u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | + ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); /* Disable SDMMC clock. */ clrbits_le32(&clock_manager_base->per_pll.en, @@ -40,8 +42,7 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); - writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel), - &system_manager_base->sdmmcgrp_ctrl); + writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl); debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, readl(&system_manager_base->sdmmcgrp_ctrl)); -- cgit v0.10.2 From 48275c96ff4deaeca10d9e18c78f6a1e3653efa2 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 3 Dec 2015 16:05:59 -0600 Subject: arm: socfpga: fix trivial header preprocessor for socfpga_common.h Replace__CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ with __CONFIG_SOCFPGA_COMMON_H__ as the file is now called socfpga_common.h Signed-off-by: Dinh Nguyen diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index b57fd4c..3a4df63 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ -#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ +#ifndef __CONFIG_SOCFPGA_COMMON_H__ +#define __CONFIG_SOCFPGA_COMMON_H__ /* Virtual target or real hardware */ @@ -323,4 +323,4 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ +#endif /* __CONFIG_SOCFPGA_COMMON_H__ */ -- cgit v0.10.2